From d387eec38a23416bf7c93b0e09983f6bbbd848d8 Mon Sep 17 00:00:00 2001 From: rollman054 Date: Fri, 17 Aug 2018 19:28:25 +0900 Subject: [PATCH] add files which are useful as references --- .../50c2fa8fed532918/50c2fa8fed532918.xci | 917 + .../design_1_processing_system7_0_0.dcp | Bin 0 -> 216957 bytes ...ign_1_processing_system7_0_0_sim_netlist.v | 5171 ++ .../design_1_processing_system7_0_0_stub.v | 164 + .../ip/2018.2/50c2fa8fed532918/stats.txt | 4 + LED_Blink/LED_Blink.cache/wt/webtalk_pa.xml | 122 + .../LED_Blink.runs/.jobs/vrs_config_1.xml | 8 + .../LED_Blink.runs/.jobs/vrs_config_10.xml | 8 + .../LED_Blink.runs/.jobs/vrs_config_11.xml | 15 + .../LED_Blink.runs/.jobs/vrs_config_12.xml | 8 + .../LED_Blink.runs/.jobs/vrs_config_13.xml | 12 + .../LED_Blink.runs/.jobs/vrs_config_2.xml | 8 + .../LED_Blink.runs/.jobs/vrs_config_3.xml | 5 + .../LED_Blink.runs/.jobs/vrs_config_4.xml | 8 + .../LED_Blink.runs/.jobs/vrs_config_5.xml | 8 + .../LED_Blink.runs/.jobs/vrs_config_6.xml | 8 + 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mode 100644 index 0000000..f18fb50 --- /dev/null +++ b/LED_Blink/LED_Blink.cache/ip/2018.2/50c2fa8fed532918/design_1_processing_system7_0_0_sim_netlist.v @@ -0,0 +1,5171 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Fri Aug 17 17:36:45 2018 +// Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_sim_netlist.v +// Design : design_1_processing_system7_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg225-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_TX, + UART0_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + IRQ_F2P, + FCLK_CLK0, + FCLK_CLK1, + FCLK_RESET0_N, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB); + (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *) input [63:0]GPIO_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *) output [63:0]GPIO_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *) output [63:0]GPIO_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) input I2C0_SDA_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) output I2C0_SDA_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) output I2C0_SDA_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) input I2C0_SCL_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) output I2C0_SCL_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output I2C0_SCL_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CLK" *) output SDIO0_CLK; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CLK_FB" *) input SDIO0_CLK_FB; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_O" *) output SDIO0_CMD_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_I" *) input SDIO0_CMD_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_T" *) output SDIO0_CMD_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_I" *) input [3:0]SDIO0_DATA_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_O" *) output [3:0]SDIO0_DATA_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_T" *) output [3:0]SDIO0_DATA_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 LED" *) output SDIO0_LED; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CDN" *) input SDIO0_CDN; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) input SDIO0_WP; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 BUSPOW" *) output SDIO0_BUSPOW; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 BUSVOLT" *) output [2:0]SDIO0_BUSVOLT; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_I" *) input SPI0_SCLK_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_O" *) output SPI0_SCLK_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_T" *) output SPI0_SCLK_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_I" *) input SPI0_MOSI_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_O" *) output SPI0_MOSI_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_T" *) output SPI0_MOSI_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_I" *) input SPI0_MISO_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_O" *) output SPI0_MISO_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_T" *) output SPI0_MISO_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_I" *) input SPI0_SS_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_O" *) output SPI0_SS_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS1_O" *) output SPI0_SS1_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS2_O" *) output SPI0_SS2_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_T" *) output SPI0_SS_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *) input SPI1_SCLK_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *) output SPI1_SCLK_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *) output SPI1_SCLK_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *) input SPI1_MOSI_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *) output SPI1_MOSI_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *) output SPI1_MOSI_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *) input SPI1_MISO_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *) output SPI1_MISO_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *) output SPI1_MISO_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *) input SPI1_SS_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *) output SPI1_SS_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *) output SPI1_SS1_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *) output SPI1_SS2_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *) output SPI1_SS_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 UART_0 TxD" *) output UART0_TX; + (* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 UART_0 RxD" *) input UART0_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) input M_AXI_GP0_ACLK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA; + (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) output FCLK_CLK0; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK1" *) output FCLK_CLK1; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [31:0]MIO; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [1:0]DDR_DM; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [15:0]DDR_DQ; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [1:0]DDR_DQS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [1:0]DDR_DQS; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB; + + wire [14:0]DDR_Addr; + wire [2:0]DDR_BankAddr; + wire DDR_CAS_n; + wire DDR_CKE; + wire DDR_CS_n; + wire DDR_Clk; + wire DDR_Clk_n; + wire [1:0]DDR_DM; + wire [15:0]DDR_DQ; + wire [1:0]DDR_DQS; + wire [1:0]DDR_DQS_n; + wire DDR_DRSTB; + wire DDR_ODT; + wire DDR_RAS_n; + wire DDR_VRN; + wire DDR_VRP; + wire DDR_WEB; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_RESET0_N; + wire [63:0]GPIO_I; + wire [63:0]GPIO_O; + wire [63:0]GPIO_T; + wire I2C0_SCL_I; + wire I2C0_SCL_O; + wire I2C0_SCL_T; + wire I2C0_SDA_I; + wire I2C0_SDA_O; + wire I2C0_SDA_T; + wire [0:0]IRQ_F2P; + wire [31:0]MIO; + wire M_AXI_GP0_ACLK; + wire [31:0]M_AXI_GP0_ARADDR; + wire [1:0]M_AXI_GP0_ARBURST; + wire [3:0]M_AXI_GP0_ARCACHE; + wire [11:0]M_AXI_GP0_ARID; + wire [3:0]M_AXI_GP0_ARLEN; + wire [1:0]M_AXI_GP0_ARLOCK; + wire [2:0]M_AXI_GP0_ARPROT; + wire [3:0]M_AXI_GP0_ARQOS; + wire M_AXI_GP0_ARREADY; + wire [2:0]M_AXI_GP0_ARSIZE; + wire M_AXI_GP0_ARVALID; + wire [31:0]M_AXI_GP0_AWADDR; + wire [1:0]M_AXI_GP0_AWBURST; + wire [3:0]M_AXI_GP0_AWCACHE; + wire [11:0]M_AXI_GP0_AWID; + wire [3:0]M_AXI_GP0_AWLEN; + wire [1:0]M_AXI_GP0_AWLOCK; + wire [2:0]M_AXI_GP0_AWPROT; + wire [3:0]M_AXI_GP0_AWQOS; + wire M_AXI_GP0_AWREADY; + wire [2:0]M_AXI_GP0_AWSIZE; + wire M_AXI_GP0_AWVALID; + wire [11:0]M_AXI_GP0_BID; + wire M_AXI_GP0_BREADY; + wire [1:0]M_AXI_GP0_BRESP; + wire M_AXI_GP0_BVALID; + wire [31:0]M_AXI_GP0_RDATA; + wire [11:0]M_AXI_GP0_RID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RREADY; + wire [1:0]M_AXI_GP0_RRESP; + wire M_AXI_GP0_RVALID; + wire [31:0]M_AXI_GP0_WDATA; + wire [11:0]M_AXI_GP0_WID; + wire M_AXI_GP0_WLAST; + wire M_AXI_GP0_WREADY; + wire [3:0]M_AXI_GP0_WSTRB; + wire M_AXI_GP0_WVALID; + wire PS_CLK; + wire PS_PORB; + wire PS_SRSTB; + wire SDIO0_BUSPOW; + wire [2:0]SDIO0_BUSVOLT; + wire SDIO0_CDN; + wire SDIO0_CLK; + wire SDIO0_CLK_FB; + wire SDIO0_CMD_I; + wire SDIO0_CMD_O; + wire SDIO0_CMD_T; + wire [3:0]SDIO0_DATA_I; + wire [3:0]SDIO0_DATA_O; + wire [3:0]SDIO0_DATA_T; + wire SDIO0_LED; + wire SDIO0_WP; + wire SPI0_MISO_I; + wire SPI0_MISO_O; + wire SPI0_MISO_T; + wire SPI0_MOSI_I; + wire SPI0_MOSI_O; + wire SPI0_MOSI_T; + wire SPI0_SCLK_I; + wire SPI0_SCLK_O; + wire SPI0_SCLK_T; + wire SPI0_SS1_O; + wire SPI0_SS2_O; + wire SPI0_SS_I; + wire SPI0_SS_O; + wire SPI0_SS_T; + wire SPI1_MISO_I; + wire SPI1_MISO_O; + wire SPI1_MISO_T; + wire SPI1_MOSI_I; + wire SPI1_MOSI_O; + wire SPI1_MOSI_T; + wire SPI1_SCLK_I; + wire SPI1_SCLK_O; + wire SPI1_SCLK_T; + wire SPI1_SS1_O; + wire SPI1_SS2_O; + wire SPI1_SS_I; + wire SPI1_SS_O; + wire SPI1_SS_T; + wire TTC0_WAVE0_OUT; + wire TTC0_WAVE1_OUT; + wire TTC0_WAVE2_OUT; + wire TTC1_WAVE0_OUT; + wire TTC1_WAVE1_OUT; + wire TTC1_WAVE2_OUT; + wire UART0_RX; + wire UART0_TX; + wire [1:0]USB0_PORT_INDCTL; + wire USB0_VBUS_PWRFAULT; + wire USB0_VBUS_PWRSELECT; + wire NLW_inst_CAN0_PHY_TX_UNCONNECTED; + wire NLW_inst_CAN1_PHY_TX_UNCONNECTED; + wire NLW_inst_DMA0_DAVALID_UNCONNECTED; + wire NLW_inst_DMA0_DRREADY_UNCONNECTED; + wire NLW_inst_DMA0_RSTN_UNCONNECTED; + wire NLW_inst_DMA1_DAVALID_UNCONNECTED; + wire NLW_inst_DMA1_DRREADY_UNCONNECTED; + wire NLW_inst_DMA1_RSTN_UNCONNECTED; + wire NLW_inst_DMA2_DAVALID_UNCONNECTED; + wire NLW_inst_DMA2_DRREADY_UNCONNECTED; + wire NLW_inst_DMA2_RSTN_UNCONNECTED; + wire NLW_inst_DMA3_DAVALID_UNCONNECTED; + wire NLW_inst_DMA3_DRREADY_UNCONNECTED; + wire NLW_inst_DMA3_RSTN_UNCONNECTED; + wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED; + wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_O_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_T_UNCONNECTED; + wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED; + wire NLW_inst_ENET0_SOF_RX_UNCONNECTED; + wire NLW_inst_ENET0_SOF_TX_UNCONNECTED; + wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED; + wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_O_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_T_UNCONNECTED; + wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED; + wire NLW_inst_ENET1_SOF_RX_UNCONNECTED; + wire NLW_inst_ENET1_SOF_TX_UNCONNECTED; + wire NLW_inst_EVENT_EVENTO_UNCONNECTED; + wire NLW_inst_FCLK_CLK2_UNCONNECTED; + wire NLW_inst_FCLK_CLK3_UNCONNECTED; + wire NLW_inst_FCLK_RESET1_N_UNCONNECTED; + wire NLW_inst_FCLK_RESET2_N_UNCONNECTED; + wire NLW_inst_FCLK_RESET3_N_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED; + wire NLW_inst_I2C1_SCL_O_UNCONNECTED; + wire NLW_inst_I2C1_SCL_T_UNCONNECTED; + wire NLW_inst_I2C1_SDA_O_UNCONNECTED; + wire NLW_inst_I2C1_SDA_T_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED; + wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED; + wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED; + wire NLW_inst_PJTAG_TDO_UNCONNECTED; + wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED; + wire NLW_inst_SDIO1_CLK_UNCONNECTED; + wire NLW_inst_SDIO1_CMD_O_UNCONNECTED; + wire NLW_inst_SDIO1_CMD_T_UNCONNECTED; + wire NLW_inst_SDIO1_LED_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED; + wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED; + wire NLW_inst_TRACE_CTL_UNCONNECTED; + wire NLW_inst_UART0_DTRN_UNCONNECTED; + wire NLW_inst_UART0_RTSN_UNCONNECTED; + wire NLW_inst_UART1_DTRN_UNCONNECTED; + wire NLW_inst_UART1_RTSN_UNCONNECTED; + wire NLW_inst_UART1_TX_UNCONNECTED; + wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED; + wire NLW_inst_WDT_RST_OUT_UNCONNECTED; + wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED; + wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED; + wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED; + wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED; + wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED; + wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED; + wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED; + wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED; + wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED; + wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED; + wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED; + wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED; + wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED; + + (* C_DM_WIDTH = "2" *) + (* C_DQS_WIDTH = "2" *) + (* C_DQ_WIDTH = "16" *) + (* C_EMIO_GPIO_WIDTH = "64" *) + (* C_EN_EMIO_ENET0 = "0" *) + (* C_EN_EMIO_ENET1 = "0" *) + (* C_EN_EMIO_PJTAG = "0" *) + (* C_EN_EMIO_TRACE = "0" *) + (* C_FCLK_CLK0_BUF = "TRUE" *) + (* C_FCLK_CLK1_BUF = "TRUE" *) + (* C_FCLK_CLK2_BUF = "FALSE" *) + (* C_FCLK_CLK3_BUF = "FALSE" *) + (* C_GP0_EN_MODIFIABLE_TXN = "1" *) + (* C_GP1_EN_MODIFIABLE_TXN = "1" *) + (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) + (* C_INCLUDE_TRACE_BUFFER = "0" *) + (* C_IRQ_F2P_MODE = "DIRECT" *) + (* C_MIO_PRIMITIVE = "32" *) + (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) + (* C_M_AXI_GP0_ID_WIDTH = "12" *) + (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) + (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) + (* C_M_AXI_GP1_ID_WIDTH = "12" *) + (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) + (* C_NUM_F2P_INTR_INPUTS = "1" *) + (* C_PACKAGE_NAME = "clg225" *) + (* C_PS7_SI_REV = "PRODUCTION" *) + (* C_S_AXI_ACP_ARUSER_VAL = "31" *) + (* C_S_AXI_ACP_AWUSER_VAL = "31" *) + (* C_S_AXI_ACP_ID_WIDTH = "3" *) + (* C_S_AXI_GP0_ID_WIDTH = "6" *) + (* C_S_AXI_GP1_ID_WIDTH = "6" *) + (* C_S_AXI_HP0_DATA_WIDTH = "64" *) + (* C_S_AXI_HP0_ID_WIDTH = "6" *) + (* C_S_AXI_HP1_DATA_WIDTH = "64" *) + (* C_S_AXI_HP1_ID_WIDTH = "6" *) + (* C_S_AXI_HP2_DATA_WIDTH = "64" *) + (* C_S_AXI_HP2_ID_WIDTH = "6" *) + (* C_S_AXI_HP3_DATA_WIDTH = "64" *) + (* C_S_AXI_HP3_ID_WIDTH = "6" *) + (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) + (* C_TRACE_BUFFER_FIFO_SIZE = "128" *) + (* C_TRACE_INTERNAL_WIDTH = "2" *) + (* C_TRACE_PIPELINE_WIDTH = "8" *) + (* C_USE_AXI_NONSECURE = "0" *) + (* C_USE_DEFAULT_ACP_USER_VAL = "0" *) + (* C_USE_M_AXI_GP0 = "1" *) + (* C_USE_M_AXI_GP1 = "0" *) + (* C_USE_S_AXI_ACP = "0" *) + (* C_USE_S_AXI_GP0 = "0" *) + (* C_USE_S_AXI_GP1 = "0" *) + (* C_USE_S_AXI_HP0 = "0" *) + (* C_USE_S_AXI_HP1 = "0" *) + (* C_USE_S_AXI_HP2 = "0" *) + (* C_USE_S_AXI_HP3 = "0" *) + (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) + (* POWER = "/>" *) + (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst + (.CAN0_PHY_RX(1'b0), + .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED), + .CAN1_PHY_RX(1'b0), + .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED), + .Core0_nFIQ(1'b0), + .Core0_nIRQ(1'b0), + .Core1_nFIQ(1'b0), + .Core1_nIRQ(1'b0), + .DDR_ARB({1'b0,1'b0,1'b0,1'b0}), + .DDR_Addr(DDR_Addr), + .DDR_BankAddr(DDR_BankAddr), + .DDR_CAS_n(DDR_CAS_n), + .DDR_CKE(DDR_CKE), + .DDR_CS_n(DDR_CS_n), + .DDR_Clk(DDR_Clk), + .DDR_Clk_n(DDR_Clk_n), + .DDR_DM(DDR_DM), + .DDR_DQ(DDR_DQ), + .DDR_DQS(DDR_DQS), + .DDR_DQS_n(DDR_DQS_n), + .DDR_DRSTB(DDR_DRSTB), + .DDR_ODT(DDR_ODT), + .DDR_RAS_n(DDR_RAS_n), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_WEB(DDR_WEB), + .DMA0_ACLK(1'b0), + .DMA0_DAREADY(1'b0), + .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]), + .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED), + .DMA0_DRLAST(1'b0), + .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED), + .DMA0_DRTYPE({1'b0,1'b0}), + .DMA0_DRVALID(1'b0), + .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED), + .DMA1_ACLK(1'b0), + .DMA1_DAREADY(1'b0), + .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]), + .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED), + .DMA1_DRLAST(1'b0), + .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED), + .DMA1_DRTYPE({1'b0,1'b0}), + .DMA1_DRVALID(1'b0), + .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED), + .DMA2_ACLK(1'b0), + .DMA2_DAREADY(1'b0), + .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]), + .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED), + .DMA2_DRLAST(1'b0), + .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED), + .DMA2_DRTYPE({1'b0,1'b0}), + .DMA2_DRVALID(1'b0), + .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED), + .DMA3_ACLK(1'b0), + .DMA3_DAREADY(1'b0), + .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]), + .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED), + .DMA3_DRLAST(1'b0), + .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED), + .DMA3_DRTYPE({1'b0,1'b0}), + .DMA3_DRVALID(1'b0), + .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED), + .ENET0_EXT_INTIN(1'b0), + .ENET0_GMII_COL(1'b0), + .ENET0_GMII_CRS(1'b0), + .ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ENET0_GMII_RX_CLK(1'b0), + .ENET0_GMII_RX_DV(1'b0), + .ENET0_GMII_RX_ER(1'b0), + .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]), + .ENET0_GMII_TX_CLK(1'b0), + .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED), + .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED), + .ENET0_MDIO_I(1'b0), + .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED), + .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED), + .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED), + .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED), + .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED), + .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED), + .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED), + .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED), + .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED), + .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED), + .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED), + .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED), + .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED), + .ENET1_EXT_INTIN(1'b0), + .ENET1_GMII_COL(1'b0), + .ENET1_GMII_CRS(1'b0), + .ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ENET1_GMII_RX_CLK(1'b0), + .ENET1_GMII_RX_DV(1'b0), + .ENET1_GMII_RX_ER(1'b0), + .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]), + .ENET1_GMII_TX_CLK(1'b0), + .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED), + .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED), + .ENET1_MDIO_I(1'b0), + .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED), + .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED), + .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED), + .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED), + .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED), + .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED), + .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED), + .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED), + .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED), + .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED), + .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED), + .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED), + .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED), + .EVENT_EVENTI(1'b0), + .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED), + .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]), + .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]), + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED), + .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED), + .FCLK_CLKTRIG0_N(1'b0), + .FCLK_CLKTRIG1_N(1'b0), + .FCLK_CLKTRIG2_N(1'b0), + .FCLK_CLKTRIG3_N(1'b0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED), + .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED), + .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED), + .FPGA_IDLE_N(1'b0), + .FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}), + .FTMD_TRACEIN_CLK(1'b0), + .FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMD_TRACEIN_VALID(1'b0), + .FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED), + .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED), + .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED), + .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED), + .FTMT_F2P_TRIG_0(1'b0), + .FTMT_F2P_TRIG_1(1'b0), + .FTMT_F2P_TRIG_2(1'b0), + .FTMT_F2P_TRIG_3(1'b0), + .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]), + .FTMT_P2F_TRIGACK_0(1'b0), + .FTMT_P2F_TRIGACK_1(1'b0), + .FTMT_P2F_TRIGACK_2(1'b0), + .FTMT_P2F_TRIGACK_3(1'b0), + .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED), + .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED), + .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED), + .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED), + .GPIO_I(GPIO_I), + .GPIO_O(GPIO_O), + .GPIO_T(GPIO_T), + .I2C0_SCL_I(I2C0_SCL_I), + .I2C0_SCL_O(I2C0_SCL_O), + .I2C0_SCL_T(I2C0_SCL_T), + .I2C0_SDA_I(I2C0_SDA_I), + .I2C0_SDA_O(I2C0_SDA_O), + .I2C0_SDA_T(I2C0_SDA_T), + .I2C1_SCL_I(1'b0), + .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED), + .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED), + .I2C1_SDA_I(1'b0), + .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED), + .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED), + .IRQ_F2P(IRQ_F2P), + .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED), + .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED), + .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED), + .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED), + .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED), + .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED), + .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED), + .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED), + .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED), + .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED), + .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED), + .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED), + .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED), + .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED), + .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED), + .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED), + .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED), + .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED), + .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED), + .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED), + .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED), + .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED), + .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED), + .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED), + .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED), + .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED), + .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED), + .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED), + .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED), + .MIO(MIO), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP1_ACLK(1'b0), + .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]), + .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]), + .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]), + .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED), + .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]), + .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]), + .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]), + .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]), + .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]), + .M_AXI_GP1_ARREADY(1'b0), + .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]), + .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED), + .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]), + .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]), + .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]), + .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]), + .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]), + .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]), + .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]), + .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]), + .M_AXI_GP1_AWREADY(1'b0), + .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]), + .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED), + .M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED), + .M_AXI_GP1_BRESP({1'b0,1'b0}), + .M_AXI_GP1_BVALID(1'b0), + .M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_RLAST(1'b0), + .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED), + .M_AXI_GP1_RRESP({1'b0,1'b0}), + .M_AXI_GP1_RVALID(1'b0), + .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]), + .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]), + .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED), + .M_AXI_GP1_WREADY(1'b0), + .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]), + .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED), + .PJTAG_TCK(1'b0), + .PJTAG_TDI(1'b0), + .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED), + .PJTAG_TMS(1'b0), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB), + .PS_SRSTB(PS_SRSTB), + .SDIO0_BUSPOW(SDIO0_BUSPOW), + .SDIO0_BUSVOLT(SDIO0_BUSVOLT), + .SDIO0_CDN(SDIO0_CDN), + .SDIO0_CLK(SDIO0_CLK), + .SDIO0_CLK_FB(SDIO0_CLK_FB), + .SDIO0_CMD_I(SDIO0_CMD_I), + .SDIO0_CMD_O(SDIO0_CMD_O), + .SDIO0_CMD_T(SDIO0_CMD_T), + .SDIO0_DATA_I(SDIO0_DATA_I), + .SDIO0_DATA_O(SDIO0_DATA_O), + .SDIO0_DATA_T(SDIO0_DATA_T), + .SDIO0_LED(SDIO0_LED), + .SDIO0_WP(SDIO0_WP), + .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED), + .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]), + .SDIO1_CDN(1'b0), + .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED), + .SDIO1_CLK_FB(1'b0), + .SDIO1_CMD_I(1'b0), + .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED), + .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED), + .SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}), + .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]), + .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]), + .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED), + .SDIO1_WP(1'b0), + .SPI0_MISO_I(SPI0_MISO_I), + .SPI0_MISO_O(SPI0_MISO_O), + .SPI0_MISO_T(SPI0_MISO_T), + .SPI0_MOSI_I(SPI0_MOSI_I), + .SPI0_MOSI_O(SPI0_MOSI_O), + .SPI0_MOSI_T(SPI0_MOSI_T), + .SPI0_SCLK_I(SPI0_SCLK_I), + .SPI0_SCLK_O(SPI0_SCLK_O), + .SPI0_SCLK_T(SPI0_SCLK_T), + .SPI0_SS1_O(SPI0_SS1_O), + .SPI0_SS2_O(SPI0_SS2_O), + .SPI0_SS_I(SPI0_SS_I), + .SPI0_SS_O(SPI0_SS_O), + .SPI0_SS_T(SPI0_SS_T), + .SPI1_MISO_I(SPI1_MISO_I), + .SPI1_MISO_O(SPI1_MISO_O), + .SPI1_MISO_T(SPI1_MISO_T), + .SPI1_MOSI_I(SPI1_MOSI_I), + .SPI1_MOSI_O(SPI1_MOSI_O), + .SPI1_MOSI_T(SPI1_MOSI_T), + .SPI1_SCLK_I(SPI1_SCLK_I), + .SPI1_SCLK_O(SPI1_SCLK_O), + .SPI1_SCLK_T(SPI1_SCLK_T), + .SPI1_SS1_O(SPI1_SS1_O), + .SPI1_SS2_O(SPI1_SS2_O), + .SPI1_SS_I(SPI1_SS_I), + .SPI1_SS_O(SPI1_SS_O), + .SPI1_SS_T(SPI1_SS_T), + .SRAM_INTIN(1'b0), + .S_AXI_ACP_ACLK(1'b0), + .S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARBURST({1'b0,1'b0}), + .S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED), + .S_AXI_ACP_ARID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARLOCK({1'b0,1'b0}), + .S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED), + .S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARVALID(1'b0), + .S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWBURST({1'b0,1'b0}), + .S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWLOCK({1'b0,1'b0}), + .S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED), + .S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWVALID(1'b0), + .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]), + .S_AXI_ACP_BREADY(1'b0), + .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]), + .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED), + .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]), + .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]), + .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED), + .S_AXI_ACP_RREADY(1'b0), + .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]), + .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED), + .S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_WID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_WLAST(1'b0), + .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED), + .S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_WVALID(1'b0), + .S_AXI_GP0_ACLK(1'b0), + .S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARBURST({1'b0,1'b0}), + .S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED), + .S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARLOCK({1'b0,1'b0}), + .S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED), + .S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARVALID(1'b0), + .S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWBURST({1'b0,1'b0}), + .S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWLOCK({1'b0,1'b0}), + .S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED), + .S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWVALID(1'b0), + .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]), + .S_AXI_GP0_BREADY(1'b0), + .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]), + .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED), + .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]), + .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]), + .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED), + .S_AXI_GP0_RREADY(1'b0), + .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]), + .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED), + .S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WLAST(1'b0), + .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED), + .S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WVALID(1'b0), + .S_AXI_GP1_ACLK(1'b0), + .S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARBURST({1'b0,1'b0}), + .S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED), + .S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARLOCK({1'b0,1'b0}), + .S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED), + .S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARVALID(1'b0), + .S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWBURST({1'b0,1'b0}), + .S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWLOCK({1'b0,1'b0}), + .S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED), + .S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWVALID(1'b0), + .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]), + .S_AXI_GP1_BREADY(1'b0), + .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]), + .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED), + .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]), + .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]), + .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED), + .S_AXI_GP1_RREADY(1'b0), + .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]), + .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED), + .S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WLAST(1'b0), + .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED), + .S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WVALID(1'b0), + .S_AXI_HP0_ACLK(1'b0), + .S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARBURST({1'b0,1'b0}), + .S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED), + .S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARLOCK({1'b0,1'b0}), + .S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED), + .S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARVALID(1'b0), + .S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWBURST({1'b0,1'b0}), + .S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWLOCK({1'b0,1'b0}), + .S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED), + .S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWVALID(1'b0), + .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]), + .S_AXI_HP0_BREADY(1'b0), + .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED), + .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP0_RDISSUECAP1_EN(1'b0), + .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]), + .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED), + .S_AXI_HP0_RREADY(1'b0), + .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED), + .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WLAST(1'b0), + .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED), + .S_AXI_HP0_WRISSUECAP1_EN(1'b0), + .S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WVALID(1'b0), + .S_AXI_HP1_ACLK(1'b0), + .S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARBURST({1'b0,1'b0}), + .S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED), + .S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARLOCK({1'b0,1'b0}), + .S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED), + .S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARVALID(1'b0), + .S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWBURST({1'b0,1'b0}), + .S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWLOCK({1'b0,1'b0}), + .S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED), + .S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWVALID(1'b0), + .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]), + .S_AXI_HP1_BREADY(1'b0), + .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED), + .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP1_RDISSUECAP1_EN(1'b0), + .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]), + .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED), + .S_AXI_HP1_RREADY(1'b0), + .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED), + .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WLAST(1'b0), + .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED), + .S_AXI_HP1_WRISSUECAP1_EN(1'b0), + .S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WVALID(1'b0), + .S_AXI_HP2_ACLK(1'b0), + .S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARBURST({1'b0,1'b0}), + .S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED), + .S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARLOCK({1'b0,1'b0}), + .S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED), + .S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARVALID(1'b0), + .S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWBURST({1'b0,1'b0}), + .S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWLOCK({1'b0,1'b0}), + .S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED), + .S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWVALID(1'b0), + .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]), + .S_AXI_HP2_BREADY(1'b0), + .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED), + .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP2_RDISSUECAP1_EN(1'b0), + .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]), + .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED), + .S_AXI_HP2_RREADY(1'b0), + .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED), + .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WLAST(1'b0), + .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED), + .S_AXI_HP2_WRISSUECAP1_EN(1'b0), + .S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WVALID(1'b0), + .S_AXI_HP3_ACLK(1'b0), + .S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARBURST({1'b0,1'b0}), + .S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED), + .S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARLOCK({1'b0,1'b0}), + .S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED), + .S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARVALID(1'b0), + .S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWBURST({1'b0,1'b0}), + .S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWLOCK({1'b0,1'b0}), + .S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED), + .S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWVALID(1'b0), + .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]), + .S_AXI_HP3_BREADY(1'b0), + .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED), + .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP3_RDISSUECAP1_EN(1'b0), + .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]), + .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED), + .S_AXI_HP3_RREADY(1'b0), + .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED), + .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WLAST(1'b0), + .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED), + .S_AXI_HP3_WRISSUECAP1_EN(1'b0), + .S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WVALID(1'b0), + .TRACE_CLK(1'b0), + .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED), + .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED), + .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]), + .TTC0_CLK0_IN(1'b0), + .TTC0_CLK1_IN(1'b0), + .TTC0_CLK2_IN(1'b0), + .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT), + .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT), + .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT), + .TTC1_CLK0_IN(1'b0), + .TTC1_CLK1_IN(1'b0), + .TTC1_CLK2_IN(1'b0), + .TTC1_WAVE0_OUT(TTC1_WAVE0_OUT), + .TTC1_WAVE1_OUT(TTC1_WAVE1_OUT), + .TTC1_WAVE2_OUT(TTC1_WAVE2_OUT), + .UART0_CTSN(1'b0), + .UART0_DCDN(1'b0), + .UART0_DSRN(1'b0), + .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED), + .UART0_RIN(1'b0), + .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED), + .UART0_RX(UART0_RX), + .UART0_TX(UART0_TX), + .UART1_CTSN(1'b0), + .UART1_DCDN(1'b0), + .UART1_DSRN(1'b0), + .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED), + .UART1_RIN(1'b0), + .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED), + .UART1_RX(1'b1), + .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED), + .USB0_PORT_INDCTL(USB0_PORT_INDCTL), + .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), + .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), + .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]), + .USB1_VBUS_PWRFAULT(1'b0), + .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED), + .WDT_CLK_IN(1'b0), + .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED)); +endmodule + +(* C_DM_WIDTH = "2" *) (* C_DQS_WIDTH = "2" *) (* C_DQ_WIDTH = "16" *) +(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *) +(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *) +(* C_FCLK_CLK1_BUF = "TRUE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *) +(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) +(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "32" *) +(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) +(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) +(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg225" *) (* C_PS7_SI_REV = "PRODUCTION" *) +(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *) +(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *) +(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *) +(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *) +(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *) +(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *) +(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *) +(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *) +(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *) +(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* POWER = "/>" *) +(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 + (CAN0_PHY_TX, + CAN0_PHY_RX, + CAN1_PHY_TX, + CAN1_PHY_RX, + ENET0_GMII_TX_EN, + ENET0_GMII_TX_ER, + ENET0_MDIO_MDC, + ENET0_MDIO_O, + ENET0_MDIO_T, + ENET0_PTP_DELAY_REQ_RX, + ENET0_PTP_DELAY_REQ_TX, + ENET0_PTP_PDELAY_REQ_RX, + ENET0_PTP_PDELAY_REQ_TX, + ENET0_PTP_PDELAY_RESP_RX, + ENET0_PTP_PDELAY_RESP_TX, + ENET0_PTP_SYNC_FRAME_RX, + ENET0_PTP_SYNC_FRAME_TX, + ENET0_SOF_RX, + ENET0_SOF_TX, + ENET0_GMII_TXD, + ENET0_GMII_COL, + ENET0_GMII_CRS, + ENET0_GMII_RX_CLK, + ENET0_GMII_RX_DV, + ENET0_GMII_RX_ER, + ENET0_GMII_TX_CLK, + ENET0_MDIO_I, + ENET0_EXT_INTIN, + ENET0_GMII_RXD, + ENET1_GMII_TX_EN, + ENET1_GMII_TX_ER, + ENET1_MDIO_MDC, + ENET1_MDIO_O, + ENET1_MDIO_T, + ENET1_PTP_DELAY_REQ_RX, + ENET1_PTP_DELAY_REQ_TX, + ENET1_PTP_PDELAY_REQ_RX, + ENET1_PTP_PDELAY_REQ_TX, + ENET1_PTP_PDELAY_RESP_RX, + ENET1_PTP_PDELAY_RESP_TX, + ENET1_PTP_SYNC_FRAME_RX, + ENET1_PTP_SYNC_FRAME_TX, + ENET1_SOF_RX, + ENET1_SOF_TX, + ENET1_GMII_TXD, + ENET1_GMII_COL, + ENET1_GMII_CRS, + ENET1_GMII_RX_CLK, + ENET1_GMII_RX_DV, + ENET1_GMII_RX_ER, + ENET1_GMII_TX_CLK, + ENET1_MDIO_I, + ENET1_EXT_INTIN, + ENET1_GMII_RXD, + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + I2C1_SDA_I, + I2C1_SDA_O, + I2C1_SDA_T, + I2C1_SCL_I, + I2C1_SCL_O, + I2C1_SCL_T, + PJTAG_TCK, + PJTAG_TMS, + PJTAG_TDI, + PJTAG_TDO, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SDIO1_CLK, + SDIO1_CLK_FB, + SDIO1_CMD_O, + SDIO1_CMD_I, + SDIO1_CMD_T, + SDIO1_DATA_I, + SDIO1_DATA_O, + SDIO1_DATA_T, + SDIO1_LED, + SDIO1_CDN, + SDIO1_WP, + SDIO1_BUSPOW, + SDIO1_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_DTRN, + UART0_RTSN, + UART0_TX, + UART0_CTSN, + UART0_DCDN, + UART0_DSRN, + UART0_RIN, + UART0_RX, + UART1_DTRN, + UART1_RTSN, + UART1_TX, + UART1_CTSN, + UART1_DCDN, + UART1_DSRN, + UART1_RIN, + UART1_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC0_CLK0_IN, + TTC0_CLK1_IN, + TTC0_CLK2_IN, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + TTC1_CLK0_IN, + TTC1_CLK1_IN, + TTC1_CLK2_IN, + WDT_CLK_IN, + WDT_RST_OUT, + TRACE_CLK, + TRACE_CTL, + TRACE_DATA, + TRACE_CLK_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + USB1_PORT_INDCTL, + USB1_VBUS_PWRSELECT, + USB1_VBUS_PWRFAULT, + SRAM_INTIN, + M_AXI_GP0_ARESETN, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + M_AXI_GP1_ARESETN, + M_AXI_GP1_ARVALID, + M_AXI_GP1_AWVALID, + M_AXI_GP1_BREADY, + M_AXI_GP1_RREADY, + M_AXI_GP1_WLAST, + M_AXI_GP1_WVALID, + M_AXI_GP1_ARID, + M_AXI_GP1_AWID, + M_AXI_GP1_WID, + M_AXI_GP1_ARBURST, + M_AXI_GP1_ARLOCK, + M_AXI_GP1_ARSIZE, + M_AXI_GP1_AWBURST, + M_AXI_GP1_AWLOCK, + M_AXI_GP1_AWSIZE, + M_AXI_GP1_ARPROT, + M_AXI_GP1_AWPROT, + M_AXI_GP1_ARADDR, + M_AXI_GP1_AWADDR, + M_AXI_GP1_WDATA, + M_AXI_GP1_ARCACHE, + M_AXI_GP1_ARLEN, + M_AXI_GP1_ARQOS, + M_AXI_GP1_AWCACHE, + M_AXI_GP1_AWLEN, + M_AXI_GP1_AWQOS, + M_AXI_GP1_WSTRB, + M_AXI_GP1_ACLK, + M_AXI_GP1_ARREADY, + M_AXI_GP1_AWREADY, + M_AXI_GP1_BVALID, + M_AXI_GP1_RLAST, + M_AXI_GP1_RVALID, + M_AXI_GP1_WREADY, + M_AXI_GP1_BID, + M_AXI_GP1_RID, + M_AXI_GP1_BRESP, + M_AXI_GP1_RRESP, + M_AXI_GP1_RDATA, + S_AXI_GP0_ARESETN, + S_AXI_GP0_ARREADY, + S_AXI_GP0_AWREADY, + S_AXI_GP0_BVALID, + S_AXI_GP0_RLAST, + S_AXI_GP0_RVALID, + S_AXI_GP0_WREADY, + S_AXI_GP0_BRESP, + S_AXI_GP0_RRESP, + S_AXI_GP0_RDATA, + S_AXI_GP0_BID, + S_AXI_GP0_RID, + S_AXI_GP0_ACLK, + S_AXI_GP0_ARVALID, + S_AXI_GP0_AWVALID, + S_AXI_GP0_BREADY, + S_AXI_GP0_RREADY, + S_AXI_GP0_WLAST, + S_AXI_GP0_WVALID, + S_AXI_GP0_ARBURST, + S_AXI_GP0_ARLOCK, + S_AXI_GP0_ARSIZE, + S_AXI_GP0_AWBURST, + S_AXI_GP0_AWLOCK, + S_AXI_GP0_AWSIZE, + S_AXI_GP0_ARPROT, + S_AXI_GP0_AWPROT, + S_AXI_GP0_ARADDR, + S_AXI_GP0_AWADDR, + S_AXI_GP0_WDATA, + S_AXI_GP0_ARCACHE, + S_AXI_GP0_ARLEN, + S_AXI_GP0_ARQOS, + S_AXI_GP0_AWCACHE, + S_AXI_GP0_AWLEN, + S_AXI_GP0_AWQOS, + S_AXI_GP0_WSTRB, + S_AXI_GP0_ARID, + S_AXI_GP0_AWID, + S_AXI_GP0_WID, + S_AXI_GP1_ARESETN, + S_AXI_GP1_ARREADY, + S_AXI_GP1_AWREADY, + S_AXI_GP1_BVALID, + S_AXI_GP1_RLAST, + S_AXI_GP1_RVALID, + S_AXI_GP1_WREADY, + S_AXI_GP1_BRESP, + S_AXI_GP1_RRESP, + S_AXI_GP1_RDATA, + S_AXI_GP1_BID, + S_AXI_GP1_RID, + S_AXI_GP1_ACLK, + S_AXI_GP1_ARVALID, + S_AXI_GP1_AWVALID, + S_AXI_GP1_BREADY, + S_AXI_GP1_RREADY, + S_AXI_GP1_WLAST, + S_AXI_GP1_WVALID, + S_AXI_GP1_ARBURST, + S_AXI_GP1_ARLOCK, + S_AXI_GP1_ARSIZE, + S_AXI_GP1_AWBURST, + S_AXI_GP1_AWLOCK, + S_AXI_GP1_AWSIZE, + S_AXI_GP1_ARPROT, + S_AXI_GP1_AWPROT, + S_AXI_GP1_ARADDR, + S_AXI_GP1_AWADDR, + S_AXI_GP1_WDATA, + S_AXI_GP1_ARCACHE, + S_AXI_GP1_ARLEN, + S_AXI_GP1_ARQOS, + S_AXI_GP1_AWCACHE, + S_AXI_GP1_AWLEN, + S_AXI_GP1_AWQOS, + S_AXI_GP1_WSTRB, + S_AXI_GP1_ARID, + S_AXI_GP1_AWID, + S_AXI_GP1_WID, + S_AXI_ACP_ARESETN, + S_AXI_ACP_ARREADY, + S_AXI_ACP_AWREADY, + S_AXI_ACP_BVALID, + S_AXI_ACP_RLAST, + S_AXI_ACP_RVALID, + S_AXI_ACP_WREADY, + S_AXI_ACP_BRESP, + S_AXI_ACP_RRESP, + S_AXI_ACP_BID, + S_AXI_ACP_RID, + S_AXI_ACP_RDATA, + S_AXI_ACP_ACLK, + S_AXI_ACP_ARVALID, + S_AXI_ACP_AWVALID, + S_AXI_ACP_BREADY, + S_AXI_ACP_RREADY, + S_AXI_ACP_WLAST, + S_AXI_ACP_WVALID, + S_AXI_ACP_ARID, + S_AXI_ACP_ARPROT, + S_AXI_ACP_AWID, + S_AXI_ACP_AWPROT, + S_AXI_ACP_WID, + S_AXI_ACP_ARADDR, + S_AXI_ACP_AWADDR, + S_AXI_ACP_ARCACHE, + S_AXI_ACP_ARLEN, + S_AXI_ACP_ARQOS, + S_AXI_ACP_AWCACHE, + S_AXI_ACP_AWLEN, + S_AXI_ACP_AWQOS, + S_AXI_ACP_ARBURST, + S_AXI_ACP_ARLOCK, + S_AXI_ACP_ARSIZE, + S_AXI_ACP_AWBURST, + S_AXI_ACP_AWLOCK, + S_AXI_ACP_AWSIZE, + S_AXI_ACP_ARUSER, + S_AXI_ACP_AWUSER, + S_AXI_ACP_WDATA, + S_AXI_ACP_WSTRB, + S_AXI_HP0_ARESETN, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + S_AXI_HP1_ARESETN, + S_AXI_HP1_ARREADY, + S_AXI_HP1_AWREADY, + S_AXI_HP1_BVALID, + S_AXI_HP1_RLAST, + S_AXI_HP1_RVALID, + S_AXI_HP1_WREADY, + S_AXI_HP1_BRESP, + S_AXI_HP1_RRESP, + S_AXI_HP1_BID, + S_AXI_HP1_RID, + S_AXI_HP1_RDATA, + S_AXI_HP1_RCOUNT, + S_AXI_HP1_WCOUNT, + S_AXI_HP1_RACOUNT, + S_AXI_HP1_WACOUNT, + S_AXI_HP1_ACLK, + S_AXI_HP1_ARVALID, + S_AXI_HP1_AWVALID, + S_AXI_HP1_BREADY, + S_AXI_HP1_RDISSUECAP1_EN, + S_AXI_HP1_RREADY, + S_AXI_HP1_WLAST, + S_AXI_HP1_WRISSUECAP1_EN, + S_AXI_HP1_WVALID, + S_AXI_HP1_ARBURST, + S_AXI_HP1_ARLOCK, + S_AXI_HP1_ARSIZE, + S_AXI_HP1_AWBURST, + S_AXI_HP1_AWLOCK, + S_AXI_HP1_AWSIZE, + S_AXI_HP1_ARPROT, + S_AXI_HP1_AWPROT, + S_AXI_HP1_ARADDR, + S_AXI_HP1_AWADDR, + S_AXI_HP1_ARCACHE, + S_AXI_HP1_ARLEN, + S_AXI_HP1_ARQOS, + S_AXI_HP1_AWCACHE, + S_AXI_HP1_AWLEN, + S_AXI_HP1_AWQOS, + S_AXI_HP1_ARID, + S_AXI_HP1_AWID, + S_AXI_HP1_WID, + S_AXI_HP1_WDATA, + S_AXI_HP1_WSTRB, + S_AXI_HP2_ARESETN, + S_AXI_HP2_ARREADY, + S_AXI_HP2_AWREADY, + S_AXI_HP2_BVALID, + S_AXI_HP2_RLAST, + S_AXI_HP2_RVALID, + S_AXI_HP2_WREADY, + S_AXI_HP2_BRESP, + S_AXI_HP2_RRESP, + S_AXI_HP2_BID, + S_AXI_HP2_RID, + S_AXI_HP2_RDATA, + S_AXI_HP2_RCOUNT, + S_AXI_HP2_WCOUNT, + S_AXI_HP2_RACOUNT, + S_AXI_HP2_WACOUNT, + S_AXI_HP2_ACLK, + S_AXI_HP2_ARVALID, + S_AXI_HP2_AWVALID, + S_AXI_HP2_BREADY, + S_AXI_HP2_RDISSUECAP1_EN, + S_AXI_HP2_RREADY, + S_AXI_HP2_WLAST, + S_AXI_HP2_WRISSUECAP1_EN, + S_AXI_HP2_WVALID, + S_AXI_HP2_ARBURST, + S_AXI_HP2_ARLOCK, + S_AXI_HP2_ARSIZE, + S_AXI_HP2_AWBURST, + S_AXI_HP2_AWLOCK, + S_AXI_HP2_AWSIZE, + S_AXI_HP2_ARPROT, + S_AXI_HP2_AWPROT, + S_AXI_HP2_ARADDR, + S_AXI_HP2_AWADDR, + S_AXI_HP2_ARCACHE, + S_AXI_HP2_ARLEN, + S_AXI_HP2_ARQOS, + S_AXI_HP2_AWCACHE, + S_AXI_HP2_AWLEN, + S_AXI_HP2_AWQOS, + S_AXI_HP2_ARID, + S_AXI_HP2_AWID, + S_AXI_HP2_WID, + S_AXI_HP2_WDATA, + S_AXI_HP2_WSTRB, + S_AXI_HP3_ARESETN, + S_AXI_HP3_ARREADY, + S_AXI_HP3_AWREADY, + S_AXI_HP3_BVALID, + S_AXI_HP3_RLAST, + S_AXI_HP3_RVALID, + S_AXI_HP3_WREADY, + S_AXI_HP3_BRESP, + S_AXI_HP3_RRESP, + S_AXI_HP3_BID, + S_AXI_HP3_RID, + S_AXI_HP3_RDATA, + S_AXI_HP3_RCOUNT, + S_AXI_HP3_WCOUNT, + S_AXI_HP3_RACOUNT, + S_AXI_HP3_WACOUNT, + S_AXI_HP3_ACLK, + S_AXI_HP3_ARVALID, + S_AXI_HP3_AWVALID, + S_AXI_HP3_BREADY, + S_AXI_HP3_RDISSUECAP1_EN, + S_AXI_HP3_RREADY, + S_AXI_HP3_WLAST, + S_AXI_HP3_WRISSUECAP1_EN, + S_AXI_HP3_WVALID, + S_AXI_HP3_ARBURST, + S_AXI_HP3_ARLOCK, + S_AXI_HP3_ARSIZE, + S_AXI_HP3_AWBURST, + S_AXI_HP3_AWLOCK, + S_AXI_HP3_AWSIZE, + S_AXI_HP3_ARPROT, + S_AXI_HP3_AWPROT, + S_AXI_HP3_ARADDR, + S_AXI_HP3_AWADDR, + S_AXI_HP3_ARCACHE, + S_AXI_HP3_ARLEN, + S_AXI_HP3_ARQOS, + S_AXI_HP3_AWCACHE, + S_AXI_HP3_AWLEN, + S_AXI_HP3_AWQOS, + S_AXI_HP3_ARID, + S_AXI_HP3_AWID, + S_AXI_HP3_WID, + S_AXI_HP3_WDATA, + S_AXI_HP3_WSTRB, + IRQ_P2F_DMAC_ABORT, + IRQ_P2F_DMAC0, + IRQ_P2F_DMAC1, + IRQ_P2F_DMAC2, + IRQ_P2F_DMAC3, + IRQ_P2F_DMAC4, + IRQ_P2F_DMAC5, + IRQ_P2F_DMAC6, + IRQ_P2F_DMAC7, + IRQ_P2F_SMC, + IRQ_P2F_QSPI, + IRQ_P2F_CTI, + IRQ_P2F_GPIO, + IRQ_P2F_USB0, + IRQ_P2F_ENET0, + IRQ_P2F_ENET_WAKE0, + IRQ_P2F_SDIO0, + IRQ_P2F_I2C0, + IRQ_P2F_SPI0, + IRQ_P2F_UART0, + IRQ_P2F_CAN0, + IRQ_P2F_USB1, + IRQ_P2F_ENET1, + IRQ_P2F_ENET_WAKE1, + IRQ_P2F_SDIO1, + IRQ_P2F_I2C1, + IRQ_P2F_SPI1, + IRQ_P2F_UART1, + IRQ_P2F_CAN1, + IRQ_F2P, + Core0_nFIQ, + Core0_nIRQ, + Core1_nFIQ, + Core1_nIRQ, + DMA0_DATYPE, + DMA0_DAVALID, + DMA0_DRREADY, + DMA0_RSTN, + DMA1_DATYPE, + DMA1_DAVALID, + DMA1_DRREADY, + DMA1_RSTN, + DMA2_DATYPE, + DMA2_DAVALID, + DMA2_DRREADY, + DMA2_RSTN, + DMA3_DATYPE, + DMA3_DAVALID, + DMA3_DRREADY, + DMA3_RSTN, + DMA0_ACLK, + DMA0_DAREADY, + DMA0_DRLAST, + DMA0_DRVALID, + DMA1_ACLK, + DMA1_DAREADY, + DMA1_DRLAST, + DMA1_DRVALID, + DMA2_ACLK, + DMA2_DAREADY, + DMA2_DRLAST, + DMA2_DRVALID, + DMA3_ACLK, + DMA3_DAREADY, + DMA3_DRLAST, + DMA3_DRVALID, + DMA0_DRTYPE, + DMA1_DRTYPE, + DMA2_DRTYPE, + DMA3_DRTYPE, + FCLK_CLK3, + FCLK_CLK2, + FCLK_CLK1, + FCLK_CLK0, + FCLK_CLKTRIG3_N, + FCLK_CLKTRIG2_N, + FCLK_CLKTRIG1_N, + FCLK_CLKTRIG0_N, + FCLK_RESET3_N, + FCLK_RESET2_N, + FCLK_RESET1_N, + FCLK_RESET0_N, + FTMD_TRACEIN_DATA, + FTMD_TRACEIN_VALID, + FTMD_TRACEIN_CLK, + FTMD_TRACEIN_ATID, + FTMT_F2P_TRIG_0, + FTMT_F2P_TRIGACK_0, + FTMT_F2P_TRIG_1, + FTMT_F2P_TRIGACK_1, + FTMT_F2P_TRIG_2, + FTMT_F2P_TRIGACK_2, + FTMT_F2P_TRIG_3, + FTMT_F2P_TRIGACK_3, + FTMT_F2P_DEBUG, + FTMT_P2F_TRIGACK_0, + FTMT_P2F_TRIG_0, + FTMT_P2F_TRIGACK_1, + FTMT_P2F_TRIG_1, + FTMT_P2F_TRIGACK_2, + FTMT_P2F_TRIG_2, + FTMT_P2F_TRIGACK_3, + FTMT_P2F_TRIG_3, + FTMT_P2F_DEBUG, + FPGA_IDLE_N, + EVENT_EVENTO, + EVENT_STANDBYWFE, + EVENT_STANDBYWFI, + EVENT_EVENTI, + DDR_ARB, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB); + output CAN0_PHY_TX; + input CAN0_PHY_RX; + output CAN1_PHY_TX; + input CAN1_PHY_RX; + output ENET0_GMII_TX_EN; + output ENET0_GMII_TX_ER; + output ENET0_MDIO_MDC; + output ENET0_MDIO_O; + output ENET0_MDIO_T; + output ENET0_PTP_DELAY_REQ_RX; + output ENET0_PTP_DELAY_REQ_TX; + output ENET0_PTP_PDELAY_REQ_RX; + output ENET0_PTP_PDELAY_REQ_TX; + output ENET0_PTP_PDELAY_RESP_RX; + output ENET0_PTP_PDELAY_RESP_TX; + output ENET0_PTP_SYNC_FRAME_RX; + output ENET0_PTP_SYNC_FRAME_TX; + output ENET0_SOF_RX; + output ENET0_SOF_TX; + output [7:0]ENET0_GMII_TXD; + input ENET0_GMII_COL; + input ENET0_GMII_CRS; + input ENET0_GMII_RX_CLK; + input ENET0_GMII_RX_DV; + input ENET0_GMII_RX_ER; + input ENET0_GMII_TX_CLK; + input ENET0_MDIO_I; + input ENET0_EXT_INTIN; + input [7:0]ENET0_GMII_RXD; + output ENET1_GMII_TX_EN; + output ENET1_GMII_TX_ER; + output ENET1_MDIO_MDC; + output ENET1_MDIO_O; + output ENET1_MDIO_T; + output ENET1_PTP_DELAY_REQ_RX; + output ENET1_PTP_DELAY_REQ_TX; + output ENET1_PTP_PDELAY_REQ_RX; + output ENET1_PTP_PDELAY_REQ_TX; + output ENET1_PTP_PDELAY_RESP_RX; + output ENET1_PTP_PDELAY_RESP_TX; + output ENET1_PTP_SYNC_FRAME_RX; + output ENET1_PTP_SYNC_FRAME_TX; + output ENET1_SOF_RX; + output ENET1_SOF_TX; + output [7:0]ENET1_GMII_TXD; + input ENET1_GMII_COL; + input ENET1_GMII_CRS; + input ENET1_GMII_RX_CLK; + input ENET1_GMII_RX_DV; + input ENET1_GMII_RX_ER; + input ENET1_GMII_TX_CLK; + input ENET1_MDIO_I; + input ENET1_EXT_INTIN; + input [7:0]ENET1_GMII_RXD; + input [63:0]GPIO_I; + output [63:0]GPIO_O; + output [63:0]GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + input I2C1_SDA_I; + output I2C1_SDA_O; + output I2C1_SDA_T; + input I2C1_SCL_I; + output I2C1_SCL_O; + output I2C1_SCL_T; + input PJTAG_TCK; + input PJTAG_TMS; + input PJTAG_TDI; + output PJTAG_TDO; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0]SDIO0_DATA_I; + output [3:0]SDIO0_DATA_O; + output [3:0]SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0]SDIO0_BUSVOLT; + output SDIO1_CLK; + input SDIO1_CLK_FB; + output SDIO1_CMD_O; + input SDIO1_CMD_I; + output SDIO1_CMD_T; + input [3:0]SDIO1_DATA_I; + output [3:0]SDIO1_DATA_O; + output [3:0]SDIO1_DATA_T; + output SDIO1_LED; + input SDIO1_CDN; + input SDIO1_WP; + output SDIO1_BUSPOW; + output [2:0]SDIO1_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_DTRN; + output UART0_RTSN; + output UART0_TX; + input UART0_CTSN; + input UART0_DCDN; + input UART0_DSRN; + input UART0_RIN; + input UART0_RX; + output UART1_DTRN; + output UART1_RTSN; + output UART1_TX; + input UART1_CTSN; + input UART1_DCDN; + input UART1_DSRN; + input UART1_RIN; + input UART1_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + input TTC0_CLK0_IN; + input TTC0_CLK1_IN; + input TTC0_CLK2_IN; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + input TTC1_CLK0_IN; + input TTC1_CLK1_IN; + input TTC1_CLK2_IN; + input WDT_CLK_IN; + output WDT_RST_OUT; + input TRACE_CLK; + output TRACE_CTL; + output [1:0]TRACE_DATA; + output TRACE_CLK_OUT; + output [1:0]USB0_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + output [1:0]USB1_PORT_INDCTL; + output USB1_VBUS_PWRSELECT; + input USB1_VBUS_PWRFAULT; + input SRAM_INTIN; + output M_AXI_GP0_ARESETN; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [11:0]M_AXI_GP0_ARID; + output [11:0]M_AXI_GP0_AWID; + output [11:0]M_AXI_GP0_WID; + output [1:0]M_AXI_GP0_ARBURST; + output [1:0]M_AXI_GP0_ARLOCK; + output [2:0]M_AXI_GP0_ARSIZE; + output [1:0]M_AXI_GP0_AWBURST; + output [1:0]M_AXI_GP0_AWLOCK; + output [2:0]M_AXI_GP0_AWSIZE; + output [2:0]M_AXI_GP0_ARPROT; + output [2:0]M_AXI_GP0_AWPROT; + output [31:0]M_AXI_GP0_ARADDR; + output [31:0]M_AXI_GP0_AWADDR; + output [31:0]M_AXI_GP0_WDATA; + output [3:0]M_AXI_GP0_ARCACHE; + output [3:0]M_AXI_GP0_ARLEN; + output [3:0]M_AXI_GP0_ARQOS; + output [3:0]M_AXI_GP0_AWCACHE; + output [3:0]M_AXI_GP0_AWLEN; + output [3:0]M_AXI_GP0_AWQOS; + output [3:0]M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [11:0]M_AXI_GP0_BID; + input [11:0]M_AXI_GP0_RID; + input [1:0]M_AXI_GP0_BRESP; + input [1:0]M_AXI_GP0_RRESP; + input [31:0]M_AXI_GP0_RDATA; + output M_AXI_GP1_ARESETN; + output M_AXI_GP1_ARVALID; + output M_AXI_GP1_AWVALID; + output M_AXI_GP1_BREADY; + output M_AXI_GP1_RREADY; + output M_AXI_GP1_WLAST; + output M_AXI_GP1_WVALID; + output [11:0]M_AXI_GP1_ARID; + output [11:0]M_AXI_GP1_AWID; + output [11:0]M_AXI_GP1_WID; + output [1:0]M_AXI_GP1_ARBURST; + output [1:0]M_AXI_GP1_ARLOCK; + output [2:0]M_AXI_GP1_ARSIZE; + output [1:0]M_AXI_GP1_AWBURST; + output [1:0]M_AXI_GP1_AWLOCK; + output [2:0]M_AXI_GP1_AWSIZE; + output [2:0]M_AXI_GP1_ARPROT; + output [2:0]M_AXI_GP1_AWPROT; + output [31:0]M_AXI_GP1_ARADDR; + output [31:0]M_AXI_GP1_AWADDR; + output [31:0]M_AXI_GP1_WDATA; + output [3:0]M_AXI_GP1_ARCACHE; + output [3:0]M_AXI_GP1_ARLEN; + output [3:0]M_AXI_GP1_ARQOS; + output [3:0]M_AXI_GP1_AWCACHE; + output [3:0]M_AXI_GP1_AWLEN; + output [3:0]M_AXI_GP1_AWQOS; + output [3:0]M_AXI_GP1_WSTRB; + input M_AXI_GP1_ACLK; + input M_AXI_GP1_ARREADY; + input M_AXI_GP1_AWREADY; + input M_AXI_GP1_BVALID; + input M_AXI_GP1_RLAST; + input M_AXI_GP1_RVALID; + input M_AXI_GP1_WREADY; + input [11:0]M_AXI_GP1_BID; + input [11:0]M_AXI_GP1_RID; + input [1:0]M_AXI_GP1_BRESP; + input [1:0]M_AXI_GP1_RRESP; + input [31:0]M_AXI_GP1_RDATA; + output S_AXI_GP0_ARESETN; + output S_AXI_GP0_ARREADY; + output S_AXI_GP0_AWREADY; + output S_AXI_GP0_BVALID; + output S_AXI_GP0_RLAST; + output S_AXI_GP0_RVALID; + output S_AXI_GP0_WREADY; + output [1:0]S_AXI_GP0_BRESP; + output [1:0]S_AXI_GP0_RRESP; + output [31:0]S_AXI_GP0_RDATA; + output [5:0]S_AXI_GP0_BID; + output [5:0]S_AXI_GP0_RID; + input S_AXI_GP0_ACLK; + input S_AXI_GP0_ARVALID; + input S_AXI_GP0_AWVALID; + input S_AXI_GP0_BREADY; + input S_AXI_GP0_RREADY; + input S_AXI_GP0_WLAST; + input S_AXI_GP0_WVALID; + input [1:0]S_AXI_GP0_ARBURST; + input [1:0]S_AXI_GP0_ARLOCK; + input [2:0]S_AXI_GP0_ARSIZE; + input [1:0]S_AXI_GP0_AWBURST; + input [1:0]S_AXI_GP0_AWLOCK; + input [2:0]S_AXI_GP0_AWSIZE; + input [2:0]S_AXI_GP0_ARPROT; + input [2:0]S_AXI_GP0_AWPROT; + input [31:0]S_AXI_GP0_ARADDR; + input [31:0]S_AXI_GP0_AWADDR; + input [31:0]S_AXI_GP0_WDATA; + input [3:0]S_AXI_GP0_ARCACHE; + input [3:0]S_AXI_GP0_ARLEN; + input [3:0]S_AXI_GP0_ARQOS; + input [3:0]S_AXI_GP0_AWCACHE; + input [3:0]S_AXI_GP0_AWLEN; + input [3:0]S_AXI_GP0_AWQOS; + input [3:0]S_AXI_GP0_WSTRB; + input [5:0]S_AXI_GP0_ARID; + input [5:0]S_AXI_GP0_AWID; + input [5:0]S_AXI_GP0_WID; + output S_AXI_GP1_ARESETN; + output S_AXI_GP1_ARREADY; + output S_AXI_GP1_AWREADY; + output S_AXI_GP1_BVALID; + output S_AXI_GP1_RLAST; + output S_AXI_GP1_RVALID; + output S_AXI_GP1_WREADY; + output [1:0]S_AXI_GP1_BRESP; + output [1:0]S_AXI_GP1_RRESP; + output [31:0]S_AXI_GP1_RDATA; + output [5:0]S_AXI_GP1_BID; + output [5:0]S_AXI_GP1_RID; + input S_AXI_GP1_ACLK; + input S_AXI_GP1_ARVALID; + input S_AXI_GP1_AWVALID; + input S_AXI_GP1_BREADY; + input S_AXI_GP1_RREADY; + input S_AXI_GP1_WLAST; + input S_AXI_GP1_WVALID; + input [1:0]S_AXI_GP1_ARBURST; + input [1:0]S_AXI_GP1_ARLOCK; + input [2:0]S_AXI_GP1_ARSIZE; + input [1:0]S_AXI_GP1_AWBURST; + input [1:0]S_AXI_GP1_AWLOCK; + input [2:0]S_AXI_GP1_AWSIZE; + input [2:0]S_AXI_GP1_ARPROT; + input [2:0]S_AXI_GP1_AWPROT; + input [31:0]S_AXI_GP1_ARADDR; + input [31:0]S_AXI_GP1_AWADDR; + input [31:0]S_AXI_GP1_WDATA; + input [3:0]S_AXI_GP1_ARCACHE; + input [3:0]S_AXI_GP1_ARLEN; + input [3:0]S_AXI_GP1_ARQOS; + input [3:0]S_AXI_GP1_AWCACHE; + input [3:0]S_AXI_GP1_AWLEN; + input [3:0]S_AXI_GP1_AWQOS; + input [3:0]S_AXI_GP1_WSTRB; + input [5:0]S_AXI_GP1_ARID; + input [5:0]S_AXI_GP1_AWID; + input [5:0]S_AXI_GP1_WID; + output S_AXI_ACP_ARESETN; + output S_AXI_ACP_ARREADY; + output S_AXI_ACP_AWREADY; + output S_AXI_ACP_BVALID; + output S_AXI_ACP_RLAST; + output S_AXI_ACP_RVALID; + output S_AXI_ACP_WREADY; + output [1:0]S_AXI_ACP_BRESP; + output [1:0]S_AXI_ACP_RRESP; + output [2:0]S_AXI_ACP_BID; + output [2:0]S_AXI_ACP_RID; + output [63:0]S_AXI_ACP_RDATA; + input S_AXI_ACP_ACLK; + input S_AXI_ACP_ARVALID; + input S_AXI_ACP_AWVALID; + input S_AXI_ACP_BREADY; + input S_AXI_ACP_RREADY; + input S_AXI_ACP_WLAST; + input S_AXI_ACP_WVALID; + input [2:0]S_AXI_ACP_ARID; + input [2:0]S_AXI_ACP_ARPROT; + input [2:0]S_AXI_ACP_AWID; + input [2:0]S_AXI_ACP_AWPROT; + input [2:0]S_AXI_ACP_WID; + input [31:0]S_AXI_ACP_ARADDR; + input [31:0]S_AXI_ACP_AWADDR; + input [3:0]S_AXI_ACP_ARCACHE; + input [3:0]S_AXI_ACP_ARLEN; + input [3:0]S_AXI_ACP_ARQOS; + input [3:0]S_AXI_ACP_AWCACHE; + input [3:0]S_AXI_ACP_AWLEN; + input [3:0]S_AXI_ACP_AWQOS; + input [1:0]S_AXI_ACP_ARBURST; + input [1:0]S_AXI_ACP_ARLOCK; + input [2:0]S_AXI_ACP_ARSIZE; + input [1:0]S_AXI_ACP_AWBURST; + input [1:0]S_AXI_ACP_AWLOCK; + input [2:0]S_AXI_ACP_AWSIZE; + input [4:0]S_AXI_ACP_ARUSER; + input [4:0]S_AXI_ACP_AWUSER; + input [63:0]S_AXI_ACP_WDATA; + input [7:0]S_AXI_ACP_WSTRB; + output S_AXI_HP0_ARESETN; + output S_AXI_HP0_ARREADY; + output S_AXI_HP0_AWREADY; + output S_AXI_HP0_BVALID; + output S_AXI_HP0_RLAST; + output S_AXI_HP0_RVALID; + output S_AXI_HP0_WREADY; + output [1:0]S_AXI_HP0_BRESP; + output [1:0]S_AXI_HP0_RRESP; + output [5:0]S_AXI_HP0_BID; + output [5:0]S_AXI_HP0_RID; + output [63:0]S_AXI_HP0_RDATA; + output [7:0]S_AXI_HP0_RCOUNT; + output [7:0]S_AXI_HP0_WCOUNT; + output [2:0]S_AXI_HP0_RACOUNT; + output [5:0]S_AXI_HP0_WACOUNT; + input S_AXI_HP0_ACLK; + input S_AXI_HP0_ARVALID; + input S_AXI_HP0_AWVALID; + input S_AXI_HP0_BREADY; + input S_AXI_HP0_RDISSUECAP1_EN; + input S_AXI_HP0_RREADY; + input S_AXI_HP0_WLAST; + input S_AXI_HP0_WRISSUECAP1_EN; + input S_AXI_HP0_WVALID; + input [1:0]S_AXI_HP0_ARBURST; + input [1:0]S_AXI_HP0_ARLOCK; + input [2:0]S_AXI_HP0_ARSIZE; + input [1:0]S_AXI_HP0_AWBURST; + input [1:0]S_AXI_HP0_AWLOCK; + input [2:0]S_AXI_HP0_AWSIZE; + input [2:0]S_AXI_HP0_ARPROT; + input [2:0]S_AXI_HP0_AWPROT; + input [31:0]S_AXI_HP0_ARADDR; + input [31:0]S_AXI_HP0_AWADDR; + input [3:0]S_AXI_HP0_ARCACHE; + input [3:0]S_AXI_HP0_ARLEN; + input [3:0]S_AXI_HP0_ARQOS; + input [3:0]S_AXI_HP0_AWCACHE; + input [3:0]S_AXI_HP0_AWLEN; + input [3:0]S_AXI_HP0_AWQOS; + input [5:0]S_AXI_HP0_ARID; + input [5:0]S_AXI_HP0_AWID; + input [5:0]S_AXI_HP0_WID; + input [63:0]S_AXI_HP0_WDATA; + input [7:0]S_AXI_HP0_WSTRB; + output S_AXI_HP1_ARESETN; + output S_AXI_HP1_ARREADY; + output S_AXI_HP1_AWREADY; + output S_AXI_HP1_BVALID; + output S_AXI_HP1_RLAST; + output S_AXI_HP1_RVALID; + output S_AXI_HP1_WREADY; + output [1:0]S_AXI_HP1_BRESP; + output [1:0]S_AXI_HP1_RRESP; + output [5:0]S_AXI_HP1_BID; + output [5:0]S_AXI_HP1_RID; + output [63:0]S_AXI_HP1_RDATA; + output [7:0]S_AXI_HP1_RCOUNT; + output [7:0]S_AXI_HP1_WCOUNT; + output [2:0]S_AXI_HP1_RACOUNT; + output [5:0]S_AXI_HP1_WACOUNT; + input S_AXI_HP1_ACLK; + input S_AXI_HP1_ARVALID; + input S_AXI_HP1_AWVALID; + input S_AXI_HP1_BREADY; + input S_AXI_HP1_RDISSUECAP1_EN; + input S_AXI_HP1_RREADY; + input S_AXI_HP1_WLAST; + input S_AXI_HP1_WRISSUECAP1_EN; + input S_AXI_HP1_WVALID; + input [1:0]S_AXI_HP1_ARBURST; + input [1:0]S_AXI_HP1_ARLOCK; + input [2:0]S_AXI_HP1_ARSIZE; + input [1:0]S_AXI_HP1_AWBURST; + input [1:0]S_AXI_HP1_AWLOCK; + input [2:0]S_AXI_HP1_AWSIZE; + input [2:0]S_AXI_HP1_ARPROT; + input [2:0]S_AXI_HP1_AWPROT; + input [31:0]S_AXI_HP1_ARADDR; + input [31:0]S_AXI_HP1_AWADDR; + input [3:0]S_AXI_HP1_ARCACHE; + input [3:0]S_AXI_HP1_ARLEN; + input [3:0]S_AXI_HP1_ARQOS; + input [3:0]S_AXI_HP1_AWCACHE; + input [3:0]S_AXI_HP1_AWLEN; + input [3:0]S_AXI_HP1_AWQOS; + input [5:0]S_AXI_HP1_ARID; + input [5:0]S_AXI_HP1_AWID; + input [5:0]S_AXI_HP1_WID; + input [63:0]S_AXI_HP1_WDATA; + input [7:0]S_AXI_HP1_WSTRB; + output S_AXI_HP2_ARESETN; + output S_AXI_HP2_ARREADY; + output S_AXI_HP2_AWREADY; + output S_AXI_HP2_BVALID; + output S_AXI_HP2_RLAST; + output S_AXI_HP2_RVALID; + output S_AXI_HP2_WREADY; + output [1:0]S_AXI_HP2_BRESP; + output [1:0]S_AXI_HP2_RRESP; + output [5:0]S_AXI_HP2_BID; + output [5:0]S_AXI_HP2_RID; + output [63:0]S_AXI_HP2_RDATA; + output [7:0]S_AXI_HP2_RCOUNT; + output [7:0]S_AXI_HP2_WCOUNT; + output [2:0]S_AXI_HP2_RACOUNT; + output [5:0]S_AXI_HP2_WACOUNT; + input S_AXI_HP2_ACLK; + input S_AXI_HP2_ARVALID; + input S_AXI_HP2_AWVALID; + input S_AXI_HP2_BREADY; + input S_AXI_HP2_RDISSUECAP1_EN; + input S_AXI_HP2_RREADY; + input S_AXI_HP2_WLAST; + input S_AXI_HP2_WRISSUECAP1_EN; + input S_AXI_HP2_WVALID; + input [1:0]S_AXI_HP2_ARBURST; + input [1:0]S_AXI_HP2_ARLOCK; + input [2:0]S_AXI_HP2_ARSIZE; + input [1:0]S_AXI_HP2_AWBURST; + input [1:0]S_AXI_HP2_AWLOCK; + input [2:0]S_AXI_HP2_AWSIZE; + input [2:0]S_AXI_HP2_ARPROT; + input [2:0]S_AXI_HP2_AWPROT; + input [31:0]S_AXI_HP2_ARADDR; + input [31:0]S_AXI_HP2_AWADDR; + input [3:0]S_AXI_HP2_ARCACHE; + input [3:0]S_AXI_HP2_ARLEN; + input [3:0]S_AXI_HP2_ARQOS; + input [3:0]S_AXI_HP2_AWCACHE; + input [3:0]S_AXI_HP2_AWLEN; + input [3:0]S_AXI_HP2_AWQOS; + input [5:0]S_AXI_HP2_ARID; + input [5:0]S_AXI_HP2_AWID; + input [5:0]S_AXI_HP2_WID; + input [63:0]S_AXI_HP2_WDATA; + input [7:0]S_AXI_HP2_WSTRB; + output S_AXI_HP3_ARESETN; + output S_AXI_HP3_ARREADY; + output S_AXI_HP3_AWREADY; + output S_AXI_HP3_BVALID; + output S_AXI_HP3_RLAST; + output S_AXI_HP3_RVALID; + output S_AXI_HP3_WREADY; + output [1:0]S_AXI_HP3_BRESP; + output [1:0]S_AXI_HP3_RRESP; + output [5:0]S_AXI_HP3_BID; + output [5:0]S_AXI_HP3_RID; + output [63:0]S_AXI_HP3_RDATA; + output [7:0]S_AXI_HP3_RCOUNT; + output [7:0]S_AXI_HP3_WCOUNT; + output [2:0]S_AXI_HP3_RACOUNT; + output [5:0]S_AXI_HP3_WACOUNT; + input S_AXI_HP3_ACLK; + input S_AXI_HP3_ARVALID; + input S_AXI_HP3_AWVALID; + input S_AXI_HP3_BREADY; + input S_AXI_HP3_RDISSUECAP1_EN; + input S_AXI_HP3_RREADY; + input S_AXI_HP3_WLAST; + input S_AXI_HP3_WRISSUECAP1_EN; + input S_AXI_HP3_WVALID; + input [1:0]S_AXI_HP3_ARBURST; + input [1:0]S_AXI_HP3_ARLOCK; + input [2:0]S_AXI_HP3_ARSIZE; + input [1:0]S_AXI_HP3_AWBURST; + input [1:0]S_AXI_HP3_AWLOCK; + input [2:0]S_AXI_HP3_AWSIZE; + input [2:0]S_AXI_HP3_ARPROT; + input [2:0]S_AXI_HP3_AWPROT; + input [31:0]S_AXI_HP3_ARADDR; + input [31:0]S_AXI_HP3_AWADDR; + input [3:0]S_AXI_HP3_ARCACHE; + input [3:0]S_AXI_HP3_ARLEN; + input [3:0]S_AXI_HP3_ARQOS; + input [3:0]S_AXI_HP3_AWCACHE; + input [3:0]S_AXI_HP3_AWLEN; + input [3:0]S_AXI_HP3_AWQOS; + input [5:0]S_AXI_HP3_ARID; + input [5:0]S_AXI_HP3_AWID; + input [5:0]S_AXI_HP3_WID; + input [63:0]S_AXI_HP3_WDATA; + input [7:0]S_AXI_HP3_WSTRB; + output IRQ_P2F_DMAC_ABORT; + output IRQ_P2F_DMAC0; + output IRQ_P2F_DMAC1; + output IRQ_P2F_DMAC2; + output IRQ_P2F_DMAC3; + output IRQ_P2F_DMAC4; + output IRQ_P2F_DMAC5; + output IRQ_P2F_DMAC6; + output IRQ_P2F_DMAC7; + output IRQ_P2F_SMC; + output IRQ_P2F_QSPI; + output IRQ_P2F_CTI; + output IRQ_P2F_GPIO; + output IRQ_P2F_USB0; + output IRQ_P2F_ENET0; + output IRQ_P2F_ENET_WAKE0; + output IRQ_P2F_SDIO0; + output IRQ_P2F_I2C0; + output IRQ_P2F_SPI0; + output IRQ_P2F_UART0; + output IRQ_P2F_CAN0; + output IRQ_P2F_USB1; + output IRQ_P2F_ENET1; + output IRQ_P2F_ENET_WAKE1; + output IRQ_P2F_SDIO1; + output IRQ_P2F_I2C1; + output IRQ_P2F_SPI1; + output IRQ_P2F_UART1; + output IRQ_P2F_CAN1; + input [0:0]IRQ_F2P; + input Core0_nFIQ; + input Core0_nIRQ; + input Core1_nFIQ; + input Core1_nIRQ; + output [1:0]DMA0_DATYPE; + output DMA0_DAVALID; + output DMA0_DRREADY; + output DMA0_RSTN; + output [1:0]DMA1_DATYPE; + output DMA1_DAVALID; + output DMA1_DRREADY; + output DMA1_RSTN; + output [1:0]DMA2_DATYPE; + output DMA2_DAVALID; + output DMA2_DRREADY; + output DMA2_RSTN; + output [1:0]DMA3_DATYPE; + output DMA3_DAVALID; + output DMA3_DRREADY; + output DMA3_RSTN; + input DMA0_ACLK; + input DMA0_DAREADY; + input DMA0_DRLAST; + input DMA0_DRVALID; + input DMA1_ACLK; + input DMA1_DAREADY; + input DMA1_DRLAST; + input DMA1_DRVALID; + input DMA2_ACLK; + input DMA2_DAREADY; + input DMA2_DRLAST; + input DMA2_DRVALID; + input DMA3_ACLK; + input DMA3_DAREADY; + input DMA3_DRLAST; + input DMA3_DRVALID; + input [1:0]DMA0_DRTYPE; + input [1:0]DMA1_DRTYPE; + input [1:0]DMA2_DRTYPE; + input [1:0]DMA3_DRTYPE; + output FCLK_CLK3; + output FCLK_CLK2; + output FCLK_CLK1; + output FCLK_CLK0; + input FCLK_CLKTRIG3_N; + input FCLK_CLKTRIG2_N; + input FCLK_CLKTRIG1_N; + input FCLK_CLKTRIG0_N; + output FCLK_RESET3_N; + output FCLK_RESET2_N; + output FCLK_RESET1_N; + output FCLK_RESET0_N; + input [31:0]FTMD_TRACEIN_DATA; + input FTMD_TRACEIN_VALID; + input FTMD_TRACEIN_CLK; + input [3:0]FTMD_TRACEIN_ATID; + input FTMT_F2P_TRIG_0; + output FTMT_F2P_TRIGACK_0; + input FTMT_F2P_TRIG_1; + output FTMT_F2P_TRIGACK_1; + input FTMT_F2P_TRIG_2; + output FTMT_F2P_TRIGACK_2; + input FTMT_F2P_TRIG_3; + output FTMT_F2P_TRIGACK_3; + input [31:0]FTMT_F2P_DEBUG; + input FTMT_P2F_TRIGACK_0; + output FTMT_P2F_TRIG_0; + input FTMT_P2F_TRIGACK_1; + output FTMT_P2F_TRIG_1; + input FTMT_P2F_TRIGACK_2; + output FTMT_P2F_TRIG_2; + input FTMT_P2F_TRIGACK_3; + output FTMT_P2F_TRIG_3; + output [31:0]FTMT_P2F_DEBUG; + input FPGA_IDLE_N; + output EVENT_EVENTO; + output [1:0]EVENT_STANDBYWFE; + output [1:0]EVENT_STANDBYWFI; + input EVENT_EVENTI; + input [3:0]DDR_ARB; + inout [31:0]MIO; + inout DDR_CAS_n; + inout DDR_CKE; + inout DDR_Clk_n; + inout DDR_Clk; + inout DDR_CS_n; + inout DDR_DRSTB; + inout DDR_ODT; + inout DDR_RAS_n; + inout DDR_WEB; + inout [2:0]DDR_BankAddr; + inout [14:0]DDR_Addr; + inout DDR_VRN; + inout DDR_VRP; + inout [1:0]DDR_DM; + inout [15:0]DDR_DQ; + inout [1:0]DDR_DQS_n; + inout [1:0]DDR_DQS; + inout PS_SRSTB; + inout PS_CLK; + inout PS_PORB; + + wire \ ; + wire \ ; + wire CAN0_PHY_RX; + wire CAN0_PHY_TX; + wire CAN1_PHY_RX; + wire CAN1_PHY_TX; + wire Core0_nFIQ; + wire Core0_nIRQ; + wire Core1_nFIQ; + wire Core1_nIRQ; + wire [3:0]DDR_ARB; + wire [14:0]DDR_Addr; + wire [2:0]DDR_BankAddr; + wire DDR_CAS_n; + wire DDR_CKE; + wire DDR_CS_n; + wire DDR_Clk; + wire DDR_Clk_n; + wire [1:0]DDR_DM; + wire [15:0]DDR_DQ; + wire [1:0]DDR_DQS; + wire [1:0]DDR_DQS_n; + wire DDR_DRSTB; + wire DDR_ODT; + wire DDR_RAS_n; + wire DDR_VRN; + wire DDR_VRP; + wire DDR_WEB; + wire DMA0_ACLK; + wire DMA0_DAREADY; + wire [1:0]DMA0_DATYPE; + wire DMA0_DAVALID; + wire DMA0_DRLAST; + wire DMA0_DRREADY; + wire [1:0]DMA0_DRTYPE; + wire DMA0_DRVALID; + wire DMA0_RSTN; + wire DMA1_ACLK; + wire DMA1_DAREADY; + wire [1:0]DMA1_DATYPE; + wire DMA1_DAVALID; + wire DMA1_DRLAST; + wire DMA1_DRREADY; + wire [1:0]DMA1_DRTYPE; + wire DMA1_DRVALID; + wire DMA1_RSTN; + wire DMA2_ACLK; + wire DMA2_DAREADY; + wire [1:0]DMA2_DATYPE; + wire DMA2_DAVALID; + wire DMA2_DRLAST; + wire DMA2_DRREADY; + wire [1:0]DMA2_DRTYPE; + wire DMA2_DRVALID; + wire DMA2_RSTN; + wire DMA3_ACLK; + wire DMA3_DAREADY; + wire [1:0]DMA3_DATYPE; + wire DMA3_DAVALID; + wire DMA3_DRLAST; + wire DMA3_DRREADY; + wire [1:0]DMA3_DRTYPE; + wire DMA3_DRVALID; + wire DMA3_RSTN; + wire ENET0_EXT_INTIN; + wire ENET0_GMII_RX_CLK; + wire ENET0_GMII_TX_CLK; + wire ENET0_MDIO_I; + wire ENET0_MDIO_MDC; + wire ENET0_MDIO_O; + wire ENET0_MDIO_T; + wire ENET0_MDIO_T_n; + wire ENET0_PTP_DELAY_REQ_RX; + wire ENET0_PTP_DELAY_REQ_TX; + wire ENET0_PTP_PDELAY_REQ_RX; + wire ENET0_PTP_PDELAY_REQ_TX; + wire ENET0_PTP_PDELAY_RESP_RX; + wire ENET0_PTP_PDELAY_RESP_TX; + wire ENET0_PTP_SYNC_FRAME_RX; + wire ENET0_PTP_SYNC_FRAME_TX; + wire ENET0_SOF_RX; + wire ENET0_SOF_TX; + wire ENET1_EXT_INTIN; + wire ENET1_GMII_RX_CLK; + wire ENET1_GMII_TX_CLK; + wire ENET1_MDIO_I; + wire ENET1_MDIO_MDC; + wire ENET1_MDIO_O; + wire ENET1_MDIO_T; + wire ENET1_MDIO_T_n; + wire ENET1_PTP_DELAY_REQ_RX; + wire ENET1_PTP_DELAY_REQ_TX; + wire ENET1_PTP_PDELAY_REQ_RX; + wire ENET1_PTP_PDELAY_REQ_TX; + wire ENET1_PTP_PDELAY_RESP_RX; + wire ENET1_PTP_PDELAY_RESP_TX; + wire ENET1_PTP_SYNC_FRAME_RX; + wire ENET1_PTP_SYNC_FRAME_TX; + wire ENET1_SOF_RX; + wire ENET1_SOF_TX; + wire EVENT_EVENTI; + wire EVENT_EVENTO; + wire [1:0]EVENT_STANDBYWFE; + wire [1:0]EVENT_STANDBYWFI; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire [1:0]FCLK_CLK_unbuffered; + wire FCLK_RESET0_N; + wire FCLK_RESET1_N; + wire FCLK_RESET2_N; + wire FCLK_RESET3_N; + wire FPGA_IDLE_N; + wire FTMD_TRACEIN_CLK; + wire [31:0]FTMT_F2P_DEBUG; + wire FTMT_F2P_TRIGACK_0; + wire FTMT_F2P_TRIGACK_1; + wire FTMT_F2P_TRIGACK_2; + wire FTMT_F2P_TRIGACK_3; + wire FTMT_F2P_TRIG_0; + wire FTMT_F2P_TRIG_1; + wire FTMT_F2P_TRIG_2; + wire FTMT_F2P_TRIG_3; + wire [31:0]FTMT_P2F_DEBUG; + wire FTMT_P2F_TRIGACK_0; + wire FTMT_P2F_TRIGACK_1; + wire FTMT_P2F_TRIGACK_2; + wire FTMT_P2F_TRIGACK_3; + wire FTMT_P2F_TRIG_0; + wire FTMT_P2F_TRIG_1; + wire FTMT_P2F_TRIG_2; + wire FTMT_P2F_TRIG_3; + wire [63:0]GPIO_I; + wire [63:0]GPIO_O; + wire [63:0]GPIO_T; + wire I2C0_SCL_I; + wire I2C0_SCL_O; + wire I2C0_SCL_T; + wire I2C0_SCL_T_n; + wire I2C0_SDA_I; + wire I2C0_SDA_O; + wire I2C0_SDA_T; + wire I2C0_SDA_T_n; + wire I2C1_SCL_I; + wire I2C1_SCL_O; + wire I2C1_SCL_T; + wire I2C1_SCL_T_n; + wire I2C1_SDA_I; + wire I2C1_SDA_O; + wire I2C1_SDA_T; + wire I2C1_SDA_T_n; + wire [0:0]IRQ_F2P; + wire IRQ_P2F_CAN0; + wire IRQ_P2F_CAN1; + wire IRQ_P2F_CTI; + wire IRQ_P2F_DMAC0; + wire IRQ_P2F_DMAC1; + wire IRQ_P2F_DMAC2; + wire IRQ_P2F_DMAC3; + wire IRQ_P2F_DMAC4; + wire IRQ_P2F_DMAC5; + wire IRQ_P2F_DMAC6; + wire IRQ_P2F_DMAC7; + wire IRQ_P2F_DMAC_ABORT; + wire IRQ_P2F_ENET0; + wire IRQ_P2F_ENET1; + wire IRQ_P2F_ENET_WAKE0; + wire IRQ_P2F_ENET_WAKE1; + wire IRQ_P2F_GPIO; + wire IRQ_P2F_I2C0; + wire IRQ_P2F_I2C1; + wire IRQ_P2F_QSPI; + wire IRQ_P2F_SDIO0; + wire IRQ_P2F_SDIO1; + wire IRQ_P2F_SMC; + wire IRQ_P2F_SPI0; + wire IRQ_P2F_SPI1; + wire IRQ_P2F_UART0; + wire IRQ_P2F_UART1; + wire IRQ_P2F_USB0; + wire IRQ_P2F_USB1; + wire [31:0]MIO; + wire M_AXI_GP0_ACLK; + wire [31:0]M_AXI_GP0_ARADDR; + wire [1:0]M_AXI_GP0_ARBURST; + wire [3:0]\^M_AXI_GP0_ARCACHE ; + wire M_AXI_GP0_ARESETN; + wire [11:0]M_AXI_GP0_ARID; + wire [3:0]M_AXI_GP0_ARLEN; + wire [1:0]M_AXI_GP0_ARLOCK; + wire [2:0]M_AXI_GP0_ARPROT; + wire [3:0]M_AXI_GP0_ARQOS; + wire M_AXI_GP0_ARREADY; + wire [1:0]\^M_AXI_GP0_ARSIZE ; + wire M_AXI_GP0_ARVALID; + wire [31:0]M_AXI_GP0_AWADDR; + wire [1:0]M_AXI_GP0_AWBURST; + wire [3:0]\^M_AXI_GP0_AWCACHE ; + wire [11:0]M_AXI_GP0_AWID; + wire [3:0]M_AXI_GP0_AWLEN; + wire [1:0]M_AXI_GP0_AWLOCK; + wire [2:0]M_AXI_GP0_AWPROT; + wire [3:0]M_AXI_GP0_AWQOS; + wire M_AXI_GP0_AWREADY; + wire [1:0]\^M_AXI_GP0_AWSIZE ; + wire M_AXI_GP0_AWVALID; + wire [11:0]M_AXI_GP0_BID; + wire M_AXI_GP0_BREADY; + wire [1:0]M_AXI_GP0_BRESP; + wire M_AXI_GP0_BVALID; + wire [31:0]M_AXI_GP0_RDATA; + wire [11:0]M_AXI_GP0_RID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RREADY; + wire [1:0]M_AXI_GP0_RRESP; + wire M_AXI_GP0_RVALID; + wire [31:0]M_AXI_GP0_WDATA; + wire [11:0]M_AXI_GP0_WID; + wire M_AXI_GP0_WLAST; + wire M_AXI_GP0_WREADY; + wire [3:0]M_AXI_GP0_WSTRB; + wire M_AXI_GP0_WVALID; + wire M_AXI_GP1_ACLK; + wire [31:0]M_AXI_GP1_ARADDR; + wire [1:0]M_AXI_GP1_ARBURST; + wire [3:0]\^M_AXI_GP1_ARCACHE ; + wire M_AXI_GP1_ARESETN; + wire [11:0]M_AXI_GP1_ARID; + wire [3:0]M_AXI_GP1_ARLEN; + wire [1:0]M_AXI_GP1_ARLOCK; + wire [2:0]M_AXI_GP1_ARPROT; + wire [3:0]M_AXI_GP1_ARQOS; + wire M_AXI_GP1_ARREADY; + wire [1:0]\^M_AXI_GP1_ARSIZE ; + wire M_AXI_GP1_ARVALID; + wire [31:0]M_AXI_GP1_AWADDR; + wire [1:0]M_AXI_GP1_AWBURST; + wire [3:0]\^M_AXI_GP1_AWCACHE ; + wire [11:0]M_AXI_GP1_AWID; + wire [3:0]M_AXI_GP1_AWLEN; + wire [1:0]M_AXI_GP1_AWLOCK; + wire [2:0]M_AXI_GP1_AWPROT; + wire [3:0]M_AXI_GP1_AWQOS; + wire M_AXI_GP1_AWREADY; + wire [1:0]\^M_AXI_GP1_AWSIZE ; + wire M_AXI_GP1_AWVALID; + wire [11:0]M_AXI_GP1_BID; + wire M_AXI_GP1_BREADY; + wire [1:0]M_AXI_GP1_BRESP; + wire M_AXI_GP1_BVALID; + wire [31:0]M_AXI_GP1_RDATA; + wire [11:0]M_AXI_GP1_RID; + wire M_AXI_GP1_RLAST; + wire M_AXI_GP1_RREADY; + wire [1:0]M_AXI_GP1_RRESP; + wire M_AXI_GP1_RVALID; + wire [31:0]M_AXI_GP1_WDATA; + wire [11:0]M_AXI_GP1_WID; + wire M_AXI_GP1_WLAST; + wire M_AXI_GP1_WREADY; + wire [3:0]M_AXI_GP1_WSTRB; + wire M_AXI_GP1_WVALID; + wire PJTAG_TCK; + wire PJTAG_TDI; + wire PJTAG_TMS; + wire PS_CLK; + wire PS_PORB; + wire PS_SRSTB; + wire SDIO0_BUSPOW; + wire [2:0]SDIO0_BUSVOLT; + wire SDIO0_CDN; + wire SDIO0_CLK; + wire SDIO0_CLK_FB; + wire SDIO0_CMD_I; + wire SDIO0_CMD_O; + wire SDIO0_CMD_T; + wire SDIO0_CMD_T_n; + wire [3:0]SDIO0_DATA_I; + wire [3:0]SDIO0_DATA_O; + wire [3:0]SDIO0_DATA_T; + wire [3:0]SDIO0_DATA_T_n; + wire SDIO0_LED; + wire SDIO0_WP; + wire SDIO1_BUSPOW; + wire [2:0]SDIO1_BUSVOLT; + wire SDIO1_CDN; + wire SDIO1_CLK; + wire SDIO1_CLK_FB; + wire SDIO1_CMD_I; + wire SDIO1_CMD_O; + wire SDIO1_CMD_T; + wire SDIO1_CMD_T_n; + wire [3:0]SDIO1_DATA_I; + wire [3:0]SDIO1_DATA_O; + wire [3:0]SDIO1_DATA_T; + wire [3:0]SDIO1_DATA_T_n; + wire SDIO1_LED; + wire SDIO1_WP; + wire SPI0_MISO_I; + wire SPI0_MISO_O; + wire SPI0_MISO_T; + wire SPI0_MISO_T_n; + wire SPI0_MOSI_I; + wire SPI0_MOSI_O; + wire SPI0_MOSI_T; + wire SPI0_MOSI_T_n; + wire SPI0_SCLK_I; + wire SPI0_SCLK_O; + wire SPI0_SCLK_T; + wire SPI0_SCLK_T_n; + wire SPI0_SS1_O; + wire SPI0_SS2_O; + wire SPI0_SS_I; + wire SPI0_SS_O; + wire SPI0_SS_T; + wire SPI0_SS_T_n; + wire SPI1_MISO_I; + wire SPI1_MISO_O; + wire SPI1_MISO_T; + wire SPI1_MISO_T_n; + wire SPI1_MOSI_I; + wire SPI1_MOSI_O; + wire SPI1_MOSI_T; + wire SPI1_MOSI_T_n; + wire SPI1_SCLK_I; + wire SPI1_SCLK_O; + wire SPI1_SCLK_T; + wire SPI1_SCLK_T_n; + wire SPI1_SS1_O; + wire SPI1_SS2_O; + wire SPI1_SS_I; + wire SPI1_SS_O; + wire SPI1_SS_T; + wire SPI1_SS_T_n; + wire SRAM_INTIN; + wire S_AXI_ACP_ACLK; + wire [31:0]S_AXI_ACP_ARADDR; + wire [1:0]S_AXI_ACP_ARBURST; + wire [3:0]S_AXI_ACP_ARCACHE; + wire S_AXI_ACP_ARESETN; + wire [2:0]S_AXI_ACP_ARID; + wire [3:0]S_AXI_ACP_ARLEN; + wire [1:0]S_AXI_ACP_ARLOCK; + wire [2:0]S_AXI_ACP_ARPROT; + wire [3:0]S_AXI_ACP_ARQOS; + wire S_AXI_ACP_ARREADY; + wire [2:0]S_AXI_ACP_ARSIZE; + wire [4:0]S_AXI_ACP_ARUSER; + wire S_AXI_ACP_ARVALID; + wire [31:0]S_AXI_ACP_AWADDR; + wire [1:0]S_AXI_ACP_AWBURST; + wire [3:0]S_AXI_ACP_AWCACHE; + wire [2:0]S_AXI_ACP_AWID; + wire [3:0]S_AXI_ACP_AWLEN; + wire [1:0]S_AXI_ACP_AWLOCK; + wire [2:0]S_AXI_ACP_AWPROT; + wire [3:0]S_AXI_ACP_AWQOS; + wire S_AXI_ACP_AWREADY; + wire [2:0]S_AXI_ACP_AWSIZE; + wire [4:0]S_AXI_ACP_AWUSER; + wire S_AXI_ACP_AWVALID; + wire [2:0]S_AXI_ACP_BID; + wire S_AXI_ACP_BREADY; + wire [1:0]S_AXI_ACP_BRESP; + wire S_AXI_ACP_BVALID; + wire [63:0]S_AXI_ACP_RDATA; + wire [2:0]S_AXI_ACP_RID; + wire S_AXI_ACP_RLAST; + wire S_AXI_ACP_RREADY; + wire [1:0]S_AXI_ACP_RRESP; + wire S_AXI_ACP_RVALID; + wire [63:0]S_AXI_ACP_WDATA; + wire [2:0]S_AXI_ACP_WID; + wire S_AXI_ACP_WLAST; + wire S_AXI_ACP_WREADY; + wire [7:0]S_AXI_ACP_WSTRB; + wire S_AXI_ACP_WVALID; + wire S_AXI_GP0_ACLK; + wire [31:0]S_AXI_GP0_ARADDR; + wire [1:0]S_AXI_GP0_ARBURST; + wire [3:0]S_AXI_GP0_ARCACHE; + wire S_AXI_GP0_ARESETN; + wire [5:0]S_AXI_GP0_ARID; + wire [3:0]S_AXI_GP0_ARLEN; + wire [1:0]S_AXI_GP0_ARLOCK; + wire [2:0]S_AXI_GP0_ARPROT; + wire [3:0]S_AXI_GP0_ARQOS; + wire S_AXI_GP0_ARREADY; + wire [2:0]S_AXI_GP0_ARSIZE; + wire S_AXI_GP0_ARVALID; + wire [31:0]S_AXI_GP0_AWADDR; + wire [1:0]S_AXI_GP0_AWBURST; + wire [3:0]S_AXI_GP0_AWCACHE; + wire [5:0]S_AXI_GP0_AWID; + wire [3:0]S_AXI_GP0_AWLEN; + wire [1:0]S_AXI_GP0_AWLOCK; + wire [2:0]S_AXI_GP0_AWPROT; + wire [3:0]S_AXI_GP0_AWQOS; + wire S_AXI_GP0_AWREADY; + wire [2:0]S_AXI_GP0_AWSIZE; + wire S_AXI_GP0_AWVALID; + wire [5:0]S_AXI_GP0_BID; + wire S_AXI_GP0_BREADY; + wire [1:0]S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire [31:0]S_AXI_GP0_RDATA; + wire [5:0]S_AXI_GP0_RID; + wire S_AXI_GP0_RLAST; + wire S_AXI_GP0_RREADY; + wire [1:0]S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire [31:0]S_AXI_GP0_WDATA; + wire [5:0]S_AXI_GP0_WID; + wire S_AXI_GP0_WLAST; + wire S_AXI_GP0_WREADY; + wire [3:0]S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP1_ACLK; + wire [31:0]S_AXI_GP1_ARADDR; + wire [1:0]S_AXI_GP1_ARBURST; + wire [3:0]S_AXI_GP1_ARCACHE; + wire S_AXI_GP1_ARESETN; + wire [5:0]S_AXI_GP1_ARID; + wire [3:0]S_AXI_GP1_ARLEN; + wire [1:0]S_AXI_GP1_ARLOCK; + wire [2:0]S_AXI_GP1_ARPROT; + wire [3:0]S_AXI_GP1_ARQOS; + wire S_AXI_GP1_ARREADY; + wire [2:0]S_AXI_GP1_ARSIZE; + wire S_AXI_GP1_ARVALID; + wire [31:0]S_AXI_GP1_AWADDR; + wire [1:0]S_AXI_GP1_AWBURST; + wire [3:0]S_AXI_GP1_AWCACHE; + wire [5:0]S_AXI_GP1_AWID; + wire [3:0]S_AXI_GP1_AWLEN; + wire [1:0]S_AXI_GP1_AWLOCK; + wire [2:0]S_AXI_GP1_AWPROT; + wire [3:0]S_AXI_GP1_AWQOS; + wire S_AXI_GP1_AWREADY; + wire [2:0]S_AXI_GP1_AWSIZE; + wire S_AXI_GP1_AWVALID; + wire [5:0]S_AXI_GP1_BID; + wire S_AXI_GP1_BREADY; + wire [1:0]S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire [31:0]S_AXI_GP1_RDATA; + wire [5:0]S_AXI_GP1_RID; + wire S_AXI_GP1_RLAST; + wire S_AXI_GP1_RREADY; + wire [1:0]S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire [31:0]S_AXI_GP1_WDATA; + wire [5:0]S_AXI_GP1_WID; + wire S_AXI_GP1_WLAST; + wire S_AXI_GP1_WREADY; + wire [3:0]S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_HP0_ACLK; + wire [31:0]S_AXI_HP0_ARADDR; + wire [1:0]S_AXI_HP0_ARBURST; + wire [3:0]S_AXI_HP0_ARCACHE; + wire S_AXI_HP0_ARESETN; + wire [5:0]S_AXI_HP0_ARID; + wire [3:0]S_AXI_HP0_ARLEN; + wire [1:0]S_AXI_HP0_ARLOCK; + wire [2:0]S_AXI_HP0_ARPROT; + wire [3:0]S_AXI_HP0_ARQOS; + wire S_AXI_HP0_ARREADY; + wire [2:0]S_AXI_HP0_ARSIZE; + wire S_AXI_HP0_ARVALID; + wire [31:0]S_AXI_HP0_AWADDR; + wire [1:0]S_AXI_HP0_AWBURST; + wire [3:0]S_AXI_HP0_AWCACHE; + wire [5:0]S_AXI_HP0_AWID; + wire [3:0]S_AXI_HP0_AWLEN; + wire [1:0]S_AXI_HP0_AWLOCK; + wire [2:0]S_AXI_HP0_AWPROT; + wire [3:0]S_AXI_HP0_AWQOS; + wire S_AXI_HP0_AWREADY; + wire [2:0]S_AXI_HP0_AWSIZE; + wire S_AXI_HP0_AWVALID; + wire [5:0]S_AXI_HP0_BID; + wire S_AXI_HP0_BREADY; + wire [1:0]S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire [2:0]S_AXI_HP0_RACOUNT; + wire [7:0]S_AXI_HP0_RCOUNT; + wire [63:0]S_AXI_HP0_RDATA; + wire S_AXI_HP0_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP0_RID; + wire S_AXI_HP0_RLAST; + wire S_AXI_HP0_RREADY; + wire [1:0]S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire [5:0]S_AXI_HP0_WACOUNT; + wire [7:0]S_AXI_HP0_WCOUNT; + wire [63:0]S_AXI_HP0_WDATA; + wire [5:0]S_AXI_HP0_WID; + wire S_AXI_HP0_WLAST; + wire S_AXI_HP0_WREADY; + wire S_AXI_HP0_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP1_ACLK; + wire [31:0]S_AXI_HP1_ARADDR; + wire [1:0]S_AXI_HP1_ARBURST; + wire [3:0]S_AXI_HP1_ARCACHE; + wire S_AXI_HP1_ARESETN; + wire [5:0]S_AXI_HP1_ARID; + wire [3:0]S_AXI_HP1_ARLEN; + wire [1:0]S_AXI_HP1_ARLOCK; + wire [2:0]S_AXI_HP1_ARPROT; + wire [3:0]S_AXI_HP1_ARQOS; + wire S_AXI_HP1_ARREADY; + wire [2:0]S_AXI_HP1_ARSIZE; + wire S_AXI_HP1_ARVALID; + wire [31:0]S_AXI_HP1_AWADDR; + wire [1:0]S_AXI_HP1_AWBURST; + wire [3:0]S_AXI_HP1_AWCACHE; + wire [5:0]S_AXI_HP1_AWID; + wire [3:0]S_AXI_HP1_AWLEN; + wire [1:0]S_AXI_HP1_AWLOCK; + wire [2:0]S_AXI_HP1_AWPROT; + wire [3:0]S_AXI_HP1_AWQOS; + wire S_AXI_HP1_AWREADY; + wire [2:0]S_AXI_HP1_AWSIZE; + wire S_AXI_HP1_AWVALID; + wire [5:0]S_AXI_HP1_BID; + wire S_AXI_HP1_BREADY; + wire [1:0]S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire [2:0]S_AXI_HP1_RACOUNT; + wire [7:0]S_AXI_HP1_RCOUNT; + wire [63:0]S_AXI_HP1_RDATA; + wire S_AXI_HP1_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP1_RID; + wire S_AXI_HP1_RLAST; + wire S_AXI_HP1_RREADY; + wire [1:0]S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire [5:0]S_AXI_HP1_WACOUNT; + wire [7:0]S_AXI_HP1_WCOUNT; + wire [63:0]S_AXI_HP1_WDATA; + wire [5:0]S_AXI_HP1_WID; + wire S_AXI_HP1_WLAST; + wire S_AXI_HP1_WREADY; + wire S_AXI_HP1_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP2_ACLK; + wire [31:0]S_AXI_HP2_ARADDR; + wire [1:0]S_AXI_HP2_ARBURST; + wire [3:0]S_AXI_HP2_ARCACHE; + wire S_AXI_HP2_ARESETN; + wire [5:0]S_AXI_HP2_ARID; + wire [3:0]S_AXI_HP2_ARLEN; + wire [1:0]S_AXI_HP2_ARLOCK; + wire [2:0]S_AXI_HP2_ARPROT; + wire [3:0]S_AXI_HP2_ARQOS; + wire S_AXI_HP2_ARREADY; + wire [2:0]S_AXI_HP2_ARSIZE; + wire S_AXI_HP2_ARVALID; + wire [31:0]S_AXI_HP2_AWADDR; + wire [1:0]S_AXI_HP2_AWBURST; + wire [3:0]S_AXI_HP2_AWCACHE; + wire [5:0]S_AXI_HP2_AWID; + wire [3:0]S_AXI_HP2_AWLEN; + wire [1:0]S_AXI_HP2_AWLOCK; + wire [2:0]S_AXI_HP2_AWPROT; + wire [3:0]S_AXI_HP2_AWQOS; + wire S_AXI_HP2_AWREADY; + wire [2:0]S_AXI_HP2_AWSIZE; + wire S_AXI_HP2_AWVALID; + wire [5:0]S_AXI_HP2_BID; + wire S_AXI_HP2_BREADY; + wire [1:0]S_AXI_HP2_BRESP; + wire S_AXI_HP2_BVALID; + wire [2:0]S_AXI_HP2_RACOUNT; + wire [7:0]S_AXI_HP2_RCOUNT; + wire [63:0]S_AXI_HP2_RDATA; + wire S_AXI_HP2_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP2_RID; + wire S_AXI_HP2_RLAST; + wire S_AXI_HP2_RREADY; + wire [1:0]S_AXI_HP2_RRESP; + wire S_AXI_HP2_RVALID; + wire [5:0]S_AXI_HP2_WACOUNT; + wire [7:0]S_AXI_HP2_WCOUNT; + wire [63:0]S_AXI_HP2_WDATA; + wire [5:0]S_AXI_HP2_WID; + wire S_AXI_HP2_WLAST; + wire S_AXI_HP2_WREADY; + wire S_AXI_HP2_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP2_WSTRB; + wire S_AXI_HP2_WVALID; + wire S_AXI_HP3_ACLK; + wire [31:0]S_AXI_HP3_ARADDR; + wire [1:0]S_AXI_HP3_ARBURST; + wire [3:0]S_AXI_HP3_ARCACHE; + wire S_AXI_HP3_ARESETN; + wire [5:0]S_AXI_HP3_ARID; + wire [3:0]S_AXI_HP3_ARLEN; + wire [1:0]S_AXI_HP3_ARLOCK; + wire [2:0]S_AXI_HP3_ARPROT; + wire [3:0]S_AXI_HP3_ARQOS; + wire S_AXI_HP3_ARREADY; + wire [2:0]S_AXI_HP3_ARSIZE; + wire S_AXI_HP3_ARVALID; + wire [31:0]S_AXI_HP3_AWADDR; + wire [1:0]S_AXI_HP3_AWBURST; + wire [3:0]S_AXI_HP3_AWCACHE; + wire [5:0]S_AXI_HP3_AWID; + wire [3:0]S_AXI_HP3_AWLEN; + wire [1:0]S_AXI_HP3_AWLOCK; + wire [2:0]S_AXI_HP3_AWPROT; + wire [3:0]S_AXI_HP3_AWQOS; + wire S_AXI_HP3_AWREADY; + wire [2:0]S_AXI_HP3_AWSIZE; + wire S_AXI_HP3_AWVALID; + wire [5:0]S_AXI_HP3_BID; + wire S_AXI_HP3_BREADY; + wire [1:0]S_AXI_HP3_BRESP; + wire S_AXI_HP3_BVALID; + wire [2:0]S_AXI_HP3_RACOUNT; + wire [7:0]S_AXI_HP3_RCOUNT; + wire [63:0]S_AXI_HP3_RDATA; + wire S_AXI_HP3_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP3_RID; + wire S_AXI_HP3_RLAST; + wire S_AXI_HP3_RREADY; + wire [1:0]S_AXI_HP3_RRESP; + wire S_AXI_HP3_RVALID; + wire [5:0]S_AXI_HP3_WACOUNT; + wire [7:0]S_AXI_HP3_WCOUNT; + wire [63:0]S_AXI_HP3_WDATA; + wire [5:0]S_AXI_HP3_WID; + wire S_AXI_HP3_WLAST; + wire S_AXI_HP3_WREADY; + wire S_AXI_HP3_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP3_WSTRB; + wire S_AXI_HP3_WVALID; + wire TRACE_CLK; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ; + wire TTC0_CLK0_IN; + wire TTC0_CLK1_IN; + wire TTC0_CLK2_IN; + wire TTC0_WAVE0_OUT; + wire TTC0_WAVE1_OUT; + wire TTC0_WAVE2_OUT; + wire TTC1_CLK0_IN; + wire TTC1_CLK1_IN; + wire TTC1_CLK2_IN; + wire TTC1_WAVE0_OUT; + wire TTC1_WAVE1_OUT; + wire TTC1_WAVE2_OUT; + wire UART0_CTSN; + wire UART0_DCDN; + wire UART0_DSRN; + wire UART0_DTRN; + wire UART0_RIN; + wire UART0_RTSN; + wire UART0_RX; + wire UART0_TX; + wire UART1_CTSN; + wire UART1_DCDN; + wire UART1_DSRN; + wire UART1_DTRN; + wire UART1_RIN; + wire UART1_RTSN; + wire UART1_RX; + wire UART1_TX; + wire [1:0]USB0_PORT_INDCTL; + wire USB0_VBUS_PWRFAULT; + wire USB0_VBUS_PWRSELECT; + wire [1:0]USB1_PORT_INDCTL; + wire USB1_VBUS_PWRFAULT; + wire USB1_VBUS_PWRSELECT; + wire WDT_CLK_IN; + wire WDT_RST_OUT; + wire [14:0]buffered_DDR_Addr; + wire [2:0]buffered_DDR_BankAddr; + wire buffered_DDR_CAS_n; + wire buffered_DDR_CKE; + wire buffered_DDR_CS_n; + wire buffered_DDR_Clk; + wire buffered_DDR_Clk_n; + wire [1:0]buffered_DDR_DM; + wire [15:0]buffered_DDR_DQ; + wire [1:0]buffered_DDR_DQS; + wire [1:0]buffered_DDR_DQS_n; + wire buffered_DDR_DRSTB; + wire buffered_DDR_ODT; + wire buffered_DDR_RAS_n; + wire buffered_DDR_VRN; + wire buffered_DDR_VRP; + wire buffered_DDR_WEB; + wire [31:0]buffered_MIO; + wire buffered_PS_CLK; + wire buffered_PS_PORB; + wire buffered_PS_SRSTB; + wire [63:0]gpio_out_t_n; + wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED; + wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED; + wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED; + wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED; + wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED; + wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED; + wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED; + wire [3:2]NLW_PS7_i_DDRDM_UNCONNECTED; + wire [31:16]NLW_PS7_i_DDRDQ_UNCONNECTED; + wire [3:2]NLW_PS7_i_DDRDQSN_UNCONNECTED; + wire [3:2]NLW_PS7_i_DDRDQSP_UNCONNECTED; + wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED; + wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED; + wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED; + wire [51:16]NLW_PS7_i_MIO_UNCONNECTED; + + assign ENET0_GMII_TXD[7] = \ ; + assign ENET0_GMII_TXD[6] = \ ; + assign ENET0_GMII_TXD[5] = \ ; + assign ENET0_GMII_TXD[4] = \ ; + assign ENET0_GMII_TXD[3] = \ ; + assign ENET0_GMII_TXD[2] = \ ; + assign ENET0_GMII_TXD[1] = \ ; + assign ENET0_GMII_TXD[0] = \ ; + assign ENET0_GMII_TX_EN = \ ; + assign ENET0_GMII_TX_ER = \ ; + assign ENET1_GMII_TXD[7] = \ ; + assign ENET1_GMII_TXD[6] = \ ; + assign ENET1_GMII_TXD[5] = \ ; + assign ENET1_GMII_TXD[4] = \ ; + assign ENET1_GMII_TXD[3] = \ ; + assign ENET1_GMII_TXD[2] = \ ; + assign ENET1_GMII_TXD[1] = \ ; + assign ENET1_GMII_TXD[0] = \ ; + assign ENET1_GMII_TX_EN = \ ; + assign ENET1_GMII_TX_ER = \ ; + assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2]; + assign M_AXI_GP0_ARCACHE[1] = \ ; + assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0]; + assign M_AXI_GP0_ARSIZE[2] = \ ; + assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0]; + assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2]; + assign M_AXI_GP0_AWCACHE[1] = \ ; + assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0]; + assign M_AXI_GP0_AWSIZE[2] = \ ; + assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0]; + assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2]; + assign M_AXI_GP1_ARCACHE[1] = \ ; + assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0]; + assign M_AXI_GP1_ARSIZE[2] = \ ; + assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0]; + assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2]; + assign M_AXI_GP1_AWCACHE[1] = \ ; + assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0]; + assign M_AXI_GP1_AWSIZE[2] = \ ; + assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0]; + assign PJTAG_TDO = \ ; + assign TRACE_CLK_OUT = \ ; + assign TRACE_CTL = \TRACE_CTL_PIPE[0] ; + assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ; + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CAS_n_BIBUF + (.IO(buffered_DDR_CAS_n), + .PAD(DDR_CAS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CKE_BIBUF + (.IO(buffered_DDR_CKE), + .PAD(DDR_CKE)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CS_n_BIBUF + (.IO(buffered_DDR_CS_n), + .PAD(DDR_CS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_Clk_BIBUF + (.IO(buffered_DDR_Clk), + .PAD(DDR_Clk)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_Clk_n_BIBUF + (.IO(buffered_DDR_Clk_n), + .PAD(DDR_Clk_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_DRSTB_BIBUF + (.IO(buffered_DDR_DRSTB), + .PAD(DDR_DRSTB)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_ODT_BIBUF + (.IO(buffered_DDR_ODT), + .PAD(DDR_ODT)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_RAS_n_BIBUF + (.IO(buffered_DDR_RAS_n), + .PAD(DDR_RAS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_VRN_BIBUF + (.IO(buffered_DDR_VRN), + .PAD(DDR_VRN)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_VRP_BIBUF + (.IO(buffered_DDR_VRP), + .PAD(DDR_VRP)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_WEB_BIBUF + (.IO(buffered_DDR_WEB), + .PAD(DDR_WEB)); + LUT1 #( + .INIT(2'h1)) + ENET0_MDIO_T_INST_0 + (.I0(ENET0_MDIO_T_n), + .O(ENET0_MDIO_T)); + LUT1 #( + .INIT(2'h1)) + ENET1_MDIO_T_INST_0 + (.I0(ENET1_MDIO_T_n), + .O(ENET1_MDIO_T)); + GND GND + (.G(\ )); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[0]_INST_0 + (.I0(gpio_out_t_n[0]), + .O(GPIO_T[0])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[10]_INST_0 + (.I0(gpio_out_t_n[10]), + .O(GPIO_T[10])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[11]_INST_0 + (.I0(gpio_out_t_n[11]), + .O(GPIO_T[11])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[12]_INST_0 + (.I0(gpio_out_t_n[12]), + .O(GPIO_T[12])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[13]_INST_0 + (.I0(gpio_out_t_n[13]), + .O(GPIO_T[13])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[14]_INST_0 + (.I0(gpio_out_t_n[14]), + .O(GPIO_T[14])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[15]_INST_0 + (.I0(gpio_out_t_n[15]), + .O(GPIO_T[15])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[16]_INST_0 + (.I0(gpio_out_t_n[16]), + .O(GPIO_T[16])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[17]_INST_0 + (.I0(gpio_out_t_n[17]), + .O(GPIO_T[17])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[18]_INST_0 + (.I0(gpio_out_t_n[18]), + .O(GPIO_T[18])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[19]_INST_0 + (.I0(gpio_out_t_n[19]), + .O(GPIO_T[19])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[1]_INST_0 + (.I0(gpio_out_t_n[1]), + .O(GPIO_T[1])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[20]_INST_0 + (.I0(gpio_out_t_n[20]), + .O(GPIO_T[20])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[21]_INST_0 + (.I0(gpio_out_t_n[21]), + .O(GPIO_T[21])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[22]_INST_0 + (.I0(gpio_out_t_n[22]), + .O(GPIO_T[22])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[23]_INST_0 + (.I0(gpio_out_t_n[23]), + .O(GPIO_T[23])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[24]_INST_0 + (.I0(gpio_out_t_n[24]), + .O(GPIO_T[24])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[25]_INST_0 + (.I0(gpio_out_t_n[25]), + .O(GPIO_T[25])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[26]_INST_0 + (.I0(gpio_out_t_n[26]), + .O(GPIO_T[26])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[27]_INST_0 + (.I0(gpio_out_t_n[27]), + .O(GPIO_T[27])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[28]_INST_0 + (.I0(gpio_out_t_n[28]), + .O(GPIO_T[28])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[29]_INST_0 + (.I0(gpio_out_t_n[29]), + .O(GPIO_T[29])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[2]_INST_0 + (.I0(gpio_out_t_n[2]), + .O(GPIO_T[2])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[30]_INST_0 + (.I0(gpio_out_t_n[30]), + .O(GPIO_T[30])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[31]_INST_0 + (.I0(gpio_out_t_n[31]), + .O(GPIO_T[31])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[32]_INST_0 + (.I0(gpio_out_t_n[32]), + .O(GPIO_T[32])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[33]_INST_0 + (.I0(gpio_out_t_n[33]), + .O(GPIO_T[33])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[34]_INST_0 + (.I0(gpio_out_t_n[34]), + .O(GPIO_T[34])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[35]_INST_0 + (.I0(gpio_out_t_n[35]), + .O(GPIO_T[35])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[36]_INST_0 + (.I0(gpio_out_t_n[36]), + .O(GPIO_T[36])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[37]_INST_0 + (.I0(gpio_out_t_n[37]), + .O(GPIO_T[37])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[38]_INST_0 + (.I0(gpio_out_t_n[38]), + .O(GPIO_T[38])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[39]_INST_0 + (.I0(gpio_out_t_n[39]), + .O(GPIO_T[39])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[3]_INST_0 + (.I0(gpio_out_t_n[3]), + .O(GPIO_T[3])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[40]_INST_0 + (.I0(gpio_out_t_n[40]), + .O(GPIO_T[40])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[41]_INST_0 + (.I0(gpio_out_t_n[41]), + .O(GPIO_T[41])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[42]_INST_0 + (.I0(gpio_out_t_n[42]), + .O(GPIO_T[42])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[43]_INST_0 + (.I0(gpio_out_t_n[43]), + .O(GPIO_T[43])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[44]_INST_0 + (.I0(gpio_out_t_n[44]), + .O(GPIO_T[44])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[45]_INST_0 + (.I0(gpio_out_t_n[45]), + .O(GPIO_T[45])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[46]_INST_0 + (.I0(gpio_out_t_n[46]), + .O(GPIO_T[46])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[47]_INST_0 + (.I0(gpio_out_t_n[47]), + .O(GPIO_T[47])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[48]_INST_0 + (.I0(gpio_out_t_n[48]), + .O(GPIO_T[48])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[49]_INST_0 + (.I0(gpio_out_t_n[49]), + .O(GPIO_T[49])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[4]_INST_0 + (.I0(gpio_out_t_n[4]), + .O(GPIO_T[4])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[50]_INST_0 + (.I0(gpio_out_t_n[50]), + .O(GPIO_T[50])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[51]_INST_0 + (.I0(gpio_out_t_n[51]), + .O(GPIO_T[51])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[52]_INST_0 + (.I0(gpio_out_t_n[52]), + .O(GPIO_T[52])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[53]_INST_0 + (.I0(gpio_out_t_n[53]), + .O(GPIO_T[53])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[54]_INST_0 + (.I0(gpio_out_t_n[54]), + .O(GPIO_T[54])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[55]_INST_0 + (.I0(gpio_out_t_n[55]), + .O(GPIO_T[55])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[56]_INST_0 + (.I0(gpio_out_t_n[56]), + .O(GPIO_T[56])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[57]_INST_0 + (.I0(gpio_out_t_n[57]), + .O(GPIO_T[57])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[58]_INST_0 + (.I0(gpio_out_t_n[58]), + .O(GPIO_T[58])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[59]_INST_0 + (.I0(gpio_out_t_n[59]), + .O(GPIO_T[59])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[5]_INST_0 + (.I0(gpio_out_t_n[5]), + .O(GPIO_T[5])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[60]_INST_0 + (.I0(gpio_out_t_n[60]), + .O(GPIO_T[60])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[61]_INST_0 + (.I0(gpio_out_t_n[61]), + .O(GPIO_T[61])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[62]_INST_0 + (.I0(gpio_out_t_n[62]), + .O(GPIO_T[62])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[63]_INST_0 + (.I0(gpio_out_t_n[63]), + .O(GPIO_T[63])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[6]_INST_0 + (.I0(gpio_out_t_n[6]), + .O(GPIO_T[6])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[7]_INST_0 + (.I0(gpio_out_t_n[7]), + .O(GPIO_T[7])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[8]_INST_0 + (.I0(gpio_out_t_n[8]), + .O(GPIO_T[8])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[9]_INST_0 + (.I0(gpio_out_t_n[9]), + .O(GPIO_T[9])); + LUT1 #( + .INIT(2'h1)) + I2C0_SCL_T_INST_0 + (.I0(I2C0_SCL_T_n), + .O(I2C0_SCL_T)); + LUT1 #( + .INIT(2'h1)) + I2C0_SDA_T_INST_0 + (.I0(I2C0_SDA_T_n), + .O(I2C0_SDA_T)); + LUT1 #( + .INIT(2'h1)) + I2C1_SCL_T_INST_0 + (.I0(I2C1_SCL_T_n), + .O(I2C1_SCL_T)); + LUT1 #( + .INIT(2'h1)) + I2C1_SDA_T_INST_0 + (.I0(I2C1_SDA_T_n), + .O(I2C1_SDA_T)); + (* BOX_TYPE = "PRIMITIVE" *) + PS7 PS7_i + (.DDRA(buffered_DDR_Addr), + .DDRARB(DDR_ARB), + .DDRBA(buffered_DDR_BankAddr), + .DDRCASB(buffered_DDR_CAS_n), + .DDRCKE(buffered_DDR_CKE), + .DDRCKN(buffered_DDR_Clk_n), + .DDRCKP(buffered_DDR_Clk), + .DDRCSB(buffered_DDR_CS_n), + .DDRDM({NLW_PS7_i_DDRDM_UNCONNECTED[3:2],buffered_DDR_DM}), + .DDRDQ({NLW_PS7_i_DDRDQ_UNCONNECTED[31:16],buffered_DDR_DQ}), + .DDRDQSN({NLW_PS7_i_DDRDQSN_UNCONNECTED[3:2],buffered_DDR_DQS_n}), + .DDRDQSP({NLW_PS7_i_DDRDQSP_UNCONNECTED[3:2],buffered_DDR_DQS}), + .DDRDRSTB(buffered_DDR_DRSTB), + .DDRODT(buffered_DDR_ODT), + .DDRRASB(buffered_DDR_RAS_n), + .DDRVRN(buffered_DDR_VRN), + .DDRVRP(buffered_DDR_VRP), + .DDRWEB(buffered_DDR_WEB), + .DMA0ACLK(DMA0_ACLK), + .DMA0DAREADY(DMA0_DAREADY), + .DMA0DATYPE(DMA0_DATYPE), + .DMA0DAVALID(DMA0_DAVALID), + .DMA0DRLAST(DMA0_DRLAST), + .DMA0DRREADY(DMA0_DRREADY), + .DMA0DRTYPE(DMA0_DRTYPE), + .DMA0DRVALID(DMA0_DRVALID), + .DMA0RSTN(DMA0_RSTN), + .DMA1ACLK(DMA1_ACLK), + .DMA1DAREADY(DMA1_DAREADY), + .DMA1DATYPE(DMA1_DATYPE), + .DMA1DAVALID(DMA1_DAVALID), + .DMA1DRLAST(DMA1_DRLAST), + .DMA1DRREADY(DMA1_DRREADY), + .DMA1DRTYPE(DMA1_DRTYPE), + .DMA1DRVALID(DMA1_DRVALID), + .DMA1RSTN(DMA1_RSTN), + .DMA2ACLK(DMA2_ACLK), + .DMA2DAREADY(DMA2_DAREADY), + .DMA2DATYPE(DMA2_DATYPE), + .DMA2DAVALID(DMA2_DAVALID), + .DMA2DRLAST(DMA2_DRLAST), + .DMA2DRREADY(DMA2_DRREADY), + .DMA2DRTYPE(DMA2_DRTYPE), + .DMA2DRVALID(DMA2_DRVALID), + .DMA2RSTN(DMA2_RSTN), + .DMA3ACLK(DMA3_ACLK), + .DMA3DAREADY(DMA3_DAREADY), + .DMA3DATYPE(DMA3_DATYPE), + .DMA3DAVALID(DMA3_DAVALID), + .DMA3DRLAST(DMA3_DRLAST), + .DMA3DRREADY(DMA3_DRREADY), + .DMA3DRTYPE(DMA3_DRTYPE), + .DMA3DRVALID(DMA3_DRVALID), + .DMA3RSTN(DMA3_RSTN), + .EMIOCAN0PHYRX(CAN0_PHY_RX), + .EMIOCAN0PHYTX(CAN0_PHY_TX), + .EMIOCAN1PHYRX(CAN1_PHY_RX), + .EMIOCAN1PHYTX(CAN1_PHY_TX), + .EMIOENET0EXTINTIN(ENET0_EXT_INTIN), + .EMIOENET0GMIICOL(1'b0), + .EMIOENET0GMIICRS(1'b0), + .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK), + .EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOENET0GMIIRXDV(1'b0), + .EMIOENET0GMIIRXER(1'b0), + .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK), + .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]), + .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED), + .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED), + .EMIOENET0MDIOI(ENET0_MDIO_I), + .EMIOENET0MDIOMDC(ENET0_MDIO_MDC), + .EMIOENET0MDIOO(ENET0_MDIO_O), + .EMIOENET0MDIOTN(ENET0_MDIO_T_n), + .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX), + .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX), + .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX), + .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX), + .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), + .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), + .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX), + .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX), + .EMIOENET0SOFRX(ENET0_SOF_RX), + .EMIOENET0SOFTX(ENET0_SOF_TX), + .EMIOENET1EXTINTIN(ENET1_EXT_INTIN), + .EMIOENET1GMIICOL(1'b0), + .EMIOENET1GMIICRS(1'b0), + .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK), + .EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOENET1GMIIRXDV(1'b0), + .EMIOENET1GMIIRXER(1'b0), + .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK), + .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]), + .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED), + .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED), + .EMIOENET1MDIOI(ENET1_MDIO_I), + .EMIOENET1MDIOMDC(ENET1_MDIO_MDC), + .EMIOENET1MDIOO(ENET1_MDIO_O), + .EMIOENET1MDIOTN(ENET1_MDIO_T_n), + .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX), + .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX), + .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX), + .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX), + .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), + .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), + .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX), + .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX), + .EMIOENET1SOFRX(ENET1_SOF_RX), + .EMIOENET1SOFTX(ENET1_SOF_TX), + .EMIOGPIOI(GPIO_I), + .EMIOGPIOO(GPIO_O), + .EMIOGPIOTN(gpio_out_t_n), + .EMIOI2C0SCLI(I2C0_SCL_I), + .EMIOI2C0SCLO(I2C0_SCL_O), + .EMIOI2C0SCLTN(I2C0_SCL_T_n), + .EMIOI2C0SDAI(I2C0_SDA_I), + .EMIOI2C0SDAO(I2C0_SDA_O), + .EMIOI2C0SDATN(I2C0_SDA_T_n), + .EMIOI2C1SCLI(I2C1_SCL_I), + .EMIOI2C1SCLO(I2C1_SCL_O), + .EMIOI2C1SCLTN(I2C1_SCL_T_n), + .EMIOI2C1SDAI(I2C1_SDA_I), + .EMIOI2C1SDAO(I2C1_SDA_O), + .EMIOI2C1SDATN(I2C1_SDA_T_n), + .EMIOPJTAGTCK(PJTAG_TCK), + .EMIOPJTAGTDI(PJTAG_TDI), + .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED), + .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED), + .EMIOPJTAGTMS(PJTAG_TMS), + .EMIOSDIO0BUSPOW(SDIO0_BUSPOW), + .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT), + .EMIOSDIO0CDN(SDIO0_CDN), + .EMIOSDIO0CLK(SDIO0_CLK), + .EMIOSDIO0CLKFB(SDIO0_CLK_FB), + .EMIOSDIO0CMDI(SDIO0_CMD_I), + .EMIOSDIO0CMDO(SDIO0_CMD_O), + .EMIOSDIO0CMDTN(SDIO0_CMD_T_n), + .EMIOSDIO0DATAI(SDIO0_DATA_I), + .EMIOSDIO0DATAO(SDIO0_DATA_O), + .EMIOSDIO0DATATN(SDIO0_DATA_T_n), + .EMIOSDIO0LED(SDIO0_LED), + .EMIOSDIO0WP(SDIO0_WP), + .EMIOSDIO1BUSPOW(SDIO1_BUSPOW), + .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT), + .EMIOSDIO1CDN(SDIO1_CDN), + .EMIOSDIO1CLK(SDIO1_CLK), + .EMIOSDIO1CLKFB(SDIO1_CLK_FB), + .EMIOSDIO1CMDI(SDIO1_CMD_I), + .EMIOSDIO1CMDO(SDIO1_CMD_O), + .EMIOSDIO1CMDTN(SDIO1_CMD_T_n), + .EMIOSDIO1DATAI(SDIO1_DATA_I), + .EMIOSDIO1DATAO(SDIO1_DATA_O), + .EMIOSDIO1DATATN(SDIO1_DATA_T_n), + .EMIOSDIO1LED(SDIO1_LED), + .EMIOSDIO1WP(SDIO1_WP), + .EMIOSPI0MI(SPI0_MISO_I), + .EMIOSPI0MO(SPI0_MOSI_O), + .EMIOSPI0MOTN(SPI0_MOSI_T_n), + .EMIOSPI0SCLKI(SPI0_SCLK_I), + .EMIOSPI0SCLKO(SPI0_SCLK_O), + .EMIOSPI0SCLKTN(SPI0_SCLK_T_n), + .EMIOSPI0SI(SPI0_MOSI_I), + .EMIOSPI0SO(SPI0_MISO_O), + .EMIOSPI0SSIN(SPI0_SS_I), + .EMIOSPI0SSNTN(SPI0_SS_T_n), + .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), + .EMIOSPI0STN(SPI0_MISO_T_n), + .EMIOSPI1MI(SPI1_MISO_I), + .EMIOSPI1MO(SPI1_MOSI_O), + .EMIOSPI1MOTN(SPI1_MOSI_T_n), + .EMIOSPI1SCLKI(SPI1_SCLK_I), + .EMIOSPI1SCLKO(SPI1_SCLK_O), + .EMIOSPI1SCLKTN(SPI1_SCLK_T_n), + .EMIOSPI1SI(SPI1_MOSI_I), + .EMIOSPI1SO(SPI1_MISO_O), + .EMIOSPI1SSIN(SPI1_SS_I), + .EMIOSPI1SSNTN(SPI1_SS_T_n), + .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), + .EMIOSPI1STN(SPI1_MISO_T_n), + .EMIOSRAMINTIN(SRAM_INTIN), + .EMIOTRACECLK(TRACE_CLK), + .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED), + .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]), + .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}), + .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), + .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}), + .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), + .EMIOUART0CTSN(UART0_CTSN), + .EMIOUART0DCDN(UART0_DCDN), + .EMIOUART0DSRN(UART0_DSRN), + .EMIOUART0DTRN(UART0_DTRN), + .EMIOUART0RIN(UART0_RIN), + .EMIOUART0RTSN(UART0_RTSN), + .EMIOUART0RX(UART0_RX), + .EMIOUART0TX(UART0_TX), + .EMIOUART1CTSN(UART1_CTSN), + .EMIOUART1DCDN(UART1_DCDN), + .EMIOUART1DSRN(UART1_DSRN), + .EMIOUART1DTRN(UART1_DTRN), + .EMIOUART1RIN(UART1_RIN), + .EMIOUART1RTSN(UART1_RTSN), + .EMIOUART1RX(UART1_RX), + .EMIOUART1TX(UART1_TX), + .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL), + .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT), + .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT), + .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL), + .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT), + .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT), + .EMIOWDTCLKI(WDT_CLK_IN), + .EMIOWDTRSTO(WDT_RST_OUT), + .EVENTEVENTI(EVENT_EVENTI), + .EVENTEVENTO(EVENT_EVENTO), + .EVENTSTANDBYWFE(EVENT_STANDBYWFE), + .EVENTSTANDBYWFI(EVENT_STANDBYWFI), + .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK_unbuffered}), + .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}), + .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), + .FPGAIDLEN(FPGA_IDLE_N), + .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}), + .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK), + .FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMDTRACEINVALID(1'b0), + .FTMTF2PDEBUG(FTMT_F2P_DEBUG), + .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), + .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), + .FTMTP2FDEBUG(FTMT_P2F_DEBUG), + .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), + .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), + .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}), + .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}), + .MAXIGP0ACLK(M_AXI_GP0_ACLK), + .MAXIGP0ARADDR(M_AXI_GP0_ARADDR), + .MAXIGP0ARBURST(M_AXI_GP0_ARBURST), + .MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ), + .MAXIGP0ARESETN(M_AXI_GP0_ARESETN), + .MAXIGP0ARID(M_AXI_GP0_ARID), + .MAXIGP0ARLEN(M_AXI_GP0_ARLEN), + .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK), + .MAXIGP0ARPROT(M_AXI_GP0_ARPROT), + .MAXIGP0ARQOS(M_AXI_GP0_ARQOS), + .MAXIGP0ARREADY(M_AXI_GP0_ARREADY), + .MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ), + .MAXIGP0ARVALID(M_AXI_GP0_ARVALID), + .MAXIGP0AWADDR(M_AXI_GP0_AWADDR), + .MAXIGP0AWBURST(M_AXI_GP0_AWBURST), + .MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ), + .MAXIGP0AWID(M_AXI_GP0_AWID), + .MAXIGP0AWLEN(M_AXI_GP0_AWLEN), + .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK), + .MAXIGP0AWPROT(M_AXI_GP0_AWPROT), + .MAXIGP0AWQOS(M_AXI_GP0_AWQOS), + .MAXIGP0AWREADY(M_AXI_GP0_AWREADY), + .MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ), + .MAXIGP0AWVALID(M_AXI_GP0_AWVALID), + .MAXIGP0BID(M_AXI_GP0_BID), + .MAXIGP0BREADY(M_AXI_GP0_BREADY), + .MAXIGP0BRESP(M_AXI_GP0_BRESP), + .MAXIGP0BVALID(M_AXI_GP0_BVALID), + .MAXIGP0RDATA(M_AXI_GP0_RDATA), + .MAXIGP0RID(M_AXI_GP0_RID), + .MAXIGP0RLAST(M_AXI_GP0_RLAST), + .MAXIGP0RREADY(M_AXI_GP0_RREADY), + .MAXIGP0RRESP(M_AXI_GP0_RRESP), + .MAXIGP0RVALID(M_AXI_GP0_RVALID), + .MAXIGP0WDATA(M_AXI_GP0_WDATA), + .MAXIGP0WID(M_AXI_GP0_WID), + .MAXIGP0WLAST(M_AXI_GP0_WLAST), + .MAXIGP0WREADY(M_AXI_GP0_WREADY), + .MAXIGP0WSTRB(M_AXI_GP0_WSTRB), + .MAXIGP0WVALID(M_AXI_GP0_WVALID), + .MAXIGP1ACLK(M_AXI_GP1_ACLK), + .MAXIGP1ARADDR(M_AXI_GP1_ARADDR), + .MAXIGP1ARBURST(M_AXI_GP1_ARBURST), + .MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ), + .MAXIGP1ARESETN(M_AXI_GP1_ARESETN), + .MAXIGP1ARID(M_AXI_GP1_ARID), + .MAXIGP1ARLEN(M_AXI_GP1_ARLEN), + .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK), + .MAXIGP1ARPROT(M_AXI_GP1_ARPROT), + .MAXIGP1ARQOS(M_AXI_GP1_ARQOS), + .MAXIGP1ARREADY(M_AXI_GP1_ARREADY), + .MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ), + .MAXIGP1ARVALID(M_AXI_GP1_ARVALID), + .MAXIGP1AWADDR(M_AXI_GP1_AWADDR), + .MAXIGP1AWBURST(M_AXI_GP1_AWBURST), + .MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ), + .MAXIGP1AWID(M_AXI_GP1_AWID), + .MAXIGP1AWLEN(M_AXI_GP1_AWLEN), + .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK), + .MAXIGP1AWPROT(M_AXI_GP1_AWPROT), + .MAXIGP1AWQOS(M_AXI_GP1_AWQOS), + .MAXIGP1AWREADY(M_AXI_GP1_AWREADY), + .MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ), + .MAXIGP1AWVALID(M_AXI_GP1_AWVALID), + .MAXIGP1BID(M_AXI_GP1_BID), + .MAXIGP1BREADY(M_AXI_GP1_BREADY), + .MAXIGP1BRESP(M_AXI_GP1_BRESP), + .MAXIGP1BVALID(M_AXI_GP1_BVALID), + .MAXIGP1RDATA(M_AXI_GP1_RDATA), + .MAXIGP1RID(M_AXI_GP1_RID), + .MAXIGP1RLAST(M_AXI_GP1_RLAST), + .MAXIGP1RREADY(M_AXI_GP1_RREADY), + .MAXIGP1RRESP(M_AXI_GP1_RRESP), + .MAXIGP1RVALID(M_AXI_GP1_RVALID), + .MAXIGP1WDATA(M_AXI_GP1_WDATA), + .MAXIGP1WID(M_AXI_GP1_WID), + .MAXIGP1WLAST(M_AXI_GP1_WLAST), + .MAXIGP1WREADY(M_AXI_GP1_WREADY), + .MAXIGP1WSTRB(M_AXI_GP1_WSTRB), + .MAXIGP1WVALID(M_AXI_GP1_WVALID), + .MIO({buffered_MIO[31:30],NLW_PS7_i_MIO_UNCONNECTED[51:50],buffered_MIO[29:28],NLW_PS7_i_MIO_UNCONNECTED[47:40],buffered_MIO[27:16],NLW_PS7_i_MIO_UNCONNECTED[27:16],buffered_MIO[15:0]}), + .PSCLK(buffered_PS_CLK), + .PSPORB(buffered_PS_PORB), + .PSSRSTB(buffered_PS_SRSTB), + .SAXIACPACLK(S_AXI_ACP_ACLK), + .SAXIACPARADDR(S_AXI_ACP_ARADDR), + .SAXIACPARBURST(S_AXI_ACP_ARBURST), + .SAXIACPARCACHE(S_AXI_ACP_ARCACHE), + .SAXIACPARESETN(S_AXI_ACP_ARESETN), + .SAXIACPARID(S_AXI_ACP_ARID), + .SAXIACPARLEN(S_AXI_ACP_ARLEN), + .SAXIACPARLOCK(S_AXI_ACP_ARLOCK), + .SAXIACPARPROT(S_AXI_ACP_ARPROT), + .SAXIACPARQOS(S_AXI_ACP_ARQOS), + .SAXIACPARREADY(S_AXI_ACP_ARREADY), + .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]), + .SAXIACPARUSER(S_AXI_ACP_ARUSER), + .SAXIACPARVALID(S_AXI_ACP_ARVALID), + .SAXIACPAWADDR(S_AXI_ACP_AWADDR), + .SAXIACPAWBURST(S_AXI_ACP_AWBURST), + .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE), + .SAXIACPAWID(S_AXI_ACP_AWID), + .SAXIACPAWLEN(S_AXI_ACP_AWLEN), + .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK), + .SAXIACPAWPROT(S_AXI_ACP_AWPROT), + .SAXIACPAWQOS(S_AXI_ACP_AWQOS), + .SAXIACPAWREADY(S_AXI_ACP_AWREADY), + .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]), + .SAXIACPAWUSER(S_AXI_ACP_AWUSER), + .SAXIACPAWVALID(S_AXI_ACP_AWVALID), + .SAXIACPBID(S_AXI_ACP_BID), + .SAXIACPBREADY(S_AXI_ACP_BREADY), + .SAXIACPBRESP(S_AXI_ACP_BRESP), + .SAXIACPBVALID(S_AXI_ACP_BVALID), + .SAXIACPRDATA(S_AXI_ACP_RDATA), + .SAXIACPRID(S_AXI_ACP_RID), + .SAXIACPRLAST(S_AXI_ACP_RLAST), + .SAXIACPRREADY(S_AXI_ACP_RREADY), + .SAXIACPRRESP(S_AXI_ACP_RRESP), + .SAXIACPRVALID(S_AXI_ACP_RVALID), + .SAXIACPWDATA(S_AXI_ACP_WDATA), + .SAXIACPWID(S_AXI_ACP_WID), + .SAXIACPWLAST(S_AXI_ACP_WLAST), + .SAXIACPWREADY(S_AXI_ACP_WREADY), + .SAXIACPWSTRB(S_AXI_ACP_WSTRB), + .SAXIACPWVALID(S_AXI_ACP_WVALID), + .SAXIGP0ACLK(S_AXI_GP0_ACLK), + .SAXIGP0ARADDR(S_AXI_GP0_ARADDR), + .SAXIGP0ARBURST(S_AXI_GP0_ARBURST), + .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE), + .SAXIGP0ARESETN(S_AXI_GP0_ARESETN), + .SAXIGP0ARID(S_AXI_GP0_ARID), + .SAXIGP0ARLEN(S_AXI_GP0_ARLEN), + .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK), + .SAXIGP0ARPROT(S_AXI_GP0_ARPROT), + .SAXIGP0ARQOS(S_AXI_GP0_ARQOS), + .SAXIGP0ARREADY(S_AXI_GP0_ARREADY), + .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]), + .SAXIGP0ARVALID(S_AXI_GP0_ARVALID), + .SAXIGP0AWADDR(S_AXI_GP0_AWADDR), + .SAXIGP0AWBURST(S_AXI_GP0_AWBURST), + .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE), + .SAXIGP0AWID(S_AXI_GP0_AWID), + .SAXIGP0AWLEN(S_AXI_GP0_AWLEN), + .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK), + .SAXIGP0AWPROT(S_AXI_GP0_AWPROT), + .SAXIGP0AWQOS(S_AXI_GP0_AWQOS), + .SAXIGP0AWREADY(S_AXI_GP0_AWREADY), + .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]), + .SAXIGP0AWVALID(S_AXI_GP0_AWVALID), + .SAXIGP0BID(S_AXI_GP0_BID), + .SAXIGP0BREADY(S_AXI_GP0_BREADY), + .SAXIGP0BRESP(S_AXI_GP0_BRESP), + .SAXIGP0BVALID(S_AXI_GP0_BVALID), + .SAXIGP0RDATA(S_AXI_GP0_RDATA), + .SAXIGP0RID(S_AXI_GP0_RID), + .SAXIGP0RLAST(S_AXI_GP0_RLAST), + .SAXIGP0RREADY(S_AXI_GP0_RREADY), + .SAXIGP0RRESP(S_AXI_GP0_RRESP), + .SAXIGP0RVALID(S_AXI_GP0_RVALID), + .SAXIGP0WDATA(S_AXI_GP0_WDATA), + .SAXIGP0WID(S_AXI_GP0_WID), + .SAXIGP0WLAST(S_AXI_GP0_WLAST), + .SAXIGP0WREADY(S_AXI_GP0_WREADY), + .SAXIGP0WSTRB(S_AXI_GP0_WSTRB), + .SAXIGP0WVALID(S_AXI_GP0_WVALID), + .SAXIGP1ACLK(S_AXI_GP1_ACLK), + .SAXIGP1ARADDR(S_AXI_GP1_ARADDR), + .SAXIGP1ARBURST(S_AXI_GP1_ARBURST), + .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE), + .SAXIGP1ARESETN(S_AXI_GP1_ARESETN), + .SAXIGP1ARID(S_AXI_GP1_ARID), + .SAXIGP1ARLEN(S_AXI_GP1_ARLEN), + .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK), + .SAXIGP1ARPROT(S_AXI_GP1_ARPROT), + .SAXIGP1ARQOS(S_AXI_GP1_ARQOS), + .SAXIGP1ARREADY(S_AXI_GP1_ARREADY), + .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]), + .SAXIGP1ARVALID(S_AXI_GP1_ARVALID), + .SAXIGP1AWADDR(S_AXI_GP1_AWADDR), + .SAXIGP1AWBURST(S_AXI_GP1_AWBURST), + .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE), + .SAXIGP1AWID(S_AXI_GP1_AWID), + .SAXIGP1AWLEN(S_AXI_GP1_AWLEN), + .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK), + .SAXIGP1AWPROT(S_AXI_GP1_AWPROT), + .SAXIGP1AWQOS(S_AXI_GP1_AWQOS), + .SAXIGP1AWREADY(S_AXI_GP1_AWREADY), + .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]), + .SAXIGP1AWVALID(S_AXI_GP1_AWVALID), + .SAXIGP1BID(S_AXI_GP1_BID), + .SAXIGP1BREADY(S_AXI_GP1_BREADY), + .SAXIGP1BRESP(S_AXI_GP1_BRESP), + .SAXIGP1BVALID(S_AXI_GP1_BVALID), + .SAXIGP1RDATA(S_AXI_GP1_RDATA), + .SAXIGP1RID(S_AXI_GP1_RID), + .SAXIGP1RLAST(S_AXI_GP1_RLAST), + .SAXIGP1RREADY(S_AXI_GP1_RREADY), + .SAXIGP1RRESP(S_AXI_GP1_RRESP), + .SAXIGP1RVALID(S_AXI_GP1_RVALID), + .SAXIGP1WDATA(S_AXI_GP1_WDATA), + .SAXIGP1WID(S_AXI_GP1_WID), + .SAXIGP1WLAST(S_AXI_GP1_WLAST), + .SAXIGP1WREADY(S_AXI_GP1_WREADY), + .SAXIGP1WSTRB(S_AXI_GP1_WSTRB), + .SAXIGP1WVALID(S_AXI_GP1_WVALID), + .SAXIHP0ACLK(S_AXI_HP0_ACLK), + .SAXIHP0ARADDR(S_AXI_HP0_ARADDR), + .SAXIHP0ARBURST(S_AXI_HP0_ARBURST), + .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE), + .SAXIHP0ARESETN(S_AXI_HP0_ARESETN), + .SAXIHP0ARID(S_AXI_HP0_ARID), + .SAXIHP0ARLEN(S_AXI_HP0_ARLEN), + .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK), + .SAXIHP0ARPROT(S_AXI_HP0_ARPROT), + .SAXIHP0ARQOS(S_AXI_HP0_ARQOS), + .SAXIHP0ARREADY(S_AXI_HP0_ARREADY), + .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]), + .SAXIHP0ARVALID(S_AXI_HP0_ARVALID), + .SAXIHP0AWADDR(S_AXI_HP0_AWADDR), + .SAXIHP0AWBURST(S_AXI_HP0_AWBURST), + .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE), + .SAXIHP0AWID(S_AXI_HP0_AWID), + .SAXIHP0AWLEN(S_AXI_HP0_AWLEN), + .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK), + .SAXIHP0AWPROT(S_AXI_HP0_AWPROT), + .SAXIHP0AWQOS(S_AXI_HP0_AWQOS), + .SAXIHP0AWREADY(S_AXI_HP0_AWREADY), + .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]), + .SAXIHP0AWVALID(S_AXI_HP0_AWVALID), + .SAXIHP0BID(S_AXI_HP0_BID), + .SAXIHP0BREADY(S_AXI_HP0_BREADY), + .SAXIHP0BRESP(S_AXI_HP0_BRESP), + .SAXIHP0BVALID(S_AXI_HP0_BVALID), + .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT), + .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT), + .SAXIHP0RDATA(S_AXI_HP0_RDATA), + .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN), + .SAXIHP0RID(S_AXI_HP0_RID), + .SAXIHP0RLAST(S_AXI_HP0_RLAST), + .SAXIHP0RREADY(S_AXI_HP0_RREADY), + .SAXIHP0RRESP(S_AXI_HP0_RRESP), + .SAXIHP0RVALID(S_AXI_HP0_RVALID), + .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT), + .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT), + .SAXIHP0WDATA(S_AXI_HP0_WDATA), + .SAXIHP0WID(S_AXI_HP0_WID), + .SAXIHP0WLAST(S_AXI_HP0_WLAST), + .SAXIHP0WREADY(S_AXI_HP0_WREADY), + .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN), + .SAXIHP0WSTRB(S_AXI_HP0_WSTRB), + .SAXIHP0WVALID(S_AXI_HP0_WVALID), + .SAXIHP1ACLK(S_AXI_HP1_ACLK), + .SAXIHP1ARADDR(S_AXI_HP1_ARADDR), + .SAXIHP1ARBURST(S_AXI_HP1_ARBURST), + .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE), + .SAXIHP1ARESETN(S_AXI_HP1_ARESETN), + .SAXIHP1ARID(S_AXI_HP1_ARID), + .SAXIHP1ARLEN(S_AXI_HP1_ARLEN), + .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK), + .SAXIHP1ARPROT(S_AXI_HP1_ARPROT), + .SAXIHP1ARQOS(S_AXI_HP1_ARQOS), + .SAXIHP1ARREADY(S_AXI_HP1_ARREADY), + .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]), + .SAXIHP1ARVALID(S_AXI_HP1_ARVALID), + .SAXIHP1AWADDR(S_AXI_HP1_AWADDR), + .SAXIHP1AWBURST(S_AXI_HP1_AWBURST), + .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE), + .SAXIHP1AWID(S_AXI_HP1_AWID), + .SAXIHP1AWLEN(S_AXI_HP1_AWLEN), + .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK), + .SAXIHP1AWPROT(S_AXI_HP1_AWPROT), + .SAXIHP1AWQOS(S_AXI_HP1_AWQOS), + .SAXIHP1AWREADY(S_AXI_HP1_AWREADY), + .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]), + .SAXIHP1AWVALID(S_AXI_HP1_AWVALID), + .SAXIHP1BID(S_AXI_HP1_BID), + .SAXIHP1BREADY(S_AXI_HP1_BREADY), + .SAXIHP1BRESP(S_AXI_HP1_BRESP), + .SAXIHP1BVALID(S_AXI_HP1_BVALID), + .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT), + .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT), + .SAXIHP1RDATA(S_AXI_HP1_RDATA), + .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN), + .SAXIHP1RID(S_AXI_HP1_RID), + .SAXIHP1RLAST(S_AXI_HP1_RLAST), + .SAXIHP1RREADY(S_AXI_HP1_RREADY), + .SAXIHP1RRESP(S_AXI_HP1_RRESP), + .SAXIHP1RVALID(S_AXI_HP1_RVALID), + .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT), + .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT), + .SAXIHP1WDATA(S_AXI_HP1_WDATA), + .SAXIHP1WID(S_AXI_HP1_WID), + .SAXIHP1WLAST(S_AXI_HP1_WLAST), + .SAXIHP1WREADY(S_AXI_HP1_WREADY), + .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN), + .SAXIHP1WSTRB(S_AXI_HP1_WSTRB), + .SAXIHP1WVALID(S_AXI_HP1_WVALID), + .SAXIHP2ACLK(S_AXI_HP2_ACLK), + .SAXIHP2ARADDR(S_AXI_HP2_ARADDR), + .SAXIHP2ARBURST(S_AXI_HP2_ARBURST), + .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE), + .SAXIHP2ARESETN(S_AXI_HP2_ARESETN), + .SAXIHP2ARID(S_AXI_HP2_ARID), + .SAXIHP2ARLEN(S_AXI_HP2_ARLEN), + .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK), + .SAXIHP2ARPROT(S_AXI_HP2_ARPROT), + .SAXIHP2ARQOS(S_AXI_HP2_ARQOS), + .SAXIHP2ARREADY(S_AXI_HP2_ARREADY), + .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]), + .SAXIHP2ARVALID(S_AXI_HP2_ARVALID), + .SAXIHP2AWADDR(S_AXI_HP2_AWADDR), + .SAXIHP2AWBURST(S_AXI_HP2_AWBURST), + .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE), + .SAXIHP2AWID(S_AXI_HP2_AWID), + .SAXIHP2AWLEN(S_AXI_HP2_AWLEN), + .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK), + .SAXIHP2AWPROT(S_AXI_HP2_AWPROT), + .SAXIHP2AWQOS(S_AXI_HP2_AWQOS), + .SAXIHP2AWREADY(S_AXI_HP2_AWREADY), + .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]), + .SAXIHP2AWVALID(S_AXI_HP2_AWVALID), + .SAXIHP2BID(S_AXI_HP2_BID), + .SAXIHP2BREADY(S_AXI_HP2_BREADY), + .SAXIHP2BRESP(S_AXI_HP2_BRESP), + .SAXIHP2BVALID(S_AXI_HP2_BVALID), + .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT), + .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT), + .SAXIHP2RDATA(S_AXI_HP2_RDATA), + .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN), + .SAXIHP2RID(S_AXI_HP2_RID), + .SAXIHP2RLAST(S_AXI_HP2_RLAST), + .SAXIHP2RREADY(S_AXI_HP2_RREADY), + .SAXIHP2RRESP(S_AXI_HP2_RRESP), + .SAXIHP2RVALID(S_AXI_HP2_RVALID), + .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT), + .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT), + .SAXIHP2WDATA(S_AXI_HP2_WDATA), + .SAXIHP2WID(S_AXI_HP2_WID), + .SAXIHP2WLAST(S_AXI_HP2_WLAST), + .SAXIHP2WREADY(S_AXI_HP2_WREADY), + .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN), + .SAXIHP2WSTRB(S_AXI_HP2_WSTRB), + .SAXIHP2WVALID(S_AXI_HP2_WVALID), + .SAXIHP3ACLK(S_AXI_HP3_ACLK), + .SAXIHP3ARADDR(S_AXI_HP3_ARADDR), + .SAXIHP3ARBURST(S_AXI_HP3_ARBURST), + .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE), + .SAXIHP3ARESETN(S_AXI_HP3_ARESETN), + .SAXIHP3ARID(S_AXI_HP3_ARID), + .SAXIHP3ARLEN(S_AXI_HP3_ARLEN), + .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK), + .SAXIHP3ARPROT(S_AXI_HP3_ARPROT), + .SAXIHP3ARQOS(S_AXI_HP3_ARQOS), + .SAXIHP3ARREADY(S_AXI_HP3_ARREADY), + .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]), + .SAXIHP3ARVALID(S_AXI_HP3_ARVALID), + .SAXIHP3AWADDR(S_AXI_HP3_AWADDR), + .SAXIHP3AWBURST(S_AXI_HP3_AWBURST), + .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE), + .SAXIHP3AWID(S_AXI_HP3_AWID), + .SAXIHP3AWLEN(S_AXI_HP3_AWLEN), + .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK), + .SAXIHP3AWPROT(S_AXI_HP3_AWPROT), + .SAXIHP3AWQOS(S_AXI_HP3_AWQOS), + .SAXIHP3AWREADY(S_AXI_HP3_AWREADY), + .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]), + .SAXIHP3AWVALID(S_AXI_HP3_AWVALID), + .SAXIHP3BID(S_AXI_HP3_BID), + .SAXIHP3BREADY(S_AXI_HP3_BREADY), + .SAXIHP3BRESP(S_AXI_HP3_BRESP), + .SAXIHP3BVALID(S_AXI_HP3_BVALID), + .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT), + .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT), + .SAXIHP3RDATA(S_AXI_HP3_RDATA), + .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN), + .SAXIHP3RID(S_AXI_HP3_RID), + .SAXIHP3RLAST(S_AXI_HP3_RLAST), + .SAXIHP3RREADY(S_AXI_HP3_RREADY), + .SAXIHP3RRESP(S_AXI_HP3_RRESP), + .SAXIHP3RVALID(S_AXI_HP3_RVALID), + .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT), + .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT), + .SAXIHP3WDATA(S_AXI_HP3_WDATA), + .SAXIHP3WID(S_AXI_HP3_WID), + .SAXIHP3WLAST(S_AXI_HP3_WLAST), + .SAXIHP3WREADY(S_AXI_HP3_WREADY), + .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN), + .SAXIHP3WSTRB(S_AXI_HP3_WSTRB), + .SAXIHP3WVALID(S_AXI_HP3_WVALID)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_CLK_BIBUF + (.IO(buffered_PS_CLK), + .PAD(PS_CLK)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_PORB_BIBUF + (.IO(buffered_PS_PORB), + .PAD(PS_PORB)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_SRSTB_BIBUF + (.IO(buffered_PS_SRSTB), + .PAD(PS_SRSTB)); + LUT1 #( + .INIT(2'h1)) + SDIO0_CMD_T_INST_0 + (.I0(SDIO0_CMD_T_n), + .O(SDIO0_CMD_T)); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[0]_INST_0 + (.I0(SDIO0_DATA_T_n[0]), + .O(SDIO0_DATA_T[0])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[1]_INST_0 + (.I0(SDIO0_DATA_T_n[1]), + .O(SDIO0_DATA_T[1])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[2]_INST_0 + (.I0(SDIO0_DATA_T_n[2]), + .O(SDIO0_DATA_T[2])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[3]_INST_0 + (.I0(SDIO0_DATA_T_n[3]), + .O(SDIO0_DATA_T[3])); + LUT1 #( + .INIT(2'h1)) + SDIO1_CMD_T_INST_0 + (.I0(SDIO1_CMD_T_n), + .O(SDIO1_CMD_T)); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[0]_INST_0 + (.I0(SDIO1_DATA_T_n[0]), + .O(SDIO1_DATA_T[0])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[1]_INST_0 + (.I0(SDIO1_DATA_T_n[1]), + .O(SDIO1_DATA_T[1])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[2]_INST_0 + (.I0(SDIO1_DATA_T_n[2]), + .O(SDIO1_DATA_T[2])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[3]_INST_0 + (.I0(SDIO1_DATA_T_n[3]), + .O(SDIO1_DATA_T[3])); + LUT1 #( + .INIT(2'h1)) + SPI0_MISO_T_INST_0 + (.I0(SPI0_MISO_T_n), + .O(SPI0_MISO_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_MOSI_T_INST_0 + (.I0(SPI0_MOSI_T_n), + .O(SPI0_MOSI_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_SCLK_T_INST_0 + (.I0(SPI0_SCLK_T_n), + .O(SPI0_SCLK_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_SS_T_INST_0 + (.I0(SPI0_SS_T_n), + .O(SPI0_SS_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_MISO_T_INST_0 + (.I0(SPI1_MISO_T_n), + .O(SPI1_MISO_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_MOSI_T_INST_0 + (.I0(SPI1_MOSI_T_n), + .O(SPI1_MOSI_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_SCLK_T_INST_0 + (.I0(SPI1_SCLK_T_n), + .O(SPI1_SCLK_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_SS_T_INST_0 + (.I0(SPI1_SS_T_n), + .O(SPI1_SS_T)); + VCC VCC + (.P(\ )); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG + (.I(FCLK_CLK_unbuffered[0]), + .O(FCLK_CLK0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_1.FCLK_CLK_1_BUFG + (.I(FCLK_CLK_unbuffered[1]), + .O(FCLK_CLK1)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[0].MIO_BIBUF + (.IO(buffered_MIO[0]), + .PAD(MIO[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[10].MIO_BIBUF + (.IO(buffered_MIO[10]), + .PAD(MIO[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[11].MIO_BIBUF + (.IO(buffered_MIO[11]), + .PAD(MIO[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[12].MIO_BIBUF + (.IO(buffered_MIO[12]), + .PAD(MIO[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[13].MIO_BIBUF + (.IO(buffered_MIO[13]), + .PAD(MIO[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[14].MIO_BIBUF + (.IO(buffered_MIO[14]), + .PAD(MIO[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[15].MIO_BIBUF + (.IO(buffered_MIO[15]), + .PAD(MIO[15])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[16].MIO_BIBUF + (.IO(buffered_MIO[16]), + .PAD(MIO[16])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[17].MIO_BIBUF + (.IO(buffered_MIO[17]), + .PAD(MIO[17])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[18].MIO_BIBUF + (.IO(buffered_MIO[18]), + .PAD(MIO[18])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[19].MIO_BIBUF + (.IO(buffered_MIO[19]), + .PAD(MIO[19])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[1].MIO_BIBUF + (.IO(buffered_MIO[1]), + .PAD(MIO[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[20].MIO_BIBUF + (.IO(buffered_MIO[20]), + .PAD(MIO[20])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[21].MIO_BIBUF + (.IO(buffered_MIO[21]), + .PAD(MIO[21])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[22].MIO_BIBUF + (.IO(buffered_MIO[22]), + .PAD(MIO[22])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[23].MIO_BIBUF + (.IO(buffered_MIO[23]), + .PAD(MIO[23])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[24].MIO_BIBUF + (.IO(buffered_MIO[24]), + .PAD(MIO[24])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[25].MIO_BIBUF + (.IO(buffered_MIO[25]), + .PAD(MIO[25])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[26].MIO_BIBUF + (.IO(buffered_MIO[26]), + .PAD(MIO[26])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[27].MIO_BIBUF + (.IO(buffered_MIO[27]), + .PAD(MIO[27])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[28].MIO_BIBUF + (.IO(buffered_MIO[28]), + .PAD(MIO[28])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[29].MIO_BIBUF + (.IO(buffered_MIO[29]), + .PAD(MIO[29])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[2].MIO_BIBUF + (.IO(buffered_MIO[2]), + .PAD(MIO[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[30].MIO_BIBUF + (.IO(buffered_MIO[30]), + .PAD(MIO[30])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[31].MIO_BIBUF + (.IO(buffered_MIO[31]), + .PAD(MIO[31])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[3].MIO_BIBUF + (.IO(buffered_MIO[3]), + .PAD(MIO[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[4].MIO_BIBUF + (.IO(buffered_MIO[4]), + .PAD(MIO[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[5].MIO_BIBUF + (.IO(buffered_MIO[5]), + .PAD(MIO[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[6].MIO_BIBUF + (.IO(buffered_MIO[6]), + .PAD(MIO[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[7].MIO_BIBUF + (.IO(buffered_MIO[7]), + .PAD(MIO[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[8].MIO_BIBUF + (.IO(buffered_MIO[8]), + .PAD(MIO[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[9].MIO_BIBUF + (.IO(buffered_MIO[9]), + .PAD(MIO[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[0].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[0]), + .PAD(DDR_BankAddr[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[1].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[1]), + .PAD(DDR_BankAddr[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[2].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[2]), + .PAD(DDR_BankAddr[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[0].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[0]), + .PAD(DDR_Addr[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[10].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[10]), + .PAD(DDR_Addr[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[11].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[11]), + .PAD(DDR_Addr[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[12].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[12]), + .PAD(DDR_Addr[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[13].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[13]), + .PAD(DDR_Addr[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[14].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[14]), + .PAD(DDR_Addr[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[1].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[1]), + .PAD(DDR_Addr[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[2].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[2]), + .PAD(DDR_Addr[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[3].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[3]), + .PAD(DDR_Addr[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[4].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[4]), + .PAD(DDR_Addr[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[5].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[5]), + .PAD(DDR_Addr[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[6].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[6]), + .PAD(DDR_Addr[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[7].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[7]), + .PAD(DDR_Addr[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[8].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[8]), + .PAD(DDR_Addr[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[9].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[9]), + .PAD(DDR_Addr[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[0].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[0]), + .PAD(DDR_DM[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[1].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[1]), + .PAD(DDR_DM[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[0].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[0]), + .PAD(DDR_DQ[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[10].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[10]), + .PAD(DDR_DQ[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[11].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[11]), + .PAD(DDR_DQ[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[12].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[12]), + .PAD(DDR_DQ[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[13].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[13]), + .PAD(DDR_DQ[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[14].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[14]), + .PAD(DDR_DQ[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[15].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[15]), + .PAD(DDR_DQ[15])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[1].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[1]), + .PAD(DDR_DQ[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[2].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[2]), + .PAD(DDR_DQ[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[3].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[3]), + .PAD(DDR_DQ[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[4].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[4]), + .PAD(DDR_DQ[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[5].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[5]), + .PAD(DDR_DQ[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[6].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[6]), + .PAD(DDR_DQ[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[7].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[7]), + .PAD(DDR_DQ[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[8].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[8]), + .PAD(DDR_DQ[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[9].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[9]), + .PAD(DDR_DQ[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[0].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[0]), + .PAD(DDR_DQS_n[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[1].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[1]), + .PAD(DDR_DQS_n[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[0].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[0]), + .PAD(DDR_DQS[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[1].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[1]), + .PAD(DDR_DQS[1])); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[0] )); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[0] [1])); + LUT1 #( + .INIT(2'h2)) + i_10 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[7] [1])); + LUT1 #( + .INIT(2'h2)) + i_11 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[7] [0])); + LUT1 #( + .INIT(2'h2)) + i_12 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[6] [1])); + LUT1 #( + .INIT(2'h2)) + i_13 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[6] [0])); + LUT1 #( + .INIT(2'h2)) + i_14 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[5] [1])); + LUT1 #( + .INIT(2'h2)) + i_15 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[5] [0])); + LUT1 #( + .INIT(2'h2)) + i_16 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[4] [1])); + LUT1 #( + .INIT(2'h2)) + i_17 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[4] [0])); + LUT1 #( + .INIT(2'h2)) + i_18 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[3] [1])); + LUT1 #( + .INIT(2'h2)) + i_19 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[3] [0])); + LUT1 #( + .INIT(2'h2)) + i_2 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[0] [0])); + LUT1 #( + .INIT(2'h2)) + i_20 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[2] [1])); + LUT1 #( + .INIT(2'h2)) + i_21 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[2] [0])); + LUT1 #( + .INIT(2'h2)) + i_22 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[1] [1])); + LUT1 #( + .INIT(2'h2)) + i_23 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[1] [0])); + LUT1 #( + .INIT(2'h2)) + i_3 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[7] )); + LUT1 #( + .INIT(2'h2)) + i_4 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[6] )); + LUT1 #( + .INIT(2'h2)) + i_5 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[5] )); + LUT1 #( + .INIT(2'h2)) + i_6 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[4] )); + LUT1 #( + .INIT(2'h2)) + i_7 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[3] )); + LUT1 #( + .INIT(2'h2)) + i_8 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[2] )); + LUT1 #( + .INIT(2'h2)) + i_9 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[1] )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LED_Blink/LED_Blink.cache/ip/2018.2/50c2fa8fed532918/design_1_processing_system7_0_0_stub.v b/LED_Blink/LED_Blink.cache/ip/2018.2/50c2fa8fed532918/design_1_processing_system7_0_0_stub.v new file mode 100644 index 0000000..0987209 --- /dev/null +++ b/LED_Blink/LED_Blink.cache/ip/2018.2/50c2fa8fed532918/design_1_processing_system7_0_0_stub.v @@ -0,0 +1,164 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Fri Aug 17 17:36:45 2018 +// Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v +// Design : design_1_processing_system7_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg225-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, + I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, SDIO0_CLK, SDIO0_CLK_FB, SDIO0_CMD_O, + SDIO0_CMD_I, SDIO0_CMD_T, SDIO0_DATA_I, SDIO0_DATA_O, SDIO0_DATA_T, SDIO0_LED, SDIO0_CDN, + SDIO0_WP, SDIO0_BUSPOW, SDIO0_BUSVOLT, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, + SPI0_MOSI_O, SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, + SPI0_SS1_O, SPI0_SS2_O, SPI0_SS_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, + SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, + SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, TTC1_WAVE0_OUT, TTC1_WAVE1_OUT, TTC1_WAVE2_OUT, USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, + M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, + M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_CLK1, + FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, + DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, + PS_SRSTB, PS_CLK, PS_PORB) +/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_CLK,SDIO0_CLK_FB,SDIO0_CMD_O,SDIO0_CMD_I,SDIO0_CMD_T,SDIO0_DATA_I[3:0],SDIO0_DATA_O[3:0],SDIO0_DATA_T[3:0],SDIO0_LED,SDIO0_CDN,SDIO0_WP,SDIO0_BUSPOW,SDIO0_BUSVOLT[2:0],SPI0_SCLK_I,SPI0_SCLK_O,SPI0_SCLK_T,SPI0_MOSI_I,SPI0_MOSI_O,SPI0_MOSI_T,SPI0_MISO_I,SPI0_MISO_O,SPI0_MISO_T,SPI0_SS_I,SPI0_SS_O,SPI0_SS1_O,SPI0_SS2_O,SPI0_SS_T,SPI1_SCLK_I,SPI1_SCLK_O,SPI1_SCLK_T,SPI1_MOSI_I,SPI1_MOSI_O,SPI1_MOSI_T,SPI1_MISO_I,SPI1_MISO_O,SPI1_MISO_T,SPI1_SS_I,SPI1_SS_O,SPI1_SS1_O,SPI1_SS2_O,SPI1_SS_T,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,TTC1_WAVE0_OUT,TTC1_WAVE1_OUT,TTC1_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[31:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[1:0],DDR_DQ[15:0],DDR_DQS_n[1:0],DDR_DQS[1:0],PS_SRSTB,PS_CLK,PS_PORB" */; + input [63:0]GPIO_I; + output [63:0]GPIO_O; + output [63:0]GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0]SDIO0_DATA_I; + output [3:0]SDIO0_DATA_O; + output [3:0]SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0]SDIO0_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_TX; + input UART0_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + output [1:0]USB0_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [11:0]M_AXI_GP0_ARID; + output [11:0]M_AXI_GP0_AWID; + output [11:0]M_AXI_GP0_WID; + output [1:0]M_AXI_GP0_ARBURST; + output [1:0]M_AXI_GP0_ARLOCK; + output [2:0]M_AXI_GP0_ARSIZE; + output [1:0]M_AXI_GP0_AWBURST; + output [1:0]M_AXI_GP0_AWLOCK; + output [2:0]M_AXI_GP0_AWSIZE; + output [2:0]M_AXI_GP0_ARPROT; + output [2:0]M_AXI_GP0_AWPROT; + output [31:0]M_AXI_GP0_ARADDR; + output [31:0]M_AXI_GP0_AWADDR; + output [31:0]M_AXI_GP0_WDATA; + output [3:0]M_AXI_GP0_ARCACHE; + output [3:0]M_AXI_GP0_ARLEN; + output [3:0]M_AXI_GP0_ARQOS; + output [3:0]M_AXI_GP0_AWCACHE; + output [3:0]M_AXI_GP0_AWLEN; + output [3:0]M_AXI_GP0_AWQOS; + output [3:0]M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [11:0]M_AXI_GP0_BID; + input [11:0]M_AXI_GP0_RID; + input [1:0]M_AXI_GP0_BRESP; + input [1:0]M_AXI_GP0_RRESP; + input [31:0]M_AXI_GP0_RDATA; + input [0:0]IRQ_F2P; + output FCLK_CLK0; + output FCLK_CLK1; + output FCLK_RESET0_N; + inout [31:0]MIO; + inout DDR_CAS_n; + inout DDR_CKE; + inout DDR_Clk_n; + inout DDR_Clk; + inout DDR_CS_n; + inout DDR_DRSTB; + inout DDR_ODT; + inout DDR_RAS_n; + inout DDR_WEB; + inout [2:0]DDR_BankAddr; + inout [14:0]DDR_Addr; + inout DDR_VRN; + inout DDR_VRP; + inout [1:0]DDR_DM; + inout [15:0]DDR_DQ; + inout [1:0]DDR_DQS_n; + inout [1:0]DDR_DQS; + inout PS_SRSTB; + inout PS_CLK; + inout PS_PORB; +endmodule diff --git a/LED_Blink/LED_Blink.cache/ip/2018.2/50c2fa8fed532918/stats.txt b/LED_Blink/LED_Blink.cache/ip/2018.2/50c2fa8fed532918/stats.txt new file mode 100644 index 0000000..4b52009 --- /dev/null +++ b/LED_Blink/LED_Blink.cache/ip/2018.2/50c2fa8fed532918/stats.txt @@ -0,0 +1,4 @@ +NumberHits:0 +Timestamp: Fri Aug 17 08:36:46 UTC 2018 +VLNV: xilinx.com:ip:processing_system7:5.5 +SynthRuntime: 62 diff --git a/LED_Blink/LED_Blink.cache/wt/webtalk_pa.xml b/LED_Blink/LED_Blink.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..4ab304f --- /dev/null +++ b/LED_Blink/LED_Blink.cache/wt/webtalk_pa.xml @@ -0,0 +1,122 @@ + + + + +
+ + +
+
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+ + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_1.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_10.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_11.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000..174466d --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_12.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_12.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_12.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_13.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_13.xml new file mode 100644 index 0000000..1b0feda --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_13.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_2.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..a5ccf12 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_3.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_3.xml new file mode 100644 index 0000000..ae806f5 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_4.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_5.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_6.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_7.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_8.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/.jobs/vrs_config_9.xml b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..723c628 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.dcp b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..acbdf8ac61273db8fb2a7366576c20a91e3885a6 GIT binary patch literal 13314 zcmaL819&CPx9GiN+s4H9#F^N(ZQHgc*2K1L+Y?(8+fHuYd+zF2w z)vBu9^;E63T22xK6cqpfKmt^wk)$mn2;FLd000|M0081E*T~S0&du5?I&sn_p8-{5 zDWSMV%^AJ$huCUqyb@4C2ofKXKZ~|HX!;OU?KcK2PFcPJ`{I*;h{DTf_N5eR_nR49 zXggwKVUBdFwlYeD`rd)fgtPk*N))}@Y;))<%DsK1*~FFY;QGtzoykE>TY-~ABw9&)y{S;{Gb z!to@BL$VYmdXFcRLA0VLPw~+Bj9F-dCs z3bfe^l-sCBI?&hQDmkauR`wx&BQ6q8SWkhP^KyzCpmBRfTReziQY!LasdfaF6Qgm^ zBh=Ap+NgFNYRqzbB;PmrpfPco?$k@@`)JB(4*UH#PmqC|-&e+K0T-(xd zmmU2*OE-5cRJ!B@Zkan_b+e2mw!zd)3?=@2vx*V}i1ZrNYACj#Uh{QJwXTLXsv5uP zIJ1cDJ&f^j>`+TwRQ2W*Q#R9+Wl-|4w-L@Wq}XM!3YXAHs@tviVflP$j`2=xJkP=2`nZ1@SsBZKF; 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Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 0 + +set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1 -new_name design_1_led_0_0 -ip [get_ips design_1_led_0_0]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top design_1_led_0_0 -part xc7z010clg225-1 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix design_1_led_0_0_ design_1_led_0_0.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_led_0_0_stub.v + lappend ipCachedFiles design_1_led_0_0_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_led_0_0_stub.vhdl + lappend ipCachedFiles design_1_led_0_0_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_led_0_0_sim_netlist.v + lappend ipCachedFiles design_1_led_0_0_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_led_0_0_sim_netlist.vhdl + lappend ipCachedFiles design_1_led_0_0_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp design_1_led_0_0.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips design_1_led_0_0] +} + +rename_ref -prefix_all design_1_led_0_0_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef design_1_led_0_0.dcp +create_report "design_1_led_0_0_synth_1_synth_report_utilization_0" "report_utilization -file design_1_led_0_0_utilization_synth.rpt -pb design_1_led_0_0_utilization_synth.pb" + +if { [catch { + file copy -force C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.dcp c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + write_verilog -force -mode synth_stub c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +if { [catch { + file copy -force C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.dcp c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.dcp +} _RESULT ] } { + send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." + error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." +} + +if { [catch { + file rename -force C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_stub.v c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_stub.vhdl c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + file rename -force C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_sim_netlist.v c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + file rename -force C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_sim_netlist.vhdl c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +}; # end if cached_ip + +if {[file isdir C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.ip_user_files/ip/design_1_led_0_0]} { + catch { + file copy -force c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.v C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.ip_user_files/ip/design_1_led_0_0 + } +} + +if {[file isdir C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.ip_user_files/ip/design_1_led_0_0]} { + catch { + file copy -force c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.vhdl C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.ip_user_files/ip/design_1_led_0_0 + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.vds b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.vds new file mode 100644 index 0000000..3e7a700 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.vds @@ -0,0 +1,268 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Aug 17 17:41:53 2018 +# Process ID: 20792 +# Current directory: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1 +# Command line: vivado.exe -log design_1_led_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_led_0_0.tcl +# Log file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.vds +# Journal file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1\vivado.jou +#----------------------------------------------------------- +source design_1_led_0_0.tcl -notrace +Command: synth_design -top design_1_led_0_0 -part xc7z010clg225-1 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 6368 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 375.090 ; gain = 104.203 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'design_1_led_0_0' [c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/synth/design_1_led_0_0.v:58] +INFO: [Synth 8-6157] synthesizing module 'led' [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/new/led.v:24] +INFO: [Synth 8-6155] done synthesizing module 'led' (1#1) [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/new/led.v:24] +INFO: [Synth 8-6155] done synthesizing module 'design_1_led_0_0' (2#1) [c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/synth/design_1_led_0_0.v:58] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 429.695 ; gain = 158.809 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 429.695 ; gain = 158.809 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 429.695 ; gain = 158.809 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg225-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +WARNING: [Constraints 18-5210] No constraint will be written out. +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.120 . Memory (MB): peak = 724.645 ; gain = 1.859 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 724.645 ; gain = 453.758 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg225-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 724.645 ; gain = 453.758 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:22 . Memory (MB): peak = 724.645 ; gain = 453.758 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 724.645 ; gain = 453.758 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module led +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 724.645 ; gain = 453.758 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 750.863 ; gain = 479.977 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 750.863 ; gain = 479.977 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:39 . Memory (MB): peak = 760.973 ; gain = 490.086 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 760.973 ; gain = 490.086 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 760.973 ; gain = 490.086 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 760.973 ; gain = 490.086 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 760.973 ; gain = 490.086 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 760.973 ; gain = 490.086 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 760.973 ; gain = 490.086 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |CARRY4 | 7| +|2 |LUT1 | 1| +|3 |LUT4 | 2| +|4 |LUT5 | 2| +|5 |LUT6 | 3| +|6 |FDRE | 26| ++------+-------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 41| +|2 | inst |led | 41| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 760.973 ; gain = 490.086 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:28 . Memory (MB): peak = 760.973 ; gain = 195.137 +Synthesis Optimization Complete : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 760.973 ; gain = 490.086 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +15 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:44 . Memory (MB): peak = 769.965 ; gain = 512.000 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.dcp' has been generated. +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file design_1_led_0_0_utilization_synth.rpt -pb design_1_led_0_0_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 769.965 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Fri Aug 17 17:42:47 2018... diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_sim_netlist.v b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_sim_netlist.v new file mode 100644 index 0000000..2d4e4a1 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_sim_netlist.v @@ -0,0 +1,503 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Fri Aug 17 17:42:46 2018 +// Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_led_0_0_sim_netlist.v +// Design : design_1_led_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg225-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_led_0_0,led,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *) +(* X_CORE_INFO = "led,Vivado 2018.2" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (m_clock, + led_op); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_clock, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) input m_clock; + output led_op; + + wire led_op; + wire m_clock; + + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led inst + (.led_op(led_op), + .m_clock(m_clock)); +endmodule + +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led + (led_op, + m_clock); + output led_op; + input m_clock; + + wire clear; + wire \cnt[0]_i_3_n_0 ; + wire \cnt[0]_i_4_n_0 ; + wire \cnt[0]_i_5_n_0 ; + wire [24:6]cnt_reg; + wire \cnt_reg[0]_i_2_n_0 ; + wire \cnt_reg[0]_i_2_n_1 ; + wire \cnt_reg[0]_i_2_n_2 ; + wire \cnt_reg[0]_i_2_n_3 ; + wire \cnt_reg[0]_i_2_n_4 ; + wire \cnt_reg[0]_i_2_n_5 ; + wire \cnt_reg[0]_i_2_n_6 ; + wire \cnt_reg[0]_i_2_n_7 ; + wire \cnt_reg[12]_i_1_n_0 ; + wire \cnt_reg[12]_i_1_n_1 ; + wire \cnt_reg[12]_i_1_n_2 ; + wire \cnt_reg[12]_i_1_n_3 ; + wire \cnt_reg[12]_i_1_n_4 ; + wire \cnt_reg[12]_i_1_n_5 ; + wire \cnt_reg[12]_i_1_n_6 ; + wire \cnt_reg[12]_i_1_n_7 ; + wire \cnt_reg[16]_i_1_n_0 ; + wire \cnt_reg[16]_i_1_n_1 ; + wire \cnt_reg[16]_i_1_n_2 ; + wire \cnt_reg[16]_i_1_n_3 ; + wire \cnt_reg[16]_i_1_n_4 ; + wire \cnt_reg[16]_i_1_n_5 ; + wire \cnt_reg[16]_i_1_n_6 ; + wire \cnt_reg[16]_i_1_n_7 ; + wire \cnt_reg[20]_i_1_n_0 ; + wire \cnt_reg[20]_i_1_n_1 ; + wire \cnt_reg[20]_i_1_n_2 ; + wire \cnt_reg[20]_i_1_n_3 ; + wire \cnt_reg[20]_i_1_n_4 ; + wire \cnt_reg[20]_i_1_n_5 ; + wire \cnt_reg[20]_i_1_n_6 ; + wire \cnt_reg[20]_i_1_n_7 ; + wire \cnt_reg[24]_i_1_n_7 ; + wire \cnt_reg[4]_i_1_n_0 ; + wire \cnt_reg[4]_i_1_n_1 ; + wire \cnt_reg[4]_i_1_n_2 ; + wire \cnt_reg[4]_i_1_n_3 ; + wire \cnt_reg[4]_i_1_n_4 ; + wire \cnt_reg[4]_i_1_n_5 ; + wire \cnt_reg[4]_i_1_n_6 ; + wire \cnt_reg[4]_i_1_n_7 ; + wire \cnt_reg[8]_i_1_n_0 ; + wire \cnt_reg[8]_i_1_n_1 ; + wire \cnt_reg[8]_i_1_n_2 ; + wire \cnt_reg[8]_i_1_n_3 ; + wire \cnt_reg[8]_i_1_n_4 ; + wire \cnt_reg[8]_i_1_n_5 ; + wire \cnt_reg[8]_i_1_n_6 ; + wire \cnt_reg[8]_i_1_n_7 ; + wire \cnt_reg_n_0_[0] ; + wire \cnt_reg_n_0_[1] ; + wire \cnt_reg_n_0_[2] ; + wire \cnt_reg_n_0_[3] ; + wire \cnt_reg_n_0_[4] ; + wire \cnt_reg_n_0_[5] ; + wire led_op; + wire led_op_r_i_1_n_0; + wire led_op_r_i_2_n_0; + wire led_op_r_i_3_n_0; + wire led_op_r_i_4_n_0; + wire m_clock; + wire [3:0]\NLW_cnt_reg[24]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_cnt_reg[24]_i_1_O_UNCONNECTED ; + + LUT6 #( + .INIT(64'hFFFF0000A8880000)) + \cnt[0]_i_1 + (.I0(\cnt[0]_i_3_n_0 ), + .I1(cnt_reg[17]), + .I2(\cnt[0]_i_4_n_0 ), + .I3(cnt_reg[16]), + .I4(cnt_reg[24]), + .I5(cnt_reg[23]), + .O(clear)); + LUT5 #( + .INIT(32'h80000000)) + \cnt[0]_i_3 + (.I0(cnt_reg[18]), + .I1(cnt_reg[19]), + .I2(cnt_reg[20]), + .I3(cnt_reg[22]), + .I4(cnt_reg[21]), + .O(\cnt[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF80000000)) + \cnt[0]_i_4 + (.I0(led_op_r_i_4_n_0), + .I1(cnt_reg[12]), + .I2(cnt_reg[11]), + .I3(cnt_reg[14]), + .I4(cnt_reg[13]), + .I5(cnt_reg[15]), + .O(\cnt[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \cnt[0]_i_5 + (.I0(\cnt_reg_n_0_[0] ), + .O(\cnt[0]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \cnt_reg[0] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[0]_i_2_n_7 ), + .Q(\cnt_reg_n_0_[0] ), + .R(clear)); + CARRY4 \cnt_reg[0]_i_2 + (.CI(1'b0), + .CO({\cnt_reg[0]_i_2_n_0 ,\cnt_reg[0]_i_2_n_1 ,\cnt_reg[0]_i_2_n_2 ,\cnt_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\cnt_reg[0]_i_2_n_4 ,\cnt_reg[0]_i_2_n_5 ,\cnt_reg[0]_i_2_n_6 ,\cnt_reg[0]_i_2_n_7 }), + .S({\cnt_reg_n_0_[3] ,\cnt_reg_n_0_[2] ,\cnt_reg_n_0_[1] ,\cnt[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \cnt_reg[10] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[8]_i_1_n_5 ), + .Q(cnt_reg[10]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[11] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[8]_i_1_n_4 ), + .Q(cnt_reg[11]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[12] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[12]_i_1_n_7 ), + .Q(cnt_reg[12]), + .R(clear)); + CARRY4 \cnt_reg[12]_i_1 + (.CI(\cnt_reg[8]_i_1_n_0 ), + .CO({\cnt_reg[12]_i_1_n_0 ,\cnt_reg[12]_i_1_n_1 ,\cnt_reg[12]_i_1_n_2 ,\cnt_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[12]_i_1_n_4 ,\cnt_reg[12]_i_1_n_5 ,\cnt_reg[12]_i_1_n_6 ,\cnt_reg[12]_i_1_n_7 }), + .S(cnt_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \cnt_reg[13] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[12]_i_1_n_6 ), + .Q(cnt_reg[13]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[14] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[12]_i_1_n_5 ), + .Q(cnt_reg[14]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[15] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[12]_i_1_n_4 ), + .Q(cnt_reg[15]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[16] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[16]_i_1_n_7 ), + .Q(cnt_reg[16]), + .R(clear)); + CARRY4 \cnt_reg[16]_i_1 + (.CI(\cnt_reg[12]_i_1_n_0 ), + .CO({\cnt_reg[16]_i_1_n_0 ,\cnt_reg[16]_i_1_n_1 ,\cnt_reg[16]_i_1_n_2 ,\cnt_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[16]_i_1_n_4 ,\cnt_reg[16]_i_1_n_5 ,\cnt_reg[16]_i_1_n_6 ,\cnt_reg[16]_i_1_n_7 }), + .S(cnt_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \cnt_reg[17] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[16]_i_1_n_6 ), + .Q(cnt_reg[17]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[18] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[16]_i_1_n_5 ), + .Q(cnt_reg[18]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[19] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[16]_i_1_n_4 ), + .Q(cnt_reg[19]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[1] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[0]_i_2_n_6 ), + .Q(\cnt_reg_n_0_[1] ), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[20] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[20]_i_1_n_7 ), + .Q(cnt_reg[20]), + .R(clear)); + CARRY4 \cnt_reg[20]_i_1 + (.CI(\cnt_reg[16]_i_1_n_0 ), + .CO({\cnt_reg[20]_i_1_n_0 ,\cnt_reg[20]_i_1_n_1 ,\cnt_reg[20]_i_1_n_2 ,\cnt_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[20]_i_1_n_4 ,\cnt_reg[20]_i_1_n_5 ,\cnt_reg[20]_i_1_n_6 ,\cnt_reg[20]_i_1_n_7 }), + .S(cnt_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \cnt_reg[21] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[20]_i_1_n_6 ), + .Q(cnt_reg[21]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[22] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[20]_i_1_n_5 ), + .Q(cnt_reg[22]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[23] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[20]_i_1_n_4 ), + .Q(cnt_reg[23]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[24] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[24]_i_1_n_7 ), + .Q(cnt_reg[24]), + .R(clear)); + CARRY4 \cnt_reg[24]_i_1 + (.CI(\cnt_reg[20]_i_1_n_0 ), + .CO(\NLW_cnt_reg[24]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_cnt_reg[24]_i_1_O_UNCONNECTED [3:1],\cnt_reg[24]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,cnt_reg[24]})); + FDRE #( + .INIT(1'b0)) + \cnt_reg[2] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[0]_i_2_n_5 ), + .Q(\cnt_reg_n_0_[2] ), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[3] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[0]_i_2_n_4 ), + .Q(\cnt_reg_n_0_[3] ), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[4] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[4]_i_1_n_7 ), + .Q(\cnt_reg_n_0_[4] ), + .R(clear)); + CARRY4 \cnt_reg[4]_i_1 + (.CI(\cnt_reg[0]_i_2_n_0 ), + .CO({\cnt_reg[4]_i_1_n_0 ,\cnt_reg[4]_i_1_n_1 ,\cnt_reg[4]_i_1_n_2 ,\cnt_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[4]_i_1_n_4 ,\cnt_reg[4]_i_1_n_5 ,\cnt_reg[4]_i_1_n_6 ,\cnt_reg[4]_i_1_n_7 }), + .S({cnt_reg[7:6],\cnt_reg_n_0_[5] ,\cnt_reg_n_0_[4] })); + FDRE #( + .INIT(1'b0)) + \cnt_reg[5] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[4]_i_1_n_6 ), + .Q(\cnt_reg_n_0_[5] ), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[6] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[4]_i_1_n_5 ), + .Q(cnt_reg[6]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[7] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[4]_i_1_n_4 ), + .Q(cnt_reg[7]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[8] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[8]_i_1_n_7 ), + .Q(cnt_reg[8]), + .R(clear)); + CARRY4 \cnt_reg[8]_i_1 + (.CI(\cnt_reg[4]_i_1_n_0 ), + .CO({\cnt_reg[8]_i_1_n_0 ,\cnt_reg[8]_i_1_n_1 ,\cnt_reg[8]_i_1_n_2 ,\cnt_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[8]_i_1_n_4 ,\cnt_reg[8]_i_1_n_5 ,\cnt_reg[8]_i_1_n_6 ,\cnt_reg[8]_i_1_n_7 }), + .S(cnt_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \cnt_reg[9] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[8]_i_1_n_6 ), + .Q(cnt_reg[9]), + .R(clear)); + LUT4 #( + .INIT(16'h37C8)) + led_op_r_i_1 + (.I0(cnt_reg[23]), + .I1(cnt_reg[24]), + .I2(led_op_r_i_2_n_0), + .I3(led_op), + .O(led_op_r_i_1_n_0)); + LUT6 #( + .INIT(64'hAAA8A8A888888888)) + led_op_r_i_2 + (.I0(\cnt[0]_i_3_n_0 ), + .I1(cnt_reg[17]), + .I2(cnt_reg[15]), + .I3(led_op_r_i_3_n_0), + .I4(led_op_r_i_4_n_0), + .I5(cnt_reg[16]), + .O(led_op_r_i_2_n_0)); + LUT4 #( + .INIT(16'h8000)) + led_op_r_i_3 + (.I0(cnt_reg[12]), + .I1(cnt_reg[11]), + .I2(cnt_reg[14]), + .I3(cnt_reg[13]), + .O(led_op_r_i_3_n_0)); + LUT5 #( + .INIT(32'hFFFFFFFE)) + led_op_r_i_4 + (.I0(cnt_reg[6]), + .I1(cnt_reg[9]), + .I2(cnt_reg[10]), + .I3(cnt_reg[8]), + .I4(cnt_reg[7]), + .O(led_op_r_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + led_op_r_reg + (.C(m_clock), + .CE(1'b1), + .D(led_op_r_i_1_n_0), + .Q(led_op), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_stub.v b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_stub.v new file mode 100644 index 0000000..59c08e3 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_stub.v @@ -0,0 +1,21 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Fri Aug 17 17:42:46 2018 +// Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_led_0_0_stub.v +// Design : design_1_led_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg225-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "led,Vivado 2018.2" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(m_clock, led_op) +/* synthesis syn_black_box black_box_pad_pin="m_clock,led_op" */; + input m_clock; + output led_op; +endmodule diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_utilization_synth.pb b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..b79f22e89be8500570be2c8a78579e7ae8d69ffe GIT binary patch literal 224 zcmd;LGcqu=&@-CEtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z9%i$7#J8F_X;yKbh@>Q^ypdH_DTXp8170kH0*X=Dg|P% zl?Rc3fno@cO literal 0 HcmV?d00001 diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_utilization_synth.rpt b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_utilization_synth.rpt new file mode 100644 index 0000000..7014123 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/design_1_led_0_0_utilization_synth.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:42:47 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_utilization -file design_1_led_0_0_utilization_synth.rpt -pb design_1_led_0_0_utilization_synth.pb +| Design : design_1_led_0_0 +| Device : 7z010clg225-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 8 | 0 | 17600 | 0.05 | +| LUT as Logic | 8 | 0 | 17600 | 0.05 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 26 | 0 | 35200 | 0.07 | +| Register as Flip Flop | 26 | 0 | 35200 | 0.07 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 26 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 54 | 0.00 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 54 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 54 | 0.00 | +| OLOGIC | 0 | 0 | 54 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 26 | Flop & Latch | +| CARRY4 | 7 | CarryLogic | +| LUT6 | 3 | LUT | +| LUT5 | 2 | LUT | +| LUT4 | 2 | LUT | +| LUT1 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/gen_run.xml b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/gen_run.xml new file mode 100644 index 0000000..e79c9f1 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/gen_run.xml @@ -0,0 +1,44 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/htr.txt b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/htr.txt new file mode 100644 index 0000000..11a5098 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log design_1_led_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_led_0_0.tcl diff --git a/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/vivado.jou b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/vivado.jou new file mode 100644 index 0000000..d6b350e --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Aug 17 17:41:53 2018 +# Process ID: 20792 +# Current directory: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_led_0_0_synth_1 +# Command line: vivado.exe -log design_1_led_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_led_0_0.tcl +# Log file: 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b/LED_Blink/LED_Blink.runs/design_1_processing_system7_0_0_synth_1/htr.txt new file mode 100644 index 0000000..43ccfd1 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_processing_system7_0_0_synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log design_1_processing_system7_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_processing_system7_0_0.tcl diff --git a/LED_Blink/LED_Blink.runs/design_1_processing_system7_0_0_synth_1/vivado.jou b/LED_Blink/LED_Blink.runs/design_1_processing_system7_0_0_synth_1/vivado.jou new file mode 100644 index 0000000..b4e6417 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/design_1_processing_system7_0_0_synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Aug 17 17:35:38 2018 +# Process ID: 13472 +# Current directory: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/design_1_processing_system7_0_0_synth_1 +# Command line: vivado.exe -log design_1_processing_system7_0_0.vds -product Vivado -mode batch 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.stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + +set_msg_config -id {HDL-1065} -limit 10000 + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + create_project -in_memory -part xc7z010clg225-1 + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.cache/wt [current_project] + set_property parent.project_path C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.xpr [current_project] + set_property ip_output_repo C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + set_property XPM_LIBRARIES {XPM_FIFO XPM_MEMORY} [current_project] + add_files -quiet C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper.dcp + set_msg_config -source 4 -id {BD 41-1661} -limit 0 + set_param project.isImplRun true + add_files C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1.bd + set_param project.isImplRun false + read_xdc C:/Users/qwpmb/Documents/summercamp2018/led.xdc + read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_bitgen_common.xdc + read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_common.xdc + read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc + read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc + read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc + read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_timing.xdc + read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/vivado_target.xdc + set_param project.isImplRun true + link_design -top design_1_wrapper -part xc7z010clg225-1 + set_param project.isImplRun false + write_hwdef -force -file design_1_wrapper.hwdef + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force design_1_wrapper_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force design_1_wrapper_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file design_1_wrapper_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force design_1_wrapper_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force design_1_wrapper_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + +start_step write_bitstream +set ACTIVE_STEP write_bitstream +set rc [catch { + create_msg_db write_bitstream.pb + set_property XPM_LIBRARIES {XPM_FIFO XPM_MEMORY} [current_project] + catch { write_mem_info -force design_1_wrapper.mmi } + write_bitstream -force design_1_wrapper.bit + catch { write_sysdef -hwdef design_1_wrapper.hwdef -bitfile design_1_wrapper.bit -meminfo design_1_wrapper.mmi -file design_1_wrapper.sysdef } + catch {write_debug_probes -quiet -force design_1_wrapper} + catch {file copy -force design_1_wrapper.ltx debug_nets.ltx} + close_msg_db -file write_bitstream.pb +} RESULT] +if {$rc} { + step_failed write_bitstream + return -code error $RESULT +} else { + end_step write_bitstream + unset ACTIVE_STEP +} + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper.vdi b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper.vdi new file mode 100644 index 0000000..954726d --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper.vdi @@ -0,0 +1,660 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Aug 17 17:43:59 2018 +# Process ID: 18056 +# Current directory: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1 +# Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace +# Log file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper.vdi +# Journal file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source design_1_wrapper.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. +add_files: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 275.211 ; gain = 38.148 +Command: link_design -top design_1_wrapper -part xc7z010clg225-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-454] Reading design checkpoint 'c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.dcp' for cell 'design_1_i/led_0' +INFO: [Project 1-454] Reading design checkpoint 'c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp' for cell 'design_1_i/processing_system7_0' +INFO: [Netlist 29-17] Analyzing 7 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2018.2 +INFO: [Device 21-403] Loading part xc7z010clg225-1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst' +Finished Parsing XDC File [c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] for cell 'design_1_i/processing_system7_0/inst' +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/led.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/led.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_bitgen_common.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_bitgen_common.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_common.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_common.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc] +WARNING: [Vivado 12-584] No ports matched 'csi_c_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:1] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:1] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_c_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_n[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:3] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:3] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_n[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:5] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:5] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:6] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:6] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:7] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:7] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:8] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:8] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_p[1]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:9] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:9] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_p[1]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:10] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:10] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:12] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:12] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_n[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'csi_c_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:15] +CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports csi_c_clk_p]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:15] +Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced. +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc] +WARNING: [Vivado 12-584] No ports matched 'hdmi_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:1] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:1] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'hdmi_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:2] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:2] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'hdmi_data_p[*]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'hdmi_data_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:5] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:5] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'hdmi_data_p[1]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:6] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:6] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'hdmi_data_p[2]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:7] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:7] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[*]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:4] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:4] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:7] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:7] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[1]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:9] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:9] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[2]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:11] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:11] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[3]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:13] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:13] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[4]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:15] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:15] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[5]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:17] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:17] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[6]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:19] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:19] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[7]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:21] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:21] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[8]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:23] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:23] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[9]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:25] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:25] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[10]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:27] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:27] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[11]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:29] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:29] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[12]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:31] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:31] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[13]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:33] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:33] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[14]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:35] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:35] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[15]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:37] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:37] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[16]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:39] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:39] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[17]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:41] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:41] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[18]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:43] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:43] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[19]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:45] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:45] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[20]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:47] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:47] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[21]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:49] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:49] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[22]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:51] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:51] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[23]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:53] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:53] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'PWM_R'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:86] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:86] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'PWM_L'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:88] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:88] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +WARNING: [Vivado 12-584] No ports matched 'PWM_*'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:89] +CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:89] +Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_timing.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_timing.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/vivado_target.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/vivado_target.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +12 Infos, 47 Warnings, 47 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 614.734 ; gain = 339.523 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 626.629 ; gain = 11.895 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 156862500 + +Time (s): cpu = 00:00:16 ; elapsed = 00:00:20 . Memory (MB): peak = 1101.488 ; gain = 474.707 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 119078520 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1101.488 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 119078520 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.120 . Memory (MB): peak = 1101.488 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 96f8efb2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.372 . Memory (MB): peak = 1101.488 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 89 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 96f8efb2 + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.426 . Memory (MB): peak = 1101.488 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 1521798de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.614 . Memory (MB): peak = 1101.488 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 1521798de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.630 . Memory (MB): peak = 1101.488 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1101.488 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 1521798de + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.643 . Memory (MB): peak = 1101.488 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 1521798de + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 1101.488 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 1521798de + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1101.488 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +28 Infos, 47 Warnings, 47 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1101.488 ; gain = 486.754 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.337 . Memory (MB): peak = 1101.488 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx +Command: report_drc -file design_1_wrapper_drc_opted.rpt -pb design_1_wrapper_drc_opted.pb -rpx design_1_wrapper_drc_opted.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1102.777 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9bd63e32 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1102.777 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1102.777 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 10f15a0e8 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1114.027 ; gain = 11.250 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 1298f0c74 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 1298f0c74 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1122.680 ; gain = 19.902 +Phase 1 Placer Initialization | Checksum: 1298f0c74 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 20bd731f8 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 2.2 Physical Synthesis In Placer +INFO: [Physopt 32-65] No nets found for high-fanout optimization. +INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. +INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1122.680 ; gain = 0.000 + +Summary of Physical Synthesis Optimizations +============================================ + + +----------------------------------------------------------------------------------------------------------------------------- +| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | +----------------------------------------------------------------------------------------------------------------------------- +| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Total | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +----------------------------------------------------------------------------------------------------------------------------- + + +Phase 2.2 Physical Synthesis In Placer | Checksum: 1147e9262 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1122.680 ; gain = 19.902 +Phase 2 Global Placement | Checksum: 13a0921c6 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 13a0921c6 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10864eb18 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 15bba2e82 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 15bba2e82 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: eb679daa + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: 110bbe024 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: 110bbe024 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 +Phase 3 Detail Placement | Checksum: 110bbe024 + +Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +INFO: [Timing 38-35] Done setting XDC timing constraints. + +Phase 4.1.1 Post Placement Optimization +Post Placement Optimization Initialization | Checksum: 14bc17437 + +Phase 4.1.1.1 BUFG Insertion +INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. +Phase 4.1.1.1 BUFG Insertion | Checksum: 14bc17437 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 +INFO: [Place 30-746] Post Placement Timing Summary WNS=16.016. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: e7b2cdb2 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 +Phase 4.1 Post Commit Optimization | Checksum: e7b2cdb2 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: e7b2cdb2 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: e7b2cdb2 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 + +Phase 4.4 Final Placement Cleanup +Phase 4.4 Final Placement Cleanup | Checksum: 1485c6970 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1485c6970 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 +Ending Placer Task | Checksum: 127e304e4 + +Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1122.680 ; gain = 19.902 +INFO: [Common 17-83] Releasing license: Implementation +49 Infos, 47 Warnings, 47 Critical Warnings and 0 Errors encountered. +place_design completed successfully +place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1122.680 ; gain = 21.191 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.213 . Memory (MB): peak = 1128.152 ; gain = 5.473 +INFO: [Common 17-1381] The checkpoint 'C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file design_1_wrapper_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1133.535 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 1133.535 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1133.535 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: aa3c114a ConstDB: 0 ShapeSum: 7da6f39a RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: fedd6a1a + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1199.941 ; gain = 66.406 +Post Restoration Checksum: NetGraph: 4b01005f NumContArr: b3dc69bb Constraints: 0 Timing: 0 + +Phase 2 Router Initialization + +Phase 2.1 Create Timer +Phase 2.1 Create Timer | Checksum: fedd6a1a + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1199.941 ; gain = 66.406 + +Phase 2.2 Fix Topology Constraints +Phase 2.2 Fix Topology Constraints | Checksum: fedd6a1a + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1205.953 ; gain = 72.418 + +Phase 2.3 Pre Route Cleanup +Phase 2.3 Pre Route Cleanup | Checksum: fedd6a1a + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1205.953 ; gain = 72.418 + Number of Nodes with overlaps = 0 + +Phase 2.4 Update Timing +Phase 2.4 Update Timing | Checksum: aa6a6345 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1208.652 ; gain = 75.117 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=15.949 | TNS=0.000 | WHS=-0.038 | THS=-0.202 | + +Phase 2 Router Initialization | Checksum: ac238b86 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 1e5d5c4eb + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 0 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=15.130 | TNS=0.000 | WHS=N/A | THS=N/A | + +Phase 4.1 Global Iteration 0 | Checksum: 1e6acfb26 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 +Phase 4 Rip-up And Reroute | Checksum: 1e6acfb26 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 + +Phase 5 Delay and Skew Optimization + +Phase 5.1 Delay CleanUp +Phase 5.1 Delay CleanUp | Checksum: 1e6acfb26 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 + +Phase 5.2 Clock Skew Optimization +Phase 5.2 Clock Skew Optimization | Checksum: 1e6acfb26 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 +Phase 5 Delay and Skew Optimization | Checksum: 1e6acfb26 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter + +Phase 6.1.1 Update Timing +Phase 6.1.1 Update Timing | Checksum: 20fe92fa7 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=15.283 | TNS=0.000 | WHS=0.237 | THS=0.000 | + +Phase 6.1 Hold Fix Iter | Checksum: 20fe92fa7 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 +Phase 6 Post Hold Fix | Checksum: 20fe92fa7 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 0.00436374 % + Global Horizontal Routing Utilization = 0.000919118 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Phase 7 Route finalize | Checksum: 25dd69eed + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1209.816 ; gain = 76.281 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: 25dd69eed + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1211.625 ; gain = 78.090 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: 1e8724916 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1211.625 ; gain = 78.090 + +Phase 10 Post Router Timing +INFO: [Route 35-57] Estimated Timing Summary | WNS=15.283 | TNS=0.000 | WHS=0.237 | THS=0.000 | + +INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. +Phase 10 Post Router Timing | Checksum: 1e8724916 + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1211.625 ; gain = 78.090 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 1211.625 ; gain = 78.090 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +66 Infos, 47 Warnings, 47 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 1211.625 ; gain = 78.090 +INFO: [Timing 38-480] Writing timing data to binary archive. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.229 . Memory (MB): peak = 1212.715 ; gain = 1.090 +INFO: [Common 17-1381] The checkpoint 'C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx +Command: report_drc -file design_1_wrapper_drc_routed.rpt -pb design_1_wrapper_drc_routed.pb -rpx design_1_wrapper_drc_routed.rpx +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx +Command: report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx +Command: report_power -file design_1_wrapper_power_routed.rpt -pb design_1_wrapper_power_summary_routed.pb -rpx design_1_wrapper_power_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +78 Infos, 47 Warnings, 47 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file design_1_wrapper_route_status.rpt -pb design_1_wrapper_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [runtcl-4] Executing : report_incremental_reuse -file design_1_wrapper_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. +INFO: [runtcl-4] Executing : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +Command: write_bitstream -force design_1_wrapper.bit +Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' +Running DRC as a precondition to command write_bitstream +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado 12-3199] DRC finished with 0 Errors +INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. +INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. +Loading data files... +Loading site data... +Loading route data... +Processing options... +Creating bitmap... +Creating bitstream... +Bitstream compression saved 14888032 bits. +Writing bitstream ./design_1_wrapper.bit... +INFO: [Vivado 12-1842] Bitgen Completed Successfully. +INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. +INFO: [Common 17-186] 'C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Fri Aug 17 17:46:05 2018. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2018.2/doc/webtalk_introduction.html. +INFO: [Common 17-83] Releasing license: Implementation +97 Infos, 47 Warnings, 47 Critical Warnings and 0 Errors encountered. +write_bitstream completed successfully +write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 1623.957 ; gain = 379.250 +INFO: [Common 17-206] Exiting Vivado at Fri Aug 17 17:46:05 2018... diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_bus_skew_routed.pb b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_bus_skew_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e GIT binary patch literal 30 lcmd;LGcqu=&@-IGEZ|gHtWcbtTCPx(T3nh_Qapp10RVJW2(bVF literal 0 HcmV?d00001 diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt new file mode 100644 index 0000000..c453f47 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:45:41 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file design_1_wrapper_bus_skew_routed.rpt -pb design_1_wrapper_bus_skew_routed.pb -rpx design_1_wrapper_bus_skew_routed.rpx +| Design : design_1_wrapper +| Device : 7z010-clg225 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt new file mode 100644 index 0000000..4d45c9f --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_clock_utilization_routed.rpt @@ -0,0 +1,154 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:45:41 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_clock_utilization -file design_1_wrapper_clock_utilization_routed.rpt +| Design : design_1_wrapper +| Device : 7z010-clg225 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +---------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +8. Clock Region Cell Placement per Global Clock: Region X0Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 48 | 0 | 0 | 0 | +| BUFIO | 0 | 8 | 0 | 0 | 0 | +| BUFMR | 0 | 4 | 0 | 0 | 0 | +| BUFR | 0 | 8 | 0 | 0 | 0 | +| MMCM | 0 | 2 | 0 | 0 | 0 | +| PLL | 0 | 2 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+--------------------------------------------------------------------------+------------------------------------------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+--------------------------------------------------------------------------+------------------------------------------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 27 | 0 | 20.000 | clk_fpga_0 | design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O | design_1_i/processing_system7_0/inst/FCLK_CLK0 | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+--------------------------------------------------------------------------+------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+-------------------------------------------------------+-------------------------------------------------------------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+-------------------------------------------------------+-------------------------------------------------------------+ +| src0 | g0 | PS7/FCLKCLK[0] | PS7_X0Y0 | PS7_X0Y0 | X0Y1 | 1 | 0 | 20.000 | clk_fpga_0 | design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] | design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | ++-----------+-----------+-----------------+------------+----------+--------------+-------------+-----------------+---------------------+--------------+-------------------------------------------------------+-------------------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 26 | 1100 | 1 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y1 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y1 | 1 | 0 | +| Y0 | 0 | 1 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+------------------------------------------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+------------------------------------------------+ +| g0 | BUFG/O | n/a | clk_fpga_0 | 20.000 | {0.000 10.000} | 27 | 0 | 0 | 0 | design_1_i/processing_system7_0/inst/FCLK_CLK0 | ++-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+------------------------------------------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+-----+ +| | X0 | X1 | ++----+----+-----+ +| Y1 | 1 | 0 | +| Y0 | 0 | 26 | ++----+----+-----+ + + +7. Clock Region Cell Placement per Global Clock: Region X1Y0 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------+ +| g0 | n/a | BUFG/O | None | 26 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/processing_system7_0/inst/FCLK_CLK0 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + +8. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------+ +| g0 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | design_1_i/processing_system7_0/inst/FCLK_CLK0 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports + +# Clock net "design_1_i/processing_system7_0/inst/FCLK_CLK0" driven by instance "design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_design_1_i/processing_system7_0/inst/FCLK_CLK0} +add_cells_to_pblock [get_pblocks {CLKAG_design_1_i/processing_system7_0/inst/FCLK_CLK0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="design_1_i/processing_system7_0/inst/FCLK_CLK0"}]]] +resize_pblock [get_pblocks {CLKAG_design_1_i/processing_system7_0/inst/FCLK_CLK0}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} +#endgroup diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_control_sets_placed.rpt b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_control_sets_placed.rpt new file mode 100644 index 0000000..d90640a --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_control_sets_placed.rpt @@ -0,0 +1,67 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:45:07 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file design_1_wrapper_control_sets_placed.rpt +| Design : design_1_wrapper +| Device : xc7z010 +--------------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 2 | +| Unused register locations in slices containing registers | 12 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 2 | 1 | +| 16+ | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 2 | 1 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 50 | 7 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++-------------------------------------------------+---------------+-----------------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++-------------------------------------------------+---------------+-----------------------------+------------------+----------------+ +| design_1_i/processing_system7_0/inst/FCLK_CLK0 | | | 1 | 2 | +| design_1_i/processing_system7_0/inst/FCLK_CLK0 | | design_1_i/led_0/inst/clear | 7 | 50 | ++-------------------------------------------------+---------------+-----------------------------+------------------+----------------+ + + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_drc_opted.pb b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_drc_opted.pb new file mode 100644 index 0000000000000000000000000000000000000000..8ebaa788697aa1bbb8ab2b30bd329d93fcb4a328 GIT binary patch literal 37 scmd;LGcqtV(KDRH% + Ruledeck: default + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_drc_routed.pb b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_drc_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..8ebaa788697aa1bbb8ab2b30bd329d93fcb4a328 GIT binary patch literal 37 scmd;LGcqtV(KDRH% + Ruledeck: default + Max violations: + Violations found: 0 ++------+----------+-------------+------------+ +| Rule | Severity | Description | Violations | ++------+----------+-------------+------------+ ++------+----------+-------------+------------+ + +2. REPORT DETAILS +----------------- + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_io_placed.rpt b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_io_placed.rpt new file mode 100644 index 0000000..7685650 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_io_placed.rpt @@ -0,0 +1,267 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:45:07 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_io -file design_1_wrapper_io_placed.rpt +| Design : design_1_wrapper +| Device : xc7z010 +| Speed File : -1 +| Package : clg225 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 87 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | DDR_dq[1] | | PS_DDR_DQ1_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| A3 | DDR_dq[7] | | PS_DDR_DQ7_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| A4 | DDR_dq[5] | | PS_DDR_DQ5_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| A5 | FIXED_IO_mio[1] | | PS_MIO1_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | +| A7 | FIXED_IO_mio[3] | | PS_MIO3_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| A8 | FIXED_IO_mio[2] | | PS_MIO2_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| A9 | FIXED_IO_mio[5] | | PS_MIO5_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| A10 | FIXED_IO_mio[6] | | PS_MIO6_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A12 | FIXED_IO_mio[30] | | PS_MIO52_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A13 | FIXED_IO_mio[26] | | PS_MIO38_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A14 | FIXED_IO_mio[23] | | PS_MIO35_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| A15 | FIXED_IO_mio[16] | | PS_MIO28_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B1 | DDR_dm[0] | | PS_DDR_DM0_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | INOUT | DIFF_SSTL135_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| B3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| B4 | DDR_dq[4] | | PS_DDR_DQ4_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | IN | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B6 | FIXED_IO_mio[8] | | PS_MIO8_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| B7 | FIXED_IO_mio[12] | | PS_MIO12_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| B8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B9 | FIXED_IO_mio[14] | | PS_MIO14_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| B10 | FIXED_IO_mio[11] | | PS_MIO11_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| B11 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| B12 | FIXED_IO_mio[28] | | PS_MIO48_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | +| B14 | FIXED_IO_mio[24] | | PS_MIO36_501 | IN | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| B15 | FIXED_IO_mio[18] | | PS_MIO30_501 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C1 | DDR_dq[3] | | PS_DDR_DQ3_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | INOUT | DIFF_SSTL135_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| C3 | DDR_dq[6] | | PS_DDR_DQ6_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| C4 | DDR_dq[2] | | PS_DDR_DQ2_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C6 | FIXED_IO_mio[13] | | PS_MIO13_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| C7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C8 | FIXED_IO_mio[4] | | PS_MIO4_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| C9 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| C10 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | +| C11 | FIXED_IO_mio[21] | | PS_MIO33_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C12 | FIXED_IO_mio[19] | | PS_MIO31_501 | IN | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C13 | FIXED_IO_mio[31] | | PS_MIO53_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C14 | FIXED_IO_mio[25] | | PS_MIO37_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| C15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D1 | DDR_dq[9] | | PS_DDR_DQ9_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| D2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D3 | DDR_dm[1] | | PS_DDR_DM1_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| D4 | DDR_dq[0] | | PS_DDR_DQ0_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| D5 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| D6 | FIXED_IO_mio[10] | | PS_MIO10_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | | +| D8 | FIXED_IO_mio[0] | | PS_MIO0_500 | IN | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D9 | FIXED_IO_mio[7] | | PS_MIO7_500 | OUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D10 | FIXED_IO_mio[15] | | PS_MIO15_500 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | | | | +| D11 | FIXED_IO_mio[17] | | PS_MIO29_501 | IN | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D13 | FIXED_IO_mio[29] | | PS_MIO49_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D14 | FIXED_IO_mio[27] | | PS_MIO39_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| D15 | FIXED_IO_mio[22] | | PS_MIO34_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| E1 | DDR_dq[8] | | PS_DDR_DQ8_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| E2 | DDR_dq[10] | | PS_DDR_DQ10_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| E3 | DDR_dq[11] | | PS_DDR_DQ11_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| E4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | | RSVDGND | GND | | | | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| E11 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | | +| E12 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | | +| E14 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | | +| E15 | FIXED_IO_mio[20] | | PS_MIO32_501 | INOUT | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | | | | +| F1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| F2 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | INOUT | DIFF_SSTL135_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| F3 | DDR_dq[12] | | PS_DDR_DQ12_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| F4 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | | +| F5 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | | +| F6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | | | | +| F7 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| F8 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| F9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| F10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F11 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| F12 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | | +| F13 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | | +| F14 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | | +| G1 | DDR_dq[13] | | PS_DDR_DQ13_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| G2 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | INOUT | DIFF_SSTL135_T_DCI | | | FAST | | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| G3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G4 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| G7 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| G8 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| G9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| G11 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| G12 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G14 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | | +| G15 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | | +| H1 | DDR_dq[14] | | PS_DDR_DQ14_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| H2 | DDR_dq[15] | | PS_DDR_DQ15_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| H3 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| H4 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | | +| H5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| H6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H7 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| H8 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| H9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| H10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H11 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| H12 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| H13 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| H15 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | | | | +| J1 | DDR_addr[10] | | PS_DDR_A10_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| J2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| J3 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | INOUT | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | | | | +| J4 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | | +| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | +| J7 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| J8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J11 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| J12 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| J13 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| J14 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| J15 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K1 | DDR_addr[14] | | PS_DDR_A14_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K2 | DDR_addr[13] | | PS_DDR_A13_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K3 | DDR_odt | | PS_DDR_ODT_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | | +| K6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K8 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | | | | +| K9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K11 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| K12 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| K13 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| K14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K15 | led_op | High Range | IO_L4N_T0_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L2 | DDR_addr[11] | | PS_DDR_A11_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L3 | DDR_cke | | PS_DDR_CKE_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L4 | DDR_reset_n | | PS_DDR_DRST_B_502 | INOUT | SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | | +| L7 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| L8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| L9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L12 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| L13 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| L14 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| L15 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| M1 | DDR_addr[2] | | PS_DDR_A2_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M2 | DDR_addr[12] | | PS_DDR_A12_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| M4 | DDR_addr[3] | | PS_DDR_A3_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M5 | DDR_addr[7] | | PS_DDR_A7_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M6 | DDR_ba[0] | | PS_DDR_BA0_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| M7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| M8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M9 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| M10 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M11 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M12 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| M13 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| M14 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M15 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| N1 | DDR_addr[1] | | PS_DDR_A1_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N2 | DDR_ck_n | | PS_DDR_CKN_502 | IN | DIFF_SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N3 | DDR_ck_p | | PS_DDR_CKP_502 | IN | DIFF_SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N4 | DDR_addr[9] | | PS_DDR_A9_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N6 | DDR_ba[2] | | PS_DDR_BA2_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| N7 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| N8 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| N9 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| N10 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| N11 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N12 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| N13 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| N14 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| N15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P1 | DDR_addr[0] | | PS_DDR_A0_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P3 | DDR_addr[4] | | PS_DDR_A4_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P4 | DDR_addr[5] | | PS_DDR_A5_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P5 | DDR_addr[6] | | PS_DDR_A6_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P6 | DDR_addr[8] | | PS_DDR_A8_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| P7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| P8 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| P9 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| P10 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| P11 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| P12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P13 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| P14 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| P15 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| R1 | DDR_ba[1] | | PS_DDR_BA1_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R2 | DDR_cs_n | | PS_DDR_CS_B_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R3 | DDR_we_n | | PS_DDR_WE_B_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | | +| R5 | DDR_cas_n | | PS_DDR_CAS_B_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R6 | DDR_ras_n | | PS_DDR_RAS_B_502 | OUT | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | | +| R7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R8 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R10 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| R11 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R12 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R13 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| R14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | | +| R15 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_methodology_drc_routed.pb b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_methodology_drc_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..1e4a6e8ad979d7f3923fa67d009abcc5d25d3af6 GIT binary patch literal 52 zcmd;LGcqtV(=(jJEajV8l98X1pOc?nso literal 0 HcmV?d00001 diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt new file mode 100644 index 0000000..e82779b --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_methodology_drc_routed.rpt @@ -0,0 +1,40 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:45:40 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_methodology -file design_1_wrapper_methodology_drc_routed.rpt -pb design_1_wrapper_methodology_drc_routed.pb -rpx design_1_wrapper_methodology_drc_routed.rpx +| Design : design_1_wrapper +| Device : xc7z010clg225-1 +| Speed File : -1 +| Design State : Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 1 ++-----------+----------+-------------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-------------------------------+------------+ +| TIMING-18 | Warning | Missing input or output delay | 1 | ++-----------+----------+-------------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-18#1 Warning +Missing input or output delay +An output delay is missing on led_op relative to clock(s) clk_fpga_0 +Related violations: + + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_opt.dcp b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_opt.dcp new file mode 100644 index 0000000000000000000000000000000000000000..38002014040eff5874072e86e6ee22f8cdf597bc GIT binary patch literal 470949 zcma%ibyOVBwsisl65JsWB)AXm77{GDI|O%k4r{31sa?DFsqU%jQIvsyh5O>gi`OsGBC+K3qJ?LFy?pV41mVRCBv`45 zu>*^Ttxe?22m3TuT%_}>OL`{x<6pRRLrV@7@7jd-Cmn{kqz=2c5~Un~uja_k@BX%qM4u?jYFVqp(yZ15GS1D!$x z*gumjGMQN`49|p=bz8+CL7Hc}iWF5E^mmXp?_6+bqhw{QCr@tTD4M|46E*1! zQMKiVy}I7XwZc+QpB)3+yu2MI#vIT4%*@W!YtZ~t^*!glmF%nCHix{05uA91yPG)i zck54(3pu1f48{L3iYAa_I0*I27fr1gFaC_JiK(-txt#%Zm(Nt>-R zF;4@_gRfuEFxeQdnzzEjY93YLSUN*kp6!`bj;wMbM@2K!fI4=@f>Xr_m4NHf)7`R% z?H4XlqjH4$(YaLshgDPcx!{Yr?&-*&z3pRn9ubn(mS>l%tJ8voC(paR#`Ox&vzx=Y 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On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Clocks | <0.001 | 4 | --- | --- | +| Slice Logic | <0.001 | 134 | --- | --- | +| LUT as Logic | <0.001 | 8 | 17600 | 0.05 | +| CARRY4 | <0.001 | 7 | 4400 | 0.16 | +| Register | <0.001 | 26 | 35200 | 0.07 | +| Others | 0.000 | 93 | --- | --- | +| Signals | <0.001 | 38 | --- | --- | +| I/O | <0.001 | 1 | 54 | 1.85 | +| PS7 | 1.172 | 1 | --- | --- | +| Static Power | 0.118 | | | | +| Total | 1.291 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 1.000 | 0.006 | 0.000 | 0.006 | +| Vccaux | 1.800 | 0.007 | 0.000 | 0.007 | +| Vcco33 | 3.300 | 0.001 | 0.000 | 0.001 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccpint | 1.000 | 0.687 | 0.661 | 0.026 | +| Vccpaux | 1.800 | 0.037 | 0.026 | 0.010 | +| Vccpll | 1.800 | 0.017 | 0.014 | 0.003 | +| Vcco_ddr | 1.350 | 0.321 | 0.319 | 0.002 | +| Vcco_mio0 | 3.300 | 0.003 | 0.002 | 0.001 | +| Vcco_mio1 | 3.300 | 0.002 | 0.001 | 0.001 | +| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | High | User specified more than 95% of clocks | | +| I/O nodes activity | High | User specified more than 95% of inputs | | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Medium | | | ++-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 11.5 | +| Airflow (LFM) | 250 | +| Heat Sink | none | +| ThetaSA (C/W) | 0.0 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 8to11 (8 to 11 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+------------------------+ + + +2.2 Clock Constraints +--------------------- + ++------------+-------------------------------------------------------------+-----------------+ +| Clock | Domain | Constraint (ns) | ++------------+-------------------------------------------------------------+-----------------+ +| clk_fpga_0 | design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | 20.0 | ++------------+-------------------------------------------------------------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++--------------------------+-----------+ +| Name | Power (W) | ++--------------------------+-----------+ +| design_1_wrapper | 1.173 | +| design_1_i | 1.172 | +| led_0 | <0.001 | +| inst | <0.001 | +| processing_system7_0 | 1.172 | +| inst | 1.172 | ++--------------------------+-----------+ + + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_power_summary_routed.pb b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_power_summary_routed.pb new file mode 100644 index 0000000000000000000000000000000000000000..7941c5ca31ba619cabf33d2304a9f9f7c301037d GIT binary patch literal 711 zcmaiyL2DC16o7Y7a}b51r=pM%Y%eWAL&c;;V?q?ADD@!qq8N53?da}IoS98cL0T<~ zco3zq1;K+97Q7XN_2S9ELJ;Xe+>3h9!u|lo9D1?No2Umb&f(+Zy*IoE@9oVMj~y=- zCRTSX&hP~yaDz46j-(Pd1^4g;ujLYtFhv~9h;pe^1zfciZBy034iU7iGp5w$Oe)c! zOzFSWC2|}~>iKR%QO*Vt%mr=}TXCV&@^7m`lzTcARg!&U?`o6beoMdXz@ejSmH41# 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All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:45:41 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file design_1_wrapper_timing_summary_routed.rpt -pb design_1_wrapper_timing_summary_routed.pb -rpx design_1_wrapper_timing_summary_routed.rpx -warn_on_violation +| Design : design_1_wrapper +| Device : 7z010-clg225 +| Speed File : -1 PRODUCTION 1.11 2014-09-11 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 0 register/latch pins with no clock. + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 0 pins that are not constrained for maximum delay. + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There are 0 input ports with no input delay specified. + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There is 1 port with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + 15.285 0.000 0 51 0.252 0.000 0 51 9.500 0.000 0 27 + + +All user specified timing constraints are met. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + +Clock Waveform(ns) Period(ns) Frequency(MHz) +----- ------------ ---------- -------------- +clk_fpga_0 {0.000 10.000} 20.000 50.000 +clk_fpga_1 {0.000 5.000} 10.000 100.000 + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- +clk_fpga_0 15.285 0.000 0 51 0.252 0.000 0 51 9.500 0.000 0 27 + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + +--------------------------------------------------------------------------------------------------- +From Clock: clk_fpga_0 + To Clock: clk_fpga_0 + +Setup : 0 Failing Endpoints, Worst Slack 15.285ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.252ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 9.500ns, Total Violation 0.000ns +--------------------------------------------------------------------------------------------------- + + +Max Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 15.285ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[24]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.961ns (logic 0.828ns (20.903%) route 3.133ns (79.097%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.023ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.768ns = ( 22.768 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.934 7.021 design_1_i/led_0/inst/clear + SLICE_X43Y43 FDRE r design_1_i/led_0/inst/cnt_reg[24]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.576 22.769 design_1_i/led_0/inst/m_clock + SLICE_X43Y43 FDRE r design_1_i/led_0/inst/cnt_reg[24]/C + clock pessimism 0.269 23.037 + clock uncertainty -0.302 22.735 + SLICE_X43Y43 FDRE (Setup_fdre_C_R) -0.429 22.306 design_1_i/led_0/inst/cnt_reg[24] + ------------------------------------------------------------------- + required time 22.306 + arrival time -7.021 + ------------------------------------------------------------------- + slack 15.285 + +Slack (MET) : 15.400ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[0]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.842ns (logic 0.828ns (21.551%) route 3.014ns (78.449%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.027ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.764ns = ( 22.764 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.815 6.902 design_1_i/led_0/inst/clear + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[0]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.572 22.764 design_1_i/led_0/inst/m_clock + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[0]/C + clock pessimism 0.269 23.033 + clock uncertainty -0.302 22.731 + SLICE_X43Y37 FDRE (Setup_fdre_C_R) -0.429 22.302 design_1_i/led_0/inst/cnt_reg[0] + ------------------------------------------------------------------- + required time 22.302 + arrival time -6.902 + ------------------------------------------------------------------- + slack 15.400 + +Slack (MET) : 15.400ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[1]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.842ns (logic 0.828ns (21.551%) route 3.014ns (78.449%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.027ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.764ns = ( 22.764 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.815 6.902 design_1_i/led_0/inst/clear + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[1]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.572 22.764 design_1_i/led_0/inst/m_clock + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[1]/C + clock pessimism 0.269 23.033 + clock uncertainty -0.302 22.731 + SLICE_X43Y37 FDRE (Setup_fdre_C_R) -0.429 22.302 design_1_i/led_0/inst/cnt_reg[1] + ------------------------------------------------------------------- + required time 22.302 + arrival time -6.902 + ------------------------------------------------------------------- + slack 15.400 + +Slack (MET) : 15.400ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[2]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.842ns (logic 0.828ns (21.551%) route 3.014ns (78.449%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.027ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.764ns = ( 22.764 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.815 6.902 design_1_i/led_0/inst/clear + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[2]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.572 22.764 design_1_i/led_0/inst/m_clock + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[2]/C + clock pessimism 0.269 23.033 + clock uncertainty -0.302 22.731 + SLICE_X43Y37 FDRE (Setup_fdre_C_R) -0.429 22.302 design_1_i/led_0/inst/cnt_reg[2] + ------------------------------------------------------------------- + required time 22.302 + arrival time -6.902 + ------------------------------------------------------------------- + slack 15.400 + +Slack (MET) : 15.400ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[3]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.842ns (logic 0.828ns (21.551%) route 3.014ns (78.449%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.027ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.764ns = ( 22.764 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.815 6.902 design_1_i/led_0/inst/clear + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[3]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.572 22.764 design_1_i/led_0/inst/m_clock + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[3]/C + clock pessimism 0.269 23.033 + clock uncertainty -0.302 22.731 + SLICE_X43Y37 FDRE (Setup_fdre_C_R) -0.429 22.302 design_1_i/led_0/inst/cnt_reg[3] + ------------------------------------------------------------------- + required time 22.302 + arrival time -6.902 + ------------------------------------------------------------------- + slack 15.400 + +Slack (MET) : 15.422ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[20]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.823ns (logic 0.828ns (21.660%) route 2.995ns (78.340%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.767ns = ( 22.767 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.795 6.883 design_1_i/led_0/inst/clear + SLICE_X43Y42 FDRE r design_1_i/led_0/inst/cnt_reg[20]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.575 22.767 design_1_i/led_0/inst/m_clock + SLICE_X43Y42 FDRE r design_1_i/led_0/inst/cnt_reg[20]/C + clock pessimism 0.269 23.036 + clock uncertainty -0.302 22.734 + SLICE_X43Y42 FDRE (Setup_fdre_C_R) -0.429 22.305 design_1_i/led_0/inst/cnt_reg[20] + ------------------------------------------------------------------- + required time 22.305 + arrival time -6.883 + ------------------------------------------------------------------- + slack 15.422 + +Slack (MET) : 15.422ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[21]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.823ns (logic 0.828ns (21.660%) route 2.995ns (78.340%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.767ns = ( 22.767 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.795 6.883 design_1_i/led_0/inst/clear + SLICE_X43Y42 FDRE r design_1_i/led_0/inst/cnt_reg[21]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.575 22.767 design_1_i/led_0/inst/m_clock + SLICE_X43Y42 FDRE r design_1_i/led_0/inst/cnt_reg[21]/C + clock pessimism 0.269 23.036 + clock uncertainty -0.302 22.734 + SLICE_X43Y42 FDRE (Setup_fdre_C_R) -0.429 22.305 design_1_i/led_0/inst/cnt_reg[21] + ------------------------------------------------------------------- + required time 22.305 + arrival time -6.883 + ------------------------------------------------------------------- + slack 15.422 + +Slack (MET) : 15.422ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[22]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.823ns (logic 0.828ns (21.660%) route 2.995ns (78.340%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.767ns = ( 22.767 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.795 6.883 design_1_i/led_0/inst/clear + SLICE_X43Y42 FDRE r design_1_i/led_0/inst/cnt_reg[22]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.575 22.767 design_1_i/led_0/inst/m_clock + SLICE_X43Y42 FDRE r design_1_i/led_0/inst/cnt_reg[22]/C + clock pessimism 0.269 23.036 + clock uncertainty -0.302 22.734 + SLICE_X43Y42 FDRE (Setup_fdre_C_R) -0.429 22.305 design_1_i/led_0/inst/cnt_reg[22] + ------------------------------------------------------------------- + required time 22.305 + arrival time -6.883 + ------------------------------------------------------------------- + slack 15.422 + +Slack (MET) : 15.422ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[23]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.823ns (logic 0.828ns (21.660%) route 2.995ns (78.340%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.024ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.767ns = ( 22.767 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.795 6.883 design_1_i/led_0/inst/clear + SLICE_X43Y42 FDRE r design_1_i/led_0/inst/cnt_reg[23]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.575 22.767 design_1_i/led_0/inst/m_clock + SLICE_X43Y42 FDRE r design_1_i/led_0/inst/cnt_reg[23]/C + clock pessimism 0.269 23.036 + clock uncertainty -0.302 22.734 + SLICE_X43Y42 FDRE (Setup_fdre_C_R) -0.429 22.305 design_1_i/led_0/inst/cnt_reg[23] + ------------------------------------------------------------------- + required time 22.305 + arrival time -6.883 + ------------------------------------------------------------------- + slack 15.422 + +Slack (MET) : 15.542ns (required time - arrival time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[4]/R + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Setup (Max at Slow Process Corner) + Requirement: 20.000ns (clk_fpga_0 rise@20.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 3.701ns (logic 0.828ns (22.371%) route 2.873ns (77.629%)) + Logic Levels: 3 (LUT5=1 LUT6=2) + Clock Path Skew: -0.026ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.766ns = ( 22.765 - 20.000 ) + Source Clock Delay (SCD): 3.060ns + Clock Pessimism Removal (CPR): 0.269ns + Clock Uncertainty: 0.302ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.600ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.207 1.207 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.752 3.060 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.456 3.516 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.862 4.378 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X42Y39 LUT5 (Prop_lut5_I2_O) 0.124 4.502 r design_1_i/led_0/inst/led_op_r_i_4/O + net (fo=2, routed) 0.676 5.178 design_1_i/led_0/inst/led_op_r_i_4_n_0 + SLICE_X42Y40 LUT6 (Prop_lut6_I0_O) 0.124 5.302 r design_1_i/led_0/inst/cnt[0]_i_4/O + net (fo=1, routed) 0.661 5.963 design_1_i/led_0/inst/cnt[0]_i_4_n_0 + SLICE_X42Y41 LUT6 (Prop_lut6_I2_O) 0.124 6.087 r design_1_i/led_0/inst/cnt[0]_i_1/O + net (fo=25, routed) 0.674 6.761 design_1_i/led_0/inst/clear + SLICE_X43Y38 FDRE r design_1_i/led_0/inst/cnt_reg[4]/R + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 20.000 20.000 r + PS7_X0Y0 PS7 0.000 20.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 1.101 21.101 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 21.192 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 1.573 22.766 design_1_i/led_0/inst/m_clock + SLICE_X43Y38 FDRE r design_1_i/led_0/inst/cnt_reg[4]/C + clock pessimism 0.269 23.034 + clock uncertainty -0.302 22.732 + SLICE_X43Y38 FDRE (Setup_fdre_C_R) -0.429 22.303 design_1_i/led_0/inst/cnt_reg[4] + ------------------------------------------------------------------- + required time 22.303 + arrival time -6.761 + ------------------------------------------------------------------- + slack 15.542 + + + + + +Min Delay Paths +-------------------------------------------------------------------------------------- +Slack (MET) : 0.252ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[3]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[3]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.357ns (logic 0.249ns (69.714%) route 0.108ns (30.286%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.227ns + Source Clock Delay (SCD): 0.930ns + Clock Pessimism Removal (CPR): 0.297ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.589 0.929 design_1_i/led_0/inst/m_clock + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[3]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y37 FDRE (Prop_fdre_C_Q) 0.141 1.071 r design_1_i/led_0/inst/cnt_reg[3]/Q + net (fo=1, routed) 0.108 1.179 design_1_i/led_0/inst/cnt_reg_n_0_[3] + SLICE_X43Y37 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.108 1.287 r design_1_i/led_0/inst/cnt_reg[0]_i_2/O[3] + net (fo=1, routed) 0.000 1.287 design_1_i/led_0/inst/cnt_reg[0]_i_2_n_4 + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.857 1.227 design_1_i/led_0/inst/m_clock + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[3]/C + clock pessimism -0.297 0.930 + SLICE_X43Y37 FDRE (Hold_fdre_C_D) 0.105 1.035 design_1_i/led_0/inst/cnt_reg[3] + ------------------------------------------------------------------- + required time -1.035 + arrival time 1.287 + ------------------------------------------------------------------- + slack 0.252 + +Slack (MET) : 0.256ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[4]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[4]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.361ns (logic 0.256ns (70.880%) route 0.105ns (29.120%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.229ns + Source Clock Delay (SCD): 0.931ns + Clock Pessimism Removal (CPR): 0.298ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.590 0.930 design_1_i/led_0/inst/m_clock + SLICE_X43Y38 FDRE r design_1_i/led_0/inst/cnt_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y38 FDRE (Prop_fdre_C_Q) 0.141 1.071 r design_1_i/led_0/inst/cnt_reg[4]/Q + net (fo=1, routed) 0.105 1.177 design_1_i/led_0/inst/cnt_reg_n_0_[4] + SLICE_X43Y38 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.115 1.292 r design_1_i/led_0/inst/cnt_reg[4]_i_1/O[0] + net (fo=1, routed) 0.000 1.292 design_1_i/led_0/inst/cnt_reg[4]_i_1_n_7 + SLICE_X43Y38 FDRE r design_1_i/led_0/inst/cnt_reg[4]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.859 1.229 design_1_i/led_0/inst/m_clock + SLICE_X43Y38 FDRE r design_1_i/led_0/inst/cnt_reg[4]/C + clock pessimism -0.298 0.931 + SLICE_X43Y38 FDRE (Hold_fdre_C_D) 0.105 1.036 design_1_i/led_0/inst/cnt_reg[4] + ------------------------------------------------------------------- + required time -1.036 + arrival time 1.292 + ------------------------------------------------------------------- + slack 0.256 + +Slack (MET) : 0.256ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[2]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[2]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.361ns (logic 0.252ns (69.733%) route 0.109ns (30.267%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.227ns + Source Clock Delay (SCD): 0.930ns + Clock Pessimism Removal (CPR): 0.297ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.589 0.929 design_1_i/led_0/inst/m_clock + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y37 FDRE (Prop_fdre_C_Q) 0.141 1.071 r design_1_i/led_0/inst/cnt_reg[2]/Q + net (fo=1, routed) 0.109 1.180 design_1_i/led_0/inst/cnt_reg_n_0_[2] + SLICE_X43Y37 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.111 1.291 r design_1_i/led_0/inst/cnt_reg[0]_i_2/O[2] + net (fo=1, routed) 0.000 1.291 design_1_i/led_0/inst/cnt_reg[0]_i_2_n_5 + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.857 1.227 design_1_i/led_0/inst/m_clock + SLICE_X43Y37 FDRE r design_1_i/led_0/inst/cnt_reg[2]/C + clock pessimism -0.297 0.930 + SLICE_X43Y37 FDRE (Hold_fdre_C_D) 0.105 1.035 design_1_i/led_0/inst/cnt_reg[2] + ------------------------------------------------------------------- + required time -1.035 + arrival time 1.291 + ------------------------------------------------------------------- + slack 0.256 + +Slack (MET) : 0.261ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[19]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[19]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.366ns (logic 0.249ns (68.025%) route 0.117ns (31.975%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.230ns + Source Clock Delay (SCD): 0.932ns + Clock Pessimism Removal (CPR): 0.298ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.591 0.932 design_1_i/led_0/inst/m_clock + SLICE_X43Y41 FDRE r design_1_i/led_0/inst/cnt_reg[19]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y41 FDRE (Prop_fdre_C_Q) 0.141 1.072 r design_1_i/led_0/inst/cnt_reg[19]/Q + net (fo=2, routed) 0.117 1.190 design_1_i/led_0/inst/cnt_reg[19] + SLICE_X43Y41 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.108 1.298 r design_1_i/led_0/inst/cnt_reg[16]_i_1/O[3] + net (fo=1, routed) 0.000 1.298 design_1_i/led_0/inst/cnt_reg[16]_i_1_n_4 + SLICE_X43Y41 FDRE r design_1_i/led_0/inst/cnt_reg[19]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.860 1.230 design_1_i/led_0/inst/m_clock + SLICE_X43Y41 FDRE r design_1_i/led_0/inst/cnt_reg[19]/C + clock pessimism -0.298 0.932 + SLICE_X43Y41 FDRE (Hold_fdre_C_D) 0.105 1.037 design_1_i/led_0/inst/cnt_reg[19] + ------------------------------------------------------------------- + required time -1.037 + arrival time 1.298 + ------------------------------------------------------------------- + slack 0.261 + +Slack (MET) : 0.264ns (arrival time - required time) + Source: design_1_i/led_0/inst/led_op_r_reg/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/led_op_r_reg/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.384ns (logic 0.209ns (54.384%) route 0.175ns (45.616%)) + Logic Levels: 1 (LUT4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.230ns + Source Clock Delay (SCD): 0.932ns + Clock Pessimism Removal (CPR): 0.298ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.591 0.932 design_1_i/led_0/inst/m_clock + SLICE_X42Y41 FDRE r design_1_i/led_0/inst/led_op_r_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y41 FDRE (Prop_fdre_C_Q) 0.164 1.095 r design_1_i/led_0/inst/led_op_r_reg/Q + net (fo=2, routed) 0.175 1.271 design_1_i/led_0/inst/led_op + SLICE_X42Y41 LUT4 (Prop_lut4_I3_O) 0.045 1.316 r design_1_i/led_0/inst/led_op_r_i_1/O + net (fo=1, routed) 0.000 1.316 design_1_i/led_0/inst/led_op_r_i_1_n_0 + SLICE_X42Y41 FDRE r design_1_i/led_0/inst/led_op_r_reg/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.860 1.230 design_1_i/led_0/inst/m_clock + SLICE_X42Y41 FDRE r design_1_i/led_0/inst/led_op_r_reg/C + clock pessimism -0.298 0.932 + SLICE_X42Y41 FDRE (Hold_fdre_C_D) 0.120 1.052 design_1_i/led_0/inst/led_op_r_reg + ------------------------------------------------------------------- + required time -1.052 + arrival time 1.316 + ------------------------------------------------------------------- + slack 0.264 + +Slack (MET) : 0.264ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[11]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[11]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.369ns (logic 0.249ns (67.424%) route 0.120ns (32.576%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.229ns + Source Clock Delay (SCD): 0.931ns + Clock Pessimism Removal (CPR): 0.298ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.590 0.930 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[11]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.141 1.071 r design_1_i/led_0/inst/cnt_reg[11]/Q + net (fo=3, routed) 0.120 1.192 design_1_i/led_0/inst/cnt_reg[11] + SLICE_X43Y39 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.108 1.300 r design_1_i/led_0/inst/cnt_reg[8]_i_1/O[3] + net (fo=1, routed) 0.000 1.300 design_1_i/led_0/inst/cnt_reg[8]_i_1_n_4 + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[11]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.859 1.229 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[11]/C + clock pessimism -0.298 0.931 + SLICE_X43Y39 FDRE (Hold_fdre_C_D) 0.105 1.036 design_1_i/led_0/inst/cnt_reg[11] + ------------------------------------------------------------------- + required time -1.036 + arrival time 1.300 + ------------------------------------------------------------------- + slack 0.264 + +Slack (MET) : 0.264ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[7]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[7]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.369ns (logic 0.249ns (67.424%) route 0.120ns (32.576%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.229ns + Source Clock Delay (SCD): 0.931ns + Clock Pessimism Removal (CPR): 0.298ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.590 0.930 design_1_i/led_0/inst/m_clock + SLICE_X43Y38 FDRE r design_1_i/led_0/inst/cnt_reg[7]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y38 FDRE (Prop_fdre_C_Q) 0.141 1.071 r design_1_i/led_0/inst/cnt_reg[7]/Q + net (fo=2, routed) 0.120 1.192 design_1_i/led_0/inst/cnt_reg[7] + SLICE_X43Y38 CARRY4 (Prop_carry4_S[3]_O[3]) + 0.108 1.300 r design_1_i/led_0/inst/cnt_reg[4]_i_1/O[3] + net (fo=1, routed) 0.000 1.300 design_1_i/led_0/inst/cnt_reg[4]_i_1_n_4 + SLICE_X43Y38 FDRE r design_1_i/led_0/inst/cnt_reg[7]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.859 1.229 design_1_i/led_0/inst/m_clock + SLICE_X43Y38 FDRE r design_1_i/led_0/inst/cnt_reg[7]/C + clock pessimism -0.298 0.931 + SLICE_X43Y38 FDRE (Hold_fdre_C_D) 0.105 1.036 design_1_i/led_0/inst/cnt_reg[7] + ------------------------------------------------------------------- + required time -1.036 + arrival time 1.300 + ------------------------------------------------------------------- + slack 0.264 + +Slack (MET) : 0.267ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[8]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[8]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.372ns (logic 0.256ns (68.766%) route 0.116ns (31.234%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.229ns + Source Clock Delay (SCD): 0.931ns + Clock Pessimism Removal (CPR): 0.298ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.590 0.930 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[8]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.141 1.071 r design_1_i/led_0/inst/cnt_reg[8]/Q + net (fo=2, routed) 0.116 1.188 design_1_i/led_0/inst/cnt_reg[8] + SLICE_X43Y39 CARRY4 (Prop_carry4_S[0]_O[0]) + 0.115 1.303 r design_1_i/led_0/inst/cnt_reg[8]_i_1/O[0] + net (fo=1, routed) 0.000 1.303 design_1_i/led_0/inst/cnt_reg[8]_i_1_n_7 + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[8]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.859 1.229 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[8]/C + clock pessimism -0.298 0.931 + SLICE_X43Y39 FDRE (Hold_fdre_C_D) 0.105 1.036 design_1_i/led_0/inst/cnt_reg[8] + ------------------------------------------------------------------- + required time -1.036 + arrival time 1.303 + ------------------------------------------------------------------- + slack 0.267 + +Slack (MET) : 0.267ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[18]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[18]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.372ns (logic 0.252ns (67.654%) route 0.120ns (32.346%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.230ns + Source Clock Delay (SCD): 0.932ns + Clock Pessimism Removal (CPR): 0.298ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.591 0.932 design_1_i/led_0/inst/m_clock + SLICE_X43Y41 FDRE r design_1_i/led_0/inst/cnt_reg[18]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y41 FDRE (Prop_fdre_C_Q) 0.141 1.072 r design_1_i/led_0/inst/cnt_reg[18]/Q + net (fo=2, routed) 0.120 1.193 design_1_i/led_0/inst/cnt_reg[18] + SLICE_X43Y41 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.111 1.304 r design_1_i/led_0/inst/cnt_reg[16]_i_1/O[2] + net (fo=1, routed) 0.000 1.304 design_1_i/led_0/inst/cnt_reg[16]_i_1_n_5 + SLICE_X43Y41 FDRE r design_1_i/led_0/inst/cnt_reg[18]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.860 1.230 design_1_i/led_0/inst/m_clock + SLICE_X43Y41 FDRE r design_1_i/led_0/inst/cnt_reg[18]/C + clock pessimism -0.298 0.932 + SLICE_X43Y41 FDRE (Hold_fdre_C_D) 0.105 1.037 design_1_i/led_0/inst/cnt_reg[18] + ------------------------------------------------------------------- + required time -1.037 + arrival time 1.304 + ------------------------------------------------------------------- + slack 0.267 + +Slack (MET) : 0.268ns (arrival time - required time) + Source: design_1_i/led_0/inst/cnt_reg[10]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Destination: design_1_i/led_0/inst/cnt_reg[10]/D + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@10.000ns period=20.000ns}) + Path Group: clk_fpga_0 + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) + Data Path Delay: 0.373ns (logic 0.252ns (67.585%) route 0.121ns (32.415%)) + Logic Levels: 1 (CARRY4=1) + Clock Path Skew: 0.000ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.229ns + Source Clock Delay (SCD): 0.931ns + Clock Pessimism Removal (CPR): 0.298ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.315 0.315 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.590 0.930 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + ------------------------------------------------------------------- ------------------- + SLICE_X43Y39 FDRE (Prop_fdre_C_Q) 0.141 1.071 r design_1_i/led_0/inst/cnt_reg[10]/Q + net (fo=2, routed) 0.121 1.192 design_1_i/led_0/inst/cnt_reg[10] + SLICE_X43Y39 CARRY4 (Prop_carry4_S[2]_O[2]) + 0.111 1.303 r design_1_i/led_0/inst/cnt_reg[8]_i_1/O[2] + net (fo=1, routed) 0.000 1.303 design_1_i/led_0/inst/cnt_reg[8]_i_1_n_5 + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/D + ------------------------------------------------------------------- ------------------- + + (clock clk_fpga_0 rise edge) + 0.000 0.000 r + PS7_X0Y0 PS7 0.000 0.000 r design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] + net (fo=1, routed) 0.341 0.341 design_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] + BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O + net (fo=27, routed) 0.859 1.229 design_1_i/led_0/inst/m_clock + SLICE_X43Y39 FDRE r design_1_i/led_0/inst/cnt_reg[10]/C + clock pessimism -0.298 0.931 + SLICE_X43Y39 FDRE (Hold_fdre_C_D) 0.105 1.036 design_1_i/led_0/inst/cnt_reg[10] + ------------------------------------------------------------------- + required time -1.036 + arrival time 1.303 + ------------------------------------------------------------------- + slack 0.268 + + + + + +Pulse Width Checks +-------------------------------------------------------------------------------------- +Clock Name: clk_fpga_0 +Waveform(ns): { 0.000 10.000 } +Period(ns): 20.000 +Sources: { design_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] } + +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a BUFG/I n/a 2.155 20.000 17.845 BUFGCTRL_X0Y0 design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/I +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y37 design_1_i/led_0/inst/cnt_reg[0]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y39 design_1_i/led_0/inst/cnt_reg[10]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y39 design_1_i/led_0/inst/cnt_reg[11]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y40 design_1_i/led_0/inst/cnt_reg[12]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y40 design_1_i/led_0/inst/cnt_reg[13]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y40 design_1_i/led_0/inst/cnt_reg[14]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y40 design_1_i/led_0/inst/cnt_reg[15]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y41 design_1_i/led_0/inst/cnt_reg[16]/C +Min Period n/a FDRE/C n/a 1.000 20.000 19.000 SLICE_X43Y42 design_1_i/led_0/inst/cnt_reg[21]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y41 design_1_i/led_0/inst/cnt_reg[16]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y42 design_1_i/led_0/inst/cnt_reg[21]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y42 design_1_i/led_0/inst/cnt_reg[22]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y42 design_1_i/led_0/inst/cnt_reg[23]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y38 design_1_i/led_0/inst/cnt_reg[4]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y38 design_1_i/led_0/inst/cnt_reg[5]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y38 design_1_i/led_0/inst/cnt_reg[6]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y38 design_1_i/led_0/inst/cnt_reg[7]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y41 design_1_i/led_0/inst/cnt_reg[17]/C +Low Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y41 design_1_i/led_0/inst/cnt_reg[18]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y43 design_1_i/led_0/inst/cnt_reg[24]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y37 design_1_i/led_0/inst/cnt_reg[0]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y37 design_1_i/led_0/inst/cnt_reg[0]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y39 design_1_i/led_0/inst/cnt_reg[10]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y39 design_1_i/led_0/inst/cnt_reg[10]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y39 design_1_i/led_0/inst/cnt_reg[11]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y39 design_1_i/led_0/inst/cnt_reg[11]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y40 design_1_i/led_0/inst/cnt_reg[12]/C +High Pulse Width Fast FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y40 design_1_i/led_0/inst/cnt_reg[12]/C +High Pulse Width Slow FDRE/C n/a 0.500 10.000 9.500 SLICE_X43Y40 design_1_i/led_0/inst/cnt_reg[13]/C + + + diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_utilization_placed.pb b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_utilization_placed.pb new file mode 100644 index 0000000000000000000000000000000000000000..a7976367558a39261eec95abee5ae74d8267fe9d GIT binary patch literal 224 zcmd;LGcqu=&@-CEtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z9%i$7#J8F_X;yKbh@>Q^ypdH_DTXp8170kH0*X=Dg|P% zm1kgRu>T7rBb<&ZRCB(yKdTB7pR2~eP~h|wNHQ?=8iB~WKyrc8QezN%tp!*YkYsQ= uYRSOh;V{XH!zt9w-8m%4=d2w_$y|FN;qVkhGQ4#Gk$YW%ghQ(vhz$S=GdrpP literal 0 HcmV?d00001 diff --git a/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_utilization_placed.rpt b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_utilization_placed.rpt new file mode 100644 index 0000000..758e2b2 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper_utilization_placed.rpt @@ -0,0 +1,207 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:45:07 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_utilization -file design_1_wrapper_utilization_placed.rpt -pb design_1_wrapper_utilization_placed.pb +| Design : design_1_wrapper +| Device : 7z010clg225-1 +| Design State : Fully Placed +----------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 8 | 0 | 17600 | 0.05 | +| LUT as Logic | 8 | 0 | 17600 | 0.05 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 26 | 0 | 35200 | 0.07 | +| Register as Flip Flop | 26 | 0 | 35200 | 0.07 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 26 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++-------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------------------------+------+-------+-----------+-------+ +| Slice | 10 | 0 | 4400 | 0.23 | +| SLICEL | 7 | 0 | | | +| SLICEM | 3 | 0 | | | +| LUT as Logic | 8 | 0 | 17600 | 0.05 | +| using O5 output only | 0 | | | | +| using O6 output only | 8 | | | | +| using O5 and O6 | 0 | | | | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| LUT Flip Flop Pairs | 2 | 0 | 17600 | 0.01 | +| fully used LUT-FF pairs | 0 | | | | +| LUT-FF pairs with one unused LUT output | 2 | | | | +| LUT-FF pairs with one unused Flip Flop | 2 | | | | +| Unique Control Sets | 2 | | | | ++-------------------------------------------+------+-------+-----------+-------+ +* Note: Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 1 | 1 | 54 | 1.85 | +| IOB Master Pads | 0 | | | | +| IOB Slave Pads | 1 | | | | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 86 | 86 | 130 | 66.15 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 54 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 54 | 0.00 | +| OLOGIC | 0 | 0 | 54 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+----------------------+ +| Ref Name | Used | Functional Category | ++----------+------+----------------------+ +| BIBUF | 86 | IO | +| FDRE | 26 | Flop & Latch | +| CARRY4 | 7 | CarryLogic | +| LUT6 | 3 | LUT | +| LUT5 | 2 | LUT | +| LUT4 | 2 | LUT | +| PS7 | 1 | Specialized Resource | +| OBUF | 1 | IO | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+----------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++---------------------------------+------+ +| Ref Name | Used | ++---------------------------------+------+ +| design_1_processing_system7_0_0 | 1 | +| design_1_led_0_0 | 1 | ++---------------------------------+------+ + + diff --git a/LED_Blink/LED_Blink.runs/impl_1/gen_run.xml b/LED_Blink/LED_Blink.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..d8f5922 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/gen_run.xml @@ -0,0 +1,168 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/impl_1/htr.txt b/LED_Blink/LED_Blink.runs/impl_1/htr.txt new file mode 100644 index 0000000..244b500 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. 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    +     diff --git a/LED_Blink/LED_Blink.runs/impl_1/vivado.jou b/LED_Blink/LED_Blink.runs/impl_1/vivado.jou new file mode 100644 index 0000000..2ddf353 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Aug 17 17:43:59 2018 +# Process ID: 18056 +# Current directory: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1 +# Command line: vivado.exe -log design_1_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source design_1_wrapper.tcl -notrace +# Log file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1/design_1_wrapper.vdi +# Journal file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/impl_1\vivado.jou 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$retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_msg_config -id {HDL-1065} -limit 10000 +create_project -in_memory -part xc7z010clg225-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.cache/wt [current_project] +set_property parent.project_path C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.xpr [current_project] +set_property XPM_LIBRARIES {XPM_FIFO XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v +add_files C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1.bd +set_property used_in_implementation false [get_files -all c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xdc] +set_property used_in_implementation false [get_files -all C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc C:/Users/qwpmb/Documents/summercamp2018/led.xdc +set_property used_in_implementation false [get_files C:/Users/qwpmb/Documents/summercamp2018/led.xdc] + +read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_bitgen_common.xdc +set_property used_in_implementation false [get_files C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_bitgen_common.xdc] + +read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_common.xdc +set_property used_in_implementation false [get_files C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_common.xdc] + +read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc +set_property used_in_implementation false [get_files C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc] + +read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc +set_property used_in_implementation false [get_files C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc] + +read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc +set_property used_in_implementation false [get_files C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc] + +read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_timing.xdc +set_property used_in_implementation false [get_files C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_timing.xdc] + +read_xdc C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/vivado_target.xdc +set_property used_in_implementation false [get_files C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/vivado_target.xdc] + +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 0 +close [open __synthesis_is_running__ w] + +synth_design -top design_1_wrapper -part xc7z010clg225-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef design_1_wrapper.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper.vds b/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper.vds new file mode 100644 index 0000000..d88260d --- /dev/null +++ b/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper.vds @@ -0,0 +1,519 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Aug 17 17:42:51 2018 +# Process ID: 20916 +# Current directory: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1 +# Command line: vivado.exe -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl +# Log file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper.vds +# Journal file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source design_1_wrapper.tcl -notrace +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'. +add_files: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 273.254 ; gain = 42.238 +Command: synth_design -top design_1_wrapper -part xc7z010clg225-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 6780 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 382.750 ; gain = 102.184 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] +INFO: [Synth 8-6157] synthesizing module 'design_1' [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-6157] synthesizing module 'design_1_led_0_0' [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/.Xil/Vivado-20916-DESKTOP-4H60MTS/realtime/design_1_led_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_led_0_0' (1#1) [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/.Xil/Vivado-20916-DESKTOP-4H60MTS/realtime/design_1_led_0_0_stub.v:6] +INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_0' [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/.Xil/Vivado-20916-DESKTOP-4H60MTS/realtime/design_1_processing_system7_0_0_stub.v:6] +INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_0' (2#1) [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/.Xil/Vivado-20916-DESKTOP-4H60MTS/realtime/design_1_processing_system7_0_0_stub.v:6] +WARNING: [Synth 8-350] instance 'processing_system7_0' of module 'design_1_processing_system7_0_0' requires 125 connections, but only 53 given [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/synth/design_1.v:87] +INFO: [Synth 8-6155] done synthesizing module 'design_1' (3#1) [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/synth/design_1.v:13] +INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (4#1) [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v:12] +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 437.102 ; gain = 156.535 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 437.102 ; gain = 156.535 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 437.102 ; gain = 156.535 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z010clg225-1 +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc] for cell 'design_1_i/processing_system7_0' +Finished Parsing XDC File [c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc] for cell 'design_1_i/processing_system7_0' +Parsing XDC File [c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0/design_1_led_0_0_in_context.xdc] for cell 'design_1_i/led_0' +Finished Parsing XDC File [c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0/design_1_led_0_0_in_context.xdc] for cell 'design_1_i/led_0' +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/led.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/led.xdc] +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/qwpmb/Documents/summercamp2018/led.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_bitgen_common.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_bitgen_common.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_common.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_common.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc] +WARNING: [Vivado 12-584] No ports matched 'csi_c_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'csi_c_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:2] +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_n[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:3] +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_n[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:4] +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:5] +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:6] +WARNING: [Vivado 12-584] No ports matched 'csi_d_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:7] +WARNING: [Vivado 12-584] No ports matched 'csi_d_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:8] +WARNING: [Vivado 12-584] No ports matched 'csi_d_p[1]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:9] +WARNING: [Vivado 12-584] No ports matched 'csi_d_p[1]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:10] +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:12] +WARNING: [Vivado 12-584] No ports matched 'csi_d_lp_n[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:13] +WARNING: [Vivado 12-584] No ports matched 'csi_c_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc:15] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc] +WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/design_1_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/design_1_wrapper_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/design_1_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc] +WARNING: [Vivado 12-584] No ports matched 'hdmi_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:1] +WARNING: [Vivado 12-584] No ports matched 'hdmi_clk_p'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:2] +WARNING: [Vivado 12-584] No ports matched 'hdmi_data_p[*]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:4] +WARNING: [Vivado 12-584] No ports matched 'hdmi_data_p[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:5] +WARNING: [Vivado 12-584] No ports matched 'hdmi_data_p[1]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:6] +WARNING: [Vivado 12-584] No ports matched 'hdmi_data_p[2]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc:7] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc] +WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/design_1_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[*]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:4] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[0]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:7] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[1]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:9] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[2]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:11] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[3]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:13] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[4]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:15] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[5]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:17] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[6]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:19] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[7]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:21] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[8]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:23] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[9]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:25] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[10]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:27] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[11]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:29] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[12]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:31] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[13]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:33] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[14]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:35] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[15]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:37] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[16]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:39] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[17]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:41] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[18]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:43] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[19]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:45] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[20]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:47] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[21]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:49] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[22]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:51] +WARNING: [Vivado 12-584] No ports matched 'gpio_1_tri_io[23]'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:53] +WARNING: [Vivado 12-584] No ports matched 'PWM_R'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:86] +WARNING: [Vivado 12-584] No ports matched 'PWM_L'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:88] +WARNING: [Vivado 12-584] No ports matched 'PWM_*'. [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc:89] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc] +WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/design_1_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_timing.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_timing.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/vivado_target.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/vivado_target.xdc] +Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/dont_touch.xdc] +Finished Parsing XDC File [C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 690.461 ; gain = 0.000 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 690.461 ; gain = 409.895 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z010clg225-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:23 . Memory (MB): peak = 690.461 ; gain = 409.895 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 5). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 6). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 7). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 8). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 9). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 10). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 11). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 12). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 13). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 14). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 15). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 16). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 17). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 18). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 19). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 20). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 21). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 22). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 23). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 24). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 25). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 26). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 27). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 28). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 29). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 30). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 31). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 32). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 33). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 34). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 35). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 36). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 37). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 38). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 39). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 40). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 41). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 42). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 43). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 44). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 45). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 46). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 47). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 48). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 49). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 50). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 51). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 52). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 53). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 54). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 55). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 56). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 57). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 58). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 59). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 60). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 61). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 62). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 63). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 64). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 65). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 66). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 67). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 68). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 69). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 70). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 71). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 72). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 73). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 74). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 75). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 76). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 77). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 78). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 79). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 80). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 81). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 82). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 83). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 84). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 85). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 86). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 87). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 88). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 89). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 90). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 91). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 92). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 93). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 94). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 95). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 96). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 97). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 98). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 99). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 100). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 101). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 102). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 103). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 104). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 105). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 106). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 107). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 108). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 109). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 110). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 111). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 112). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 113). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 114). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 115). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 116). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 117). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 118). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 119). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 120). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 121). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 122). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 123). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 124). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 125). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 126). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 127). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 128). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 129). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 130). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 131). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 132). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 133). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 134). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 135). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 136). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 137). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 138). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 139). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 140). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 141). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 142). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 143). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 144). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 145). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 146). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 147). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 148). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 149). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 150). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 151). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 152). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 153). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 154). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 155). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 156). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 157). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 158). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 159). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 160). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 161). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 162). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 163). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 164). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 165). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 166). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 167). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 168). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 169). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 170). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 171). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 172). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 173). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0/design_1_processing_system7_0_0_in_context.xdc, line 174). +Applied set_property DONT_TOUCH = true for design_1_i. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for design_1_i/processing_system7_0. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for design_1_i/led_0. (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 690.461 ; gain = 409.895 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:24 . Memory (MB): peak = 690.461 ; gain = 409.895 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 80 (col length:40) +BRAMs: 120 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:25 . Memory (MB): peak = 690.461 ; gain = 409.895 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +INFO: [Synth 8-5578] Moved timing constraint from pin 'design_1_i/processing_system7_0/FCLK_CLK0' to pin 'design_1_i/processing_system7_0/bbstub_FCLK_CLK0/O' +INFO: [Synth 8-5578] Moved timing constraint from pin 'design_1_i/processing_system7_0/FCLK_CLK1' to pin 'design_1_i/processing_system7_0/bbstub_FCLK_CLK1/O' +INFO: [Synth 8-5819] Moved 2 constraints on hierarchical pins to their respective driving/loading pins +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 754.000 ; gain = 473.434 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 754.074 ; gain = 473.508 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:41 . Memory (MB): peak = 754.074 ; gain = 473.508 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 755.199 ; gain = 474.633 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 755.199 ; gain = 474.633 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 755.199 ; gain = 474.633 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 755.199 ; gain = 474.633 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 755.199 ; gain = 474.633 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 755.199 ; gain = 474.633 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++------+--------------------------------+----------+ +| |BlackBox name |Instances | ++------+--------------------------------+----------+ +|1 |design_1_led_0_0 | 1| +|2 |design_1_processing_system7_0_0 | 1| ++------+--------------------------------+----------+ + +Report Cell Usage: ++------+--------------------------------+------+ +| |Cell |Count | ++------+--------------------------------+------+ +|1 |design_1_led_0_0 | 1| +|2 |design_1_processing_system7_0_0 | 1| +|3 |OBUF | 1| ++------+--------------------------------+------+ + +Report Instance Areas: ++------+-------------+---------+------+ +| |Instance |Module |Cells | ++------+-------------+---------+------+ +|1 |top | | 369| +|2 | design_1_i |design_1 | 368| ++------+-------------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 755.199 ; gain = 474.633 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:29 . Memory (MB): peak = 755.203 ; gain = 221.277 +Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:00:43 . Memory (MB): peak = 755.203 ; gain = 474.637 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +25 Infos, 51 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:46 . Memory (MB): peak = 776.754 ; gain = 503.500 +WARNING: [Constraints 18-5210] No constraint will be written out. +INFO: [Common 17-1381] The checkpoint 'C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb +report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 776.926 ; gain = 0.000 +INFO: [Common 17-206] Exiting Vivado at Fri Aug 17 17:43:50 2018... diff --git a/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper_utilization_synth.pb b/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..5cbc3b6dc2fe482633b65968564938e5e04ae192 GIT binary patch literal 224 zcmd;LGcqu=&@-CEtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- zk1?sTHQcw02CZG_5c6? literal 0 HcmV?d00001 diff --git a/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper_utilization_synth.rpt b/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper_utilization_synth.rpt new file mode 100644 index 0000000..618ce3c --- /dev/null +++ b/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper_utilization_synth.rpt @@ -0,0 +1,171 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +| Date : Fri Aug 17 17:43:50 2018 +| Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +| Command : report_utilization -file design_1_wrapper_utilization_synth.rpt -pb design_1_wrapper_utilization_synth.pb +| Design : design_1_wrapper +| Device : 7z010clg225-1 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 17600 | 0.00 | +| LUT as Logic | 0 | 0 | 17600 | 0.00 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 0 | 0 | 35200 | 0.00 | +| Register as Flip Flop | 0 | 0 | 35200 | 0.00 | +| Register as Latch | 0 | 0 | 35200 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 60 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 | +| RAMB18 | 0 | 0 | 120 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 80 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 1 | 0 | 54 | 1.85 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 54 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 54 | 0.00 | +| OLOGIC | 0 | 0 | 54 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| OBUF | 1 | IO | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++---------------------------------+------+ +| Ref Name | Used | ++---------------------------------+------+ +| design_1_processing_system7_0_0 | 1 | +| design_1_led_0_0 | 1 | ++---------------------------------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/LED_Blink/LED_Blink.runs/synth_1/dont_touch.xdc b/LED_Blink/LED_Blink.runs/synth_1/dont_touch.xdc new file mode 100644 index 0000000..8830142 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/synth_1/dont_touch.xdc @@ -0,0 +1,29 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# XDC: C:/Users/qwpmb/Documents/summercamp2018/led.xdc + +# XDC: C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_bitgen_common.xdc + +# XDC: C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_common.xdc + +# XDC: C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_csi.xdc + +# XDC: C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_hdmi.xdc + +# XDC: C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_te0726.xdc + +# XDC: C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/_i_timing.xdc + +# XDC: C:/Users/qwpmb/Documents/summercamp2018/zynqberrydemo1/constraints/vivado_target.xdc + +# Block Designs: bd/design_1/design_1.bd +set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==design_1 || ORIG_REF_NAME==design_1} -quiet] -quiet + +# IP: bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci +set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==design_1_processing_system7_0_0 || ORIG_REF_NAME==design_1_processing_system7_0_0} -quiet] -quiet + +# IP: bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.xci +set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==design_1_led_0_0 || ORIG_REF_NAME==design_1_led_0_0} -quiet] -quiet + +# XDC: bd/design_1/design_1_ooc.xdc diff --git a/LED_Blink/LED_Blink.runs/synth_1/gen_run.xml b/LED_Blink/LED_Blink.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..60fa0d4 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/synth_1/gen_run.xml @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LED_Blink/LED_Blink.runs/synth_1/htr.txt b/LED_Blink/LED_Blink.runs/synth_1/htr.txt new file mode 100644 index 0000000..274e434 --- /dev/null +++ b/LED_Blink/LED_Blink.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log design_1_wrapper.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl diff --git a/LED_Blink/LED_Blink.runs/synth_1/vivado.jou b/LED_Blink/LED_Blink.runs/synth_1/vivado.jou new file mode 100644 index 0000000..eba3dec --- /dev/null +++ b/LED_Blink/LED_Blink.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# Start of session at: Fri Aug 17 17:42:51 2018 +# Process ID: 20916 +# Current directory: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1 +# Command line: vivado.exe -log design_1_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_wrapper.tcl +# Log file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1/design_1_wrapper.vds +# Journal file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source design_1_wrapper.tcl -notrace diff --git a/LED_Blink/LED_Blink.runs/synth_1/vivado.pb b/LED_Blink/LED_Blink.runs/synth_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..70ba99b468bcc56cdf316234bdfa1d91de3c33d8 GIT binary patch literal 48028 zcmeG_YjYgOaaw=?!x1AR6Goi;^HkQTgl`T0Cdp(%J-HurJPHwbR9~;Bz+q zAxw0oV*_CB*D_urZPVJp7nbJWwGL6<4&GZ=G{e0{Q>TG;wZ`^AwGv5Ra&j) znx+$b7RMnHpF!Wp^Rx6nY0szigr`rVlVV*ei&Z({;Tbe3i)B%2#Gk={)=K~-P~r6U zX>UM3jZV)4$coXL1>Dipi8EtWY5LTrJ0y;(i`P-Z-Z7kwW{cR`x`9iM*}>j*Q)q5k zN~Z(NQ0gd_gSXZCeO};IeO(l*B_RQV3ArS=!*F8zga^PZdg7)7Kc*ZR?TCUhF32+x zSnk5FB~bwI!(aajhdy!1aY(!4HsF|eoj6#*x~3AtCV0)X@ETE^u0>pq!hmQ6?zPA! zyy4z*JCgYR*nJe8x=AqxeC;?2B2eGQGyc$}uq4-`ApQ)8_}5G)A4njIlE8=Tba;?v zqOAWL92z@kPo18ga49Z+i9_4rAgtWFju&)g)wC2xGYve8cgu*+xH2Ot;mu@u0e&pk zt33R~7aD;V%R)m&aUw?9^OwfZ85c$vjQf;D+GeY(djkg;fTEG*nfmmEsn|QV_%SrK zn=|9hi;ts667Igop*AR%+o0O)$~#+~_G;y_sdn4MaO{fRZMTV~D(wzcHI?fNmz#5- zfZpz3m2FFf_sp)P61yo>R$G+-l*&d+55EKwQ{J575}T_MnKAha%t2MUg1W=%m%;oBX~h^J^UX zY3?wzvAPEEjH_LRN*U%fe?lvX{ESd5U0%3(?beOul6wSIa}b{~bf;Tc$xgWt=E>_`*5+g>&{rU;L^`;+L0}A4Xild?BXX{-994 z8WrWg&c(Q32L+{upf9UJsx6VxEghV@*0{A~_>vsgY(MqrR^{k8D}v-JQe4eTr? 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    diff --git a/LED_Blink/LED_Blink.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/LED_Blink/LED_Blink.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml new file mode 100644 index 0000000..9a8f2a9 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -0,0 +1,15 @@ + +
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    diff --git a/LED_Blink/LED_Blink.sdk/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml b/LED_Blink/LED_Blink.sdk/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml new file mode 100644 index 0000000..0705825 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/.metadata/.plugins/org.eclipse.ui.workbench/workingsets.xml @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.c b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.c new file mode 100644 index 0000000..a06e306 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.c @@ -0,0 +1,13206 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF800015C[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x6 + // .. ==> 0XF800015C[25:20] = 0x00000006U + // .. ==> MASK : 0x03F00000U VAL : 0x00600000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00600701U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B00[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF800015C[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x6 + // .. ==> 0XF800015C[25:20] = 0x00000006U + // .. ==> MASK : 0x03F00000U VAL : 0x00600000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00600701U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF800015C[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x6 + // .. ==> 0XF800015C[25:20] = 0x00000006U + // .. ==> MASK : 0x03F00000U VAL : 0x00600000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00600701U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.h b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.h new file mode 100644 index 0000000..fd189b5 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 25000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 23809523 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.tcl b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.tcl new file mode 100644 index 0000000..05a88d2 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init.tcl @@ -0,0 +1,882 @@ +proc ps7_pll_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00500801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF800015C 0x03F03F33 0x00600701 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452440D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x0003C81D + mask_write 0XF8006130 0x000FFFFF 0x00036012 + mask_write 0XF8006134 0x000FFFFF 0x0003780C + mask_write 0XF8006138 0x000FFFFF 0x0003B821 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000009D + mask_write 0XF8006158 0x000FFFFF 0x00000092 + mask_write 0XF800615C 0x000FFFFF 0x0000008C + mask_write 0XF8006160 0x000FFFFF 0x000000A1 + mask_write 0XF8006168 0x001FFFFF 0x00000147 + mask_write 0XF800616C 0x001FFFFF 0x0000012D + mask_write 0XF8006170 0x001FFFFF 0x00000133 + mask_write 0XF8006174 0x001FFFFF 0x00000143 + mask_write 0XF800617C 0x000FFFFF 0x000000DD + mask_write 0XF8006180 0x000FFFFF 0x000000D2 + mask_write 0XF8006184 0x000FFFFF 0x000000CC + mask_write 0XF8006188 0x000FFFFF 0x000000E1 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B00 0x00000071 0x00000001 + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000209 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001201 + mask_write 0XF8000704 0x00003FFF 0x00001202 + mask_write 0XF8000708 0x00003FFF 0x00000202 + mask_write 0XF800070C 0x00003FFF 0x00000202 + mask_write 0XF8000710 0x00003FFF 0x00000202 + mask_write 0XF8000714 0x00003FFF 0x00000202 + mask_write 0XF8000718 0x00003FFF 0x00000202 + mask_write 0XF800071C 0x00003FFF 0x00000200 + mask_write 0XF8000720 0x00003FFF 0x00000202 + mask_write 0XF8000724 0x00003FFF 0x00001200 + mask_write 0XF8000728 0x00003FFF 0x00001200 + mask_write 0XF800072C 0x00003FFF 0x00001200 + mask_write 0XF8000730 0x00003FFF 0x00001200 + mask_write 0XF8000734 0x00003FFF 0x00001200 + mask_write 0XF8000738 0x00003FFF 0x00001200 + mask_write 0XF800073C 0x00003F01 0x00001201 + mask_write 0XF8000740 0x00003FFF 0x00002802 + mask_write 0XF8000744 0x00003FFF 0x00002802 + mask_write 0XF8000748 0x00003FFF 0x00002802 + mask_write 0XF800074C 0x00003FFF 0x00002802 + mask_write 0XF8000750 0x00003FFF 0x00002802 + mask_write 0XF8000754 0x00003FFF 0x00002802 + mask_write 0XF8000758 0x00003FFF 0x00000803 + mask_write 0XF800075C 0x00003FFF 0x00000803 + mask_write 0XF8000760 0x00003FFF 0x00000803 + mask_write 0XF8000764 0x00003FFF 0x00000803 + mask_write 0XF8000768 0x00003FFF 0x00000803 + mask_write 0XF800076C 0x00003FFF 0x00000803 + mask_write 0XF8000770 0x00003FFF 0x00000204 + mask_write 0XF8000774 0x00003FFF 0x00000205 + mask_write 0XF8000778 0x00003FFF 0x00000204 + mask_write 0XF800077C 0x00003FFF 0x00000205 + mask_write 0XF8000780 0x00003FFF 0x00000204 + mask_write 0XF8000784 0x00003FFF 0x00000204 + mask_write 0XF8000788 0x00003FFF 0x00000204 + mask_write 0XF800078C 0x00003FFF 0x00000204 + mask_write 0XF8000790 0x00003FFF 0x00000205 + mask_write 0XF8000794 0x00003FFF 0x00000204 + mask_write 0XF8000798 0x00003FFF 0x00000204 + mask_write 0XF800079C 0x00003FFF 0x00000204 + mask_write 0XF80007A0 0x00003FFF 0x00000280 + mask_write 0XF80007A4 0x00003FFF 0x00000280 + mask_write 0XF80007A8 0x00003FFF 0x00000280 + mask_write 0XF80007AC 0x00003FFF 0x00000280 + mask_write 0XF80007B0 0x00003FFF 0x00000280 + mask_write 0XF80007B4 0x00003FFF 0x00000280 + mask_write 0XF80007B8 0x00003FFF 0x00001221 + mask_write 0XF80007BC 0x00003FFF 0x00001220 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00001240 + mask_write 0XF80007CC 0x00003FFF 0x00001240 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x0000000F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_delay 0XF8F00200 1 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_delay 0XF8F00200 1 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_3_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00500801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF800015C 0x03F03F33 0x00600701 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452440D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x0003C81D + mask_write 0XF8006130 0x000FFFFF 0x00036012 + mask_write 0XF8006134 0x000FFFFF 0x0003780C + mask_write 0XF8006138 0x000FFFFF 0x0003B821 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000009D + mask_write 0XF8006158 0x000FFFFF 0x00000092 + mask_write 0XF800615C 0x000FFFFF 0x0000008C + mask_write 0XF8006160 0x000FFFFF 0x000000A1 + mask_write 0XF8006168 0x001FFFFF 0x00000147 + mask_write 0XF800616C 0x001FFFFF 0x0000012D + mask_write 0XF8006170 0x001FFFFF 0x00000133 + mask_write 0XF8006174 0x001FFFFF 0x00000143 + mask_write 0XF800617C 0x000FFFFF 0x000000DD + mask_write 0XF8006180 0x000FFFFF 0x000000D2 + mask_write 0XF8006184 0x000FFFFF 0x000000CC + mask_write 0XF8006188 0x000FFFFF 0x000000E1 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B00 0x00000303 0x00000001 + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000209 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001201 + mask_write 0XF8000704 0x00003FFF 0x00001202 + mask_write 0XF8000708 0x00003FFF 0x00000202 + mask_write 0XF800070C 0x00003FFF 0x00000202 + mask_write 0XF8000710 0x00003FFF 0x00000202 + mask_write 0XF8000714 0x00003FFF 0x00000202 + mask_write 0XF8000718 0x00003FFF 0x00000202 + mask_write 0XF800071C 0x00003FFF 0x00000200 + mask_write 0XF8000720 0x00003FFF 0x00000202 + mask_write 0XF8000724 0x00003FFF 0x00001200 + mask_write 0XF8000728 0x00003FFF 0x00001200 + mask_write 0XF800072C 0x00003FFF 0x00001200 + mask_write 0XF8000730 0x00003FFF 0x00001200 + mask_write 0XF8000734 0x00003FFF 0x00001200 + mask_write 0XF8000738 0x00003FFF 0x00001200 + mask_write 0XF800073C 0x00003F01 0x00001201 + mask_write 0XF8000740 0x00003FFF 0x00002802 + mask_write 0XF8000744 0x00003FFF 0x00002802 + mask_write 0XF8000748 0x00003FFF 0x00002802 + mask_write 0XF800074C 0x00003FFF 0x00002802 + mask_write 0XF8000750 0x00003FFF 0x00002802 + mask_write 0XF8000754 0x00003FFF 0x00002802 + mask_write 0XF8000758 0x00003FFF 0x00000803 + mask_write 0XF800075C 0x00003FFF 0x00000803 + mask_write 0XF8000760 0x00003FFF 0x00000803 + mask_write 0XF8000764 0x00003FFF 0x00000803 + mask_write 0XF8000768 0x00003FFF 0x00000803 + mask_write 0XF800076C 0x00003FFF 0x00000803 + mask_write 0XF8000770 0x00003FFF 0x00000204 + mask_write 0XF8000774 0x00003FFF 0x00000205 + mask_write 0XF8000778 0x00003FFF 0x00000204 + mask_write 0XF800077C 0x00003FFF 0x00000205 + mask_write 0XF8000780 0x00003FFF 0x00000204 + mask_write 0XF8000784 0x00003FFF 0x00000204 + mask_write 0XF8000788 0x00003FFF 0x00000204 + mask_write 0XF800078C 0x00003FFF 0x00000204 + mask_write 0XF8000790 0x00003FFF 0x00000205 + mask_write 0XF8000794 0x00003FFF 0x00000204 + mask_write 0XF8000798 0x00003FFF 0x00000204 + mask_write 0XF800079C 0x00003FFF 0x00000204 + mask_write 0XF80007A0 0x00003FFF 0x00000280 + mask_write 0XF80007A4 0x00003FFF 0x00000280 + mask_write 0XF80007A8 0x00003FFF 0x00000280 + mask_write 0XF80007AC 0x00003FFF 0x00000280 + mask_write 0XF80007B0 0x00003FFF 0x00000280 + mask_write 0XF80007B4 0x00003FFF 0x00000280 + mask_write 0XF80007B8 0x00003FFF 0x00001221 + mask_write 0XF80007BC 0x00003FFF 0x00001220 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00001240 + mask_write 0XF80007CC 0x00003FFF 0x00001240 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x0000000F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_delay 0XF8F00200 1 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_delay 0XF8F00200 1 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_2_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00500801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF800015C 0x03F03F33 0x00600701 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452440D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x0003C81D + mask_write 0XF8006130 0x000FFFFF 0x00036012 + mask_write 0XF8006134 0x000FFFFF 0x0003780C + mask_write 0XF8006138 0x000FFFFF 0x0003B821 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000009D + mask_write 0XF8006158 0x000FFFFF 0x00000092 + mask_write 0XF800615C 0x000FFFFF 0x0000008C + mask_write 0XF8006160 0x000FFFFF 0x000000A1 + mask_write 0XF8006168 0x001FFFFF 0x00000147 + mask_write 0XF800616C 0x001FFFFF 0x0000012D + mask_write 0XF8006170 0x001FFFFF 0x00000133 + mask_write 0XF8006174 0x001FFFFF 0x00000143 + mask_write 0XF800617C 0x000FFFFF 0x000000DD + mask_write 0XF8006180 0x000FFFFF 0x000000D2 + mask_write 0XF8006184 0x000FFFFF 0x000000CC + mask_write 0XF8006188 0x000FFFFF 0x000000E1 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B00 0x00000303 0x00000001 + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000209 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001201 + mask_write 0XF8000704 0x00003FFF 0x00001202 + mask_write 0XF8000708 0x00003FFF 0x00000202 + mask_write 0XF800070C 0x00003FFF 0x00000202 + mask_write 0XF8000710 0x00003FFF 0x00000202 + mask_write 0XF8000714 0x00003FFF 0x00000202 + mask_write 0XF8000718 0x00003FFF 0x00000202 + mask_write 0XF800071C 0x00003FFF 0x00000200 + mask_write 0XF8000720 0x00003FFF 0x00000202 + mask_write 0XF8000724 0x00003FFF 0x00001200 + mask_write 0XF8000728 0x00003FFF 0x00001200 + mask_write 0XF800072C 0x00003FFF 0x00001200 + mask_write 0XF8000730 0x00003FFF 0x00001200 + mask_write 0XF8000734 0x00003FFF 0x00001200 + mask_write 0XF8000738 0x00003FFF 0x00001200 + mask_write 0XF800073C 0x00003F01 0x00001201 + mask_write 0XF8000740 0x00003FFF 0x00002802 + mask_write 0XF8000744 0x00003FFF 0x00002802 + mask_write 0XF8000748 0x00003FFF 0x00002802 + mask_write 0XF800074C 0x00003FFF 0x00002802 + mask_write 0XF8000750 0x00003FFF 0x00002802 + mask_write 0XF8000754 0x00003FFF 0x00002802 + mask_write 0XF8000758 0x00003FFF 0x00000803 + mask_write 0XF800075C 0x00003FFF 0x00000803 + mask_write 0XF8000760 0x00003FFF 0x00000803 + mask_write 0XF8000764 0x00003FFF 0x00000803 + mask_write 0XF8000768 0x00003FFF 0x00000803 + mask_write 0XF800076C 0x00003FFF 0x00000803 + mask_write 0XF8000770 0x00003FFF 0x00000204 + mask_write 0XF8000774 0x00003FFF 0x00000205 + mask_write 0XF8000778 0x00003FFF 0x00000204 + mask_write 0XF800077C 0x00003FFF 0x00000205 + mask_write 0XF8000780 0x00003FFF 0x00000204 + mask_write 0XF8000784 0x00003FFF 0x00000204 + mask_write 0XF8000788 0x00003FFF 0x00000204 + mask_write 0XF800078C 0x00003FFF 0x00000204 + mask_write 0XF8000790 0x00003FFF 0x00000205 + mask_write 0XF8000794 0x00003FFF 0x00000204 + mask_write 0XF8000798 0x00003FFF 0x00000204 + mask_write 0XF800079C 0x00003FFF 0x00000204 + mask_write 0XF80007A0 0x00003FFF 0x00000280 + mask_write 0XF80007A4 0x00003FFF 0x00000280 + mask_write 0XF80007A8 0x00003FFF 0x00000280 + mask_write 0XF80007AC 0x00003FFF 0x00000280 + mask_write 0XF80007B0 0x00003FFF 0x00000280 + mask_write 0XF80007B4 0x00003FFF 0x00000280 + mask_write 0XF80007B8 0x00003FFF 0x00001221 + mask_write 0XF80007BC 0x00003FFF 0x00001220 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00001240 + mask_write 0XF80007CC 0x00003FFF 0x00001240 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x0000000F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_delay 0XF8F00200 1 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_delay 0XF8F00200 1 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_delay 0XF8F00200 1 +} +proc ps7_post_config_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_1_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init_gpl.c b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init_gpl.c new file mode 100644 index 0000000..2000dd4 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init_gpl.c @@ -0,0 +1,13197 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF800015C[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x6 + // .. ==> 0XF800015C[25:20] = 0x00000006U + // .. ==> MASK : 0x03F00000U VAL : 0x00600000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00600701U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B00[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF800015C[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x6 + // .. ==> 0XF800015C[25:20] = 0x00000006U + // .. ==> MASK : 0x03F00000U VAL : 0x00600000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00600701U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x7 + // .. ==> 0XF800015C[13:8] = 0x00000007U + // .. ==> MASK : 0x00003F00U VAL : 0x00000700U + // .. DIVISOR1 = 0x6 + // .. ==> 0XF800015C[25:20] = 0x00000006U + // .. ==> MASK : 0x03F00000U VAL : 0x00600000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00600701U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[6:6] = 0x00000001U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. CAN0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. .. START: USB1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB1 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: ENET0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. .. DATA_0_LSW = 0x800 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET0 RESET + // .. .. .. START: ENET1 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: ENET1 RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: I2C0 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C0 RESET + // .. .. .. START: I2C1 RESET + // .. .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: OUTPUT ENABLE + // .. .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: I2C1 RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init_gpl.h b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init_gpl.h new file mode 100644 index 0000000..fd189b5 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/ZC702_hw_platform/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 25000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 23809523 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 10000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.c b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.c new file mode 100644 index 0000000..3bcce86 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.c @@ -0,0 +1,10638 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.h b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.h new file mode 100644 index 0000000..bb95e06 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 166666672 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 100000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl new file mode 100644 index 0000000..d0f4463 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000158 0x00003F33 0x00000603 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000180 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FCCC0D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000000 + mask_write 0XF8006124 0x7FFFFFCF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x00007FFF 0x00000220 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x000006E0 + mask_write 0XF8000724 0x00003FFF 0x000016E1 + mask_write 0XF8000728 0x00003FFF 0x00000680 + mask_write 0XF800072C 0x00003FFF 0x00000680 + mask_write 0XF8000730 0x00003FFF 0x00000680 + mask_write 0XF8000734 0x00003FFF 0x00000680 + mask_write 0XF8000738 0x00003FFF 0x00000680 + mask_write 0XF800073C 0x00003FFF 0x00000680 + mask_write 0XF8000770 0x00003FFF 0x00001604 + mask_write 0XF8000774 0x00003FFF 0x00001605 + mask_write 0XF8000778 0x00003FFF 0x00001604 + mask_write 0XF800077C 0x00003FFF 0x00001605 + mask_write 0XF8000780 0x00003FFF 0x00001604 + mask_write 0XF8000784 0x00003FFF 0x00001604 + mask_write 0XF8000788 0x00003FFF 0x00001604 + mask_write 0XF800078C 0x00003FFF 0x00001604 + mask_write 0XF8000790 0x00003FFF 0x00001605 + mask_write 0XF8000794 0x00003FFF 0x00001604 + mask_write 0XF8000798 0x00003FFF 0x00001604 + mask_write 0XF800079C 0x00003FFF 0x00001604 + mask_write 0XF80007C0 0x00003FFF 0x00001640 + mask_write 0XF80007C4 0x00003FFF 0x00001640 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 + mask_write 0XF8000830 0x003F003F 0x00380037 + mask_write 0XF8000834 0x003F003F 0x00000039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000158 0x00003F33 0x00000603 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000180 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FCCC0D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000000 + mask_write 0XF8006124 0x7FFFFFFF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x00007FFF 0x00000220 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x000006E0 + mask_write 0XF8000724 0x00003FFF 0x000016E1 + mask_write 0XF8000728 0x00003FFF 0x00000680 + mask_write 0XF800072C 0x00003FFF 0x00000680 + mask_write 0XF8000730 0x00003FFF 0x00000680 + mask_write 0XF8000734 0x00003FFF 0x00000680 + mask_write 0XF8000738 0x00003FFF 0x00000680 + mask_write 0XF800073C 0x00003FFF 0x00000680 + mask_write 0XF8000770 0x00003FFF 0x00001604 + mask_write 0XF8000774 0x00003FFF 0x00001605 + mask_write 0XF8000778 0x00003FFF 0x00001604 + mask_write 0XF800077C 0x00003FFF 0x00001605 + mask_write 0XF8000780 0x00003FFF 0x00001604 + mask_write 0XF8000784 0x00003FFF 0x00001604 + mask_write 0XF8000788 0x00003FFF 0x00001604 + mask_write 0XF800078C 0x00003FFF 0x00001604 + mask_write 0XF8000790 0x00003FFF 0x00001605 + mask_write 0XF8000794 0x00003FFF 0x00001604 + mask_write 0XF8000798 0x00003FFF 0x00001604 + mask_write 0XF800079C 0x00003FFF 0x00001604 + mask_write 0XF80007C0 0x00003FFF 0x00001640 + mask_write 0XF80007C4 0x00003FFF 0x00001640 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 + mask_write 0XF8000830 0x003F003F 0x00380037 + mask_write 0XF8000834 0x003F003F 0x00000039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000158 0x00003F33 0x00000603 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000180 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FCCC0D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000000 + mask_write 0XF8006124 0x7FFFFFFF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x000073FF 0x00000220 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x000006E0 + mask_write 0XF8000724 0x00003FFF 0x000016E1 + mask_write 0XF8000728 0x00003FFF 0x00000680 + mask_write 0XF800072C 0x00003FFF 0x00000680 + mask_write 0XF8000730 0x00003FFF 0x00000680 + mask_write 0XF8000734 0x00003FFF 0x00000680 + mask_write 0XF8000738 0x00003FFF 0x00000680 + mask_write 0XF800073C 0x00003FFF 0x00000680 + mask_write 0XF8000770 0x00003FFF 0x00001604 + mask_write 0XF8000774 0x00003FFF 0x00001605 + mask_write 0XF8000778 0x00003FFF 0x00001604 + mask_write 0XF800077C 0x00003FFF 0x00001605 + mask_write 0XF8000780 0x00003FFF 0x00001604 + mask_write 0XF8000784 0x00003FFF 0x00001604 + mask_write 0XF8000788 0x00003FFF 0x00001604 + mask_write 0XF800078C 0x00003FFF 0x00001604 + mask_write 0XF8000790 0x00003FFF 0x00001605 + mask_write 0XF8000794 0x00003FFF 0x00001604 + mask_write 0XF8000798 0x00003FFF 0x00001604 + mask_write 0XF800079C 0x00003FFF 0x00001604 + mask_write 0XF80007C0 0x00003FFF 0x00001640 + mask_write 0XF80007C4 0x00003FFF 0x00001640 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 + mask_write 0XF8000830 0x003F003F 0x00380037 + mask_write 0XF8000834 0x003F003F 0x00000039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init_gpl.c b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init_gpl.c new file mode 100644 index 0000000..52d7d38 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init_gpl.c @@ -0,0 +1,10629 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init_gpl.h b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init_gpl.h new file mode 100644 index 0000000..bb95e06 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/design_1_wrapper_hw_platform_0/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 166666672 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 100000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git 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zxUh=iY^8a@=8^7TbW8(fA<^};dK>X^EH}$rrfp#0$-t2{GrqoQS}@M2HX%tL2IPzv zkXHVsxGgq;5My&7t6DpXyL4$$q1f6y`$N?Ub4Zb$g@UhU|B-pv!j_>OWfrRcBI_TuE|tag7w$^$fx0djjo zz%3nuZG@mt^4-*tNeMzHR>nS0kQIN5IPG_ISC$93Dd<+?pD*1!sQ z)K}~|`)${aChxk*=lESR;%>-C+@gZGOUpYq(7M;Q?76tSj6>c7C5OG?bq%;#T-gpG zAq1Ap1G%tAk(G>q=xmQZCQL3K?E32nMm000m$*3p!(2?4OU1=cdEC?Dqv5DWnLY{~ zjfBvD7Vh0qIL>ER_X*eK!%?M6y~OQ(!VURwRE=`J_GyHx+Q;C=X+E#_;ATD;ALp5e zJ6deI2A42(6TPQ}6Mf1#Q0F9w{G%VQ%ec7;EGk*f(_U$ekI5hcgSujdqkf@%pKxm$ zrive#=N(440TTYQ?{W!`d18E=4>BC*kak(tKLiI0$9Xfuxx_+gS&;e&?hx*EAC5`^ zf7y3G2Aa>k-u*p@ug^d8hkm@du4nJy(QP2yP(Zn)em|27_p@JaalaNVds`e_r?qFs zxBm4OH^NHv7t_w`U*nF$y^aOL>1V`C{+Zve=fZvcdt2SncQ%ImeIL&9`+v@~y8rnr z*>H^WzxZ(G^VM&*y4%ty)Wz!Kf8@el|8}eU8SPXO(9-v3xp05c-X +#include "platform.h" +#include "xil_printf.h" + + +int main() +{ + init_platform(); + + print("Hello World\n\r"); + + cleanup_platform(); + return 0; +} diff --git a/LED_Blink/LED_Blink.sdk/hello/src/platform.c b/LED_Blink/LED_Blink.sdk/hello/src/platform.c new file mode 100644 index 0000000..0ee2dcb --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello/src/platform.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xparameters.h" +#include "xil_cache.h" + +#include "platform_config.h" + +/* + * Uncomment one of the following two lines, depending on the target, + * if ps7/psu init source files are added in the source directory for + * compiling example outside of SDK. + */ +/*#include "ps7_init.h"*/ +/*#include "psu_init.h"*/ + +#ifdef STDOUT_IS_16550 + #include "xuartns550_l.h" + + #define UART_BAUD 9600 +#endif + +void +enable_caches() +{ +#ifdef __PPC__ + Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK); + Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK); +#elif __MICROBLAZE__ +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheEnable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheEnable(); +#endif +#endif +} + +void +disable_caches() +{ +#ifdef __MICROBLAZE__ +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheDisable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheDisable(); +#endif +#endif +} + +void +init_uart() +{ +#ifdef STDOUT_IS_16550 + XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD); + XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); +#endif + /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */ +} + +void +init_platform() +{ + /* + * If you want to run this example outside of SDK, + * uncomment one of the following two lines and also #include "ps7_init.h" + * or #include "ps7_init.h" at the top, depending on the target. + * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included + * along with this example source files for compilation. + */ + /* ps7_init();*/ + /* psu_init();*/ + enable_caches(); + init_uart(); +} + +void +cleanup_platform() +{ + disable_caches(); +} diff --git a/LED_Blink/LED_Blink.sdk/hello/src/platform.h b/LED_Blink/LED_Blink.sdk/hello/src/platform.h new file mode 100644 index 0000000..e273e37 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello/src/platform.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef __PLATFORM_H_ +#define __PLATFORM_H_ + +#include "platform_config.h" + +void init_platform(); +void cleanup_platform(); + +#endif diff --git a/LED_Blink/LED_Blink.sdk/hello/src/platform_config.h b/LED_Blink/LED_Blink.sdk/hello/src/platform_config.h new file mode 100644 index 0000000..3e9b7f1 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello/src/platform_config.h @@ -0,0 +1,6 @@ +#ifndef __PLATFORM_CONFIG_H_ +#define __PLATFORM_CONFIG_H_ + +#define STDOUT_IS_PS7_UART +#define UART_DEVICE_ID 0 +#endif diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h new file mode 100644 index 0000000..2cee66b --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h @@ -0,0 +1,312 @@ +/****************************************************************************** +* +* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +****************************************************************************** +* +* _program_timer_hw.h: +* Timer related functions +* +******************************************************************************/ + +#ifndef PROFILE_TIMER_HW_H +#define PROFILE_TIMER_HW_H + +#include "profile.h" + +#ifdef PROC_PPC +#if defined __GNUC__ +# define SYNCHRONIZE_IO __asm__ volatile ("eieio") +#elif defined __DCC__ +# define SYNCHRONIZE_IO __asm volatile(" eieio") +#else +# define SYNCHRONIZE_IO +#endif +#endif + +#ifdef PROC_PPC +#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; } +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; } +#else +#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr)); +#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); } +#endif + +#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\ + ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + \ + (u32)(RegOffset)), (u32)(ValueToWrite)) + +#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset) \ + ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset)) + +#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\ + ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET, \ + (RegisterValue)) + +#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber) \ + ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET) + + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef PROC_PPC +#include "xexception_l.h" +#include "xtime_l.h" +#include "xpseudo_asm.h" +#endif + +#ifdef TIMER_CONNECT_INTC +#include "xintc_l.h" +#include "xintc.h" +#endif /* TIMER_CONNECT_INTC */ + +#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9) +#include "xtmrctr_l.h" +#endif + +#ifdef PROC_CORTEXA9 +#include "xscutimer_hw.h" +#include "xscugic.h" +#endif + +extern u32 timer_clk_ticks ; + +/*-------------------------------------------------------------------- + * PowerPC Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_PPC + +#ifdef PPC_PIT_INTERRUPT +u32 timer_lo_clk_ticks ; /* Clk ticks when Timer is disabled in CG */ +#endif + +#ifdef PROC_PPC440 +#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE +#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS +#define XREG_SPR_PIT XREG_SPR_DEC +#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT +#endif + +/* -------------------------------------------------------------------- + * Disable the Timer - During Profiling + * + * For PIT Timer - + * 1. XTime_PITDisableInterrupt() ; + * 2. Store the remaining timer clk tick + * 3. Stop the PIT Timer + *-------------------------------------------------------------------- */ + +#ifdef PPC_PIT_INTERRUPT +#define disable_timer() \ + { \ + u32 val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE)); \ + timer_lo_clk_ticks = mfspr(XREG_SPR_PIT); \ + mtspr(XREG_SPR_PIT, 0); \ + } +#else +#define disable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +/* -------------------------------------------------------------------- + * Enable the Timer + * + * For PIT Timer - + * 1. Load the remaining timer clk ticks + * 2. XTime_PITEnableInterrupt() ; + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +#define enable_timer() \ + { \ + u32 val; \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_PIT, timer_lo_clk_ticks); \ + mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \ + } +#else +#define enable_timer() \ + { \ + u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(addr); \ + tmp_v = tmp_v | XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \ + } +#endif + + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + * For PIT Timer - + * 1. Load the timer clk ticks + * 2. Enable AutoReload and Interrupt + * 3. Clear PIT Timer Status bits + *-------------------------------------------------------------------- */ +#ifdef PPC_PIT_INTERRUPT +#define timer_ack() \ + { \ + u32 val; \ + mtspr(XREG_SPR_PIT, timer_clk_ticks); \ + mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS); \ + val=mfspr(XREG_SPR_TCR); \ + mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \ + } +#else +#define timer_ack() \ + { \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0); \ + ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr); \ + } +#endif + +/*-------------------------------------------------------------------- */ +#endif /* PROC_PPC */ +/* -------------------------------------------------------------------- */ + + + + +/* -------------------------------------------------------------------- + * MicroBlaze Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_MICROBLAZE + +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define disable_timer() \ + { \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = ProfIo_In32(Addr); \ + tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \ + u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \ + OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + OutAddr += (u32)XTC_TCSR_OFFSET; \ + ProfIo_Out32(OutAddr, (u32)tmp_v); \ + } + + +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define enable_timer() \ + { \ + u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \ + Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \ + Addr += (u32)XTC_TCSR_OFFSET; \ + u32 tmp_v = (u32)ProfIo_In32(Addr); \ + tmp_v = tmp_v | (u32)XTC_CSR_ENABLE_TMR_MASK; \ + ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \ + } + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ + { \ + u32 csr; \ + csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0); \ + ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr); \ + } + +/*-------------------------------------------------------------------- */ +#endif /* PROC_MICROBLAZE */ +/*-------------------------------------------------------------------- */ + +/* -------------------------------------------------------------------- + * Cortex A9 Target - Timer related functions + *-------------------------------------------------------------------- */ +#ifdef PROC_CORTEXA9 + +/* -------------------------------------------------------------------- + * Disable the Timer during Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define disable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} + + +/* -------------------------------------------------------------------- + * Enable the Timer after Call-Graph Data collection + * + *-------------------------------------------------------------------- */ +#define enable_timer() \ +{ \ + u32 Reg; \ + Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \ + Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \ + Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\ +} + + +/* -------------------------------------------------------------------- + * Send Ack to Timer Interrupt + * + *-------------------------------------------------------------------- */ +#define timer_ack() \ +{ \ + Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \ + (u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\ +} + +/*-------------------------------------------------------------------- */ +#endif /* PROC_CORTEXA9 */ +/*-------------------------------------------------------------------- */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/bspconfig.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/bspconfig.h new file mode 100644 index 0000000..9427ad0 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/bspconfig.h @@ -0,0 +1,45 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Configurations for Standalone BSP +* +*******************************************************************/ + +#ifndef BSPCONFIG_H /* prevent circular inclusions */ +#define BSPCONFIG_H /* by using protection macros */ + +#define MICROBLAZE_PVR_NONE + +#endif /*end of __BSPCONFIG_H_*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h new file mode 100644 index 0000000..7096a92 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h @@ -0,0 +1,54 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + + +#ifndef _MBLAZE_NT_TYPES_H +#define _MBLAZE_NT_TYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef char byte; +typedef short half; +typedef int word; +typedef unsigned char ubyte; +typedef unsigned short uhalf; +typedef unsigned int uword; +typedef ubyte boolean; + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/profile.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/profile.h new file mode 100644 index 0000000..4cb07a7 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/profile.h @@ -0,0 +1,131 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef PROFILE_H +#define PROFILE_H 1 + +#include +#include "xil_types.h" +#include "profile_config.h" + +#ifdef PROC_MICROBLAZE +#include "mblaze_nt_types.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void _system_init( void ) ; +void _system_clean( void ) ; +void mcount(u32 frompc, u32 selfpc); +void profile_intr_handler( void ) ; +void _profile_init( void ); + + + +/**************************************************************************** + * Profiling on hardware - Hash table maintained on hardware and data sent + * to xmd for gmon.out generation. + ****************************************************************************/ +/* + * histogram counters are unsigned shorts (according to the kernel). + */ +#define HISTCOUNTER u16 + +struct tostruct { + u32 selfpc; + s32 count; + s16 link; + u16 pad; +}; + +struct fromstruct { + u32 frompc ; + s16 link ; + u16 pad ; +} ; + +/* + * general rounding functions. + */ +#define ROUNDDOWN(x,y) (((x)/(y))*(y)) +#define ROUNDUP(x,y) ((((x)+(y)-1)/(y))*(y)) + +/* + * The profiling data structures are housed in this structure. + */ +struct gmonparam { + s32 state; + + /* Histogram Information */ + u16 *kcount; /* No. of bins in histogram */ + u32 kcountsize; /* Histogram samples */ + + /* Call-graph Information */ + struct fromstruct *froms; + u32 fromssize; + struct tostruct *tos; + u32 tossize; + + /* Initialization I/Ps */ + u32 lowpc; + u32 highpc; + u32 textsize; + /* u32 cg_froms, */ + /* u32 cg_tos, */ +}; +extern struct gmonparam *_gmonparam; +extern s32 n_gmon_sections; + +/* + * Possible states of profiling. + */ +#define GMON_PROF_ON 0 +#define GMON_PROF_BUSY 1 +#define GMON_PROF_ERROR 2 +#define GMON_PROF_OFF 3 + +/* + * Sysctl definitions for extracting profiling information from the kernel. + */ +#define GPROF_STATE 0 /* int: profiling enabling variable */ +#define GPROF_COUNT 1 /* struct: profile tick count buffer */ +#define GPROF_FROMS 2 /* struct: from location hash bucket */ +#define GPROF_TOS 3 /* struct: destination/count structure */ +#define GPROF_GMONPARAM 4 /* struct: profiling parameters (see above) */ + +#ifdef __cplusplus +} +#endif + +#endif /* PROFILE_H */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/sleep.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/sleep.h new file mode 100644 index 0000000..f53b2d8 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/sleep.h @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file sleep.h +* +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. +* +* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6   srm  11/02/17 Added processor specific sleep rountines
+*								 function prototypes.
+*
+*
    +* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/** +* +* This macro polls an address periodically until a condition is met or till the +* timeout occurs. +* The minimum timeout for calling this macro is 100us. If the timeout is less +* than 100us, it still waits for 100us. Also the unit for the timeout is 100us. +* If the timeout is not a multiple of 100us, it waits for a timeout of +* the next usec value which is a multiple of 100us. +* +* @param IO_func - accessor function to read the register contents. +* Depends on the register width. +* @param ADDR - Address to be polled +* @param VALUE - variable to read the value +* @param COND - Condition to checked (usually involves VALUE) +* @param TIMEOUT_US - timeout in micro seconds +* +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period +* +* @note none +* +*****************************************************************************/ +#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \ + ( { \ + u64 timeout = TIMEOUT_US/100; \ + if(TIMEOUT_US%100!=0) \ + timeout++; \ + for(;;) { \ + VALUE = IO_func(ADDR); \ + if(COND) \ + break; \ + else { \ + usleep(100); \ + timeout--; \ + if(timeout==0) \ + break; \ + } \ + } \ + (timeout>0) ? 0 : -1; \ + } ) + +void usleep(unsigned long useconds); +void sleep(unsigned int seconds); +int usleep_R5(unsigned long useconds); +unsigned sleep_R5(unsigned int seconds); +int usleep_MB(unsigned long useconds); +unsigned sleep_MB(unsigned int seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/smc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/smc.h new file mode 100644 index 0000000..5a4d336 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/smc.h @@ -0,0 +1,114 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file smc.h +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+*					  as smc.c is removed
+*
    +* +* @note None. +* +******************************************************************************/ + +#ifndef SMC_H /* prevent circular inclusions */ +#define SMC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xil_io.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory controller configuration register offset */ +#define XSMCPSS_MC_STATUS 0x000U /* Controller status reg, RO */ +#define XSMCPSS_MC_INTERFACE_CONFIG 0x004U /* Interface config reg, RO */ +#define XSMCPSS_MC_SET_CONFIG 0x008U /* Set configuration reg, WO */ +#define XSMCPSS_MC_CLR_CONFIG 0x00CU /* Clear config reg, WO */ +#define XSMCPSS_MC_DIRECT_CMD 0x010U /* Direct command reg, WO */ +#define XSMCPSS_MC_SET_CYCLES 0x014U /* Set cycles register, WO */ +#define XSMCPSS_MC_SET_OPMODE 0x018U /* Set opmode register, WO */ +#define XSMCPSS_MC_REFRESH_PERIOD_0 0x020U /* Refresh period_0 reg, RW */ +#define XSMCPSS_MC_REFRESH_PERIOD_1 0x024U /* Refresh period_1 reg, RW */ + +/* Chip select configuration register offset */ +#define XSMCPSS_CS_IF0_CHIP_0_OFFSET 0x100U /* Interface 0 chip 0 config */ +#define XSMCPSS_CS_IF0_CHIP_1_OFFSET 0x120U /* Interface 0 chip 1 config */ +#define XSMCPSS_CS_IF0_CHIP_2_OFFSET 0x140U /* Interface 0 chip 2 config */ +#define XSMCPSS_CS_IF0_CHIP_3_OFFSET 0x160U /* Interface 0 chip 3 config */ +#define XSMCPSS_CS_IF1_CHIP_0_OFFSET 0x180U /* Interface 1 chip 0 config */ +#define XSMCPSS_CS_IF1_CHIP_1_OFFSET 0x1A0U /* Interface 1 chip 1 config */ +#define XSMCPSS_CS_IF1_CHIP_2_OFFSET 0x1C0U /* Interface 1 chip 2 config */ +#define XSMCPSS_CS_IF1_CHIP_3_OFFSET 0x1E0U /* Interface 1 chip 3 config */ + +/* User configuration register offset */ +#define XSMCPSS_UC_STATUS_OFFSET 0x200U /* User status reg, RO */ +#define XSMCPSS_UC_CONFIG_OFFSET 0x204U /* User config reg, WO */ + +/* Integration test register offset */ +#define XSMCPSS_IT_OFFSET 0xE00U + +/* ID configuration register offset */ +#define XSMCPSS_ID_PERIP_0_OFFSET 0xFE0U +#define XSMCPSS_ID_PERIP_1_OFFSET 0xFE4U +#define XSMCPSS_ID_PERIP_2_OFFSET 0xFE8U +#define XSMCPSS_ID_PERIP_3_OFFSET 0xFECU +#define XSMCPSS_ID_PCELL_0_OFFSET 0xFF0U +#define XSMCPSS_ID_PCELL_1_OFFSET 0xFF4U +#define XSMCPSS_ID_PCELL_2_OFFSET 0xFF8U +#define XSMCPSS_ID_PCELL_3_OFFSET 0xFFCU + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SMC_H */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/vectors.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/vectors.h new file mode 100644 index 0000000..bb599b5 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/vectors.h @@ -0,0 +1,88 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file vectors.h +* +* This file contains the C level vector prototypes for the ARM Cortex A9 core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _VECTORS_H_ +#define _VECTORS_H_ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void FIQInterrupt(void); +void IRQInterrupt(void); +#if !defined (__aarch64__) +void SWInterrupt(void); +void DataAbortInterrupt(void); +void PrefetchAbortInterrupt(void); +void UndefinedException(void); +#else +void SynchronousInterrupt(void); +void SErrorInterrupt(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps.h new file mode 100644 index 0000000..549bfff --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps.h @@ -0,0 +1,591 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xadcps.h +* @addtogroup xadcps_v2_2 +* @{ +* @details +* +* The XAdcPs driver supports the Xilinx XADC/ADC device. +* +* The XADC/ADC device has the following features: +* - 10-bit, 200-KSPS (kilo samples per second) +* Analog-to-Digital Converter (ADC) +* - Monitoring of on-chip supply voltages and temperature +* - 1 dedicated differential analog-input pair and +* 16 auxiliary differential analog-input pairs +* - Automatic alarms based on user defined limits for the on-chip +* supply voltages and temperature +* - Automatic Channel Sequencer, programmable averaging, programmable +* acquisition time for the external inputs, unipolar or differential +* input selection for the external inputs +* - Inbuilt Calibration +* - Optional interrupt request generation +* +* +* The user should refer to the hardware device specification for detailed +* information about the device. +* +* This header file contains the prototypes of driver functions that can +* be used to access the XADC/ADC device. +* +* +* XADC Channel Sequencer Modes +* +* The XADC Channel Sequencer supports the following operating modes: +* +* - Default : This is the default mode after power up. +* In this mode of operation the XADC operates in +* a sequence mode, monitoring the on chip sensors: +* Temperature, VCCINT, and VCCAUX. +* - One pass through sequence : In this mode the XADC +* converts the channels enabled in the Sequencer Channel Enable +* registers for a single pass and then stops. +* - Continuous cycling of sequence : In this mode the XADC +* converts the channels enabled in the Sequencer Channel Enable +* registers continuously. +* - Single channel mode: In this mode the XADC Channel +* Sequencer is disabled and the XADC operates in a +* Single Channel Mode. +* The XADC can operate either in a Continuous or Event +* driven sampling mode in the single channel mode. +* - Simultaneous Sampling Mode: In this mode the XADC Channel +* Sequencer will automatically sequence through eight fixed pairs +* of auxiliary analog input channels for simulataneous conversion. +* - Independent ADC mode: In this mode the first ADC (A) is used to +* is used to implement a fixed monitoring mode similar to the +* default mode but the alarm fucntions ar eenabled. +* The second ADC (B) is available to be used with external analog +* input channels only. +* +* Read the XADC spec for more information about the sequencer modes. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the XADC/ADC device. +* +* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC +* device. The user needs to first call the XAdcPs_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XAdcPs_CfgInitialize() API. +* +* +* Interrupts +* +* The XADC/ADC device supports interrupt driven mode and the default +* operation mode is polling mode. +* +* The interrupt mode is available only if hardware is configured to support +* interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* device in interrupt mode. +* +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* +* Building the driver +* +* The XAdcPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* Limitations of the driver +* +* XADC/ADC device can be accessed through the JTAG port and the PLB +* interface. The driver implementation does not support the simultaneous access +* of the device by both these interfaces. The user has to care of this situation +* in the user application code. +* +*

    +* +* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+*			functions.
+*			Modified Assert for XAdcPs_SetSingleChParams in
+*			xadcps.c to fix CR #807563.
+* 2.2   bss    04/27/14 Modified to use correct Device Config base address in
+*						xadcps.c (CR#854437).
+*       ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*       ms     04/05/17 Modified Comment lines in functions of xadcps
+*                       examples to recognize it as documentation block
+*                       for doxygen generation.
+*
+*
    +* +*****************************************************************************/ +#ifndef XADCPS_H /* Prevent circular inclusions */ +#define XADCPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xadcps_hw.h" + +/************************** Constant Definitions ****************************/ + + +/** + * @name Indexes for the different channels. + * @{ + */ +#define XADCPS_CH_TEMP 0x0 /**< On Chip Temperature */ +#define XADCPS_CH_VCCINT 0x1 /**< VCCINT */ +#define XADCPS_CH_VCCAUX 0x2 /**< VCCAUX */ +#define XADCPS_CH_VPVN 0x3 /**< VP/VN Dedicated analog inputs */ +#define XADCPS_CH_VREFP 0x4 /**< VREFP */ +#define XADCPS_CH_VREFN 0x5 /**< VREFN */ +#define XADCPS_CH_VBRAM 0x6 /**< On-chip VBRAM Data Reg, 7 series */ +#define XADCPS_CH_SUPPLY_CALIB 0x07 /**< Supply Calib Data Reg */ +#define XADCPS_CH_ADC_CALIB 0x08 /**< ADC Offset Channel Reg */ +#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg */ +#define XADCPS_CH_VCCPINT 0x0D /**< On-chip PS VCCPINT Channel , Zynq */ +#define XADCPS_CH_VCCPAUX 0x0E /**< On-chip PS VCCPAUX Channel , Zynq */ +#define XADCPS_CH_VCCPDRO 0x0F /**< On-chip PS VCCPDRO Channel , Zynq */ +#define XADCPS_CH_AUX_MIN 16 /**< Channel number for 1st Aux Channel */ +#define XADCPS_CH_AUX_MAX 31 /**< Channel number for Last Aux channel */ + +/*@}*/ + + +/** + * @name Indexes for reading the Calibration Coefficient Data. + * @{ + */ +#define XADCPS_CALIB_SUPPLY_COEFF 0 /**< Supply Offset Calib Coefficient */ +#define XADCPS_CALIB_ADC_COEFF 1 /**< ADC Offset Calib Coefficient */ +#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/ +/*@}*/ + + +/** + * @name Indexes for reading the Minimum/Maximum Measurement Data. + * @{ + */ +#define XADCPS_MAX_TEMP 0 /**< Maximum Temperature Data */ +#define XADCPS_MAX_VCCINT 1 /**< Maximum VCCINT Data */ +#define XADCPS_MAX_VCCAUX 2 /**< Maximum VCCAUX Data */ +#define XADCPS_MAX_VBRAM 3 /**< Maximum VBRAM Data */ +#define XADCPS_MIN_TEMP 4 /**< Minimum Temperature Data */ +#define XADCPS_MIN_VCCINT 5 /**< Minimum VCCINT Data */ +#define XADCPS_MIN_VCCAUX 6 /**< Minimum VCCAUX Data */ +#define XADCPS_MIN_VBRAM 7 /**< Minimum VBRAM Data */ +#define XADCPS_MAX_VCCPINT 8 /**< Maximum VCCPINT Register , Zynq */ +#define XADCPS_MAX_VCCPAUX 9 /**< Maximum VCCPAUX Register , Zynq */ +#define XADCPS_MAX_VCCPDRO 0xA /**< Maximum VCCPDRO Register , Zynq */ +#define XADCPS_MIN_VCCPINT 0xC /**< Minimum VCCPINT Register , Zynq */ +#define XADCPS_MIN_VCCPAUX 0xD /**< Minimum VCCPAUX Register , Zynq */ +#define XADCPS_MIN_VCCPDRO 0xE /**< Minimum VCCPDRO Register , Zynq */ + +/*@}*/ + + +/** + * @name Alarm Threshold(Limit) Register (ATR) indexes. + * @{ + */ +#define XADCPS_ATR_TEMP_UPPER 0 /**< High user Temperature */ +#define XADCPS_ATR_VCCINT_UPPER 1 /**< VCCINT high voltage limit register */ +#define XADCPS_ATR_VCCAUX_UPPER 2 /**< VCCAUX high voltage limit register */ +#define XADCPS_ATR_OT_UPPER 3 /**< VCCAUX high voltage limit register */ +#define XADCPS_ATR_TEMP_LOWER 4 /**< Upper Over Temperature limit Reg */ +#define XADCPS_ATR_VCCINT_LOWER 5 /**< VCCINT high voltage limit register */ +#define XADCPS_ATR_VCCAUX_LOWER 6 /**< VCCAUX low voltage limit register */ +#define XADCPS_ATR_OT_LOWER 7 /**< Lower Over Temperature limit */ +#define XADCPS_ATR_VBRAM_UPPER_ 8 /**< VRBAM Upper Alarm Reg, 7 Series */ +#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */ +#define XADCPS_ATR_VBRAM_LOWER 0xC /**< VRBAM Lower Alarm Reg, 7 Series */ +#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */ +#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */ +#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */ + +/*@}*/ + + +/** + * @name Averaging to be done for the channels. + * @{ + */ +#define XADCPS_AVG_0_SAMPLES 0 /**< No Averaging */ +#define XADCPS_AVG_16_SAMPLES 1 /**< Average 16 samples */ +#define XADCPS_AVG_64_SAMPLES 2 /**< Average 64 samples */ +#define XADCPS_AVG_256_SAMPLES 3 /**< Average 256 samples */ + +/*@}*/ + + +/** + * @name Channel Sequencer Modes of operation + * @{ + */ +#define XADCPS_SEQ_MODE_SAFE 0 /**< Default Safe Mode */ +#define XADCPS_SEQ_MODE_ONEPASS 1 /**< Onepass through Sequencer */ +#define XADCPS_SEQ_MODE_CONTINPASS 2 /**< Continuous Cycling Sequencer */ +#define XADCPS_SEQ_MODE_SINGCHAN 3 /**< Single channel -No Sequencing */ +#define XADCPS_SEQ_MODE_SIMUL_SAMPLING 4 /**< Simultaneous sampling */ +#define XADCPS_SEQ_MODE_INDEPENDENT 8 /**< Independent mode */ + +/*@}*/ + + + +/** + * @name Power Down Modes + * @{ + */ +#define XADCPS_PD_MODE_NONE 0 /**< No Power Down */ +#define XADCPS_PD_MODE_ADCB 1 /**< Power Down ADC B */ +#define XADCPS_PD_MODE_XADC 2 /**< Power Down ADC A and ADC B */ +/*@}*/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the XADC/ADC + * device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Device base address */ +} XAdcPs_Config; + + +/** + * The driver's instance data. The user is required to allocate a variable + * of this type for every XADC/ADC device in the system. A pointer to + * a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XAdcPs_Config Config; /**< XAdcPs_Config of current device */ + u32 IsReady; /**< Device is initialized and ready */ + +} XAdcPs; + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the XADC device is in Event Sampling mode. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - TRUE if the device is in Event Sampling Mode. +* - FALSE if the device is in Continuous Sampling Mode. +* +* @note C-Style signature: +* int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_IsEventSamplingModeSet(InstancePtr) \ + (((XAdcPs_ReadInternalReg(InstancePtr, \ + XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ? \ + TRUE : FALSE)) + + +/****************************************************************************/ +/** +* +* This macro checks if the XADC device is in External Mux mode. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - TRUE if the device is in External Mux Mode. +* - FALSE if the device is NOT in External Mux Mode. +* +* @note C-Style signature: +* int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_IsExternalMuxModeSet(InstancePtr) \ + (((XAdcPs_ReadInternalReg(InstancePtr, \ + XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ? \ + TRUE : FALSE)) + +/****************************************************************************/ +/** +* +* This macro converts XADC Raw Data to Temperature(centigrades). +* +* @param AdcData is the Raw ADC Data from XADC. +* +* @return The Temperature in centigrades. +* +* @note C-Style signature: +* float XAdcPs_RawToTemperature(u32 AdcData); +* +*****************************************************************************/ +#define XAdcPs_RawToTemperature(AdcData) \ + ((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f) + +/****************************************************************************/ +/** +* +* This macro converts XADC/ADC Raw Data to Voltage(volts). +* +* @param AdcData is the XADC/ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XAdcPs_RawToVoltage(u32 AdcData); +* +*****************************************************************************/ +#define XAdcPs_RawToVoltage(AdcData) \ + ((((float)(AdcData))* (3.0f))/65536.0f) + +/****************************************************************************/ +/** +* +* This macro converts Temperature in centigrades to XADC/ADC Raw Data. +* +* @param Temperature is the Temperature in centigrades to be +* converted to XADC/ADC Raw Data. +* +* @return The XADC/ADC Raw Data. +* +* @note C-Style signature: +* int XAdcPs_TemperatureToRaw(float Temperature); +* +*****************************************************************************/ +#define XAdcPs_TemperatureToRaw(Temperature) \ + ((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f)) + +/****************************************************************************/ +/** +* +* This macro converts Voltage in Volts to XADC/ADC Raw Data. +* +* @param Voltage is the Voltage in volts to be converted to +* XADC/ADC Raw Data. +* +* @return The XADC/ADC Raw Data. +* +* @note C-Style signature: +* int XAdcPs_VoltageToRaw(float Voltage); +* +*****************************************************************************/ +#define XAdcPs_VoltageToRaw(Voltage) \ + ((int)((Voltage)*65536.0f/3.0f)) + + +/****************************************************************************/ +/** +* +* This macro is used for writing to the XADC Registers using the +* command FIFO. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data); +* +*****************************************************************************/ +#define XAdcPs_WriteFifo(InstancePtr, Data) \ + XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XADCPS_CMDFIFO_OFFSET, Data); + + +/****************************************************************************/ +/** +* +* This macro is used for reading from the XADC Registers using the +* data FIFO. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return Data read from the FIFO +* +* @note C-Style signature: +* u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr); +* +*****************************************************************************/ +#define XAdcPs_ReadFifo(InstancePtr) \ + XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XADCPS_RDFIFO_OFFSET); + + +/************************** Function Prototypes *****************************/ + + + +/** + * Functions in xadcps_sinit.c + */ +XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId); + +/** + * Functions in xadcps.c + */ +int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, + XAdcPs_Config *ConfigPtr, + u32 EffectiveAddr); + + +u32 XAdcPs_GetStatus(XAdcPs *InstancePtr); + +u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr); + +void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr); + +void XAdcPs_Reset(XAdcPs *InstancePtr); + +u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel); + +u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType); + +u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType); + +void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average); +u8 XAdcPs_GetAvg(XAdcPs *InstancePtr); + +int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr, + u8 Channel, + int IncreaseAcqCycles, + int IsEventMode, + int IsDifferentialMode); + + +void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask); +u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr); + +void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration); +u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr); + +void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode); +u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr); + +void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor); +u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask); +u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask); +u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask); +u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr); + +int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask); +u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr); + +void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value); +u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg); + +void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr); +void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr); + +void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode); + +int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr); + +void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel); + +void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode); + +u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr); + +/** + * Functions in xadcps_selftest.c + */ +int XAdcPs_SelfTest(XAdcPs *InstancePtr); + +/** + * Functions in xadcps_intr.c + */ +void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask); +void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask); +u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr); + +u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr); +void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask); + + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps_hw.h new file mode 100644 index 0000000..55a47a4 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xadcps_hw.h @@ -0,0 +1,502 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xadcps_hw.h +* @addtogroup xadcps_v2_2 +* @{ +* +* This header file contains identifiers and basic driver functions (or +* macros) that can be used to access the XADC device through the Device +* Config Interface of the Zynq. +* +* +* Refer to the device specification for more information about this driver. +* +* @note None. +* +* +* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+*
    +* +*****************************************************************************/ +#ifndef XADCPS_HW_H /* Prevent circular inclusions */ +#define XADCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ + + +/**@name Register offsets of XADC in the Device Config + * + * The following constants provide access to each of the registers of the + * XADC device. + * @{ + */ + +#define XADCPS_CFG_OFFSET 0x00 /**< Configuration Register */ +#define XADCPS_INT_STS_OFFSET 0x04 /**< Interrupt Status Register */ +#define XADCPS_INT_MASK_OFFSET 0x08 /**< Interrupt Mask Register */ +#define XADCPS_MSTS_OFFSET 0x0C /**< Misc status register */ +#define XADCPS_CMDFIFO_OFFSET 0x10 /**< Command FIFO Register */ +#define XADCPS_RDFIFO_OFFSET 0x14 /**< Read FIFO Register */ +#define XADCPS_MCTL_OFFSET 0x18 /**< Misc control register */ + +/* @} */ + + + + + +/** @name XADC Config Register Bit definitions + * @{ + */ +#define XADCPS_CFG_ENABLE_MASK 0x80000000 /**< Enable access from PS mask */ +#define XADCPS_CFG_CFIFOTH_MASK 0x00F00000 /**< Command FIFO Threshold mask */ +#define XADCPS_CFG_DFIFOTH_MASK 0x000F0000 /**< Data FIFO Threshold mask */ +#define XADCPS_CFG_WEDGE_MASK 0x00002000 /**< Write Edge Mask */ +#define XADCPS_CFG_REDGE_MASK 0x00001000 /**< Read Edge Mask */ +#define XADCPS_CFG_TCKRATE_MASK 0x00000300 /**< Clock freq control */ +#define XADCPS_CFG_IGAP_MASK 0x0000001F /**< Idle Gap between + * successive commands */ +/* @} */ + + +/** @name XADC Interrupt Status/Mask Register Bit definitions + * + * The definitions are same for the Interrupt Status Register and + * Interrupt Mask Register. They are defined only once. + * @{ + */ +#define XADCPS_INTX_ALL_MASK 0x000003FF /**< Alarm Signals Mask */ +#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */ +#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */ +#define XADCPS_INTX_OT_MASK 0x00000080 /**< Over temperature Alarm Status */ +#define XADCPS_INTX_ALM_ALL_MASK 0x0000007F /**< Alarm Signals Mask */ +#define XADCPS_INTX_ALM6_MASK 0x00000040 /**< Alarm 6 Mask */ +#define XADCPS_INTX_ALM5_MASK 0x00000020 /**< Alarm 5 Mask */ +#define XADCPS_INTX_ALM4_MASK 0x00000010 /**< Alarm 4 Mask */ +#define XADCPS_INTX_ALM3_MASK 0x00000008 /**< Alarm 3 Mask */ +#define XADCPS_INTX_ALM2_MASK 0x00000004 /**< Alarm 2 Mask */ +#define XADCPS_INTX_ALM1_MASK 0x00000002 /**< Alarm 1 Mask */ +#define XADCPS_INTX_ALM0_MASK 0x00000001 /**< Alarm 0 Mask */ + +/* @} */ + + +/** @name XADC Miscellaneous Register Bit definitions + * @{ + */ +#define XADCPS_MSTS_CFIFO_LVL_MASK 0x000F0000 /**< Command FIFO Level mask */ +#define XADCPS_MSTS_DFIFO_LVL_MASK 0x0000F000 /**< Data FIFO Level Mask */ +#define XADCPS_MSTS_CFIFOF_MASK 0x00000800 /**< Command FIFO Full Mask */ +#define XADCPS_MSTS_CFIFOE_MASK 0x00000400 /**< Command FIFO Empty Mask */ +#define XADCPS_MSTS_DFIFOF_MASK 0x00000200 /**< Data FIFO Full Mask */ +#define XADCPS_MSTS_DFIFOE_MASK 0x00000100 /**< Data FIFO Empty Mask */ +#define XADCPS_MSTS_OT_MASK 0x00000080 /**< Over Temperature Mask */ +#define XADCPS_MSTS_ALM_MASK 0x0000007F /**< Alarms Mask */ +/* @} */ + + +/** @name XADC Miscellaneous Control Register Bit definitions + * @{ + */ +#define XADCPS_MCTL_RESET_MASK 0x00000010 /**< Reset XADC */ +#define XADCPS_MCTL_FLUSH_MASK 0x00000001 /**< Flush the FIFOs */ +/* @} */ + + +/**@name Internal Register offsets of the XADC + * + * The following constants provide access to each of the internal registers of + * the XADC device. + * @{ + */ + +/* + * XADC Internal Channel Registers + */ +#define XADCPS_TEMP_OFFSET 0x00 /**< On-chip Temperature Reg */ +#define XADCPS_VCCINT_OFFSET 0x01 /**< On-chip VCCINT Data Reg */ +#define XADCPS_VCCAUX_OFFSET 0x02 /**< On-chip VCCAUX Data Reg */ +#define XADCPS_VPVN_OFFSET 0x03 /**< ADC out of VP/VN */ +#define XADCPS_VREFP_OFFSET 0x04 /**< On-chip VREFP Data Reg */ +#define XADCPS_VREFN_OFFSET 0x05 /**< On-chip VREFN Data Reg */ +#define XADCPS_VBRAM_OFFSET 0x06 /**< On-chip VBRAM , 7 Series */ +#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET 0x08 /**< ADC A Supply Offset Reg */ +#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET 0x09 /**< ADC A Offset Data Reg */ +#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg */ +#define XADCPS_VCCPINT_OFFSET 0x0D /**< On-chip VCCPINT Reg, Zynq */ +#define XADCPS_VCCPAUX_OFFSET 0x0E /**< On-chip VCCPAUX Reg, Zynq */ +#define XADCPS_VCCPDRO_OFFSET 0x0F /**< On-chip VCCPDRO Reg, Zynq */ + +/* + * XADC External Channel Registers + */ +#define XADCPS_AUX00_OFFSET 0x10 /**< ADC out of VAUXP0/VAUXN0 */ +#define XADCPS_AUX01_OFFSET 0x11 /**< ADC out of VAUXP1/VAUXN1 */ +#define XADCPS_AUX02_OFFSET 0x12 /**< ADC out of VAUXP2/VAUXN2 */ +#define XADCPS_AUX03_OFFSET 0x13 /**< ADC out of VAUXP3/VAUXN3 */ +#define XADCPS_AUX04_OFFSET 0x14 /**< ADC out of VAUXP4/VAUXN4 */ +#define XADCPS_AUX05_OFFSET 0x15 /**< ADC out of VAUXP5/VAUXN5 */ +#define XADCPS_AUX06_OFFSET 0x16 /**< ADC out of VAUXP6/VAUXN6 */ +#define XADCPS_AUX07_OFFSET 0x17 /**< ADC out of VAUXP7/VAUXN7 */ +#define XADCPS_AUX08_OFFSET 0x18 /**< ADC out of VAUXP8/VAUXN8 */ +#define XADCPS_AUX09_OFFSET 0x19 /**< ADC out of VAUXP9/VAUXN9 */ +#define XADCPS_AUX10_OFFSET 0x1A /**< ADC out of VAUXP10/VAUXN10 */ +#define XADCPS_AUX11_OFFSET 0x1B /**< ADC out of VAUXP11/VAUXN11 */ +#define XADCPS_AUX12_OFFSET 0x1C /**< ADC out of VAUXP12/VAUXN12 */ +#define XADCPS_AUX13_OFFSET 0x1D /**< ADC out of VAUXP13/VAUXN13 */ +#define XADCPS_AUX14_OFFSET 0x1E /**< ADC out of VAUXP14/VAUXN14 */ +#define XADCPS_AUX15_OFFSET 0x1F /**< ADC out of VAUXP15/VAUXN15 */ + +/* + * XADC Registers for Maximum/Minimum data captured for the + * on chip Temperature/VCCINT/VCCAUX data. + */ +#define XADCPS_MAX_TEMP_OFFSET 0x20 /**< Max Temperature Reg */ +#define XADCPS_MAX_VCCINT_OFFSET 0x21 /**< Max VCCINT Register */ +#define XADCPS_MAX_VCCAUX_OFFSET 0x22 /**< Max VCCAUX Register */ +#define XADCPS_MAX_VCCBRAM_OFFSET 0x23 /**< Max BRAM Register, 7 series */ +#define XADCPS_MIN_TEMP_OFFSET 0x24 /**< Min Temperature Reg */ +#define XADCPS_MIN_VCCINT_OFFSET 0x25 /**< Min VCCINT Register */ +#define XADCPS_MIN_VCCAUX_OFFSET 0x26 /**< Min VCCAUX Register */ +#define XADCPS_MIN_VCCBRAM_OFFSET 0x27 /**< Min BRAM Register, 7 series */ +#define XADCPS_MAX_VCCPINT_OFFSET 0x28 /**< Max VCCPINT Register, Zynq */ +#define XADCPS_MAX_VCCPAUX_OFFSET 0x29 /**< Max VCCPAUX Register, Zynq */ +#define XADCPS_MAX_VCCPDRO_OFFSET 0x2A /**< Max VCCPDRO Register, Zynq */ +#define XADCPS_MIN_VCCPINT_OFFSET 0x2C /**< Min VCCPINT Register, Zynq */ +#define XADCPS_MIN_VCCPAUX_OFFSET 0x2D /**< Min VCCPAUX Register, Zynq */ +#define XADCPS_MIN_VCCPDRO_OFFSET 0x2E /**< Min VCCPDRO Register,Zynq */ + /* Undefined 0x2F to 0x3E */ +#define XADCPS_FLAG_OFFSET 0x3F /**< Flag Register */ + +/* + * XADC Configuration Registers + */ +#define XADCPS_CFR0_OFFSET 0x40 /**< Configuration Register 0 */ +#define XADCPS_CFR1_OFFSET 0x41 /**< Configuration Register 1 */ +#define XADCPS_CFR2_OFFSET 0x42 /**< Configuration Register 2 */ + +/* Test Registers 0x43 to 0x47 */ + +/* + * XADC Sequence Registers + */ +#define XADCPS_SEQ00_OFFSET 0x48 /**< Seq Reg 00 Adc Channel Selection */ +#define XADCPS_SEQ01_OFFSET 0x49 /**< Seq Reg 01 Adc Channel Selection */ +#define XADCPS_SEQ02_OFFSET 0x4A /**< Seq Reg 02 Adc Average Enable */ +#define XADCPS_SEQ03_OFFSET 0x4B /**< Seq Reg 03 Adc Average Enable */ +#define XADCPS_SEQ04_OFFSET 0x4C /**< Seq Reg 04 Adc Input Mode Select */ +#define XADCPS_SEQ05_OFFSET 0x4D /**< Seq Reg 05 Adc Input Mode Select */ +#define XADCPS_SEQ06_OFFSET 0x4E /**< Seq Reg 06 Adc Acquisition Select */ +#define XADCPS_SEQ07_OFFSET 0x4F /**< Seq Reg 07 Adc Acquisition Select */ + +/* + * XADC Alarm Threshold/Limit Registers (ATR) + */ +#define XADCPS_ATR_TEMP_UPPER_OFFSET 0x50 /**< Temp Upper Alarm Register */ +#define XADCPS_ATR_VCCINT_UPPER_OFFSET 0x51 /**< VCCINT Upper Alarm Reg */ +#define XADCPS_ATR_VCCAUX_UPPER_OFFSET 0x52 /**< VCCAUX Upper Alarm Reg */ +#define XADCPS_ATR_OT_UPPER_OFFSET 0x53 /**< Over Temp Upper Alarm Reg */ +#define XADCPS_ATR_TEMP_LOWER_OFFSET 0x54 /**< Temp Lower Alarm Register */ +#define XADCPS_ATR_VCCINT_LOWER_OFFSET 0x55 /**< VCCINT Lower Alarm Reg */ +#define XADCPS_ATR_VCCAUX_LOWER_OFFSET 0x56 /**< VCCAUX Lower Alarm Reg */ +#define XADCPS_ATR_OT_LOWER_OFFSET 0x57 /**< Over Temp Lower Alarm Reg */ +#define XADCPS_ATR_VBRAM_UPPER_OFFSET 0x58 /**< VBRAM Upper Alarm, 7 series */ +#define XADCPS_ATR_VCCPINT_UPPER_OFFSET 0x59 /**< VCCPINT Upper Alarm, Zynq */ +#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET 0x5A /**< VCCPAUX Upper Alarm, Zynq */ +#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET 0x5B /**< VCCPDRO Upper Alarm, Zynq */ +#define XADCPS_ATR_VBRAM_LOWER_OFFSET 0x5C /**< VRBAM Lower Alarm, 7 Series */ +#define XADCPS_ATR_VCCPINT_LOWER_OFFSET 0x5D /**< VCCPINT Lower Alarm, Zynq */ +#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET 0x5E /**< VCCPAUX Lower Alarm, Zynq */ +#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET 0x5F /**< VCCPDRO Lower Alarm, Zynq */ + +/* Undefined 0x60 to 0x7F */ + +/*@}*/ + + + +/** + * @name Configuration Register 0 (CFR0) mask(s) + * @{ + */ +#define XADCPS_CFR0_CAL_AVG_MASK 0x8000 /**< Averaging enable Mask */ +#define XADCPS_CFR0_AVG_VALID_MASK 0x3000 /**< Averaging bit Mask */ +#define XADCPS_CFR0_AVG1_MASK 0x0000 /**< No Averaging */ +#define XADCPS_CFR0_AVG16_MASK 0x1000 /**< Average 16 samples */ +#define XADCPS_CFR0_AVG64_MASK 0x2000 /**< Average 64 samples */ +#define XADCPS_CFR0_AVG256_MASK 0x3000 /**< Average 256 samples */ +#define XADCPS_CFR0_AVG_SHIFT 12 /**< Averaging bits shift */ +#define XADCPS_CFR0_MUX_MASK 0x0800 /**< External Mask Enable */ +#define XADCPS_CFR0_DU_MASK 0x0400 /**< Bipolar/Unipolar mode */ +#define XADCPS_CFR0_EC_MASK 0x0200 /**< Event driven/ + * Continuous mode selection + */ +#define XADCPS_CFR0_ACQ_MASK 0x0100 /**< Add acquisition by 6 ADCCLK */ +#define XADCPS_CFR0_CHANNEL_MASK 0x001F /**< Channel number bit Mask */ + +/*@}*/ + +/** + * @name Configuration Register 1 (CFR1) mask(s) + * @{ + */ +#define XADCPS_CFR1_SEQ_VALID_MASK 0xF000 /**< Sequence bit Mask */ +#define XADCPS_CFR1_SEQ_SAFEMODE_MASK 0x0000 /**< Default Safe Mode */ +#define XADCPS_CFR1_SEQ_ONEPASS_MASK 0x1000 /**< Onepass through Seq */ +#define XADCPS_CFR1_SEQ_CONTINPASS_MASK 0x2000 /**< Continuous Cycling Seq */ +#define XADCPS_CFR1_SEQ_SINGCHAN_MASK 0x3000 /**< Single channel - No Seq */ +#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK 0x4000 /**< Simulataneous Sampling Mask */ +#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK 0x8000 /**< Independent Mode */ +#define XADCPS_CFR1_SEQ_SHIFT 12 /**< Sequence bit shift */ +#define XADCPS_CFR1_ALM_VCCPDRO_MASK 0x0800 /**< Alm 6 - VCCPDRO, Zynq */ +#define XADCPS_CFR1_ALM_VCCPAUX_MASK 0x0400 /**< Alm 5 - VCCPAUX, Zynq */ +#define XADCPS_CFR1_ALM_VCCPINT_MASK 0x0200 /**< Alm 4 - VCCPINT, Zynq */ +#define XADCPS_CFR1_ALM_VBRAM_MASK 0x0100 /**< Alm 3 - VBRAM, 7 series */ +#define XADCPS_CFR1_CAL_VALID_MASK 0x00F0 /**< Valid Calibration Mask */ +#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK 0x0080 /**< Calibration 3 -Power + Supply Gain/Offset + Enable */ +#define XADCPS_CFR1_CAL_PS_OFFSET_MASK 0x0040 /**< Calibration 2 -Power + Supply Offset Enable */ +#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain + Offset Enable */ +#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK 0x0010 /**< Calibration 0 -ADC Offset + Enable */ +#define XADCPS_CFR1_CAL_DISABLE_MASK 0x0000 /**< No Calibration */ +#define XADCPS_CFR1_ALM_ALL_MASK 0x0F0F /**< Mask for all alarms */ +#define XADCPS_CFR1_ALM_VCCAUX_MASK 0x0008 /**< Alarm 2 - VCCAUX Enable */ +#define XADCPS_CFR1_ALM_VCCINT_MASK 0x0004 /**< Alarm 1 - VCCINT Enable */ +#define XADCPS_CFR1_ALM_TEMP_MASK 0x0002 /**< Alarm 0 - Temperature */ +#define XADCPS_CFR1_OT_MASK 0x0001 /**< Over Temperature Enable */ + +/*@}*/ + +/** + * @name Configuration Register 2 (CFR2) mask(s) + * @{ + */ +#define XADCPS_CFR2_CD_VALID_MASK 0xFF00 /** +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a adk 1/31/14 Added in bsp common folder for backward compatibility +* +* +******************************************************************************/ + +#ifndef XBASIC_TYPES_H /* prevent circular inclusions */ +#define XBASIC_TYPES_H /* by using protection macros */ + +/** @name Legacy types + * Deprecated legacy types. + * @{ + */ +typedef unsigned char Xuint8; /**< unsigned 8-bit */ +typedef char Xint8; /**< signed 8-bit */ +typedef unsigned short Xuint16; /**< unsigned 16-bit */ +typedef short Xint16; /**< signed 16-bit */ +typedef unsigned long Xuint32; /**< unsigned 32-bit */ +typedef long Xint32; /**< signed 32-bit */ +typedef float Xfloat32; /**< 32-bit floating point */ +typedef double Xfloat64; /**< 64-bit double precision FP */ +typedef unsigned long Xboolean; /**< boolean (XTRUE or XFALSE) */ + +#if !defined __XUINT64__ +typedef struct +{ + Xuint32 Upper; + Xuint32 Lower; +} Xuint64; +#endif + +/** @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XIL_TYPES_H +typedef Xuint32 u32; +typedef Xuint16 u16; +typedef Xuint8 u8; +#endif +#else +#include +#endif + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +/* + * Xilinx NULL, TRUE and FALSE legacy support. Deprecated. + * Please use NULL, TRUE and FALSE + */ +#define XNULL NULL +#define XTRUE TRUE +#define XFALSE FALSE + +/* + * This file is deprecated and users + * should use xil_types.h and xil_assert.h\n\r + */ +#warning The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert. +#warning Please refer the Standalone BSP UG647 for further details + + +#endif /* end of protection macro */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps.h new file mode 100644 index 0000000..9feb45e --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps.h @@ -0,0 +1,577 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.h +* @addtogroup canps_v3_2 +* @{ +* @details +* +* The Xilinx CAN driver component. This component supports the Xilinx +* CAN Controller. +* +* The CAN Controller supports the following features: +* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards. +* - Supports both Standard (11 bit Identifier) and Extended (29 bit +* Identifier) frames. +* - Supports Bit Rates up to 1 Mbps. +* - Transmit message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Transmit prioritization through one TX High Priority Buffer. +* - Receive message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Watermark interrupts for Rx FIFO with configurable Watermark. +* - Acceptance filtering with 4 acceptance filters. +* - Sleep mode with automatic wake up. +* - Loop Back mode for diagnostic applications. +* - Snoop mode for diagnostic applications. +* - Maskable Error and Status Interrupts. +* - Readable Error Counters. +* - External PHY chip required. +* - Receive Timestamp. +* +* The device driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CAN. The driver handles transmission and reception of +* CAN frames, as well as configuration of the controller. The driver is simply a +* pass-through mechanism between a protocol stack and the CAN. A single device +* driver can support multiple CANs. +* +* Since the driver is a simple pass-through mechanism between a protocol stack +* and the CAN, no assembly or disassembly of CAN frames is done at the +* driver-level. This assumes that the protocol stack passes a correctly +* formatted CAN frame to the driver for transmission, and that the driver +* does not validate the contents of an incoming frame +* +* Operation Modes +* +* The CAN controller supports the following modes of operation: +* - Configuration Mode: In this mode the CAN timing parameters and +* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN +* controller loses synchronization with the CAN bus and drives a +* constant recessive bit on the bus line. The Error Counter Register are +* reset. The CAN controller does not receive or transmit any messages +* even if there are pending transmit requests from the TX FIFO or the TX +* High Priority Buffer. The Storage FIFOs and the CAN configuration +* registers are still accessible. +* - Normal Mode:In Normal Mode the CAN controller participates in bus +* communication, by transmitting and receiving messages. +* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any +* messages. However, if any other node transmits a message, then the CAN +* Controller receives the transmitted message and exits from Sleep Mode. +* If there are new transmission requests from either the TX FIFO or the +* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these +* requests are not serviced, and the CAN Controller continues to remain +* in Sleep Mode. Interrupts are generated when the CAN controller enters +* Sleep mode or Wakes up from Sleep mode. +* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus. Any message that is transmitted +* is looped back to the �Rx� line and acknowledged. The CAN controller +* thus receives any message that it transmits. It does not participate in +* normal bus communication and does not receive any messages that are +* transmitted by other CAN nodes. This mode is used for diagnostic +* purposes. +* - Snoop Mode: In Snoop mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus and does not participate +* in normal bus communication but receives messages that are transmitted +* by other CAN nodes. This mode is used for diagnostic purposes. +* +* +* Buffer Alignment +* +* It is important to note that frame buffers passed to the driver must be +* 32-bit aligned. +* +* Receive Address Filtering +* +* The device can be set to accept frames whose Identifiers match any of the +* 4 filters set in the Acceptance Filter Mask/ID registers. +* +* The incoming Identifier is masked with the bits in the Acceptance Filter Mask +* Register. This value is compared with the result of masking the bits in the +* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If +* both these values are equal, the message will be stored in the RX FIFO. +* +* Acceptance Filtering is performed by each of the defined acceptance filters. +* If the incoming identifier passes through any acceptance filter then the +* frame is stored in the RX FIFO. +* +* If the Accpetance Filters are not set up then all the received messages are +* stroed in the RX FIFO. +* +* PHY Communication +* +* This driver does not provide any mechanism for directly programming PHY. +* +* Interrupts +* +* The driver has no dependencies on the interrupt controller. The driver +* provides an interrupt handler. User of this driver needs to provide +* callback functions. An interrupt handler example is available with +* the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Device Reset +* +* Bus Off interrupt that can occur in the device requires a device reset. +* The user is responsible for resetting the device and re-configuring it +* based on its needs (the driver does not save the current configuration). +* When integrating into an RTOS, these reset and re-configure obligations are +* taken care of by the OS adapter software if it exists for that RTOS. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xcanps_g.c files. +* A table is defined where each entry contains configuration information +* for a CAN device. This information includes such things as the base address +* of the memory-mapped device. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCanPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

    +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*			Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*			SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk     09/12/14  Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.1 adk     10/11/15  Fixed CR#911958 Add support for Tx Watermark example.
+*			Data mismatch while sending data less than 8 bytes.
+* 3.1 nsk     12/21/15  Updated XCanPs_IntrHandler in xcanps_intr.c to handle
+*			error interrupts correctly. CR#925615
+*     ms      03/17/17  Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
    +* +******************************************************************************/ +#ifndef XCANPS_H /* prevent circular inclusions */ +#define XCANPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xcanps_hw.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +/** @name CAN operation modes + * @{ + */ +#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */ +#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */ +#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */ +#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */ +#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */ +/* @} */ + +/** @name Callback identifiers used as parameters to XCanPs_SetHandler() + * @{ + */ +#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */ +#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/ +#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */ +#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XCanPs_Config; + +/******************************************************************************/ +/** + * Callback type for frame sending and reception interrupts. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. +*******************************************************************************/ +typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef); + +/******************************************************************************/ +/** + * Callback type for error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param ErrorMask is a bit mask indicating the cause of the error. Its + * value equals 'OR'ing one or more XCANPS_ESR_* values defined in + * xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask); + +/******************************************************************************/ +/** + * Callback type for all kinds of interrupts except sending frame interrupt, + * receiving frame interrupt, and error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param Mask is a bit mask indicating the pending interrupts. Its value + * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask); + +/** + * The XCanPs driver instance data. The user is required to allocate a + * variable of this type for every CAN device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XCanPs_Config CanConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + + /** + * Callback and callback reference for TXOK interrupt. + */ + XCanPs_SendRecvHandler SendHandler; + void *SendRef; + + /** + * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts. + */ + XCanPs_SendRecvHandler RecvHandler; + void *RecvRef; + + /** + * Callback and callback reference for ERROR interrupt. + */ + XCanPs_ErrorHandler ErrorHandler; + void *ErrorRef; + + /** + * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/ + * Wakeup/Sleep/Bus off/ARBLST interrupts. + */ + XCanPs_EventHandler EventHandler; + void *EventRef; + +} XCanPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the transmission is complete. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the transmission is done. +* - FALSE if the transmission is not done. +* +* @note C-Style signature: +* int XCanPs_IsTxDone(XCanPs *InstancePtr) +* +*******************************************************************************/ +#define XCanPs_IsTxDone(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the transmission FIFO is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if TX FIFO is full. +* - FALSE if the TX FIFO is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsTxFifoFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the Transmission High Priority Buffer is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the TX High Priority Buffer is full. +* - FALSE if the TX High Priority Buffer is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsHighPriorityBufFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the receive FIFO is empty. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if RX FIFO is empty. +* - FALSE if the RX FIFO is NOT empty. +* +* @note C-Style signature: +* int XCanPs_IsRxEmpty(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsRxEmpty(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE) + + +/****************************************************************************/ +/** +* +* This macro checks if the CAN device is ready for the driver to change +* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask +* Registers (AFMR). +* +* AFIR and AFMR for a filter are changeable only after the filter is disabled +* and this routine returns FALSE. The filter can be disabled using the +* XCanPs_AcceptFilterDisable function. +* +* Use the XCanPs_Accept_* functions for configuring the acceptance filters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the device is busy and NOT ready to accept writes to +* AFIR and AFMR. +* - FALSE if the device is ready to accept writes to AFIR and +* AFMR. +* +* @note C-Style signature: +* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsAcceptFilterBusy(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro calculates CAN message identifier value given identifier field +* values. +* +* @param StandardId contains Standard Message ID value. +* @param SubRemoteTransReq contains Substitute Remote Transmission +* Request value. +* @param IdExtension contains Identifier Extension value. +* @param ExtendedId contains Extended Message ID value. +* @param RemoteTransReq contains Remote Transmission Request value. +* +* @return Message Identifier value. +* +* @note C-Style signature: +* u32 XCanPs_CreateIdValue(u32 StandardId, +* u32 SubRemoteTransReq, +* u32 IdExtension, u32 ExtendedId, +* u32 RemoteTransReq) +* +* Read the CAN specification for meaning of each parameter. +* +*****************************************************************************/ +#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \ + ExtendedId, RemoteTransReq) \ + ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \ + (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\ + (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \ + (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \ + ((RemoteTransReq) & XCANPS_IDR_RTR_MASK)) + + +/****************************************************************************/ +/** +* +* This macro calculates value for Data Length Code register given Data +* Length Code value. +* +* @param DataLengCode indicates Data Length Code value. +* +* @return Value that can be assigned to Data Length Code register. +* +* @note C-Style signature: +* u32 XCanPs_CreateDlcValue(u32 DataLengCode) +* +* Read the CAN specification for meaning of Data Length Code. +* +*****************************************************************************/ +#define XCanPs_CreateDlcValue(DataLengCode) \ + (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK) + + +/****************************************************************************/ +/** +* +* This macro clears the timestamp in the Timestamp Control Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XCanPs_ClearTimestamp(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_ClearTimestamp(InstancePtr) \ + XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \ + XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xcanps.c + */ +s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr); + +void XCanPs_Reset(XCanPs *InstancePtr); +u8 XCanPs_GetMode(XCanPs *InstancePtr); +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode); +u32 XCanPs_GetStatus(XCanPs *InstancePtr); +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount); +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr); +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask); +s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr); +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes); +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes); +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr); +s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue); +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue); + +s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler); +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr); +s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1); +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1); + +s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr); +s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr); + +/* + * Diagnostic functions in xcanps_selftest.c + */ +s32 XCanPs_SelfTest(XCanPs *InstancePtr); + +/* + * Functions in xcanps_intr.c + */ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask); +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr); +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr); +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrHandler(void *InstancePtr); +s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef); + +/* + * Functions in xcanps_sinit.c + */ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps_hw.h new file mode 100644 index 0000000..30ec68a --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcanps_hw.h @@ -0,0 +1,369 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.h +* @addtogroup canps_v3_2 +* @{ +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xcanps.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a sbs    12/27/11 Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk   08/08/13  Updated for inclding the function prototype
+* 3.00  kvn   02/13/15  Modified code for MISRA-C:2012 compliance.
+*
    +* +******************************************************************************/ + +#ifndef XCANPS_HW_H /* prevent circular inclusions */ +#define XCANPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the CAN. Each register is 32 bits. + * @{ + */ +#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */ +#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */ +#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */ +#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */ +#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */ +#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */ +#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */ + +#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */ +#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */ +#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */ +#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */ +#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */ + +#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */ +#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */ +#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */ +#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */ + +#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */ +#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */ +#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */ +#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */ + +#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */ +#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */ +#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */ +#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */ + +#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */ +#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */ +#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */ +#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */ +#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */ +#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */ +#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */ +#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */ +#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */ +/* @} */ + +/** @name Software Reset Register (SRR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */ +#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */ +/* @} */ + +/** @name Mode Select Register (MSR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */ +#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */ +#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */ +/* @} */ + +/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */ +/* @} */ + +/** @name Bit Timing Register (BTR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */ +#define XCANPS_BTR_SJW_SHIFT 7U +#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */ +#define XCANPS_BTR_TS2_SHIFT 4U +#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */ +/* @} */ + +/** @name Error Counter Register (ECR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */ +#define XCANPS_ECR_REC_SHIFT 8U +#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */ +/* @} */ + +/** @name Error Status Register (ESR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */ +#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */ +#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */ +#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */ +#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */ +/* @} */ + +/** @name Status Register (SR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */ +#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */ +#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */ +#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */ +#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */ +#define XCANPS_SR_ESTAT_SHIFT 7U +#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */ +#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */ +#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */ +#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */ +#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */ +#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */ +#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */ +/* @} */ + +/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks + * @{ + */ +#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */ +#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */ +#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */ +#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */ +#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */ +#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */ +#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */ +#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */ +#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */ +#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */ +#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */ +#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */ +#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */ +#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */ +#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */ +#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \ + (u32)XCANPS_IXR_WKUP_MASK | \ + (u32)XCANPS_IXR_SLP_MASK | \ + (u32)XCANPS_IXR_BSOFF_MASK | \ + (u32)XCANPS_IXR_ERROR_MASK | \ + (u32)XCANPS_IXR_RXNEMP_MASK | \ + (u32)XCANPS_IXR_RXOFLW_MASK | \ + (u32)XCANPS_IXR_RXUFLW_MASK | \ + (u32)XCANPS_IXR_RXOK_MASK | \ + (u32)XCANPS_IXR_TXBFLL_MASK | \ + (u32)XCANPS_IXR_TXFLL_MASK | \ + (u32)XCANPS_IXR_TXOK_MASK | \ + (u32)XCANPS_IXR_ARBLST_MASK) +/* @} */ + +/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */ +/* @} */ + +/** @name CAN Watermark Register (WIR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */ +#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */ +#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */ + +/* @} */ + +/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter + Mask/Acceptance Filter ID) + * @{ + */ +#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */ +#define XCANPS_IDR_ID1_SHIFT 21U +#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */ +#define XCANPS_IDR_SRR_SHIFT 20U +#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */ +#define XCANPS_IDR_IDE_SHIFT 19U +#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */ +#define XCANPS_IDR_ID2_SHIFT 1U +#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */ +/* @} */ + +/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */ +#define XCANPS_DLCR_DLC_SHIFT 28U +#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */ + +/* @} */ + +/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */ +#define XCANPS_DW1R_DB0_SHIFT 24U +#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */ +#define XCANPS_DW1R_DB1_SHIFT 16U +#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */ +#define XCANPS_DW1R_DB2_SHIFT 8U +#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */ +/* @} */ + +/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */ +#define XCANPS_DW2R_DB4_SHIFT 24U +#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */ +#define XCANPS_DW2R_DB5_SHIFT 16U +#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */ +#define XCANPS_DW2R_DB6_SHIFT 8U +#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */ +/* @} */ + +/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */ +#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */ +#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */ +#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */ +#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \ + (u32)XCANPS_AFR_UAF3_MASK | \ + (u32)XCANPS_AFR_UAF2_MASK | \ + (u32)XCANPS_AFR_UAF1_MASK) +/* @} */ + +/** @name CAN frame length constants + * @{ + */ +#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */ +/* @} */ + +/* For backwards compatibilty */ +#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET +#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET +#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET +#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET + +#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK +#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET +#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK + + + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the CanPs interface + */ +void XCanPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h new file mode 100644 index 0000000..67959e3 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h @@ -0,0 +1,74 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcoresightpsdcc.h +* @addtogroup coresightps_dcc_v1_4 +* @{ +* @details +* +* CoreSight driver component. +* +* The coresight is a part of debug communication channel (DCC) group. Jtag UART +* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an +* ARM target in XSDB console before running the jtag terminal command. Using the +* coresight driver component, the output stream can be directed to a log file. +* +* @note None. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifndef __MICROBLAZE__ +#include + +void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data); + +u8 XCoresightPs_DccRecvByte(u32 BaseAddress); +#endif +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h new file mode 100644 index 0000000..95c8ba5 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* @addtogroup cpu_cortexa9_v2_5 +* @{ +* @details +* +* dummy file +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h +******************************************************************************/ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xddrps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xddrps.h new file mode 100644 index 0000000..c8804d2 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xddrps.h @@ -0,0 +1,66 @@ +/******************************************************************************* + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xddrps.h + * @addtogroup ddrps_v1_0 + * @{ + * @details + * + * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps + * IP core. + * + * @note None. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ *
    + * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdebug.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdebug.h new file mode 100644 index 0000000..650946b --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdebug.h @@ -0,0 +1,32 @@ +#ifndef XDEBUG /* prevent circular inclusions */ +#define XDEBUG /* by using protection macros */ + +#if defined(DEBUG) && !defined(NDEBUG) + +#ifndef XDEBUG_WARNING +#define XDEBUG_WARNING +#warning DEBUG is enabled +#endif + +int printf(const char *format, ...); + +#define XDBG_DEBUG_ERROR 0x00000001U /* error condition messages */ +#define XDBG_DEBUG_GENERAL 0x00000002U /* general debug messages */ +#define XDBG_DEBUG_ALL 0xFFFFFFFFU /* all debugging data */ + +#define xdbg_current_types (XDBG_DEBUG_GENERAL) + +#define xdbg_stmnt(x) x + +#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0) + + +#else /* defined(DEBUG) && !defined(NDEBUG) */ + +#define xdbg_stmnt(x) + +#define xdbg_printf(...) + +#endif /* defined(DEBUG) && !defined(NDEBUG) */ + +#endif /* XDEBUG */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg.h new file mode 100644 index 0000000..b9a0111 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg.h @@ -0,0 +1,403 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.h +* @addtogroup devcfg_v3_5 +* @{ +* @details +* +* The is the main header file for the Device Configuration Interface of the Zynq +* device. The device configuration interface has three main functionality. +* 1. AXI-PCAP +* 2. Security Policy +* 3. XADC +* This current version of the driver supports only the AXI-PCAP and Security +* Policy blocks. There is a separate driver for XADC. +* +* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. +* DMA embedded in the AXI PCAP provides the master interface to +* the Device configuration block for any DMA transfers. The data transfer can +* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip +* RAM/DDR/peripheral memory). +* +* The current driver only supports the downloading the FPGA bitstream and +* readback of the decrypted image (sort of loopback). +* The driver does not know what information needs to be written to the FPGA to +* readback FPGA configuration register or memory data. The application above the +* driver should take care of creating the data that needs to be downloaded to +* the FPGA so that the bitstream can be readback. +* This driver also does not support the reading of the internal registers of the +* PCAP. The driver has no knowledge of the PCAP internals. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Device Configuration device. +* +* XDcfg_CfgInitialize() API is used to initialize the Device Configuration +* Interface. The user needs to first call the XDcfg_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XDcfg_CfgInitialize() API. +* +* Interrupts +* The Driver implements an interrupt handler to support the interrupts provided +* by this interface. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XDcfg driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

    +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* 		     Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg.
+*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+*		     and XDcfg_SelectPcapInterface APIs for CR 643295
+*		     The user has to call the XDcfg_SelectIcapInterface API
+*		     for the PL reconfiguration using AXI HwIcap.
+*		     Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+*		     Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   adk 10/12/13 Updated as per the New Tcl API's
+* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*		     A new example has been added to read back the
+*		     configuration registers from the PL region.
+*		     xdevcfg_reg_readback_example.c
+* 3.3   sk  04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*       ms  04/10/17 Modified filename tag in interrupt and polled examples
+*                    to include them in doxygen examples.
+* 3.5   ms  04/18/17 Modified tcl file to add suffix U for all macros
+*                    definitions of devcfg in xparameters.h
+*       ms  08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
    +* +******************************************************************************/ +#ifndef XDCFG_H /* prevent circular inclusions */ +#define XDCFG_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" +#include "xstatus.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* Types of PCAP transfers */ + +#define XDCFG_NON_SECURE_PCAP_WRITE 1 +#define XDCFG_SECURE_PCAP_WRITE 2 +#define XDCFG_PCAP_READBACK 3 +#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 +#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 + + +/**************************** Type Definitions *******************************/ +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* unimportant to the driver component, so it is a void pointer. +* @param Status is the Interrupt status of the XDcfg device. +*/ +typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XDcfg_Config; + +/** + * The XDcfg driver instance data. + */ +typedef struct { + XDcfg_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device Configuration Interface + * is running + */ + XDcfg_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XDcfg; + +/****************************************************************************/ +/** +* +* Unlock the Device Config Interface block. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_Unlock(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_Unlock(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + + + +/****************************************************************************/ +/** +* +* Get the version number of the PS from the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return Version of the PS. +* +* @note C-style signature: +* void XDcfg_GetPsVersion(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_GetPsVersion(InstancePtr) \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MCTRL_OFFSET)) & \ + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + + + +/****************************************************************************/ +/** +* +* Read the multiboot config register value. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_ReadMultiBootConfig(InstancePtr) \ + XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MULTIBOOT_ADDR_OFFSET) + + +/****************************************************************************/ +/** +* +* Selects ICAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectIcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + +/****************************************************************************/ +/** +* +* Selects PCAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectPcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) + + + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xdevcfg_sinit.c. + */ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xdevcfg_selftest.c + */ +int XDcfg_SelfTest(XDcfg *InstancePtr); + +/* + * Interface functions in xdevcfg.c + */ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + +void XDcfg_EnablePCAP(XDcfg *InstancePtr); + +void XDcfg_DisablePCAP(XDcfg *InstancePtr); + +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); + +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); + +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); + +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); + +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); + +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); + +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); + +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength); + +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); + +/* + * Interrupt related function prototypes implemented in xdevcfg_intr.c + */ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); + +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); + +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_InterruptHandler(XDcfg *InstancePtr); + +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h new file mode 100644 index 0000000..c506ca5 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h @@ -0,0 +1,395 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.h +* @addtogroup devcfg_v3_3 +* @{ +* +* This file contains the hardware interface to the Device Config Interface. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  08/01/12 Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 2.04a	kpc	10/07/13 Added function prototype.
+* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
    +* +******************************************************************************/ +#ifndef XDCFG_HW_H /* prevent circular inclusions */ +#define XDCFG_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ +#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ +#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ +#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ +#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ +#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ + +/* @} */ + +/** @name Control Register Bit definitions + * @{ + */ + +#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into + * Secure Reset + */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to + * Reset FPGA + */ +#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ +#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data + * to FPGA every 4 PCAP + * cycles + */ +#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ +#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ +#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ +#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ +#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure + * Status mask + */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive + * Debug Enable + */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive + * Debug Enable + */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ + +/* @} */ + +/** @name Lock register bit definitions + * @{ + */ + +#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ +#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and + * USER_MODE + */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks + * security config + * including: DAP_En, + * DBGEN,, + * NIDEN, SPNIEN + */ +/*@}*/ + + + +/** @name Config Register Bit definitions + * @{ + */ +#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO + * Threshold Mask + */ +#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold + * Mask + */ +#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active + * clock edge + */ +#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active + * clock edge + */ +#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address + * increment mask + */ +#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination + * address increment + * mask + */ +/* @} */ + + +/** @name Interrupt Status/Mask Register Bit definitions + * @{ + */ +#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during + * HIZ + */ +#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration + * done + */ +#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ +#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during + * configuration + */ +#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration + * reset + */ +#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address + * or Data or response + * timeout + */ +#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response + * error + */ +#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or + * response timeout + */ +#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response + * error + */ +#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ +#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than + * threshold */ +#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than + * threshold */ +#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ +#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue + * overflow + */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ +#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP + * transfers Done + */ +#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer + * length error + */ +#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ +#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ +#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ +#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ +#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge + * of Init Signal + */ +#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge + * of Init Signal + */ +#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + + +#define XDCFG_IXR_ALL_MASK 0x00F7F8EF + + + +/* @} */ + + +/** @name Status Register Bit definitions + * @{ + */ +#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command + * Queue full + */ +#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command + * Queue empty + */ +#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of + * completed DMA + * transfers + */ +#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ +#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ + +#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO + * during HIZ + */ +#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config + * done + */ +#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ +#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during + * config + */ +#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset + * POR Status + */ +#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB + * access + */ +#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config + * reset status + */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init + * Status + */ +#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 + /**< BBRAM key + * disable + */ +#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security + * Enable Status + */ +#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG + * Disable + * status + */ +/* @} */ + + +/** @name DMA Source/Destination Transfer Length Register Bit definitions + * @{ + */ +#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ +/*@}*/ + + + + +/** @name Miscellaneous Control Register Bit definitions + * @{ + */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ +/* @} */ + +/** @name FIFO Threshold Bit definitions + * @{ + */ + +#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ +#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ +#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ +#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ +/* @}*/ + + +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ +#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ +#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base + * address + */ +#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XDcfg_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the devcfg interface + */ +void XDcfg_ResetHw(u32 BaseAddr); +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps.h new file mode 100644 index 0000000..5a0c1a2 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps.h @@ -0,0 +1,352 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.h +* @addtogroup dmaps_v2_3 +* @{ +* @details +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/10 First Release
+* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		        the maximum number of channels.
+*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+*			Added the tcl file to automatically generate the
+*			xparameters.h
+* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
+*			header from the xdmaps.h file to xdmaps.c file
+*			Other cleanup for coding guidelines and CR 657109
+*			and CR 657898
+*			The xdmaps_example_no_intr.c example is removed
+*			as it is using interrupts  and is similar to
+*			the interrupt example - CR 652477
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.0   adk    10/12/13  Updated as per the New Tcl API's
+* 2.01  kpc    08/23/14  Fixed the IAR compiler reported errors
+* 2.2   mus    08/12/16  Declared all inline functions in xdmaps.c as extern, to avoid
+*                        linker error for IAR compiler
+* 2.3   ms     01/23/17 Modified xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
    +* +*****************************************************************************/ + +#ifndef XDMAPS_H /* prevent circular inclusions */ +#define XDMAPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xparameters.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" + +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ +} XDmaPs_Config; + + +/** DMA channle control structure. It's for AXI bus transaction. + * This struct will be translated into a 32-bit channel control register value. + */ +typedef struct { + unsigned int EndianSwapSize; /**< Endian swap size. */ + unsigned int DstCacheCtrl; /**< Destination cache control */ + unsigned int DstProtCtrl; /**< Destination protection control */ + unsigned int DstBurstLen; /**< Destination burst length */ + unsigned int DstBurstSize; /**< Destination burst size */ + unsigned int DstInc; /**< Destination incrementing or fixed + * address */ + unsigned int SrcCacheCtrl; /**< Source cache control */ + unsigned int SrcProtCtrl; /**< Source protection control */ + unsigned int SrcBurstLen; /**< Source burst length */ + unsigned int SrcBurstSize; /**< Source burst size */ + unsigned int SrcInc; /**< Source incrementing or fixed + * address */ +} XDmaPs_ChanCtrl; + +/** DMA block descriptor stucture. + */ +typedef struct { + u32 SrcAddr; /**< Source starting address */ + u32 DstAddr; /**< Destination starting address */ + unsigned int Length; /**< Number of bytes for the block */ +} XDmaPs_BD; + +/** + * A DMA command consisits of a channel control struct, a block descriptor, + * a user defined program, a pointer pointing to generated DMA program, and + * execution result. + * + */ +typedef struct { + XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ + XDmaPs_BD BD; /**< Together with SgLength field, + * it's a scatter-gather list. + */ + void *UserDmaProg; /**< If user wants the driver to + * execute their own DMA program, + * this field points to the DMA + * program. + */ + int UserDmaProgLength; /**< The length of user defined + * DMA program. + */ + + void *GeneratedDmaProg; /**< The DMA program genreated + * by the driver. This field will be + * set if a user invokes the DMA + * program generation function. Or + * the DMA command is finished and + * a user informs the driver not to + * release the program buffer. + * This field has two purposes, one + * is to ask the driver to generate + * a DMA program while the DMAC is + * performaning DMA transactions. The + * other purpose is to debug the + * driver. + */ + int GeneratedDmaProgLength; /**< The length of the DMA program + * generated by the driver + */ + int DmaStatus; /**< 0 on success, otherwise error code + */ + u32 ChanFaultType; /**< Channel fault type in case of fault + */ + u32 ChanFaultPCAddr; /**< Channel fault PC address + */ +} XDmaPs_Cmd; + +/** + * It's the done handler a user can set for a channel + */ +typedef void (*XDmaPsDoneHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +/** + * It's the fault handler a user can set for a channel + */ +typedef void (*XDmaPsFaultHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +#define XDMAPS_MAX_CHAN_BUFS 2 +#define XDMAPS_CHAN_BUF_LEN 128 + +/** + * The XDmaPs_ProgBuf is the struct for a DMA program buffer. + */ +typedef struct { + char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the + * content */ + unsigned Len; /**< The actual length of the DMA + * program in bytes. */ + int Allocated; /**< A tag indicating whether the + * buffer is allocated or not */ +} XDmaPs_ProgBuf; + +/** + * The XDmaPs_ChannelData is a struct to book keep individual channel of + * the DMAC. + */ +typedef struct { + unsigned DevId; /**< Device id indicating which DMAC */ + unsigned ChanId; /**< Channel number of the DMAC */ + XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of + program buffers*/ + XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ + void *DoneRef; /**< Done interrupt callback data */ + XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ + XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. + * This field is for debugging purpose + */ + int HoldDmaProg; /**< A tag indicating whether to hold the + * DMA program after the DMA is done. + */ + +} XDmaPs_ChannelData; + +/** + * The XDmaPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XDmaPs_Config Config; /**< Configuration data structure */ + int IsReady; /**< Device is Ready */ + int CacheLength; /**< icache length */ + XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ + void *FaultRef; /**< fault call back data */ + XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; + /**< + * channel data + */ +} XDmaPs; + +/* + * Functions implemented in xdmaps.c + */ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr); + +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg); + +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + + +int XDmaPs_ResetManager(XDmaPs *InstPtr); +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); + + +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); + +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); + +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + +/** + * To avoid linking error,Declare all inline functions as extern for + * IAR compiler + */ +#ifdef __ICCARM__ +extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg); +extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src); +extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns); +extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations); +extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc); +extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm); +extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber); +extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg); +extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize); +extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize); +#endif + +/** + * Driver done interrupt service routines for the channels. + * We need this done ISR mainly because the driver needs to release the + * DMA program buffer. This is the one that connects the GIC + */ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr); +void XDmaPs_DoneISR_1(XDmaPs *InstPtr); +void XDmaPs_DoneISR_2(XDmaPs *InstPtr); +void XDmaPs_DoneISR_3(XDmaPs *InstPtr); +void XDmaPs_DoneISR_4(XDmaPs *InstPtr); +void XDmaPs_DoneISR_5(XDmaPs *InstPtr); +void XDmaPs_DoneISR_6(XDmaPs *InstPtr); +void XDmaPs_DoneISR_7(XDmaPs *InstPtr); + +/** + * Driver fault interrupt service routine + */ +void XDmaPs_FaultISR(XDmaPs *InstPtr); + + +/* + * Static loopup function implemented in xdmaps_sinit.c + */ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); + + +/* + * self-test functions in xdmaps_selftest.c + */ +int XDmaPs_SelfTest(XDmaPs *InstPtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps_hw.h new file mode 100644 index 0000000..628f1ec --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xdmaps_hw.h @@ -0,0 +1,293 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdmaps_hw.h +* @addtogroup dmaps_v2_3 +* @{ +* +* This header file contains the hardware interface of an XDmaPs device. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who   Date     Changes
+* ----- ----  -------- ----------------------------------------------
+* 1.00a	hbm   08/18/10 First Release
+* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		       the maximum number of channels.
+*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg    05/16/12 Made changes for doxygen
+* 1.06a kpc   07/10/13 Added function prototype
+*
    +* +******************************************************************************/ + +#ifndef XDMAPS_HW_H /* prevent circular inclusions */ +#define XDMAPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the DMAC. + * @{ + */ + +#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ +#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ +#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ +#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ +#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register + */ +#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ +#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager + * Register + */ +#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register + */ +#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ + +#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ +/* + * The offset for the rest of the FTC registers is calculated as + * FTC0 + dev_chan_num * 4 + */ +#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) + +#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ +/* + * The offset for the rest of the CS registers is calculated as + * CS0 + * dev_chan_num * 0x08 + */ +#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) + +#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA + * Channel 0 + */ +/* + * The offset for the rest of the CPC registers is calculated as + * CPC0 + dev_chan_num * 0x08 + */ +#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) + +#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA + * Channel 0 + */ +/* The offset for the rest of the SA registers is calculated as + * SA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for + * DMA Channel 0 + */ +/* The offset for the rest of the DA registers is calculated as + * DA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for + * DMA Channel 0 + */ +/* + * The offset for the rest of the CC registers is calculated as + * CC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ +/* + * The offset for the rest of the LC0 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) +#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ +/* + * The offset for the rest of the LC1 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ +#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ +#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ +#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ + +#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ +#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ +#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ +#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ +#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ +#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ + +#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification + * Register 0 + */ +#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification + * Register 1 + */ +#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification + * Register 2 + */ +#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification + * Register 3 + */ +#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification + * Register 0 + */ +#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification + * Register 1 + */ +#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification + * Register 2 + */ +#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification + * Register 3 + */ + +/* + * Some useful register masks + */ +#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ +#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ + +#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ + +#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, + * llast 3 bits of CS register + */ + +#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ + + +/* + * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. + * @b1: Instruction byte 1 + * @b0: Instruction byte 0 + * @ch: Channel number + * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel + */ +#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ + (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) + +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +/* @}*/ + + +#define XDMAPS_CHANNELS_PER_DEV 8 + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ + +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ + +/* @} */ +#define XDMAPS_INTCLR_ALL_MASK 0xFF + +#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write a DMAC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note +* C-Style signature: +* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +******************************************************************************/ +#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the dmaps interface + */ +void XDmaPs_ResetHw(u32 BaseAddr); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps.h new file mode 100644 index 0000000..6d4b15b --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps.h @@ -0,0 +1,809 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h +* @addtogroup emacps_v3_7 +* @{ +* @details + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+ *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4   ms   01/23/17 Modified xil_printf statement in main function for all
+ *                     examples to ensure that "Successfully ran" and "Failed"
+ *                     strings are available in all examples. This is a fix
+ *                     for CR-965028.
+ *       ms   03/17/17 Modified text file in examples folder for doxygen
+ *                     generation.
+ *       ms   04/05/17 Added tabspace for return statements in functions of
+ *                     xemacps_ieee1588_example.c for proper documentation
+ *                     while generating doxygen.
+ * 3.5   hk   08/14/17 Update cache coherency information of the interface in
+ *                     its config structure.
+ * 3.6   rb   09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ *		       changed to volatile.
+ *		       Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *
+ *
    + * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001U +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002U +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004U +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020U +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040U +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400U +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800U +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U +#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U + +#define XEMACPS_DEFAULT_OPTIONS \ + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1U +#define XEMACPS_HANDLER_DMARECV 2U +#define XEMACPS_HANDLER_ERROR 3U +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ + +#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ +#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 0x00000001 +#define XEMACPS_4BYTE_BURST 0x00000004 +#define XEMACPS_8BYTE_BURST 0x00000008 +#define XEMACPS_16BYTE_BURST 0x00000010 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ + u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; + * describes whether Cache Coherent or not */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs_Instance { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + u32 Version; + u32 RxBufMask; + u32 MaxMtuSize; + u32 MaxFrameSize; + u32 MaxVlanFrameSize; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + UINTPTR EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPointer, void *CallBackRef); +void XEmacPs_IntrHandler(void *XEmacPsPtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bd.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bd.h new file mode 100644 index 0000000..83f9a87 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bd.h @@ -0,0 +1,804 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h +* @addtogroup emacps_v3_7 +* @{ + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ * 3.2   hk   11/18/15 Change BD typedef and number of words.
+ *
+ *
    + * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ +#ifdef __aarch64__ +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U +#define XEMACPS_BD_NUM_WORDS 4U +#else +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U +#define XEMACPS_BD_NUM_WORDS 2U +#endif + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + (u32)((Addr) & ULONG64_LO_MASK)); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr))) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data)) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U) +#else +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) +#endif + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + +/*****************************************************************************/ +/** + * Retrieve the RX frame size. + * + * The returned value is the size of the received packet. + * This API supports jumbo frame sizes if enabled. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr) + * RxBufMask is dependent on whether jumbo is enabled or not. + * + *****************************************************************************/ +#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + (InstancePtr)->RxBufMask) + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bdring.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bdring.h new file mode 100644 index 0000000..b89e898 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_bdring.h @@ -0,0 +1,241 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.h +* @addtogroup emacps_v3_7 +* @{ +* +* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs +* DMA functionalities. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6   rb   09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+*		      changed to volatile.
+*
+*
    +* +******************************************************************************/ + +#ifndef XEMACPS_BDRING_H /* prevent curcular inclusions */ +#define XEMACPS_BDRING_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/**************************** Type Definitions *******************************/ + +/** This is an internal structure used to maintain the DMA list */ +typedef struct { + UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */ + UINTPTR BaseBdAddr; /**< Virtual address of 1st BD in list */ + UINTPTR HighBdAddr; /**< Virtual address of last BD in the list */ + u32 Length; /**< Total size of ring in bytes */ + u32 RunState; /**< Flag to indicate DMA is started */ + u32 Separation; /**< Number of bytes between the starting address + of adjacent BDs */ + XEmacPs_Bd *FreeHead; + /**< First BD in the free group */ + XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */ + XEmacPs_Bd *HwHead; /**< First BD in the work group */ + XEmacPs_Bd *HwTail; /**< Last BD in the work group */ + XEmacPs_Bd *PostHead; + /**< First BD in the post-work group */ + XEmacPs_Bd *BdaRestart; + /**< BDA to load when channel is started */ + + volatile u32 HwCnt; /**< Number of BDs in work group */ + u32 PreCnt; /**< Number of BDs in pre-work group */ + u32 FreeCnt; /**< Number of allocatable BDs in the free group */ + u32 PostCnt; /**< Number of BDs in post-work group */ + u32 AllCnt; /**< Total Number of BDs for channel */ +} XEmacPs_BdRing; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many BDs will fit +* in a BD list within the given memory constraints. +* +* The results of this macro can be provided to XEmacPs_BdRingCreate(). +* +* @param Alignment specifies what byte alignment the BDs must fall on and +* must be a power of 2 to get an accurate calculation (32, 64, 128,...) +* @param Bytes is the number of bytes to be used to store BDs. +* +* @return Number of BDs that can fit in the given memory area +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes) +* +******************************************************************************/ +#define XEmacPs_BdRingCntCalc(Alignment, Bytes) \ + (u32)((Bytes) / (sizeof(XEmacPs_Bd))) + +/*****************************************************************************/ +/** +* Use this macro at initialization time to determine how many bytes of memory +* is required to contain a given number of BDs at a given alignment. +* +* @param Alignment specifies what byte alignment the BDs must fall on. This +* parameter must be a power of 2 to get an accurate calculation (32, 64, +* 128,...) +* @param NumBd is the number of BDs to calculate memory size requirements for +* +* @return The number of bytes of memory required to create a BD list with the +* given memory constraints. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd) +* +******************************************************************************/ +#define XEmacPs_BdRingMemCalc(Alignment, NumBd) \ + (u32)(sizeof(XEmacPs_Bd) * (NumBd)) + +/****************************************************************************/ +/** +* Return the total number of BDs allocated by this channel with +* XEmacPs_BdRingCreate(). +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The total number of BDs allocated for this channel. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt) + +/****************************************************************************/ +/** +* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre- +* processing. +* +* @param RingPtr is the DMA channel to operate on. +* +* @return The number of BDs currently allocatable. +* +* @note +* C-style signature: +* u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingGetFreeCnt(RingPtr) ((RingPtr)->FreeCnt) + +/****************************************************************************/ +/** +* Return the next BD from BdPtr in a list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on. +* +* @return The next BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingNext(RingPtr, BdPtr) \ + (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ? \ + (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) : \ + (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation)) + +/****************************************************************************/ +/** +* Return the previous BD from BdPtr in the list. +* +* @param RingPtr is the DMA channel to operate on. +* @param BdPtr is the BD to operate on +* +* @return The previous BD in the list relative to the BdPtr parameter. +* +* @note +* C-style signature: +* XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr, +* XEmacPs_Bd *BdPtr) +* +*****************************************************************************/ +#define XEmacPs_BdRingPrev(RingPtr, BdPtr) \ + (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ? \ + (XEmacPs_Bd*)(RingPtr)->HighBdAddr : \ + (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation)) + +/************************** Function Prototypes ******************************/ + +/* + * Scatter gather DMA related functions in xemacps_bdring.c + */ +LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, u32 BdCount); +LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction); +LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd ** BdSetPtr); +LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd, + XEmacPs_Bd * BdSetPtr); +u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit, + XEmacPs_Bd ** BdSetPtr); +u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit, + XEmacPs_Bd ** BdSetPtr); +LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); + +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc); + +#ifdef __cplusplus +} +#endif + + +#endif /* end of protection macros */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_hw.h new file mode 100644 index 0000000..e535470 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xemacps_hw.h @@ -0,0 +1,656 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_hw.h +* @addtogroup emacps_v3_7 +* @{ +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device. +* High-level driver functions are defined in xemacps.h. +* +* @note +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+*
    +* +******************************************************************************/ + +#ifndef XEMACPS_HW_H /* prevent circular inclusions */ +#define XEMACPS_HW_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +#define XEMACPS_MAX_MAC_ADDR 4U /**< Maxmum number of mac address + supported */ +#define XEMACPS_MAX_TYPE_ID 4U /**< Maxmum number of type id supported */ + +#ifdef __aarch64__ +#define XEMACPS_BD_ALIGNMENT 64U /**< Minimum buffer descriptor alignment + on the local bus */ +#else + +#define XEMACPS_BD_ALIGNMENT 4U /**< Minimum buffer descriptor alignment + on the local bus */ +#endif +#define XEMACPS_RX_BUF_ALIGNMENT 4U /**< Minimum buffer alignment when using + options that impose alignment + restrictions on the buffer data on + the local bus */ + +/** @name Direction identifiers + * + * These are used by several functions and callbacks that need + * to specify whether an operation specifies a send or receive channel. + * @{ + */ +#define XEMACPS_SEND 1U /**< send direction */ +#define XEMACPS_RECV 2U /**< receive direction */ +/*@}*/ + +/** @name MDC clock division + * currently supporting 8, 16, 32, 48, 64, 96, 128, 224. + * @{ + */ +typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48, + MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224 +} XEmacPs_MdcDiv; + +/*@}*/ + +#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in + bytes, 64, 128, ... 10240 */ +#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U + +#define XEMACPS_RX_BUF_UNIT 64U /**< Number of receive buffer bytes as a + unit, this is HW setup */ + +#define XEMACPS_MAX_RXBD 128U /**< Size of RX buffer descriptor queues */ +#define XEMACPS_MAX_TXBD 128U /**< Size of TX buffer descriptor queues */ + +#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */ + +/* Register offset definitions. Unless otherwise noted, register access is + * 32 bit. Names are self explained here. + */ + +#define XEMACPS_NWCTRL_OFFSET 0x00000000U /**< Network Control reg */ +#define XEMACPS_NWCFG_OFFSET 0x00000004U /**< Network Config reg */ +#define XEMACPS_NWSR_OFFSET 0x00000008U /**< Network Status reg */ + +#define XEMACPS_DMACR_OFFSET 0x00000010U /**< DMA Control reg */ +#define XEMACPS_TXSR_OFFSET 0x00000014U /**< TX Status reg */ +#define XEMACPS_RXQBASE_OFFSET 0x00000018U /**< RX Q Base address reg */ +#define XEMACPS_TXQBASE_OFFSET 0x0000001CU /**< TX Q Base address reg */ +#define XEMACPS_RXSR_OFFSET 0x00000020U /**< RX Status reg */ + +#define XEMACPS_ISR_OFFSET 0x00000024U /**< Interrupt Status reg */ +#define XEMACPS_IER_OFFSET 0x00000028U /**< Interrupt Enable reg */ +#define XEMACPS_IDR_OFFSET 0x0000002CU /**< Interrupt Disable reg */ +#define XEMACPS_IMR_OFFSET 0x00000030U /**< Interrupt Mask reg */ + +#define XEMACPS_PHYMNTNC_OFFSET 0x00000034U /**< Phy Maintaince reg */ +#define XEMACPS_RXPAUSE_OFFSET 0x00000038U /**< RX Pause Time reg */ +#define XEMACPS_TXPAUSE_OFFSET 0x0000003CU /**< TX Pause Time reg */ + +#define XEMACPS_JUMBOMAXLEN_OFFSET 0x00000048U /**< Jumbo max length reg */ + +#define XEMACPS_HASHL_OFFSET 0x00000080U /**< Hash Low address reg */ +#define XEMACPS_HASHH_OFFSET 0x00000084U /**< Hash High address reg */ + +#define XEMACPS_LADDR1L_OFFSET 0x00000088U /**< Specific1 addr low reg */ +#define XEMACPS_LADDR1H_OFFSET 0x0000008CU /**< Specific1 addr high reg */ +#define XEMACPS_LADDR2L_OFFSET 0x00000090U /**< Specific2 addr low reg */ +#define XEMACPS_LADDR2H_OFFSET 0x00000094U /**< Specific2 addr high reg */ +#define XEMACPS_LADDR3L_OFFSET 0x00000098U /**< Specific3 addr low reg */ +#define XEMACPS_LADDR3H_OFFSET 0x0000009CU /**< Specific3 addr high reg */ +#define XEMACPS_LADDR4L_OFFSET 0x000000A0U /**< Specific4 addr low reg */ +#define XEMACPS_LADDR4H_OFFSET 0x000000A4U /**< Specific4 addr high reg */ + +#define XEMACPS_MATCH1_OFFSET 0x000000A8U /**< Type ID1 Match reg */ +#define XEMACPS_MATCH2_OFFSET 0x000000ACU /**< Type ID2 Match reg */ +#define XEMACPS_MATCH3_OFFSET 0x000000B0U /**< Type ID3 Match reg */ +#define XEMACPS_MATCH4_OFFSET 0x000000B4U /**< Type ID4 Match reg */ + +#define XEMACPS_STRETCH_OFFSET 0x000000BCU /**< IPG Stretch reg */ + +#define XEMACPS_OCTTXL_OFFSET 0x00000100U /**< Octects transmitted Low + reg */ +#define XEMACPS_OCTTXH_OFFSET 0x00000104U /**< Octects transmitted High + reg */ + +#define XEMACPS_TXCNT_OFFSET 0x00000108U /**< Error-free Frmaes + transmitted counter */ +#define XEMACPS_TXBCCNT_OFFSET 0x0000010CU /**< Error-free Broadcast + Frames counter*/ +#define XEMACPS_TXMCCNT_OFFSET 0x00000110U /**< Error-free Multicast + Frame counter */ +#define XEMACPS_TXPAUSECNT_OFFSET 0x00000114U /**< Pause Frames Transmitted + Counter */ +#define XEMACPS_TX64CNT_OFFSET 0x00000118U /**< Error-free 64 byte Frames + Transmitted counter */ +#define XEMACPS_TX65CNT_OFFSET 0x0000011CU /**< Error-free 65-127 byte + Frames Transmitted + counter */ +#define XEMACPS_TX128CNT_OFFSET 0x00000120U /**< Error-free 128-255 byte + Frames Transmitted + counter*/ +#define XEMACPS_TX256CNT_OFFSET 0x00000124U /**< Error-free 256-511 byte + Frames transmitted + counter */ +#define XEMACPS_TX512CNT_OFFSET 0x00000128U /**< Error-free 512-1023 byte + Frames transmitted + counter */ +#define XEMACPS_TX1024CNT_OFFSET 0x0000012CU /**< Error-free 1024-1518 byte + Frames transmitted + counter */ +#define XEMACPS_TX1519CNT_OFFSET 0x00000130U /**< Error-free larger than + 1519 byte Frames + transmitted counter */ +#define XEMACPS_TXURUNCNT_OFFSET 0x00000134U /**< TX under run error + counter */ + +#define XEMACPS_SNGLCOLLCNT_OFFSET 0x00000138U /**< Single Collision Frame + Counter */ +#define XEMACPS_MULTICOLLCNT_OFFSET 0x0000013CU /**< Multiple Collision Frame + Counter */ +#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame + Counter */ +#define XEMACPS_LATECOLLCNT_OFFSET 0x00000144U /**< Late Collision Frame + Counter */ +#define XEMACPS_TXDEFERCNT_OFFSET 0x00000148U /**< Deferred Transmission + Frame Counter */ +#define XEMACPS_TXCSENSECNT_OFFSET 0x0000014CU /**< Transmit Carrier Sense + Error Counter */ + +#define XEMACPS_OCTRXL_OFFSET 0x00000150U /**< Octects Received register + Low */ +#define XEMACPS_OCTRXH_OFFSET 0x00000154U /**< Octects Received register + High */ + +#define XEMACPS_RXCNT_OFFSET 0x00000158U /**< Error-free Frames + Received Counter */ +#define XEMACPS_RXBROADCNT_OFFSET 0x0000015CU /**< Error-free Broadcast + Frames Received Counter */ +#define XEMACPS_RXMULTICNT_OFFSET 0x00000160U /**< Error-free Multicast + Frames Received Counter */ +#define XEMACPS_RXPAUSECNT_OFFSET 0x00000164U /**< Pause Frames + Received Counter */ +#define XEMACPS_RX64CNT_OFFSET 0x00000168U /**< Error-free 64 byte Frames + Received Counter */ +#define XEMACPS_RX65CNT_OFFSET 0x0000016CU /**< Error-free 65-127 byte + Frames Received Counter */ +#define XEMACPS_RX128CNT_OFFSET 0x00000170U /**< Error-free 128-255 byte + Frames Received Counter */ +#define XEMACPS_RX256CNT_OFFSET 0x00000174U /**< Error-free 256-512 byte + Frames Received Counter */ +#define XEMACPS_RX512CNT_OFFSET 0x00000178U /**< Error-free 512-1023 byte + Frames Received Counter */ +#define XEMACPS_RX1024CNT_OFFSET 0x0000017CU /**< Error-free 1024-1518 byte + Frames Received Counter */ +#define XEMACPS_RX1519CNT_OFFSET 0x00000180U /**< Error-free 1519-max byte + Frames Received Counter */ +#define XEMACPS_RXUNDRCNT_OFFSET 0x00000184U /**< Undersize Frames Received + Counter */ +#define XEMACPS_RXOVRCNT_OFFSET 0x00000188U /**< Oversize Frames Received + Counter */ +#define XEMACPS_RXJABCNT_OFFSET 0x0000018CU /**< Jabbers Received + Counter */ +#define XEMACPS_RXFCSCNT_OFFSET 0x00000190U /**< Frame Check Sequence + Error Counter */ +#define XEMACPS_RXLENGTHCNT_OFFSET 0x00000194U /**< Length Field Error + Counter */ +#define XEMACPS_RXSYMBCNT_OFFSET 0x00000198U /**< Symbol Error Counter */ +#define XEMACPS_RXALIGNCNT_OFFSET 0x0000019CU /**< Alignment Error Counter */ +#define XEMACPS_RXRESERRCNT_OFFSET 0x000001A0U /**< Receive Resource Error + Counter */ +#define XEMACPS_RXORCNT_OFFSET 0x000001A4U /**< Receive Overrun Counter */ +#define XEMACPS_RXIPCCNT_OFFSET 0x000001A8U /**< IP header Checksum Error + Counter */ +#define XEMACPS_RXTCPCCNT_OFFSET 0x000001ACU /**< TCP Checksum Error + Counter */ +#define XEMACPS_RXUDPCCNT_OFFSET 0x000001B0U /**< UDP Checksum Error + Counter */ +#define XEMACPS_LAST_OFFSET 0x000001B4U /**< Last statistic counter + offset, for clearing */ + +#define XEMACPS_1588_SEC_OFFSET 0x000001D0U /**< 1588 second counter */ +#define XEMACPS_1588_NANOSEC_OFFSET 0x000001D4U /**< 1588 nanosecond counter */ +#define XEMACPS_1588_ADJ_OFFSET 0x000001D8U /**< 1588 nanosecond + adjustment counter */ +#define XEMACPS_1588_INC_OFFSET 0x000001DCU /**< 1588 nanosecond + increment counter */ +#define XEMACPS_PTP_TXSEC_OFFSET 0x000001E0U /**< 1588 PTP transmit second + counter */ +#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit + nanosecond counter */ +#define XEMACPS_PTP_RXSEC_OFFSET 0x000001E8U /**< 1588 PTP receive second + counter */ +#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive + nanosecond counter */ +#define XEMACPS_PTPP_TXSEC_OFFSET 0x000001F0U /**< 1588 PTP peer transmit + second counter */ +#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit + nanosecond counter */ +#define XEMACPS_PTPP_RXSEC_OFFSET 0x000001F8U /**< 1588 PTP peer receive + second counter */ +#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive + nanosecond counter */ + +#define XEMACPS_INTQ1_STS_OFFSET 0x00000400U /**< Interrupt Q1 Status + reg */ +#define XEMACPS_TXQ1BASE_OFFSET 0x00000440U /**< TX Q1 Base address + reg */ +#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address + reg */ +#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base + reg */ +#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base + reg */ +#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable + reg */ +#define XEMACPS_INTQ1_IDR_OFFSET 0x00000620U /**< Interrupt Q1 Disable + reg */ +#define XEMACPS_INTQ1_IMR_OFFSET 0x00000640U /**< Interrupt Q1 Mask + reg */ + +/* Define some bit positions for registers. */ + +/** @name network control register bit definitions + * @{ + */ +#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK 0x00040000U /**< Flush a packet from + Rx SRAM */ +#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum + pause frame */ +#define XEMACPS_NWCTRL_PAUSETX_MASK 0x00000800U /**< Transmit pause frame */ +#define XEMACPS_NWCTRL_HALTTX_MASK 0x00000400U /**< Halt transmission + after current frame */ +#define XEMACPS_NWCTRL_STARTTX_MASK 0x00000200U /**< Start tx (tx_go) */ + +#define XEMACPS_NWCTRL_STATWEN_MASK 0x00000080U /**< Enable writing to + stat counters */ +#define XEMACPS_NWCTRL_STATINC_MASK 0x00000040U /**< Increment statistic + registers */ +#define XEMACPS_NWCTRL_STATCLR_MASK 0x00000020U /**< Clear statistic + registers */ +#define XEMACPS_NWCTRL_MDEN_MASK 0x00000010U /**< Enable MDIO port */ +#define XEMACPS_NWCTRL_TXEN_MASK 0x00000008U /**< Enable transmit */ +#define XEMACPS_NWCTRL_RXEN_MASK 0x00000004U /**< Enable receive */ +#define XEMACPS_NWCTRL_LOOPEN_MASK 0x00000002U /**< local loopback */ +/*@}*/ + +/** @name network configuration register bit definitions + * @{ + */ +#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of + non-standard preamble */ +#define XEMACPS_NWCFG_IPDSTRETCH_MASK 0x10000000U /**< enable transmit IPG */ +#define XEMACPS_NWCFG_SGMIIEN_MASK 0x08000000U /**< SGMII Enable */ +#define XEMACPS_NWCFG_FCSIGNORE_MASK 0x04000000U /**< disable rejection of + FCS error */ +#define XEMACPS_NWCFG_HDRXEN_MASK 0x02000000U /**< RX half duplex */ +#define XEMACPS_NWCFG_RXCHKSUMEN_MASK 0x01000000U /**< enable RX checksum + offload */ +#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause + Frames to memory */ +#define XEMACPS_NWCFG_DWIDTH_64_MASK 0x00200000U /**< 64 bit Data bus width */ +#define XEMACPS_NWCFG_MDC_SHIFT_MASK 18U /**< shift bits for MDC */ +#define XEMACPS_NWCFG_MDCCLKDIV_MASK 0x001C0000U /**< MDC Mask PCLK divisor */ +#define XEMACPS_NWCFG_FCSREM_MASK 0x00020000U /**< Discard FCS from + received frames */ +#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U +/**< RX length error discard */ +#define XEMACPS_NWCFG_RXOFFS_MASK 0x0000C000U /**< RX buffer offset */ +#define XEMACPS_NWCFG_PAUSEEN_MASK 0x00002000U /**< Enable pause RX */ +#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */ +#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U +/**< External address match enable */ +#define XEMACPS_NWCFG_PCSSEL_MASK 0x00000800U /**< PCS Select */ +#define XEMACPS_NWCFG_1000_MASK 0x00000400U /**< 1000 Mbps */ +#define XEMACPS_NWCFG_1536RXEN_MASK 0x00000100U /**< Enable 1536 byte + frames reception */ +#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash + frames */ +#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash + frames */ +#define XEMACPS_NWCFG_BCASTDI_MASK 0x00000020U /**< Do not receive + broadcast frames */ +#define XEMACPS_NWCFG_COPYALLEN_MASK 0x00000010U /**< Copy all frames */ +#define XEMACPS_NWCFG_JUMBO_MASK 0x00000008U /**< Jumbo frames */ +#define XEMACPS_NWCFG_NVLANDISC_MASK 0x00000004U /**< Receive only VLAN + frames */ +#define XEMACPS_NWCFG_FDEN_MASK 0x00000002U/**< full duplex */ +#define XEMACPS_NWCFG_100_MASK 0x00000001U /**< 100 Mbps */ +#define XEMACPS_NWCFG_RESET_MASK 0x00080000U/**< reset value */ +/*@}*/ + +/** @name network status register bit definitaions + * @{ + */ +#define XEMACPS_NWSR_MDIOIDLE_MASK 0x00000004U /**< PHY management idle */ +#define XEMACPS_NWSR_MDIO_MASK 0x00000002U /**< Status of mdio_in */ +/*@}*/ + + +/** @name MAC address register word 1 mask + * @{ + */ +#define XEMACPS_LADDR_MACH_MASK 0x0000FFFFU /**< Address bits[47:32] + bit[31:0] are in BOTTOM */ +/*@}*/ + + +/** @name DMA control register bit definitions + * @{ + */ +#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */ +#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */ +#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */ +#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer + size */ +#define XEMACPS_DMACR_RXBUF_SHIFT 16U /**< Shift bit for RX buffer + size */ +#define XEMACPS_DMACR_TCPCKSUM_MASK 0x00000800U /**< enable/disable TX + checksum offload */ +#define XEMACPS_DMACR_TXSIZE_MASK 0x00000400U /**< TX buffer memory size */ +#define XEMACPS_DMACR_RXSIZE_MASK 0x00000300U /**< RX buffer memory size */ +#define XEMACPS_DMACR_ENDIAN_MASK 0x00000080U /**< endian configuration */ +#define XEMACPS_DMACR_BLENGTH_MASK 0x0000001FU /**< buffer burst length */ +#define XEMACPS_DMACR_SINGLE_AHB_BURST 0x00000001U /**< single AHB bursts */ +#define XEMACPS_DMACR_INCR4_AHB_BURST 0x00000004U /**< 4 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR8_AHB_BURST 0x00000008U /**< 8 bytes AHB bursts */ +#define XEMACPS_DMACR_INCR16_AHB_BURST 0x00000010U /**< 16 bytes AHB bursts */ +/*@}*/ + +/** @name transmit status register bit definitions + * @{ + */ +#define XEMACPS_TXSR_HRESPNOK_MASK 0x00000100U /**< Transmit hresp not OK */ +#define XEMACPS_TXSR_URUN_MASK 0x00000040U /**< Transmit underrun */ +#define XEMACPS_TXSR_TXCOMPL_MASK 0x00000020U /**< Transmit completed OK */ +#define XEMACPS_TXSR_BUFEXH_MASK 0x00000010U /**< Transmit buffs exhausted + mid frame */ +#define XEMACPS_TXSR_TXGO_MASK 0x00000008U /**< Status of go flag */ +#define XEMACPS_TXSR_RXOVR_MASK 0x00000004U /**< Retry limit exceeded */ +#define XEMACPS_TXSR_FRAMERX_MASK 0x00000002U /**< Collision tx frame */ +#define XEMACPS_TXSR_USEDREAD_MASK 0x00000001U /**< TX buffer used bit set */ + +#define XEMACPS_TXSR_ERROR_MASK ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \ + (u32)XEMACPS_TXSR_URUN_MASK | \ + (u32)XEMACPS_TXSR_BUFEXH_MASK | \ + (u32)XEMACPS_TXSR_RXOVR_MASK | \ + (u32)XEMACPS_TXSR_FRAMERX_MASK | \ + (u32)XEMACPS_TXSR_USEDREAD_MASK) +/*@}*/ + +/** + * @name receive status register bit definitions + * @{ + */ +#define XEMACPS_RXSR_HRESPNOK_MASK 0x00000008U /**< Receive hresp not OK */ +#define XEMACPS_RXSR_RXOVR_MASK 0x00000004U /**< Receive overrun */ +#define XEMACPS_RXSR_FRAMERX_MASK 0x00000002U /**< Frame received OK */ +#define XEMACPS_RXSR_BUFFNA_MASK 0x00000001U /**< RX buffer used bit set */ + +#define XEMACPS_RXSR_ERROR_MASK ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \ + (u32)XEMACPS_RXSR_RXOVR_MASK | \ + (u32)XEMACPS_RXSR_BUFFNA_MASK) +/*@}*/ + +/** + * @name Interrupt Q1 status register bit definitions + * @{ + */ +#define XEMACPS_INTQ1SR_TXCOMPL_MASK 0x00000080U /**< Transmit completed OK */ +#define XEMACPS_INTQ1SR_TXERR_MASK 0x00000040U /**< Transmit AMBA Error */ + +#define XEMACPS_INTQ1_IXR_ALL_MASK ((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \ + (u32)XEMACPS_INTQ1SR_TXERR_MASK) + +/*@}*/ + +/** + * @name interrupts bit definitions + * Bits definitions are same in XEMACPS_ISR_OFFSET, + * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET + * @{ + */ +#define XEMACPS_IXR_PTPPSTX_MASK 0x02000000U /**< PTP Psync transmitted */ +#define XEMACPS_IXR_PTPPDRTX_MASK 0x01000000U /**< PTP Pdelay_req + transmitted */ +#define XEMACPS_IXR_PTPSTX_MASK 0x00800000U /**< PTP Sync transmitted */ +#define XEMACPS_IXR_PTPDRTX_MASK 0x00400000U /**< PTP Delay_req transmitted + */ +#define XEMACPS_IXR_PTPPSRX_MASK 0x00200000U /**< PTP Psync received */ +#define XEMACPS_IXR_PTPPDRRX_MASK 0x00100000U /**< PTP Pdelay_req received */ +#define XEMACPS_IXR_PTPSRX_MASK 0x00080000U /**< PTP Sync received */ +#define XEMACPS_IXR_PTPDRRX_MASK 0x00040000U /**< PTP Delay_req received */ +#define XEMACPS_IXR_PAUSETX_MASK 0x00004000U /**< Pause frame transmitted */ +#define XEMACPS_IXR_PAUSEZERO_MASK 0x00002000U /**< Pause time has reached + zero */ +#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U /**< Pause frame received */ +#define XEMACPS_IXR_HRESPNOK_MASK 0x00000800U /**< hresp not ok */ +#define XEMACPS_IXR_RXOVR_MASK 0x00000400U /**< Receive overrun occurred */ +#define XEMACPS_IXR_TXCOMPL_MASK 0x00000080U /**< Frame transmitted ok */ +#define XEMACPS_IXR_TXEXH_MASK 0x00000040U /**< Transmit err occurred or + no buffers*/ +#define XEMACPS_IXR_RETRY_MASK 0x00000020U /**< Retry limit exceeded */ +#define XEMACPS_IXR_URUN_MASK 0x00000010U /**< Transmit underrun */ +#define XEMACPS_IXR_TXUSED_MASK 0x00000008U /**< Tx buffer used bit read */ +#define XEMACPS_IXR_RXUSED_MASK 0x00000004U /**< Rx buffer used bit read */ +#define XEMACPS_IXR_FRAMERX_MASK 0x00000002U /**< Frame received ok */ +#define XEMACPS_IXR_MGMNT_MASK 0x00000001U /**< PHY management complete */ +#define XEMACPS_IXR_ALL_MASK 0x00007FFFU /**< Everything! */ + +#define XEMACPS_IXR_TX_ERR_MASK ((u32)XEMACPS_IXR_TXEXH_MASK | \ + (u32)XEMACPS_IXR_RETRY_MASK | \ + (u32)XEMACPS_IXR_URUN_MASK) + + +#define XEMACPS_IXR_RX_ERR_MASK ((u32)XEMACPS_IXR_HRESPNOK_MASK | \ + (u32)XEMACPS_IXR_RXUSED_MASK | \ + (u32)XEMACPS_IXR_RXOVR_MASK) + +/*@}*/ + +/** @name PHY Maintenance bit definitions + * @{ + */ +#define XEMACPS_PHYMNTNC_OP_MASK 0x40020000U /**< operation mask bits */ +#define XEMACPS_PHYMNTNC_OP_R_MASK 0x20000000U /**< read operation */ +#define XEMACPS_PHYMNTNC_OP_W_MASK 0x10000000U /**< write operation */ +#define XEMACPS_PHYMNTNC_ADDR_MASK 0x0F800000U /**< Address bits */ +#define XEMACPS_PHYMNTNC_REG_MASK 0x007C0000U /**< register bits */ +#define XEMACPS_PHYMNTNC_DATA_MASK 0x00000FFFU /**< data bits */ +#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK 23U /**< Shift bits for PHYAD */ +#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK 18U /**< Shift bits for PHREG */ +/*@}*/ + +/* Transmit buffer descriptor status words offset + * @{ + */ +#define XEMACPS_BD_ADDR_OFFSET 0x00000000U /**< word 0/addr of BDs */ +#define XEMACPS_BD_STAT_OFFSET 0x00000004U /**< word 1/status of BDs */ +#define XEMACPS_BD_ADDR_HI_OFFSET 0x00000008U /**< word 2/addr of BDs */ + +/* + * @} + */ + +/* Transmit buffer descriptor status words bit positions. + * Transmit buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit address pointing to the location of + * the transmit data. + * The following register - word1, consists of various information to control + * the XEmacPs transmit process. After transmit, this is updated with status + * information, whether the frame was transmitted OK or why it had failed. + * @{ + */ +#define XEMACPS_TXBUF_USED_MASK 0x80000000U /**< Used bit. */ +#define XEMACPS_TXBUF_WRAP_MASK 0x40000000U /**< Wrap bit, last descriptor */ +#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */ +#define XEMACPS_TXBUF_URUN_MASK 0x10000000U /**< Transmit underrun occurred */ +#define XEMACPS_TXBUF_EXH_MASK 0x08000000U /**< Buffers exhausted */ +#define XEMACPS_TXBUF_TCP_MASK 0x04000000U /**< Late collision. */ +#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */ +#define XEMACPS_TXBUF_LAST_MASK 0x00008000U /**< Last buffer */ +#define XEMACPS_TXBUF_LEN_MASK 0x00003FFFU /**< Mask for length field */ +/* + * @} + */ + +/* Receive buffer descriptor status words bit positions. + * Receive buffer descriptor consists of two 32-bit registers, + * the first - word0 contains a 32-bit word aligned address pointing to the + * address of the buffer. The lower two bits make up the wrap bit indicating + * the last descriptor and the ownership bit to indicate it has been used by + * the XEmacPs. + * The following register - word1, contains status information regarding why + * the frame was received (the filter match condition) as well as other + * useful info. + * @{ + */ +#define XEMACPS_RXBUF_BCAST_MASK 0x80000000U /**< Broadcast frame */ +#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */ +#define XEMACPS_RXBUF_UNIHASH_MASK 0x20000000U /**< Unicast hashed frame */ +#define XEMACPS_RXBUF_EXH_MASK 0x08000000U /**< buffer exhausted */ +#define XEMACPS_RXBUF_AMATCH_MASK 0x06000000U /**< Specific address + matched */ +#define XEMACPS_RXBUF_IDFOUND_MASK 0x01000000U /**< Type ID matched */ +#define XEMACPS_RXBUF_IDMATCH_MASK 0x00C00000U /**< ID matched mask */ +#define XEMACPS_RXBUF_VLAN_MASK 0x00200000U /**< VLAN tagged */ +#define XEMACPS_RXBUF_PRI_MASK 0x00100000U /**< Priority tagged */ +#define XEMACPS_RXBUF_VPRI_MASK 0x000E0000U /**< Vlan priority */ +#define XEMACPS_RXBUF_CFI_MASK 0x00010000U /**< CFI frame */ +#define XEMACPS_RXBUF_EOF_MASK 0x00008000U /**< End of frame. */ +#define XEMACPS_RXBUF_SOF_MASK 0x00004000U /**< Start of frame. */ +#define XEMACPS_RXBUF_LEN_MASK 0x00001FFFU /**< Mask for length field */ +#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */ + +#define XEMACPS_RXBUF_WRAP_MASK 0x00000002U /**< Wrap bit, last BD */ +#define XEMACPS_RXBUF_NEW_MASK 0x00000001U /**< Used bit.. */ +#define XEMACPS_RXBUF_ADD_MASK 0xFFFFFFFCU /**< Mask for address */ +/* + * @} + */ + +/* + * Define appropriate I/O access method to memory mapped I/O or other + * interface if necessary. + */ + +#define XEmacPs_In32 Xil_In32 +#define XEmacPs_Out32 Xil_Out32 + + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XEmacPs_ReadReg(BaseAddress, RegOffset) \ + XEmacPs_In32((BaseAddress) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddress is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \ + XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the emacps interface + */ +void XEmacPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus + } +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv.h new file mode 100644 index 0000000..3d97beb --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv.h @@ -0,0 +1,187 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv.h +* +* Defines common services that are typically found in a host operating. +* environment. This include file simply includes an OS specific file based +* on the compile-time constant BUILD_ENV_*, where * is the name of the target +* environment. +* +* All services are defined as macros. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+*
    +* +******************************************************************************/ + +#ifndef XENV_H /* prevent circular inclusions */ +#define XENV_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Select which target environment we are operating under + */ + +/* VxWorks target environment */ +#if defined XENV_VXWORKS +#include "xenv_vxworks.h" + +/* Linux target environment */ +#elif defined XENV_LINUX +#include "xenv_linux.h" + +/* Unit test environment */ +#elif defined XENV_UNITTEST +#include "ut_xenv.h" + +/* Integration test environment */ +#elif defined XENV_INTTEST +#include "int_xenv.h" + +/* Standalone environment selected */ +#else +#include "xenv_standalone.h" +#endif + + +/* + * The following comments specify the types and macro wrappers that are + * expected to be defined by the target specific header files + */ + +/**************************** Type Definitions *******************************/ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP + * + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes) + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr is the destination address to copy data to. + * @param SrcPtr is the source address to copy data from. + * @param Bytes is the number of bytes to copy. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes) + * + * Fills an area of memory with constant data. + * + * @param DestPtr is the destination address to set. + * @param Data contains the value to set. + * @param Bytes is the number of bytes to set. + * + * @return None + */ +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + * + * Samples the processor's or external timer's time base counter. + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of microseconds. + */ + +/*****************************************************************************/ +/** + * + * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr) + * + * Computes the delta between the two time stamps. + * + * @param Stamp1Ptr - First sampled time stamp. + * @param Stamp1Ptr - Sedond sampled time stamp. + * + * @return An unsigned int value with units of milliseconds. + */ + +/*****************************************************************************//** + * + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. + * + * @param delay is the number of microseconds to delay. + * + * @return None + */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv_standalone.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv_standalone.h new file mode 100644 index 0000000..f186018 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xenv_standalone.h @@ -0,0 +1,368 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xenv_standalone.h +* +* Defines common services specified by xenv.h. +* +* @note +* This file is not intended to be included directly by driver code. +* Instead, the generic xenv.h file is intended to be included by driver +* code. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+*
    +* +* +******************************************************************************/ + +#ifndef XENV_STANDALONE_H +#define XENV_STANDALONE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +/****************************************************************************** + * + * Get the processor dependent includes + * + ******************************************************************************/ + +#include + +#if defined __MICROBLAZE__ +# include "mb_interface.h" +# include "xparameters.h" /* XPAR constants used below in MB section */ + +#elif defined __PPC__ +# include "sleep.h" +# include "xcache_l.h" /* also include xcache_l.h for caching macros */ +#endif + +/****************************************************************************** + * + * MEMCPY / MEMSET related macros. + * + * The following are straight forward implementations of memset and memcpy. + * + * NOTE: memcpy may not work if source and target memory area are overlapping. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * Copies a non-overlapping block of memory. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param SrcPtr + * Source address to copy data from. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_COPY is deprecated. Use memcpy() instead. + * + * @note + * This implemention MAY BREAK work if source and target memory + * area are overlapping. + * + *****************************************************************************/ + +#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \ + memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes) + + + +/*****************************************************************************/ +/** + * + * Fills an area of memory with constant data. + * + * @param DestPtr + * Destination address to copy data to. + * + * @param Data + * Value to set. + * + * @param Bytes + * Number of bytes to copy. + * + * @return None. + * + * @note + * The use of XENV_MEM_FILL is deprecated. Use memset() instead. + * + *****************************************************************************/ + +#define XENV_MEM_FILL(DestPtr, Data, Bytes) \ + memset((void *) DestPtr, (s32) Data, (size_t) Bytes) + + + +/****************************************************************************** + * + * TIME related macros + * + ******************************************************************************/ + +/** + * A structure that contains a time stamp used by other time stamp macros + * defined below. This structure is processor dependent. + */ +typedef s32 XENV_TIME_STAMP; + +/*****************************************************************************/ +/** + * + * Time is derived from the 64 bit PPC timebase register + * + * @param StampPtr is the storage for the retrieved time stamp. + * + * @return None. + * + * @note + * + * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr) + *

    + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_GET(StampPtr) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * + * This macro is not yet implemented and always returns 0. + * + * @param Stamp1Ptr is the first sampled time stamp. + * @param Stamp2Ptr is the second sampled time stamp. + * + * @return 0 + * + * @note + * + * This macro must be implemented by the user. + * + *****************************************************************************/ +#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr) (0) + +/*****************************************************************************/ +/** + * XENV_USLEEP(unsigned delay) + * + * Delay the specified number of microseconds. Not implemented without OS + * support. + * + * @param delay + * Number of microseconds to delay. + * + * @return None. + * + *****************************************************************************/ + +#ifdef __PPC__ +#define XENV_USLEEP(delay) usleep(delay) +#define udelay(delay) usleep(delay) +#else +#define XENV_USLEEP(delay) +#define udelay(delay) +#endif + + +/****************************************************************************** + * + * CACHE handling macros / mappings + * + ******************************************************************************/ +/****************************************************************************** + * + * Processor independent macros + * + ******************************************************************************/ + +#define XCACHE_ENABLE_CACHE() \ + { XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); } + +#define XCACHE_DISABLE_CACHE() \ + { XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); } + + +/****************************************************************************** + * + * MicroBlaze case + * + * NOTE: Currently the following macros will only work on systems that contain + * only ONE MicroBlaze processor. Also, the macros will only be enabled if the + * system is built using a xparameters.h file. + * + ******************************************************************************/ + +#if defined __MICROBLAZE__ + +/* Check if MicroBlaze data cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_DCACHE == 1) +# define XCACHE_ENABLE_DCACHE() microblaze_enable_dcache() +# define XCACHE_DISABLE_DCACHE() microblaze_disable_dcache() +# define XCACHE_INVALIDATE_DCACHE() microblaze_invalidate_dcache() + +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) + +#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1) +# define XCACHE_FLUSH_DCACHE() microblaze_flush_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_flush_dcache_range((s32)(Addr), (s32)(Len)) +#else +# define XCACHE_FLUSH_DCACHE() microblaze_invalidate_dcache() +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len)) +#endif /*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/ + +#else +# define XCACHE_ENABLE_DCACHE() +# define XCACHE_DISABLE_DCACHE() +# define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) +# define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) +#endif /*XPAR_MICROBLAZE_USE_DCACHE*/ + + +/* Check if MicroBlaze instruction cache was built into the core. + */ +#if (XPAR_MICROBLAZE_USE_ICACHE == 1) +# define XCACHE_ENABLE_ICACHE() microblaze_enable_icache() +# define XCACHE_DISABLE_ICACHE() microblaze_disable_icache() + +# define XCACHE_INVALIDATE_ICACHE() microblaze_invalidate_icache() + +# define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \ + microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len)) + +#else +# define XCACHE_ENABLE_ICACHE() +# define XCACHE_DISABLE_ICACHE() +#endif /*XPAR_MICROBLAZE_USE_ICACHE*/ + + +/****************************************************************************** + * + * PowerPC case + * + * Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a + * specific memory region (0x80000001). Each bit (0-30) in the regions + * bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB + * range. + * + * regions --> cached address range + * ------------|-------------------------------------------------- + * 0x80000000 | [0, 0x7FFFFFF] + * 0x00000001 | [0xF8000000, 0xFFFFFFFF] + * 0x80000001 | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF] + * + ******************************************************************************/ + +#elif defined __PPC__ + +#define XCACHE_ENABLE_DCACHE() XCache_EnableDCache(0x80000001) +#define XCACHE_DISABLE_DCACHE() XCache_DisableDCache() +#define XCACHE_ENABLE_ICACHE() XCache_EnableICache(0x80000001) +#define XCACHE_DISABLE_ICACHE() XCache_DisableICache() + +#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \ + XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \ + XCache_FlushDCacheRange((u32)(Addr), (u32)(Len)) + +#define XCACHE_INVALIDATE_ICACHE() XCache_InvalidateICache() + + +/****************************************************************************** + * + * Unknown processor / architecture + * + ******************************************************************************/ + +#else +/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef XENV_STANDALONE_H */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops.h new file mode 100644 index 0000000..fda562d --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops.h @@ -0,0 +1,277 @@ + +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xgpiops.h +* @addtogroup gpiops_v3_3 +* @{ +* @details +* +* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO +* Controller. +* +* The GPIO Controller supports the following features: +* - 4 banks +* - Masked writes (There are no masked reads) +* - Bypass mode +* - Configurable Interrupts (Level/Edge) +* +* This driver is intended to be RTOS and processor independent. Any needs for +* dynamic memory management, threads or thread mutual exclusion, virtual +* memory, or cache control must be satisfied by the layer above this driver. + +* This driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the GPIO. +* +* Interrupts +* +* The driver provides interrupt management functions and an interrupt handler. +* Users of this driver need to provide callback functions. An interrupt handler +* example is available with the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XGpioPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

    +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*       ms   04/05/17 Added tabspace for return statements in functions of
+*                     gpiops examples for proper documentation while
+*                     generating doxygen.
+* 3.3   ms   04/17/17 Added notes about gpio input and output pin description
+*                     for zcu102 and zc702 boards in polled and interrupt
+*                     example, configured Interrupt pin to input pin for
+*                     proper functioning of interrupt example.
+*
    +* +******************************************************************************/ +#ifndef XGPIOPS_H /* prevent circular inclusions */ +#define XGPIOPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xgpiops_hw.h" +#include "xplatform_info.h" + +/************************** Constant Definitions *****************************/ + +/** @name Interrupt types + * @{ + * The following constants define the interrupt types that can be set for each + * GPIO pin. + */ +#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */ +#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */ +#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */ +#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */ +/*@}*/ + +#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */ +#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */ +#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */ +#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */ +#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */ + +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_BANK4 0x04U /**< GPIO Bank 4 */ +#define XGPIOPS_BANK5 0x05U /**< GPIO Bank 5 */ +#endif + +#define XGPIOPS_MAX_BANKS_ZYNQMP 0x06U /**< Max banks in a + * Zynq Ultrascale+ MP GPIO device + */ +#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a Zynq GPIO device */ + +#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP (u32)174 /**< Max pins in the + * Zynq Ultrascale+ MP GPIO device + * 0 - 25, Bank 0 + * 26 - 51, Bank 1 + * 52 - 77, Bank 2 + * 78 - 109, Bank 3 + * 110 - 141, Bank 4 + * 142 - 173, Bank 5 + */ +#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /**< Max pins in the Zynq GPIO device + * 0 - 31, Bank 0 + * 32 - 53, Bank 1 + * 54 - 85, Bank 2 + * 86 - 117, Bank 3 + */ + +/**************************** Type Definitions *******************************/ + +/****************************************************************************/ +/** + * This handler data type allows the user to define a callback function to + * handle the interrupts for the GPIO device. The application using this + * driver is expected to define a handler of this type, to support interrupt + * driven mode. The handler executes in an interrupt context such that minimal + * processing should be performed. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions for a GPIO bank. It is + * passed back to the upper layer when the callback is invoked. Its + * type is not important to the driver component, so it is a void + * pointer. + * @param Bank is the bank for which the interrupt status has changed. + * @param Status is the Interrupt status of the GPIO bank. + * + *****************************************************************************/ +typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status); + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XGpioPs_Config; + +/** + * The XGpioPs driver instance data. The user is required to allocate a + * variable of this type for the GPIO device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XGpioPs_Config GpioConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + XGpioPs_Handler Handler; /**< Status handlers for all banks */ + void *CallBackRef; /**< Callback ref for bank handlers */ + u32 Platform; /**< Platform data */ + u32 MaxPinNum; /**< Max pins in the GPIO device */ + u8 MaxBanks; /**< Max banks in a GPIO device */ +} XGpioPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/* Functions in xgpiops.c */ +s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr, + u32 EffectiveAddr); + +/* Bank APIs in xgpiops.c */ +u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data); +void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction); +u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable); +u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank); + +/* Pin APIs in xgpiops.c */ +u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data); +void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction); +u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable); +u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin); + +/* Diagnostic functions in xgpiops_selftest.c */ +s32 XGpioPs_SelfTest(XGpioPs *InstancePtr); + +/* Functions in xgpiops_intr.c */ +/* Bank APIs in xgpiops_intr.c */ +void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank); +u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank); +void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask); +void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType, + u32 IntrPolarity, u32 IntrOnAny); +void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType, + u32 *IntrPolarity, u32 *IntrOnAny); +void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef, + XGpioPs_Handler FuncPointer); +void XGpioPs_IntrHandler(XGpioPs *InstancePtr); + +/* Pin APIs in xgpiops_intr.c */ +void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType); +u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin); + +void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin); +u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin); +void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin); + +/* Functions in xgpiops_sinit.c */ +XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops_hw.h new file mode 100644 index 0000000..ff01906 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xgpiops_hw.h @@ -0,0 +1,164 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xgpiops_hw.h +* @addtogroup gpiops_v3_3 +* @{ +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xgpiops.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+*
    +* +******************************************************************************/ +#ifndef XGPIOPS_HW_H /* prevent circular inclusions */ +#define XGPIOPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the GPIO. Each register is 32 bits. + * @{ + */ +#define XGPIOPS_DATA_LSW_OFFSET 0x00000000U /* Mask and Data Register LSW, WO */ +#define XGPIOPS_DATA_MSW_OFFSET 0x00000004U /* Mask and Data Register MSW, WO */ +#define XGPIOPS_DATA_OFFSET 0x00000040U /* Data Register, RW */ +#define XGPIOPS_DATA_RO_OFFSET 0x00000060U /* Data Register - Input, RO */ +#define XGPIOPS_DIRM_OFFSET 0x00000204U /* Direction Mode Register, RW */ +#define XGPIOPS_OUTEN_OFFSET 0x00000208U /* Output Enable Register, RW */ +#define XGPIOPS_INTMASK_OFFSET 0x0000020CU /* Interrupt Mask Register, RO */ +#define XGPIOPS_INTEN_OFFSET 0x00000210U /* Interrupt Enable Register, WO */ +#define XGPIOPS_INTDIS_OFFSET 0x00000214U /* Interrupt Disable Register, WO*/ +#define XGPIOPS_INTSTS_OFFSET 0x00000218U /* Interrupt Status Register, RO */ +#define XGPIOPS_INTTYPE_OFFSET 0x0000021CU /* Interrupt Type Register, RW */ +#define XGPIOPS_INTPOL_OFFSET 0x00000220U /* Interrupt Polarity Register, RW */ +#define XGPIOPS_INTANY_OFFSET 0x00000224U /* Interrupt On Any Register, RW */ +/* @} */ + +/** @name Register offsets for each Bank. + * @{ + */ +#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U /* Data/Mask Registers offset */ +#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U /* Data Registers offset */ +#define XGPIOPS_REG_MASK_OFFSET 0x00000040U /* Registers offset */ +/* @} */ + +/* For backwards compatibility */ +#define XGPIOPS_BYPM_MASK_OFFSET (u32)0x40 + +/** @name Interrupt type reset values for each bank + * @{ + */ +#ifdef XPAR_PSU_GPIO_0_BASEADDR +#define XGPIOPS_INTTYPE_BANK0_RESET 0x03FFFFFFU /* Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK1_RESET 0x03FFFFFFU +#define XGPIOPS_INTTYPE_BANK2_RESET 0x03FFFFFFU +#else +#define XGPIOPS_INTTYPE_BANK0_RESET 0xFFFFFFFFU /* Resets specific to Zynq */ +#define XGPIOPS_INTTYPE_BANK1_RESET 0x003FFFFFU +#define XGPIOPS_INTTYPE_BANK2_RESET 0xFFFFFFFFU +#endif + +#define XGPIOPS_INTTYPE_BANK3_RESET 0xFFFFFFFFU /* Reset common to both platforms */ +#define XGPIOPS_INTTYPE_BANK4_RESET 0xFFFFFFFFU /* Resets specific to Zynq Ultrascale+ MP */ +#define XGPIOPS_INTTYPE_BANK5_RESET 0xFFFFFFFFU +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + +/****************************************************************************/ +/** +* +* This macro writes to the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the offset of the register to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ + +void XGpioPs_ResetHw(u32 BaseAddress); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XGPIOPS_HW_H */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps.h new file mode 100644 index 0000000..d3713de --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps.h @@ -0,0 +1,425 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xiicps.h +* @addtogroup iicps_v3_7 +* @{ +* @details +* +* This is an implementation of IIC driver in the PS block. The device can +* be either a master or a slave on the IIC bus. This implementation supports +* both interrupt mode transfer and polled mode transfer. Only 7-bit address +* is used in the driver, although the hardware also supports 10-bit address. +* +* IIC is a 2-wire serial interface. The master controls the clock, so it can +* regulate when it wants to send or receive data. The slave is under control of +* the master, it must respond quickly since it has no control of the clock and +* must send/receive data as fast or as slow as the master does. +* +* The higher level software must implement a higher layer protocol to inform +* the slave what to send to the master. +* +* Initialization & Configuration +* +* The XIicPs_Config structure is used by the driver to configure itself. This +* configuration structure is typically created by the tool-chain based on HW +* build properties. +* +* To support multiple runtime loading and initialization strategies employed by +* various operating systems, the driver instance can be initialized in the +* following way: +* +* - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find +* the static configuration structure defined in xiicps_g.c. This is +* setup by the tools. For some operating systems the config structure +* will be initialized by the software and this call is not needed. +* +* - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a +* system with address translation, the provided virtual memory base +* address replaces the physical address in the configuration +* structure. +* +* Multiple Masters +* +* More than one master can exist, bus arbitration is defined in the IIC +* standard. Lost of arbitration causes arbitration loss interrupt on the device. +* +* Multiple Slaves +* +* Multiple slaves are supported by selecting them with unique addresses. It is +* up to the system designer to be sure all devices on the IIC bus have +* unique addresses. +* +* Addressing +* +* The IIC hardware can use 7 or 10 bit addresses. The driver provides the +* ability to control which address size is sent in messages as a master to a +* slave device. +* +* FIFO Size +* The hardware FIFO is 32 bytes deep. The user must know the limitations of +* other IIC devices on the bus. Some are only able to receive a limited number +* of bytes in a single transfer. +* +* Data Rates +* +* The data rate is set by values in the control register. The formula for +* determining the correct register values is: +* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1)) +* +* When the device is configured as a slave, the slck setting controls the +* sample rate and so must be set to be at least as fast as the fastest scl +* expected to be seen in the system. +* +* Polled Mode Operation +* +* This driver supports polled mode transfers. +* +* Interrupts +* +* The user must connect the interrupt handler of the driver, +* XIicPs_InterruptHandler to an interrupt system such that it will be called +* when an interrupt occurs. This function does not save and restore the +* processor context such that the user must provide this processing. +* +* The driver handles the following interrupts: +* - Transfer complete +* - More Data +* - Transfer not Acknowledged +* - Transfer Time out +* - Monitored slave ready - master mode only +* - Receive Overflow +* - Transmit FIFO overflow +* - Receive FIFO underflow +* - Arbitration lost +* +* Bus Busy +* +* Bus busy is checked before the setup of a master mode device, to avoid +* unnecessary arbitration loss interrupt. +* +* RTOS Independence +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads or +* thread mutual exclusion, virtual memory, or cache control must be satisfied by +* the layer above this driver. +* +*Repeated Start +* +* The I2C controller does not indicate completion of a receive transfer if HOLD +* bit is set. Due to this errata, repeated start cannot be used if a receive +* transfer is followed by any other transfer. +* +* 
     MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                    read mode and clear transfer size register.
+*                    Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	10/07/14 Repeated start feature deleted.
+* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
+* 					 in XIicPs_Reset.
+* 			12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* 3.7   ask  04/17/18 Updated the Eeprom scanning mechanism
+*                     as per the other examples (CR#997545)
+*
+*
    +* +******************************************************************************/ + +#ifndef XIICPS_H /* prevent circular inclusions */ +#define XIICPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xiicps_hw.h" +#include "xplatform_info.h" + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * The following options may be specified or retrieved for the device and + * enable/disable additional features of the IIC. Each of the options + * are bit fields, so more than one may be specified. + * + * @{ + */ +#define XIICPS_7_BIT_ADDR_OPTION 0x01U /**< 7-bit address mode */ +#define XIICPS_10_BIT_ADDR_OPTION 0x02U /**< 10-bit address mode */ +#define XIICPS_SLAVE_MON_OPTION 0x04U /**< Slave monitor mode */ +#define XIICPS_REP_START_OPTION 0x08U /**< Repeated Start */ +/*@}*/ + +/** @name Callback events + * + * These constants specify the handler events that are passed to an application + * event handler from the driver. These constants are bit masks such that + * more than one event can be passed to the handler. + * + * @{ + */ +#define XIICPS_EVENT_COMPLETE_SEND 0x0001U /**< Transmit Complete Event*/ +#define XIICPS_EVENT_COMPLETE_RECV 0x0002U /**< Receive Complete Event*/ +#define XIICPS_EVENT_TIME_OUT 0x0004U /**< Transfer timed out */ +#define XIICPS_EVENT_ERROR 0x0008U /**< Receive error */ +#define XIICPS_EVENT_ARB_LOST 0x0010U /**< Arbitration lost */ +#define XIICPS_EVENT_NACK 0x0020U /**< NACK Received */ +#define XIICPS_EVENT_SLAVE_RDY 0x0040U /**< Slave ready */ +#define XIICPS_EVENT_RX_OVR 0x0080U /**< RX overflow */ +#define XIICPS_EVENT_TX_OVR 0x0100U /**< TX overflow */ +#define XIICPS_EVENT_RX_UNF 0x0200U /**< RX underflow */ +/*@}*/ + +/** @name Role constants + * + * These constants are used to pass into the device setup routines to + * set up the device according to transfer direction. + */ +#define SENDING_ROLE 1 /**< Transfer direction is sending */ +#define RECVING_ROLE 0 /**< Transfer direction is receiving */ + +/* Maximum transfer size */ +#define XIICPS_MAX_TRANSFER_SIZE (u32)(255U - 3U) + +/**************************** Type Definitions *******************************/ + +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* not important to the driver, so it is a void pointer. +* @param StatusEvent indicates one or more status events that occurred. +*/ +typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ +} XIicPs_Config; + +/** + * The XIicPs driver instance data. The user is required to allocate a + * variable of this type for each IIC device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XIicPs_Config Config; /* Configuration structure */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Options set in the device */ + + u8 *SendBufferPtr; /* Pointer to send buffer */ + u8 *RecvBufferPtr; /* Pointer to recv buffer */ + s32 SendByteCount; /* Number of bytes still expected to send */ + s32 RecvByteCount; /* Number of bytes still expected to receive */ + s32 CurrByteCount; /* No. of bytes expected in current transfer */ + + s32 UpdateTxSize; /* If tx size register has to be updated */ + s32 IsSend; /* Whether master is sending or receiving */ + s32 IsRepeatedStart; /* Indicates if user set repeated start */ + + XIicPs_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XIicPs; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/* +* +* Place one byte into the transmit FIFO. +* +* @param InstancePtr is the instance of IIC +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_SendByte(XIicPs *InstancePtr) +* +*****************************************************************************/ +#define XIicPs_SendByte(InstancePtr) \ +{ \ + u8 Data; \ + Data = *((InstancePtr)->SendBufferPtr); \ + XIicPs_Out32((InstancePtr)->Config.BaseAddress \ + + (u32)(XIICPS_DATA_OFFSET), \ + (u32)(Data)); \ + (InstancePtr)->SendBufferPtr += 1; \ + (InstancePtr)->SendByteCount -= 1;\ +} + +/****************************************************************************/ +/* +* +* Receive one byte from FIFO. +* +* @param InstancePtr is the instance of IIC +* +* @return None. +* +* @note C-Style signature: +* u8 XIicPs_RecvByte(XIicPs *InstancePtr) +* +*****************************************************************************/ +#define XIicPs_RecvByte(InstancePtr) \ +{ \ + u8 *Data, Value; \ + Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress \ + + (u32)XIICPS_DATA_OFFSET)); \ + Data = &Value; \ + *(InstancePtr)->RecvBufferPtr = *Data; \ + (InstancePtr)->RecvBufferPtr += 1; \ + (InstancePtr)->RecvByteCount --; \ +} + +/************************** Function Prototypes ******************************/ + +/* + * Function for configuration lookup, in xiicps_sinit.c + */ +XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId); + +/* + * Functions for general setup, in xiicps.c + */ +s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr, + u32 EffectiveAddr); + +void XIicPs_Abort(XIicPs *InstancePtr); +void XIicPs_Reset(XIicPs *InstancePtr); + +s32 XIicPs_BusIsBusy(XIicPs *InstancePtr); +s32 TransmitFifoFill(XIicPs *InstancePtr); + +/* + * Functions for interrupts, in xiicps_intr.c + */ +void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef, + XIicPs_IntrHandler FunctionPtr); + +/* + * Functions for device as master, in xiicps_master.c + */ +void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, + u16 SlaveAddr); +void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, + u16 SlaveAddr); +s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, + u16 SlaveAddr); +s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, + u16 SlaveAddr); +void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr); +void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr); +void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr); + +/* + * Functions for device as slave, in xiicps_slave.c + */ +void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr); +void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount); +void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount); +s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount); +s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount); +void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr); + +/* + * Functions for selftest, in xiicps_selftest.c + */ +s32 XIicPs_SelfTest(XIicPs *InstancePtr); + +/* + * Functions for setting and getting data rate, in xiicps_options.c + */ +s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options); +s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options); +u32 XIicPs_GetOptions(XIicPs *InstancePtr); + +s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz); +u32 XIicPs_GetSClk(XIicPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps_hw.h new file mode 100644 index 0000000..e9d63ec --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xiicps_hw.h @@ -0,0 +1,383 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xiicps_hw.h +* @addtogroup iicps_v3_7 +* @{ +* +* This header file contains the hardware definition for an IIC device. +* It includes register definitions and interface functions to read/write +* the registers. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype.
+* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
    +* +******************************************************************************/ +#ifndef XIICPS_HW_H /* prevent circular inclusions */ +#define XIICPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the IIC. + * @{ + */ +#define XIICPS_CR_OFFSET 0x00U /**< 32-bit Control */ +#define XIICPS_SR_OFFSET 0x04U /**< Status */ +#define XIICPS_ADDR_OFFSET 0x08U /**< IIC Address */ +#define XIICPS_DATA_OFFSET 0x0CU /**< IIC FIFO Data */ +#define XIICPS_ISR_OFFSET 0x10U /**< Interrupt Status */ +#define XIICPS_TRANS_SIZE_OFFSET 0x14U /**< Transfer Size */ +#define XIICPS_SLV_PAUSE_OFFSET 0x18U /**< Slave monitor pause */ +#define XIICPS_TIME_OUT_OFFSET 0x1CU /**< Time Out */ +#define XIICPS_IMR_OFFSET 0x20U /**< Interrupt Enabled Mask */ +#define XIICPS_IER_OFFSET 0x24U /**< Interrupt Enable */ +#define XIICPS_IDR_OFFSET 0x28U /**< Interrupt Disable */ +/* @} */ + +/** @name Control Register + * + * This register contains various control bits that + * affects the operation of the IIC controller. Read/Write. + * @{ + */ + +#define XIICPS_CR_DIV_A_MASK 0x0000C000U /**< Clock Divisor A */ +#define XIICPS_CR_DIV_A_SHIFT 14U /**< Clock Divisor A shift */ +#define XIICPS_DIV_A_MAX 4U /**< Maximum value of Divisor A */ +#define XIICPS_CR_DIV_B_MASK 0x00003F00U /**< Clock Divisor B */ +#define XIICPS_CR_DIV_B_SHIFT 8U /**< Clock Divisor B shift */ +#define XIICPS_CR_CLR_FIFO_MASK 0x00000040U /**< Clear FIFO, auto clears*/ +#define XIICPS_CR_SLVMON_MASK 0x00000020U /**< Slave monitor mode */ +#define XIICPS_CR_HOLD_MASK 0x00000010U /**< Hold bus 1=Hold scl, + 0=terminate transfer */ +#define XIICPS_CR_ACKEN_MASK 0x00000008U /**< Enable TX of ACK when + Master receiver*/ +#define XIICPS_CR_NEA_MASK 0x00000004U /**< Addressing Mode 1=7 bit, + 0=10 bit */ +#define XIICPS_CR_MS_MASK 0x00000002U /**< Master mode bit 1=Master, + 0=Slave */ +#define XIICPS_CR_RD_WR_MASK 0x00000001U /**< Read or Write Master + transfer 0=Transmitter, + 1=Receiver*/ +#define XIICPS_CR_RESET_VALUE 0U /**< Reset value of the Control + register */ +/* @} */ + +/** @name IIC Status Register + * + * This register is used to indicate status of the IIC controller. Read only + * @{ + */ +#define XIICPS_SR_BA_MASK 0x00000100U /**< Bus Active Mask */ +#define XIICPS_SR_RXOVF_MASK 0x00000080U /**< Receiver Overflow Mask */ +#define XIICPS_SR_TXDV_MASK 0x00000040U /**< Transmit Data Valid Mask */ +#define XIICPS_SR_RXDV_MASK 0x00000020U /**< Receiver Data Valid Mask */ +#define XIICPS_SR_RXRW_MASK 0x00000008U /**< Receive read/write Mask */ +/* @} */ + +/** @name IIC Address Register + * + * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0]. + * A write access to this register always initiates a transfer if the IIC is in + * master mode. Read/Write + * @{ + */ +#define XIICPS_ADDR_MASK 0x000003FF /**< IIC Address Mask */ +/* @} */ + +/** @name IIC Data Register + * + * When written to, the data register sets data to transmit. When read from, the + * data register reads the last received byte of data. Read/Write + * @{ + */ +#define XIICPS_DATA_MASK 0x000000FF /**< IIC Data Mask */ +/* @} */ + +/** @name IIC Interrupt Registers + * + * IIC Interrupt Status Register + * + * This register holds the interrupt status flags for the IIC controller. Some + * of the flags are level triggered + * - i.e. are set as long as the interrupt condition exists. Other flags are + * edge triggered, which means they are set one the interrupt condition occurs + * then remain set until they are cleared by software. + * The interrupts are cleared by writing a one to the interrupt bit position + * in the Interrupt Status Register. Read/Write. + * + * IIC Interrupt Enable Register + * + * This register is used to enable interrupt sources for the IIC controller. + * Writing a '1' to a bit in this register clears the corresponding bit in the + * IIC Interrupt Mask register. Write only. + * + * IIC Interrupt Disable Register + * + * This register is used to disable interrupt sources for the IIC controller. + * Writing a '1' to a bit in this register sets the corresponding bit in the + * IIC Interrupt Mask register. Write only. + * + * IIC Interrupt Mask Register + * + * This register shows the enabled/disabled status of each IIC controller + * interrupt source. A bit set to 1 will ignore the corresponding interrupt in + * the status register. A bit set to 0 means the interrupt is enabled. + * All mask bits are set and all interrupts are disabled after reset. Read only. + * + * All four registers have the same bit definitions. They are only defined once + * for each of the Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Interrupt Status Register + * @{ + */ + +#define XIICPS_IXR_ARB_LOST_MASK 0x00000200U /**< Arbitration Lost Interrupt + mask */ +#define XIICPS_IXR_RX_UNF_MASK 0x00000080U /**< FIFO Recieve Underflow + Interrupt mask */ +#define XIICPS_IXR_TX_OVR_MASK 0x00000040U /**< Transmit Overflow + Interrupt mask */ +#define XIICPS_IXR_RX_OVR_MASK 0x00000020U /**< Receive Overflow Interrupt + mask */ +#define XIICPS_IXR_SLV_RDY_MASK 0x00000010U /**< Monitored Slave Ready + Interrupt mask */ +#define XIICPS_IXR_TO_MASK 0x00000008U /**< Transfer Time Out + Interrupt mask */ +#define XIICPS_IXR_NACK_MASK 0x00000004U /**< NACK Interrupt mask */ +#define XIICPS_IXR_DATA_MASK 0x00000002U /**< Data Interrupt mask */ +#define XIICPS_IXR_COMP_MASK 0x00000001U /**< Transfer Complete + Interrupt mask */ +#define XIICPS_IXR_DEFAULT_MASK 0x000002FFU /**< Default ISR Mask */ +#define XIICPS_IXR_ALL_INTR_MASK 0x000002FFU /**< All ISR Mask */ +/* @} */ + + +/** @name IIC Transfer Size Register +* +* The register's meaning varies according to the operating mode as follows: +* - Master transmitter mode: number of data bytes still not transmitted minus +* one +* - Master receiver mode: number of data bytes that are still expected to be +* received +* - Slave transmitter mode: number of bytes remaining in the FIFO after the +* master terminates the transfer +* - Slave receiver mode: number of valid data bytes in the FIFO +* +* This register is cleared if CLR_FIFO bit in the control register is set. +* Read/Write +* @{ +*/ +#define XIICPS_TRANS_SIZE_MASK 0x0000003F /**< IIC Transfer Size Mask */ +#define XIICPS_FIFO_DEPTH 16 /**< Number of bytes in the FIFO */ +#define XIICPS_DATA_INTR_DEPTH 14 /**< Number of bytes at DATA intr */ +/* @} */ + + +/** @name IIC Slave Monitor Pause Register +* +* This register is associated with the slave monitor mode of the I2C interface. +* It is meaningful only when the module is in master mode and bit SLVMON in the +* control register is set. +* +* This register defines the pause interval between consecutive attempts to +* address the slave once a write to an I2C address register is done by the +* host. It represents the number of sclk cycles minus one between two attempts. +* +* The reset value of the register is 0, which results in the master repeatedly +* trying to access the slave immediately after unsuccessful attempt. +* Read/Write +* @{ +*/ +#define XIICPS_SLV_PAUSE_MASK 0x0000000F /**< Slave monitor pause mask */ +/* @} */ + + +/** @name IIC Time Out Register +* +* The value of time out register represents the time out interval in number of +* sclk cycles minus one. +* +* When the accessed slave holds the sclk line low for longer than the time out +* period, thus prohibiting the I2C interface in master mode to complete the +* current transfer, an interrupt is generated and TO interrupt flag is set. +* +* The reset value of the register is 0x1f. +* Read/Write +* @{ + */ +#define XIICPS_TIME_OUT_MASK 0x000000FFU /**< IIC Time Out mask */ +#define XIICPS_TO_RESET_VALUE 0x000000FFU /**< IIC Time Out reset value */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XIicPs_In32 Xil_In32 +#define XIicPs_Out32 Xil_Out32 + +/****************************************************************************/ +/** +* Read an IIC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to select the specific register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XIicPs_ReadReg(BaseAddress, RegOffset) \ + XIicPs_In32((BaseAddress) + (u32)(RegOffset)) + +/***************************************************************************/ +/** +* Write an IIC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to select the specific register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue) +* +******************************************************************************/ +#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) + +/***************************************************************************/ +/** +* Read the interrupt enable register. +* +* @param BaseAddress contains the base address of the device. +* +* @return Current bit mask that represents currently enabled interrupts. +* +* @note C-Style signature: +* u32 XIicPs_ReadIER(u32 BaseAddress) +* +******************************************************************************/ +#define XIicPs_ReadIER(BaseAddress) \ + XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET) + +/***************************************************************************/ +/** +* Write to the interrupt enable register. +* +* @param BaseAddress contains the base address of the device. +* +* @param IntrMask is the interrupts to be enabled. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask) +* +******************************************************************************/ +#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask)) + +/***************************************************************************/ +/** +* Disable all interrupts. +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_DisableAllInterrupts(u32 BaseAddress) +* +******************************************************************************/ +#define XIicPs_DisableAllInterrupts(BaseAddress) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ + XIICPS_IXR_ALL_INTR_MASK) + +/***************************************************************************/ +/** +* Disable selected interrupts. +* +* @param BaseAddress contains the base address of the device. +* +* @param IntrMask is the interrupts to be disabled. +* +* @return None. +* +* @note C-Style signature: +* void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask) +* +******************************************************************************/ +#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \ + XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \ + (IntrMask)) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the I2c interface + */ +void XIicPs_ResetHw(u32 BaseAddress); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_assert.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_assert.h new file mode 100644 index 0000000..add4124 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_assert.h @@ -0,0 +1,195 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_assert.h +* +* @addtogroup common_assert_apis Assert APIs and Macros +* +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+*
    +* +******************************************************************************/ + +#ifndef XIL_ASSERT_H /* prevent circular inclusions */ +#define XIL_ASSERT_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + + +/************************** Constant Definitions *****************************/ + +#define XIL_ASSERT_NONE 0U +#define XIL_ASSERT_OCCURRED 1U +#define XNULL NULL + +extern u32 Xil_AssertStatus; +extern s32 Xil_AssertWait; +extern void Xil_Assert(const char8 *File, s32 Line); +void XNullHandler(void *NullParameter); + +/** + * This data type defines a callback to be invoked when an + * assert occurs. The callback is invoked only when asserts are enabled + */ +typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifndef NDEBUG + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for void functions. This in +* conjunction with the Xil_AssertWait boolean can be used to +* accomodate tests so that asserts which fail allow execution to +* continue. +* +* @param Expression: expression to be evaluated. If it evaluates to +* false, the assert occurs. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief This assert macro is to be used for functions that do return a +* value. This in conjunction with the Xil_AssertWait boolean can be +* used to accomodate tests so that asserts which fail allow execution +* to continue. +* +* @param Expression: expression to be evaluated. If it evaluates to false, +* the assert occurs. +* +* @return Returns 0 unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoid(Expression) \ +{ \ + if (Expression) { \ + Xil_AssertStatus = XIL_ASSERT_NONE; \ + } else { \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ + } \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for void functions. +* Use for instances where an assert should always occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertVoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return; \ +} + +/*****************************************************************************/ +/** +* @brief Always assert. This assert macro is to be used for functions that +* do return a value. Use for instances where an assert should always +* occur. +* +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. +* +******************************************************************************/ +#define Xil_AssertNonvoidAlways() \ +{ \ + Xil_Assert(__FILE__, __LINE__); \ + Xil_AssertStatus = XIL_ASSERT_OCCURRED; \ + return 0; \ +} + + +#else + +#define Xil_AssertVoid(Expression) +#define Xil_AssertVoidAlways() +#define Xil_AssertNonvoid(Expression) +#define Xil_AssertNonvoidAlways() + +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_AssertSetCallback(Xil_AssertCallback Routine); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_assert_apis". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache.h new file mode 100644 index 0000000..b6614d5 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache.h @@ -0,0 +1,121 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache.h +* +* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+*
    +* +******************************************************************************/ +#ifndef XIL_CACHE_H +#define XIL_CACHE_H + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __GNUC__ + +#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)); + +#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)); + +#elif defined (__ICCARM__) + +#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)); + +#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)); + +#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \ + XREG_CP15_INVAL_DC_LINE_SW :: "r" (param)); + +#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)); + +#endif + +void Xil_DCacheEnable(void); +void Xil_DCacheDisable(void); +void Xil_DCacheInvalidate(void); +void Xil_DCacheInvalidateRange(INTPTR adr, u32 len); +void Xil_DCacheFlush(void); +void Xil_DCacheFlushRange(INTPTR adr, u32 len); + +void Xil_ICacheEnable(void); +void Xil_ICacheDisable(void); +void Xil_ICacheInvalidate(void); +void Xil_ICacheInvalidateRange(INTPTR adr, u32 len); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_cache_apis". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_l.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_l.h new file mode 100644 index 0000000..fa92c6b --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_l.h @@ -0,0 +1,100 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_l.h +* +* Contains L1 and L2 specific functions for the ARM cache functionality +* used by xcache.c. This functionality is being made available here for +* more sophisticated users. +* +* @addtogroup a9_cache_apis +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+*
    +* +******************************************************************************/ +#ifndef XIL_CACHE_MACH_H +#define XIL_CACHE_MACH_H + +#include "xil_types.h" +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Function Prototypes ******************************/ + +void Xil_DCacheInvalidateLine(u32 adr); +void Xil_DCacheFlushLine(u32 adr); +void Xil_DCacheStoreLine(u32 adr); +void Xil_ICacheInvalidateLine(u32 adr); + +void Xil_L1DCacheEnable(void); +void Xil_L1DCacheDisable(void); +void Xil_L1DCacheInvalidate(void); +void Xil_L1DCacheInvalidateLine(u32 adr); +void Xil_L1DCacheInvalidateRange(u32 adr, u32 len); +void Xil_L1DCacheFlush(void); +void Xil_L1DCacheFlushLine(u32 adr); +void Xil_L1DCacheFlushRange(u32 adr, u32 len); +void Xil_L1DCacheStoreLine(u32 adr); + +void Xil_L1ICacheEnable(void); +void Xil_L1ICacheDisable(void); +void Xil_L1ICacheInvalidate(void); +void Xil_L1ICacheInvalidateLine(u32 adr); +void Xil_L1ICacheInvalidateRange(u32 adr, u32 len); + +void Xil_L2CacheEnable(void); +void Xil_L2CacheDisable(void); +void Xil_L2CacheInvalidate(void); +void Xil_L2CacheInvalidateLine(u32 adr); +void Xil_L2CacheInvalidateRange(u32 adr, u32 len); +void Xil_L2CacheFlush(void); +void Xil_L2CacheFlushLine(u32 adr); +void Xil_L2CacheFlushRange(u32 adr, u32 len); +void Xil_L2CacheStoreLine(u32 adr); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_cache_apis". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h new file mode 100644 index 0000000..6e8cfa7 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h @@ -0,0 +1,93 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_cache_vxworks.h +* +* Contains the cache related functions for VxWorks that is wrapped by +* xil_cache. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef XIL_CACHE_VXWORKS_H +#define XIL_CACHE_VXWORKS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "vxWorks.h" +#include "vxLib.h" +#include "sysLibExtra.h" +#include "cacheLib.h" + +#if (CPU_FAMILY==PPC) + +#define Xil_DCacheEnable() cacheEnable(DATA_CACHE) + +#define Xil_DCacheDisable() cacheDisable(DATA_CACHE) + +#define Xil_DCacheInvalidateRange(Addr, Len) \ + cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_DCacheFlushRange(Addr, Len) \ + cacheFlush(DATA_CACHE, (void *)(Addr), (Len)) + +#define Xil_ICacheEnable() cacheEnable(INSTRUCTION_CACHE) + +#define Xil_ICacheDisable() cacheDisable(INSTRUCTION_CACHE) + +#define Xil_ICacheInvalidateRange(Addr, Len) \ + cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len)) + + +#else +#error "Unknown processor / architecture. Must be PPC for VxWorks." +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_errata.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_errata.h new file mode 100644 index 0000000..490aebe --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_errata.h @@ -0,0 +1,123 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_errata.h +* +* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support +* @{ +* Various ARM errata are handled in the standalone BSP. The implementation for +* errata handling follows ARM guidelines and is based on the open source Linux +* support for these errata. +* +* @note +* The errata handling is enabled by default. To disable handling of all the +* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To +* disable errata on a per-erratum basis, un-define relevant macros in +* xil_errata.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+* 6.6   mus  12/07/17 Removed errata 753970, It fixes CR#989132.
+*
    +* +******************************************************************************/ +#ifndef XIL_ERRATA_H +#define XIL_ERRATA_H + +/** + * @name errata_definitions + * + * The errata conditions handled in the standalone BSP are listed below + * @{ + */ + +#define ENABLE_ARM_ERRATA 1 + +#ifdef ENABLE_ARM_ERRATA + +/** + * Errata No: 742230 + * Description: DMB operation may be faulty + */ +#define CONFIG_ARM_ERRATA_742230 1 + +/** + * Errata No: 743622 + * Description: Faulty hazard checking in the Store Buffer may lead + * to data corruption. + */ +#define CONFIG_ARM_ERRATA_743622 1 + +/** + * Errata No: 775420 + * Description: A data cache maintenance operation which aborts, + * might lead to deadlock + */ +#define CONFIG_ARM_ERRATA_775420 1 + +/** + * Errata No: 794073 + * Description: Speculative instruction fetches with MMU disabled + * might not comply with architectural requirements + */ +#define CONFIG_ARM_ERRATA_794073 1 + + +/** PL310 L2 Cache Errata */ + +/** + * Errata No: 588369 + * Description: Clean & Invalidate maintenance operations do not + * invalidate clean lines + */ +#define CONFIG_PL310_ERRATA_588369 1 + +/** + * Errata No: 727915 + * Description: Background Clean and Invalidate by Way operation + * can cause data corruption + */ +#define CONFIG_PL310_ERRATA_727915 1 + +/*@}*/ +#endif /* ENABLE_ARM_ERRATA */ + +#endif /* XIL_ERRATA_H */ +/** +* @} End of "addtogroup a9_errata". +*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_exception.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_exception.h new file mode 100644 index 0000000..8330387 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_exception.h @@ -0,0 +1,260 @@ +/****************************************************************************** +* +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_exception.h +* +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. +* For exception related functions that can be used across all Xilinx supported +* processors, please use xil_exception.h. +* +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7   mna      26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7   asa      18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+*
    +* +******************************************************************************/ + +#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */ +#define XIL_EXCEPTION_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xpseudo_asm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions ****************************/ + +#define XIL_EXCEPTION_FIQ XREG_CPSR_FIQ_ENABLE +#define XIL_EXCEPTION_IRQ XREG_CPSR_IRQ_ENABLE +#define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) + +#define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else +#define XIL_EXCEPTION_ID_RESET 0U +#define XIL_EXCEPTION_ID_UNDEFINED_INT 1U +#define XIL_EXCEPTION_ID_SWI_INT 2U +#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT 3U +#define XIL_EXCEPTION_ID_DATA_ABORT_INT 4U +#define XIL_EXCEPTION_ID_IRQ_INT 5U +#define XIL_EXCEPTION_ID_FIQ_INT 6U +#define XIL_EXCEPTION_ID_LAST 6U +#endif + +/* + * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. + */ +#define XIL_EXCEPTION_ID_INT XIL_EXCEPTION_ID_IRQ_INT + +/**************************** Type Definitions ******************************/ + +/** + * This typedef is the exception handler function. + */ +typedef void (*Xil_ExceptionHandler)(void *data); +typedef void (*Xil_InterruptHandler)(void *data); + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* @brief Enable Exceptions. +* +* @param Mask: Value for enabling the exceptions. +* +* @return None. +* +* @note If bit is 0, exception is enabled. +* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* +******************************************************************************/ +#if defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionEnableMask(Mask) \ + mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionEnableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ + } +#endif +/****************************************************************************/ +/** +* @brief Enable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionEnable() \ + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) + +/****************************************************************************/ +/** +* @brief Disable Exceptions. +* +* @param Mask: Value for disabling the exceptions. +* +* @return None. +* +* @note If bit is 1, exception is disabled. +* C-Style signature: Xil_ExceptionDisableMask(Mask) +* +******************************************************************************/ +#if defined (__GNUC__) || defined (__ICCARM__) +#define Xil_ExceptionDisableMask(Mask) \ + mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) +#else +#define Xil_ExceptionDisableMask(Mask) \ + { \ + register u32 Reg __asm("cpsr"); \ + mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ + } +#endif +/****************************************************************************/ +/** +* Disable the IRQ exception. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define Xil_ExceptionDisable() \ + Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) + +#if !defined (__aarch64__) && !defined (ARMA53_32) +/****************************************************************************/ +/** +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is supposed to be used from interrupt handlers. In the +* interrupt handler the interrupts are disabled by default (I and F +* are 1). To allow nesting of interrupts, this macro should be +* used. It clears the I and F bits by changing the ARM mode to +* system mode. Once these bits are cleared and provided the +* preemption of interrupt conditions are met in the GIC, nesting of +* interrupts will start happening. +* Caution: This macro must be used with caution. Before calling this +* macro, the user must ensure that the source of the current IRQ +* is appropriately cleared. Otherwise, as soon as we clear the I and +* F bits, there can be an infinite loop of interrupts with an +* eventual crash (all the stack space getting consumed). +******************************************************************************/ +#define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("mrs lr, spsr"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); + +/****************************************************************************/ +/** +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. +* +* @return None. +* +* @note This macro is meant to be called in the interrupt service routines. +* This macro cannot be used independently. It can only be used when +* nesting of interrupts have been enabled by using the macro +* Xil_EnableNestedInterrupts(). In a typical flow, the user first +* calls the Xil_EnableNestedInterrupts in the ISR at the appropriate +* point. The user then must call this macro before exiting the interrupt +* service routine. This macro puts the ARM back in IRQ/FIQ mode and +* hence sets back the I and F bits. +******************************************************************************/ +#define Xil_DisableNestedInterrupts() \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ + +#endif +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +extern void Xil_ExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler Handler, + void *Data); + +extern void Xil_ExceptionRemoveHandler(u32 Exception_id); +extern void Xil_GetExceptionRegisterHandler(u32 Exception_id, + Xil_ExceptionHandler *Handler, void **Data); + +extern void Xil_ExceptionInit(void); +#if defined (__aarch64__) +void Xil_SyncAbortHandler(void *CallBackRef); +void Xil_SErrorAbortHandler(void *CallBackRef); +#else +extern void Xil_DataAbortHandler(void *CallBackRef); +extern void Xil_PrefetchAbortHandler(void *CallBackRef); +extern void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_hal.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_hal.h new file mode 100644 index 0000000..d4434d0 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_hal.h @@ -0,0 +1,61 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_hal.h +* +* Contains all the HAL header files. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef XIL_HAL_H +#define XIL_HAL_H + +#include "xil_cache.h" +#include "xil_io.h" +#include "xil_assert.h" +#include "xil_exception.h" +#include "xil_types.h" + +#endif diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_io.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_io.h new file mode 100644 index 0000000..9c5aa43 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_io.h @@ -0,0 +1,345 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* @addtogroup common_io_interfacing_apis Register IO interfacing APIs +* +* The xil_io.h file contains the interface for the general I/O component, which +* encapsulates the Input/Output functions for the processors that do not +* require any special I/O handling. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+*
    +******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_printf.h" + +#if defined (__MICROBLAZE__) +#include "mb_interface.h" +#else +#include "xpseudo_asm.h" +#endif + +/************************** Function Prototypes ******************************/ +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); +#ifdef ENABLE_SAFETY +extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ +#if defined __GNUC__ +#if defined (__MICROBLAZE__) +# define INST_SYNC mbar(0) +# define DATA_SYNC mbar(1) +# else +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +# endif +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +# define INST_SYNC +# define DATA_SYNC +#endif + +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) +#define INLINE inline +#else +#define INLINE __inline +#endif + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading +* from the specified address and returning the 8 bit Value read from +* that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 8 bit Value read from the specified input address. + +* +******************************************************************************/ +static INLINE u8 Xil_In8(UINTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading from +* the specified address and returning the 16 bit Value read from that +* address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 16 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u16 Xil_In16(UINTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by +* reading from the specified address and returning the 32 bit Value +* read from that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 32 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading the +* 64 bit Value read from that address. +* +* +* @param Addr: contains the address to perform the input operation +* +* @return The 64 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u64 Xil_In64(UINTPTR Addr) +{ + return *(volatile u64 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for an memory location by +* writing the 8 bit Value to the the specified address. +* +* @param Addr: contains the address to perform the output operation +* @param Value: contains the 8 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out8(UINTPTR Addr, u8 Value) +{ + volatile u8 *LocalAddr = (volatile u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 16 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out16(UINTPTR Addr, u16 Value) +{ + volatile u16 *LocalAddr = (volatile u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 32 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the 32 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out32(UINTPTR Addr, u32 Value) +{ +#ifndef ENABLE_SAFETY + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +#else + XStl_RegUpdate(Addr, Value); +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 64 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains 64 bit Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out64(UINTPTR Addr, u64 Value) +{ + volatile u64 *LocalAddr = (volatile u64 *)Addr; + *LocalAddr = Value; +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +# else +# define Xil_In16BE Xil_In16 +# define Xil_In32BE Xil_In32 +# define Xil_Out16BE Xil_Out16 +# define Xil_Out32BE Xil_Out32 +# define Xil_Htons(Data) (Data) +# define Xil_Htonl(Data) (Data) +# define Xil_Ntohs(Data) (Data) +# define Xil_Ntohl(Data) (Data) +#endif +#else +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +#endif + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#else +static INLINE u16 Xil_In16LE(UINTPTR Addr) +#endif +#else +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#endif +{ + u16 value = Xil_In16(Addr); + return Xil_EndianSwap16(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#else +static INLINE u32 Xil_In32LE(UINTPTR Addr) +#endif +#else +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#endif +{ + u32 value = Xil_In32(Addr); + return Xil_EndianSwap32(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#else +static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) +#endif +#else +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#endif +{ + Value = Xil_EndianSwap16(Value); + Xil_Out16(Addr, Value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#else +static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) +#endif +#else +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#endif +{ + Value = Xil_EndianSwap32(Value); + Xil_Out32(Addr, Value); +} + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_io_interfacing_apis". +*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_macroback.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_macroback.h new file mode 100644 index 0000000..ebafde8 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_macroback.h @@ -0,0 +1,1052 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*********************************************************************/ +/** + * @file xil_macroback.h + * + * This header file is meant to bring back the removed _m macros. + * This header file must be included last. + * The following macros are not defined here due to the driver change: + * XGpio_mSetDataDirection + * XGpio_mGetDataReg + * XGpio_mSetDataReg + * XIIC_RESET + * XIIC_CLEAR_STATS + * XSpi_mReset + * XSysAce_mSetCfgAddr + * XSysAce_mIsCfgDone + * XTft_mSetPixel + * XTft_mGetPixel + * XWdtTb_mEnableWdt + * XWdtTb_mDisbleWdt + * XWdtTb_mRestartWdt + * XWdtTb_mGetTimebaseReg + * XWdtTb_mHasReset + * + * Please refer the corresonding driver document for replacement. + * + *********************************************************************/ + +#ifndef XIL_MACROBACK_H +#define XIL_MACROBACK_H + +/*********************************************************************/ +/** + * Macros for Driver XCan + * + *********************************************************************/ +#ifndef XCan_mReadReg +#define XCan_mReadReg XCan_ReadReg +#endif + +#ifndef XCan_mWriteReg +#define XCan_mWriteReg XCan_WriteReg +#endif + +#ifndef XCan_mIsTxDone +#define XCan_mIsTxDone XCan_IsTxDone +#endif + +#ifndef XCan_mIsTxFifoFull +#define XCan_mIsTxFifoFull XCan_IsTxFifoFull +#endif + +#ifndef XCan_mIsHighPriorityBufFull +#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull +#endif + +#ifndef XCan_mIsRxEmpty +#define XCan_mIsRxEmpty XCan_IsRxEmpty +#endif + +#ifndef XCan_mIsAcceptFilterBusy +#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy +#endif + +#ifndef XCan_mCreateIdValue +#define XCan_mCreateIdValue XCan_CreateIdValue +#endif + +#ifndef XCan_mCreateDlcValue +#define XCan_mCreateDlcValue XCan_CreateDlcValue +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDmaCentral + * + *********************************************************************/ +#ifndef XDmaCentral_mWriteReg +#define XDmaCentral_mWriteReg XDmaCentral_WriteReg +#endif + +#ifndef XDmaCentral_mReadReg +#define XDmaCentral_mReadReg XDmaCentral_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsAdc + * + *********************************************************************/ +#ifndef XDsAdc_mWriteReg +#define XDsAdc_mWriteReg XDsAdc_WriteReg +#endif + +#ifndef XDsAdc_mReadReg +#define XDsAdc_mReadReg XDsAdc_ReadReg +#endif + +#ifndef XDsAdc_mIsEmpty +#define XDsAdc_mIsEmpty XDsAdc_IsEmpty +#endif + +#ifndef XDsAdc_mSetFstmReg +#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg +#endif + +#ifndef XDsAdc_mGetFstmReg +#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg +#endif + +#ifndef XDsAdc_mEnableConversion +#define XDsAdc_mEnableConversion XDsAdc_EnableConversion +#endif + +#ifndef XDsAdc_mDisableConversion +#define XDsAdc_mDisableConversion XDsAdc_DisableConversion +#endif + +#ifndef XDsAdc_mGetFifoOccyReg +#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XDsDac + * + *********************************************************************/ +#ifndef XDsDac_mWriteReg +#define XDsDac_mWriteReg XDsDac_WriteReg +#endif + +#ifndef XDsDac_mReadReg +#define XDsDac_mReadReg XDsDac_ReadReg +#endif + +#ifndef XDsDac_mIsEmpty +#define XDsDac_mIsEmpty XDsDac_IsEmpty +#endif + +#ifndef XDsDac_mFifoIsFull +#define XDsDac_mFifoIsFull XDsDac_FifoIsFull +#endif + +#ifndef XDsDac_mGetVacancy +#define XDsDac_mGetVacancy XDsDac_GetVacancy +#endif + +/*********************************************************************/ +/** + * Macros for Driver XEmacLite + * + *********************************************************************/ +#ifndef XEmacLite_mReadReg +#define XEmacLite_mReadReg XEmacLite_ReadReg +#endif + +#ifndef XEmacLite_mWriteReg +#define XEmacLite_mWriteReg XEmacLite_WriteReg +#endif + +#ifndef XEmacLite_mGetTxStatus +#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus +#endif + +#ifndef XEmacLite_mSetTxStatus +#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus +#endif + +#ifndef XEmacLite_mGetRxStatus +#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus +#endif + +#ifndef XEmacLite_mSetRxStatus +#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus +#endif + +#ifndef XEmacLite_mIsTxDone +#define XEmacLite_mIsTxDone XEmacLite_IsTxDone +#endif + +#ifndef XEmacLite_mIsRxEmpty +#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty +#endif + +#ifndef XEmacLite_mNextTransmitAddr +#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr +#endif + +#ifndef XEmacLite_mNextReceiveAddr +#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr +#endif + +#ifndef XEmacLite_mIsMdioConfigured +#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured +#endif + +#ifndef XEmacLite_mIsLoopbackConfigured +#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured +#endif + +#ifndef XEmacLite_mGetReceiveDataLength +#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength +#endif + +#ifndef XEmacLite_mGetTxActive +#define XEmacLite_mGetTxActive XEmacLite_GetTxActive +#endif + +#ifndef XEmacLite_mSetTxActive +#define XEmacLite_mSetTxActive XEmacLite_SetTxActive +#endif + +/*********************************************************************/ +/** + * Macros for Driver XGpio + * + *********************************************************************/ +#ifndef XGpio_mWriteReg +#define XGpio_mWriteReg XGpio_WriteReg +#endif + +#ifndef XGpio_mReadReg +#define XGpio_mReadReg XGpio_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XHwIcap + * + *********************************************************************/ +#ifndef XHwIcap_mFifoWrite +#define XHwIcap_mFifoWrite XHwIcap_FifoWrite +#endif + +#ifndef XHwIcap_mFifoRead +#define XHwIcap_mFifoRead XHwIcap_FifoRead +#endif + +#ifndef XHwIcap_mSetSizeReg +#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg +#endif + +#ifndef XHwIcap_mGetControlReg +#define XHwIcap_mGetControlReg XHwIcap_GetControlReg +#endif + +#ifndef XHwIcap_mStartConfig +#define XHwIcap_mStartConfig XHwIcap_StartConfig +#endif + +#ifndef XHwIcap_mStartReadBack +#define XHwIcap_mStartReadBack XHwIcap_StartReadBack +#endif + +#ifndef XHwIcap_mGetStatusReg +#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg +#endif + +#ifndef XHwIcap_mIsTransferDone +#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone +#endif + +#ifndef XHwIcap_mIsDeviceBusy +#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy +#endif + +#ifndef XHwIcap_mIntrGlobalEnable +#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable +#endif + +#ifndef XHwIcap_mIntrGlobalDisable +#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable +#endif + +#ifndef XHwIcap_mIntrGetStatus +#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus +#endif + +#ifndef XHwIcap_mIntrDisable +#define XHwIcap_mIntrDisable XHwIcap_IntrDisable +#endif + +#ifndef XHwIcap_mIntrEnable +#define XHwIcap_mIntrEnable XHwIcap_IntrEnable +#endif + +#ifndef XHwIcap_mIntrGetEnabled +#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled +#endif + +#ifndef XHwIcap_mIntrClear +#define XHwIcap_mIntrClear XHwIcap_IntrClear +#endif + +#ifndef XHwIcap_mGetWrFifoVacancy +#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy +#endif + +#ifndef XHwIcap_mGetRdFifoOccupancy +#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy +#endif + +#ifndef XHwIcap_mSliceX2Col +#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col +#endif + +#ifndef XHwIcap_mSliceY2Row +#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row +#endif + +#ifndef XHwIcap_mSliceXY2Slice +#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice +#endif + +#ifndef XHwIcap_mReadReg +#define XHwIcap_mReadReg XHwIcap_ReadReg +#endif + +#ifndef XHwIcap_mWriteReg +#define XHwIcap_mWriteReg XHwIcap_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIic + * + *********************************************************************/ +#ifndef XIic_mReadReg +#define XIic_mReadReg XIic_ReadReg +#endif + +#ifndef XIic_mWriteReg +#define XIic_mWriteReg XIic_WriteReg +#endif + +#ifndef XIic_mEnterCriticalRegion +#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable +#endif + +#ifndef XIic_mExitCriticalRegion +#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_GINTR_DISABLE +#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable +#endif + +#ifndef XIIC_GINTR_ENABLE +#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable +#endif + +#ifndef XIIC_IS_GINTR_ENABLED +#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled +#endif + +#ifndef XIIC_WRITE_IISR +#define XIIC_WRITE_IISR XIic_WriteIisr +#endif + +#ifndef XIIC_READ_IISR +#define XIIC_READ_IISR XIic_ReadIisr +#endif + +#ifndef XIIC_WRITE_IIER +#define XIIC_WRITE_IIER XIic_WriteIier +#endif + +#ifndef XIic_mClearIisr +#define XIic_mClearIisr XIic_ClearIisr +#endif + +#ifndef XIic_mSend7BitAddress +#define XIic_mSend7BitAddress XIic_Send7BitAddress +#endif + +#ifndef XIic_mDynSend7BitAddress +#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress +#endif + +#ifndef XIic_mDynSendStartStopAddress +#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress +#endif + +#ifndef XIic_mDynSendStop +#define XIic_mDynSendStop XIic_DynSendStop +#endif + +#ifndef XIic_mSend10BitAddrByte1 +#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1 +#endif + +#ifndef XIic_mSend10BitAddrByte2 +#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2 +#endif + +#ifndef XIic_mSend7BitAddr +#define XIic_mSend7BitAddr XIic_Send7BitAddr +#endif + +#ifndef XIic_mDisableIntr +#define XIic_mDisableIntr XIic_DisableIntr +#endif + +#ifndef XIic_mEnableIntr +#define XIic_mEnableIntr XIic_EnableIntr +#endif + +#ifndef XIic_mClearIntr +#define XIic_mClearIntr XIic_ClearIntr +#endif + +#ifndef XIic_mClearEnableIntr +#define XIic_mClearEnableIntr XIic_ClearEnableIntr +#endif + +#ifndef XIic_mFlushRxFifo +#define XIic_mFlushRxFifo XIic_FlushRxFifo +#endif + +#ifndef XIic_mFlushTxFifo +#define XIic_mFlushTxFifo XIic_FlushTxFifo +#endif + +#ifndef XIic_mReadRecvByte +#define XIic_mReadRecvByte XIic_ReadRecvByte +#endif + +#ifndef XIic_mWriteSendByte +#define XIic_mWriteSendByte XIic_WriteSendByte +#endif + +#ifndef XIic_mSetControlRegister +#define XIic_mSetControlRegister XIic_SetControlRegister +#endif + +/*********************************************************************/ +/** + * Macros for Driver XIntc + * + *********************************************************************/ +#ifndef XIntc_mMasterEnable +#define XIntc_mMasterEnable XIntc_MasterEnable +#endif + +#ifndef XIntc_mMasterDisable +#define XIntc_mMasterDisable XIntc_MasterDisable +#endif + +#ifndef XIntc_mEnableIntr +#define XIntc_mEnableIntr XIntc_EnableIntr +#endif + +#ifndef XIntc_mDisableIntr +#define XIntc_mDisableIntr XIntc_DisableIntr +#endif + +#ifndef XIntc_mAckIntr +#define XIntc_mAckIntr XIntc_AckIntr +#endif + +#ifndef XIntc_mGetIntrStatus +#define XIntc_mGetIntrStatus XIntc_GetIntrStatus +#endif + +/*********************************************************************/ +/** + * Macros for Driver XLlDma + * + *********************************************************************/ +#ifndef XLlDma_mBdRead +#define XLlDma_mBdRead XLlDma_BdRead +#endif + +#ifndef XLlDma_mBdWrite +#define XLlDma_mBdWrite XLlDma_BdWrite +#endif + +#ifndef XLlDma_mWriteReg +#define XLlDma_mWriteReg XLlDma_WriteReg +#endif + +#ifndef XLlDma_mReadReg +#define XLlDma_mReadReg XLlDma_ReadReg +#endif + +#ifndef XLlDma_mBdClear +#define XLlDma_mBdClear XLlDma_BdClear +#endif + +#ifndef XLlDma_mBdSetStsCtrl +#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl +#endif + +#ifndef XLlDma_mBdGetStsCtrl +#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl +#endif + +#ifndef XLlDma_mBdSetLength +#define XLlDma_mBdSetLength XLlDma_BdSetLength +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mBdSetId +#define XLlDma_mBdSetId XLlDma_BdSetId +#endif + +#ifndef XLlDma_mBdGetId +#define XLlDma_mBdGetId XLlDma_BdGetId +#endif + +#ifndef XLlDma_mBdSetBufAddr +#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr +#endif + +#ifndef XLlDma_mBdGetBufAddr +#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr +#endif + +#ifndef XLlDma_mBdGetLength +#define XLlDma_mBdGetLength XLlDma_BdGetLength +#endif + +#ifndef XLlDma_mGetTxRing +#define XLlDma_mGetTxRing XLlDma_GetTxRing +#endif + +#ifndef XLlDma_mGetRxRing +#define XLlDma_mGetRxRing XLlDma_GetRxRing +#endif + +#ifndef XLlDma_mGetCr +#define XLlDma_mGetCr XLlDma_GetCr +#endif + +#ifndef XLlDma_mSetCr +#define XLlDma_mSetCr XLlDma_SetCr +#endif + +#ifndef XLlDma_mBdRingCntCalc +#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc +#endif + +#ifndef XLlDma_mBdRingMemCalc +#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc +#endif + +#ifndef XLlDma_mBdRingGetCnt +#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt +#endif + +#ifndef XLlDma_mBdRingGetFreeCnt +#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt +#endif + +#ifndef XLlDma_mBdRingSnapShotCurrBd +#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd +#endif + +#ifndef XLlDma_mBdRingNext +#define XLlDma_mBdRingNext XLlDma_BdRingNext +#endif + +#ifndef XLlDma_mBdRingPrev +#define XLlDma_mBdRingPrev XLlDma_BdRingPrev +#endif + +#ifndef XLlDma_mBdRingGetSr +#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr +#endif + +#ifndef XLlDma_mBdRingSetSr +#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr +#endif + +#ifndef XLlDma_mBdRingGetCr +#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr +#endif + +#ifndef XLlDma_mBdRingSetCr +#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr +#endif + +#ifndef XLlDma_mBdRingBusy +#define XLlDma_mBdRingBusy XLlDma_BdRingBusy +#endif + +#ifndef XLlDma_mBdRingIntEnable +#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable +#endif + +#ifndef XLlDma_mBdRingIntDisable +#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable +#endif + +#ifndef XLlDma_mBdRingIntGetEnabled +#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled +#endif + +#ifndef XLlDma_mBdRingGetIrq +#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq +#endif + +#ifndef XLlDma_mBdRingAckIrq +#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMbox + * + *********************************************************************/ +#ifndef XMbox_mWriteReg +#define XMbox_mWriteReg XMbox_WriteReg +#endif + +#ifndef XMbox_mReadReg +#define XMbox_mReadReg XMbox_ReadReg +#endif + +#ifndef XMbox_mWriteMBox +#define XMbox_mWriteMBox XMbox_WriteMBox +#endif + +#ifndef XMbox_mReadMBox +#define XMbox_mReadMBox XMbox_ReadMBox +#endif + +#ifndef XMbox_mFSLReadMBox +#define XMbox_mFSLReadMBox XMbox_FSLReadMBox +#endif + +#ifndef XMbox_mFSLWriteMBox +#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox +#endif + +#ifndef XMbox_mFSLIsEmpty +#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty +#endif + +#ifndef XMbox_mFSLIsFull +#define XMbox_mFSLIsFull XMbox_FSLIsFull +#endif + +#ifndef XMbox_mIsEmpty +#define XMbox_mIsEmpty XMbox_IsEmptyHw +#endif + +#ifndef XMbox_mIsFull +#define XMbox_mIsFull XMbox_IsFullHw +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMpmc + * + *********************************************************************/ +#ifndef XMpmc_mReadReg +#define XMpmc_mReadReg XMpmc_ReadReg +#endif + +#ifndef XMpmc_mWriteReg +#define XMpmc_mWriteReg XMpmc_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XMutex + * + *********************************************************************/ +#ifndef XMutex_mWriteReg +#define XMutex_mWriteReg XMutex_WriteReg +#endif + +#ifndef XMutex_mReadReg +#define XMutex_mReadReg XMutex_ReadReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XPcie + * + *********************************************************************/ +#ifndef XPcie_mReadReg +#define XPcie_mReadReg XPcie_ReadReg +#endif + +#ifndef XPcie_mWriteReg +#define XPcie_mWriteReg XPcie_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSpi + * + *********************************************************************/ +#ifndef XSpi_mIntrGlobalEnable +#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable +#endif + +#ifndef XSpi_mIntrGlobalDisable +#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable +#endif + +#ifndef XSpi_mIsIntrGlobalEnabled +#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled +#endif + +#ifndef XSpi_mIntrGetStatus +#define XSpi_mIntrGetStatus XSpi_IntrGetStatus +#endif + +#ifndef XSpi_mIntrClear +#define XSpi_mIntrClear XSpi_IntrClear +#endif + +#ifndef XSpi_mIntrEnable +#define XSpi_mIntrEnable XSpi_IntrEnable +#endif + +#ifndef XSpi_mIntrDisable +#define XSpi_mIntrDisable XSpi_IntrDisable +#endif + +#ifndef XSpi_mIntrGetEnabled +#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled +#endif + +#ifndef XSpi_mSetControlReg +#define XSpi_mSetControlReg XSpi_SetControlReg +#endif + +#ifndef XSpi_mGetControlReg +#define XSpi_mGetControlReg XSpi_GetControlReg +#endif + +#ifndef XSpi_mGetStatusReg +#define XSpi_mGetStatusReg XSpi_GetStatusReg +#endif + +#ifndef XSpi_mSetSlaveSelectReg +#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg +#endif + +#ifndef XSpi_mGetSlaveSelectReg +#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg +#endif + +#ifndef XSpi_mEnable +#define XSpi_mEnable XSpi_Enable +#endif + +#ifndef XSpi_mDisable +#define XSpi_mDisable XSpi_Disable +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysAce + * + *********************************************************************/ +#ifndef XSysAce_mGetControlReg +#define XSysAce_mGetControlReg XSysAce_GetControlReg +#endif + +#ifndef XSysAce_mSetControlReg +#define XSysAce_mSetControlReg XSysAce_SetControlReg +#endif + +#ifndef XSysAce_mOrControlReg +#define XSysAce_mOrControlReg XSysAce_OrControlReg +#endif + +#ifndef XSysAce_mAndControlReg +#define XSysAce_mAndControlReg XSysAce_AndControlReg +#endif + +#ifndef XSysAce_mGetErrorReg +#define XSysAce_mGetErrorReg XSysAce_GetErrorReg +#endif + +#ifndef XSysAce_mGetStatusReg +#define XSysAce_mGetStatusReg XSysAce_GetStatusReg +#endif + +#ifndef XSysAce_mWaitForLock +#define XSysAce_mWaitForLock XSysAce_WaitForLock +#endif + +#ifndef XSysAce_mEnableIntr +#define XSysAce_mEnableIntr XSysAce_EnableIntr +#endif + +#ifndef XSysAce_mDisableIntr +#define XSysAce_mDisableIntr XSysAce_DisableIntr +#endif + +#ifndef XSysAce_mIsReadyForCmd +#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd +#endif + +#ifndef XSysAce_mIsMpuLocked +#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked +#endif + +#ifndef XSysAce_mIsIntrEnabled +#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled +#endif + +/*********************************************************************/ +/** + * Macros for Driver XSysMon + * + *********************************************************************/ +#ifndef XSysMon_mIsEventSamplingModeSet +#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet +#endif + +#ifndef XSysMon_mIsDrpBusy +#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy +#endif + +#ifndef XSysMon_mIsDrpLocked +#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked +#endif + +#ifndef XSysMon_mRawToTemperature +#define XSysMon_mRawToTemperature XSysMon_RawToTemperature +#endif + +#ifndef XSysMon_mRawToVoltage +#define XSysMon_mRawToVoltage XSysMon_RawToVoltage +#endif + +#ifndef XSysMon_mTemperatureToRaw +#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw +#endif + +#ifndef XSysMon_mVoltageToRaw +#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw +#endif + +#ifndef XSysMon_mReadReg +#define XSysMon_mReadReg XSysMon_ReadReg +#endif + +#ifndef XSysMon_mWriteReg +#define XSysMon_mWriteReg XSysMon_WriteReg +#endif + +/*********************************************************************/ +/** + * Macros for Driver XTmrCtr + * + *********************************************************************/ +#ifndef XTimerCtr_mReadReg +#define XTimerCtr_mReadReg XTimerCtr_ReadReg +#endif + +#ifndef XTmrCtr_mWriteReg +#define XTmrCtr_mWriteReg XTmrCtr_WriteReg +#endif + +#ifndef XTmrCtr_mSetControlStatusReg +#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetControlStatusReg +#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg +#endif + +#ifndef XTmrCtr_mGetTimerCounterReg +#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg +#endif + +#ifndef XTmrCtr_mSetLoadReg +#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg +#endif + +#ifndef XTmrCtr_mGetLoadReg +#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg +#endif + +#ifndef XTmrCtr_mEnable +#define XTmrCtr_mEnable XTmrCtr_Enable +#endif + +#ifndef XTmrCtr_mDisable +#define XTmrCtr_mDisable XTmrCtr_Disable +#endif + +#ifndef XTmrCtr_mEnableIntr +#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr +#endif + +#ifndef XTmrCtr_mDisableIntr +#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr +#endif + +#ifndef XTmrCtr_mLoadTimerCounterReg +#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg +#endif + +#ifndef XTmrCtr_mHasEventOccurred +#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartLite + * + *********************************************************************/ +#ifndef XUartLite_mUpdateStats +#define XUartLite_mUpdateStats XUartLite_UpdateStats +#endif + +#ifndef XUartLite_mWriteReg +#define XUartLite_mWriteReg XUartLite_WriteReg +#endif + +#ifndef XUartLite_mReadReg +#define XUartLite_mReadReg XUartLite_ReadReg +#endif + +#ifndef XUartLite_mClearStats +#define XUartLite_mClearStats XUartLite_ClearStats +#endif + +#ifndef XUartLite_mSetControlReg +#define XUartLite_mSetControlReg XUartLite_SetControlReg +#endif + +#ifndef XUartLite_mGetStatusReg +#define XUartLite_mGetStatusReg XUartLite_GetStatusReg +#endif + +#ifndef XUartLite_mIsReceiveEmpty +#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty +#endif + +#ifndef XUartLite_mIsTransmitFull +#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull +#endif + +#ifndef XUartLite_mIsIntrEnabled +#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled +#endif + +#ifndef XUartLite_mEnableIntr +#define XUartLite_mEnableIntr XUartLite_EnableIntr +#endif + +#ifndef XUartLite_mDisableIntr +#define XUartLite_mDisableIntr XUartLite_DisableIntr +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUartNs550 + * + *********************************************************************/ +#ifndef XUartNs550_mUpdateStats +#define XUartNs550_mUpdateStats XUartNs550_UpdateStats +#endif + +#ifndef XUartNs550_mReadReg +#define XUartNs550_mReadReg XUartNs550_ReadReg +#endif + +#ifndef XUartNs550_mWriteReg +#define XUartNs550_mWriteReg XUartNs550_WriteReg +#endif + +#ifndef XUartNs550_mClearStats +#define XUartNs550_mClearStats XUartNs550_ClearStats +#endif + +#ifndef XUartNs550_mGetLineStatusReg +#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg +#endif + +#ifndef XUartNs550_mGetLineControlReg +#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg +#endif + +#ifndef XUartNs550_mSetLineControlReg +#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg +#endif + +#ifndef XUartNs550_mEnableIntr +#define XUartNs550_mEnableIntr XUartNs550_EnableIntr +#endif + +#ifndef XUartNs550_mDisableIntr +#define XUartNs550_mDisableIntr XUartNs550_DisableIntr +#endif + +#ifndef XUartNs550_mIsReceiveData +#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData +#endif + +#ifndef XUartNs550_mIsTransmitEmpty +#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty +#endif + +/*********************************************************************/ +/** + * Macros for Driver XUsb + * + *********************************************************************/ +#ifndef XUsb_mReadReg +#define XUsb_mReadReg XUsb_ReadReg +#endif + +#ifndef XUsb_mWriteReg +#define XUsb_mWriteReg XUsb_WriteReg +#endif + +#endif diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mem.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mem.h new file mode 100644 index 0000000..a2d5e66 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mem.h @@ -0,0 +1,59 @@ +/******************************************************************************/ +/** +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* @file xil_mem.h +* +* @addtogroup common_mem_operation_api Customized APIs for Memory Operations +* +* The xil_mem.h file contains prototype for functions related +* to memory operations. These APIs are applicable for all processors supported +* by Xilinx. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+*
    +* +*****************************************************************************/ + +/************************** Function Prototypes *****************************/ + +void Xil_MemCpy(void* dst, const void* src, u32 cnt); +/** +* @} End of "addtogroup common_mem_operation_api". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h new file mode 100644 index 0000000..c228c98 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h @@ -0,0 +1,277 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_misc_psreset_api.h +* +* This file contains the various register defintions and function prototypes for +* implementing the reset functionality of zynq ps devices +* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00b kpc 03/07/13 First release. +* +* +******************************************************************************/ + +#ifndef XIL_MISC_RESET_H /* prevent circular inclusions */ +#define XIL_MISC_RESET_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ +#define XDDRC_CTRL_BASEADDR 0xF8006000U +#define XSLCR_BASEADDR 0xF8000000U +/**< OCM configuration register */ +#define XSLCR_OCM_CFG_ADDR (XSLCR_BASEADDR + 0x00000910U) +/**< SLCR unlock register */ +#define XSLCR_UNLOCK_ADDR (XSLCR_BASEADDR + 0x00000008U) +/**< SLCR GEM0 rx clock control register */ +#define XSLCR_GEM0_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000138U) +/**< SLCR GEM1 rx clock control register */ +#define XSLCR_GEM1_RCLK_CTRL_ADDR (XSLCR_BASEADDR + 0x0000013CU) +/**< SLCR GEM0 clock control register */ +#define XSLCR_GEM0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000140U) +/**< SLCR GEM1 clock control register */ +#define XSLCR_GEM1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000144U) +/**< SLCR SMC clock control register */ +#define XSLCR_SMC_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000148U) +/**< SLCR GEM reset control register */ +#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U) +/**< SLCR USB0 clock control register */ +#define XSLCR_USB0_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000130U) +/**< SLCR USB1 clock control register */ +#define XSLCR_USB1_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000134U) +/**< SLCR USB1 reset control register */ +#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U) +/**< SLCR SMC reset control register */ +#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U) +/**< SLCR Level shifter enable register */ +#define XSLCR_LVL_SHFTR_EN_ADDR (XSLCR_BASEADDR + 0x00000900U) +/**< SLCR ARM pll control register */ +#define XSLCR_ARM_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000100U) +/**< SLCR DDR pll control register */ +#define XSLCR_DDR_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000104U) +/**< SLCR IO pll control register */ +#define XSLCR_IO_PLL_CTRL_ADDR (XSLCR_BASEADDR + 0x00000108U) +/**< SLCR ARM pll configuration register */ +#define XSLCR_ARM_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000110U) +/**< SLCR DDR pll configuration register */ +#define XSLCR_DDR_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000114U) +/**< SLCR IO pll configuration register */ +#define XSLCR_IO_PLL_CFG_ADDR (XSLCR_BASEADDR + 0x00000118U) +/**< SLCR ARM clock control register */ +#define XSLCR_ARM_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000120U) +/**< SLCR DDR clock control register */ +#define XSLCR_DDR_CLK_CTRL_ADDR (XSLCR_BASEADDR + 0x00000124U) +/**< SLCR MIO pin address register */ +#define XSLCR_MIO_PIN_00_ADDR (XSLCR_BASEADDR + 0x00000700U) +/**< SLCR DMAC reset control address register */ +#define XSLCR_DMAC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000020CU) +/**< SLCR USB reset control address register */ +/*#define XSLCR_USB_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000210U)*/ +/**< SLCR GEM reset control address register */ +/*#define XSLCR_GEM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000214U)*/ +/**< SLCR SDIO reset control address register */ +#define XSLCR_SDIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000218U) +/**< SLCR SPI reset control address register */ +#define XSLCR_SPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000021CU) +/**< SLCR CAN reset control address register */ +#define XSLCR_CAN_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000220U) +/**< SLCR I2C reset control address register */ +#define XSLCR_I2C_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000224U) +/**< SLCR UART reset control address register */ +#define XSLCR_UART_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000228U) +/**< SLCR GPIO reset control address register */ +#define XSLCR_GPIO_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x0000022CU) +/**< SLCR LQSPI reset control address register */ +#define XSLCR_LQSPI_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000230U) +/**< SLCR SMC reset control address register */ +/*#define XSLCR_SMC_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000234U)*/ +/**< SLCR OCM reset control address register */ +#define XSLCR_OCM_RST_CTRL_ADDR (XSLCR_BASEADDR + 0x00000238U) + +/**< SMC mem controller clear config register */ +#define XSMC_MEMC_CLR_CONFIG_OFFSET 0x0000000CU +/**< SMC idlecount configuration register */ +#define XSMC_REFRESH_PERIOD_0_OFFSET 0x00000020U +#define XSMC_REFRESH_PERIOD_1_OFFSET 0x00000024U +/**< SMC ECC configuration register */ +#define XSMC_ECC_MEMCFG1_OFFSET 0x00000404U +/**< SMC ECC command 1 register */ +#define XSMC_ECC_MEMCMD1_OFFSET 0x00000404U +/**< SMC ECC command 2 register */ +#define XSMC_ECC_MEMCMD2_OFFSET 0x00000404U + +/**< SLCR unlock code */ +#define XSLCR_UNLOCK_CODE 0x0000DF0DU + +/**< SMC mem clear configuration mask */ +#define XSMC_MEMC_CLR_CONFIG_MASK 0x000005FU +/**< SMC ECC memconfig 1 reset value */ +#define XSMC_ECC_MEMCFG1_RESET_VAL 0x0000043U +/**< SMC ECC memcommand 1 reset value */ +#define XSMC_ECC_MEMCMD1_RESET_VAL 0x01300080U +/**< SMC ECC memcommand 2 reset value */ +#define XSMC_ECC_MEMCMD2_RESET_VAL 0x01E00585U + +/**< DDR controller reset bit mask */ +#define XDDRPS_CTRL_RESET_MASK 0x00000001U +/**< SLCR OCM configuration reset value*/ +#define XSLCR_OCM_CFG_RESETVAL 0x00000008U +/**< SLCR OCM bank selection mask*/ +#define XSLCR_OCM_CFG_HIADDR_MASK 0x0000000FU +/**< SLCR level shifter enable mask*/ +#define XSLCR_LVL_SHFTR_EN_MASK 0x0000000FU + +/**< SLCR PLL register reset values */ +#define XSLCR_ARM_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_DDR_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_IO_PLL_CTRL_RESET_VAL 0x0001A008U +#define XSLCR_ARM_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_DDR_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_IO_PLL_CFG_RESET_VAL 0x00177EA0U +#define XSLCR_ARM_CLK_CTRL_RESET_VAL 0x1F000400U +#define XSLCR_DDR_CLK_CTRL_RESET_VAL 0x18400003U + +/**< SLCR MIO register default values */ +#define XSLCR_MIO_PIN_00_RESET_VAL 0x00001601U +#define XSLCR_MIO_PIN_02_RESET_VAL 0x00000601U + +/**< SLCR Reset control registers default values */ +#define XSLCR_DMAC_RST_CTRL_VAL 0x00000001U +#define XSLCR_GEM_RST_CTRL_VAL 0x000000F3U +#define XSLCR_USB_RST_CTRL_VAL 0x00000003U +#define XSLCR_I2C_RST_CTRL_VAL 0x00000003U +#define XSLCR_SPI_RST_CTRL_VAL 0x0000000FU +#define XSLCR_UART_RST_CTRL_VAL 0x0000000FU +#define XSLCR_QSPI_RST_CTRL_VAL 0x00000003U +#define XSLCR_GPIO_RST_CTRL_VAL 0x00000001U +#define XSLCR_SMC_RST_CTRL_VAL 0x00000003U +#define XSLCR_OCM_RST_CTRL_VAL 0x00000001U +#define XSLCR_SDIO_RST_CTRL_VAL 0x00000033U +#define XSLCR_CAN_RST_CTRL_VAL 0x00000003U +/**************************** Type Definitions *******************************/ + +/* the following data type is used to hold a null terminated version string + * consisting of the following format, "X.YYX" + */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +/* + * Performs reset operation to the ddr interface + */ +void XDdr_ResetHw(void); +/* + * Map the ocm region to post bootrom state + */ +void XOcm_Remap(void); +/* + * Performs the smc interface reset + */ +void XSmc_ResetHw(u32 BaseAddress); +/* + * updates the MIO registers with reset values + */ +void XSlcr_MioWriteResetValues(void); +/* + * updates the PLL and clock registers with reset values + */ +void XSlcr_PllWriteResetValues(void); +/* + * Disables the level shifters + */ +void XSlcr_DisableLevelShifters(void); +/* + * provides softreset to the GPIO interface + */ +void XSlcr_GpioPsReset(void); +/* + * provides softreset to the DMA interface + */ +void XSlcr_DmaPsReset(void); +/* + * provides softreset to the SMC interface + */ +void XSlcr_SmcPsReset(void); +/* + * provides softreset to the CAN interface + */ +void XSlcr_CanPsReset(void); +/* + * provides softreset to the Uart interface + */ +void XSlcr_UartPsReset(void); +/* + * provides softreset to the I2C interface + */ +void XSlcr_I2cPsReset(void); +/* + * provides softreset to the SPI interface + */ +void XSlcr_SpiPsReset(void); +/* + * provides softreset to the QSPI interface + */ +void XSlcr_QspiPsReset(void); +/* + * provides softreset to the USB interface + */ +void XSlcr_UsbPsReset(void); +/* + * provides softreset to the GEM interface + */ +void XSlcr_EmacPsReset(void); +/* + * provides softreset to the OCM interface + */ +void XSlcr_OcmReset(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* XIL_MISC_RESET_H */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mmu.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mmu.h new file mode 100644 index 0000000..dd14b63 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_mmu.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions +* +* MMU functions equip users to enable MMU, disable MMU and modify default +* memory attributes of MMU table as per the need. +* +* @{ +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 4.2	pkp	 07/21/14 Included xil_types.h file which contains definition for
+*					  u32 which resolves issue of CR#805869
+* 5.4	pkp	 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+*
    +* +* +******************************************************************************/ + +#ifndef XIL_MMU_H +#define XIL_MMU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/* Memory type */ +#define NORM_NONCACHE 0x11DE2 /* Normal Non-cacheable */ +#define STRONG_ORDERED 0xC02 /* Strongly ordered */ +#define DEVICE_MEMORY 0xC06 /* Device memory */ +#define RESERVED 0x0 /* reserved memory */ + +/* Normal write-through cacheable shareable */ +#define NORM_WT_CACHE 0x16DEA + +/* Normal write back cacheable shareable */ +#define NORM_WB_CACHE 0x15DE6 + +/* shareability attribute */ +#define SHAREABLE (0x1 << 16) +#define NON_SHAREABLE (~(0x1 << 16)) + +/* Execution type */ +#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0)) + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); +void Xil_EnableMMU(void); +void Xil_DisableMMU(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MMU_H */ +/** +* @} End of "addtogroup a9_mmu_apis". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_printf.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_printf.h new file mode 100644 index 0000000..016ae3b --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_printf.h @@ -0,0 +1,48 @@ + #ifndef XIL_PRINTF_H + #define XIL_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include "xil_types.h" +#include "xparameters.h" +#include "bspconfig.h" +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +#include "xen_console.h" +#endif + +/*----------------------------------------------------*/ +/* Use the following parameter passing structure to */ +/* make xil_printf re-entrant. */ +/*----------------------------------------------------*/ + +struct params_s; + + +/*---------------------------------------------------*/ +/* The purpose of this routine is to output data the */ +/* same as the standard printf function without the */ +/* overhead most run-time libraries involve. Usually */ +/* the printf brings in many kilobytes of code and */ +/* that is unacceptable in most embedded systems. */ +/*---------------------------------------------------*/ + +typedef char8* charptr; +typedef s32 (*func_ptr)(int c); + +/* */ + +void xil_printf( const char8 *ctrl1, ...); +void print( const char8 *ptr); +extern void outbyte (char8 c); +extern char8 inbyte(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h new file mode 100644 index 0000000..4bfac0a --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h @@ -0,0 +1,116 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.h +* +* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs. +* For sleep related functions that can be used across all Xilinx supported +* processors, please use xil_sleeptimer.h. +* +* +* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+*
+*
    +*****************************************************************************/ + +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32) +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SleepTTCCommon(u32 delay, u64 frequency); +void XTime_StartTTCTimer(); + +#endif +#endif /* XIL_SLEEPTIMER_H */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testcache.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testcache.h new file mode 100644 index 0000000..c35e9a4 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testcache.h @@ -0,0 +1,71 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testcache.h +* +* @addtogroup common_test_utils +*

    Cache test

    +* The xil_testcache.h file contains utility functions to test cache. +* +* @{ +* 
    +* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+*
    +* +******************************************************************************/ + +#ifndef XIL_TESTCACHE_H /* prevent circular inclusions */ +#define XIL_TESTCACHE_H /* by using protection macros */ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +extern s32 Xil_TestDCacheRange(void); +extern s32 Xil_TestDCacheAll(void); +extern s32 Xil_TestICacheRange(void); +extern s32 Xil_TestICacheAll(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testio.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testio.h new file mode 100644 index 0000000..ad68ead --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testio.h @@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testio.h +* +* @addtogroup common_test_utils Test Utilities +*

    I/O test

    +* The xil_testio.h file contains utility functions to test endian related memory +* IO functions. +* +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+*
    +* +******************************************************************************/ + +#ifndef XIL_TESTIO_H /* prevent circular inclusions */ +#define XIL_TESTIO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +#define XIL_TESTIO_DEFAULT 0 +#define XIL_TESTIO_LE 1 +#define XIL_TESTIO_BE 2 + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value); +extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap); +extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testmem.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testmem.h new file mode 100644 index 0000000..c204728 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_testmem.h @@ -0,0 +1,158 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_testmem.h +* @addtogroup common_test_utils +* +*

    Memory test

    +* +* The xil_testmem.h file contains utility functions to test memory. +* A subset of the memory tests can be selected or all of the tests can be run +* in order. If there is an error detected by a subtest, the test stops and the +* failure code is returned. Further tests are not run even if all of the tests +* are selected. +* Following list describes the supported memory tests: +* +* - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests. +* +* - XIL_TESTMEM_INCREMENT: This test +* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the +* test value for memory. +* +* - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test +* uses a walking '1' as the test value for memory. +* @code +* location 1 = 0x00000001 +* location 2 = 0x00000002 +* ... +* @endcode +* +* - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test. +* This test uses the inverse value of the walking ones test +* as the test value for memory. +* @code +* location 1 = 0xFFFFFFFE +* location 2 = 0xFFFFFFFD +* ... +*@endcode +* +* - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test. +* This test uses the inverse of the address of the location under test +* as the test value for memory. +* +* - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test. +* This test uses the provided patters as the test value for memory. +* If zero is provided as the pattern the test uses '0xDEADBEEF". +* +* @warning +* The tests are DESTRUCTIVE. Run before any initialized memory spaces +* have been set up. +* The address provided to the memory tests is not checked for +* validity except for the NULL case. It is possible to provide a code-space +* pointer for this test to start with and ultimately destroy executable code +* causing random failures. +* +* @note +* Used for spaces where the address range of the region is smaller than +* the data width. If the memory range is greater than 2 ** width, +* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will +* repeat on a boundry of a power of two making it more difficult to detect +* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR +* tests suffer the same problem. Ideally, if large blocks of memory are to be +* tested, break them up into smaller regions of memory to allow the test +* patterns used not to repeat over the region tested. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+*
    +* +******************************************************************************/ + +#ifndef XIL_TESTMEM_H /* prevent circular inclusions */ +#define XIL_TESTMEM_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + +/* xutil_memtest defines */ + +#define XIL_TESTMEM_INIT_VALUE 1U + +/** @name Memory subtests + * @{ + */ +/** + * See the detailed description of the subtests in the file description. + */ +#define XIL_TESTMEM_ALLMEMTESTS 0x00U +#define XIL_TESTMEM_INCREMENT 0x01U +#define XIL_TESTMEM_WALKONES 0x02U +#define XIL_TESTMEM_WALKZEROS 0x03U +#define XIL_TESTMEM_INVERSEADDR 0x04U +#define XIL_TESTMEM_FIXEDPATTERN 0x05U +#define XIL_TESTMEM_MAXTEST XIL_TESTMEM_FIXEDPATTERN +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/* xutil_testmem prototypes */ + +extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest); +extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest); +extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_types.h new file mode 100644 index 0000000..8143aff --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xil_types.h @@ -0,0 +1,209 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* @addtogroup common_types Basic Data types for Xilinx® Software IP +* +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+*
    +* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#include +#include + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ + +/* @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/* + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +/** @}*/ +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* @brief Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* @brief Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/* + * xbasic_types.h does not typedef s* or u64 + */ +/** @{ */ +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; +/** @}*/ +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include +#endif + +/** @{ */ +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/** + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. + * + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. + */ +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) + +/** + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number + */ +#define LOWER_32_BITS(n) ((u32)(n)) + + + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_types". +*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc.h new file mode 100644 index 0000000..735e26d --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc.h @@ -0,0 +1,172 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xl2cc.h +* +* This file contains the address definitions for the PL310 Level-2 Cache +* Controller. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XL2CC_H_ +#define _XL2CC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/* L2CC Register Offsets */ +#define XPS_L2CC_ID_OFFSET 0x0000U +#define XPS_L2CC_TYPE_OFFSET 0x0004U +#define XPS_L2CC_CNTRL_OFFSET 0x0100U +#define XPS_L2CC_AUX_CNTRL_OFFSET 0x0104U +#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET 0x0108U +#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET 0x010CU + +#define XPS_L2CC_EVNT_CNTRL_OFFSET 0x0200U +#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET 0x0204U +#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET 0x0208U +#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET 0x020CU +#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET 0x0210U + +#define XPS_L2CC_IER_OFFSET 0x0214U /* Interrupt Mask */ +#define XPS_L2CC_IPR_OFFSET 0x0218U /* Masked interrupt status */ +#define XPS_L2CC_ISR_OFFSET 0x021CU /* Raw Interrupt Status */ +#define XPS_L2CC_IAR_OFFSET 0x0220U /* Interrupt Clear */ + +#define XPS_L2CC_CACHE_SYNC_OFFSET 0x0730U /* Cache Sync */ +#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET 0x0740U /* Dummy Register for Cache Sync */ +#define XPS_L2CC_CACHE_INVLD_PA_OFFSET 0x0770U /* Cache Invalid by PA */ +#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET 0x077CU /* Cache Invalid by Way */ +#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET 0x07B0U /* Cache Clean by PA */ +#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET 0x07B8U /* Cache Clean by Index */ +#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET 0x07BCU /* Cache Clean by Way */ +#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET 0x07F0U /* Cache Invalidate and Clean by PA */ +#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET 0x07F8U /* Cache Invalidate and Clean by Index */ +#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET 0x07FCU /* Cache Invalidate and Clean by Way */ + +#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET 0x0900U /* Cache Data Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET 0x0904U /* Cache Instruction Lockdown 0 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET 0x0908U /* Cache Data Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET 0x090CU /* Cache Instruction Lockdown 1 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET 0x0910U /* Cache Data Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET 0x0914U /* Cache Instruction Lockdown 2 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET 0x0918U /* Cache Data Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET 0x091CU /* Cache Instruction Lockdown 3 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET 0x0920U /* Cache Data Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET 0x0924U /* Cache Instruction Lockdown 4 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET 0x0928U /* Cache Data Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET 0x092CU /* Cache Instruction Lockdown 5 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET 0x0930U /* Cache Data Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET 0x0934U /* Cache Instruction Lockdown 6 by Way */ +#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET 0x0938U /* Cache Data Lockdown 7 by Way */ +#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET 0x093CU /* Cache Instruction Lockdown 7 by Way */ + +#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U /* Cache Lockdown Line Enable */ +#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET 0x0954U /* Cache Unlock All Lines by Way */ + +#define XPS_L2CC_ADDR_FILTER_START_OFFSET 0x0C00U /* Start of address filtering */ +#define XPS_L2CC_ADDR_FILTER_END_OFFSET 0x0C04U /* Start of address filtering */ + +#define XPS_L2CC_DEBUG_CTRL_OFFSET 0x0F40U /* Debug Control Register */ + +/* XPS_L2CC_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_ENABLE_MASK 0x00000001U /* enables the L2CC */ + +/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */ +#define XPS_L2CC_AUX_EBRESPE_MASK 0x40000000U /* Early BRESP Enable */ +#define XPS_L2CC_AUX_IPFE_MASK 0x20000000U /* Instruction Prefetch Enable */ +#define XPS_L2CC_AUX_DPFE_MASK 0x10000000U /* Data Prefetch Enable */ +#define XPS_L2CC_AUX_NSIC_MASK 0x08000000U /* Non-secure interrupt access control */ +#define XPS_L2CC_AUX_NSLE_MASK 0x04000000U /* Non-secure lockdown enable */ +#define XPS_L2CC_AUX_CRP_MASK 0x02000000U /* Cache replacement policy */ +#define XPS_L2CC_AUX_FWE_MASK 0x01800000U /* Force write allocate */ +#define XPS_L2CC_AUX_SAOE_MASK 0x00400000U /* Shared attribute override enable */ +#define XPS_L2CC_AUX_PE_MASK 0x00200000U /* Parity enable */ +#define XPS_L2CC_AUX_EMBE_MASK 0x00100000U /* Event monitor bus enable */ +#define XPS_L2CC_AUX_WAY_SIZE_MASK 0x000E0000U /* Way-size */ +#define XPS_L2CC_AUX_ASSOC_MASK 0x00010000U /* Associativity */ +#define XPS_L2CC_AUX_SAIE_MASK 0x00002000U /* Shared attribute invalidate enable */ +#define XPS_L2CC_AUX_EXCL_CACHE_MASK 0x00001000U /* Exclusive cache configuration */ +#define XPS_L2CC_AUX_SBDLE_MASK 0x00000800U /* Store buffer device limitation Enable */ +#define XPS_L2CC_AUX_HPSODRE_MASK 0x00000400U /* High Priority for SO and Dev Reads Enable */ +#define XPS_L2CC_AUX_FLZE_MASK 0x00000001U /* Full line of zero enable */ + +#define XPS_L2CC_AUX_REG_DEFAULT_MASK 0x72360000U /* Enable all prefetching, */ + /* Cache replacement policy, Parity enable, */ + /* Event monitor bus enable and Way Size (64 KB) */ +#define XPS_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFFU /* */ + +#define XPS_L2CC_TAG_RAM_DEFAULT_MASK 0x00000111U /* latency for TAG RAM */ +#define XPS_L2CC_DATA_RAM_DEFAULT_MASK 0x00000121U /* latency for DATA RAM */ + +/* Interrupt bit masks */ +#define XPS_L2CC_IXR_DECERR_MASK 0x00000100U /* DECERR from L3 */ +#define XPS_L2CC_IXR_SLVERR_MASK 0x00000080U /* SLVERR from L3 */ +#define XPS_L2CC_IXR_ERRRD_MASK 0x00000040U /* Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_ERRRT_MASK 0x00000020U /* Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ERRWD_MASK 0x00000010U /* Error on L2 data RAM (Write) */ +#define XPS_L2CC_IXR_ERRWT_MASK 0x00000008U /* Error on L2 tag RAM (Write) */ +#define XPS_L2CC_IXR_PARRD_MASK 0x00000004U /* Parity Error on L2 data RAM (Read) */ +#define XPS_L2CC_IXR_PARRT_MASK 0x00000002U /* Parity Error on L2 tag RAM (Read) */ +#define XPS_L2CC_IXR_ECNTR_MASK 0x00000001U /* Event Counter1/0 Overflow Increment */ + +/* Address filtering mask and enable bit */ +#define XPS_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000U /* Address filtering valid bits*/ +#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U /* Address filtering enable bit*/ + +/* Debug control bits */ +#define XPS_L2CC_DEBUG_SPIDEN_MASK 0x00000004U /* Debug SPIDEN bit */ +#define XPS_L2CC_DEBUG_DWB_MASK 0x00000002U /* Debug DWB bit, forces write through */ +#define XPS_L2CC_DEBUG_DCL_MASK 0x00000002U /* Debug DCL bit, disables cache line fill */ + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc_counter.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc_counter.h new file mode 100644 index 0000000..8d0a61f --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xl2cc_counter.h @@ -0,0 +1,113 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xl2cc_counter.h +* +* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions +* +* xl2cc_counter.h contains APIs for configuring and controlling the event +* counters in PL310 L2 cache controller. +* PL310 has two event counters which can be used to count variety of events +* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions +* for different configurations which can be used for the event counters to +* count a set of events. +* +* +* @{ +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+*
    +* +******************************************************************************/ + +#ifndef L2CCCOUNTER_H /* prevent circular inclusions */ +#define L2CCCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* + * The following constants define the event codes for the event counters. + */ +#define XL2CC_CO 0x1 +#define XL2CC_DRHIT 0x2 +#define XL2CC_DRREQ 0x3 +#define XL2CC_DWHIT 0x4 +#define XL2CC_DWREQ 0x5 +#define XL2CC_DWTREQ 0x6 +#define XL2CC_IRHIT 0x7 +#define XL2CC_IRREQ 0x8 +#define XL2CC_WA 0x9 +#define XL2CC_IPFALLOC 0xa +#define XL2CC_EPFHIT 0xb +#define XL2CC_EPFALLOC 0xc +#define XL2CC_SRRCVD 0xd +#define XL2CC_SRCONF 0xe +#define XL2CC_EPFRCVD 0xf + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +void XL2cc_EventCtrInit(s32 Event0, s32 Event1); +void XL2cc_EventCtrStart(void); +void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* L2CCCOUNTER_H */ +/** +* @} End of "addtogroup l2_event_counter_apis". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters.h new file mode 100644 index 0000000..cfa8887 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters.h @@ -0,0 +1,499 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + +/* Definition for CPU ID */ +#define XPAR_CPU_ID 0U + +/* Definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_CORTEXA9_0 */ +#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 + + +/******************************************************************/ + +#include "xparameters_ps.h" + +#define STDIN_BASEADDRESS 0xE0001000 +#define STDOUT_BASEADDRESS 0xE0001000 + +/******************************************************************/ + +/* Platform specific definitions */ +#define PLATFORM_ZYNQ + +/* Definitions for sleep timer configuration */ +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + + +/******************************************************************/ +/* Definitions for driver CANPS */ +#define XPAR_XCANPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_CAN_0 */ +#define XPAR_PS7_CAN_0_DEVICE_ID 0 +#define XPAR_PS7_CAN_0_BASEADDR 0xE0008000 +#define XPAR_PS7_CAN_0_HIGHADDR 0xE0008FFF +#define XPAR_PS7_CAN_0_CAN_CLK_FREQ_HZ 23809523 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_CAN_0 */ +#define XPAR_XCANPS_0_DEVICE_ID XPAR_PS7_CAN_0_DEVICE_ID +#define XPAR_XCANPS_0_BASEADDR 0xE0008000 +#define XPAR_XCANPS_0_HIGHADDR 0xE0008FFF +#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 23809523 + + +/******************************************************************/ + + +/* Definitions for peripheral PS7_DDR_0 */ +#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000 +#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x3FFFFFFF + + +/******************************************************************/ + +/* Definitions for driver DEVCFG */ +#define XPAR_XDCFG_NUM_INSTANCES 1U + +/* Definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U +#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U +#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DEV_CFG_0 */ +#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID +#define XPAR_XDCFG_0_BASEADDR 0xF8007000U +#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU + + +/******************************************************************/ + +/* Definitions for driver DMAPS */ +#define XPAR_XDMAPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PS7_DMA_NS */ +#define XPAR_PS7_DMA_NS_DEVICE_ID 0 +#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000 +#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF + + +/* Definitions for peripheral PS7_DMA_S */ +#define XPAR_PS7_DMA_S_DEVICE_ID 1 +#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000 +#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_DMA_NS */ +#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID +#define XPAR_XDMAPS_0_BASEADDR 0xF8004000 +#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF + +/* Canonical definitions for peripheral PS7_DMA_S */ +#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID +#define XPAR_XDMAPS_1_BASEADDR 0xF8003000 +#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF + + +/******************************************************************/ + +/* Definitions for driver EMACPS */ +#define XPAR_XEMACPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0 +#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000 +#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF +#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 +#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 +#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PS7_ETHERNET_0 */ +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID +#define XPAR_XEMACPS_0_BASEADDR 0xE000B000 +#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 25000000 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0 + + +/******************************************************************/ + + +/* Definitions for peripheral PS7_AFI_0 */ +#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000 +#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF + + +/* Definitions for peripheral PS7_AFI_1 */ +#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000 +#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF + + +/* Definitions for peripheral PS7_AFI_2 */ +#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000 +#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF + + +/* Definitions for peripheral PS7_AFI_3 */ +#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000 +#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF + + +/* Definitions for peripheral PS7_DDRC_0 */ +#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000 +#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF + + +/* Definitions for peripheral PS7_GLOBALTIMER_0 */ +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200 +#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF + + +/* Definitions for peripheral PS7_GPV_0 */ +#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000 +#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF + + +/* Definitions for peripheral PS7_INTC_DIST_0 */ +#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000 +#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF + + +/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */ +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000 +#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF + + +/* Definitions for peripheral PS7_L2CACHEC_0 */ +#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Definitions for peripheral PS7_OCMC_0 */ +#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000 +#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF + + +/* Definitions for peripheral PS7_PL310_0 */ +#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000 +#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF + + +/* Definitions for peripheral PS7_PMU_0 */ +#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000 +#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF +#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000 +#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF + + +/* Definitions for peripheral PS7_QSPI_LINEAR_0 */ +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000 +#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF + + +/* Definitions for peripheral PS7_RAM_0 */ +#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000 +#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF + + +/* Definitions for peripheral PS7_RAM_1 */ +#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000 +#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Definitions for peripheral PS7_SCUC_0 */ +#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000 +#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC + + +/* Definitions for peripheral PS7_SLCR_0 */ +#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000 +#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF + + +/******************************************************************/ + +/* Definitions for driver GPIOPS */ +#define XPAR_XGPIOPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_GPIO_0 */ +#define XPAR_PS7_GPIO_0_DEVICE_ID 0 +#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000 +#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_GPIO_0 */ +#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID +#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000 +#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF + + +/******************************************************************/ + +/* Definitions for driver IICPS */ +#define XPAR_XIICPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_I2C_0 */ +#define XPAR_PS7_I2C_0_DEVICE_ID 0 +#define XPAR_PS7_I2C_0_BASEADDR 0xE0004000 +#define XPAR_PS7_I2C_0_HIGHADDR 0xE0004FFF +#define XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ 111111115 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_I2C_0 */ +#define XPAR_XIICPS_0_DEVICE_ID XPAR_PS7_I2C_0_DEVICE_ID +#define XPAR_XIICPS_0_BASEADDR 0xE0004000 +#define XPAR_XIICPS_0_HIGHADDR 0xE0004FFF +#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 111111115 + + +/******************************************************************/ + +/* Definitions for driver QSPIPS */ +#define XPAR_XQSPIPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_QSPI_0 */ +#define XPAR_PS7_QSPI_0_DEVICE_ID 0 +#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000 +#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF +#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000 +#define XPAR_PS7_QSPI_0_QSPI_MODE 0 +#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_QSPI_0 */ +#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID +#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000 +#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF +#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000 +#define XPAR_XQSPIPS_0_QSPI_MODE 0 +#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Definitions for driver SCUGIC */ +#define XPAR_XSCUGIC_NUM_INSTANCES 1U + +/* Definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U +#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U +#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU +#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUGIC_0 */ +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U + + +/******************************************************************/ + +/* Definitions for driver SCUTIMER */ +#define XPAR_XSCUTIMER_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0 +#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUTIMER_0 */ +#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID +#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600 +#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F + + +/******************************************************************/ + +/* Definitions for driver SCUWDT */ +#define XPAR_XSCUWDT_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0 +#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_SCUWDT_0 */ +#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID +#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620 +#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF + + +/******************************************************************/ + +/* Definitions for driver SDPS */ +#define XPAR_XSDPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_SD_0 */ +#define XPAR_PS7_SD_0_DEVICE_ID 0 +#define XPAR_PS7_SD_0_BASEADDR 0xE0100000 +#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF +#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000 +#define XPAR_PS7_SD_0_HAS_CD 1 +#define XPAR_PS7_SD_0_HAS_WP 1 +#define XPAR_PS7_SD_0_BUS_WIDTH 0 +#define XPAR_PS7_SD_0_MIO_BANK 0 +#define XPAR_PS7_SD_0_HAS_EMIO 0 + + +/******************************************************************/ + +#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PS7_SD_0 */ +#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID +#define XPAR_XSDPS_0_BASEADDR 0xE0100000 +#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000 +#define XPAR_XSDPS_0_HAS_CD 1 +#define XPAR_XSDPS_0_HAS_WP 1 +#define XPAR_XSDPS_0_BUS_WIDTH 0 +#define XPAR_XSDPS_0_MIO_BANK 0 +#define XPAR_XSDPS_0_HAS_EMIO 0 + + +/******************************************************************/ + +/* Definitions for driver TTCPS */ +#define XPAR_XTTCPS_NUM_INSTANCES 3U + +/* Definitions for peripheral PS7_TTC_0 */ +#define XPAR_PS7_TTC_0_DEVICE_ID 0U +#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U +#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U +#define XPAR_PS7_TTC_1_DEVICE_ID 1U +#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U +#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U +#define XPAR_PS7_TTC_2_DEVICE_ID 2U +#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U +#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_TTC_0 */ +#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID +#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID +#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U + +#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID +#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U + + +/******************************************************************/ + +/* Definitions for driver UARTPS */ +#define XPAR_XUARTPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_UART_1 */ +#define XPAR_PS7_UART_1_DEVICE_ID 0 +#define XPAR_PS7_UART_1_BASEADDR 0xE0001000 +#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF +#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000 +#define XPAR_PS7_UART_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_UART_1 */ +#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID +#define XPAR_XUARTPS_0_BASEADDR 0xE0001000 +#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000 +#define XPAR_XUARTPS_0_HAS_MODEM 0 + + +/******************************************************************/ + +/* Definitions for driver USBPS */ +#define XPAR_XUSBPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_USB_0 */ +#define XPAR_PS7_USB_0_DEVICE_ID 0 +#define XPAR_PS7_USB_0_BASEADDR 0xE0002000 +#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_USB_0 */ +#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID +#define XPAR_XUSBPS_0_BASEADDR 0xE0002000 +#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF + + +/******************************************************************/ + +/* Definitions for driver XADCPS */ +#define XPAR_XADCPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PS7_XADC_0 */ +#define XPAR_PS7_XADC_0_DEVICE_ID 0 +#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100 +#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PS7_XADC_0 */ +#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID +#define XPAR_XADCPS_0_BASEADDR 0xF8007100 +#define XPAR_XADCPS_0_HIGHADDR 0xF8007120 + + +/******************************************************************/ + +#endif /* end of protection macro */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters_ps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters_ps.h new file mode 100644 index 0000000..0fa7771 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xparameters_ps.h @@ -0,0 +1,338 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xparameters_ps.h +* +* This file contains the address definitions for the hard peripherals +* attached to the ARM Cortex A9 core. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6   srm     10/18/17 Added ARMA9 macro to identify CortexA9
+*
+*
    +* +* @note +* +* None. +* +******************************************************************************/ + +#ifndef _XPARAMETERS_PS_H_ +#define _XPARAMETERS_PS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/**************************** Include Files *******************************/ + + +/************************** Constant Definitions *****************************/ + +/* + * This block contains constant declarations for the peripherals + * within the hardblock + */ + +/* Canonical definitions for DDR MEMORY */ +#define XPAR_DDR_MEM_BASEADDR 0x00000000U +#define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU + +/* Canonical definitions for Interrupts */ +#define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID +#define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID +#define XPAR_XUSBPS_0_INTR XPS_USB0_INT_ID +#define XPAR_XUSBPS_1_INTR XPS_USB1_INT_ID +#define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID +#define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID +#define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID +#define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID +#define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID +#define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID +#define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID +#define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID +#define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID +#define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID +#define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID +#define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID +#define XPAR_XWDTPS_0_INTR XPS_WDT_INT_ID +#define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID +#define XPAR_SCUTIMER_INTR XPS_SCU_TMR_INT_ID +#define XPAR_SCUWDT_INTR XPS_SCU_WDT_INT_ID +#define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID +#define XPAR_XDMAPS_0_FAULT_INTR XPS_DMA0_ABORT_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_0 XPS_DMA0_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_1 XPS_DMA1_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_2 XPS_DMA2_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_3 XPS_DMA3_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_4 XPS_DMA4_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_5 XPS_DMA5_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_6 XPS_DMA6_INT_ID +#define XPAR_XDMAPS_0_DONE_INTR_7 XPS_DMA7_INT_ID + + +#define XPAR_XQSPIPS_0_LINEAR_BASEADDR XPS_QSPI_LINEAR_BASEADDR +#define XPAR_XPARPORTPS_CTRL_BASEADDR XPS_PARPORT_CRTL_BASEADDR + + + +/* Canonical definitions for DMAC */ + + +/* Canonical definitions for WDT */ + +/* Canonical definitions for SLCR */ +#define XPAR_XSLCR_NUM_INSTANCES 1U +#define XPAR_XSLCR_0_DEVICE_ID 0U +#define XPAR_XSLCR_0_BASEADDR XPS_SYS_CTRL_BASEADDR + +/* Canonical definitions for SCU GIC */ +#define XPAR_SCUGIC_NUM_INSTANCES 1U +#define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U +#define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000100U) +#define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) +#define XPAR_SCUGIC_ACK_BEFORE 0U + +/* Canonical definitions for Global Timer */ +#define XPAR_GLOBAL_TMR_NUM_INSTANCES 1U +#define XPAR_GLOBAL_TMR_DEVICE_ID 0U +#define XPAR_GLOBAL_TMR_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00000200U) +#define XPAR_GLOBAL_TMR_INTR XPS_GLOBAL_TMR_INT_ID + + +/* Xilinx Parallel Flash Library (XilFlash) User Settings */ +#define XPAR_AXI_EMC + + +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ + + +/* + * This block contains constant declarations for the peripherals + * within the hardblock. These have been put for bacwards compatibilty + */ + +#define XPS_PERIPHERAL_BASEADDR 0xE0000000U +#define XPS_UART0_BASEADDR 0xE0000000U +#define XPS_UART1_BASEADDR 0xE0001000U +#define XPS_USB0_BASEADDR 0xE0002000U +#define XPS_USB1_BASEADDR 0xE0003000U +#define XPS_I2C0_BASEADDR 0xE0004000U +#define XPS_I2C1_BASEADDR 0xE0005000U +#define XPS_SPI0_BASEADDR 0xE0006000U +#define XPS_SPI1_BASEADDR 0xE0007000U +#define XPS_CAN0_BASEADDR 0xE0008000U +#define XPS_CAN1_BASEADDR 0xE0009000U +#define XPS_GPIO_BASEADDR 0xE000A000U +#define XPS_GEM0_BASEADDR 0xE000B000U +#define XPS_GEM1_BASEADDR 0xE000C000U +#define XPS_QSPI_BASEADDR 0xE000D000U +#define XPS_PARPORT_CRTL_BASEADDR 0xE000E000U +#define XPS_SDIO0_BASEADDR 0xE0100000U +#define XPS_SDIO1_BASEADDR 0xE0101000U +#define XPS_IOU_BUS_CFG_BASEADDR 0xE0200000U +#define XPS_NAND_BASEADDR 0xE1000000U +#define XPS_PARPORT0_BASEADDR 0xE2000000U +#define XPS_PARPORT1_BASEADDR 0xE4000000U +#define XPS_QSPI_LINEAR_BASEADDR 0xFC000000U +#define XPS_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */ +#define XPS_TTC0_BASEADDR 0xF8001000U +#define XPS_TTC1_BASEADDR 0xF8002000U +#define XPS_DMAC0_SEC_BASEADDR 0xF8003000U +#define XPS_DMAC0_NON_SEC_BASEADDR 0xF8004000U +#define XPS_WDT_BASEADDR 0xF8005000U +#define XPS_DDR_CTRL_BASEADDR 0xF8006000U +#define XPS_DEV_CFG_APB_BASEADDR 0xF8007000U +#define XPS_AFI0_BASEADDR 0xF8008000U +#define XPS_AFI1_BASEADDR 0xF8009000U +#define XPS_AFI2_BASEADDR 0xF800A000U +#define XPS_AFI3_BASEADDR 0xF800B000U +#define XPS_OCM_BASEADDR 0xF800C000U +#define XPS_EFUSE_BASEADDR 0xF800D000U +#define XPS_CORESIGHT_BASEADDR 0xF8800000U +#define XPS_TOP_BUS_CFG_BASEADDR 0xF8900000U +#define XPS_SCU_PERIPH_BASE 0xF8F00000U +#define XPS_L2CC_BASEADDR 0xF8F02000U +#define XPS_SAM_RAM_BASEADDR 0xFFFC0000U +#define XPS_FPGA_AXI_S0_BASEADDR 0x40000000U +#define XPS_FPGA_AXI_S1_BASEADDR 0x80000000U +#define XPS_IOU_S_SWITCH_BASEADDR 0xE0000000U +#define XPS_PERIPH_APB_BASEADDR 0xF8000000U + +/* Shared Peripheral Interrupts (SPI) */ +#define XPS_CORE_PARITY0_INT_ID 32U +#define XPS_CORE_PARITY1_INT_ID 33U +#define XPS_L2CC_INT_ID 34U +#define XPS_OCMINTR_INT_ID 35U +#define XPS_ECC_INT_ID 36U +#define XPS_PMU0_INT_ID 37U +#define XPS_PMU1_INT_ID 38U +#define XPS_SYSMON_INT_ID 39U +#define XPS_DVC_INT_ID 40U +#define XPS_WDT_INT_ID 41U +#define XPS_TTC0_0_INT_ID 42U +#define XPS_TTC0_1_INT_ID 43U +#define XPS_TTC0_2_INT_ID 44U +#define XPS_DMA0_ABORT_INT_ID 45U +#define XPS_DMA0_INT_ID 46U +#define XPS_DMA1_INT_ID 47U +#define XPS_DMA2_INT_ID 48U +#define XPS_DMA3_INT_ID 49U +#define XPS_SMC_INT_ID 50U +#define XPS_QSPI_INT_ID 51U +#define XPS_GPIO_INT_ID 52U +#define XPS_USB0_INT_ID 53U +#define XPS_GEM0_INT_ID 54U +#define XPS_GEM0_WAKE_INT_ID 55U +#define XPS_SDIO0_INT_ID 56U +#define XPS_I2C0_INT_ID 57U +#define XPS_SPI0_INT_ID 58U +#define XPS_UART0_INT_ID 59U +#define XPS_CAN0_INT_ID 60U +#define XPS_FPGA0_INT_ID 61U +#define XPS_FPGA1_INT_ID 62U +#define XPS_FPGA2_INT_ID 63U +#define XPS_FPGA3_INT_ID 64U +#define XPS_FPGA4_INT_ID 65U +#define XPS_FPGA5_INT_ID 66U +#define XPS_FPGA6_INT_ID 67U +#define XPS_FPGA7_INT_ID 68U +#define XPS_TTC1_0_INT_ID 69U +#define XPS_TTC1_1_INT_ID 70U +#define XPS_TTC1_2_INT_ID 71U +#define XPS_DMA4_INT_ID 72U +#define XPS_DMA5_INT_ID 73U +#define XPS_DMA6_INT_ID 74U +#define XPS_DMA7_INT_ID 75U +#define XPS_USB1_INT_ID 76U +#define XPS_GEM1_INT_ID 77U +#define XPS_GEM1_WAKE_INT_ID 78U +#define XPS_SDIO1_INT_ID 79U +#define XPS_I2C1_INT_ID 80U +#define XPS_SPI1_INT_ID 81U +#define XPS_UART1_INT_ID 82U +#define XPS_CAN1_INT_ID 83U +#define XPS_FPGA8_INT_ID 84U +#define XPS_FPGA9_INT_ID 85U +#define XPS_FPGA10_INT_ID 86U +#define XPS_FPGA11_INT_ID 87U +#define XPS_FPGA12_INT_ID 88U +#define XPS_FPGA13_INT_ID 89U +#define XPS_FPGA14_INT_ID 90U +#define XPS_FPGA15_INT_ID 91U + +/* Private Peripheral Interrupts (PPI) */ +#define XPS_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */ +#define XPS_FIQ_INT_ID 28U /* FIQ from FPGA fabric */ +#define XPS_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */ +#define XPS_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */ +#define XPS_IRQ_INT_ID 31U /* IRQ from FPGA fabric */ + + +/* REDEFINES for TEST APP */ +/* Definitions for UART */ +#define XPAR_PS7_UART_0_INTR XPS_UART0_INT_ID +#define XPAR_PS7_UART_1_INTR XPS_UART1_INT_ID +#define XPAR_PS7_USB_0_INTR XPS_USB0_INT_ID +#define XPAR_PS7_USB_1_INTR XPS_USB1_INT_ID +#define XPAR_PS7_I2C_0_INTR XPS_I2C0_INT_ID +#define XPAR_PS7_I2C_1_INTR XPS_I2C1_INT_ID +#define XPAR_PS7_SPI_0_INTR XPS_SPI0_INT_ID +#define XPAR_PS7_SPI_1_INTR XPS_SPI1_INT_ID +#define XPAR_PS7_CAN_0_INTR XPS_CAN0_INT_ID +#define XPAR_PS7_CAN_1_INTR XPS_CAN1_INT_ID +#define XPAR_PS7_GPIO_0_INTR XPS_GPIO_INT_ID +#define XPAR_PS7_ETHERNET_0_INTR XPS_GEM0_INT_ID +#define XPAR_PS7_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID +#define XPAR_PS7_ETHERNET_1_INTR XPS_GEM1_INT_ID +#define XPAR_PS7_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID +#define XPAR_PS7_QSPI_0_INTR XPS_QSPI_INT_ID +#define XPAR_PS7_WDT_0_INTR XPS_WDT_INT_ID +#define XPAR_PS7_SCUWDT_0_INTR XPS_SCU_WDT_INT_ID +#define XPAR_PS7_SCUTIMER_0_INTR XPS_SCU_TMR_INT_ID +#define XPAR_PS7_XADC_0_INTR XPS_SYSMON_INT_ID +#define XPAR_PS7_TTC_0_INTR XPS_TTC0_0_INT_ID +#define XPAR_PS7_TTC_1_INTR XPS_TTC0_1_INT_ID +#define XPAR_PS7_TTC_2_INTR XPS_TTC0_2_INT_ID +#define XPAR_PS7_TTC_3_INTR XPS_TTC1_0_INT_ID +#define XPAR_PS7_TTC_4_INTR XPS_TTC1_1_INT_ID +#define XPAR_PS7_TTC_5_INTR XPS_TTC1_2_INT_ID + +#define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID + +/* For backwards compatibilty */ +#define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ +#define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ +#define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ +#define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ +#define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ +#define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ + +#define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ + +#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ +#endif + +#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ +#endif + +#define XPAR_SCUTIMER_DEVICE_ID 0U +#define XPAR_SCUWDT_DEVICE_ID 0U + + +#ifdef __cplusplus +} +#endif + +#endif /* protection macro */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xplatform_info.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xplatform_info.h new file mode 100644 index 0000000..0582222 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xplatform_info.h @@ -0,0 +1,109 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xplatform_info.h +* +* @addtogroup common_platform_info APIs to Get Platform Information +* +* The xplatform_info.h file contains definitions for various available Xilinx® +* platforms. Also, it contains prototype of APIs, which can be used to get the +* platform information. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date    Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4    ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                      function for PMUFW.
+*
    +* +******************************************************************************/ + +#ifndef XPLATFORM_INFO_H /* prevent circular inclusions */ +#define XPLATFORM_INFO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +#define XPAR_CSU_BASEADDR 0xFFCA0000U +#define XPAR_CSU_VER_OFFSET 0x00000044U + +#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0 +#define XPLAT_ZYNQ_ULTRA_MP 0x1 +#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2 +#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3 +#define XPLAT_ZYNQ 0x4 +#define XPLAT_MICROBLAZE 0x5 + +#define XPS_VERSION_1 0x0 +#define XPS_VERSION_2 0x1 + +#define XPLAT_INFO_MASK (0xF) +#define XPLAT_INFO_SHIFT (0xC) +#define XPS_VERSION_INFO_MASK (0xF) + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +u32 XGetPlatform_Info(); + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) +u32 XGetPSVersion_Info(); +#endif + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +u32 XGet_Zynq_UltraMp_Platform_info(); +#endif +/************************** Function Prototypes ******************************/ + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_platform_info". +*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpm_counter.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpm_counter.h new file mode 100644 index 0000000..45f0919 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpm_counter.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpm_counter.h +* +* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions +* +* Cortex A9 event counter functions can be utilized to configure and control +* the Cortex-A9 performance monitor events. +* +* Cortex-A9 performance monitor has six event counters which can be used to +* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines +* configurations XPM_CNTRCFGx which can be used to program the event counters +* to count a set of events. +* +* @note +* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is +* being used for time keeping. +* +* @{ +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+*
    +* +******************************************************************************/ + +#ifndef XPMCOUNTER_H /* prevent circular inclusions */ +#define XPMCOUNTER_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include +#include "xpseudo_asm.h" +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/* Number of performance counters */ +#define XPM_CTRCOUNT 6U + +/* The following constants define the Cortex-A9 Performance Monitor Events */ + +/* + * Software increment. The register is incremented only on writes to the + * Software Increment Register + */ +#define XPM_EVENT_SOFTINCR 0x00U + +/* + * Instruction fetch that causes a refill at (at least) the lowest level(s) of + * instruction or unified cache. Includes the speculative linefills in the + * count + */ +#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U + +/* + * Instruction fetch that causes a TLB refill at (at least) the lowest level of + * TLB. Includes the speculative requests in the count + */ +#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U + +/* + * Data read or write operation that causes a refill at (at least) the lowest + * level(s)of data or unified cache. Counts the number of allocations performed + * in the Data Cache due to a read or a write + */ +#define XPM_EVENT_DATA_CACHEREFILL 0x03U + +/* + * Data read or write operation that causes a cache access at (at least) the + * lowest level(s) of data or unified cache. This includes speculative reads + */ +#define XPM_EVENT_DATA_CACHEACCESS 0x04U + +/* + * Data read or write operation that causes a TLB refill at (at least) the + * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI, + * CP15 Cache operation by MVA and CP15 VA to PA operations + */ +#define XPM_EVENT_DATA_TLBREFILL 0x05U + +/* + * Data read architecturally executed. Counts the number of data read + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted LDR/LDM, as well as the reads due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_READS 0x06U + +/* + * Data write architecturally executed. Counts the number of data write + * instructions accepted by the Load Store Unit. This includes counting the + * speculative and aborted STR/STM, as well as the writes due to the SWP + * instructions + */ +#define XPM_EVENT_DATA_WRITE 0x07U + +/* Exception taken. Counts the number of exceptions architecturally taken.*/ +#define XPM_EVENT_EXCEPTION 0x09U + +/* Exception return architecturally executed.*/ +#define XPM_EVENT_EXCEPRETURN 0x0AU + +/* + * Change to ContextID retired. Counts the number of instructions + * architecturally executed writing into the ContextID Register + */ +#define XPM_EVENT_CHANGECONTEXT 0x0BU + +/* + * Software change of PC, except by an exception, architecturally executed. + * Count the number of PC changes architecturally executed, excluding the PC + * changes due to taken exceptions + */ +#define XPM_EVENT_SW_CHANGEPC 0x0CU + +/* + * Immediate branch architecturally executed (taken or not taken). This includes + * the branches which are flushed due to a previous load/store which aborts + * late + */ +#define XPM_EVENT_IMMEDBRANCH 0x0DU + +/* + * Unaligned access architecturally executed. Counts the number of aborted + * unaligned accessed architecturally executed, and the number of not-aborted + * unaligned accesses, including the speculative ones + */ +#define XPM_EVENT_UNALIGNEDACCESS 0x0FU + +/* + * Branch mispredicted/not predicted. Counts the number of mispredicted or + * not-predicted branches executed. This includes the branches which are flushed + * due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHMISS 0x10U + +/* + * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This + * event is not exported on the PMUEVENT bus + */ +#define XPM_EVENT_CLOCKCYCLES 0x11U + +/* + * Branches or other change in program flow that could have been predicted by + * the branch prediction resources of the processor. This includes the branches + * which are flushed due to a previous load/store which aborts late + */ +#define XPM_EVENT_BRANCHPREDICT 0x12U + +/* + * Java bytecode execute. Counts the number of Java bytecodes being decoded, + * including speculative ones + */ +#define XPM_EVENT_JAVABYTECODE 0x40U + +/* + * Software Java bytecode executed. Counts the number of software java bytecodes + * being decoded, including speculative ones + */ +#define XPM_EVENT_SWJAVABYTECODE 0x41U + +/* + * Jazelle backward branches executed. Counts the number of Jazelle taken + * branches being executed. This includes the branches which are flushed due + * to a previous load/store which aborts late + */ +#define XPM_EVENT_JAVABACKBRANCH 0x42U + +/* + * Coherent linefill miss Counts the number of coherent linefill requests + * performed by the Cortex-A9 processor which also miss in all the other + * Cortex-A9 processors, meaning that the request is sent to the external + * memory + */ +#define XPM_EVENT_COHERLINEMISS 0x50U + +/* + * Coherent linefill hit. Counts the number of coherent linefill requests + * performed by the Cortex-A9 processor which hit in another Cortex-A9 + * processor, meaning that the linefill data is fetched directly from the + * relevant Cortex-A9 cache + */ +#define XPM_EVENT_COHERLINEHIT 0x51U + +/* + * Instruction cache dependent stall cycles. Counts the number of cycles where + * the processor is ready to accept new instructions, but does not receive any + * due to the instruction side not being able to provide any and the + * instruction cache is currently performing at least one linefill + */ +#define XPM_EVENT_INSTRSTALL 0x60U + +/* + * Data cache dependent stall cycles. Counts the number of cycles where the core + * has some instructions that it cannot issue to any pipeline, and the Load + * Store unit has at least one pending linefill request, and no pending + */ +#define XPM_EVENT_DATASTALL 0x61U + +/* + * Main TLB miss stall cycles. Counts the number of cycles where the processor + * is stalled waiting for the completion of translation table walks from the + * main TLB. The processor stalls can be due to the instruction side not being + * able to provide the instructions, or to the data side not being able to + * provide the necessary data, due to them waiting for the main TLB translation + * table walk to complete + */ +#define XPM_EVENT_MAINTLBSTALL 0x62U + +/* + * Counts the number of STREX instructions architecturally executed and + * passed + */ +#define XPM_EVENT_STREXPASS 0x63U + +/* + * Counts the number of STREX instructions architecturally executed and + * failed + */ +#define XPM_EVENT_STREXFAIL 0x64U + +/* + * Data eviction. Counts the number of eviction requests due to a linefill in + * the data cache + */ +#define XPM_EVENT_DATAEVICT 0x65U + +/* + * Counts the number of cycles where the issue stage does not dispatch any + * instruction because it is empty or cannot dispatch any instructions + */ +#define XPM_EVENT_NODISPATCH 0x66U + +/* + * Counts the number of cycles where the issue stage is empty + */ +#define XPM_EVENT_ISSUEEMPTY 0x67U + +/* + * Counts the number of instructions going through the Register Renaming stage. + * This number is an approximate number of the total number of instructions + * speculatively executed, and even more approximate of the total number of + * instructions architecturally executed. The approximation depends mainly on + * the branch misprediction rate. + * The renaming stage can handle two instructions in the same cycle so the event + * is two bits long: + * - b00 no instructions renamed + * - b01 one instruction renamed + * - b10 two instructions renamed + */ +#define XPM_EVENT_INSTRRENAME 0x68U + +/* + * Counts the number of procedure returns whose condition codes do not fail, + * excluding all returns from exception. This count includes procedure returns + * which are flushed due to a previous load/store which aborts late. + * Only the following instructions are reported: + * - BX R14 + * - MOV PC LR + * - POP {..,pc} + * - LDR pc,[sp],#offset + * The following instructions are not reported: + * - LDMIA R9!,{..,PC} (ThumbEE state only) + * - LDR PC,[R9],#offset (ThumbEE state only) + * - BX R0 (Rm != R14) + * - MOV PC,R0 (Rm != R14) + * - LDM SP,{...,PC} (writeback not specified) + * - LDR PC,[SP,#offset] (wrong addressing mode) + */ +#define XPM_EVENT_PREDICTFUNCRET 0x6EU + +/* + * Counts the number of instructions being executed in the main execution + * pipeline of the processor, the multiply pipeline and arithmetic logic unit + * pipeline. The counted instructions are still speculative + */ +#define XPM_EVENT_MAINEXEC 0x70U + +/* + * Counts the number of instructions being executed in the processor second + * execution pipeline (ALU). The counted instructions are still speculative + */ +#define XPM_EVENT_SECEXEC 0x71U + +/* + * Counts the number of instructions being executed in the Load/Store unit. The + * counted instructions are still speculative + */ +#define XPM_EVENT_LDRSTR 0x72U + +/* + * Counts the number of Floating-point instructions going through the Register + * Rename stage. Instructions are still speculative in this stage. + *Two floating-point instructions can be renamed in the same cycle so the event + * is two bitslong: + *0b00 no floating-point instruction renamed + *0b01 one floating-point instruction renamed + *0b10 two floating-point instructions renamed + */ +#define XPM_EVENT_FLOATRENAME 0x73U + +/* + * Counts the number of Neon instructions going through the Register Rename + * stage.Instructions are still speculative in this stage. + * Two NEON instructions can be renamed in the same cycle so the event is two + * bits long: + *0b00 no NEON instruction renamed + *0b01 one NEON instruction renamed + *0b10 two NEON instructions renamed + */ +#define XPM_EVENT_NEONRENAME 0x74U + +/* + * Counts the number of cycles where the processor is stalled because PLD slots + * are all full + */ +#define XPM_EVENT_PLDSTALL 0x80U + +/* + * Counts the number of cycles when the processor is stalled and the data side + * is stalled too because it is full and executing writes to the external + * memory + */ +#define XPM_EVENT_WRITESTALL 0x81U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the instruction side + */ +#define XPM_EVENT_INSTRTLBSTALL 0x82U + +/* + * Counts the number of stall cycles due to main TLB misses on requests issued + * by the data side + */ +#define XPM_EVENT_DATATLBSTALL 0x83U + +/* + * Counts the number of stall cycles due to micro TLB misses on the instruction + * side. This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_INSTR_uTLBSTALL 0x84U + +/* + * Counts the number of stall cycles due to micro TLB misses on the data side. + * This event does not include main TLB miss stall cycles that are already + * counted in the corresponding main TLB event + */ +#define XPM_EVENT_DATA_uTLBSTALL 0x85U + +/* + * Counts the number of stall cycles because of the execution of a DMB memory + * barrier. This includes all DMB instructions being executed, even + * speculatively + */ +#define XPM_EVENT_DMB_STALL 0x86U + +/* + * Counts the number of cycles during which the integer core clock is enabled + */ +#define XPM_EVENT_INT_CLKEN 0x8AU + +/* + * Counts the number of cycles during which the Data Engine clock is enabled + */ +#define XPM_EVENT_DE_CLKEN 0x8BU + +/* + * Counts the number of ISB instructions architecturally executed + */ +#define XPM_EVENT_INSTRISB 0x90U + +/* + * Counts the number of DSB instructions architecturally executed + */ +#define XPM_EVENT_INSTRDSB 0x91U + +/* + * Counts the number of DMB instructions speculatively executed + */ +#define XPM_EVENT_INSTRDMB 0x92U + +/* + * Counts the number of external interrupts executed by the processor + */ +#define XPM_EVENT_EXTINT 0x93U + +/* + * PLE cache line request completed + */ +#define XPM_EVENT_PLE_LRC 0xA0U + +/* + * PLE cache line request skipped + */ +#define XPM_EVENT_PLE_LRS 0xA1U + +/* + * PLE FIFO flush + */ +#define XPM_EVENT_PLE_FLUSH 0xA2U + +/* + * PLE request complete + */ +#define XPM_EVENT_PLE_CMPL 0xA3U + +/* + * PLE FIFO overflow + */ +#define XPM_EVENT_PLE_OVFL 0xA4U + +/* + * PLE request programmed + */ +#define XPM_EVENT_PLE_PROG 0xA5U + +/* + * The following constants define the configurations for Cortex-A9 Performance + * Monitor Events. Each configuration configures the event counters for a set + * of events. + * ----------------------------------------------- + * Config PmCtr0... PmCtr5 + * ----------------------------------------------- + * XPM_CNTRCFG1 { XPM_EVENT_SOFTINCR, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + * + * XPM_CNTRCFG2 { XPM_EVENT_DATA_READS, + * XPM_EVENT_DATA_WRITE, + * XPM_EVENT_EXCEPTION, + * XPM_EVENT_EXCEPRETURN, + * XPM_EVENT_CHANGECONTEXT, + * XPM_EVENT_SW_CHANGEPC } + * + * XPM_CNTRCFG3 { XPM_EVENT_IMMEDBRANCH, + * XPM_EVENT_UNALIGNEDACCESS, + * XPM_EVENT_BRANCHMISS, + * XPM_EVENT_CLOCKCYCLES, + * XPM_EVENT_BRANCHPREDICT, + * XPM_EVENT_JAVABYTECODE } + * + * XPM_CNTRCFG4 { XPM_EVENT_SWJAVABYTECODE, + * XPM_EVENT_JAVABACKBRANCH, + * XPM_EVENT_COHERLINEMISS, + * XPM_EVENT_COHERLINEHIT, + * XPM_EVENT_INSTRSTALL, + * XPM_EVENT_DATASTALL } + * + * XPM_CNTRCFG5 { XPM_EVENT_MAINTLBSTALL, + * XPM_EVENT_STREXPASS, + * XPM_EVENT_STREXFAIL, + * XPM_EVENT_DATAEVICT, + * XPM_EVENT_NODISPATCH, + * XPM_EVENT_ISSUEEMPTY } + * + * XPM_CNTRCFG6 { XPM_EVENT_INSTRRENAME, + * XPM_EVENT_PREDICTFUNCRET, + * XPM_EVENT_MAINEXEC, + * XPM_EVENT_SECEXEC, + * XPM_EVENT_LDRSTR, + * XPM_EVENT_FLOATRENAME } + * + * XPM_CNTRCFG7 { XPM_EVENT_NEONRENAME, + * XPM_EVENT_PLDSTALL, + * XPM_EVENT_WRITESTALL, + * XPM_EVENT_INSTRTLBSTALL, + * XPM_EVENT_DATATLBSTALL, + * XPM_EVENT_INSTR_uTLBSTALL } + * + * XPM_CNTRCFG8 { XPM_EVENT_DATA_uTLBSTALL, + * XPM_EVENT_DMB_STALL, + * XPM_EVENT_INT_CLKEN, + * XPM_EVENT_DE_CLKEN, + * XPM_EVENT_INSTRISB, + * XPM_EVENT_INSTRDSB } + * + * XPM_CNTRCFG9 { XPM_EVENT_INSTRDMB, + * XPM_EVENT_EXTINT, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG10 { XPM_EVENT_PLE_OVFL, + * XPM_EVENT_PLE_PROG, + * XPM_EVENT_PLE_LRC, + * XPM_EVENT_PLE_LRS, + * XPM_EVENT_PLE_FLUSH, + * XPM_EVENT_PLE_CMPL } + * + * XPM_CNTRCFG11 { XPM_EVENT_DATASTALL, + * XPM_EVENT_INSRFETCH_CACHEREFILL, + * XPM_EVENT_INSTRFECT_TLBREFILL, + * XPM_EVENT_DATA_CACHEREFILL, + * XPM_EVENT_DATA_CACHEACCESS, + * XPM_EVENT_DATA_TLBREFILL } + */ +#define XPM_CNTRCFG1 0 +#define XPM_CNTRCFG2 1 +#define XPM_CNTRCFG3 2 +#define XPM_CNTRCFG4 3 +#define XPM_CNTRCFG5 4 +#define XPM_CNTRCFG6 5 +#define XPM_CNTRCFG7 6 +#define XPM_CNTRCFG8 7 +#define XPM_CNTRCFG9 8 +#define XPM_CNTRCFG10 9 +#define XPM_CNTRCFG11 10 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/* Interface fuctions to access perfromance counters from abstraction layer */ +void Xpm_SetEvents(s32 PmcrCfg); +void Xpm_GetEventCounters(u32 *PmCtrValue); + +#ifdef __cplusplus +} +#endif + +#endif +/** +* @} End of "addtogroup a9_event_counter_apis". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm.h new file mode 100644 index 0000000..4ad9e5d --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm.h @@ -0,0 +1,77 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm.h +* +* @addtogroup a9_specific Cortex A9 Processor Specific Include Files +* +* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h. +* +* The xreg_cortexa9.h file contains definitions for inline assembler code. +* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers, +* co-processor registers and Debug registers. +* +* The xpseudo_asm_gcc.h contains the definitions for the most often used inline +* assembler instructions, available as macros. These can be very useful for +* tasks such as setting or getting special purpose registers, synchronization, +* or cache manipulation etc. These inline assembler instructions can be used +* from drivers and user applications written in C. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+*
    +* +******************************************************************************/ +#ifndef XPSEUDO_ASM_H +#define XPSEUDO_ASM_H + +#include "xreg_cortexa9.h" +#ifdef __GNUC__ + #include "xpseudo_asm_gcc.h" +#elif defined (__ICCARM__) + #include "xpseudo_asm_iccarm.h" +#else + #include "xpseudo_asm_rvct.h" +#endif + +#endif /* XPSEUDO_ASM_H */ +/** +* @} End of "addtogroup a9_specific". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h new file mode 100644 index 0000000..37971bc --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h @@ -0,0 +1,256 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xpseudo_asm_gcc.h +* +* This header file contains macros for using inline assembler code. It is +* written specifically for the GNU compiler. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
+*
    +* +******************************************************************************/ + +#ifndef XPSEUDO_ASM_GCC_H /* prevent circular inclusions */ +#define XPSEUDO_ASM_GCC_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* necessary for pre-processor */ +#define stringify(s) tostring(s) +#define tostring(s) #s + +#if defined (__aarch64__) +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define mfelrel3() ({u64 rval = 0U; \ + asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ + rval;\ + }) + +#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v)) + +#else + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) + +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") + +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) + +#define mfgpr(rn) ({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb" : : : "memory") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__ ("dsb" : : : "memory") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__ ("dmb" : : : "memory") + + +/* Memory Operations */ +#define ldr(adr) ({u32 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#endif + +#define ldrb(adr) ({u8 rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) + +/* Count leading zeroes (clz) */ +#define clz(arg) ({u8 rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) + +#if defined (__aarch64__) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) + +#else +/* CP15 operations */ +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); + +#define mfcp(rn) ({u32 rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) +#endif + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XPSEUDO_ASM_GCC_H */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips.h new file mode 100644 index 0000000..139ce4d --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips.h @@ -0,0 +1,799 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspips.h +* @addtogroup qspips_v3_4 +* @{ +* @details +* +* This file contains the implementation of the XQspiPs driver. It supports only +* master mode. User documentation for the driver functions is contained in this +* file in the form of comment blocks at the front of each function. +* +* A QSPI device connects to an QSPI bus through a 4-wire serial interface. +* The QSPI bus is a full-duplex, synchronous bus that facilitates communication +* between one master and one slave. The device is always full-duplex, +* which means that for every byte sent, one is received, and vice-versa. +* The master controls the clock, so it can regulate when it wants to +* send or receive data. The slave is under control of the master, it must +* respond quickly since it has no control of the clock and must send/receive +* data as fast or as slow as the master does. +* +* Linear Mode +* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s +* functionality by adding a linear addressing scheme that allows the SPI flash +* memory subsystem to behave like a typical ROM device. The new feature hides +* the normal SPI protocol from a master reading from the SPI flash memory. The +* feature improves both the user friendliness and the overall read memory +* throughput over that of the current Quad-SPI Controller by lessening the +* amount of software overheads required and by the use of the faster AXI +* interface. +* +* Initialization & Configuration +* +* The XQspiPs_Config structure is used by the driver to configure itself. This +* configuration structure is typically created by the tool-chain based on HW +* build properties. +* +* To support multiple runtime loading and initialization strategies employed by +* various operating systems, the driver instance can be initialized in the +* following way: +* - XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find +* static configuration structure defined in xqspips_g.c. This is setup +* by the tools. For some operating systems the config structure will be +* initialized by the software and this call is not needed. +* - XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the provided virtual memory base address +* replaces the physical address present in the configuration structure. +* +* Multiple Masters +* +* More than one master can exist, but arbitration is the responsibility of +* the higher layer software. The device driver does not perform any type of +* arbitration. +* +* Modes of Operation +* +* There are four modes to perform a data transfer and the selection of a mode +* is based on Chip Select(CS) and Start. These two options individually, can +* be controlled either by software(Manual) or hardware(Auto). +* - Auto CS: Chip select is automatically asserted as soon as the first word +* is written into the TXFIFO and de asserted when the TXFIFO becomes +* empty +* - Manual CS: Software must assert and de assert CS. +* - Auto Start: Data transmission starts as soon as there is data in the +* TXFIFO and stalls when the TXFIFO is empty +* - Manual Start: Software must start data transmission at the beginning of +* the transaction or whenever the TXFIFO has become empty +* +* The preferred combination is Manual CS and Auto Start. +* In this combination, the software asserts CS before loading any data into +* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it +* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the +* data is available. If no further data, software disables CS. +* +* Risks/challenges of other combinations: +* - Manual CS and Manual Start: Manual Start bit should be set after each +* TXFIFO write otherwise there could be a race condition where the TXFIFO +* becomes empty before the new word is written. In that case the +* transmission stops. +* - Auto CS with Manual or Auto Start: It is very difficult for software to +* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted. +* This results in a single transaction to be split into multiple pieces each +* with its own chip select. This will result in garbage data to be sent. +* +* Interrupts +* +* The user must connect the interrupt handler of the driver, +* XQspiPs_InterruptHandler, to an interrupt system such that it will be +* called when an interrupt occurs. This function does not save and restore +* the processor context such that the user must provide this processing. +* +* The driver handles the following interrupts: +* - Data Transmit Register/FIFO Underflow +* - Data Receive Register/FIFO Not Empty +* - Data Transmit Register/FIFO Overwater +* - Data Receive Register/FIFO Overrun +* +* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the +* QSPI device has transmitted the data available to transmit, and now its data +* register and FIFO is ready to accept more data. The driver uses this +* interrupt to indicate progress while sending data. The driver may have +* more data to send, in which case the data transmit register and FIFO is +* filled for subsequent transmission. When this interrupt arrives and all +* the data has been sent, the driver invokes the status callback with a +* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that +* all data has been sent. +* +* The Data Transmit Register/FIFO Underflow interrupt -- indicates that, +* as slave, the QSPI device was required to transmit but there was no data +* available to transmit in the transmit register (or FIFO). This may not +* be an error if the master is not expecting data. But in the case where +* the master is expecting data, this serves as a notification of such a +* condition. The driver reports this condition to the upper layer +* software through the status handler. +* +* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI +* device received data and subsequently dropped the data because the data +* receive register and FIFO was full. The driver reports this condition to the +* upper layer software through the status handler. This likely indicates a +* problem with the higher layer protocol, or a problem with the slave +* performance. +* +* +* Polled Operation +* +* Transfer in polled mode is supported through a separate interface function +* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode, +* this function blocks until all data has been sent/received. +* +* Device Busy +* +* Some operations are disallowed when the device is busy. The driver tracks +* whether a device is busy. The device is considered busy when a data transfer +* request is outstanding, and is considered not busy only when that transfer +* completes (or is aborted with a mode fault error). +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xqspips_g.c file or +* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry +* contains configuration information for an QSPI device, including the base +* address for the device. +* +* RTOS Independence +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads or +* thread mutual exclusion, virtual memory, or cache control must be satisfied +* by the layer above this driver. +* +* NOTE: This driver was always tested with endianess set to little-endian. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+*		     in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* 		     Removed code related to mode fault for CR 671468
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added a flag ShiftReadData to the instance structure
+*.		     and is used in the XQspiPs_GetReadData API.
+*		     The ShiftReadData Flag indicates whether the data
+*		     read from the Rx FIFO needs to be shifted
+*		     in cases where the data is less than 4  bytes
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     This version of the driver fixes CRs 670197/663787/
+*		     670297/671468.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Added macros for Set/Get Rx Watermark. Changed QSPI
+*		     Enable/Disable macro argument from BaseAddress to
+*		     Instance Pointer. Added DelayNss argument to SetDelays
+*		     and GetDelays API's.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*		     SetDelays and GetDelays API's include DelayNss parameter.
+*		     Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register. Renamed Fixed burst error to
+*		     data FSM error in  LQSPI Status register.
+*
+* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
+*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+*			 Added enable and disable to the XQspiPs_LqspiRead() function
+*			 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set.
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added prefix to constant definitions for ConnectionMode
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added API's for QSPI reset and
+*                    linear mode initialization for boot.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*                    Updated linear init API for parallel and stacked modes.
+*                    CR#737760.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*       ms  04/05/17 Modified Comment lines in functions of qspips
+*                    examples to recognize it as documentation block
+*                    and modified filename tag in
+*                    xqspips_dual_flash_stack_lqspi_example.c to include it in
+*                    doxygen examples.
+* 3.4   nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+*
+*
    +* +******************************************************************************/ +#ifndef XQSPIPS_H /* prevent circular inclusions */ +#define XQSPIPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xqspips_hw.h" +#include + +/************************** Constant Definitions *****************************/ + +/** @name Configuration options + * + * The following options are supported to enable/disable certain features of + * an QSPI device. Each of the options is a bit mask, so more than one may be + * specified. + * + * + * The Active Low Clock option configures the device's clock polarity. + * Setting this option means the clock is active low and the SCK signal idles + * high. By default, the clock is active high and SCK idles low. + * + * The Clock Phase option configures the QSPI device for one of two + * transfer formats. A clock phase of 0, the default, means data is valid on + * the first SCK edge (rising or falling) after the slave select (SS) signal + * has been asserted. A clock phase of 1 means data is valid on the second SCK + * edge (rising or falling) after SS has been asserted. + * + * + * The QSPI Force Slave Select option is used to enable manual control of + * the slave select signal. + * 0: The SPI_SS signal is controlled by the QSPI controller during + * transfers. (Default) + * 1: The SPI_SS signal is forced active (driven low) regardless of any + * transfers in progress. + * + * NOTE: The driver will handle setting and clearing the Slave Select when + * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the + * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the + * processor cannot empty and refill the FIFOs before the TX FIFO is empty + * When the QSPI hardware is controlling the Slave Select signals, this + * will cause slave to be de-selected and terminate the transfer. + * + * The Manual Start option is used to enable manual control of + * the Start command to perform data transfer. + * 0: The Start command is controlled by the QSPI controller during + * transfers(Default). Data transmission starts as soon as there is data in + * the TXFIFO and stalls when the TXFIFO is empty + * 1: The Start command must be issued by software to perform data transfer. + * Bit 15 of Configuration register is used to issue Start command. This bit + * must be set whenever TXFIFO is filled with new data. + * + * NOTE: The driver will set the Manual Start Enable bit in Configuration + * Register, if Manual Start option is selected. Software will issue + * Manual Start command whenever TXFIFO is filled with data. When there is + * no further data, driver will clear the Manual Start Enable bit. + * + * @{ + */ +#define XQSPIPS_CLK_ACTIVE_LOW_OPTION 0x2 /**< Active Low Clock option */ +#define XQSPIPS_CLK_PHASE_1_OPTION 0x4 /**< Clock Phase one option */ +#define XQSPIPS_FORCE_SSELECT_OPTION 0x10 /**< Force Slave Select */ +#define XQSPIPS_MANUAL_START_OPTION 0x20 /**< Manual Start enable */ +#define XQSPIPS_LQSPI_MODE_OPTION 0x80 /**< Linear QPSI mode */ +#define XQSPIPS_HOLD_B_DRIVE_OPTION 0x100 /**< Drive HOLD_B Pin */ +/*@}*/ + + +/** @name QSPI Clock Prescaler options + * The QSPI Clock Prescaler Configuration bits are used to program master mode + * bit rate. The bit rate can be programmed in divide-by-two decrements from + * pclk/2 to pclk/256. + * + * @{ + */ +#define XQSPIPS_CLK_PRESCALE_2 0x00 /**< PCLK/2 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_4 0x01 /**< PCLK/4 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_8 0x02 /**< PCLK/8 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_16 0x03 /**< PCLK/16 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_32 0x04 /**< PCLK/32 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_64 0x05 /**< PCLK/64 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_128 0x06 /**< PCLK/128 Prescaler */ +#define XQSPIPS_CLK_PRESCALE_256 0x07 /**< PCLK/256 Prescaler */ + +/*@}*/ + + +/** @name Callback events + * + * These constants specify the handler events that are passed to + * a handler from the driver. These constants are not bit masks such that + * only one will be passed at a time to the handler. + * + * @{ + */ +#define XQSPIPS_EVENT_TRANSFER_DONE 2 /**< Transfer done */ +#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */ +#define XQSPIPS_EVENT_RECEIVE_OVERRUN 4 /**< Receive data loss because + RX FIFO full */ +/*@}*/ + +/** @name Flash commands + * + * The following constants define most of the commands supported by flash + * devices. Users can add more commands supported by the flash devices + * + * @{ + */ +#define XQSPIPS_FLASH_OPCODE_WRSR 0x01 /* Write status register */ +#define XQSPIPS_FLASH_OPCODE_PP 0x02 /* Page program */ +#define XQSPIPS_FLASH_OPCODE_NORM_READ 0x03 /* Normal read data bytes */ +#define XQSPIPS_FLASH_OPCODE_WRDS 0x04 /* Write disable */ +#define XQSPIPS_FLASH_OPCODE_RDSR1 0x05 /* Read status register 1 */ +#define XQSPIPS_FLASH_OPCODE_WREN 0x06 /* Write enable */ +#define XQSPIPS_FLASH_OPCODE_FAST_READ 0x0B /* Fast read data bytes */ +#define XQSPIPS_FLASH_OPCODE_BE_4K 0x20 /* Erase 4KiB block */ +#define XQSPIPS_FLASH_OPCODE_RDSR2 0x35 /* Read status register 2 */ +#define XQSPIPS_FLASH_OPCODE_DUAL_READ 0x3B /* Dual read data bytes */ +#define XQSPIPS_FLASH_OPCODE_BE_32K 0x52 /* Erase 32KiB block */ +#define XQSPIPS_FLASH_OPCODE_QUAD_READ 0x6B /* Quad read data bytes */ +#define XQSPIPS_FLASH_OPCODE_ERASE_SUS 0x75 /* Erase suspend */ +#define XQSPIPS_FLASH_OPCODE_ERASE_RES 0x7A /* Erase resume */ +#define XQSPIPS_FLASH_OPCODE_RDID 0x9F /* Read JEDEC ID */ +#define XQSPIPS_FLASH_OPCODE_BE 0xC7 /* Erase whole flash block */ +#define XQSPIPS_FLASH_OPCODE_SE 0xD8 /* Sector erase (usually 64KB)*/ +#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */ +#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */ +#define XQSPIPS_FLASH_OPCODE_BRWR 0x17 /* Bank Register Write */ +#define XQSPIPS_FLASH_OPCODE_BRRD 0x16 /* Bank Register Read */ +/* Extende Address Register Write - Micron's equivalent of Bank Register */ +#define XQSPIPS_FLASH_OPCODE_EARWR 0xC5 +/* Extende Address Register Read - Micron's equivalent of Bank Register */ +#define XQSPIPS_FLASH_OPCODE_EARRD 0xC8 +#define XQSPIPS_FLASH_OPCODE_DIE_ERASE 0xC4 +#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR 0x70 +#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR 0x50 +#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG 0xE8 /* Lock register Read */ +#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG 0xE5 /* Lock Register Write */ + +/*@}*/ + +/** @name Instruction size + * + * The following constants define numbers 1 to 4. + * Used to identify whether TXD0,1,2 or 3 is to be used. + * + * @{ + */ +#define XQSPIPS_SIZE_ONE 1 +#define XQSPIPS_SIZE_TWO 2 +#define XQSPIPS_SIZE_THREE 3 +#define XQSPIPS_SIZE_FOUR 4 + +/*@}*/ + +/** @name ConnectionMode + * + * The following constants are the possible values of ConnectionMode in + * Config structure. + * + * @{ + */ +#define XQSPIPS_CONNECTION_MODE_SINGLE 0 +#define XQSPIPS_CONNECTION_MODE_STACKED 1 +#define XQSPIPS_CONNECTION_MODE_PARALLEL 2 + +/*@}*/ + +/** @name FIFO threshold value + * + * This is the Rx FIFO threshold (in words) that was found to be most + * optimal in terms of performance + * + * @{ + */ +#define XQSPIPS_RXFIFO_THRESHOLD_OPT 32 + +/*@}*/ + +/**************************** Type Definitions *******************************/ +/** + * The handler data type allows the user to define a callback function to + * handle the asynchronous processing for the QSPI device. The application + * using this driver is expected to define a handler of this type to support + * interrupt driven mode. The handler executes in an interrupt context, so + * only minimal processing should be performed. + * + * @param CallBackRef is the callback reference passed in by the upper + * layer when setting the callback functions, and passed back to + * the upper layer when the callback is invoked. Its type is + * not important to the driver, so it is a void pointer. + * @param StatusEvent holds one or more status events that have occurred. + * See the XQspiPs_SetStatusHandler() for details on the status + * events that can be passed in the callback. + * @param ByteCount indicates how many bytes of data were successfully + * transferred. This may be less than the number of bytes + * requested if the status event indicates an error. + */ +typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent, + unsigned ByteCount); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ +} XQspiPs_Config; + +/** + * The XQspiPs driver instance data. The user is required to allocate a + * variable of this type for every QSPI device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XQspiPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + + u8 *SendBufferPtr; /**< Buffer to send (state) */ + u8 *RecvBufferPtr; /**< Buffer to receive (state) */ + int RequestedBytes; /**< Number of bytes to transfer (state) */ + int RemainingBytes; /**< Number of bytes left to transfer(state) */ + u32 IsBusy; /**< A transfer is in progress (state) */ + XQspiPs_StatusHandler StatusHandler; + void *StatusRef; /**< Callback reference for status handler */ + u32 ShiftReadData; /**< Flag to indicate whether the data + * read from the Rx FIFO needs to be shifted + * in cases where the data is less than 4 + * bytes + */ +} XQspiPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Manual Start Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr); +* +*****************************************************************************/ +#define XQspiPs_IsManualStart(InstancePtr) \ + ((XQspiPs_GetOptions(InstancePtr) & \ + XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE) + +/****************************************************************************/ +/* +* +* Check in OptionsTable if Manual Chip Select Option is enabled or disabled. +* +* @param InstancePtr is a pointer to the XSpiPs instance. +* +* @return +* - TRUE if option is set +* - FALSE if option is not set +* +* @note C-Style signature: +* u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr); +* +*****************************************************************************/ +#define XQspiPs_IsManualChipSelect(InstancePtr) \ + ((XQspiPs_GetOptions(InstancePtr) & \ + XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* Set the contents of the slave idle count register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are +* 0-255. +* +* @return None +* +* @note +* C-Style signature: +* void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_SICR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_* +* constants defined in xqspips_hw.h to interpret the bit-mask returned. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return An 8-bit value representing Slave Idle Count. +* +* @note C-Style signature: +* u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetSlaveIdle(InstancePtr) \ + XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_SICR_OFFSET) + +/****************************************************************************/ +/** +* +* Set the contents of the transmit FIFO watermark register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are 1-63. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_TXWR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the transmit FIFO watermark register. +* Valid values are in the range 1-63. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 6-bit value representing Tx Watermark level. +* +* @note C-Style signature: +* u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetTXWatermark(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET) + +/****************************************************************************/ +/** +* +* Set the contents of the receive FIFO watermark register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written, valid values are 1-63. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_RXWR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the receive FIFO watermark register. +* Valid values are in the range 1-63. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 6-bit value representing Rx Watermark level. +* +* @note C-Style signature: +* u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetRXWatermark(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET) + +/****************************************************************************/ +/** +* +* Enable the device and uninhibit master transactions. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_Enable(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_Enable(InstancePtr) \ + XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \ + XQSPIPS_ER_ENABLE_MASK) + +/****************************************************************************/ +/** +* +* Disable the device. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_Disable(XQspiPs *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_Disable(InstancePtr) \ + XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0) + +/****************************************************************************/ +/** +* +* Set the contents of the Linear QSPI Configuration register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* @param RegisterValue is the value to be written to the Linear QSPI +* configuration register. +* +* @return None. +* +* @note +* C-Style signature: +* void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr, +* u32 RegisterValue) +* +*****************************************************************************/ +#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue) \ + XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + \ + XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue)) + +/****************************************************************************/ +/** +* +* Get the contents of the Linear QSPI Configuration register. +* +* @param InstancePtr is a pointer to the XQspiPs instance. +* +* @return A 32-bit value representing the contents of the LQSPI Config +* register. +* +* @note C-Style signature: +* u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr) +* +*****************************************************************************/ +#define XQspiPs_GetLqspiConfigReg(InstancePtr) \ + XQspiPs_In32((InstancePtr->Config.BaseAddress) + \ + XQSPIPS_LQSPI_CR_OFFSET) + +/************************** Function Prototypes ******************************/ + +/* + * Initialization function, implemented in xqspips_sinit.c + */ +XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId); + +/* + * Functions implemented in xqspips.c + */ +int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config, + u32 EffectiveAddr); +void XQspiPs_Reset(XQspiPs *InstancePtr); +void XQspiPs_Abort(XQspiPs *InstancePtr); + +s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, + u32 ByteCount); +s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr, + u8 *RecvBufPtr, u32 ByteCount); +int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr, + u32 Address, unsigned ByteCount); + +int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr); + +void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef, + XQspiPs_StatusHandler FuncPtr); +void XQspiPs_InterruptHandler(void *InstancePtr); + +/* + * Functions for selftest, in xqspips_selftest.c + */ +int XQspiPs_SelfTest(XQspiPs *InstancePtr); + +/* + * Functions for options, in xqspips_options.c + */ +s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options); +u32 XQspiPs_GetOptions(XQspiPs *InstancePtr); + +s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler); +u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr); + +int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn, + u8 DelayAfter, u8 DelayInit); +void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn, + u8 *DelayAfter, u8 *DelayInit); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips_hw.h new file mode 100644 index 0000000..96c867a --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xqspips_hw.h @@ -0,0 +1,423 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xqspips_hw.h +* @addtogroup qspips_v3_4 +* @{ +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xqspips.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a ka  07/25/12 Added a few register defines for CR 670297
+*		     and removed some defines of reserved fields for
+*		     CR 671468
+*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+*		     bit in Configuration register.
+* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register.
+* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
+*                    linear mode initialization for boot. Added related
+*                    constant definitions.
+* 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+*
+*
    +* +******************************************************************************/ +#ifndef XQSPIPS_HW_H /* prevent circular inclusions */ +#define XQSPIPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an QSPI device. + * @{ + */ +#define XQSPIPS_CR_OFFSET 0x00 /**< Configuration Register */ +#define XQSPIPS_SR_OFFSET 0x04 /**< Interrupt Status */ +#define XQSPIPS_IER_OFFSET 0x08 /**< Interrupt Enable */ +#define XQSPIPS_IDR_OFFSET 0x0c /**< Interrupt Disable */ +#define XQSPIPS_IMR_OFFSET 0x10 /**< Interrupt Enabled Mask */ +#define XQSPIPS_ER_OFFSET 0x14 /**< Enable/Disable Register */ +#define XQSPIPS_DR_OFFSET 0x18 /**< Delay Register */ +#define XQSPIPS_TXD_00_OFFSET 0x1C /**< Transmit 4-byte inst/data */ +#define XQSPIPS_RXD_OFFSET 0x20 /**< Data Receive Register */ +#define XQSPIPS_SICR_OFFSET 0x24 /**< Slave Idle Count */ +#define XQSPIPS_TXWR_OFFSET 0x28 /**< Transmit FIFO Watermark */ +#define XQSPIPS_RXWR_OFFSET 0x2C /**< Receive FIFO Watermark */ +#define XQSPIPS_GPIO_OFFSET 0x30 /**< GPIO Register */ +#define XQSPIPS_LPBK_DLY_ADJ_OFFSET 0x38 /**< Loopback Delay Adjust Reg */ +#define XQSPIPS_TXD_01_OFFSET 0x80 /**< Transmit 1-byte inst */ +#define XQSPIPS_TXD_10_OFFSET 0x84 /**< Transmit 2-byte inst */ +#define XQSPIPS_TXD_11_OFFSET 0x88 /**< Transmit 3-byte inst */ +#define XQSPIPS_LQSPI_CR_OFFSET 0xA0 /**< Linear QSPI config register */ +#define XQSPIPS_LQSPI_SR_OFFSET 0xA4 /**< Linear QSPI status register */ +#define XQSPIPS_MOD_ID_OFFSET 0xFC /**< Module ID register */ + +/* @} */ + +/** @name Configuration Register + * + * This register contains various control bits that + * affect the operation of the QSPI device. Read/Write. + * @{ + */ + +#define XQSPIPS_CR_IFMODE_MASK 0x80000000 /**< Flash mem interface mode */ +#define XQSPIPS_CR_ENDIAN_MASK 0x04000000 /**< Tx/Rx FIFO endianness */ +#define XQSPIPS_CR_MANSTRT_MASK 0x00010000 /**< Manual Transmission Start */ +#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start + Enable */ +#define XQSPIPS_CR_SSFORCE_MASK 0x00004000 /**< Force Slave Select */ +#define XQSPIPS_CR_SSCTRL_MASK 0x00000400 /**< Slave Select Decode */ +#define XQSPIPS_CR_SSCTRL_SHIFT 10 /**< Slave Select Decode shift */ +#define XQSPIPS_CR_DATA_SZ_MASK 0x000000C0 /**< Size of word to be + transferred */ +#define XQSPIPS_CR_PRESC_MASK 0x00000038 /**< Prescaler Setting */ +#define XQSPIPS_CR_PRESC_SHIFT 3 /**< Prescaler shift */ +#define XQSPIPS_CR_PRESC_MAXIMUM 0x07 /**< Prescaler maximum value */ + +#define XQSPIPS_CR_CPHA_MASK 0x00000004 /**< Phase Configuration */ +#define XQSPIPS_CR_CPOL_MASK 0x00000002 /**< Polarity Configuration */ + +#define XQSPIPS_CR_MSTREN_MASK 0x00000001 /**< Master Mode Enable */ + +#define XQSPIPS_CR_HOLD_B_MASK 0x00080000 /**< HOLD_B Pin Drive Enable */ + +#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */ + +/* Deselect the Slave select line and set the transfer size to 32 at reset */ +#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \ + XQSPIPS_CR_SSCTRL_MASK | \ + XQSPIPS_CR_DATA_SZ_MASK | \ + XQSPIPS_CR_MSTREN_MASK | \ + XQSPIPS_CR_SSFORCE_MASK | \ + XQSPIPS_CR_HOLD_B_MASK +#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \ + XQSPIPS_CR_CPHA_MASK | \ + XQSPIPS_CR_PRESC_MASK | \ + XQSPIPS_CR_MANSTRTEN_MASK | \ + XQSPIPS_CR_MANSTRT_MASK | \ + XQSPIPS_CR_ENDIAN_MASK | \ + XQSPIPS_CR_REF_CLK_MASK +/* @} */ + + +/** @name QSPI Interrupt Registers + * + * QSPI Status Register + * + * This register holds the interrupt status flags for an QSPI device. Some + * of the flags are level triggered, which means that they are set as long + * as the interrupt condition exists. Other flags are edge triggered, + * which means they are set once the interrupt condition occurs and remain + * set until they are cleared by software. The interrupts are cleared by + * writing a '1' to the interrupt bit position in the Status Register. + * Read/Write. + * + * QSPI Interrupt Enable Register + * + * This register is used to enable chosen interrupts for an QSPI device. + * Writing a '1' to a bit in this register sets the corresponding bit in the + * QSPI Interrupt Mask register. Write only. + * + * QSPI Interrupt Disable Register + * + * This register is used to disable chosen interrupts for an QSPI device. + * Writing a '1' to a bit in this register clears the corresponding bit in the + * QSPI Interrupt Mask register. Write only. + * + * QSPI Interrupt Mask Register + * + * This register shows the enabled/disabled interrupts of an QSPI device. + * Read only. + * + * All four registers have the same bit definitions. They are only defined once + * for each of the Interrupt Enable Register, Interrupt Disable Register, + * Interrupt Mask Register, and Channel Interrupt Status Register + * @{ + */ + +#define XQSPIPS_IXR_TXUF_MASK 0x00000040 /**< QSPI Tx FIFO Underflow */ +#define XQSPIPS_IXR_RXFULL_MASK 0x00000020 /**< QSPI Rx FIFO Full */ +#define XQSPIPS_IXR_RXNEMPTY_MASK 0x00000010 /**< QSPI Rx FIFO Not Empty */ +#define XQSPIPS_IXR_TXFULL_MASK 0x00000008 /**< QSPI Tx FIFO Full */ +#define XQSPIPS_IXR_TXOW_MASK 0x00000004 /**< QSPI Tx FIFO Overwater */ +#define XQSPIPS_IXR_RXOVR_MASK 0x00000001 /**< QSPI Rx FIFO Overrun */ +#define XQSPIPS_IXR_DFLT_MASK 0x00000025 /**< QSPI default interrupts + mask */ +#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041 /**< Interrupts which + need write to clear */ +#define XQSPIPS_ISR_RESET_STATE 0x00000004 /**< Default to tx/rx empty */ +#define XQSPIPS_IXR_DISABLE_ALL 0x0000007D /**< Disable all interrupts */ +/* @} */ + + +/** @name Enable Register + * + * This register is used to enable or disable an QSPI device. + * Read/Write + * @{ + */ +#define XQSPIPS_ER_ENABLE_MASK 0x00000001 /**< QSPI Enable Bit Mask */ +/* @} */ + + +/** @name Delay Register + * + * This register is used to program timing delays in + * slave mode. Read/Write + * @{ + */ +#define XQSPIPS_DR_NSS_MASK 0xFF000000 /**< Delay to de-assert slave select + between two words mask */ +#define XQSPIPS_DR_NSS_SHIFT 24 /**< Delay to de-assert slave select + between two words shift */ +#define XQSPIPS_DR_BTWN_MASK 0x00FF0000 /**< Delay Between Transfers + mask */ +#define XQSPIPS_DR_BTWN_SHIFT 16 /**< Delay Between Transfers shift */ +#define XQSPIPS_DR_AFTER_MASK 0x0000FF00 /**< Delay After Transfers mask */ +#define XQSPIPS_DR_AFTER_SHIFT 8 /**< Delay After Transfers shift */ +#define XQSPIPS_DR_INIT_MASK 0x000000FF /**< Delay Initially mask */ +/* @} */ + +/** @name Slave Idle Count Registers + * + * This register defines the number of pclk cycles the slave waits for a the + * QSPI clock to become stable in quiescent state before it can detect the start + * of the next transfer in CPHA = 1 mode. + * Read/Write + * + * @{ + */ +#define XQSPIPS_SICR_MASK 0x000000FF /**< Slave Idle Count Mask */ +/* @} */ + + +/** @name Transmit FIFO Watermark Register + * + * This register defines the watermark setting for the Transmit FIFO. + * + * @{ + */ +#define XQSPIPS_TXWR_MASK 0x0000003F /**< Transmit Watermark Mask */ +#define XQSPIPS_TXWR_RESET_VALUE 0x00000001 /**< Transmit Watermark + * register reset value */ + +/* @} */ + +/** @name Receive FIFO Watermark Register + * + * This register defines the watermark setting for the Receive FIFO. + * + * @{ + */ +#define XQSPIPS_RXWR_MASK 0x0000003F /**< Receive Watermark Mask */ +#define XQSPIPS_RXWR_RESET_VALUE 0x00000001 /**< Receive Watermark + * register reset value */ + +/* @} */ + +/** @name FIFO Depth + * + * This macro provides the depth of transmit FIFO and receive FIFO. + * + * @{ + */ +#define XQSPIPS_FIFO_DEPTH 63 /**< FIFO depth (words) */ +/* @} */ + + +/** @name Linear QSPI Configuration Register + * + * This register contains various control bits that + * affect the operation of the Linear QSPI controller. Read/Write. + * + * @{ + */ +#define XQSPIPS_LQSPI_CR_LINEAR_MASK 0x80000000 /**< LQSPI mode enable */ +#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK 0x40000000 /**< Both memories or one */ +#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK 0x20000000 /**< Seperate memory bus */ +#define XQSPIPS_LQSPI_CR_U_PAGE_MASK 0x10000000 /**< Upper memory page */ +#define XQSPIPS_LQSPI_CR_MODE_EN_MASK 0x02000000 /**< Enable mode bits */ +#define XQSPIPS_LQSPI_CR_MODE_ON_MASK 0x01000000 /**< Mode on */ +#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK 0x00FF0000 /**< Mode value for dual I/O + or quad I/O */ +#define XQSPIPS_LQSPI_CR_DUMMY_MASK 0x00000700 /**< Number of dummy bytes + between addr and return + read data */ +#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ +#define XQSPIPS_LQSPI_CR_RST_STATE 0x8000016B /**< Default CR value */ +/* @} */ + +/** @name Linear QSPI Status Register + * + * This register contains various status bits of the Linear QSPI controller. + * Read/Write. + * + * @{ + */ +#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK 0x00000004 /**< AXI Data FSM Error + received */ +#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK 0x00000002 /**< AXI write command + received */ +/* @} */ + + +/** @name Loopback Delay Adjust Register + * + * This register contains various bit masks of Loopback Delay Adjust Register. + * + * @{ + */ + +#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */ + +/* @} */ + + +/** @name SLCR Register + * + * Register offsets from SLCR base address. + * + * @{ + */ + +#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */ +#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */ +#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */ +#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */ + +/* @} */ + + +/** @name SLCR Register + * + * Bit Masks of above SLCR Registers . + * + * @{ + */ + +#ifndef XPAR_XSLCR_0_BASEADDR +#define XPAR_XSLCR_0_BASEADDR 0xF8000000 +#endif +#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/ +#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */ +#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */ + +/* @} */ + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XQspiPs_In32 Xil_In32 +#define XQspiPs_Out32 Xil_Out32 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XQspiPs_ReadReg(BaseAddress, RegOffset) \ + XQspiPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/************************** Function Prototypes ******************************/ + +/* + * Functions implemented in xqspips_hw.c + */ +void XQspiPs_ResetHw(u32 BaseAddress); +void XQspiPs_LinearInit(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h new file mode 100644 index 0000000..dc9a4eb --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h @@ -0,0 +1,591 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xreg_cortexa9.h +* +* This header file contains definitions for using inline assembler code. It is +* written specifically for the GNU, ARMCC compiler. +* +* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along +* with the positions of the bits within the registers. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+*
    +* +******************************************************************************/ +#ifndef XREG_CORTEXA9_H +#define XREG_CORTEXA9_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* GPRs */ +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr + +/* Coprocessor number defines */ +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 + +/* Coprocessor control register defines */ +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 + +/* Current Processor Status Register (CPSR) Bits */ +#define XREG_CPSR_THUMB_MODE 0x20 +#define XREG_CPSR_MODE_BITS 0x1F +#define XREG_CPSR_SYSTEM_MODE 0x1F +#define XREG_CPSR_UNDEFINED_MODE 0x1B +#define XREG_CPSR_DATA_ABORT_MODE 0x17 +#define XREG_CPSR_SVC_MODE 0x13 +#define XREG_CPSR_IRQ_MODE 0x12 +#define XREG_CPSR_FIQ_MODE 0x11 +#define XREG_CPSR_USER_MODE 0x10 + +#define XREG_CPSR_IRQ_ENABLE 0x80 +#define XREG_CPSR_FIQ_ENABLE 0x40 + +#define XREG_CPSR_N_BIT 0x80000000 +#define XREG_CPSR_Z_BIT 0x40000000 +#define XREG_CPSR_C_BIT 0x20000000 +#define XREG_CPSR_V_BIT 0x10000000 + + +/* CP15 defines */ +#if defined (__GNUC__) || defined (__ICCARM__) +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" + +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" + +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" + +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" + +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" + +#define XREG_CP15_SECURE_CONFIG "p15, 0, %0, c1, c1, 0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "p15, 0, %0, c1, c1, 1" +#define XREG_CP15_NS_ACCESS_CONTROL "p15, 0, %0, c1, c1, 2" +#define XREG_CP15_VIRTUAL_CONTROL "p15, 0, %0, c1, c1, 3" + +#else /* RVCT */ +/* C0 Register defines */ +#define XREG_CP15_MAIN_ID "cp15:0:c0:c0:0" +#define XREG_CP15_CACHE_TYPE "cp15:0:c0:c0:1" +#define XREG_CP15_TCM_TYPE "cp15:0:c0:c0:2" +#define XREG_CP15_TLB_TYPE "cp15:0:c0:c0:3" +#define XREG_CP15_MULTI_PROC_AFFINITY "cp15:0:c0:c0:5" + +#define XREG_CP15_PROC_FEATURE_0 "cp15:0:c0:c1:0" +#define XREG_CP15_PROC_FEATURE_1 "cp15:0:c0:c1:1" +#define XREG_CP15_DEBUG_FEATURE_0 "cp15:0:c0:c1:2" +#define XREG_CP15_MEMORY_FEATURE_0 "cp15:0:c0:c1:4" +#define XREG_CP15_MEMORY_FEATURE_1 "cp15:0:c0:c1:5" +#define XREG_CP15_MEMORY_FEATURE_2 "cp15:0:c0:c1:6" +#define XREG_CP15_MEMORY_FEATURE_3 "cp15:0:c0:c1:7" + +#define XREG_CP15_INST_FEATURE_0 "cp15:0:c0:c2:0" +#define XREG_CP15_INST_FEATURE_1 "cp15:0:c0:c2:1" +#define XREG_CP15_INST_FEATURE_2 "cp15:0:c0:c2:2" +#define XREG_CP15_INST_FEATURE_3 "cp15:0:c0:c2:3" +#define XREG_CP15_INST_FEATURE_4 "cp15:0:c0:c2:4" + +#define XREG_CP15_CACHE_SIZE_ID "cp15:1:c0:c0:0" +#define XREG_CP15_CACHE_LEVEL_ID "cp15:1:c0:c0:1" +#define XREG_CP15_AUXILARY_ID "cp15:1:c0:c0:7" + +#define XREG_CP15_CACHE_SIZE_SEL "cp15:2:c0:c0:0" + +/* C1 Register Defines */ +#define XREG_CP15_SYS_CONTROL "cp15:0:c1:c0:0" +#define XREG_CP15_AUX_CONTROL "cp15:0:c1:c0:1" +#define XREG_CP15_CP_ACCESS_CONTROL "cp15:0:c1:c0:2" + +#define XREG_CP15_SECURE_CONFIG "cp15:0:c1:c1:0" +#define XREG_CP15_SECURE_DEBUG_ENABLE "cp15:0:c1:c1:1" +#define XREG_CP15_NS_ACCESS_CONTROL "cp15:0:c1:c1:2" +#define XREG_CP15_VIRTUAL_CONTROL "cp15:0:c1:c1:3" +#endif + +/* XREG_CP15_CONTROL bit defines */ +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U + +#if defined (__GNUC__) || defined (__ICCARM__) +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "p15, 0, %0, c2, c0, 0" +#define XREG_CP15_TTBR1 "p15, 0, %0, c2, c0, 1" +#define XREG_CP15_TTB_CONTROL "p15, 0, %0, c2, c0, 2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "p15, 0, %0, c3, c0, 0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" + +#define XREG_CP15_INVAL_IC_POU_IS "p15, 0, %0, c7, c1, 0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "p15, 0, %0, c7, c1, 6" + +#define XREG_CP15_PHYS_ADDR "p15, 0, %0, c7, c4, 0" + +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "p15, 0, %0, c7, c8, 0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "p15, 0, %0, c7, c8, 1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "p15, 0, %0, c7, c8, 2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "p15, 0, %0, c7, c8, 3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "p15, 0, %0, c7, c8, 4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "p15, 0, %0, c7, c8, 5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "p15, 0, %0, c7, c8, 6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "p15, 0, %0, c7, c8, 7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" + +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "p15, 0, %0, c8, c3, 0" +#define XREG_CP15_INVAL_TLB_MVA_IS "p15, 0, %0, c8, c3, 1" +#define XREG_CP15_INVAL_TLB_ASID_IS "p15, 0, %0, c8, c3, 2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "p15, 0, %0, c8, c3, 3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "p15, 0, %0, c8, c5, 0" +#define XREG_CP15_INVAL_ITLB_MVA "p15, 0, %0, c8, c5, 1" +#define XREG_CP15_INVAL_ITLB_ASID "p15, 0, %0, c8, c5, 2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "p15, 0, %0, c8, c6, 0" +#define XREG_CP15_INVAL_DTLB_MVA "p15, 0, %0, c8, c6, 1" +#define XREG_CP15_INVAL_DTLB_ASID "p15, 0, %0, c8, c6, 2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "p15, 0, %0, c8, c7, 0" +#define XREG_CP15_INVAL_UTLB_MVA "p15, 0, %0, c8, c7, 1" +#define XREG_CP15_INVAL_UTLB_ASID "p15, 0, %0, c8, c7, 2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "p15, 0, %0, c8, c7, 3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" + +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "p15, 0, %0, c10, c0, 0" + +#define XREG_CP15_PRI_MEM_REMAP "p15, 0, %0, c10, c2, 0" +#define XREG_CP15_NORM_MEM_REMAP "p15, 0, %0, c10, c2, 1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "p15, 0, %0, c12, c0, 1" + +#define XREG_CP15_INTERRUPT_STATUS "p15, 0, %0, c12, c1, 0" +#define XREG_CP15_VIRTUALIZATION_INTR "p15, 0, %0, c12, c1, 1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_CONFIG_BASE_ADDR "p15, 4, %0, c15, c0, 0" + +#define XREG_CP15_READ_TLB_ENTRY "p15, 5, %0, c15, c4, 2" +#define XREG_CP15_WRITE_TLB_ENTRY "p15, 5, %0, c15, c4, 4" + +#define XREG_CP15_MAIN_TLB_VA "p15, 5, %0, c15, c5, 2" + +#define XREG_CP15_MAIN_TLB_PA "p15, 5, %0, c15, c6, 2" + +#define XREG_CP15_MAIN_TLB_ATTR "p15, 5, %0, c15, c7, 2" + +#else +/* C2 Register Defines */ +#define XREG_CP15_TTBR0 "cp15:0:c2:c0:0" +#define XREG_CP15_TTBR1 "cp15:0:c2:c0:1" +#define XREG_CP15_TTB_CONTROL "cp15:0:c2:c0:2" + +/* C3 Register Defines */ +#define XREG_CP15_DOMAIN_ACCESS_CTRL "cp15:0:c3:c0:0" + +/* C4 Register Defines */ +/* Not Used */ + +/* C5 Register Defines */ +#define XREG_CP15_DATA_FAULT_STATUS "cp15:0:c5:c0:0" +#define XREG_CP15_INST_FAULT_STATUS "cp15:0:c5:c0:1" + +#define XREG_CP15_AUX_DATA_FAULT_STATUS "cp15:0:c5:c1:0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "cp15:0:c5:c1:1" + +/* C6 Register Defines */ +#define XREG_CP15_DATA_FAULT_ADDRESS "cp15:0:c6:c0:0" +#define XREG_CP15_INST_FAULT_ADDRESS "cp15:0:c6:c0:2" + +/* C7 Register Defines */ +#define XREG_CP15_NOP "cp15:0:c7:c0:4" + +#define XREG_CP15_INVAL_IC_POU_IS "cp15:0:c7:c1:0" +#define XREG_CP15_INVAL_BRANCH_ARRAY_IS "cp15:0:c7:c1:6" + +#define XREG_CP15_PHYS_ADDR "cp15:0:c7:c4:0" + +#define XREG_CP15_INVAL_IC_POU "cp15:0:c7:c5:0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "cp15:0:c7:c5:1" + +/* The CP15 register access below has been deprecated in favor of the new + * isb instruction in Cortex A9. + */ +#define XREG_CP15_INST_SYNC_BARRIER "cp15:0:c7:c5:4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "cp15:0:c7:c5:6" + +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c6:1" +#define XREG_CP15_INVAL_DC_LINE_SW "cp15:0:c7:c6:2" + +#define XREG_CP15_VA_TO_PA_CURRENT_0 "cp15:0:c7:c8:0" +#define XREG_CP15_VA_TO_PA_CURRENT_1 "cp15:0:c7:c8:1" +#define XREG_CP15_VA_TO_PA_CURRENT_2 "cp15:0:c7:c8:2" +#define XREG_CP15_VA_TO_PA_CURRENT_3 "cp15:0:c7:c8:3" + +#define XREG_CP15_VA_TO_PA_OTHER_0 "cp15:0:c7:c8:4" +#define XREG_CP15_VA_TO_PA_OTHER_1 "cp15:0:c7:c8:5" +#define XREG_CP15_VA_TO_PA_OTHER_2 "cp15:0:c7:c8:6" +#define XREG_CP15_VA_TO_PA_OTHER_3 "cp15:0:c7:c8:7" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "cp15:0:c7:c10:1" +#define XREG_CP15_CLEAN_DC_LINE_SW "cp15:0:c7:c10:2" + +/* The next two CP15 register accesses below have been deprecated in favor + * of the new dsb and dmb instructions in Cortex A9. + */ +#define XREG_CP15_DATA_SYNC_BARRIER "cp15:0:c7:c10:4" +#define XREG_CP15_DATA_MEMORY_BARRIER "cp15:0:c7:c10:5" + +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "cp15:0:c7:c11:1" + +#define XREG_CP15_NOP2 "cp15:0:c7:c13:1" + +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "cp15:0:c7:c14:1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "cp15:0:c7:c14:2" + +/* C8 Register Defines */ +#define XREG_CP15_INVAL_TLB_IS "cp15:0:c8:c3:0" +#define XREG_CP15_INVAL_TLB_MVA_IS "cp15:0:c8:c3:1" +#define XREG_CP15_INVAL_TLB_ASID_IS "cp15:0:c8:c3:2" +#define XREG_CP15_INVAL_TLB_MVA_ASID_IS "cp15:0:c8:c3:3" + +#define XREG_CP15_INVAL_ITLB_UNLOCKED "cp15:0:c8:c5:0" +#define XREG_CP15_INVAL_ITLB_MVA "cp15:0:c8:c5:1" +#define XREG_CP15_INVAL_ITLB_ASID "cp15:0:c8:c5:2" + +#define XREG_CP15_INVAL_DTLB_UNLOCKED "cp15:0:c8:c6:0" +#define XREG_CP15_INVAL_DTLB_MVA "cp15:0:c8:c6:1" +#define XREG_CP15_INVAL_DTLB_ASID "cp15:0:c8:c6:2" + +#define XREG_CP15_INVAL_UTLB_UNLOCKED "cp15:0:c8:c7:0" +#define XREG_CP15_INVAL_UTLB_MVA "cp15:0:c8:c7:1" +#define XREG_CP15_INVAL_UTLB_ASID "cp15:0:c8:c7:2" +#define XREG_CP15_INVAL_UTLB_MVA_ASID "cp15:0:c8:c7:3" + +/* C9 Register Defines */ +#define XREG_CP15_PERF_MONITOR_CTRL "cp15:0:c9:c12:0" +#define XREG_CP15_COUNT_ENABLE_SET "cp15:0:c9:c12:1" +#define XREG_CP15_COUNT_ENABLE_CLR "cp15:0:c9:c12:2" +#define XREG_CP15_V_FLAG_STATUS "cp15:0:c9:c12:3" +#define XREG_CP15_SW_INC "cp15:0:c9:c12:4" +#define XREG_CP15_EVENT_CNTR_SEL "cp15:0:c9:c12:5" + +#define XREG_CP15_PERF_CYCLE_COUNTER "cp15:0:c9:c13:0" +#define XREG_CP15_EVENT_TYPE_SEL "cp15:0:c9:c13:1" +#define XREG_CP15_PERF_MONITOR_COUNT "cp15:0:c9:c13:2" + +#define XREG_CP15_USER_ENABLE "cp15:0:c9:c14:0" +#define XREG_CP15_INTR_ENABLE_SET "cp15:0:c9:c14:1" +#define XREG_CP15_INTR_ENABLE_CLR "cp15:0:c9:c14:2" + +/* C10 Register Defines */ +#define XREG_CP15_TLB_LOCKDWN "cp15:0:c10:c0:0" + +#define XREG_CP15_PRI_MEM_REMAP "cp15:0:c10:c2:0" +#define XREG_CP15_NORM_MEM_REMAP "cp15:0:c10:c2:1" + +/* C11 Register Defines */ +/* Not used */ + +/* C12 Register Defines */ +#define XREG_CP15_VEC_BASE_ADDR "cp15:0:c12:c0:0" +#define XREG_CP15_MONITOR_VEC_BASE_ADDR "cp15:0:c12:c0:1" + +#define XREG_CP15_INTERRUPT_STATUS "cp15:0:c12:c1:0" +#define XREG_CP15_VIRTUALIZATION_INTR "cp15:0:c12:c1:1" + +/* C13 Register Defines */ +#define XREG_CP15_CONTEXT_ID "cp15:0:c13:c0:1" +#define USER_RW_THREAD_PID "cp15:0:c13:c0:2" +#define USER_RO_THREAD_PID "cp15:0:c13:c0:3" +#define USER_PRIV_THREAD_PID "cp15:0:c13:c0:4" + +/* C14 Register Defines */ +/* not used */ + +/* C15 Register Defines */ +#define XREG_CP15_POWER_CTRL "cp15:0:c15:c0:0" +#define XREG_CP15_CONFIG_BASE_ADDR "cp15:4:c15:c0:0" + +#define XREG_CP15_READ_TLB_ENTRY "cp15:5:c15:c4:2" +#define XREG_CP15_WRITE_TLB_ENTRY "cp15:5:c15:c4:4" + +#define XREG_CP15_MAIN_TLB_VA "cp15:5:c15:c5:2" + +#define XREG_CP15_MAIN_TLB_PA "cp15:5:c15:c6:2" + +#define XREG_CP15_MAIN_TLB_ATTR "cp15:5:c15:c7:2" +#endif + + +/* MPE register definitions */ +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 + +/* FPSID bits */ +#define XREG_FPSID_IMPLEMENTER_BIT (24) +#define XREG_FPSID_IMPLEMENTER_MASK (0xFF << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (1<<23) +#define XREG_FPSID_ARCH_BIT (16) +#define XREG_FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8) +#define XREG_FPSID_PART_MASK (0xFF << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4) +#define XREG_FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0) +#define XREG_FPSID_REV_MASK (0xF << FPSID_REV_BIT) + +/* FPSCR bits */ +#define XREG_FPSCR_N_BIT (1 << 31) +#define XREG_FPSCR_Z_BIT (1 << 30) +#define XREG_FPSCR_C_BIT (1 << 29) +#define XREG_FPSCR_V_BIT (1 << 28) +#define XREG_FPSCR_QC (1 << 27) +#define XREG_FPSCR_AHP (1 << 26) +#define XREG_FPSCR_DEFAULT_NAN (1 << 25) +#define XREG_FPSCR_FLUSHTOZERO (1 << 24) +#define XREG_FPSCR_ROUND_NEAREST (0 << 22) +#define XREG_FPSCR_ROUND_PLUSINF (1 << 22) +#define XREG_FPSCR_ROUND_MINUSINF (2 << 22) +#define XREG_FPSCR_ROUND_TOZERO (3 << 22) +#define XREG_FPSCR_RMODE_BIT (22) +#define XREG_FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20) +#define XREG_FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16) +#define XREG_FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (1 << 7) +#define XREG_FPSCR_IXC (1 << 4) +#define XREG_FPSCR_UFC (1 << 3) +#define XREG_FPSCR_OFC (1 << 2) +#define XREG_FPSCR_DZC (1 << 1) +#define XREG_FPSCR_IOC (1 << 0) + +/* MVFR0 bits */ +#define XREG_MVFR0_RMODE_BIT (28) +#define XREG_MVFR0_RMODE_MASK (0xF << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24) +#define XREG_MVFR0_SHORT_VEC_MASK (0xF << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20) +#define XREG_MVFR0_SQRT_MASK (0xF << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16) +#define XREG_MVFR0_DIVIDE_MASK (0xF << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12) +#define XREG_MVFR0_EXEC_TRAP_MASK (0xF << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8) +#define XREG_MVFR0_DP_MASK (0xF << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4) +#define XREG_MVFR0_SP_MASK (0xF << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0) +#define XREG_MVFR0_A_SIMD_MASK (0xF << MVFR0_A_SIMD_BIT) + +/* FPEXC bits */ +#define XREG_FPEXC_EX (1 << 31) +#define XREG_FPEXC_EN (1 << 30) +#define XREG_FPEXC_DEX (1 << 29) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XREG_CORTEXA9_H */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic.h new file mode 100644 index 0000000..e22ee5b --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic.h @@ -0,0 +1,372 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xscugic.h +* @addtogroup scugic_v3_8 +* @{ +* @details +* +* The generic interrupt controller driver component. +* +* The interrupt controller driver uses the idea of priority for the various +* handlers. Priority is an integer within the range of 1 and 31 inclusive with +* default of 1 being the highest priority interrupt source. The priorities +* of the various sources can be dynamically altered as needed through +* hardware configuration. +* +* The generic interrupt controller supports the following +* features: +* +* - specific individual interrupt enabling/disabling +* - specific individual interrupt acknowledging +* - attaching specific callback function to handle interrupt source +* - assigning desired priority to interrupt source if default is not +* acceptable. +* +* Details about connecting the interrupt handler of the driver are contained +* in the source file specific to interrupt processing, xscugic_intr.c. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* Interrupt Vector Tables +* +* The device ID of the interrupt controller device is used by the driver as a +* direct index into the configuration data table. The user should populate the +* vector table with handlers and callbacks at run-time using the +* XScuGic_Connect() and XScuGic_Disconnect() functions. +* +* Each vector table entry corresponds to a device that can generate an +* interrupt. Each entry contains an interrupt handler function and an +* argument to be passed to the handler when an interrupt occurs. The +* user must use XScuGic_Connect() when the interrupt handler takes an +* argument other than the base address. +* +* Nested Interrupts Processing +* +* Nested interrupts are not supported by this driver. +* +* NOTE: +* The generic interrupt controller is not a part of the snoop control unit +* as indicated by the prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*            the flow and avoid code duplication. Changes are made for
+*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*            one R5 is operating with A53 in open amp config and other
+*            R5 running baremetal app, the existing code
+*            had the potential to stop the whole AMP solution to work (if
+*            for some reason the R5 running the baremetal app tasked to
+*            initialize the Distributor hangs or crashes before initializing).
+*            Changes are made so that the R5 under AMP first checks if
+*            the distributor is enabled or not and if not, it does the
+*            standard Distributor initialization.
+*            This fixes the CR#952962.
+* 3.6   ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* 3.7   ms   04/11/17 Modified tcl file to add suffix U for all macro
+*                     definitions of scugic in xparameters.h
+* 3.8   mus  07/05/17 Updated scugic.tcl to add support for intrrupts connected
+*                     through util_reduced_vector IP(OR gate)
+*       mus  07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+*                     the HandlerTable in XScuGic_ConfigTable to 0, it removes
+*                     the compilation warning in xscugic_g.c. Fix for CR#978736.
+*       mus  07/25/17 Updated xdefine_gic_params proc to export correct canonical
+*                     definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9   mus  02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+*                     XScuGic_InterruptUnmapFromCpu, These API's can be used
+*                     by applications to unmap specific/all interrupts from
+*                     target CPU.
+*
+*
    +* +******************************************************************************/ + +#ifndef XSCUGIC_H /* prevent circular inclusions */ +#define XSCUGIC_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_io.h" +#include "xscugic_hw.h" +#include "xil_exception.h" + +/************************** Constant Definitions *****************************/ + +#define EFUSE_STATUS_OFFSET 0x10 +#define EFUSE_STATUS_CPU_MASK 0x80 + +#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) +#define ARMA9 +#endif +/**************************** Type Definitions *******************************/ + +/* The following data type defines each entry in an interrupt vector table. + * The callback reference is the base address of the interrupting device + * for the low level driver and an instance pointer for the high level driver. + */ +typedef struct +{ + Xil_InterruptHandler Handler; + void *CallBackRef; +} XScuGic_VectorTableEntry; + +/** + * This typedef contains configuration information for the device. + */ +typedef struct +{ + u16 DeviceId; /**< Unique ID of device */ + u32 CpuBaseAddress; /**< CPU Interface Register base address */ + u32 DistBaseAddress; /**< Distributor Register base address */ + XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**< + Vector table of interrupt handlers */ +} XScuGic_Config; + +/** + * The XScuGic driver instance data. The user is required to allocate a + * variable of this type for every intc device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct +{ + XScuGic_Config *Config; /**< Configuration table entry */ + u32 IsReady; /**< Device is initialized and ready */ + u32 UnhandledInterrupts; /**< Intc Statistics */ +} XScuGic; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \ + ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given CPU Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \ + (XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \ +(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \ + ((u32)(Data)))) + +/****************************************************************************/ +/** +* +* Read the given Distributor Interface register +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_DistReadReg(InstancePtr, RegOffset) \ +(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset))) + +/************************** Function Prototypes ******************************/ + +/* + * Required functions in xscugic.c + */ + +s32 XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id); + +void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id); +void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id); + +s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr, + u32 EffectiveAddr); + +s32 XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id); + +void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 *Priority, u8 *Trigger); +void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, + u8 Priority, u8 Trigger); +void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id); +void XScuGic_Stop(XScuGic *InstancePtr); +void XScuGic_SetCpuID(u32 CpuCoreId); +u32 XScuGic_GetCpuID(void); +/* + * Initialization functions in xscugic_sinit.c + */ +XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId); + +/* + * Interrupt functions in xscugic_intr.c + */ +void XScuGic_InterruptHandler(XScuGic *InstancePtr); + +/* + * Self-test functions in xscugic_selftest.c + */ +s32 XScuGic_SelfTest(XScuGic *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic_hw.h new file mode 100644 index 0000000..08e65f4 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscugic_hw.h @@ -0,0 +1,650 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xscugic_hw.h +* @addtogroup scugic_v3_8 +* @{ +* +* This header file contains identifiers and HW access functions (or +* macros) that can be used to access the device. The user should refer to the +* hardware device specification for more details of the device operation. +* The driver functions/APIs are defined in xscugic.h. +* +* This GIC device has two parts, a distributor and CPU interface(s). Each part +* has separate register definition sections. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
+*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9   mus  02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+*					  and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+*					  API's can be used by applications to unmap specific/all
+*					  interrupts from target CPU. It fixes CR#992490.
+*
    +* +******************************************************************************/ + +#ifndef XSCUGIC_HW_H /* prevent circular inclusions */ +#define XSCUGIC_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xil_exception.h" + +/************************** Constant Definitions *****************************/ + +/* + * The maximum number of interrupts supported by the hardware. + */ +#ifdef __ARM_NEON__ +#define XSCUGIC_MAX_NUM_INTR_INPUTS 95U /* Maximum number of interrupt defined by Zynq */ +#else +#define XSCUGIC_MAX_NUM_INTR_INPUTS 195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */ +#endif + +/* + * The maximum priority value that can be used in the GIC. + */ +#define XSCUGIC_MAX_INTR_PRIO_VAL 248U +#define XSCUGIC_INTR_PRIO_MASK 0x000000F8U + +/** @name Distributor Interface Register Map + * + * Define the offsets from the base address for all Distributor registers of + * the interrupt controller, some registers may be reserved in the hardware + * device. + * @{ + */ +#define XSCUGIC_DIST_EN_OFFSET 0x00000000U /**< Distributor Enable + Register */ +#define XSCUGIC_IC_TYPE_OFFSET 0x00000004U /**< Interrupt Controller + Type Register */ +#define XSCUGIC_DIST_IDENT_OFFSET 0x00000008U /**< Implementor ID + Register */ +#define XSCUGIC_SECURITY_OFFSET 0x00000080U /**< Interrupt Security + Register */ +#define XSCUGIC_ENABLE_SET_OFFSET 0x00000100U /**< Enable Set + Register */ +#define XSCUGIC_DISABLE_OFFSET 0x00000180U /**< Enable Clear Register */ +#define XSCUGIC_PENDING_SET_OFFSET 0x00000200U /**< Pending Set + Register */ +#define XSCUGIC_PENDING_CLR_OFFSET 0x00000280U /**< Pending Clear + Register */ +#define XSCUGIC_ACTIVE_OFFSET 0x00000300U /**< Active Status Register */ +#define XSCUGIC_PRIORITY_OFFSET 0x00000400U /**< Priority Level Register */ +#define XSCUGIC_SPI_TARGET_OFFSET 0x00000800U /**< SPI Target + Register 0x800-0x8FB */ +#define XSCUGIC_INT_CFG_OFFSET 0x00000C00U /**< Interrupt Configuration + Register 0xC00-0xCFC */ +#define XSCUGIC_PPI_STAT_OFFSET 0x00000D00U /**< PPI Status Register */ +#define XSCUGIC_SPI_STAT_OFFSET 0x00000D04U /**< SPI Status Register + 0xd04-0xd7C */ +#define XSCUGIC_AHB_CONFIG_OFFSET 0x00000D80U /**< AHB Configuration + Register */ +#define XSCUGIC_SFI_TRIG_OFFSET 0x00000F00U /**< Software Triggered + Interrupt Register */ +#define XSCUGIC_PERPHID_OFFSET 0x00000FD0U /**< Peripheral ID Reg */ +#define XSCUGIC_PCELLID_OFFSET 0x00000FF0U /**< Pcell ID Register */ +/* @} */ + +/** @name Distributor Enable Register + * Controls if the distributor response to external interrupt inputs. + * @{ + */ +#define XSCUGIC_EN_INT_MASK 0x00000001U /**< Interrupt In Enable */ +/* @} */ + +/** @name Interrupt Controller Type Register + * @{ + */ +#define XSCUGIC_LSPI_MASK 0x0000F800U /**< Number of Lockable + Shared Peripheral + Interrupts*/ +#define XSCUGIC_DOMAIN_MASK 0x00000400U /**< Number os Security domains*/ +#define XSCUGIC_CPU_NUM_MASK 0x000000E0U /**< Number of CPU Interfaces */ +#define XSCUGIC_NUM_INT_MASK 0x0000001FU /**< Number of Interrupt IDs */ +/* @} */ + +/** @name Implementor ID Register + * Implementor and revision information. + * @{ + */ +#define XSCUGIC_REV_MASK 0x00FFF000U /**< Revision Number */ +#define XSCUGIC_IMPL_MASK 0x00000FFFU /**< Implementor */ +/* @} */ + +/** @name Interrupt Security Registers + * Each bit controls the security level of an interrupt, either secure or non + * secure. These registers can only be accessed using secure read and write. + * There are registers for each of the CPU interfaces at offset 0x080. A + * register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x084. + * @{ + */ +#define XSCUGIC_INT_NS_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Set Register + * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a + * bit to 0. + * There are registers for each of the CPU interfaces at offset 0x100. With up + * to 8 registers aliased to the same address. A register set for the SPI + * interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x104. + * @{ + */ +#define XSCUGIC_INT_EN_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Enable Clear Register + * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is + * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and + * sets the corresponding bit to 0. + * There are registers for each of the CPU interfaces at offset 0x180. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x184. + * @{ + */ +#define XSCUGIC_INT_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Set Register + * Each bit controls the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets + * an interrupt to the pending state. + * There are registers for each of the CPU interfaces at offset 0x200. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x204. + * @{ + */ +#define XSCUGIC_PEND_SET_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Pending Clear Register + * Each bit can clear the Pending or Active and Pending state of an interrupt, a + * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 + * clears the pending state of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x280. With up + * to 8 registers aliased to the same address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x284. + * @{ + */ +#define XSCUGIC_PEND_CLR_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Active Status Register + * Each bit provides the Active status of an interrupt, a + * 0 is not Active, a 1 is Active. This is a read only register. + * There are registers for each of the CPU interfaces at offset 0x300. With up + * to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 32 of these registers staring at location 0x380. + * @{ + */ +#define XSCUGIC_ACTIVE_MASK 0x00000001U /**< Each bit corresponds to an + INT_ID */ +/* @} */ + +/** @name Priority Level Register + * Each byte in a Priority Level Register sets the priority level of an + * interrupt. Reading the register provides the priority level of an interrupt. + * There are registers for each of the CPU interfaces at offset 0x400 through + * 0x41C. With up to 8 registers aliased to each address. + * 0 is highest priority, 0xFF is lowest. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x420. + * @{ + */ +#define XSCUGIC_PRIORITY_MASK 0x000000FFU /**< Each Byte corresponds to an + INT_ID */ +#define XSCUGIC_PRIORITY_MAX 0x000000FFU /**< Highest value of a priority + actually the lowest priority*/ +/* @} */ + +/** @name SPI Target Register 0x800-0x8FB + * Each byte references a separate SPI and programs which of the up to 8 CPU + * interfaces are sent a Pending interrupt. + * There are registers for each of the CPU interfaces at offset 0x800 through + * 0x81C. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0x820. + * + * This driver does not support multiple CPU interfaces. These are included + * for complete documentation. + * @{ + */ +#define XSCUGIC_SPI_CPU7_MASK 0x00000080U /**< CPU 7 Mask*/ +#define XSCUGIC_SPI_CPU6_MASK 0x00000040U /**< CPU 6 Mask*/ +#define XSCUGIC_SPI_CPU5_MASK 0x00000020U /**< CPU 5 Mask*/ +#define XSCUGIC_SPI_CPU4_MASK 0x00000010U /**< CPU 4 Mask*/ +#define XSCUGIC_SPI_CPU3_MASK 0x00000008U /**< CPU 3 Mask*/ +#define XSCUGIC_SPI_CPU2_MASK 0x00000004U /**< CPU 2 Mask*/ +#define XSCUGIC_SPI_CPU1_MASK 0x00000002U /**< CPU 1 Mask*/ +#define XSCUGIC_SPI_CPU0_MASK 0x00000001U /**< CPU 0 Mask*/ +/* @} */ + +/** @name Interrupt Configuration Register 0xC00-0xCFC + * The interrupt configuration registers program an SFI to be active HIGH level + * sensitive or rising edge sensitive. + * Each bit pair describes the configuration for an INT_ID. + * SFI Read Only b10 always + * PPI Read Only depending on how the PPIs are configured. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive + * SPI LSB is read only. + * b01 Active HIGH level sensitive + * b11 Rising edge sensitive/ + * There are registers for each of the CPU interfaces at offset 0xC00 through + * 0xC04. With up to 8 registers aliased to each address. + * A register set for the SPI interrupts is available to all CPU interfaces. + * There are up to 255 of these registers staring at location 0xC08. + * @{ + */ +#define XSCUGIC_INT_CFG_MASK 0x00000003U /**< */ +/* @} */ + +/** @name PPI Status Register + * Enables an external AMBA master to access the status of the PPI inputs. + * A CPU can only read the status of its local PPI signals and cannot read the + * status for other CPUs. + * This register is aliased for each CPU interface. + * @{ + */ +#define XSCUGIC_PPI_C15_MASK 0x00008000U /**< PPI Status */ +#define XSCUGIC_PPI_C14_MASK 0x00004000U /**< PPI Status */ +#define XSCUGIC_PPI_C13_MASK 0x00002000U /**< PPI Status */ +#define XSCUGIC_PPI_C12_MASK 0x00001000U /**< PPI Status */ +#define XSCUGIC_PPI_C11_MASK 0x00000800U /**< PPI Status */ +#define XSCUGIC_PPI_C10_MASK 0x00000400U /**< PPI Status */ +#define XSCUGIC_PPI_C09_MASK 0x00000200U /**< PPI Status */ +#define XSCUGIC_PPI_C08_MASK 0x00000100U /**< PPI Status */ +#define XSCUGIC_PPI_C07_MASK 0x00000080U /**< PPI Status */ +#define XSCUGIC_PPI_C06_MASK 0x00000040U /**< PPI Status */ +#define XSCUGIC_PPI_C05_MASK 0x00000020U /**< PPI Status */ +#define XSCUGIC_PPI_C04_MASK 0x00000010U /**< PPI Status */ +#define XSCUGIC_PPI_C03_MASK 0x00000008U /**< PPI Status */ +#define XSCUGIC_PPI_C02_MASK 0x00000004U /**< PPI Status */ +#define XSCUGIC_PPI_C01_MASK 0x00000002U /**< PPI Status */ +#define XSCUGIC_PPI_C00_MASK 0x00000001U /**< PPI Status */ +/* @} */ + +/** @name SPI Status Register 0xd04-0xd7C + * Enables an external AMBA master to access the status of the SPI inputs. + * There are up to 63 registers if the maximum number of SPI inputs are + * configured. + * @{ + */ +#define XSCUGIC_SPI_N_MASK 0x00000001U /**< Each bit corresponds to an SPI + input */ +/* @} */ + +/** @name AHB Configuration Register + * Provides the status of the CFGBIGEND input signal and allows the endianess + * of the GIC to be set. + * @{ + */ +#define XSCUGIC_AHB_END_MASK 0x00000004U /**< 0-GIC uses little Endian, + 1-GIC uses Big Endian */ +#define XSCUGIC_AHB_ENDOVR_MASK 0x00000002U /**< 0-Uses CFGBIGEND control, + 1-use the AHB_END bit */ +#define XSCUGIC_AHB_TIE_OFF_MASK 0x00000001U /**< State of CFGBIGEND */ + +/* @} */ + +/** @name Software Triggered Interrupt Register + * Controls issueing of software interrupts. + * @{ + */ +#define XSCUGIC_SFI_SELFTRIG_MASK 0x02010000U +#define XSCUGIC_SFI_TRIG_TRGFILT_MASK 0x03000000U /**< Target List filter + b00-Use the target List + b01-All CPUs except requester + b10-To Requester + b11-reserved */ +#define XSCUGIC_SFI_TRIG_CPU_MASK 0x00FF0000U /**< CPU Target list */ +#define XSCUGIC_SFI_TRIG_SATT_MASK 0x00008000U /**< 0= Use a secure interrupt */ +#define XSCUGIC_SFI_TRIG_INTID_MASK 0x0000000FU /**< Set to the INTID + signaled to the CPU*/ +/* @} */ + +/** @name CPU Interface Register Map + * + * Define the offsets from the base address for all CPU registers of the + * interrupt controller, some registers may be reserved in the hardware device. + * @{ + */ +#define XSCUGIC_CONTROL_OFFSET 0x00000000U /**< CPU Interface Control + Register */ +#define XSCUGIC_CPU_PRIOR_OFFSET 0x00000004U /**< Priority Mask Reg */ +#define XSCUGIC_BIN_PT_OFFSET 0x00000008U /**< Binary Point Register */ +#define XSCUGIC_INT_ACK_OFFSET 0x0000000CU /**< Interrupt ACK Reg */ +#define XSCUGIC_EOI_OFFSET 0x00000010U /**< End of Interrupt Reg */ +#define XSCUGIC_RUN_PRIOR_OFFSET 0x00000014U /**< Running Priority Reg */ +#define XSCUGIC_HI_PEND_OFFSET 0x00000018U /**< Highest Pending Interrupt + Register */ +#define XSCUGIC_ALIAS_BIN_PT_OFFSET 0x0000001CU /**< Aliased non-Secure + Binary Point Register */ + +/**< 0x00000020 to 0x00000FBC are reserved and should not be read or written + * to. */ +/* @} */ + + +/** @name Control Register + * CPU Interface Control register definitions + * All bits are defined here although some are not available in the non-secure + * mode. + * @{ + */ +#define XSCUGIC_CNTR_SBPR_MASK 0x00000010U /**< Secure Binary Pointer, + 0=separate registers, + 1=both use bin_pt_s */ +#define XSCUGIC_CNTR_FIQEN_MASK 0x00000008U /**< Use nFIQ_C for secure + interrupts, + 0= use IRQ for both, + 1=Use FIQ for secure, IRQ for non*/ +#define XSCUGIC_CNTR_ACKCTL_MASK 0x00000004U /**< Ack control for secure or non secure */ +#define XSCUGIC_CNTR_EN_NS_MASK 0x00000002U /**< Non Secure enable */ +#define XSCUGIC_CNTR_EN_S_MASK 0x00000001U /**< Secure enable, 0=Disabled, 1=Enabled */ +/* @} */ + +/** @name Priority Mask Register + * Priority Mask register definitions + * The CPU interface does not send interrupt if the level of the interrupt is + * lower than the level of the register. + * @{ + */ +/*#define XSCUGIC_PRIORITY_MASK 0x000000FFU*/ /**< All interrupts */ +/* @} */ + +/** @name Binary Point Register + * Binary Point register definitions + * @{ + */ + +#define XSCUGIC_BIN_PT_MASK 0x00000007U /**< Binary point mask value + Value Secure Non-secure + b000 0xFE 0xFF + b001 0xFC 0xFE + b010 0xF8 0xFC + b011 0xF0 0xF8 + b100 0xE0 0xF0 + b101 0xC0 0xE0 + b110 0x80 0xC0 + b111 0x00 0x80 + */ +/*@}*/ + +/** @name Interrupt Acknowledge Register + * Interrupt Acknowledge register definitions + * Identifies the current Pending interrupt, and the CPU ID for software + * interrupts. + */ +#define XSCUGIC_ACK_INTID_MASK 0x000003FFU /**< Interrupt ID */ +#define XSCUGIC_CPUID_MASK 0x00000C00U /**< CPU ID */ +/* @} */ + +/** @name End of Interrupt Register + * End of Interrupt register definitions + * Allows the CPU to signal the GIC when it completes an interrupt service + * routine. + */ +#define XSCUGIC_EOI_INTID_MASK 0x000003FFU /**< Interrupt ID */ + +/* @} */ + +/** @name Running Priority Register + * Running Priority register definitions + * Identifies the interrupt priority level of the highest priority active + * interrupt. + */ +#define XSCUGIC_RUN_PRIORITY_MASK 0x000000FFU /**< Interrupt Priority */ +/* @} */ + +/* + * Highest Pending Interrupt register definitions + * Identifies the interrupt priority of the highest priority pending interupt + */ +#define XSCUGIC_PEND_INTID_MASK 0x000003FFU /**< Pending Interrupt ID */ +/*#define XSCUGIC_CPUID_MASK 0x00000C00U */ /**< CPU ID */ +/* @} */ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the Interrupt Configuration Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Priority Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the SPI Target Register offset for an interrupt id. +* +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \ + ((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the Interrupt Clear-Enable Register offset for an interrupt ID +* +* @param Register is the register offset for the clear/enable bank. +* @param InterruptID is the interrupt number. +* +* @return The 32-bit value of the offset +* +* @note +* +*****************************************************************************/ +#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \ + ((Register) + (((InterruptID)/32U) * 4U)) + +/****************************************************************************/ +/** +* +* Read the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note +* C-style signature: +* u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XScuGic_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + + +/****************************************************************************/ +/** +* +* Write the given Intc register. +* +* @param BaseAddress is the base address of the device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note +* C-style signature: +* void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data)))) + + +/****************************************************************************/ +/** +* +* Enable specific interrupt(s) in the interrupt controller. +* +* @param DistBaseAddress is the Distributor Register base address of the +* device +* @param Int_Id is the ID of the interrupt source and should be in the +* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* +* @return None. +* +* @note C-style signature: +* void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id) +* +*****************************************************************************/ +#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \ + XScuGic_WriteReg((DistBaseAddress), \ + XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \ + (0x00000001U << ((Int_Id) % 32U))) + +/****************************************************************************/ +/** +* +* Disable specific interrupt(s) in the interrupt controller. +* +* @param DistBaseAddress is the Distributor Register base address of the +* device +* @param Int_Id is the ID of the interrupt source and should be in the +* range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* +* +* @return None. +* +* @note C-style signature: +* void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id) +* +*****************************************************************************/ +#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \ + XScuGic_WriteReg((DistBaseAddress), \ + XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \ + (0x00000001U << ((Int_Id) % 32U))) + + +/************************** Function Prototypes ******************************/ + +void XScuGic_DeviceInterruptHandler(void *DeviceId); +s32 XScuGic_DeviceInitialize(u32 DeviceId); +void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID, + Xil_InterruptHandler Handler, void *CallBackRef); +void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 Priority, u8 Trigger); +void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, + u8 *Priority, u8 *Trigger); +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id); +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer.h new file mode 100644 index 0000000..ea4ba79 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer.h @@ -0,0 +1,368 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscutimer.h +* @addtogroup scutimer_v2_1 +* @{ +* @details +* +* The timer driver supports the Cortex A9 private timer. +* +* The timer driver supports the following features: +* - Normal mode and Auto reload mode +* - Interrupts (Interrupt handler is not provided in this driver. Application +* has to register it's own handler) +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Timer. +* +* XScuTimer_CfgInitialize() API is used to initialize the Timer. The +* user needs to first call the XScuTimer_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to +* the XScuTimer_CfgInitialize() API. +* +* Interrupts +* +* The Timer hardware supports interrupts. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* Timer in interrupt mode. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XScuTimer driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

    +* +* NOTE: +* The timer is not a part of the snoop control unit as indicated by the +* prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
    +* +******************************************************************************/ +#ifndef XSCUTIMER_H /* prevent circular inclusions */ +#define XSCUTIMER_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xscutimer_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XScuTimer_Config; + +/** + * The XScuTimer driver instance data. The user is required to allocate a + * variable of this type for every timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XScuTimer_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device timer is running */ +} XScuTimer; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Check if the timer has expired. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return +* - TRUE if the timer has expired. +* - FALSE if the timer has not expired. +* +* @note C-style signature: +* int XScuTimer_IsExpired(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_IsExpired(InstancePtr) \ + ((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET) & \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) == \ + XSCUTIMER_ISR_EVENT_FLAG_MASK) + +/****************************************************************************/ +/** +* +* Re-start the timer. This macro will read the timer load register +* and writes the same value to load register to update the counter register. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_RestartTimer(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_RestartTimer(InstancePtr) \ + XScuTimer_LoadTimer((InstancePtr), \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET)) + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_LoadTimer(InstancePtr, Value) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. It can be called at any +* time. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_GetCounterValue(InstancePtr) \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_COUNTER_OFFSET) + +/****************************************************************************/ +/** +* +* Enable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_EnableAutoReload(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)) + +/****************************************************************************/ +/** +* +* Disable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_DisableAutoReload(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))) + +/****************************************************************************/ +/** +* +* Enable the Timer interrupt. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_EnableInterrupt(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) | \ + XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)) + +/****************************************************************************/ +/** +* +* Disable the Timer interrupt. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_DisableInterrupt(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET, \ + (XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_CONTROL_OFFSET) & \ + ~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))) + +/*****************************************************************************/ +/** +* +* This function reads the interrupt status. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_GetInterruptStatus(InstancePtr) \ + XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the interrupt status. +* +* @param InstancePtr is a pointer to the XScuTimer instance. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr) +* +******************************************************************************/ +#define XScuTimer_ClearInterruptStatus(InstancePtr) \ + XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xscutimer_sinit.c + */ +XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xscutimer_selftest.c + */ +s32 XScuTimer_SelfTest(XScuTimer *InstancePtr); + +/* + * Interface functions in xscutimer.c + */ +s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr, + XScuTimer_Config *ConfigPtr, u32 EffectiveAddress); +void XScuTimer_Start(XScuTimer *InstancePtr); +void XScuTimer_Stop(XScuTimer *InstancePtr); +void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue); +u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer_hw.h new file mode 100644 index 0000000..ac7b429 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscutimer_hw.h @@ -0,0 +1,287 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscutimer_hw.h +* @addtogroup scutimer_v2_1 +* @{ +* +* This file contains the hardware interface to the Timer. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+*		     and interrupt registers
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
    +* +******************************************************************************/ +#ifndef XSCUTIMER_HW_H /* prevent circular inclusions */ +#define XSCUTIMER_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_io.h" +#include "xil_assert.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XSCUTIMER_LOAD_OFFSET 0x00U /**< Timer Load Register */ +#define XSCUTIMER_COUNTER_OFFSET 0x04U /**< Timer Counter Register */ +#define XSCUTIMER_CONTROL_OFFSET 0x08U /**< Timer Control Register */ +#define XSCUTIMER_ISR_OFFSET 0x0CU /**< Timer Interrupt + Status Register */ +/* @} */ + +/** @name Timer Control register + * This register bits control the prescaler, Intr enable, + * auto-reload and timer enable. + * @{ + */ + +#define XSCUTIMER_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */ +#define XSCUTIMER_CONTROL_PRESCALER_SHIFT 8U +#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK 0x00000004U /**< Intr enable */ +#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload */ +#define XSCUTIMER_CONTROL_ENABLE_MASK 0x00000001U /**< Timer enable */ +/* @} */ + +/** @name Interrupt Status register + * This register indicates the Timer counter register has reached zero. + * @{ + */ + +#define XSCUTIMER_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetLoadReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer load register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer load register. +* +* @note C-style signature: +* u32 XScuTimer_GetLoadReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetLoadReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer counter register. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the counter register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetCounterReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetCounterReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetCounterReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer load register. This will also update the +* timer counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the load register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetControlReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer load register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer load register. +* +* @note C-style signature: + u32 XScuTimer_GetControlReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetControlReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the timer counter register. +* +* @param BaseAddr is the base address of the scu timer. +* @param Value is the count to be loaded in to the counter register. +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value) +* +******************************************************************************/ +#define XScuTimer_SetIntrReg(BaseAddr, Value) \ + XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Returns the current timer counter register value. +* +* @param BaseAddr is the base address of the scu timer. +* +* @return Contents of the timer counter register. +* +* @note C-style signature: + u32 XScuTimer_GetIntrReg(u32 BaseAddr) +* +******************************************************************************/ +#define XScuTimer_GetIntrReg(BaseAddr) \ + XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET) + +/****************************************************************************/ +/** +* +* Read from the given Timer register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuTimer_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given Timer register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt.h new file mode 100644 index 0000000..372bbc3 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt.h @@ -0,0 +1,383 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscuwdt.h +* @addtogroup scuwdt_v2_1 +* @{ +* @details +* +* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private +* watchdog timer hardware. +* +* The XScuWdt driver supports the following features: +* - Watchdog mode +* - Timer mode +* - Auto reload (timer mode only) +* +* The watchdog counter register is a down counter and starts decrementing when +* the watchdog is started. +* In watchdog mode, when the counter reaches 0, the Reset flag is set in the +* Reset status register and the WDRESETREQ pin is asserted, causing a system +* reset. The Reset flag is not reset by normal processor reset and is cleared +* when written with a value of 1. This enables the user to differentiate a +* normal reset and a reset caused by watchdog time-out. The user needs to call +* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out. +* +* The IsWdtExpired function can be used to check if the watchdog was the cause +* of the last reset. In this situation, call Initialize then call IsWdtExpired. +* If the result is true, watchdog timeout caused the last system reset. The +* application then needs to clear the Reset flag. +* +* In timer mode, when the counter reaches 0, the Event flag is set in the +* Interrupt status register and if interrupts are enabled, interrupt ID 30 is +* set as pending in the interrupt distributor. The IsTimerExpired function +* is used to check if the watchdog counter has decremented to 0 in timer mode. +* If auto-reload mode is enabled, the Counter register is automatically reloaded +* from the Load register. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Watchdog Timer. +* +* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The +* user needs to first call the XScuWdt_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to +* the XScuWdt_CfgInitialize() API. +* +* Interrupts +* +* The SCU Watchdog Timer supports interrupts in Timer mode. +* +* This driver does not provide a Interrupt Service Routine (ISR) for the device. +* It is the responsibility of the application to provide one if needed. Refer to +* the interrupt example provided with this driver for details on using the +* Timer in interrupt mode. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XScuWdt driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

    +* +* NOTE: +* The watchdog timer is not a part of the snoop control unit as indicated +* by the prefix "scu" in the name of the driver. +* It is an independent module in APU. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*
    +* +******************************************************************************/ +#ifndef XSCUWDT_H /* prevent circular inclusions */ +#define XSCUWDT_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xscuwdt_hw.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XScuWdt_Config; + +/** + * The XScuWdt driver instance data. The user is required to allocate a + * variable of this type for every watchdog/timer device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XScuWdt_Config Config;/**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device watchdog timer is running */ +} XScuWdt; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/** +* +* This function is used to check if the watchdog has timed-out and the last +* reset was caused by the watchdog reset. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_IsWdtExpired(InstancePtr) \ + ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_RST_STS_OFFSET) & \ + XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK) + +/****************************************************************************/ +/** +* +* This function is used to check if the watchdog counter has reached 0 in timer +* mode. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return +* - TRUE if the watchdog has expired. +* - FALSE if the watchdog has not expired. +* +* @note C-style signature: +* int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_IsTimerExpired(InstancePtr) \ + ((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_ISR_OFFSET) & \ + XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK) + +/****************************************************************************/ +/** +* +* Re-start the watchdog timer. This macro will read the watchdog load register +* and write the same value to load register to update the counter register. +* An application needs to call this function periodically to keep the watchdog +* from asserting the WDRESETREQ reset request output pin. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_RestartWdt(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_RestartWdt(InstancePtr) \ + XScuWdt_LoadWdt((InstancePtr), \ + (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_LOAD_OFFSET))) + +/****************************************************************************/ +/** +* +* Write to the watchdog timer load register. This will also update the +* watchdog counter register with the new value. This macro can be used to +* change the time-out value. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* @param Value is the value to be written to the Watchdog Load register. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value) +* +******************************************************************************/ +#define XScuWdt_LoadWdt(InstancePtr, Value) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_LOAD_OFFSET, (Value)) + +/****************************************************************************/ +/** +* +* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the +* Watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_SetWdMode(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_SetWdMode(InstancePtr) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET, \ + (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET) | \ + (XSCUWDT_CONTROL_WD_MODE_MASK))) + +/****************************************************************************/ +/** +* +* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321 +* successively to the Watchdog Disable Register. +* The software must write 0x12345678 and 0x87654321 successively to the +* Watchdog Disable Register so that the watchdog mode bit in the Watchdog +* Control Register is set to zero. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_SetTimerMode(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_SetTimerMode(InstancePtr) \ +{ \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE1); \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_DISABLE_OFFSET, \ + XSCUWDT_DISABLE_VALUE2); \ +} + +/****************************************************************************/ +/** +* +* Get the contents of the watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return Contents of the watchdog control register. +* +* @note C-style signature: + u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_GetControlReg(InstancePtr) \ + XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET) + +/****************************************************************************/ +/** +* +* Write to the watchdog control register. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* @param ControlReg is the value to be written to the watchdog control +* register. +* +* @return None. +* +* @note C-style signature: + void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg) +* +******************************************************************************/ +#define XScuWdt_SetControlReg(InstancePtr, ControlReg) \ + XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr, \ + XSCUWDT_CONTROL_OFFSET, (ControlReg)) + +/****************************************************************************/ +/** +* +* Enable auto-reload mode. +* +* @param InstancePtr is a pointer to the XScuWdt instance. +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr) +* +******************************************************************************/ +#define XScuWdt_EnableAutoReload(InstancePtr) \ + XScuWdt_SetControlReg((InstancePtr), \ + (XScuWdt_GetControlReg(InstancePtr) | \ + XSCUWDT_CONTROL_AUTO_RELOAD_MASK)) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xscuwdt_sinit.c. + */ +XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xscuwdt_selftest.c + */ +s32 XScuWdt_SelfTest(XScuWdt *InstancePtr); + +/* + * Interface functions in xscuwdt.c + */ +s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr, + XScuWdt_Config *ConfigPtr, u32 EffectiveAddress); + +void XScuWdt_Start(XScuWdt *InstancePtr); + +void XScuWdt_Stop(XScuWdt *InstancePtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h new file mode 100644 index 0000000..2067d3a --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h @@ -0,0 +1,182 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xscuwdt_hw.h +* @addtogroup scuwdt_v2_1 +* @{ +* +* This file contains the hardware interface to the Xilinx SCU private Watch Dog +* Timer (XSCUWDT). +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+*                    of 0x20 as the base address obtained from the tools
+*		     starts at 0x20.
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*
    +* +******************************************************************************/ +#ifndef XSCUWDT_HW_H /* prevent circular inclusions */ +#define XSCUWDT_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" +#include "xil_assert.h" +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device. The WDT registers start at + * an offset 0x20 + * @{ + */ + +#define XSCUWDT_LOAD_OFFSET 0x00U /**< Watchdog Load Register */ +#define XSCUWDT_COUNTER_OFFSET 0x04U /**< Watchdog Counter Register */ +#define XSCUWDT_CONTROL_OFFSET 0x08U /**< Watchdog Control Register */ +#define XSCUWDT_ISR_OFFSET 0x0CU /**< Watchdog Interrupt Status Register */ +#define XSCUWDT_RST_STS_OFFSET 0x10U /**< Watchdog Reset Status Register */ +#define XSCUWDT_DISABLE_OFFSET 0x14U /**< Watchdog Disable Register */ +/* @} */ + +/** @name Watchdog Control register + * This register bits control the prescaler, WD/Timer mode, Intr enable, + * auto-reload, watchdog enable. + * @{ + */ + +#define XSCUWDT_CONTROL_PRESCALER_MASK 0x0000FF00U /**< Prescaler */ +#define XSCUWDT_CONTROL_PRESCALER_SHIFT 8U +#define XSCUWDT_CONTROL_WD_MODE_MASK 0x00000008U /**< Watchdog/Timer mode */ +#define XSCUWDT_CONTROL_IT_ENABLE_MASK 0x00000004U /**< Intr enable (in + timer mode) */ +#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in + timer mode) */ +#define XSCUWDT_CONTROL_WD_ENABLE_MASK 0x00000001U /**< Watchdog enable */ +/* @} */ + +/** @name Interrupt Status register + * This register indicates the Counter register has reached zero in Counter + * mode. + * @{ + */ + +#define XSCUWDT_ISR_EVENT_FLAG_MASK 0x00000001U /**< Event flag */ +/*@}*/ + +/** @name Reset Status register + * This register indicates the Counter register has reached zero in Watchdog + * mode and a reset request is sent. + * @{ + */ + +#define XSCUWDT_RST_STS_RESET_FLAG_MASK 0x00000001U /**< Time out occured */ +/*@}*/ + +/** @name Disable register + * This register is used to switch from watchdog mode to timer mode. + * The software must write 0x12345678 and 0x87654321 successively to the + * Watchdog Disable Register so that the watchdog mode bit in the Watchdog + * Control Register is set to zero. + * @{ + */ +#define XSCUWDT_DISABLE_VALUE1 0x12345678U /**< Watchdog mode disable + value 1 */ +#define XSCUWDT_DISABLE_VALUE2 0x87654321U /**< Watchdog mode disable + value 2 */ +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XScuWdt_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + ((u32)RegOffset)) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps.h new file mode 100644 index 0000000..b8d979d --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps.h @@ -0,0 +1,280 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsdps.h +* @addtogroup sdps_v3_5 +* @{ +* @details +* +* This file contains the implementation of XSdPs driver. +* This driver is used initialize read from and write to the SD card. +* Features such as switching bus width to 4-bit and switching to high speed, +* changing clock frequency, block size etc. are supported. +* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however +* is done using 1-bit bus width and 400KHz clock frequency. +* SD commands are classified as broadcast and addressed. Commands can be +* those with response only (using only command line) or +* response + data (using command and data lines). +* Only one command can be sent at a time. During a data transfer however, +* when dsta lines are in use, certain commands (which use only the command +* line) can be sent, most often to obtain status. +* This driver does not support multi card slots at present. +* +* Intialization: +* This includes initialization on the host controller side to select +* clock frequency, bus power and default transfer related parameters. +* The default voltage is 3.3V. +* On the SD card side, the initialization and identification state diagram is +* implemented. This resets the card, gives it a unique address/ID and +* identifies key card related specifications. +* +* Data transfer: +* The SD card is put in tranfer state to read from or write to it. +* The default block size is 512 bytes and if supported, +* default bus width is 4-bit and bus speed is High speed. +* The read and write functions are implemented in polled mode using ADMA2. +* +* At any point, when key parameters such as block size or +* clock/speed or bus width are modified, this driver takes care of +* maintaining the same selection on host and card. +* All error bits in host controller are monitored by the driver and in the +* event one of them is set, driver will clear the interrupt status and +* communicate failure to the upper layer. +* +* File system use: +* This driver can be used with xilffs library to read and write files to SD. +* (Please refer to procedure in diskio.c). The file system read/write example +* in polled mode can used for reference. +* +* There is no example for using SD driver without file system at present. +* However, the driver can be used without the file system. The glue layer +* in filesytem can be used as reference for the same. The block count +* passed to the read/write function in one call is limited by the ADMA2 +* descriptor table and hence care will have to be taken to call read/write +* API's in a loop for large file sizes. +* +* Interrupt mode is not supported because it offers no improvement when used +* with file system. +* +* eMMC support: +* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. +* The features of eMMC supported by the driver will depend on those supported +* by the host controller. The current driver supports read/write on eMMC card +* using 4-bit and high speed mode currently. +* +* Features not supported include - card write protect, password setting, +* lock/unlock, interrupts, SDMA mode, programmed I/O mode and +* 64-bit addressed ADMA2, erase/pre-erase commands. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     05/17/17 Add support for 64bit DMA addressing
+* 	mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*       mn     08/17/17 Enabled CCI support for A53 by adding cache coherency
+*                       information.
+*       mn     09/06/17 Resolved compilation errors with IAR toolchain
+*
+*
    +* +******************************************************************************/ + + +#ifndef SDPS_H_ +#define SDPS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "xil_printf.h" +#include "xil_cache.h" +#include "xstatus.h" +#include "xsdps_hw.h" +#include "xplatform_info.h" +#include + +/************************** Constant Definitions *****************************/ + +#define XSDPS_CT_ERROR 0x2U /**< Command timeout flag */ +#define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */ + +/**************************** Type Definitions *******************************/ + +typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ + u32 InputClockHz; /**< Input clock frequency */ + u32 CardDetect; /**< Card Detect */ + u32 WriteProtect; /**< Write Protect */ + u32 BusWidth; /**< Bus Width */ + u32 BankNumber; /**< MIO Bank selection for SD */ + u32 HasEMIO; /**< If SD is connected to EMIO */ + u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ +} XSdPs_Config; + +/* ADMA2 descriptor table */ +typedef struct { + u16 Attribute; /**< Attributes of descriptor */ + u16 Length; /**< Length of current dma transfer */ +#ifdef __aarch64__ + u64 Address; /**< Address of current dma transfer */ +#else + u32 Address; /**< Address of current dma transfer */ +#endif +#ifdef __ICCARM__ +#pragma data_alignment = 32 +} XSdPs_Adma2Descriptor; +#pragma data_alignment = 4 +#else +} __attribute__((__packed__))XSdPs_Adma2Descriptor; +#endif + +/** + * The XSdPs driver instance data. The user is required to allocate a + * variable of this type for every SD device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XSdPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ + u32 Host_Caps; /**< Capabilities of host controller */ + u32 Host_CapsExt; /**< Extended Capabilities */ + u32 HCS; /**< High capacity support in card */ + u8 CardType; /**< Type of card - SD/MMC/eMMC */ + u8 Card_Version; /**< Card version */ + u8 HC_Version; /**< Host controller version */ + u8 BusWidth; /**< Current operating bus width */ + u32 BusSpeed; /**< Current operating bus speed */ + u8 Switch1v8; /**< 1.8V Switch support */ + u32 CardID[4]; /**< Card ID Register */ + u32 RelCardAddr; /**< Relative Card Address */ + u32 CardSpecData[4]; /**< Card Specific Data Register */ + u32 SectorCount; /**< Sector Count */ + u32 SdCardConfig; /**< Sd Card Configuration Register */ + u32 Mode; /**< Bus Speed Mode */ + XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */ + /**< ADMA Descriptors */ +#ifdef __ICCARM__ +#pragma data_alignment = 32 + XSdPs_Adma2Descriptor Adma2_DescrTbl[32]; +#pragma data_alignment = 4 +#else + XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32))); +#endif +} XSdPs; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); +s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, + u32 EffectiveAddr); +s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); +s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); +s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize); +s32 XSdPs_Select_Card (XSdPs *InstancePtr); +s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq); +s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr); +s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr); +s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR); +s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Pullup(XSdPs *InstancePtr); +s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr); +s32 XSdPs_CardInitialize(XSdPs *InstancePtr); +s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg); +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff); +void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* SD_H_ */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps_hw.h new file mode 100644 index 0000000..c63d8f6 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xsdps_hw.h @@ -0,0 +1,1301 @@ +/****************************************************************************** +* +* Copyright (C) 2013 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xsdps_hw.h +* @addtogroup sdps_v3_5 +* @{ +* +* This header file contains the identifiers and basic HW access driver +* functions (or macros) that can be used to access the device. Other driver +* functions are defined in xsdps.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     08/22/17 Updated for Word Access System support
+*       mn     09/06/17 Added support for ARMCC toolchain
+* 3.4   mn     01/22/18 Separated out SDR104 and HS200 clock defines
+*
+*
    +* +******************************************************************************/ + +#ifndef SD_HW_H_ +#define SD_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets from the base address of an SD device. + * @{ + */ + +#define XSDPS_SDMA_SYS_ADDR_OFFSET 0x00U /**< SDMA System Address + Register */ +#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET XSDPS_SDMA_SYS_ADDR_OFFSET + /**< SDMA System Address + Low Register */ +#define XSDPS_ARGMT2_LO_OFFSET 0x00U /**< Argument2 Low Register */ +#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET 0x02U /**< SDMA System Address + High Register */ +#define XSDPS_ARGMT2_HI_OFFSET 0x02U /**< Argument2 High Register */ + +#define XSDPS_BLK_SIZE_OFFSET 0x04U /**< Block Size Register */ +#define XSDPS_BLK_CNT_OFFSET 0x06U /**< Block Count Register */ +#define XSDPS_ARGMT_OFFSET 0x08U /**< Argument Register */ +#define XSDPS_ARGMT1_LO_OFFSET XSDPS_ARGMT_OFFSET + /**< Argument1 Register */ +#define XSDPS_ARGMT1_HI_OFFSET 0x0AU /**< Argument1 Register */ + +#define XSDPS_XFER_MODE_OFFSET 0x0CU /**< Transfer Mode Register */ +#define XSDPS_CMD_OFFSET 0x0EU /**< Command Register */ +#define XSDPS_RESP0_OFFSET 0x10U /**< Response0 Register */ +#define XSDPS_RESP1_OFFSET 0x14U /**< Response1 Register */ +#define XSDPS_RESP2_OFFSET 0x18U /**< Response2 Register */ +#define XSDPS_RESP3_OFFSET 0x1CU /**< Response3 Register */ +#define XSDPS_BUF_DAT_PORT_OFFSET 0x20U /**< Buffer Data Port */ +#define XSDPS_PRES_STATE_OFFSET 0x24U /**< Present State */ +#define XSDPS_HOST_CTRL1_OFFSET 0x28U /**< Host Control 1 */ +#define XSDPS_POWER_CTRL_OFFSET 0x29U /**< Power Control */ +#define XSDPS_BLK_GAP_CTRL_OFFSET 0x2AU /**< Block Gap Control */ +#define XSDPS_WAKE_UP_CTRL_OFFSET 0x2BU /**< Wake Up Control */ +#define XSDPS_CLK_CTRL_OFFSET 0x2CU /**< Clock Control */ +#define XSDPS_TIMEOUT_CTRL_OFFSET 0x2EU /**< Timeout Control */ +#define XSDPS_SW_RST_OFFSET 0x2FU /**< Software Reset */ +#define XSDPS_NORM_INTR_STS_OFFSET 0x30U /**< Normal Interrupt + Status Register */ +#define XSDPS_ERR_INTR_STS_OFFSET 0x32U /**< Error Interrupt + Status Register */ +#define XSDPS_NORM_INTR_STS_EN_OFFSET 0x34U /**< Normal Interrupt + Status Enable Register */ +#define XSDPS_ERR_INTR_STS_EN_OFFSET 0x36U /**< Error Interrupt + Status Enable Register */ +#define XSDPS_NORM_INTR_SIG_EN_OFFSET 0x38U /**< Normal Interrupt + Signal Enable Register */ +#define XSDPS_ERR_INTR_SIG_EN_OFFSET 0x3AU /**< Error Interrupt + Signal Enable Register */ + +#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET 0x3CU /**< Auto CMD12 Error Status + Register */ +#define XSDPS_HOST_CTRL2_OFFSET 0x3EU /**< Host Control2 Register */ +#define XSDPS_CAPS_OFFSET 0x40U /**< Capabilities Register */ +#define XSDPS_CAPS_EXT_OFFSET 0x44U /**< Capabilities Extended */ +#define XSDPS_MAX_CURR_CAPS_OFFSET 0x48U /**< Maximum Current + Capabilities Register */ +#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET 0x4CU /**< Maximum Current + Capabilities Ext Register */ +#define XSDPS_FE_ERR_INT_STS_OFFSET 0x52U /**< Force Event for + Error Interrupt Status */ +#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET 0x50U /**< Auto CM12 Error Interrupt + Status Register */ +#define XSDPS_ADMA_ERR_STS_OFFSET 0x54U /**< ADMA Error Status + Register */ +#define XSDPS_ADMA_SAR_OFFSET 0x58U /**< ADMA System Address + Register */ +#define XSDPS_ADMA_SAR_EXT_OFFSET 0x5CU /**< ADMA System Address + Extended Register */ +#define XSDPS_PRE_VAL_1_OFFSET 0x60U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_2_OFFSET 0x64U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_3_OFFSET 0x68U /**< Preset Value Register */ +#define XSDPS_PRE_VAL_4_OFFSET 0x6CU /**< Preset Value Register */ +#define XSDPS_BOOT_TOUT_CTRL_OFFSET 0x70U /**< Boot timeout control + register */ + +#define XSDPS_SHARED_BUS_CTRL_OFFSET 0xE0U /**< Shared Bus Control + Register */ +#define XSDPS_SLOT_INTR_STS_OFFSET 0xFCU /**< Slot Interrupt Status + Register */ +#define XSDPS_HOST_CTRL_VER_OFFSET 0xFEU /**< Host Controller Version + Register */ + +/* @} */ + +/** @name Control Register - Host control, Power control, + * Block Gap control and Wakeup control + * + * This register contains bits for various configuration options of + * the SD host controller. Read/Write apart from the reserved bits. + * @{ + */ + +#define XSDPS_HC_LED_MASK 0x00000001U /**< LED Control */ +#define XSDPS_HC_WIDTH_MASK 0x00000002U /**< Bus width */ +#define XSDPS_HC_BUS_WIDTH_4 0x00000002U +#define XSDPS_HC_SPEED_MASK 0x00000004U /**< High Speed */ +#define XSDPS_HC_DMA_MASK 0x00000018U /**< DMA Mode Select */ +#define XSDPS_HC_DMA_SDMA_MASK 0x00000000U /**< SDMA Mode */ +#define XSDPS_HC_DMA_ADMA1_MASK 0x00000008U /**< ADMA1 Mode */ +#define XSDPS_HC_DMA_ADMA2_32_MASK 0x00000010U /**< ADMA2 Mode - 32 bit */ +#define XSDPS_HC_DMA_ADMA2_64_MASK 0x00000018U /**< ADMA2 Mode - 64 bit */ +#define XSDPS_HC_EXT_BUS_WIDTH 0x00000020U /**< Bus width - 8 bit */ +#define XSDPS_HC_CARD_DET_TL_MASK 0x00000040U /**< Card Detect Tst Lvl */ +#define XSDPS_HC_CARD_DET_SD_MASK 0x00000080U /**< Card Detect Sig Det */ + +#define XSDPS_PC_BUS_PWR_MASK 0x00000001U /**< Bus Power Control */ +#define XSDPS_PC_BUS_VSEL_MASK 0x0000000EU /**< Bus Voltage Select */ +#define XSDPS_PC_BUS_VSEL_3V3_MASK 0x0000000EU /**< Bus Voltage 3.3V */ +#define XSDPS_PC_BUS_VSEL_3V0_MASK 0x0000000CU /**< Bus Voltage 3.0V */ +#define XSDPS_PC_BUS_VSEL_1V8_MASK 0x0000000AU /**< Bus Voltage 1.8V */ +#define XSDPS_PC_EMMC_HW_RST_MASK 0x00000010U /**< HW reset for eMMC */ + +#define XSDPS_BGC_STP_REQ_MASK 0x00000001U /**< Block Gap Stop Req */ +#define XSDPS_BGC_CNT_REQ_MASK 0x00000002U /**< Block Gap Cont Req */ +#define XSDPS_BGC_RWC_MASK 0x00000004U /**< Block Gap Rd Wait */ +#define XSDPS_BGC_INTR_MASK 0x00000008U /**< Block Gap Intr */ +#define XSDPS_BGC_SPI_MODE_MASK 0x00000010U /**< Block Gap SPI Mode */ +#define XSDPS_BGC_BOOT_EN_MASK 0x00000020U /**< Block Gap Boot Enb */ +#define XSDPS_BGC_ALT_BOOT_EN_MASK 0x00000040U /**< Block Gap Alt BootEn */ +#define XSDPS_BGC_BOOT_ACK_MASK 0x00000080U /**< Block Gap Boot Ack */ + +#define XSDPS_WC_WUP_ON_INTR_MASK 0x00000001U /**< Wakeup Card Intr */ +#define XSDPS_WC_WUP_ON_INSRT_MASK 0x00000002U /**< Wakeup Card Insert */ +#define XSDPS_WC_WUP_ON_REM_MASK 0x00000004U /**< Wakeup Card Removal */ + +/* @} */ + +/** @name Control Register - Clock control, Timeout control & Software reset + * + * This register contains bits for configuration options of clock, timeout and + * software reset. + * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits. + * @{ + */ + +#define XSDPS_CC_INT_CLK_EN_MASK 0x00000001U +#define XSDPS_CC_INT_CLK_STABLE_MASK 0x00000002U +#define XSDPS_CC_SD_CLK_EN_MASK 0x00000004U +#define XSDPS_CC_SD_CLK_GEN_SEL_MASK 0x00000020U +#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK 0x000000C0U +#define XSDPS_CC_SDCLK_FREQ_SEL_MASK 0x0000FF00U +#define XSDPS_CC_SDCLK_FREQ_D256_MASK 0x00008000U +#define XSDPS_CC_SDCLK_FREQ_D128_MASK 0x00004000U +#define XSDPS_CC_SDCLK_FREQ_D64_MASK 0x00002000U +#define XSDPS_CC_SDCLK_FREQ_D32_MASK 0x00001000U +#define XSDPS_CC_SDCLK_FREQ_D16_MASK 0x00000800U +#define XSDPS_CC_SDCLK_FREQ_D8_MASK 0x00000400U +#define XSDPS_CC_SDCLK_FREQ_D4_MASK 0x00000200U +#define XSDPS_CC_SDCLK_FREQ_D2_MASK 0x00000100U +#define XSDPS_CC_SDCLK_FREQ_BASE_MASK 0x00000000U +#define XSDPS_CC_MAX_DIV_CNT 256U +#define XSDPS_CC_EXT_MAX_DIV_CNT 2046U +#define XSDPS_CC_EXT_DIV_SHIFT 6U + +#define XSDPS_TC_CNTR_VAL_MASK 0x0000000FU + +#define XSDPS_SWRST_ALL_MASK 0x00000001U +#define XSDPS_SWRST_CMD_LINE_MASK 0x00000002U +#define XSDPS_SWRST_DAT_LINE_MASK 0x00000004U + +#define XSDPS_CC_MAX_NUM_OF_DIV 9U +#define XSDPS_CC_DIV_SHIFT 8U + +/* @} */ + +/** @name SD Interrupt Registers + * + * Normal and Error Interrupt Status Register + * This register shows the normal and error interrupt status. + * Status enable register affects reads of this register. + * If Signal enable register is set and the corresponding status bit is set, + * interrupt is generated. + * Write to clear except + * Error_interrupt and Card_Interrupt bits - Read only + * + * Normal and Error Interrupt Status Enable Register + * Setting this register bits enables Interrupt status. + * Read/Write except Fixed_to_0 bit (Read only) + * + * Normal and Error Interrupt Signal Enable Register + * This register is used to select which interrupt status is + * indicated to the Host System as the interrupt. + * Read/Write except Fixed_to_0 bit (Read only) + * + * All three registers have same bit definitions + * @{ + */ + +#define XSDPS_INTR_CC_MASK 0x00000001U /**< Command Complete */ +#define XSDPS_INTR_TC_MASK 0x00000002U /**< Transfer Complete */ +#define XSDPS_INTR_BGE_MASK 0x00000004U /**< Block Gap Event */ +#define XSDPS_INTR_DMA_MASK 0x00000008U /**< DMA Interrupt */ +#define XSDPS_INTR_BWR_MASK 0x00000010U /**< Buffer Write Ready */ +#define XSDPS_INTR_BRR_MASK 0x00000020U /**< Buffer Read Ready */ +#define XSDPS_INTR_CARD_INSRT_MASK 0x00000040U /**< Card Insert */ +#define XSDPS_INTR_CARD_REM_MASK 0x00000080U /**< Card Remove */ +#define XSDPS_INTR_CARD_MASK 0x00000100U /**< Card Interrupt */ +#define XSDPS_INTR_INT_A_MASK 0x00000200U /**< INT A Interrupt */ +#define XSDPS_INTR_INT_B_MASK 0x00000400U /**< INT B Interrupt */ +#define XSDPS_INTR_INT_C_MASK 0x00000800U /**< INT C Interrupt */ +#define XSDPS_INTR_RE_TUNING_MASK 0x00001000U /**< Re-Tuning Interrupt */ +#define XSDPS_INTR_BOOT_ACK_RECV_MASK 0x00002000U /**< Boot Ack Recv + Interrupt */ +#define XSDPS_INTR_BOOT_TERM_MASK 0x00004000U /**< Boot Terminate + Interrupt */ +#define XSDPS_INTR_ERR_MASK 0x00008000U /**< Error Interrupt */ +#define XSDPS_NORM_INTR_ALL_MASK 0x0000FFFFU + +#define XSDPS_INTR_ERR_CT_MASK 0x00000001U /**< Command Timeout + Error */ +#define XSDPS_INTR_ERR_CCRC_MASK 0x00000002U /**< Command CRC Error */ +#define XSDPS_INTR_ERR_CEB_MASK 0x00000004U /**< Command End Bit + Error */ +#define XSDPS_INTR_ERR_CI_MASK 0x00000008U /**< Command Index Error */ +#define XSDPS_INTR_ERR_DT_MASK 0x00000010U /**< Data Timeout Error */ +#define XSDPS_INTR_ERR_DCRC_MASK 0x00000020U /**< Data CRC Error */ +#define XSDPS_INTR_ERR_DEB_MASK 0x00000040U /**< Data End Bit Error */ +#define XSDPS_INTR_ERR_CUR_LMT_MASK 0x00000080U /**< Current Limit Error */ +#define XSDPS_INTR_ERR_AUTO_CMD12_MASK 0x00000100U /**< Auto CMD12 Error */ +#define XSDPS_INTR_ERR_ADMA_MASK 0x00000200U /**< ADMA Error */ +#define XSDPS_INTR_ERR_TR_MASK 0x00001000U /**< Tuning Error */ +#define XSDPS_INTR_VEND_SPF_ERR_MASK 0x0000E000U /**< Vendor Specific + Error */ +#define XSDPS_ERROR_INTR_ALL_MASK 0x0000F3FFU /**< Mask for error bits */ +/* @} */ + +/** @name Block Size and Block Count Register + * + * This register contains the block count for current transfer, + * block size and SDMA buffer size. + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_BLK_SIZE_MASK 0x00000FFFU /**< Transfer Block Size */ +#define XSDPS_SDMA_BUFF_SIZE_MASK 0x00007000U /**< Host SDMA Buffer Size */ +#define XSDPS_BLK_SIZE_1024 0x400U +#define XSDPS_BLK_SIZE_2048 0x800U +#define XSDPS_BLK_CNT_MASK 0x0000FFFFU /**< Block Count for + Current Transfer */ + +/* @} */ + +/** @name Transfer Mode and Command Register + * + * The Transfer Mode register is used to control the data transfers and + * Command register is used for command generation + * Read/Write except for reserved bits. + * @{ + */ + +#define XSDPS_TM_DMA_EN_MASK 0x00000001U /**< DMA Enable */ +#define XSDPS_TM_BLK_CNT_EN_MASK 0x00000002U /**< Block Count Enable */ +#define XSDPS_TM_AUTO_CMD12_EN_MASK 0x00000004U /**< Auto CMD12 Enable */ +#define XSDPS_TM_DAT_DIR_SEL_MASK 0x00000010U /**< Data Transfer + Direction Select */ +#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK 0x00000020U /**< Multi/Single + Block Select */ + +#define XSDPS_CMD_RESP_SEL_MASK 0x00000003U /**< Response Type + Select */ +#define XSDPS_CMD_RESP_NONE_MASK 0x00000000U /**< No Response */ +#define XSDPS_CMD_RESP_L136_MASK 0x00000001U /**< Response length 138 */ +#define XSDPS_CMD_RESP_L48_MASK 0x00000002U /**< Response length 48 */ +#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK 0x00000003U /**< Response length 48 & + check busy after + response */ +#define XSDPS_CMD_CRC_CHK_EN_MASK 0x00000008U /**< Command CRC Check + Enable */ +#define XSDPS_CMD_INX_CHK_EN_MASK 0x00000010U /**< Command Index Check + Enable */ +#define XSDPS_DAT_PRESENT_SEL_MASK 0x00000020U /**< Data Present Select */ +#define XSDPS_CMD_TYPE_MASK 0x000000C0U /**< Command Type */ +#define XSDPS_CMD_TYPE_NORM_MASK 0x00000000U /**< CMD Type - Normal */ +#define XSDPS_CMD_TYPE_SUSPEND_MASK 0x00000040U /**< CMD Type - Suspend */ +#define XSDPS_CMD_TYPE_RESUME_MASK 0x00000080U /**< CMD Type - Resume */ +#define XSDPS_CMD_TYPE_ABORT_MASK 0x000000C0U /**< CMD Type - Abort */ +#define XSDPS_CMD_MASK 0x00003F00U /**< Command Index Mask - + Set to CMD0-63, + AMCD0-63 */ + +/* @} */ + +/** @name Auto CMD Error Status Register + * + * This register is read only register which contains + * information about the error status of Auto CMD 12 and 23. + * Read Only + * @{ + */ +#define XSDPS_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not + executed */ +#define XSDPS_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout + Error */ +#define XSDPS_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit + Error */ +#define XSDPS_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by + Auto CMD12 Error */ +/* @} */ + +/** @name Host Control2 Register + * + * This register contains extended configuration bits. + * Read Write + * @{ + */ +#define XSDPS_HC2_UHS_MODE_MASK 0x0007U /**< UHS Mode select bits */ +#define XSDPS_HC2_UHS_MODE_SDR12_MASK 0x0000U /**< SDR12 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR25_MASK 0x0001U /**< SDR25 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR50_MASK 0x0002U /**< SDR50 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_SDR104_MASK 0x0003U /**< SDR104 UHS Mode */ +#define XSDPS_HC2_UHS_MODE_DDR50_MASK 0x0004U /**< DDR50 UHS Mode */ +#define XSDPS_HC2_1V8_EN_MASK 0x0008U /**< 1.8V Signal Enable */ +#define XSDPS_HC2_DRV_STR_SEL_MASK 0x0030U /**< Driver Strength + Selection */ +#define XSDPS_HC2_DRV_STR_B_MASK 0x0000U /**< Driver Strength B */ +#define XSDPS_HC2_DRV_STR_A_MASK 0x0010U /**< Driver Strength A */ +#define XSDPS_HC2_DRV_STR_C_MASK 0x0020U /**< Driver Strength C */ +#define XSDPS_HC2_DRV_STR_D_MASK 0x0030U /**< Driver Strength D */ +#define XSDPS_HC2_EXEC_TNG_MASK 0x0040U /**< Execute Tuning */ +#define XSDPS_HC2_SAMP_CLK_SEL_MASK 0x0080U /**< Sampling Clock + Selection */ +#define XSDPS_HC2_ASYNC_INTR_EN_MASK 0x4000U /**< Asynchronous Interrupt + Enable */ +#define XSDPS_HC2_PRE_VAL_EN_MASK 0x8000U /**< Preset Value Enable */ + +/* @} */ + +/** @name Capabilities Register + * + * Capabilities register is a read only register which contains + * information about the host controller. + * Sufficient if read once after power on. + * Read Only + * @{ + */ +#define XSDPS_CAP_TOUT_CLK_FREQ_MASK 0x0000003FU /**< Timeout clock freq + select */ +#define XSDPS_CAP_TOUT_CLK_UNIT_MASK 0x00000080U /**< Timeout clock unit - + MHz/KHz */ +#define XSDPS_CAP_MAX_BLK_LEN_MASK 0x00030000U /**< Max block length */ +#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK 0x00000000U /**< Max block 512 bytes */ +#define XSDPS_CAP_MAX_BL_LN_1024_MASK 0x00010000U /**< Max block 1024 bytes */ +#define XSDPS_CAP_MAX_BL_LN_2048_MASK 0x00020000U /**< Max block 2048 bytes */ +#define XSDPS_CAP_MAX_BL_LN_4096_MASK 0x00030000U /**< Max block 4096 bytes */ + +#define XSDPS_CAP_EXT_MEDIA_BUS_MASK 0x00040000U /**< Extended media bus */ +#define XSDPS_CAP_ADMA2_MASK 0x00080000U /**< ADMA2 support */ +#define XSDPS_CAP_HIGH_SPEED_MASK 0x00200000U /**< High speed support */ +#define XSDPS_CAP_SDMA_MASK 0x00400000U /**< SDMA support */ +#define XSDPS_CAP_SUSP_RESUME_MASK 0x00800000U /**< Suspend/Resume + support */ +#define XSDPS_CAP_VOLT_3V3_MASK 0x01000000U /**< 3.3V support */ +#define XSDPS_CAP_VOLT_3V0_MASK 0x02000000U /**< 3.0V support */ +#define XSDPS_CAP_VOLT_1V8_MASK 0x04000000U /**< 1.8V support */ + +#define XSDPS_CAP_SYS_BUS_64_MASK 0x10000000U /**< 64 bit system bus + support */ +/* Spec 2.0 */ +#define XSDPS_CAP_INTR_MODE_MASK 0x08000000U /**< Interrupt mode + support */ +#define XSDPS_CAP_SPI_MODE_MASK 0x20000000U /**< SPI mode */ +#define XSDPS_CAP_SPI_BLOCK_MODE_MASK 0x40000000U /**< SPI block mode */ + + +/* Spec 3.0 */ +#define XSDPS_CAPS_ASYNC_INTR_MASK 0x20000000U /**< Async Interrupt + support */ +#define XSDPS_CAPS_SLOT_TYPE_MASK 0xC0000000U /**< Slot Type */ +#define XSDPS_CAPS_REM_CARD 0x00000000U /**< Removable Slot */ +#define XSDPS_CAPS_EMB_SLOT 0x40000000U /**< Embedded Slot */ +#define XSDPS_CAPS_SHR_BUS 0x80000000U /**< Shared Bus Slot */ + +#define XSDPS_ECAPS_SDR50_MASK 0x00000001U /**< SDR50 Mode support */ +#define XSDPS_ECAPS_SDR104_MASK 0x00000002U /**< SDR104 Mode support */ +#define XSDPS_ECAPS_DDR50_MASK 0x00000004U /**< DDR50 Mode support */ +#define XSDPS_ECAPS_DRV_TYPE_A_MASK 0x00000010U /**< DriverType A support */ +#define XSDPS_ECAPS_DRV_TYPE_C_MASK 0x00000020U /**< DriverType C support */ +#define XSDPS_ECAPS_DRV_TYPE_D_MASK 0x00000040U /**< DriverType D support */ +#define XSDPS_ECAPS_TMR_CNT_MASK 0x00000F00U /**< Timer Count for + Re-tuning */ +#define XSDPS_ECAPS_USE_TNG_SDR50_MASK 0x00002000U /**< SDR50 Mode needs + tuning */ +#define XSDPS_ECAPS_RE_TNG_MODES_MASK 0x0000C000U /**< Re-tuning modes + support */ +#define XSDPS_ECAPS_RE_TNG_MODE1_MASK 0x00000000U /**< Re-tuning mode 1 */ +#define XSDPS_ECAPS_RE_TNG_MODE2_MASK 0x00004000U /**< Re-tuning mode 2 */ +#define XSDPS_ECAPS_RE_TNG_MODE3_MASK 0x00008000U /**< Re-tuning mode 3 */ +#define XSDPS_ECAPS_CLK_MULT_MASK 0x00FF0000U /**< Clock Multiplier value + for Programmable clock + mode */ +#define XSDPS_ECAPS_SPI_MODE_MASK 0x01000000U /**< SPI mode */ +#define XSDPS_ECAPS_SPI_BLK_MODE_MASK 0x02000000U /**< SPI block mode */ + +/* @} */ + +/** @name Present State Register + * + * Gives the current status of the host controller + * Read Only + * @{ + */ + +#define XSDPS_PSR_INHIBIT_CMD_MASK 0x00000001U /**< Command inhibit - CMD */ +#define XSDPS_PSR_INHIBIT_DAT_MASK 0x00000002U /**< Command Inhibit - DAT */ +#define XSDPS_PSR_DAT_ACTIVE_MASK 0x00000004U /**< DAT line active */ +#define XSDPS_PSR_RE_TUNING_REQ_MASK 0x00000008U /**< Re-tuning request */ +#define XSDPS_PSR_WR_ACTIVE_MASK 0x00000100U /**< Write transfer active */ +#define XSDPS_PSR_RD_ACTIVE_MASK 0x00000200U /**< Read transfer active */ +#define XSDPS_PSR_BUFF_WR_EN_MASK 0x00000400U /**< Buffer write enable */ +#define XSDPS_PSR_BUFF_RD_EN_MASK 0x00000800U /**< Buffer read enable */ +#define XSDPS_PSR_CARD_INSRT_MASK 0x00010000U /**< Card inserted */ +#define XSDPS_PSR_CARD_STABLE_MASK 0x00020000U /**< Card state stable */ +#define XSDPS_PSR_CARD_DPL_MASK 0x00040000U /**< Card detect pin level */ +#define XSDPS_PSR_WPS_PL_MASK 0x00080000U /**< Write protect switch + pin level */ +#define XSDPS_PSR_DAT30_SG_LVL_MASK 0x00F00000U /**< Data 3:0 signal lvl */ +#define XSDPS_PSR_CMD_SG_LVL_MASK 0x01000000U /**< Cmd Line signal lvl */ +#define XSDPS_PSR_DAT74_SG_LVL_MASK 0x1E000000U /**< Data 7:4 signal lvl */ + +/* @} */ + +/** @name Maximum Current Capablities Register + * + * This register is read only register which contains + * information about current capabilities at each voltage levels. + * Read Only + * @{ + */ +#define XSDPS_MAX_CUR_CAPS_1V8_MASK 0x00000F00U /**< Maximum Current + Capability at 1.8V */ +#define XSDPS_MAX_CUR_CAPS_3V0_MASK 0x000000F0U /**< Maximum Current + Capability at 3.0V */ +#define XSDPS_MAX_CUR_CAPS_3V3_MASK 0x0000000FU /**< Maximum Current + Capability at 3.3V */ +/* @} */ + + +/** @name Force Event for Auto CMD Error Status Register + * + * This register is write only register which contains + * control bits to generate events for Auto CMD error status. + * Write Only + * @{ + */ +#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK 0x0001U /**< Auto CMD12 Not + executed */ +#define XSDPS_FE_AUTO_CMD_TOUT_MASK 0x0002U /**< Auto CMD Timeout + Error */ +#define XSDPS_FE_AUTO_CMD_CRC_MASK 0x0004U /**< Auto CMD CRC Error */ +#define XSDPS_FE_AUTO_CMD_EB_MASK 0x0008U /**< Auto CMD End Bit + Error */ +#define XSDPS_FE_AUTO_CMD_IND_MASK 0x0010U /**< Auto CMD Index Error */ +#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK 0x0080U /**< Command not issued by + Auto CMD12 Error */ +/* @} */ + + + +/** @name Force Event for Error Interrupt Status Register + * + * This register is write only register which contains + * control bits to generate events of error interrupt status register. + * Write Only + * @{ + */ +#define XSDPS_FE_INTR_ERR_CT_MASK 0x0001U /**< Command Timeout + Error */ +#define XSDPS_FE_INTR_ERR_CCRC_MASK 0x0002U /**< Command CRC Error */ +#define XSDPS_FE_INTR_ERR_CEB_MASK 0x0004U /**< Command End Bit + Error */ +#define XSDPS_FE_INTR_ERR_CI_MASK 0x0008U /**< Command Index Error */ +#define XSDPS_FE_INTR_ERR_DT_MASK 0x0010U /**< Data Timeout Error */ +#define XSDPS_FE_INTR_ERR_DCRC_MASK 0x0020U /**< Data CRC Error */ +#define XSDPS_FE_INTR_ERR_DEB_MASK 0x0040U /**< Data End Bit Error */ +#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK 0x0080U /**< Current Limit Error */ +#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK 0x0100U /**< Auto CMD Error */ +#define XSDPS_FE_INTR_ERR_ADMA_MASK 0x0200U /**< ADMA Error */ +#define XSDPS_FE_INTR_ERR_TR_MASK 0x1000U /**< Target Reponse */ +#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK 0xE000U /**< Vendor Specific + Error */ + +/* @} */ + +/** @name ADMA Error Status Register + * + * This register is read only register which contains + * status information about ADMA errors. + * Read Only + * @{ + */ +#define XSDPS_ADMA_ERR_MM_LEN_MASK 0x04U /**< ADMA Length Mismatch + Error */ +#define XSDPS_ADMA_ERR_STATE_MASK 0x03U /**< ADMA Error State */ +#define XSDPS_ADMA_ERR_STATE_STOP_MASK 0x00U /**< ADMA Error State + STOP */ +#define XSDPS_ADMA_ERR_STATE_FDS_MASK 0x01U /**< ADMA Error State + FDS */ +#define XSDPS_ADMA_ERR_STATE_TFR_MASK 0x03U /**< ADMA Error State + TFR */ +/* @} */ + +/** @name Preset Values Register + * + * This register is read only register which contains + * preset values for each of speed modes. + * Read Only + * @{ + */ +#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK 0x03FFU /**< SDCLK Frequency + Select Value */ +#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK 0x0400U /**< Clock Generator + Mode Select */ +#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK 0xC000U /**< Driver Strength + Select Value */ + +/* @} */ + +/** @name Slot Interrupt Status Register + * + * This register is read only register which contains + * interrupt slot signal for each slot. + * Read Only + * @{ + */ +#define XSDPS_SLOT_INTR_STS_INT_MASK 0x0007U /**< Interrupt Signal + mask */ + +/* @} */ + +/** @name Host Controller Version Register + * + * This register is read only register which contains + * Host Controller and Vendor Specific version. + * Read Only + * @{ + */ +#define XSDPS_HC_VENDOR_VER 0xFF00U /**< Vendor + Specification + version mask */ +#define XSDPS_HC_SPEC_VER_MASK 0x00FFU /**< Host + Specification + version mask */ +#define XSDPS_HC_SPEC_V3 0x0002U +#define XSDPS_HC_SPEC_V2 0x0001U +#define XSDPS_HC_SPEC_V1 0x0000U + +/** @name Block size mask for 512 bytes + * + * Block size mask for 512 bytes - This is the default block size. + * @{ + */ + +#define XSDPS_BLK_SIZE_512_MASK 0x200U + +/* @} */ + +/** @name Commands + * + * Constant definitions for commands and response related to SD + * @{ + */ + +#define XSDPS_APP_CMD_PREFIX 0x8000U +#define CMD0 0x0000U +#define CMD1 0x0100U +#define CMD2 0x0200U +#define CMD3 0x0300U +#define CMD4 0x0400U +#define CMD5 0x0500U +#define CMD6 0x0600U +#define ACMD6 (XSDPS_APP_CMD_PREFIX + 0x0600U) +#define CMD7 0x0700U +#define CMD8 0x0800U +#define CMD9 0x0900U +#define CMD10 0x0A00U +#define CMD11 0x0B00U +#define CMD12 0x0C00U +#define ACMD13 (XSDPS_APP_CMD_PREFIX + 0x0D00U) +#define CMD16 0x1000U +#define CMD17 0x1100U +#define CMD18 0x1200U +#define CMD19 0x1300U +#define CMD21 0x1500U +#define CMD23 0x1700U +#define ACMD23 (XSDPS_APP_CMD_PREFIX + 0x1700U) +#define CMD24 0x1800U +#define CMD25 0x1900U +#define CMD41 0x2900U +#define ACMD41 (XSDPS_APP_CMD_PREFIX + 0x2900U) +#define ACMD42 (XSDPS_APP_CMD_PREFIX + 0x2A00U) +#define ACMD51 (XSDPS_APP_CMD_PREFIX + 0x3300U) +#define CMD52 0x3400U +#define CMD55 0x3700U +#define CMD58 0x3A00U + +#define RESP_NONE (u32)XSDPS_CMD_RESP_NONE_MASK +#define RESP_R1 (u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \ + (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R1B (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + +#define RESP_R2 (u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK +#define RESP_R3 (u32)XSDPS_CMD_RESP_L48_MASK + +#define RESP_R6 (u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \ + (u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK + +/* @} */ + +/* Card Interface Conditions Definitions */ +#define XSDPS_CIC_CHK_PATTERN 0xAAU +#define XSDPS_CIC_VOLT_MASK (0xFU<<8) +#define XSDPS_CIC_VOLT_2V7_3V6 (1U<<8) +#define XSDPS_CIC_VOLT_LOW (1U<<9) + +/* Operation Conditions Register Definitions */ +#define XSDPS_OCR_PWRUP_STS (1U<<31) +#define XSDPS_OCR_CC_STS (1U<<30) +#define XSDPS_OCR_S18 (1U<<24) +#define XSDPS_OCR_3V5_3V6 (1U<<23) +#define XSDPS_OCR_3V4_3V5 (1U<<22) +#define XSDPS_OCR_3V3_3V4 (1U<<21) +#define XSDPS_OCR_3V2_3V3 (1U<<20) +#define XSDPS_OCR_3V1_3V2 (1U<<19) +#define XSDPS_OCR_3V0_3V1 (1U<<18) +#define XSDPS_OCR_2V9_3V0 (1U<<17) +#define XSDPS_OCR_2V8_2V9 (1U<<16) +#define XSDPS_OCR_2V7_2V8 (1U<<15) +#define XSDPS_OCR_1V7_1V95 (1U<<7) +#define XSDPS_OCR_HIGH_VOL 0x00FF8000U +#define XSDPS_OCR_LOW_VOL 0x00000080U + +/* SD Card Configuration Register Definitions */ +#define XSDPS_SCR_REG_LEN 8U +#define XSDPS_SCR_STRUCT_MASK (0xFU<<28) +#define XSDPS_SCR_SPEC_MASK (0xFU<<24) +#define XSDPS_SCR_SPEC_1V0 0U +#define XSDPS_SCR_SPEC_1V1 (1U<<24) +#define XSDPS_SCR_SPEC_2V0_3V0 (2U<<24) +#define XSDPS_SCR_MEM_VAL_AF_ERASE (1U<<23) +#define XSDPS_SCR_SEC_SUPP_MASK (7U<<20) +#define XSDPS_SCR_SEC_SUPP_NONE 0U +#define XSDPS_SCR_SEC_SUPP_1V1 (2U<<20) +#define XSDPS_SCR_SEC_SUPP_2V0 (3U<<20) +#define XSDPS_SCR_SEC_SUPP_3V0 (4U<<20) +#define XSDPS_SCR_BUS_WIDTH_MASK (0xFU<<16) +#define XSDPS_SCR_BUS_WIDTH_1 (1U<<16) +#define XSDPS_SCR_BUS_WIDTH_4 (4U<<16) +#define XSDPS_SCR_SPEC3_MASK (1U<<12) +#define XSDPS_SCR_SPEC3_2V0 0U +#define XSDPS_SCR_SPEC3_3V0 (1U<<12) +#define XSDPS_SCR_CMD_SUPP_MASK 0x3U +#define XSDPS_SCR_CMD23_SUPP (1U<<1) +#define XSDPS_SCR_CMD20_SUPP (1U<<0) + +/* Card Status Register Definitions */ +#define XSDPS_CD_STS_OUT_OF_RANGE (1U<<31) +#define XSDPS_CD_STS_ADDR_ERR (1U<<30) +#define XSDPS_CD_STS_BLK_LEN_ERR (1U<<29) +#define XSDPS_CD_STS_ER_SEQ_ERR (1U<<28) +#define XSDPS_CD_STS_ER_PRM_ERR (1U<<27) +#define XSDPS_CD_STS_WP_VIO (1U<<26) +#define XSDPS_CD_STS_IS_LOCKED (1U<<25) +#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL (1U<<24) +#define XSDPS_CD_STS_CMD_CRC_ERR (1U<<23) +#define XSDPS_CD_STS_ILGL_CMD (1U<<22) +#define XSDPS_CD_STS_CARD_ECC_FAIL (1U<<21) +#define XSDPS_CD_STS_CC_ERR (1U<<20) +#define XSDPS_CD_STS_ERR (1U<<19) +#define XSDPS_CD_STS_CSD_OVRWR (1U<<16) +#define XSDPS_CD_STS_WP_ER_SKIP (1U<<15) +#define XSDPS_CD_STS_CARD_ECC_DIS (1U<<14) +#define XSDPS_CD_STS_ER_RST (1U<<13) +#define XSDPS_CD_STS_CUR_STATE (0xFU<<9) +#define XSDPS_CD_STS_RDY_FOR_DATA (1U<<8) +#define XSDPS_CD_STS_APP_CMD (1U<<5) +#define XSDPS_CD_STS_AKE_SEQ_ERR (1U<<2) + +/* Switch Function Definitions CMD6 */ +#define XSDPS_SWITCH_SD_RESP_LEN 64U + +#define XSDPS_SWITCH_FUNC_SWITCH (1U<<31) +#define XSDPS_SWITCH_FUNC_CHECK 0U + +#define XSDPS_MODE_FUNC_GRP1 1U +#define XSDPS_MODE_FUNC_GRP2 2U +#define XSDPS_MODE_FUNC_GRP3 3U +#define XSDPS_MODE_FUNC_GRP4 4U +#define XSDPS_MODE_FUNC_GRP5 5U +#define XSDPS_MODE_FUNC_GRP6 6U + +#define XSDPS_FUNC_GRP_DEF_VAL 0xFU +#define XSDPS_FUNC_ALL_GRP_DEF_VAL 0xFFFFFFU + +#define XSDPS_ACC_MODE_DEF_SDR12 0U +#define XSDPS_ACC_MODE_HS_SDR25 1U +#define XSDPS_ACC_MODE_SDR50 2U +#define XSDPS_ACC_MODE_SDR104 3U +#define XSDPS_ACC_MODE_DDR50 4U + +#define XSDPS_CMD_SYS_ARG_SHIFT 4U +#define XSDPS_CMD_SYS_DEF 0U +#define XSDPS_CMD_SYS_eC 1U +#define XSDPS_CMD_SYS_OTP 3U +#define XSDPS_CMD_SYS_ASSD 4U +#define XSDPS_CMD_SYS_VEND 5U + +#define XSDPS_DRV_TYPE_ARG_SHIFT 8U +#define XSDPS_DRV_TYPE_B 0U +#define XSDPS_DRV_TYPE_A 1U +#define XSDPS_DRV_TYPE_C 2U +#define XSDPS_DRV_TYPE_D 3U + +#define XSDPS_CUR_LIM_ARG_SHIFT 12U +#define XSDPS_CUR_LIM_200 0U +#define XSDPS_CUR_LIM_400 1U +#define XSDPS_CUR_LIM_600 2U +#define XSDPS_CUR_LIM_800 3U + +#define CSD_SPEC_VER_MASK 0x3C0000U +#define READ_BLK_LEN_MASK 0x00000F00U +#define C_SIZE_MULT_MASK 0x00000380U +#define C_SIZE_LOWER_MASK 0xFFC00000U +#define C_SIZE_UPPER_MASK 0x00000003U +#define CSD_STRUCT_MASK 0x00C00000U +#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U + +/* EXT_CSD field definitions */ +#define XSDPS_EXT_CSD_SIZE 512U + +#define EXT_CSD_WR_REL_PARAM_EN (1U<<2) + +#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10U) +#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04U) +#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01U) + +#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7U) +#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1U) +#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3U) +#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4U) + +#define EXT_CSD_PART_SUPPORT_PART_EN (0x1U) + +#define EXT_CSD_CMD_SET_NORMAL (1U<<0) +#define EXT_CSD_CMD_SET_SECURE (1U<<1) +#define EXT_CSD_CMD_SET_CPSECURE (1U<<2) + +#define EXT_CSD_CARD_TYPE_26 (1U<<0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1U<<1) /* Card can run at 52MHz */ +#define EXT_CSD_CARD_TYPE_MASK 0x3FU /* Mask out reserved bits */ +#define EXT_CSD_CARD_TYPE_DDR_1_8V (1U<<2) /* Card can run at 52MHz */ + /* DDR mode @1.8V or 3V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_1_2V (1U<<3) /* Card can run at 52MHz */ + /* DDR mode @1.2V I/O */ +#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ + | EXT_CSD_CARD_TYPE_DDR_1_2V) +#define EXT_CSD_CARD_TYPE_SDR_1_8V (1U<<4) /* Card can run at 200MHz */ +#define EXT_CSD_CARD_TYPE_SDR_1_2V (1U<<5) /* Card can run at 200MHz */ + /* SDR mode @1.2V I/O */ +#define EXT_CSD_BUS_WIDTH_BYTE 183U +#define EXT_CSD_BUS_WIDTH_1_BIT 0U /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4_BIT 1U /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8_BIT 2U /* Card is in 8 bit mode */ +#define EXT_CSD_BUS_WIDTH_DDR_4_BIT 5U /* Card is in 4 bit DDR mode */ +#define EXT_CSD_BUS_WIDTH_DDR_8_BIT 6U /* Card is in 8 bit DDR mode */ + +#define EXT_CSD_HS_TIMING_BYTE 185U +#define EXT_CSD_HS_TIMING_DEF 0U +#define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */ +#define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */ + +#define EXT_CSD_RST_N_FUN_BYTE 162U +#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */ +#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */ +#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */ + +#define XSDPS_EXT_CSD_CMD_SET 0U +#define XSDPS_EXT_CSD_SET_BITS 1U +#define XSDPS_EXT_CSD_CLR_BITS 2U +#define XSDPS_EXT_CSD_WRITE_BYTE 3U + +#define XSDPS_MMC_DEF_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_DEF << 8)) + +#define XSDPS_MMC_HIGH_SPEED_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HIGH << 8)) + +#define XSDPS_MMC_HS200_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \ + | ((u32)EXT_CSD_HS_TIMING_HS200 << 8)) + +#define XSDPS_MMC_1_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8)) + +#define XSDPS_MMC_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8)) + +#define XSDPS_MMC_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8)) + +#define XSDPS_MMC_DDR_4_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8)) + +#define XSDPS_MMC_DDR_8_BIT_BUS_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ + | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) + +#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ + | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) + +#define XSDPS_MMC_DELAY_FOR_SWITCH 1000U + +/* @} */ + +/* @400KHz, in usec */ +#define XSDPS_74CLK_DELAY 2960U +#define XSDPS_100CLK_DELAY 4000U +#define XSDPS_INIT_DELAY 10000U + +#define XSDPS_DEF_VOLT_LVL XSDPS_PC_BUS_VSEL_3V0_MASK +#define XSDPS_CARD_DEF_ADDR 0x1234U + +#define XSDPS_CARD_SD 1U +#define XSDPS_CARD_MMC 2U +#define XSDPS_CARD_SDIO 3U +#define XSDPS_CARD_SDCOMBO 4U +#define XSDPS_CHIP_EMMC 5U + + +/** @name ADMA2 Descriptor related definitions + * + * ADMA2 Descriptor related definitions + * @{ + */ + +#define XSDPS_DESC_MAX_LENGTH 65536U + +#define XSDPS_DESC_VALID (0x1U << 0) +#define XSDPS_DESC_END (0x1U << 1) +#define XSDPS_DESC_INT (0x1U << 2) +#define XSDPS_DESC_TRAN (0x2U << 4) + +/* @} */ + +/* For changing clock frequencies */ +#define XSDPS_CLK_400_KHZ 400000U /**< 400 KHZ */ +#define XSDPS_CLK_50_MHZ 50000000U /**< 50 MHZ */ +#define XSDPS_CLK_52_MHZ 52000000U /**< 52 MHZ */ +#define XSDPS_SD_VER_1_0 0x1U /**< SD ver 1 */ +#define XSDPS_SD_VER_2_0 0x2U /**< SD ver 2 */ +#define XSDPS_SCR_BLKCNT 1U +#define XSDPS_SCR_BLKSIZE 8U +#define XSDPS_1_BIT_WIDTH 0x1U +#define XSDPS_4_BIT_WIDTH 0x2U +#define XSDPS_8_BIT_WIDTH 0x3U +#define XSDPS_UHS_SPEED_MODE_SDR12 0x0U +#define XSDPS_UHS_SPEED_MODE_SDR25 0x1U +#define XSDPS_UHS_SPEED_MODE_SDR50 0x2U +#define XSDPS_UHS_SPEED_MODE_SDR104 0x3U +#define XSDPS_UHS_SPEED_MODE_DDR50 0x4U +#define XSDPS_HIGH_SPEED_MODE 0x5U +#define XSDPS_DEFAULT_SPEED_MODE 0x6U +#define XSDPS_HS200_MODE 0x7U +#define XSDPS_DDR52_MODE 0x4U +#define XSDPS_SWITCH_CMD_BLKCNT 1U +#define XSDPS_SWITCH_CMD_BLKSIZE 64U +#define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U +#define XSDPS_SWITCH_CMD_HS_SET 0x80FFFFF1U +#define XSDPS_SWITCH_CMD_SDR12_SET 0x80FFFFF0U +#define XSDPS_SWITCH_CMD_SDR25_SET 0x80FFFFF1U +#define XSDPS_SWITCH_CMD_SDR50_SET 0x80FFFFF2U +#define XSDPS_SWITCH_CMD_SDR104_SET 0x80FFFFF3U +#define XSDPS_SWITCH_CMD_DDR50_SET 0x80FFFFF4U +#define XSDPS_EXT_CSD_CMD_BLKCNT 1U +#define XSDPS_EXT_CSD_CMD_BLKSIZE 512U +#define XSDPS_TUNING_CMD_BLKCNT 1U +#define XSDPS_TUNING_CMD_BLKSIZE 64U + +#define XSDPS_HIGH_SPEED_MAX_CLK 50000000U +#define XSDPS_UHS_SDR104_MAX_CLK 208000000U +#define XSDPS_UHS_SDR50_MAX_CLK 100000000U +#define XSDPS_UHS_DDR50_MAX_CLK 50000000U +#define XSDPS_UHS_SDR25_MAX_CLK 50000000U +#define XSDPS_UHS_SDR12_MAX_CLK 25000000U + +#define SD_DRIVER_TYPE_B 0x01U +#define SD_DRIVER_TYPE_A 0x02U +#define SD_DRIVER_TYPE_C 0x04U +#define SD_DRIVER_TYPE_D 0x08U +#define SD_SET_CURRENT_LIMIT_200 0U +#define SD_SET_CURRENT_LIMIT_400 1U +#define SD_SET_CURRENT_LIMIT_600 2U +#define SD_SET_CURRENT_LIMIT_800 3U + +#define SD_MAX_CURRENT_200 (1U << SD_SET_CURRENT_LIMIT_200) +#define SD_MAX_CURRENT_400 (1U << SD_SET_CURRENT_LIMIT_400) +#define SD_MAX_CURRENT_600 (1U << SD_SET_CURRENT_LIMIT_600) +#define SD_MAX_CURRENT_800 (1U << SD_SET_CURRENT_LIMIT_800) + +#define XSDPS_SD_SDR12_MAX_CLK 25000000U +#define XSDPS_SD_SDR25_MAX_CLK 50000000U +#define XSDPS_SD_SDR50_MAX_CLK 100000000U +#define XSDPS_SD_DDR50_MAX_CLK 50000000U +#define XSDPS_SD_SDR104_MAX_CLK 208000000U +/* + * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller + * than the clock value coming from the core. This value is kept to safely + * switch to SDR104 mode if the SD card supports it. + */ +#define XSDPS_SD_INPUT_MAX_CLK 175000000U + +#define XSDPS_MMC_HS200_MAX_CLK 200000000U +#define XSDPS_MMC_HSD_MAX_CLK 52000000U +#define XSDPS_MMC_DDR_MAX_CLK 52000000U + +#define XSDPS_CARD_STATE_IDLE 0U +#define XSDPS_CARD_STATE_RDY 1U +#define XSDPS_CARD_STATE_IDEN 2U +#define XSDPS_CARD_STATE_STBY 3U +#define XSDPS_CARD_STATE_TRAN 4U +#define XSDPS_CARD_STATE_DATA 5U +#define XSDPS_CARD_STATE_RCV 6U +#define XSDPS_CARD_STATE_PROG 7U +#define XSDPS_CARD_STATE_DIS 8U +#define XSDPS_CARD_STATE_BTST 9U +#define XSDPS_CARD_STATE_SLP 10U + +#define XSDPS_SLOT_REM 0U +#define XSDPS_SLOT_EMB 1U + +#define XSDPS_WIDTH_8 8U +#define XSDPS_WIDTH_4 4U + + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +#define SD0_ITAPDLY_SEL_MASK 0x000000FFU +#define SD0_OTAPDLY_SEL_MASK 0x0000003FU +#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U +#define SD1_OTAPDLY_SEL_MASK 0x003F0000U +#define SD_DLL_CTRL 0x00000358U +#define SD_ITAPDLY 0x00000314U +#define SD_OTAPDLY 0x00000318U +#define SD0_DLL_RST 0x00000004U +#define SD1_DLL_RST 0x00040000U +#define SD0_ITAPCHGWIN 0x00000200U +#define SD0_ITAPDLYENA 0x00000100U +#define SD0_OTAPDLYENA 0x00000040U +#define SD1_ITAPCHGWIN 0x02000000U +#define SD1_ITAPDLYENA 0x01000000U +#define SD1_OTAPDLYENA 0x00400000U + +#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U +#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U +#define SD0_ITAPDLYSEL_SD50 0x00000014U +#define SD0_OTAPDLYSEL_SD50 0x00000003U +#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU +#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U +#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U +#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U +#define SD0_ITAPDLYSEL_HSD 0x00000015U +#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U +#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U + +#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U +#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U +#define SD1_ITAPDLYSEL_SD50 0x00140000U +#define SD1_OTAPDLYSEL_SD50 0x00030000U +#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U +#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U +#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U +#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U +#define SD1_ITAPDLYSEL_HSD 0x00150000U +#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U +#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U + +#endif + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define XSdPs_In64 Xil_In64 +#define XSdPs_Out64 Xil_Out64 + +#define XSdPs_In32 Xil_In32 +#define XSdPs_Out32 Xil_Out32 + +#define XSdPs_In16 Xil_In16 +#define XSdPs_Out16 Xil_Out16 + +#define XSdPs_In8 Xil_In8 +#define XSdPs_Out8 Xil_Out8 + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg64(InstancePtr, RegOffset) \ + XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset, +* u64 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \ + XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \ + (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +#define XSdPs_ReadReg(BaseAddress, RegOffset) \ + XSdPs_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +* +******************************************************************************/ +#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue)) + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u16)Reg; +#else + return XSdPs_In16((BaseAddress) + (RegOffset)); +#endif +} + +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ + +static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} + +/****************************************************************************/ +/** +* Read a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to the target register. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) +* +******************************************************************************/ +static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u8)Reg; +#else + return XSdPs_In8((BaseAddress) + (RegOffset)); +#endif +} +/***************************************************************************/ +/** +* Write to a register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the 1st register of the +* device to target register. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} +/***************************************************************************/ +/** +* Macro to get present status register +* +* @param BaseAddress contains the base address of the device. +* +* @return None. +* +* @note C-Style signature: +* void XSdPs_WriteReg(u32 BaseAddress, int RegOffset, +* u8 RegisterValue) +* +******************************************************************************/ +#define XSdPs_GetPresentStatusReg(BaseAddress) \ + XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET)) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* SD_HW_H_ */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xstatus.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xstatus.h new file mode 100644 index 0000000..9937475 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xstatus.h @@ -0,0 +1,535 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* @addtogroup common_status_codes Xilinx® software status codes +* +* The xstatus.h file contains the Xilinx® software status codes.These codes are +* used throughout the Xilinx device drivers. +* +* @{ +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ +/** +@name Common Status Codes for All Device Drivers +@{ +*/ +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /*!< An error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /*!< An error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /*!< The device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /*!< There was no data available */ +#define XST_REGISTER_ERROR 14L /*!< A register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /*!< The device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */ +#define XST_NO_CALLBACK 18L /*!< A callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /*!< Device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /*!< Device is busy */ +#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /*!< Used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /*!< Used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /*!< Driver defined error */ +#define XST_RECV_ERROR 27L /*!< Generic receive error */ +#define XST_SEND_ERROR 28L /*!< Generic transmit error */ +#define XST_NOT_ENABLED 29L /*!< A requested service is not + available because it has not + been enabled */ +/** @} */ +/***************** Utility Component statuses 401 - 500 *********************/ +/** +@name Utility Component Status Codes 401 - 500 +@{ +*/ +#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */ + +/** @} */ +/***************** Common Components statuses 501 - 1000 *********************/ +/** +@name Packet Fifo Status Codes 501 - 510 +@{ +*/ +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting + * empty and full simultaneously + */ +/** @} */ +/** +@name DMA Status Codes 511 - 530 +@{ +*/ +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor + error */ +/** @} */ +/** +@name IPIF Status Codes Codes 531 - 550 +@{ +*/ +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /*!< Generic ipif error */ +/** @} */ + +/****************** Device specific statuses 1001 - 4095 *********************/ +/** +@name Ethernet Status Codes 1001 - 1050 +@{ +*/ +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */ +#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late + * collision on polled send */ +/** @} */ +/** +@name UART Status Codes 1051 - 1075 +@{ +*/ +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/** @} */ +/** +@name IIC Status Codes 1076 - 1100 +@{ +*/ +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */ +#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */ +/** @} */ +/** +@name ATMC Status Codes 1101 - 1125 +@{ +*/ +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ +/** @} */ +/** +@name Flash Status Codes 1126 - 1150 +@{ +*/ +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */ +/** @} */ +/** +@name SPI Status Codes 1151 - 1175 +@{ +*/ +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */ +#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the + device for status */ +/** @} */ +/** +@name OPB Arbiter Status Codes 1176 - 1200 +@{ +*/ +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ +/** @} */ +/** +@name INTC Status Codes 1201 - 1225 +@{ +*/ +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */ +/** @} */ +/** +@name TmrCtr Status Codes 1226 - 1250 +@{ +*/ +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */ +/** @} */ +/** +@name WdtTb Status Codes 1251 - 1275 +@{ +*/ +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L +/** @} */ +/** +@name PlbArb status Codes 1276 - 1300 +@{ +*/ +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L +/** @} */ +/** +@name Plb2Opb Status Codes 1301 - 1325 +@{ +*/ +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L +/** @} */ +/** +@name Opb2Plb Status 1326 - 1350 +@{ +*/ +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L +/** @} */ +/** +@name SysAce Status Codes 1351 - 1360 +@{ +*/ +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */ +/** @} */ +/** +@name PCI Bridge Status Codes 1361 - 1375 +@{ +*/ +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L +/** @} */ +/** +@name FlexRay Constants 1400 - 1409 +@{ +*/ +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 +/** @} */ +/** +@name USB constants 1410 - 1420 +@{ +*/ +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 +/** @} */ +/** +@name HWICAP constants 1421 - 1429 +@{ +*/ +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + +/** @} */ +/** +@name AXI VDMA constants 1430 - 1440 +@{ +*/ +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 +/** @} */ +/** +@name NAND Flash Status Codes 1441 - 1459 +@{ +*/ +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /*!< Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /*!< Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /*!< Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected + */ +/** @} */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_status_codes". +*/ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xtime_l.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xtime_l.h new file mode 100644 index 0000000..9b872b6 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xtime_l.h @@ -0,0 +1,105 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xtime_l.h +* @addtogroup a9_time_apis Cortex A9 Time Functions +* +* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This +* counter increases by one at every two processor cycles. These functions can +* be used to get/set time in the global timer. +* +* @{ +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
+*						implementation
+*
    +* +******************************************************************************/ + +#ifndef XTIME_H /* prevent circular inclusions */ +#define XTIME_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xparameters.h" + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +typedef u64 XTime; + +/************************** Constant Definitions *****************************/ +#define GLOBAL_TMR_BASEADDR XPAR_GLOBAL_TMR_BASEADDR +#define GTIMER_COUNTER_LOWER_OFFSET 0x00U +#define GTIMER_COUNTER_UPPER_OFFSET 0x04U +#define GTIMER_CONTROL_OFFSET 0x08U + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_SECOND (SLEEP_TIMER_FREQUENCY) +#else +/* Global Timer is always clocked at half of the CPU frequency */ +#define COUNTS_PER_SECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2) +#endif + +#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) +#pragma message ("For the sleep routines, Global timer is being used") +#endif +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void XTime_SetTime(XTime Xtime_Global); +void XTime_GetTime(XTime *Xtime_Global); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XTIME_H */ +/** +* @} End of "addtogroup a9_time_apis". +*/ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps.h new file mode 100644 index 0000000..b7b4e19 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps.h @@ -0,0 +1,467 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps.h +* @addtogroup ttcps_v3_5 +* @{ +* @details +* +* This is the driver for one 16-bit timer counter in the Triple Timer Counter +* (TTC) module in the Ps block. +* +* The TTC module provides three independent timer/counter modules that can each +* be clocked using either the system clock (pclk) or an externally driven +* clock (ext_clk). In addition, each counter can independently prescale its +* selected clock input (divided by 2 to 65536). Counters can be set to +* decrement or increment. +* +* Each of the counters can be programmed to generate interrupt pulses: +* . At a regular, predefined period, that is on a timed interval +* . When the counter registers overflow +* . When the count matches any one of the three 'match' registers +* +* Therefore, up to six different events can trigger a timer interrupt: three +* match interrupts, an overflow interrupt, an interval interrupt and an event +* timer interrupt. Note that the overflow interrupt and the interval interrupt +* are mutually exclusive. +* +* Initialization & Configuration +* +* An XTtcPs_Config structure is used to configure a driver instance. +* Information in the XTtcPs_Config structure is the hardware properties +* about the device. +* +* A driver instance is initialized through +* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr +* is a pointer to the XTtcPs_Config structure, it can be looked up statically +* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The +* EffectiveAddr can be the static base address of the device or virtual +* mapped address if address translation is supported. +* +* Interrupts +* +* Interrupt handler is not provided by the driver, as handling of interrupt +* is application specific. +* +* @note +* The default setting for a timer/counter is: +* - Overflow Mode +* - Internal clock (pclk) selected +* - Counter disabled +* - All Interrupts disabled +* - Output waveforms disabled +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.2   mus    10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+*                       macros to return 32 bit values for zynq ultrascale+mpsoc
+*       ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* 3.4   ms   04/18/17 Modified tcl file to add suffix U for all macros
+*                     definitions of ttcps in xparameters.h
+* 3.5   srm  10/06/17 Added new typedef XMatchRegValue for match register width
+*
+*
    +* +******************************************************************************/ + +#ifndef XTTCPS_H /* prevent circular inclusions */ +#define XTTCPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xttcps_hw.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + + +/* + * Maximum Value for interval counter + */ + #if defined(ARMA9) + #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU + #else + #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU + #endif + +/** @name Configuration options + * + * Options for the device. Each of the options is bit field, so more than one + * options can be specified. + * + * @{ + */ +#define XTTCPS_OPTION_EXTERNAL_CLK 0x00000001U /**< External clock source */ +#define XTTCPS_OPTION_CLK_EDGE_NEG 0x00000002U /**< Clock on trailing edge for + external clock*/ +#define XTTCPS_OPTION_INTERVAL_MODE 0x00000004U /**< Interval mode */ +#define XTTCPS_OPTION_DECREMENT 0x00000008U /**< Decrement the counter */ +#define XTTCPS_OPTION_MATCH_MODE 0x00000010U /**< Match mode */ +#define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */ +#define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */ +/*@}*/ +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID for device */ + u32 BaseAddress; /**< Base address for device */ + u32 InputClockHz; /**< Input clock frequency */ +} XTtcPs_Config; + +/** + * The XTtcPs driver instance data. The user is required to allocate a + * variable of this type for each PS timer/counter device in the system. A + * pointer to a variable of this type is then passed to various driver API + * functions. + */ +typedef struct { + XTtcPs_Config Config; /**< Configuration structure */ + u32 IsReady; /**< Device is initialized and ready */ +} XTtcPs; + +/** + * This typedef contains interval count and Match register value + */ +#if defined(ARMA9) +typedef u16 XInterval; +typedef u16 XMatchRegValue; +#else +typedef u32 XInterval; +typedef u32 XMatchRegValue; +#endif +/***************** Macros (Inline Functions) Definitions *********************/ + +/* + * Internal helper macros + */ +#define InstReadReg(InstancePtr, RegOffset) \ + (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset))) + +#define InstWriteReg(InstancePtr, RegOffset, Data) \ + (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data))) + +/*****************************************************************************/ +/** +* +* This function starts the counter/timer without resetting the counter value. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_Start(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_Start(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ + ~XTTCPS_CNT_CNTRL_DIS_MASK)) + +/*****************************************************************************/ +/** +* +* This function stops the counter/timer. This macro may be called at any time +* to stop the counter. The counter holds the last value until it is reset, +* restarted or enabled. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_Stop(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_Stop(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ + XTTCPS_CNT_CNTRL_DIS_MASK)) + +/*****************************************************************************/ +/** +* +* This function checks whether the timer counter has already started. +* +* @param InstancePtr is a pointer to the XTtcPs instance +* +* @return Non-zero if the device has started, '0' otherwise. +* +* @note C-style signature: +* int XTtcPs_IsStarted(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_IsStarted(InstancePtr) \ + ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \ + XTTCPS_CNT_CNTRL_DIS_MASK) == 0U) + +/*****************************************************************************/ +/** +* +* This function returns the current 16-bit counter value. It may be called at +* any time. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return zynq:16 bit counter value. +* zynq ultrascale+mpsoc:32 bit counter value. +* +* @note C-style signature: +* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) +* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) +* +****************************************************************************/ +#if defined(ARMA9) +/* + * ttc supports 16 bit counter for zynq + */ +#define XTtcPs_GetCounterValue(InstancePtr) \ + (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET) +#else +/* + * ttc supports 32 bit counter for zynq ultrascale+mpsoc + */ +#define XTtcPs_GetCounterValue(InstancePtr) \ + InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET) +#endif + +/*****************************************************************************/ +/** +* +* This function sets the interval value to be used in interval mode. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param Value is the 16-bit value to be set in the interval register. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value) +* +****************************************************************************/ +#define XTtcPs_SetInterval(InstancePtr, Value) \ + InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value)) + +/*****************************************************************************/ +/** +* +* This function gets the interval value from the interval register. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return zynq:16 bit interval value. +* zynq ultrascale+mpsoc:32 bit interval value. +* +* @note C-style signature: +* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr) +* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr) +* +****************************************************************************/ +#if defined(ARMA9) +/* + * ttc supports 16 bit interval counter for zynq + */ +#define XTtcPs_GetInterval(InstancePtr) \ + (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET) +#else +/* + * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc + */ +#define XTtcPs_GetInterval(InstancePtr) \ + InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET) +#endif +/*****************************************************************************/ +/** +* +* This macro resets the count register. It may be called at any time. The +* counter is reset to either 0 or 0xFFFF, or the interval value, depending on +* the increment/decrement mode. The state of the counter, as started or +* stopped, is not affected by calling reset. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None +* +* @note C-style signature: +* void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr) +* +****************************************************************************/ +#define XTtcPs_ResetCounterValue(InstancePtr) \ + InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \ + (u32)XTTCPS_CNT_CNTRL_RST_MASK)) + +/*****************************************************************************/ +/** +* +* This function enables the interrupts. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be enabled. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be enabled, cleared bits +* will not be disabled. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) | \ + (InterruptMask))) + +/*****************************************************************************/ +/** +* +* This function disables the interrupts. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be disabled. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be disabled, cleared bits +* will not be disabled. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET, \ + (InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) & \ + ~(InterruptMask))) + +/*****************************************************************************/ +/** +* +* This function reads the interrupt status. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* +* @return None. +* +* @note C-style signature: +* u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr) +* +******************************************************************************/ +#define XTtcPs_GetInterruptStatus(InstancePtr) \ + InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET) + +/*****************************************************************************/ +/** +* +* This function clears the interrupt status. +* +* @param InstancePtr is a pointer to the XTtcPs instance. +* @param InterruptMask defines which interrupt should be cleared. +* Constants are defined in xttcps_hw.h as XTTCPS_IXR_*. +* This is a bit mask, all set bits will be cleared, cleared bits +* will not be cleared. +* +* @return None. +* +* @note +* C-style signature: +* void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask) +* +******************************************************************************/ +#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \ + InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \ + (InterruptMask)) + + +/************************** Function Prototypes ******************************/ + +/* + * Initialization functions in xttcps_sinit.c + */ +XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); + +/* + * Required functions, in xttcps.c + */ +s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, + XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); + +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value); +XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); + +void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue); +u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr); + +void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, + XInterval *Interval, u8 *Prescaler); + +/* + * Functions for options, in file xttcps_options.c + */ +s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options); +u32 XTtcPs_GetOptions(XTtcPs *InstancePtr); + +/* + * Function for self-test, in file xttcps_selftest.c + */ +s32 XTtcPs_SelfTest(XTtcPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps_hw.h new file mode 100644 index 0000000..b1fa545 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xttcps_hw.h @@ -0,0 +1,233 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xttcps_hw.h +* @addtogroup ttcps_v3_5 +* @{ +* +* This file defines the hardware interface to one of the three timer counters +* in the Ps block. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5   srm    10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+*                       XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+*                       mask 16 bit values for zynq and 32 bit values for
+*                       zynq ultrascale+mpsoc "
+*
    +* +******************************************************************************/ + +#ifndef XTTCPS_HW_H /* prevent circular inclusions */ +#define XTTCPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ +/* + * Flag for a9 processor + */ + #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) + #define ARMA9 + #endif + +/** @name Register Map + * + * Register offsets from the base address of the device. + * + * @{ + */ +#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */ +#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/ +#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */ +#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */ +#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */ +#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */ +#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */ +#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */ +#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */ +/* @} */ + +/** @name Clock Control Register + * Clock Control Register definitions + * @{ + */ +#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */ +#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */ +#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */ +#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */ +#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */ +#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */ +/* @} */ + +/** @name Counter Control Register + * Counter Control Register definitions + * @{ + */ +#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */ +#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */ +#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */ +#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */ +#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */ +#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */ +#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */ +#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */ +/* @} */ + +/** @name Current Counter Value Register + * Current Counter Value Register definitions + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */ +#else +#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */ +#endif +/* @} */ + +/** @name Interval Value Register + * Interval Value Register is the maximum value the counter will count up or + * down to. + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/ +#else +#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/ +#endif +/* @} */ + +/** @name Match Registers + * Definitions for Match registers, each timer counter has three match + * registers. + * @{ + */ +#if defined(ARMA9) +#define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */ +#else +#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */ +#endif +#define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */ +/* @} */ + +/** @name Interrupt Registers + * Following register bit mask is for all interrupt registers. + * + * @{ + */ +#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */ +#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */ +#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */ +#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */ +#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */ +#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */ +/* @} */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XTtcPs_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (u32)(RegOffset))) + +/****************************************************************************/ +/** +* +* Write the given Timer Counter register. +* +* @param BaseAddress is the base address of the timer counter device. +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset, +* u32 Data) +* +*****************************************************************************/ +#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))) + +/****************************************************************************/ +/** +* +* Calculate a match register offset using the Match Register index. +* +* @param MatchIndex is the 0-2 value of the match register +* +* @return MATCH_N_OFFSET. +* +* @note C-style signature: +* u32 XTtcPs_Match_N_Offset(u8 MatchIndex) +* +*****************************************************************************/ +#define XTtcPs_Match_N_Offset(MatchIndex) \ + ((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex))) + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps.h new file mode 100644 index 0000000..33758c2 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps.h @@ -0,0 +1,520 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xuartps.h +* @addtogroup uartps_v3_5 +* @{ +* @details +* +* This driver supports the following features: +* +* - Dynamic data format (baud rate, data bits, stop bits, parity) +* - Polled mode +* - Interrupt driven mode +* - Transmit and receive FIFOs (32 byte FIFO depth) +* - Access to the external modem control lines +* +* Initialization & Configuration +* +* The XUartPs_Config structure is used by the driver to configure itself. +* Fields inside this structure are properties of XUartPs based on its hardware +* build. +* +* To support multiple runtime loading and initialization strategies employed +* by various operating systems, the driver instance can be initialized in the +* following way: +* +* - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a +* configuration structure provided by the caller. If running in a system +* with address translation, the parameter EffectiveAddr should be the +* virtual address. +* +* Baud Rate +* +* The UART has an internal baud rate generator, which furnishes the baud rate +* clock for both the receiver and the transmitter. Ther input clock frequency +* can be either the master clock or the master clock divided by 8, configured +* through the mode register. +* +* Accompanied with the baud rate divider register, the baud rate is determined +* by: +* 
    +*	baud_rate = input_clock / (bgen * (bdiv + 1)
+*
    +* where bgen is the value of the baud rate generator, and bdiv is the value of +* baud rate divider. +* +* Interrupts +* +* The FIFOs are not flushed when the driver is initialized, but a function is +* provided to allow the user to reset the FIFOs if desired. +* +* The driver defaults to no interrupts at initialization such that interrupts +* must be enabled if desired. An interrupt is generated for one of the +* following conditions. +* +* - A change in the modem signals +* - Data in the receive FIFO for a configuable time without receiver activity +* - A parity error +* - A framing error +* - An overrun error +* - Transmit FIFO is full +* - Transmit FIFO is empty +* - Receive FIFO is full +* - Receive FIFO is empty +* - Data in the receive FIFO equal to the receive threshold +* +* The application can control which interrupts are enabled using the +* XUartPs_SetInterruptMask() function. +* +* In order to use interrupts, it is necessary for the user to connect the +* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt +* system of the application. A separate handler should be provided by the +* application to communicate with the interrupt system, and conduct +* application specific interrupt handling. An application registers its own +* handler through the XUartPs_SetHandler() function. +* +* Data Transfer +* +* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the +* driver to allow data to be sent and received. They can be used in either +* polled or interrupt mode. +* +* @note +* +* The default configuration for the UART after initialization is: +* +* - 9,600 bps or XPAR_DFT_BAUDRATE if defined +* - 8 data bits +* - 1 stop bit +* - no parity +* - FIFO's are enabled with a receive threshold of 8 bytes +* - The RX timeout is enabled with a timeout of 1 (4 char times) +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
+*						platform variable in driver instance structure.
+* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
+*			uart is connected to a valid interrupt controller CR#946803.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+* 3.4   ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+* 3.6   ms     02/16/18 Updates the flow control mode offset value in modem
+*                       control register.
+*
+*
    +* +*****************************************************************************/ + +#ifndef XUARTPS_H /* prevent circular inclusions */ +#define XUARTPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xuartps_hw.h" +#include "xplatform_info.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constants indicate the max and min baud rates and these + * numbers are based only on the testing that has been done. The hardware + * is capable of other baud rates. + */ +#define XUARTPS_MAX_RATE 921600U +#define XUARTPS_MIN_RATE 110U + +#define XUARTPS_DFT_BAUDRATE 115200U /* Default baud rate */ + +/** @name Configuration options + * @{ + */ +/** + * These constants specify the options that may be set or retrieved + * with the driver, each is a unique bit mask such that multiple options + * may be specified. These constants indicate the available options + * in active state. + * + */ + +#define XUARTPS_OPTION_SET_BREAK 0x0080U /**< Starts break transmission */ +#define XUARTPS_OPTION_STOP_BREAK 0x0040U /**< Stops break transmission */ +#define XUARTPS_OPTION_RESET_TMOUT 0x0020U /**< Reset the receive timeout */ +#define XUARTPS_OPTION_RESET_TX 0x0010U /**< Reset the transmitter */ +#define XUARTPS_OPTION_RESET_RX 0x0008U /**< Reset the receiver */ +#define XUARTPS_OPTION_ASSERT_RTS 0x0004U /**< Assert the RTS bit */ +#define XUARTPS_OPTION_ASSERT_DTR 0x0002U /**< Assert the DTR bit */ +#define XUARTPS_OPTION_SET_FCM 0x0001U /**< Turn on flow control mode */ +/*@}*/ + + +/** @name Channel Operational Mode + * + * The UART can operate in one of four modes: Normal, Local Loopback, Remote + * Loopback, or automatic echo. + * + * @{ + */ + +#define XUARTPS_OPER_MODE_NORMAL (u8)0x00U /**< Normal Mode */ +#define XUARTPS_OPER_MODE_AUTO_ECHO (u8)0x01U /**< Auto Echo Mode */ +#define XUARTPS_OPER_MODE_LOCAL_LOOP (u8)0x02U /**< Local Loopback Mode */ +#define XUARTPS_OPER_MODE_REMOTE_LOOP (u8)0x03U /**< Remote Loopback Mode */ + +/* @} */ + +/** @name Data format values + * + * These constants specify the data format that the driver supports. + * The data format includes the number of data bits, the number of stop + * bits and parity. + * + * @{ + */ +#define XUARTPS_FORMAT_8_BITS 0U /**< 8 data bits */ +#define XUARTPS_FORMAT_7_BITS 2U /**< 7 data bits */ +#define XUARTPS_FORMAT_6_BITS 3U /**< 6 data bits */ + +#define XUARTPS_FORMAT_NO_PARITY 4U /**< No parity */ +#define XUARTPS_FORMAT_MARK_PARITY 3U /**< Mark parity */ +#define XUARTPS_FORMAT_SPACE_PARITY 2U /**< parity */ +#define XUARTPS_FORMAT_ODD_PARITY 1U /**< Odd parity */ +#define XUARTPS_FORMAT_EVEN_PARITY 0U /**< Even parity */ + +#define XUARTPS_FORMAT_2_STOP_BIT 2U /**< 2 stop bits */ +#define XUARTPS_FORMAT_1_5_STOP_BIT 1U /**< 1.5 stop bits */ +#define XUARTPS_FORMAT_1_STOP_BIT 0U /**< 1 stop bit */ +/*@}*/ + +/** @name Callback events + * + * These constants specify the handler events that an application can handle + * using its specific handler function. Note that these constants are not bit + * mask, so only one event can be passed to an application at a time. + * + * @{ + */ +#define XUARTPS_EVENT_RECV_DATA 1U /**< Data receiving done */ +#define XUARTPS_EVENT_RECV_TOUT 2U /**< A receive timeout occurred */ +#define XUARTPS_EVENT_SENT_DATA 3U /**< Data transmission done */ +#define XUARTPS_EVENT_RECV_ERROR 4U /**< A receive error detected */ +#define XUARTPS_EVENT_MODEM 5U /**< Modem status changed */ +#define XUARTPS_EVENT_PARE_FRAME_BRKE 6U /**< A receive parity, frame, break + * error detected */ +#define XUARTPS_EVENT_RECV_ORERR 7U /**< A receive overrun error detected */ +/*@}*/ + + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ + u32 InputClockHz;/**< Input clock frequency */ + s32 ModemPinsConnected; /** Specifies whether modem pins are connected + * to MIO or FMIO */ +} XUartPs_Config; + +/* Keep track of state information about a data buffer in the interrupt mode. */ +typedef struct { + u8 *NextBytePtr; + u32 RequestedBytes; + u32 RemainingBytes; +} XUartPsBuffer; + +/** + * Keep track of data format setting of a device. + */ +typedef struct { + u32 BaudRate; /**< In bps, ie 1200 */ + u32 DataBits; /**< Number of data bits */ + u32 Parity; /**< Parity */ + u8 StopBits; /**< Number of stop bits */ +} XUartPsFormat; + +/******************************************************************************/ +/** + * This data type defines a handler that an application defines to communicate + * with interrupt system to retrieve state information about an application. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the handler, and is passed back to the upper layer + * when the handler is called. It is used to find the device driver + * instance. + * @param Event contains one of the event constants indicating events that + * have occurred. + * @param EventData contains the number of bytes sent or received at the + * time of the call for send and receive events and contains the + * modem status for modem events. + * + ******************************************************************************/ +typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event, + u32 EventData); + +/** + * The XUartPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XUartPs_Config Config; /* Configuration data structure */ + u32 InputClockHz; /* Input clock frequency */ + u32 IsReady; /* Device is initialized and ready */ + u32 BaudRate; /* Current baud rate */ + + XUartPsBuffer SendBuffer; + XUartPsBuffer ReceiveBuffer; + + XUartPs_Handler Handler; + void *CallBackRef; /* Callback reference for event handler */ + u32 Platform; + u8 is_rxbs_error; +} XUartPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Get the UART Channel Status Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetChannelStatus(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) + +/****************************************************************************/ +/** +* Get the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_GetControl(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_GetModeControl(InstancePtr) \ + Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET) + +/****************************************************************************/ +/** +* Set the UART Mode Control Register. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \ + (u32)(RegisterValue)) + +/****************************************************************************/ +/** +* Enable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_EnableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_EnableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \ + ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \ + (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN))) + +/****************************************************************************/ +/** +* Disable the transmitter and receiver of the UART. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_DisableUart(XUartPs *InstancePtr) +* +******************************************************************************/ +#define XUartPs_DisableUart(InstancePtr) \ + Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \ + (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \ + (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS))) + +/****************************************************************************/ +/** +* Determine if the transmitter FIFO is empty. +* +* @param InstancePtr is a pointer to the XUartPs instance. +* +* @return +* - TRUE if a byte can be sent +* - FALSE if the Transmitter Fifo is not empty +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr) +* +******************************************************************************/ +#define XUartPs_IsTransmitEmpty(InstancePtr) \ + ((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY) + + +/************************** Function Prototypes *****************************/ + +/* Static lookup function implemented in xuartps_sinit.c */ +XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId); + +/* Interface functions implemented in xuartps.c */ +s32 XUartPs_CfgInitialize(XUartPs *InstancePtr, + XUartPs_Config * Config, u32 EffectiveAddr); + +u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr, + u32 NumBytes); + +u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr, + u32 NumBytes); + +s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate); + +/* Options functions in xuartps_options.c */ +void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options); + +u16 XUartPs_GetOptions(XUartPs *InstancePtr); + +void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel); + +u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr); + +u16 XUartPs_GetModemStatus(XUartPs *InstancePtr); + +u32 XUartPs_IsSending(XUartPs *InstancePtr); + +u8 XUartPs_GetOperMode(XUartPs *InstancePtr); + +void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode); + +u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr); + +void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue); + +u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr); + +void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout); + +s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr); + +void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr); + +/* interrupt functions in xuartps_intr.c */ +u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr); + +void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask); + +void XUartPs_InterruptHandler(XUartPs *InstancePtr); + +void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr, + void *CallBackRef); + +/* self-test functions in xuartps_selftest.c */ +s32 XUartPs_SelfTest(XUartPs *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps_hw.h new file mode 100644 index 0000000..9a2bc43 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xuartps_hw.h @@ -0,0 +1,451 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xuartps_hw.h +* @addtogroup uartps_v3_5 +* @{ +* +* This header file contains the hardware interface of an XUartPs device. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 3.6   ms     02/16/18 Updates flow control mode offset value in
+*			modem control register.
+*
+*
    +* +******************************************************************************/ +#ifndef XUARTPS_HW_H /* prevent circular inclusions */ +#define XUARTPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the UART. + * @{ + */ +#define XUARTPS_CR_OFFSET 0x0000U /**< Control Register [8:0] */ +#define XUARTPS_MR_OFFSET 0x0004U /**< Mode Register [9:0] */ +#define XUARTPS_IER_OFFSET 0x0008U /**< Interrupt Enable [12:0] */ +#define XUARTPS_IDR_OFFSET 0x000CU /**< Interrupt Disable [12:0] */ +#define XUARTPS_IMR_OFFSET 0x0010U /**< Interrupt Mask [12:0] */ +#define XUARTPS_ISR_OFFSET 0x0014U /**< Interrupt Status [12:0]*/ +#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */ +#define XUARTPS_RXTOUT_OFFSET 0x001CU /**< RX Timeout [7:0] */ +#define XUARTPS_RXWM_OFFSET 0x0020U /**< RX FIFO Trigger Level [5:0] */ +#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */ +#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */ +#define XUARTPS_SR_OFFSET 0x002CU /**< Channel Status [14:0] */ +#define XUARTPS_FIFO_OFFSET 0x0030U /**< FIFO [7:0] */ +#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */ +#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */ +#define XUARTPS_TXWM_OFFSET 0x0044U /**< TX FIFO Trigger Level [5:0] */ +#define XUARTPS_RXBS_OFFSET 0x0048U /**< RX FIFO Byte Status [11:0] */ +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +#define XUARTPS_CR_STOPBRK 0x00000100U /**< Stop transmission of break */ +#define XUARTPS_CR_STARTBRK 0x00000080U /**< Set break */ +#define XUARTPS_CR_TORST 0x00000040U /**< RX timeout counter restart */ +#define XUARTPS_CR_TX_DIS 0x00000020U /**< TX disabled. */ +#define XUARTPS_CR_TX_EN 0x00000010U /**< TX enabled */ +#define XUARTPS_CR_RX_DIS 0x00000008U /**< RX disabled. */ +#define XUARTPS_CR_RX_EN 0x00000004U /**< RX enabled */ +#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */ +#define XUARTPS_CR_TXRST 0x00000002U /**< TX logic reset */ +#define XUARTPS_CR_RXRST 0x00000001U /**< RX logic reset */ +/* @}*/ + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ +#define XUARTPS_MR_CCLK 0x00000400U /**< Input clock selection */ +#define XUARTPS_MR_CHMODE_R_LOOP 0x00000300U /**< Remote loopback mode */ +#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200U /**< Local loopback mode */ +#define XUARTPS_MR_CHMODE_ECHO 0x00000100U /**< Auto echo mode */ +#define XUARTPS_MR_CHMODE_NORM 0x00000000U /**< Normal mode */ +#define XUARTPS_MR_CHMODE_SHIFT 8U /**< Mode shift */ +#define XUARTPS_MR_CHMODE_MASK 0x00000300U /**< Mode mask */ +#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080U /**< 2 stop bits */ +#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */ +#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000U /**< 1 stop bit */ +#define XUARTPS_MR_STOPMODE_SHIFT 6U /**< Stop bits shift */ +#define XUARTPS_MR_STOPMODE_MASK 0x000000A0U /**< Stop bits mask */ +#define XUARTPS_MR_PARITY_NONE 0x00000020U /**< No parity mode */ +#define XUARTPS_MR_PARITY_MARK 0x00000018U /**< Mark parity mode */ +#define XUARTPS_MR_PARITY_SPACE 0x00000010U /**< Space parity mode */ +#define XUARTPS_MR_PARITY_ODD 0x00000008U /**< Odd parity mode */ +#define XUARTPS_MR_PARITY_EVEN 0x00000000U /**< Even parity mode */ +#define XUARTPS_MR_PARITY_SHIFT 3U /**< Parity setting shift */ +#define XUARTPS_MR_PARITY_MASK 0x00000038U /**< Parity mask */ +#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006U /**< 6 bits data */ +#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004U /**< 7 bits data */ +#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000U /**< 8 bits data */ +#define XUARTPS_MR_CHARLEN_SHIFT 1U /**< Data Length shift */ +#define XUARTPS_MR_CHARLEN_MASK 0x00000006U /**< Data length mask */ +#define XUARTPS_MR_CLKSEL 0x00000001U /**< Input clock selection */ +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ +#define XUARTPS_IXR_RBRK 0x00002000U /**< Rx FIFO break detect interrupt */ +#define XUARTPS_IXR_TOVR 0x00001000U /**< Tx FIFO Overflow interrupt */ +#define XUARTPS_IXR_TNFUL 0x00000800U /**< Tx FIFO Nearly Full interrupt */ +#define XUARTPS_IXR_TTRIG 0x00000400U /**< Tx Trig interrupt */ +#define XUARTPS_IXR_DMS 0x00000200U /**< Modem status change interrupt */ +#define XUARTPS_IXR_TOUT 0x00000100U /**< Timeout error interrupt */ +#define XUARTPS_IXR_PARITY 0x00000080U /**< Parity error interrupt */ +#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */ +#define XUARTPS_IXR_OVER 0x00000020U /**< Overrun error interrupt */ +#define XUARTPS_IXR_TXFULL 0x00000010U /**< TX FIFO full interrupt. */ +#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXFULL 0x00000004U /**< RX FIFO full interrupt. */ +#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */ +#define XUARTPS_IXR_RXOVR 0x00000001U /**< RX FIFO trigger interrupt. */ +#define XUARTPS_IXR_MASK 0x00003FFFU /**< Valid bit mask */ +/* @} */ + + +/** @name Baud Rate Generator Register + * + * The baud rate generator control register (BRGR) is a 16 bit register that + * controls the receiver bit sample clock and baud rate. + * Valid values are 1 - 65535. + * + * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit + * in the MR register. + * @{ + */ +#define XUARTPS_BAUDGEN_DISABLE 0x00000000U /**< Disable clock */ +#define XUARTPS_BAUDGEN_MASK 0x0000FFFFU /**< Valid bits mask */ +#define XUARTPS_BAUDGEN_RESET_VAL 0x0000028BU /**< Reset value */ + +/** @name Baud Divisor Rate register + * + * The baud rate divider register (BDIV) controls how much the bit sample + * rate is divided by. It sets the baud rate. + * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored. + * + * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by + * the MR_CCLK bit in the MR register. + * @{ + */ +#define XUARTPS_BAUDDIV_MASK 0x000000FFU /**< 8 bit baud divider mask */ +#define XUARTPS_BAUDDIV_RESET_VAL 0x0000000FU /**< Reset value */ +/* @} */ + + +/** @name Receiver Timeout Register + * + * Use the receiver timeout register (RTR) to detect an idle condition on + * the receiver data line. + * + * @{ + */ +#define XUARTPS_RXTOUT_DISABLE 0x00000000U /**< Disable time out */ +#define XUARTPS_RXTOUT_MASK 0x000000FFU /**< Valid bits mask */ + +/** @name Receiver FIFO Trigger Level Register + * + * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at + * which the RX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_RXWM_DISABLE 0x00000000U /**< Disable RX trigger interrupt */ +#define XUARTPS_RXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_RXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Transmit FIFO Trigger Level Register + * + * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at + * which the TX FIFO triggers an interrupt event. + * @{ + */ + +#define XUARTPS_TXWM_MASK 0x0000003FU /**< Valid bits mask */ +#define XUARTPS_TXWM_RESET_VAL 0x00000020U /**< Reset value */ +/* @} */ + +/** @name Modem Control Register + * + * This register (MODEMCR) controls the interface with the modem or data set, + * or a peripheral device emulating a modem. + * + * @{ + */ +#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */ +#define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ +#define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ +/* @} */ + +/** @name Modem Status Register + * + * This register (MODEMSR) indicates the current state of the control lines + * from a modem, or another peripheral device, to the CPU. In addition, four + * bits of the modem status register provide change information. These bits + * are set to a logic 1 whenever a control input from the modem changes state. + * + * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem + * status interrupt is generated and this is reflected in the modem status + * register. + * + * @{ + */ +#define XUARTPS_MODEMSR_FCMS 0x00000100U /**< Flow control mode (FCMS) */ +#define XUARTPS_MODEMSR_DCD 0x00000080U /**< Complement of DCD input */ +#define XUARTPS_MODEMSR_RI 0x00000040U /**< Complement of RI input */ +#define XUARTPS_MODEMSR_DSR 0x00000020U /**< Complement of DSR input */ +#define XUARTPS_MODEMSR_CTS 0x00000010U /**< Complement of CTS input */ +#define XUARTPS_MODEMSR_DDCD 0x00000008U /**< Delta DCD indicator */ +#define XUARTPS_MODEMSR_TERI 0x00000004U /**< Trailing Edge Ring Indicator */ +#define XUARTPS_MODEMSR_DDSR 0x00000002U /**< Change of DSR */ +#define XUARTPS_MODEMSR_DCTS 0x00000001U /**< Change of CTS */ +/* @} */ + +/** @name Channel Status Register + * + * The channel status register (CSR) is provided to enable the control logic + * to monitor the status of bits in the channel interrupt status register, + * even if these are masked out by the interrupt mask register. + * + * @{ + */ +#define XUARTPS_SR_TNFUL 0x00004000U /**< TX FIFO Nearly Full Status */ +#define XUARTPS_SR_TTRIG 0x00002000U /**< TX FIFO Trigger Status */ +#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */ +#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */ +#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */ +#define XUARTPS_SR_TXFULL 0x00000010U /**< TX FIFO full */ +#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */ +#define XUARTPS_SR_RXFULL 0x00000004U /**< RX FIFO full */ +#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */ +#define XUARTPS_SR_RXOVR 0x00000001U /**< RX FIFO fill over trigger */ +/* @} */ + +/** @name Flow Delay Register + * + * Operation of the flow delay register (FLOWDEL) is very similar to the + * receive FIFO trigger register. An internal trigger signal activates when the + * FIFO is filled to the level set by this register. This trigger will not + * cause an interrupt, although it can be read through the channel status + * register. In hardware flow control mode, RTS is deactivated when the trigger + * becomes active. RTS only resets when the FIFO level is four less than the + * level of the flow delay trigger and the flow delay trigger is not activated. + * A value less than 4 disables the flow delay. + * @{ + */ +#define XUARTPS_FLOWDEL_MASK XUARTPS_RXWM_MASK /**< Valid bit mask */ +/* @} */ + +/** @name Receiver FIFO Byte Status Register + * + * The Receiver FIFO Status register is used to have a continuous + * monitoring of the raw unmasked byte status information. The register + * contains frame, parity and break status information for the top + * four bytes in the RX FIFO. + * + * Receiver FIFO Byte Status Register Bit Definition + * @{ + */ +#define XUARTPS_RXBS_BYTE3_BRKE 0x00000800U /**< Byte3 Break Error */ +#define XUARTPS_RXBS_BYTE3_FRME 0x00000400U /**< Byte3 Frame Error */ +#define XUARTPS_RXBS_BYTE3_PARE 0x00000200U /**< Byte3 Parity Error */ +#define XUARTPS_RXBS_BYTE2_BRKE 0x00000100U /**< Byte2 Break Error */ +#define XUARTPS_RXBS_BYTE2_FRME 0x00000080U /**< Byte2 Frame Error */ +#define XUARTPS_RXBS_BYTE2_PARE 0x00000040U /**< Byte2 Parity Error */ +#define XUARTPS_RXBS_BYTE1_BRKE 0x00000020U /**< Byte1 Break Error */ +#define XUARTPS_RXBS_BYTE1_FRME 0x00000010U /**< Byte1 Frame Error */ +#define XUARTPS_RXBS_BYTE1_PARE 0x00000008U /**< Byte1 Parity Error */ +#define XUARTPS_RXBS_BYTE0_BRKE 0x00000004U /**< Byte0 Break Error */ +#define XUARTPS_RXBS_BYTE0_FRME 0x00000002U /**< Byte0 Frame Error */ +#define XUARTPS_RXBS_BYTE0_PARE 0x00000001U /**< Byte0 Parity Error */ +#define XUARTPS_RXBS_MASK 0x00000007U /**< 3 bit RX byte status mask */ +/* @} */ + + +/* + * Defines for backwards compatabilty, will be removed + * in the next version of the driver + */ +#define XUARTPS_MEDEMSR_DCDX XUARTPS_MODEMSR_DDCD +#define XUARTPS_MEDEMSR_RIX XUARTPS_MODEMSR_TERI +#define XUARTPS_MEDEMSR_DSRX XUARTPS_MODEMSR_DDSR +#define XUARTPS_MEDEMSR_CTSX XUARTPS_MODEMSR_DCTS + + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* Read a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* +* @return The value read from the register. +* +* @note C-Style signature: +* u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset) +* +******************************************************************************/ +#define XUartPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (u32)(RegOffset)) + +/***************************************************************************/ +/** +* Write a UART register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the +* device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note C-Style signature: +* void XUartPs_WriteReg(u32 BaseAddress, int RegOffset, +* u16 RegisterValue) +* +******************************************************************************/ +#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue)) + +/****************************************************************************/ +/** +* Determine if there is receive data in the receiver and/or FIFO. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if there is receive data, FALSE otherwise. +* +* @note C-Style signature: +* u32 XUartPs_IsReceiveData(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsReceiveData(BaseAddress) \ + !((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY) + +/****************************************************************************/ +/** +* Determine if a byte of data can be sent with the transmitter. +* +* @param BaseAddress contains the base address of the device. +* +* @return TRUE if the TX FIFO is full, FALSE if a byte can be put in the +* FIFO. +* +* @note C-Style signature: +* u32 XUartPs_IsTransmitFull(u32 BaseAddress) +* +******************************************************************************/ +#define XUartPs_IsTransmitFull(BaseAddress) \ + ((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & \ + (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL) + +/************************** Function Prototypes ******************************/ + +void XUartPs_SendByte(u32 BaseAddress, u8 Data); + +u8 XUartPs_RecvByte(u32 BaseAddress); + +void XUartPs_ResetHw(u32 BaseAddress); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps.h new file mode 100644 index 0000000..b5c472e --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps.h @@ -0,0 +1,1098 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusbps.h +* @addtogroup usbps_v2_4 +* @{ +* @details + * + * This file contains the implementation of the XUsbPs driver. It is the + * driver for an USB controller in DEVICE or HOST mode. + * + *

    Introduction

    + * + * The Spartan-3AF Embedded Peripheral Block contains a USB controller for + * communication with serial peripherals or hosts. The USB controller supports + * Host, Device and On the Go (OTG) applications. + * + *

    USB Controller Features

    + * + * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and + * High Speed USB 2.0 (480Mbps) data speeds + * - Supports Device, Host and OTG operational modes + * - ULPI transceiver interface for USB 2.0 operation + * - Integrated USB Full and Low speed serial transceiver interfaces for lowest + * cost connections + * + *

    Initialization & Configuration

    + * + * The configuration of the USB driver happens in multiple stages: + * + * - (a) Configuration of the basic parameters: + * In this stage the basic parameters for the driver are configured, + * including the base address and the controller ID. + * + * - (b) Configuration of the DEVICE endpoints (if applicable): + * If DEVICE mode is desired, the endpoints of the controller need to be + * configured using the XUsbPs_DeviceConfig data structure. Once the + * endpoint configuration is set up in the data structure, The user then + * needs to allocate the required amount of DMAable memory and + * finalize the configuration of the XUsbPs_DeviceConfig data structure, + * e.g. setting the DMAMemVirt and DMAMemPhys members. + * + * - (c) Configuration of the DEVICE modes: + * In the second stage the parameters for DEVICE are configured. + * The caller only needs to configure the modes that are + * actually used. Configuration is done with the: + * XUsbPs_ConfigureDevice() + * Configuration parameters are defined and passed + * into these functions using the: + * XUsbPs_DeviceConfig data structures. + * + * + *

    USB Device Endpoints

    + * + * The USB core supports up to 4 endpoints. Each endpoint has two directions, + * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from + * the host's perspective. Endpoint 0 defaults to be the control endpoint and + * does not need to be set up. Other endpoints need to be configured and set up + * depending on the application. Only endpoints that are actuelly used by the + * application need to be initialized. + * See the example code (xusbps_intr_example.c) for more information. + * + * + *

    Interrupt Handling

    + * + * The USB core uses one interrupt line to report interrupts to the CPU. + * Interrupts are handled by the driver's interrupt handler function + * XUsbPs_IntrHandler(). + * It has to be registered with the OS's interrupt subsystem. The driver's + * interrupt handler divides incoming interrupts into two categories: + * + * - General device interrupts + * - Endopint related interrupts + * + * The user (typically the adapter layer) can register general interrupt + * handler fucntions and endpoint specific interrupt handler functions with the + * driver to receive those interrupts by calling the + * XUsbPs_IntrSetHandler() + * and + * XUsbPs_EpSetHandler() + * functions respectively. Calling these functions with a NULL pointer as the + * argument for the function pointer will "clear" the handler function. + * + * The user can register one handler function for the generic interrupts and + * two handler functions for each endpoint, one for the RX (OUT) and one for + * the TX (IN) direction. For some applications it may be useful to register a + * single endpoint handler function for muliple endpoints/directions. + * + * When a callback function is called by the driver, parameters identifying the + * type of the interrupt will be passed into the handler functions. For general + * interrupts the interrupt mask will be passed into the handler function. For + * endpoint interrupts the parameters include the number of the endpoint, the + * direction (OUT/IN) and the type of the interrupt. + * + * + *

    Data buffer handling

    + * + * Data buffers are sent to and received from endpoint using the + * XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT() + * and + * XUsbPs_EpBufferReceive() + * functions. + * + * User data buffer size is limited to 16 Kbytes. If the user wants to send a + * data buffer that is bigger than this limit it needs to break down the data + * buffer into multiple fragments and send the fragments individually. + * + * From the controller perspective Data buffers can be aligned at any boundary. + * if the buffers are from cache region then the buffer and buffer size should + * be aligned to cache line aligned + * + * + *

    Zero copy

    + * + * The driver uses a zero copy mechanism which imposes certain restrictions to + * the way the user can handle the data buffers. + * + * One restriction is that the user needs to release a buffer after it is done + * processing the data in the buffer. + * + * Similarly, when the user sends a data buffer it MUST not re-use the buffer + * until it is notified by the driver that the buffer has been transmitted. The + * driver will notify the user via the registered endpoint interrupt handling + * function by sending a XUSBPS_EP_EVENT_DATA_TX event. + * + * + *

    DMA

    + * + * The driver uses DMA internally to move data from/to memory. This behaviour + * is transparent to the user. Keeping the DMA handling hidden from the user + * has the advantage that the same API can be used with USB cores that do not + * support DMA. + * + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.02a wgr  05/16/12 Removed comments as they are showing up in SDK
+ *		       Tabs for CR 657898
+ * 1.03a nm   09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ *	      11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1   kpc 04/28/14 Removed unused function prototypes
+ * 2.2   kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
+ *                    code coverage tests.
+ * 2.3   kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
+ *                    moving of dTD Head/Tail Pointers. Invalidate the cache
+ *                    after buffer receive in Endpoint Buffer Handler.
+ * 2.4   sg  04/26/16 Fixed CR#949693, Corrected the logic for EP flush
+ *       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+ *                    generation.
+ *       ms  04/10/17 Modified filename tag to include the file in doxygen
+ *                    examples.
+ *
    + * + ******************************************************************************/ + +#ifndef XUSBPS_H +#define XUSBPS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xusbps_hw.h" +#include "xil_types.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/** + * @name System hang prevention Timeout counter value. + * + * This value is used throughout the code to initialize a Timeout counter that + * is used when hard polling a register. The ides is to initialize the Timeout + * counter to a value that is longer than any expected Timeout but short enough + * so the system will continue to work and report an error while the user is + * still paying attention. A reasonable Timeout time would be about 10 seconds. + * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would + * run about 10 seconds before a Timeout is detected. For example: + * + * int Timeout = XUSBPS_TIMEOUT_COUNTER; + * while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, + * XUSBPS_CMD_OFFSET) & + * XUSBPS_CMD_RST_MASK) && --Timeout) { + * ; + * } + * if (0 == Timeout) { + * return XST_FAILURE; + * } + * + */ +#define XUSBPS_TIMEOUT_COUNTER 1000000 + + +/** + * @name Endpoint Direction (bitmask) + * Definitions to be used with Endpoint related function that require a + * 'Direction' parameter. + * + * NOTE: + * The direction is always defined from the perspective of the HOST! This + * means that an IN endpoint on the controller is used for sending data while + * the OUT endpoint on the controller is used for receiving data. + * @{ + */ +#define XUSBPS_EP_DIRECTION_IN 0x01 /**< Endpoint direction IN. */ +#define XUSBPS_EP_DIRECTION_OUT 0x02 /**< Endpoint direction OUT. */ +/* @} */ + + +/** + * @name Endpoint Type + * Definitions to be used with Endpoint related functions that require a 'Type' + * parameter. + * @{ + */ +#define XUSBPS_EP_TYPE_NONE 0 /**< Endpoint is not used. */ +#define XUSBPS_EP_TYPE_CONTROL 1 /**< Endpoint for Control Transfers */ +#define XUSBPS_EP_TYPE_ISOCHRONOUS 2 /**< Endpoint for isochronous data */ +#define XUSBPS_EP_TYPE_BULK 3 /**< Endpoint for BULK Transfers. */ +#define XUSBPS_EP_TYPE_INTERRUPT 4 /**< Endpoint for interrupt Transfers */ +/* @} */ + +/** + * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6. + * + * @{ + */ +#define ENDPOINT_MAXP_LENGTH 0x400 +#define ENDPOINT_MAXP_MULT_MASK 0xC00 +#define ENDPOINT_MAXP_MULT_SHIFT 10 +/* @} */ + +/** + * @name Field names for status retrieval + * Definitions for the XUsbPs_GetStatus() function call 'StatusType' + * parameter. + * @{ + */ +#define XUSBPS_EP_STS_ADDRESS 1 /**< Address of controller. */ +#define XUSBPS_EP_STS_CONTROLLER_STATE 2 /**< Current controller state. */ +/* @} */ + + + +/** + * @name USB Default alternate setting + * + * @{ + */ +#define XUSBPS_DEFAULT_ALT_SETTING 0 /**< The default alternate setting is 0 */ +/* @} */ + +/** + * @name Endpoint event types + * Definitions that are used to identify events that occur on endpoints. Passed + * to the endpoint event handler functions registered with + * XUsbPs_EpSetHandler(). + * @{ + */ +#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED 0x01 + /**< Setup data has been received on the enpoint. */ +#define XUSBPS_EP_EVENT_DATA_RX 0x02 + /**< Data frame has been received on the endpoint. */ +#define XUSBPS_EP_EVENT_DATA_TX 0x03 + /**< Data frame has been sent on the endpoint. */ +/* @} */ + + +/* + * Maximum packet size for endpoint, 1024 + * @{ + */ +#define XUSBPS_MAX_PACKET_SIZE 1024 + /**< Maximum value can be put into the queue head */ +/* @} */ +/**************************** Type Definitions *******************************/ + +/****************************************************************************** + * This data type defines the callback function to be used for Endpoint + * handlers. + * + * @param CallBackRef is the Callback reference passed in by the upper + * layer when setting the handler, and is passed back to the upper + * layer when the handler is called. + * @param EpNum is the Number of the endpoint that caused the event. + * @param EventType is the type of the event that occured on the endpoint. + * @param Data is a pointer to user data pointer specified when callback + * was registered. + */ +typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef, + u8 EpNum, u8 EventType, void *Data); + + +/****************************************************************************** + * This data type defines the callback function to be used for the general + * interrupt handler. + * + * @param CallBackRef is the Callback reference passed in by the upper + * layer when setting the handler, and is passed back to the upper + * layer when the handler is called. + * @param IrqMask is the Content of the interrupt status register. This + * value can be used by the callback function to distinguish the + * individual interrupt types. + */ +typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask); + + +/******************************************************************************/ + +/* The following type definitions are used for referencing Queue Heads and + * Transfer Descriptors. The structures themselves are not used, however, the + * types are used in the API to avoid using (void *) pointers. + */ +typedef u8 XUsbPs_dQH[XUSBPS_dQH_ALIGN]; +typedef u8 XUsbPs_dTD[XUSBPS_dTD_ALIGN]; + + +/** + * The following data structures are used internally by the L0/L1 driver. + * Their contents MUST NOT be changed by the upper layers. + */ + +/** + * The following data structure represents OUT endpoint. + */ +typedef struct { + XUsbPs_dQH *dQH; + /**< Pointer to the Queue Head structure of the endpoint. */ + + XUsbPs_dTD *dTDs; + /**< Pointer to the first dTD of the dTD list for this + * endpoint. */ + + XUsbPs_dTD *dTDCurr; + /**< Buffer to the currently processed descriptor. */ + + u8 *dTDBufs; + /**< Pointer to the first buffer of the buffer list for this + * endpoint. */ + + XUsbPs_EpHandlerFunc HandlerFunc; + /**< Handler function for this endpoint. */ + void *HandlerRef; + /**< User data reference for the handler. */ +} XUsbPs_EpOut; + + +/** + * The following data structure represents IN endpoint. + */ +typedef struct { + XUsbPs_dQH *dQH; + /**< Pointer to the Queue Head structure of the endpoint. */ + + XUsbPs_dTD *dTDs; + /**< List of pointers to the Transfer Descriptors of the + * endpoint. */ + + XUsbPs_dTD *dTDHead; + /**< Buffer to the next available descriptor in the list. */ + + XUsbPs_dTD *dTDTail; + /**< Buffer to the last unsent descriptor in the list*/ + + XUsbPs_EpHandlerFunc HandlerFunc; + /**< Handler function for this endpoint. */ + void *HandlerRef; + /**< User data reference for the handler. */ +} XUsbPs_EpIn; + + +/** + * The following data structure represents an endpoint used internally + * by the L0/L1 driver. + */ +typedef struct { + /* Each endpoint has an OUT and an IN component. + */ + XUsbPs_EpOut Out; /**< OUT endpoint structure */ + XUsbPs_EpIn In; /**< IN endpoint structure */ +} XUsbPs_Endpoint; + + + +/** + * The following structure is used by the user to receive Setup Data from an + * endpoint. Using this structure simplifies the process of interpreting the + * setup data in the core's data fields. + * + * The naming scheme for the members of this structure is different from the + * naming scheme found elsewhere in the code. The members of this structure are + * defined in the Chapter 9 USB reference guide. Using this naming scheme makes + * it easier for people familiar with the standard to read the code. + */ +typedef struct { + u8 bmRequestType; /**< bmRequestType in setup data */ + u8 bRequest; /**< bRequest in setup data */ + u16 wValue; /**< wValue in setup data */ + u16 wIndex; /**< wIndex in setup data */ + u16 wLength; /**< wLength in setup data */ +} +XUsbPs_SetupData; + + +/** + * Data structures used to configure endpoints. + */ +typedef struct { + u32 Type; + /**< Endpoint type: + - XUSBPS_EP_TYPE_CONTROL + - XUSBPS_EP_TYPE_ISOCHRONOUS + - XUSBPS_EP_TYPE_BULK + - XUSBPS_EP_TYPE_INTERRUPT */ + + u32 NumBufs; + /**< Number of buffers to be handled by this endpoint. */ + u32 BufSize; + /**< Buffer size. Only relevant for OUT (receive) Endpoints. */ + + u16 MaxPacketSize; + /**< Maximum packet size for this endpoint. This number will + * define the maximum number of bytes sent on the wire per + * transaction. Range: 0..1024 */ +} XUsbPs_EpSetup; + + +/** + * Endpoint configuration structure. + */ +typedef struct { + XUsbPs_EpSetup Out; /**< OUT component of endpoint. */ + XUsbPs_EpSetup In; /**< IN component of endpoint. */ +} XUsbPs_EpConfig; + + +/** + * The XUsbPs_DeviceConfig structure contains the configuration information to + * configure the USB controller for DEVICE mode. This data structure is used + * with the XUsbPs_ConfigureDevice() function call. + */ +typedef struct { + u8 NumEndpoints; /**< Number of Endpoints for the controller. + This number depends on the runtime + configuration of driver. The driver may + configure fewer endpoints than are available + in the core. */ + + XUsbPs_EpConfig EpCfg[XUSBPS_MAX_ENDPOINTS]; + /**< List of endpoint configurations. */ + + + u32 DMAMemPhys; /**< Physical base address of DMAable memory + allocated for the driver. */ + + /* The following members are used internally by the L0/L1 driver. They + * MUST NOT be accesses and/or modified in any way by the upper layers. + * + * The reason for having these members is that we generally try to + * avoid allocating memory in the L0/L1 driver as we want to be OS + * independent. In order to avoid allocating memory for this data + * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig + * structure which is allocated by the caller. + */ + XUsbPs_Endpoint Ep[XUSBPS_MAX_ENDPOINTS]; + /**< List of endpoint metadata structures. */ + + u32 PhysAligned; /**< 64 byte aligned base address of the DMA + memory block. Will be computed and set by + the L0/L1 driver. */ +} XUsbPs_DeviceConfig; + + +/** + * The XUsbPs_Config structure contains configuration information for the USB + * controller. + * + * This structure only contains the basic configuration for the controller. The + * caller also needs to initialize the controller for the DEVICE mode + * using the XUsbPs_DeviceConfig data structures with the + * XUsbPs_ConfigureDevice() function call + */ +typedef struct { + u16 DeviceID; /**< Unique ID of controller. */ + u32 BaseAddress; /**< Core register base address. */ +} XUsbPs_Config; + + +/** + * The XUsbPs driver instance data. The user is required to allocate a + * variable of this type for every USB controller in the system. A pointer to a + * variable of this type is then passed to the driver API functions. + */ +typedef struct { + XUsbPs_Config Config; /**< Configuration structure */ + + int CurrentAltSetting; /**< Current alternative setting of interface */ + + void *UserDataPtr; /**< Data pointer to be used by upper layers to + store application dependent data structures. + The upper layers are responsible to allocated + and free the memory. The driver will not + mofidy this data pointer. */ + + /** + * The following structures hold the configuration for DEVICE mode + * of the controller. They are initialized using the + * XUsbPs_ConfigureDevice() function call. + */ + XUsbPs_DeviceConfig DeviceConfig; + /**< Configuration for the DEVICE mode. */ + + XUsbPs_IntrHandlerFunc HandlerFunc; + /**< Handler function for the controller. */ + void *HandlerRef; + /**< User data reference for the handler. */ + u32 HandlerMask; + /**< User interrupt mask. Defines which interrupts will cause + * the callback to be called. */ +} XUsbPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************** + * + * USB CONTROLLER RELATED MACROS + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * This macro returns the current frame number. + * + * @param InstancePtr is a pointer to the XUsbPs instance of the + * controller. + * + * @return The current frame number. + * + * @note C-style signature: + * u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr) + * + ******************************************************************************/ +#define XUsbPs_GetFrameNum(InstancePtr) \ + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET) + + +/*****************************************************************************/ +/** + * This macro starts the USB engine. + * + * @param InstancePtr is a pointer to the XUsbPs instance of the + * controller. + * + * @note C-style signature: + * void XUsbPs_Start(XUsbPs *InstancePtr) + * + ******************************************************************************/ +#define XUsbPs_Start(InstancePtr) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK) + + +/*****************************************************************************/ +/** + * This macro stops the USB engine. + * + * @param InstancePtr is a pointer to the XUsbPs instance of the + * controller. + * + * @note C-style signature: + * void XUsbPs_Stop(XUsbPs *InstancePtr) + * + ******************************************************************************/ +#define XUsbPs_Stop(InstancePtr) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK) + + +/*****************************************************************************/ +/** + * This macro forces the USB engine to be in Full Speed (FS) mode. + * + * @param InstancePtr is a pointer to the XUsbPs instance of the + * controller. + * + * @note C-style signature: + * void XUsbPs_ForceFS(XUsbPs *InstancePtr) + * + ******************************************************************************/ +#define XUsbPs_ForceFS(InstancePtr) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ + XUSBPS_PORTSCR_PFSC_MASK) + + +/*****************************************************************************/ +/** + * This macro starts the USB Timer 0, with repeat option for period of + * one second. + * + * @param InstancePtr is a pointer to XUsbPs instance of the controller. + * @param Interval is the interval for Timer0 to generate an interrupt + * + * @note C-style signature: + * void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval) + * + ******************************************************************************/ +#define XUsbPs_StartTimer0(InstancePtr, Interval) \ +{ \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_TIMER0_LD_OFFSET, (Interval)); \ + XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ + XUSBPS_TIMER_RUN_MASK | \ + XUSBPS_TIMER_RESET_MASK | \ + XUSBPS_TIMER_REPEAT_MASK); \ +} \ + + +/*****************************************************************************/ +/** +* This macro stops Timer 0. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_StopTimer0(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_StopTimer0(InstancePtr) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET, \ + XUSBPS_TIMER_RUN_MASK) + + +/*****************************************************************************/ +/** +* This macro reads Timer 0. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_ReadTimer0(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_ReadTimer0(InstancePtr) \ + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_TIMER0_CTL_OFFSET) & \ + XUSBPS_TIMER_COUNTER_MASK + + +/*****************************************************************************/ +/** +* This macro force remote wakeup on host +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_RemoteWakeup(InstancePtr) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET, \ + XUSBPS_PORTSCR_FPR_MASK) + + +/****************************************************************************** + * + * ENDPOINT RELATED MACROS + * + ******************************************************************************/ +/*****************************************************************************/ +/** +* This macro enables the given endpoint for the given direction. +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is number of the endpoint to enable. +* @param Dir is direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) + + +/*****************************************************************************/ +/** +* This macro disables the given endpoint for the given direction. +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is the number of the endpoint to disable. +* @param Dir is the direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXE_MASK : 0)) + + +/*****************************************************************************/ +/** +* This macro stalls the given endpoint for the given direction, and flush +* the buffers. +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is number of the endpoint to stall. +* @param Dir is the direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) + + +/*****************************************************************************/ +/** +* This macro unstalls the given endpoint for the given direction. +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is the Number of the endpoint to unstall. +* @param Dir is the Direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum), \ + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \ + ((Dir) & XUSBPS_EP_DIRECTION_IN ? XUSBPS_EPCR_TXS_MASK : 0)) + + +/*****************************************************************************/ +/** +* This macro flush an endpoint upon interface disable +* +* @param InstancePtr is a pointer to the XUsbPs instance of the +* controller. +* @param EpNum is the number of the endpoint to flush. +* @param Dir is the direction of the endpoint (bitfield): +* - XUSBPS_EP_DIRECTION_OUT +* - XUSBPS_EP_DIRECTION_IN +* +* @note C-style signature: +* void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir) +* +******************************************************************************/ +#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \ + 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ + XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \ + +/*****************************************************************************/ +/** +* This macro enables the interrupts defined by the bit mask. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param IntrMask is the Bit mask of interrupts to be enabled. +* +* @note C-style signature: +* void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask) +* +******************************************************************************/ +#define XUsbPs_IntrEnable(InstancePtr, IntrMask) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) + + +/*****************************************************************************/ +/** +* This function disables the interrupts defined by the bit mask. +* +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param IntrMask is a Bit mask of interrupts to be disabled. +* +* @note C-style signature: +* void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask) +* +******************************************************************************/ +#define XUsbPs_IntrDisable(InstancePtr, IntrMask) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask) + + +/*****************************************************************************/ +/** +* This macro enables the endpoint NAK interrupts defined by the bit mask. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be +* enabled. +* @note C-style signature: +* void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask) +* +******************************************************************************/ +#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask) + + +/*****************************************************************************/ +/** +* This macro disables the endpoint NAK interrupts defined by the bit mask. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param NakIntrMask is a Bit mask of endpoint NAK interrupts to be +* disabled. +* +* @note +* C-style signature: +* void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask) +* +******************************************************************************/ +#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask) + + +/*****************************************************************************/ +/** +* This function clears the endpoint NAK interrupts status defined by the +* bit mask. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared. +* +* @note C-style signature: +* void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask) +* +******************************************************************************/ +#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask) \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_EPNAKISR_OFFSET, NakIntrMask) + + + +/*****************************************************************************/ +/** +* This macro sets the Interrupt Threshold value in the control register +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param Threshold is the Interrupt threshold to be set. +* Allowed values: +* - XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt +* - XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame +* - XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames +* - XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames +* - XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames +* - XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames +* - XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames +* - XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames +* +* @note +* C-style signature: +* void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold) +* +******************************************************************************/ +#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold) \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_CMD_OFFSET, (Threshold))\ + + +/*****************************************************************************/ +/** +* This macro sets the Tripwire bit in the USB command register. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_SetTripwire(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_SetSetupTripwire(InstancePtr) \ + XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, \ + XUSBPS_CMD_SUTW_MASK) + + +/*****************************************************************************/ +/** +* This macro clears the Tripwire bit in the USB command register. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @note C-style signature: +* void XUsbPs_ClrTripwire(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_ClrSetupTripwire(InstancePtr) \ + XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, \ + XUSBPS_CMD_SUTW_MASK) + + +/*****************************************************************************/ +/** +* This macro checks if the Tripwire bit in the USB command register is set. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* +* @return +* - TRUE: The tripwire bit is still set. +* - FALSE: The tripwire bit has been cleared. +* +* @note C-style signature: +* int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr) +* +******************************************************************************/ +#define XUsbPs_SetupTripwireIsSet(InstancePtr) \ + (XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XUSBPS_CMD_OFFSET) & \ + XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE) + + +/****************************************************************************** +* +* GENERAL REGISTER / BIT MANIPULATION MACROS +* +******************************************************************************/ +/****************************************************************************/ +/** +* This macro sets the given bit mask in the register. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param RegOffset is the register offset to be written. +* @param Bits is the Bits to be set in the register +* +* @return None. +* +* @note C-style signature: +* void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits) +* +*****************************************************************************/ +#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + RegOffset) | (Bits)); + + +/****************************************************************************/ +/** +* +* This macro clears the given bits in the register. +* +* @param InstancePtr is a pointer to XUsbPs instance of the controller. +* @param RegOffset is the register offset to be written. +* @param Bits are the bits to be cleared in the register +* +* @return None. +* +* @note +* C-style signature: +* void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits) +* +*****************************************************************************/ +#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \ + XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset, \ + XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + RegOffset) & ~(Bits)); + + +/************************** Function Prototypes ******************************/ + +/** + * Setup / Initialize functions. + * + * Implemented in file xusbps.c + */ +int XUsbPs_CfgInitialize(XUsbPs *InstancePtr, + const XUsbPs_Config *ConfigPtr, u32 BaseAddress); + +int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr, + const XUsbPs_DeviceConfig *CfgPtr); + +/** + * Common functions used for DEVICE/HOST mode. + */ +int XUsbPs_Reset(XUsbPs *InstancePtr); + +void XUsbPs_DeviceReset(XUsbPs *InstancePtr); + +/** + * DEVICE mode specific functions. + */ +int XUsbPs_BusReset(XUsbPs *InstancePtr); +int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address); + + +/** + * Handling Suspend and Resume. + * + * Implemented in xusbps.c + */ +int XUsbPs_Suspend(const XUsbPs *InstancePtr); +int XUsbPs_Resume(const XUsbPs *InstancePtr); +int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr); + + +/* + * Functions for managing Endpoints / Transfers + * + * Implemented in file xusbps_endpoint.c + */ +int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum, + const u8 *BufferPtr, u32 BufferLen); +int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum, + const u8 *BufferPtr, u32 BufferLen); +int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum, + u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle); +void XUsbPs_EpBufferRelease(u32 Handle); + +int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction, + XUsbPs_EpHandlerFunc CallBackFunc, + void *CallBackRef); +int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum, + XUsbPs_SetupData *SetupDataPtr); + +int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction); + +int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr, + int EpNum, unsigned short NewDirection, int DirectionChanged); + +/* + * Interrupt handling functions + * + * Implemented in file xusbps_intr.c + */ +void XUsbPs_IntrHandler(void *InstancePtr); + +int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr, + XUsbPs_IntrHandlerFunc CallBackFunc, + void *CallBackRef, u32 Mask); +/* + * Helper functions for static configuration. + * Implemented in xusbps_sinit.c + */ +XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* XUSBPS_H */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h new file mode 100644 index 0000000..1cb0cfc --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_endpoint.h @@ -0,0 +1,515 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusbps_endpoint.h +* @addtogroup usbps_v2_4 +* @{ + * + * This is an internal file containung the definitions for endpoints. It is + * included by the xusbps_endpoint.c which is implementing the endpoint + * functions and by xusbps_intr.c. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ *
    + * + ******************************************************************************/ +#ifndef XUSBPS_ENDPOINT_H +#define XUSBPS_ENDPOINT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xusbps.h" +#include "xil_types.h" + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + + +/** + * Endpoint Device Transfer Descriptor + * + * The dTD describes to the device controller the location and quantity of data + * to be sent/received for given transfer. The driver does not attempt to + * modify any field in an active dTD except the Next Link Pointer. + */ +#define XUSBPS_dTDNLP 0x00 /**< Pointer to the next descriptor */ +#define XUSBPS_dTDTOKEN 0x04 /**< Descriptor Token */ +#define XUSBPS_dTDBPTR0 0x08 /**< Buffer Pointer 0 */ +#define XUSBPS_dTDBPTR1 0x0C /**< Buffer Pointer 1 */ +#define XUSBPS_dTDBPTR2 0x10 /**< Buffer Pointer 2 */ +#define XUSBPS_dTDBPTR3 0x14 /**< Buffer Pointer 3 */ +#define XUSBPS_dTDBPTR4 0x18 /**< Buffer Pointer 4 */ +#define XUSBPS_dTDBPTR(n) (XUSBPS_dTDBPTR0 + (n) * 0x04) +#define XUSBPS_dTDRSRVD 0x1C /**< Reserved field */ + +/* We use the reserved field in the dTD to store user data. */ +#define XUSBPS_dTDUSERDATA XUSBPS_dTDRSRVD /**< Reserved field */ + + +/** @name dTD Next Link Pointer (dTDNLP) bit positions. + * @{ + */ +#define XUSBPS_dTDNLP_T_MASK 0x00000001 + /**< USB dTD Next Link Pointer Terminate Bit */ +#define XUSBPS_dTDNLP_ADDR_MASK 0xFFFFFFE0 + /**< USB dTD Next Link Pointer Address [31:5] */ +/* @} */ + + +/** @name dTD Token (dTDTOKEN) bit positions. + * @{ + */ +#define XUSBPS_dTDTOKEN_XERR_MASK 0x00000008 /**< dTD Transaction Error */ +#define XUSBPS_dTDTOKEN_BUFERR_MASK 0x00000020 /**< dTD Data Buffer Error */ +#define XUSBPS_dTDTOKEN_HALT_MASK 0x00000040 /**< dTD Halted Flag */ +#define XUSBPS_dTDTOKEN_ACTIVE_MASK 0x00000080 /**< dTD Active Bit */ +#define XUSBPS_dTDTOKEN_MULTO_MASK 0x00000C00 /**< Multiplier Override Field [1:0] */ +#define XUSBPS_dTDTOKEN_IOC_MASK 0x00008000 /**< Interrupt on Complete Bit */ +#define XUSBPS_dTDTOKEN_LEN_MASK 0x7FFF0000 /**< Transfer Length Field */ +/* @} */ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * + * IMPORTANT NOTE: + * =============== + * + * Many of the following macros modify Device Queue Head (dQH) data structures + * and Device Transfer Descriptor (dTD) data structures. Those structures can + * potentially reside in CACHED memory. Therefore, it's the callers + * responsibility to ensure cache coherency by using provided + * + * XUsbPs_dQHInvalidateCache() + * XUsbPs_dQHFlushCache() + * XUsbPs_dTDInvalidateCache() + * XUsbPs_dTDFlushCache() + * + * function calls. + * + ******************************************************************************/ +#define XUsbPs_dTDInvalidateCache(dTDPtr) \ + Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) + +#define XUsbPs_dTDFlushCache(dTDPtr) \ + Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD)) + +#define XUsbPs_dQHInvalidateCache(dQHPtr) \ + Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) + +#define XUsbPs_dQHFlushCache(dQHPtr) \ + Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH)) + +/*****************************************************************************/ +/** + * + * This macro sets the Transfer Length for the given Transfer Descriptor. + * + * @param dTDPtr is pointer to the dTD element. + * @param Len is the length to be set. Range: 0..16384 + * + * @note C-style signature: + * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len) + * + ******************************************************************************/ +#define XUsbPs_dTDSetTransferLen(dTDPtr, Len) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ + ~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16)) + + +/*****************************************************************************/ +/** + * + * This macro gets the Next Link pointer of the given Transfer Descriptor. + * + * @param dTDPtr is pointer to the dTD element. + * + * @return TransferLength field of the descriptor. + * + * @note C-style signature: + * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDGetNLP(dTDPtr) \ + (XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\ + & XUSBPS_dTDNLP_ADDR_MASK)) + + +/*****************************************************************************/ +/** + * + * This macro sets the Next Link pointer of the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * @param NLP is the Next Link Pointer + * + * @note C-style signature: + * void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len) + * + ******************************************************************************/ +#define XUsbPs_dTDSetNLP(dTDPtr, NLP) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + (XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ + ~XUSBPS_dTDNLP_ADDR_MASK) | \ + ((NLP) & XUSBPS_dTDNLP_ADDR_MASK)) + + +/*****************************************************************************/ +/** + * + * This macro gets the Transfer Length for the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @return TransferLength field of the descriptor. + * + * @note C-style signature: + * u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDGetTransferLen(dTDPtr) \ + (u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) \ + & XUSBPS_dTDTOKEN_LEN_MASK) >> 16) + + +/*****************************************************************************/ +/** + * + * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer + * Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @note C-style signature: + * void XUsbPs_dTDSetIOC(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDSetIOC(dTDPtr) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ + XUSBPS_dTDTOKEN_IOC_MASK) + + +/*****************************************************************************/ +/** + * + * This macro sets the Terminate bit for the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @note C-style signature: + * void XUsbPs_dTDSetTerminate(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDSetTerminate(dTDPtr) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) | \ + XUSBPS_dTDNLP_T_MASK) + + +/*****************************************************************************/ +/** + * + * This macro clears the Terminate bit for the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @note C-style signature: + * void XUsbPs_dTDClrTerminate(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDClrTerminate(dTDPtr) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, \ + XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) & \ + ~XUSBPS_dTDNLP_T_MASK) + + +/*****************************************************************************/ +/** + * + * This macro checks if the given descriptor is active. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @return + * - TRUE: The buffer is active. + * - FALSE: The buffer is not active. + * + * @note C-style signature: + * int XUsbPs_dTDIsActive(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDIsActive(dTDPtr) \ + ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) & \ + XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * + * This macro sets the Active bit for the given Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * + * @note C-style signature: + * void XUsbPs_dTDSetActive(u32 dTDPtr) + * + ******************************************************************************/ +#define XUsbPs_dTDSetActive(dTDPtr) \ + XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, \ + XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) | \ + XUSBPS_dTDTOKEN_ACTIVE_MASK) + + +/*****************************************************************************/ +/** + * + * This macro reads the content of a field in a Transfer Descriptor. + * + * @param dTDPtr is a pointer to the dTD element. + * @param Id is the field ID inside the dTD element to read. + * + * @note C-style signature: + * u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id) + * + ******************************************************************************/ +#define XUsbPs_ReaddTD(dTDPtr, Id) (*(u32 *)((u32)(dTDPtr) + (u32)(Id))) + +/*****************************************************************************/ +/** + * + * This macro writes a value to a field in a Transfer Descriptor. + * + * @param dTDPtr is pointer to the dTD element. + * @param Id is the field ID inside the dTD element to read. + * @param Val is the value to write to the field. + * + * @note C-style signature: + * u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val) + * + ******************************************************************************/ +#define XUsbPs_WritedTD(dTDPtr, Id, Val) \ + (*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val)) + + +/******************************************************************************/ +/** + * Endpoint Device Queue Head + * + * Device queue heads are arranged in an array in a continuous area of memory + * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index + * into this array based upon the endpoint number received from the USB bus. + * All information necessary to respond to transactions for all primed + * transfers is contained in this list so the Device Controller can readily + * respond to incoming requests without having to traverse a linked list. + * + * The device Endpoint Queue Head (dQH) is where all transfers are managed. The + * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary. + * During priming of an endpoint, the dTD (device transfer descriptor) is + * copied into the overlay area of the dQH, which starts at the nextTD pointer + * DWord and continues through the end of the buffer pointers DWords. After a + * transfer is complete, the dTD status DWord is updated in the dTD pointed to + * by the currentTD pointer. While a packet is in progress, the overlay area of + * the dQH is used as a staging area for the dTD so that the Device Controller + * can access needed information with little minimal latency. + * + * @note + * Software must ensure that no interface data structure reachable by the + * Device Controller spans a 4K-page boundary. The first element of the + * Endpoint Queue Head List must be aligned on a 4K boundary. + */ +#define XUSBPS_dQHCFG 0x00 /**< dQH Configuration */ +#define XUSBPS_dQHCPTR 0x04 /**< dQH Current dTD Pointer */ +#define XUSBPS_dQHdTDNLP 0x08 /**< dTD Next Link Ptr in dQH + overlay */ +#define XUSBPS_dQHdTDTOKEN 0x0C /**< dTD Token in dQH overlay */ +#define XUSBPS_dQHSUB0 0x28 /**< USB dQH Setup Buffer 0 */ +#define XUSBPS_dQHSUB1 0x2C /**< USB dQH Setup Buffer 1 */ + + +/** @name dQH Configuration (dQHCFG) bit positions. + * @{ + */ +#define XUSBPS_dQHCFG_IOS_MASK 0x00008000 + /**< USB dQH Interrupt on Setup Bit */ +#define XUSBPS_dQHCFG_MPL_MASK 0x07FF0000 + /**< USB dQH Maximum Packet Length + * Field [10:0] */ +#define XUSBPS_dQHCFG_MPL_SHIFT 16 +#define XUSBPS_dQHCFG_ZLT_MASK 0x20000000 + /**< USB dQH Zero Length Termination + * Select Bit */ +#define XUSBPS_dQHCFG_MULT_MASK 0xC0000000 + /* USB dQH Number of Transactions Field + * [1:0] */ +#define XUSBPS_dQHCFG_MULT_SHIFT 30 +/* @} */ + + +/*****************************************************************************/ +/** + * + * This macro sets the Maximum Packet Length field of the give Queue Head. + * + * @param dQHPtr is a pointer to the dQH element. + * @param Len is the length to be set. + * + * @note C-style signature: + * void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len) + * + ******************************************************************************/ +#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + (XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ + ~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16)) + +/*****************************************************************************/ +/** + * + * This macro sets the Interrupt On Setup (IOS) bit for an endpoint. + * + * @param dQHPtr is a pointer to the dQH element. + * + * @note C-style signature: + * void XUsbPs_dQHSetIOS(u32 dQHPtr) + * + ******************************************************************************/ +#define XUsbPs_dQHSetIOS(dQHPtr) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ + XUSBPS_dQHCFG_IOS_MASK) + +/*****************************************************************************/ +/** + * + * This macro clears the Interrupt On Setup (IOS) bit for an endpoint. + * + * @param dQHPtr is a pointer to the dQH element. + * + * @note C-style signature: + * void XUsbPs_dQHClrIOS(u32 dQHPtr) + * + ******************************************************************************/ +#define XUsbPs_dQHClrIOS(dQHPtr) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ + ~XUSBPS_dQHCFG_IOS_MASK) + +/*****************************************************************************/ +/** + * + * This macro enables Zero Length Termination for the endpoint. + * + * @param dQHPtr is a pointer to the dQH element. + * + * @note C-style signature: + * void XUsbPs_dQHEnableZLT(u32 dQHPtr) + * + * + ******************************************************************************/ +#define XUsbPs_dQHEnableZLT(dQHPtr) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) & \ + ~XUSBPS_dQHCFG_ZLT_MASK) + + +/*****************************************************************************/ +/** + * + * This macro disables Zero Length Termination for the endpoint. + * + * @param dQHPtr is a pointer to the dQH element. + * + * @note C-style signature: + * void XUsbPs_dQHDisableZLT(u32 dQHPtr) + * + * + ******************************************************************************/ +#define XUsbPs_dQHDisableZLT(dQHPtr) \ + XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, \ + XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) | \ + XUSBPS_dQHCFG_ZLT_MASK) + +/*****************************************************************************/ +/** + * + * This macro reads the content of a field in a Queue Head. + * + * @param dQHPtr is a pointer to the dQH element. + * @param Id is the Field ID inside the dQH element to read. + * + * @note C-style signature: + * u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id) + * + ******************************************************************************/ +#define XUsbPs_ReaddQH(dQHPtr, Id) (*(u32 *)((u32)(dQHPtr) + (u32) (Id))) + +/*****************************************************************************/ +/** + * + * This macro writes a value to a field in a Queue Head. + * + * @param dQHPtr is a pointer to the dQH element. + * @param Id is the Field ID inside the dQH element to read. + * @param Val is the Value to write to the field. + * + * @note C-style signature: + * u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val) + * + ******************************************************************************/ +#define XUsbPs_WritedQH(dQHPtr, Id, Val) \ + (*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val)) + + + +#ifdef __cplusplus +} +#endif + +#endif /* XUSBPS_ENDPOINT_H */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_hw.h new file mode 100644 index 0000000..69f3ebf --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/include/xusbps_hw.h @@ -0,0 +1,526 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusbps_hw.h +* @addtogroup usbps_v2_4 +* @{ + * + * This header file contains identifiers and low-level driver functions (or + * macros) that can be used to access the device. High-level driver functions + * are defined in xusbps.h. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ * 1.05a kpc  07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc  04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks 
+ *
    + * + ******************************************************************************/ +#ifndef XUSBPS_HW_H +#define XUSBPS_HW_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + + +#define XUSBPS_REG_SPACING 4 + +/** @name Timer 0 Register offsets + * + * @{ + */ +#define XUSBPS_TIMER0_LD_OFFSET 0x00000080 +#define XUSBPS_TIMER0_CTL_OFFSET 0x00000084 +/* @} */ + +/** @name Timer Control Register bit mask + * + * @{ + */ +#define XUSBPS_TIMER_RUN_MASK 0x80000000 +#define XUSBPS_TIMER_STOP_MASK 0x80000000 +#define XUSBPS_TIMER_RESET_MASK 0x40000000 +#define XUSBPS_TIMER_REPEAT_MASK 0x01000000 +/* @} */ + +/** @name Timer Control Register bit mask + * + * @{ + */ +#define XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF +/* @} */ + +/** @name Device Hardware Parameters + * + * @{ + */ +#define XUSBPS_HWDEVICE_OFFSET 0x0000000C + +#define XUSBPS_EP_NUM_MASK 0x3E +#define XUSBPS_EP_NUM_SHIFT 1 +/* @} */ + +/** @name Capability Regsiter offsets + */ +#define XUSBPS_HCSPARAMS_OFFSET 0x00000104 + +/** @name Operational Register offsets. + * Register comments are tagged with "H:" and "D:" for Host and Device modes, + * respectively. + * Tags are only present for registers that have a different meaning DEVICE and + * HOST modes. Most registers are only valid for either DEVICE or HOST mode. + * Those registers don't have tags. + * @{ + */ +#define XUSBPS_CMD_OFFSET 0x00000140 /**< Configuration */ +#define XUSBPS_ISR_OFFSET 0x00000144 /**< Interrupt Status */ +#define XUSBPS_IER_OFFSET 0x00000148 /**< Interrupt Enable */ +#define XUSBPS_FRAME_OFFSET 0x0000014C /**< USB Frame Index */ +#define XUSBPS_LISTBASE_OFFSET 0x00000154 /**< H: Periodic List Base Address */ +#define XUSBPS_DEVICEADDR_OFFSET 0x00000154 /**< D: Device Address */ +#define XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 /**< H: Async List Address */ +#define XUSBPS_EPLISTADDR_OFFSET 0x00000158 /**< D: Endpoint List Addr */ +#define XUSBPS_TTCTRL_OFFSET 0x0000015C /**< TT Control */ +#define XUSBPS_BURSTSIZE_OFFSET 0x00000160 /**< Burst Size */ +#define XUSBPS_TXFILL_OFFSET 0x00000164 /**< Tx Fill Tuning */ +#define XUSBPS_ULPIVIEW_OFFSET 0x00000170 /**< ULPI Viewport */ +#define XUSBPS_EPNAKISR_OFFSET 0x00000178 /**< Endpoint NAK IRQ Status */ +#define XUSBPS_EPNAKIER_OFFSET 0x0000017C /**< Endpoint NAK IRQ Enable */ +#define XUSBPS_PORTSCR1_OFFSET 0x00000184 /**< Port Control/Status 1 */ + +/* NOTE: The Port Control / Status Register index is 1-based. */ +#define XUSBPS_PORTSCRn_OFFSET(n) \ + (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) + + +#define XUSBPS_OTGCSR_OFFSET 0x000001A4 /**< OTG Status and Control */ +#define XUSBPS_MODE_OFFSET 0x000001A8 /**< USB Mode */ +#define XUSBPS_EPSTAT_OFFSET 0x000001AC /**< Endpoint Setup Status */ +#define XUSBPS_EPPRIME_OFFSET 0x000001B0 /**< Endpoint Prime */ +#define XUSBPS_EPFLUSH_OFFSET 0x000001B4 /**< Endpoint Flush */ +#define XUSBPS_EPRDY_OFFSET 0x000001B8 /**< Endpoint Ready */ +#define XUSBPS_EPCOMPL_OFFSET 0x000001BC /**< Endpoint Complete */ +#define XUSBPS_EPCR0_OFFSET 0x000001C0 /**< Endpoint Control 0 */ +#define XUSBPS_EPCR1_OFFSET 0x000001C4 /**< Endpoint Control 1 */ +#define XUSBPS_EPCR2_OFFSET 0x000001C8 /**< Endpoint Control 2 */ +#define XUSBPS_EPCR3_OFFSET 0x000001CC /**< Endpoint Control 3 */ +#define XUSBPS_EPCR4_OFFSET 0x000001D0 /**< Endpoint Control 4 */ + +#define XUSBPS_MAX_ENDPOINTS 12 /**< Number of supported Endpoints in + * this core. */ +#define XUSBPS_EP_OUT_MASK 0x00000FFF /**< OUR (RX) endpoint mask */ +#define XUSBPS_EP_IN_MASK 0x0FFF0000 /**< IN (TX) endpoint mask */ +#define XUSBPS_EP_ALL_MASK 0x0FFF0FFF /**< Mask used for endpoint control + * registers */ +#define XUSBPS_EPCRn_OFFSET(n) \ + (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) + +#define XUSBPS_EPFLUSH_RX_SHIFT 0 +#define XUSBPS_EPFLUSH_TX_SHIFT 16 + +/* @} */ + + + +/** @name Endpoint Control Register (EPCR) bit positions. + * @{ + */ + +/* Definitions for TX Endpoint bits */ +#define XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - TX */ +#define XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 /**< Isochronous. Endpoint */ +#define XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 /**< Bulk Endpoint - TX */ +#define XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 /**< Interrupt Endpoint */ +#define XUSBPS_EPCR_TXS_MASK 0x00010000 /**< Stall TX endpoint */ +#define XUSBPS_EPCR_TXE_MASK 0x00800000 /**< Transmit enable - TX */ +#define XUSBPS_EPCR_TXR_MASK 0x00400000 /**< Data Toggle Reset Bit */ + + +/* Definitions for RX Endpoint bits */ +#define XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 /**< Control Endpoint - RX */ +#define XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 /**< Isochronous Endpoint */ +#define XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 /**< Bulk Endpoint - RX */ +#define XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C /**< Interrupt Endpoint */ +#define XUSBPS_EPCR_RXS_MASK 0x00000001 /**< Stall RX endpoint. */ +#define XUSBPS_EPCR_RXE_MASK 0x00000080 /**< Transmit enable. - RX */ +#define XUSBPS_EPCR_RXR_MASK 0x00000040 /**< Data Toggle Reset Bit */ +/* @} */ + + +/** @name USB Command Register (CR) bit positions. + * @{ + */ +#define XUSBPS_CMD_RS_MASK 0x00000001 /**< Run/Stop */ +#define XUSBPS_CMD_RST_MASK 0x00000002 /**< Controller RESET */ +#define XUSBPS_CMD_FS01_MASK 0x0000000C /**< Frame List Size bit 0,1 */ +#define XUSBPS_CMD_PSE_MASK 0x00000010 /**< Periodic Sched Enable */ +#define XUSBPS_CMD_ASE_MASK 0x00000020 /**< Async Sched Enable */ +#define XUSBPS_CMD_IAA_MASK 0x00000040 /**< IRQ Async Advance Doorbell */ +#define XUSBPS_CMD_ASP_MASK 0x00000300 /**< Async Sched Park Mode Cnt */ +#define XUSBPS_CMD_ASPE_MASK 0x00000800 /**< Async Sched Park Mode Enbl */ +#define XUSBPS_CMD_SUTW_MASK 0x00002000 /**< Setup TripWire */ +#define XUSBPS_CMD_ATDTW_MASK 0x00004000 /**< Add dTD TripWire */ +#define XUSBPS_CMD_FS2_MASK 0x00008000 /**< Frame List Size bit 2 */ +#define XUSBPS_CMD_ITC_MASK 0x00FF0000 /**< IRQ Threshold Control */ +/* @} */ + + +/** + * @name Interrupt Threshold + * These definitions are used by software to set the maximum rate at which the + * USB controller will generate interrupt requests. The interrupt interval is + * given in number of micro-frames. + * + * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF) + * packet each and every 1ms. USB also defines a high-speed micro-frame with a + * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is + * generated. Data is sent in between the SOF packets. The interrupt threshold + * defines how many micro-frames the controller waits before issuing an + * interrupt after data has been received. + * + * For a threshold of 0 the controller will issue an interrupt immediately + * after the last byte of the data has been received. For a threshold n>0 the + * controller will wait for n micro-frames before issuing an interrupt. + * + * Therefore, a setting of 8 micro-frames (default) means that the controller + * will issue at most 1 interrupt per millisecond. + * + * @{ + */ +#define XUSBPS_CMD_ITHRESHOLD_0 0x00 /**< Immediate interrupt. */ +#define XUSBPS_CMD_ITHRESHOLD_1 0x01 /**< 1 micro-frame */ +#define XUSBPS_CMD_ITHRESHOLD_2 0x02 /**< 2 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_4 0x04 /**< 4 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_8 0x08 /**< 8 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_16 0x10 /**< 16 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_32 0x20 /**< 32 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_64 0x40 /**< 64 micro-frames */ +#define XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64 +#define XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8 +/* @} */ + + + +/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER) + * bit positions. + * @{ + */ +#define XUSBPS_IXR_UI_MASK 0x00000001 /**< USB Transaction Complete */ +#define XUSBPS_IXR_UE_MASK 0x00000002 /**< Transaction Error */ +#define XUSBPS_IXR_PC_MASK 0x00000004 /**< Port Change Detect */ +#define XUSBPS_IXR_FRE_MASK 0x00000008 /**< Frame List Rollover */ +#define XUSBPS_IXR_AA_MASK 0x00000020 /**< Async Advance */ +#define XUSBPS_IXR_UR_MASK 0x00000040 /**< RESET Received */ +#define XUSBPS_IXR_SR_MASK 0x00000080 /**< Start of Frame */ +#define XUSBPS_IXR_SLE_MASK 0x00000100 /**< Device Controller Suspend */ +#define XUSBPS_IXR_ULPI_MASK 0x00000400 /**< ULPI IRQ */ +#define XUSBPS_IXR_HCH_MASK 0x00001000 /**< Host Controller Halted + * Read Only */ +#define XUSBPS_IXR_RCL_MASK 0x00002000 /**< USB Reclamation Read Only */ +#define XUSBPS_IXR_PS_MASK 0x00004000 /**< Periodic Sched Status + * Read Only */ +#define XUSBPS_IXR_AS_MASK 0x00008000 /**< Async Sched Status Read only */ +#define XUSBPS_IXR_NAK_MASK 0x00010000 /**< NAK IRQ */ +#define XUSBPS_IXR_UA_MASK 0x00040000 /**< USB Host Async IRQ */ +#define XUSBPS_IXR_UP_MASK 0x00080000 /**< USB Host Periodic IRQ */ +#define XUSBPS_IXR_TI0_MASK 0x01000000 /**< Timer 0 Interrupt */ +#define XUSBPS_IXR_TI1_MASK 0x02000000 /**< Timer 1 Interrupt */ + +#define XUSBPS_IXR_ALL (XUSBPS_IXR_UI_MASK | \ + XUSBPS_IXR_UE_MASK | \ + XUSBPS_IXR_PC_MASK | \ + XUSBPS_IXR_FRE_MASK | \ + XUSBPS_IXR_AA_MASK | \ + XUSBPS_IXR_UR_MASK | \ + XUSBPS_IXR_SR_MASK | \ + XUSBPS_IXR_SLE_MASK | \ + XUSBPS_IXR_ULPI_MASK | \ + XUSBPS_IXR_HCH_MASK | \ + XUSBPS_IXR_RCL_MASK | \ + XUSBPS_IXR_PS_MASK | \ + XUSBPS_IXR_AS_MASK | \ + XUSBPS_IXR_NAK_MASK | \ + XUSBPS_IXR_UA_MASK | \ + XUSBPS_IXR_UP_MASK | \ + XUSBPS_IXR_TI0_MASK | \ + XUSBPS_IXR_TI1_MASK) + /**< Mask for ALL IRQ types */ +/* @} */ + + +/** @name USB Mode Register (MODE) bit positions. + * @{ + */ +#define XUSBPS_MODE_CM_MASK 0x00000003 /**< Controller Mode Select */ +#define XUSBPS_MODE_CM_IDLE_MASK 0x00000000 +#define XUSBPS_MODE_CM_DEVICE_MASK 0x00000002 +#define XUSBPS_MODE_CM_HOST_MASK 0x00000003 +#define XUSBPS_MODE_ES_MASK 0x00000004 /**< USB Endian Select */ +#define XUSBPS_MODE_SLOM_MASK 0x00000008 /**< USB Setup Lockout Mode Disable */ +#define XUSBPS_MODE_SDIS_MASK 0x00000010 +#define XUSBPS_MODE_VALID_MASK 0x0000001F + +/* @} */ + + +/** @name USB Device Address Register (DEVICEADDR) bit positions. + * @{ + */ +#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000 + /**< Device Addr Auto Advance */ +#define XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000 + /**< Device Address */ +#define XUSBPS_DEVICEADDR_ADDR_SHIFT 25 + /**< Address shift */ +#define XUSBPS_DEVICEADDR_MAX 127 + /**< Biggest allowed address */ +/* @} */ + +/** @name USB TT Control Register (TTCTRL) bit positions. + * @{ + */ +#define XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 /**< TT Hub Address */ +/* @} */ + + +/** @name USB Burst Size Register (BURSTSIZE) bit posisions. + * @{ + */ +#define XUSBPS_BURSTSIZE_RX_MASK 0x000000FF /**< RX Burst Length */ +#define XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 /**< TX Burst Length */ +/* @} */ + + +/** @name USB Tx Fill Tuning Register (TXFILL) bit positions. + * @{ + */ +#define XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF + /**< Scheduler Overhead */ +#define XUSBPS_TXFILL_HEALTH_MASK 0x00001F00 + /**< Scheduler Health Cntr */ +#define XUSBPS_TXFILL_BURST_MASK 0x003F0000 + /**< FIFO Burst Threshold */ +/* @} */ + + +/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions. + * @{ + */ +#define XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF /**< ULPI Data Write */ +#define XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 /**< ULPI Data Read */ +#define XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 /**< ULPI Data Address */ +#define XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 /**< ULPI Port Number */ +#define XUSBPS_ULPIVIEW_SS_MASK 0x08000000 /**< ULPI Synchronous State */ +#define XUSBPS_ULPIVIEW_RW_MASK 0x20000000 /**< ULPI Read/Write Control */ +#define XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 /**< ULPI Run */ +#define XUSBPS_ULPIVIEW_WU_MASK 0x80000000 /**< ULPI Wakeup */ +/* @} */ + + +/** @name Port Status Control Register bit positions. + * @{ + */ +#define XUSBPS_PORTSCR_CCS_MASK 0x00000001 /**< Current Connect Status */ +#define XUSBPS_PORTSCR_CSC_MASK 0x00000002 /**< Connect Status Change */ +#define XUSBPS_PORTSCR_PE_MASK 0x00000004 /**< Port Enable/Disable */ +#define XUSBPS_PORTSCR_PEC_MASK 0x00000008 /**< Port Enable/Disable Change */ +#define XUSBPS_PORTSCR_OCA_MASK 0x00000010 /**< Over-current Active */ +#define XUSBPS_PORTSCR_OCC_MASK 0x00000020 /**< Over-current Change */ +#define XUSBPS_PORTSCR_FPR_MASK 0x00000040 /**< Force Port Resume */ +#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */ +#define XUSBPS_PORTSCR_PR_MASK 0x00000100 /**< Port Reset */ +#define XUSBPS_PORTSCR_HSP_MASK 0x00000200 /**< High Speed Port */ +#define XUSBPS_PORTSCR_LS_MASK 0x00000C00 /**< Line Status */ +#define XUSBPS_PORTSCR_PP_MASK 0x00001000 /**< Port Power */ +#define XUSBPS_PORTSCR_PO_MASK 0x00002000 /**< Port Owner */ +#define XUSBPS_PORTSCR_PIC_MASK 0x0000C000 /**< Port Indicator Control */ +#define XUSBPS_PORTSCR_PTC_MASK 0x000F0000 /**< Port Test Control */ +#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */ +#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */ +#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */ +#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend - + * Clock Disable */ +#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed + * Connect */ +#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */ +/* @} */ + + +/** @name On-The-Go Status Control Register (OTGCSR) bit positions. + * @{ + */ +#define XUSBPS_OTGSC_VD_MASK 0x00000001 /**< VBus Discharge Bit */ +#define XUSBPS_OTGSC_VC_MASK 0x00000002 /**< VBus Charge Bit */ +#define XUSBPS_OTGSC_HAAR_MASK 0x00000004 /**< HW Assist Auto Reset + * Enable Bit */ +#define XUSBPS_OTGSC_OT_MASK 0x00000008 /**< OTG Termination Bit */ +#define XUSBPS_OTGSC_DP_MASK 0x00000010 /**< Data Pulsing Pull-up + * Enable Bit */ +#define XUSBPS_OTGSC_IDPU_MASK 0x00000020 /**< ID Pull-up Enable Bit */ +#define XUSBPS_OTGSC_HADP_MASK 0x00000040 /**< HW Assist Data Pulse + * Enable Bit */ +#define XUSBPS_OTGSC_HABA_MASK 0x00000080 /**< USB Hardware Assist + * B Disconnect to A + * Connect Enable Bit */ +#define XUSBPS_OTGSC_ID_MASK 0x00000100 /**< ID Status Flag */ +#define XUSBPS_OTGSC_AVV_MASK 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_ASV_MASK 0x00000400 /**< USB A Session Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_BSV_MASK 0x00000800 /**< USB B Session Valid Status Flag */ +#define XUSBPS_OTGSC_BSE_MASK 0x00001000 /**< USB B Session End Status Flag */ +#define XUSBPS_OTGSC_1MST_MASK 0x00002000 /**< USB 1 Millisecond Timer Status Flag */ +#define XUSBPS_OTGSC_DPS_MASK 0x00004000 /**< Data Pulse Status Flag */ +#define XUSBPS_OTGSC_IDIS_MASK 0x00010000 /**< USB ID Interrupt Status Flag */ +#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */ +#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */ +#define XUSBPS_OTGSC_1MSS_MASK 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */ +#define XUSBPS_OTGSC_DPIS_MASK 0x00400000 /**< Data Pulse Interrupt Status Flag */ +#define XUSBPS_OTGSC_IDIE_MASK 0x01000000 /**< ID Interrupt Enable Bit */ +#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */ +#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */ +#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */ +#define XUSBPS_OTGSC_BSEE_MASK 0x10000000 /**< USB B Session End Interrupt Enable Bit */ +#define XUSBPS_OTGSC_1MSE_MASK 0x20000000 /**< 1 Millisecond Timer + * Interrupt Enable Bit */ +#define XUSBPS_OTGSC_DPIE_MASK 0x40000000 /**< Data Pulse Interrupt + * Enable Bit */ + +#define XUSBPS_OTG_ISB_ALL (XUSBPS_OTGSC_IDIS_MASK |\ + XUSBPS_OTGSC_AVVIS_MASK | \ + XUSBPS_OTGSC_ASVIS_MASK | \ + XUSBPS_OTGSC_BSVIS_MASK | \ + XUSBPS_OTGSC_BSEIS_MASK | \ + XUSBPS_OTGSC_1MSS_MASK | \ + XUSBPS_OTGSC_DPIS_MASK) + /** Mask for All IRQ status masks */ + +#define XUSBPS_OTG_IEB_ALL (XUSBPS_OTGSC_IDIE_MASK |\ + XUSBPS_OTGSC_AVVIE_MASK | \ + XUSBPS_OTGSC_ASVIE_MASK | \ + XUSBPS_OTGSC_BSVIE_MASK | \ + XUSBPS_OTGSC_BSEE_IEB_MASK | \ + XUSBPS_OTGSC_1MSE_MASK | \ + XUSBPS_OTGSC_DPIE_MASK) + /** Mask for All IRQ Enable masks */ +/* @} */ + + +/**< Alignment of the Device Queue Head List BASE. */ +#define XUSBPS_dQH_BASE_ALIGN 2048 + +/**< Alignment of a Device Queue Head structure. */ +#define XUSBPS_dQH_ALIGN 64 + +/**< Alignment of a Device Transfer Descriptor structure. */ +#define XUSBPS_dTD_ALIGN 32 + +/**< Size of one RX buffer for a OUT Transfer Descriptor. */ +#define XUSBPS_dTD_BUF_SIZE 4096 + +/**< Maximum size of one RX/TX buffer. */ +#define XUSBPS_dTD_BUF_MAX_SIZE 16*1024 + +/**< Alignment requirement for Transfer Descriptor buffers. */ +#define XUSBPS_dTD_BUF_ALIGN 4096 + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the base address for the USB registers. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset) +* +*****************************************************************************/ +#define XUsbPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32(BaseAddress + (RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddress is the the base address for the USB registers. +* @param RegOffset is the register offset to be written. +* @param Data is the the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* + *****************************************************************************/ +#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32(BaseAddress + (RegOffset), (Data)) + + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the USB PS interface + */ +void XUsbPs_ResetHw(u32 BaseAddress); +/************************** Variable Definitions ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* XUSBPS_L_H */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c new file mode 100644 index 0000000..f852de4 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c @@ -0,0 +1,1205 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.c +* @addtogroup canps_v3_2 +* @{ +* +* Functions in this file are the minimum required functions for the XCanPs +* driver. See xcanps.h for a detailed description of the driver. +* +* @note None. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +static void StubHandler(void); + +/*****************************************************************************/ +/* +* +* This function initializes a XCanPs instance/driver. +* +* The initialization entails: +* - Initialize all members of the XCanPs structure. +* - Reset the CAN device. The CAN device will enter Configuration Mode +* immediately after the reset is finished. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param ConfigPtr points to the XCanPs device configuration structure. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. If the address translation is not used then the +* physical address is passed. +* Unexpected errors may occur if the address mapping is changed +* after this function is invoked. +* +* @return XST_SUCCESS always. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * Set some default values for instance data, don't indicate the device + * is ready to use until everything has been initialized successfully. + */ + InstancePtr->IsReady = 0U; + InstancePtr->CanConfig.BaseAddr = EffectiveAddr; + InstancePtr->CanConfig.DeviceId = ConfigPtr->DeviceId; + + /* + * Set all handlers to stub values, let user configure this data later. + */ + InstancePtr->SendHandler = (XCanPs_SendRecvHandler) StubHandler; + InstancePtr->RecvHandler = (XCanPs_SendRecvHandler) StubHandler; + InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) StubHandler; + InstancePtr->EventHandler = (XCanPs_EventHandler) StubHandler; + + /* + * Indicate the component is now ready to use. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + /* + * Reset the device to get it into its initial state. + */ + XCanPs_Reset(InstancePtr); + + Status = XST_SUCCESS; + return Status; +} + +/*****************************************************************************/ +/** +* +* This function resets the CAN device. Calling this function resets the device +* immediately, and any pending transmission or reception is terminated at once. +* Both Object Layer and Transfer Layer are reset. This function does not reset +* the Physical Layer. All registers are reset to the default values, and no +* previous status will be restored. TX FIFO, RX FIFO and TX High Priority +* Buffer are also reset. +* +* When a reset is required due to an internal error, the driver notifies the +* upper layer software of this need through the error status code or interrupts. +* The upper layer software is responsible for calling this Reset function and +* then re-configuring the device. +* +* The CAN device will be in Configuration Mode immediately after this function +* returns. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_Reset(XCanPs *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_SRR_OFFSET, \ + XCANPS_SRR_SRST_MASK); +} + +/****************************************************************************/ +/** +* +* This routine returns the current operation mode of the CAN device. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - XCANPS_MODE_CONFIG if the device is in Configuration Mode. +* - XCANPS_MODE_SLEEP if the device is in Sleep Mode. +* - XCANPS_MODE_NORMAL if the device is in Normal Mode. +* - XCANPS_MODE_LOOPBACK if the device is in Loop Back Mode. +* - XCANPS_MODE_SNOOP if the device is in Snoop Mode. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetMode(XCanPs *InstancePtr) +{ + u32 StatusReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + StatusReg = XCanPs_GetStatus(InstancePtr); + + if ((StatusReg & XCANPS_SR_CONFIG_MASK) != (u32)0) { + return (u8)XCANPS_MODE_CONFIG; + + } + else if ((StatusReg & XCANPS_SR_SLEEP_MASK) != (u32)0) { + return (u8)XCANPS_MODE_SLEEP; + + } + else if ((StatusReg & XCANPS_SR_NORMAL_MASK) != (u32)0) { + if ((StatusReg & XCANPS_SR_SNOOP_MASK) != (u32)0) { + return (u8)XCANPS_MODE_SNOOP; + } else { + return (u8)XCANPS_MODE_NORMAL; + } + } + else { + /* + * If this line is reached, the device is in Loop Back Mode. + */ + return (u8)XCANPS_MODE_LOOPBACK; + } +} + +/*****************************************************************************/ +/** +* +* This function allows the CAN device to enter one of the following operation +* modes: +* - Configuration Mode: Pass in parameter XCANPS_MODE_CONFIG +* - Sleep Mode: Pass in parameter XCANPS_MODE_SLEEP +* - Normal Mode: Pass in parameter XCANPS_MODE_NORMAL +* - Loop Back Mode: Pass in parameter XCANPS_MODE_LOOPBACK. +* - Snoop Mode: Pass in parameter XCANPS_MODE_SNOOP. +* +* Read the xcanps.h file and device specification for detailed description of +* each operation mode. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param OperationMode specify which operation mode to enter. Valid value +* is any of XCANPS_MODE_* defined in xcanps.h. Multiple modes +* can not be entered at the same time. +* +* @return None. +* +* @note +* +* This function does NOT ensure CAN device enters the specified operation mode +* before it returns the control to the caller. The caller is responsible for +* checking current operation mode using XCanPs_GetMode(). +* +******************************************************************************/ +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode) +{ + u8 CurrentMode; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((OperationMode == (u8)XCANPS_MODE_CONFIG) || + (OperationMode == (u8)XCANPS_MODE_SLEEP) || + (OperationMode == (u8)XCANPS_MODE_NORMAL) || + (OperationMode == (u8)XCANPS_MODE_LOOPBACK) || + (OperationMode == (u8)XCANPS_MODE_SNOOP)); + + CurrentMode = XCanPs_GetMode(InstancePtr); + + /* + * If current mode is Normal Mode and the mode to enter is Sleep Mode, + * or if current mode is Sleep Mode and the mode to enter is Normal + * Mode, no transition through Configuration Mode is needed. + */ + if ((CurrentMode == (u8)XCANPS_MODE_NORMAL) && + (OperationMode == (u8)XCANPS_MODE_SLEEP)) { + /* + * Normal Mode ---> Sleep Mode + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK); + return; + + } else if ((CurrentMode == (u8)XCANPS_MODE_SLEEP) && + (OperationMode == (u8)XCANPS_MODE_NORMAL)) { + /* + * Sleep Mode ---> Normal Mode + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, 0U); + return; + } + else { + /*This else was made for misra-c compliance*/ + ; + } + + /* + * If the mode transition is not any of the two cases above, CAN must + * enter Configuration Mode before switching into the target operation + * mode. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, 0U); + + /* + * Check if the device has entered Configuration Mode, if not, return to + * the caller. + */ + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + return; + } + + switch (OperationMode) { + case XCANPS_MODE_CONFIG: + /* + * As CAN is in Configuration Mode already. + * Nothing is needed to be done here. + */ + break; + + case XCANPS_MODE_SLEEP: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_NORMAL: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, 0U); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_LOOPBACK: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_SNOOP: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + + } +} + +/*****************************************************************************/ +/** +* +* This function returns Status value from Status Register (SR). Use the +* XCANPS_SR_* constants defined in xcanps_hw.h to interpret the returned +* value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The 32-bit value read from Status Register. +* +* @note None. +* +******************************************************************************/ +u32 XCanPs_GetStatus(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SR_OFFSET); +} + +/*****************************************************************************/ +/** +* +* This function reads Receive and Transmit error counters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param RxErrorCount is a pointer to data in which the Receive Error +* counter value is returned. +* @param TxErrorCount is a pointer to data in which the Transmit Error +* counter value is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount) +{ + u32 ErrorCount; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(RxErrorCount != NULL); + Xil_AssertVoid(TxErrorCount != NULL); + /* + * Read Error Counter Register and parse it. + */ + ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ECR_OFFSET); + *RxErrorCount = (u8)((ErrorCount & XCANPS_ECR_REC_MASK) >> + XCANPS_ECR_REC_SHIFT); + *TxErrorCount = (u8)(ErrorCount & XCANPS_ECR_TEC_MASK); +} + +/*****************************************************************************/ +/** +* +* This function reads Error Status value from Error Status Register (ESR). Use +* the XCANPS_ESR_* constants defined in xcanps_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The 32-bit value read from Error Status Register. +* +* @note None. +* +******************************************************************************/ +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ESR_OFFSET); +} + +/*****************************************************************************/ +/** +* +* This function clears Error Status bit(s) previously set in Error +* Status Register (ESR). Use the XCANPS_ESR_* constants defined in xcanps_hw.h +* to create the value to pass in. If a bit was cleared in Error Status Register +* before this function is called, it will not be modified. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @param Mask is he 32-bit mask used to clear bits in Error Status +* Register. Multiple XCANPS_ESR_* values can be 'OR'ed to clear +* multiple bits. +* +* @note None. +* +******************************************************************************/ +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ESR_OFFSET, Mask); +} + +/*****************************************************************************/ +/** +* +* This function sends a CAN Frame. If the TX FIFO is not full then the given +* frame is written into the the TX FIFO otherwise, it returns an error code +* immediately. +* This function does not wait for the given frame being sent to CAN bus. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer containing the +* CAN frame to be sent. +* +* @return +* - XST_SUCCESS if TX FIFO was not full and the given frame was +* written into the FIFO. +* - XST_FIFO_NO_ROOM if there is no room in the TX FIFO for the +* given frame. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) { + Status = XST_FIFO_NO_ROOM; + } else { + + /* + * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2])); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3])); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This function receives a CAN Frame. This function first checks if RX FIFO is +* empty, if not, it then reads a frame from the RX FIFO into the given buffer. +* This function returns error code immediately if there is no frame in the RX +* FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer where the CAN +* frame to be written. +* +* @return +* - XST_SUCCESS if RX FIFO was not empty and a frame was read from +* RX FIFO successfully and written into the given buffer. +* - XST_NO_DATA if there is no frame to be received from the FIFO. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) { + Status = XST_NO_DATA; + } else { + + /* + * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device. + */ + FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_ID_OFFSET); + FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DLC_OFFSET); + FramePtr[2] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DW1_OFFSET)); + FramePtr[3] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DW2_OFFSET)); + + /* + * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call + * returns correct RX FIFO occupancy/empty condition. + */ + XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine sends a CAN High Priority frame. This function first checks if +* TX High Priority Buffer is empty. If yes, it then writes the given frame into +* the Buffer. If not, this function returns immediately. This function does not +* wait for the given frame being sent to CAN bus. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer containing the +* CAN High Priority frame to be sent. +* +* @return +* - XST_SUCCESS if TX High Priority Buffer was not full and the +* given frame was written into the buffer. +* - XST_FIFO_NO_ROOM if there is no room in the TX High Priority +* Buffer for this frame. +* +* @note +* +* If the frame needs to be sent immediately and not delayed by processor's +* interrupt handling, the caller should disable interrupt at processor +* level before invoking this function. +* +******************************************************************************/ +s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) { + Status = XST_FIFO_NO_ROOM; + } else { + + /* + * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_ID_OFFSET, FramePtr[0]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2])); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3])); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine enables individual acceptance filters. Up to 4 filters could +* be enabled. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndexes specifies which filter(s) to enable. Use +* any XCANPS_AFR_UAF*_MASK to enable one filter, and "Or" +* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need +* to be enabled. Any filter not specified in this parameter will +* keep its previous enable/disable setting. +* +* @return None. +* +* @note None. +* +* +******************************************************************************/ +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes) +{ + u32 EnabledFilters; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Calculate the new value and write to AFR. + */ + EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + EnabledFilters |= FilterIndexes; + EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET, + EnabledFilters); +} + +/*****************************************************************************/ +/** +* +* This routine disables individual acceptance filters. Up to 4 filters could +* be disabled. If all acceptance filters are disabled then all the received +* frames are stored in the RX FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndexes specifies which filter(s) to disable. Use +* any XCANPS_AFR_UAF*_MASK to disable one filter, and "Or" +* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need +* to be disabled. Any filter not specified in this parameter will +* keep its previous enable/disable setting. If all acceptance +* filters are disabled then all received frames are stored in the +* RX FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes) +{ + u32 EnabledFilters; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Calculate the new value and write to AFR. + */ + EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET, + EnabledFilters); +} + +/*****************************************************************************/ +/** +* +* This function returns enabled acceptance filters. Use XCANPS_AFR_UAF*_MASK +* defined in xcanps_hw.h to interpret the returned value. If no acceptance +* filters are enabled then all received frames are stored in the RX FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The value stored in Acceptance Filter Register. +* +* @note None. +* +* +******************************************************************************/ +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + +} + +/*****************************************************************************/ +/** +* +* This function sets values to the Acceptance Filter Mask Register (AFMR) and +* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter. +* Use XCANPS_IDR_* defined in xcanps_hw.h to create the values to set the +* filter. Read the xcanps.h file and device specification for details. +* +* This function should be called only after: +* - The given filter is disabled by calling XCanPs_AcceptFilterDisable() +* - And the CAN device is ready to accept writes to AFMR and AFIR, i.e., +* XCanPs_IsAcceptFilterBusy() returns FALSE. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndex defines which Acceptance Filter Mask and ID Register +* to set. Use any single XCANPS_AFR_UAF*_MASK value. +* @param MaskValue is the value to write to the chosen Acceptance Filter +* Mask Register. +* @param IdValue is the value to write to the chosen Acceptance Filter +* ID Register. +* +* @return +* - XST_SUCCESS if the values were set successfully. +* - XST_FAILURE if the given filter was not disabled, or the CAN +* device was not ready to accept writes to AFMR and AFIR. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue) +{ + u32 EnabledFilters; + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((FilterIndex == XCANPS_AFR_UAF4_MASK) || + (FilterIndex == XCANPS_AFR_UAF3_MASK) || + (FilterIndex == XCANPS_AFR_UAF2_MASK) || + (FilterIndex == XCANPS_AFR_UAF1_MASK)); + + /* + * Return an error if the given filter is currently enabled. + */ + EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr); + if ((EnabledFilters & FilterIndex) == FilterIndex) { + Status = XST_FAILURE; + } else { + + /* + * If the CAN device is not ready to accept writes to AFMR and AFIR, + * return error code. + */ + if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) { + Status = XST_FAILURE; + } else { + + /* + * Write to the AFMR and AFIR of the specified filter. + */ + switch (FilterIndex) { + case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */ + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR1_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR1_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR2_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR2_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR3_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR3_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR4_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR4_OFFSET, IdValue); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + } + + Status = XST_SUCCESS; + } + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This function reads the values of the Acceptance Filter Mask and ID Register +* for the specified Acceptance Filter. Use XCANPS_IDR_* defined in xcanps_hw.h +* to interpret the values. Read the xcanps.h file and device specification for +* details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndex defines which Acceptance Filter Mask Register to get +* Mask and ID from. Use any single XCANPS_FILTER_* value. +* @param MaskValue is a pointer to the data in which the Mask value read +* from the chosen Acceptance Filter Mask Register is returned. +* @param IdValue is a pointer to the data in which the ID value read +* from the chosen Acceptance Filter ID Register is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((FilterIndex == XCANPS_AFR_UAF4_MASK) || + (FilterIndex == XCANPS_AFR_UAF3_MASK) || + (FilterIndex == XCANPS_AFR_UAF2_MASK) || + (FilterIndex == XCANPS_AFR_UAF1_MASK)); + Xil_AssertVoid(MaskValue != NULL); + Xil_AssertVoid(IdValue != NULL); + + /* + * Read from the AFMR and AFIR of the specified filter. + */ + switch (FilterIndex) { + case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR1_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR1_OFFSET); + break; + + case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR2_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR2_OFFSET); + break; + + case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR3_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR3_OFFSET); + break; + + case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR4_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR4_OFFSET); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + } +} + +/*****************************************************************************/ +/** +* +* This routine sets Baud Rate Prescaler value. The system clock for the CAN +* controller is divided by (Prescaler + 1) to generate the quantum clock +* needed for sampling and synchronization. Read the device specification +* for details. +* +* Baud Rate Prescaler can be set only if the CAN device is in Configuration +* Mode. Call XCanPs_EnterMode() to enter Configuration Mode before using this +* function. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Prescaler is the value to set. Valid values are from 0 to 255. +* +* @return +* - XST_SUCCESS if the Baud Rate Prescaler value is set +* successfully. +* - XST_FAILURE if CAN device is not in Configuration Mode. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET, + (u32)Prescaler); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine gets Baud Rate Prescaler value. The system clock for the CAN +* controller is divided by (Prescaler + 1) to generate the quantum clock +* needed for sampling and synchronization. Read the device specification for +* details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return Current used Baud Rate Prescaler value. The value's range is +* from 0 to 255. +* +* @note None. +* +******************************************************************************/ +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr) +{ + u32 ReadValue; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + ReadValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BRPR_OFFSET); + return ((u8)ReadValue); +} + +/*****************************************************************************/ +/** +* +* This routine sets Bit time. Time segment 1, Time segment 2 and +* Synchronization Jump Width are set in this function. Device specification +* requires the values passed into this function be one less than the actual +* values of these fields. Read the device specification for details. +* +* Bit time can be set only if the CAN device is in Configuration Mode. +* Call XCanPs_EnterMode() to enter Configuration Mode before using this +* function. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param SyncJumpWidth is the Synchronization Jump Width value to set. +* Valid values are from 0 to 3. +* @param TimeSegment2 is the Time Segment 2 value to set. Valid values +* are from 0 to 7. +* @param TimeSegment1 is the Time Segment 1 value to set. Valid values +* are from 0 to 15. +* +* @return +* - XST_SUCCESS if the Bit time is set successfully. +* - XST_FAILURE if CAN device is not in Configuration Mode. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1) +{ + u32 Value; + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(SyncJumpWidth <= (u8)3U); + Xil_AssertNonvoid(TimeSegment2 <= (u8)7U); + Xil_AssertNonvoid(TimeSegment1 <= (u8)15U ); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK; + Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) & + XCANPS_BTR_TS2_MASK; + Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) & + XCANPS_BTR_SJW_MASK; + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BTR_OFFSET, Value); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine gets Bit time. Time segment 1, Time segment 2 and +* Synchronization Jump Width values are read in this function. According to +* device specification, the actual value of each of these fields is one +* more than the value read. Read the device specification for details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param SyncJumpWidth will store the Synchronization Jump Width value +* after this function returns. Its value ranges from 0 to 3. +* @param TimeSegment2 will store the Time Segment 2 value after this +* function returns. Its value ranges from 0 to 7. +* @param TimeSegment1 will store the Time Segment 1 value after this +* function returns. Its value ranges from 0 to 15. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1) +{ + u32 Value; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(SyncJumpWidth != NULL); + Xil_AssertVoid(TimeSegment2 != NULL); + Xil_AssertVoid(TimeSegment1 != NULL); + + Value = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BTR_OFFSET); + + *TimeSegment1 = (u8) (Value & XCANPS_BTR_TS1_MASK); + *TimeSegment2 = + (u8) ((Value & XCANPS_BTR_TS2_MASK) >> XCANPS_BTR_TS2_SHIFT); + *SyncJumpWidth = + (u8) ((Value & XCANPS_BTR_SJW_MASK) >> XCANPS_BTR_SJW_SHIFT); +} + + +/****************************************************************************/ +/** +* +* This routine sets the Rx Full threshold in the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Threshold is the threshold to be set. The valid values are +* from 1 to 63. +* +* @return +* - XST_FAILURE - If the CAN device is not in Configuration Mode. +* - XST_SUCCESS - If the Rx Full threshold is set in Watermark +* Interrupt Register. +* +* @note The threshold can only be set when the CAN device is in the +* configuration mode. +* +*****************************************************************************/ +s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold) +{ + + u32 ThrReg; + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Threshold <= (u8)63); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET); + + ThrReg &= XCANPS_WIR_EW_MASK; + ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET, ThrReg); + + Status = XST_SUCCESS; + } + return Status; +} + +/****************************************************************************/ +/** +* +* This routine gets the Rx Full threshold from the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The Rx FIFO full watermark threshold value. The valid values +* are 1 to 63. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + return (u8) (XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET) & + XCANPS_WIR_FW_MASK); +} + + +/****************************************************************************/ +/** +* +* This routine sets the Tx Empty Threshold in the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Threshold is the threshold to be set. The valid values are +* from 1 to 63. +* +* @return +* - XST_FAILURE - If the CAN device is not in Configuration Mode. +* - XST_SUCCESS - If the threshold is set in Watermark +* Interrupt Register. +* +* @note The threshold can only be set when the CAN device is in the +* configuration mode. +* +*****************************************************************************/ +s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold) +{ + u32 ThrReg; + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Threshold <= (u8)63); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET); + + ThrReg &= XCANPS_WIR_FW_MASK; + ThrReg |= (((u32)Threshold << XCANPS_WIR_EW_SHIFT) + & XCANPS_WIR_EW_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET, ThrReg); + + Status = XST_SUCCESS; + } + return Status; +} + +/****************************************************************************/ +/** +* +* This routine gets the Tx Empty threshold from Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The Tx Empty FIFO threshold value. The valid values are 1 to 63. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + return (u8) ((XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET) & XCANPS_WIR_EW_MASK) >> + XCANPS_WIR_EW_SHIFT); +} + + + +/******************************************************************************/ +/* + * This routine is a stub for the asynchronous callbacks. The stub is here in + * case the upper layer forgot to set the handler(s). On initialization, all + * handlers are set to this callback. It is considered an error for this handler + * to be invoked. + * + ******************************************************************************/ +static void StubHandler(void) +{ + Xil_AssertVoidAlways(); +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h new file mode 100644 index 0000000..9feb45e --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h @@ -0,0 +1,577 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.h +* @addtogroup canps_v3_2 +* @{ +* @details +* +* The Xilinx CAN driver component. This component supports the Xilinx +* CAN Controller. +* +* The CAN Controller supports the following features: +* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards. +* - Supports both Standard (11 bit Identifier) and Extended (29 bit +* Identifier) frames. +* - Supports Bit Rates up to 1 Mbps. +* - Transmit message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Transmit prioritization through one TX High Priority Buffer. +* - Receive message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Watermark interrupts for Rx FIFO with configurable Watermark. +* - Acceptance filtering with 4 acceptance filters. +* - Sleep mode with automatic wake up. +* - Loop Back mode for diagnostic applications. +* - Snoop mode for diagnostic applications. +* - Maskable Error and Status Interrupts. +* - Readable Error Counters. +* - External PHY chip required. +* - Receive Timestamp. +* +* The device driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CAN. The driver handles transmission and reception of +* CAN frames, as well as configuration of the controller. The driver is simply a +* pass-through mechanism between a protocol stack and the CAN. A single device +* driver can support multiple CANs. +* +* Since the driver is a simple pass-through mechanism between a protocol stack +* and the CAN, no assembly or disassembly of CAN frames is done at the +* driver-level. This assumes that the protocol stack passes a correctly +* formatted CAN frame to the driver for transmission, and that the driver +* does not validate the contents of an incoming frame +* +* Operation Modes +* +* The CAN controller supports the following modes of operation: +* - Configuration Mode: In this mode the CAN timing parameters and +* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN +* controller loses synchronization with the CAN bus and drives a +* constant recessive bit on the bus line. The Error Counter Register are +* reset. The CAN controller does not receive or transmit any messages +* even if there are pending transmit requests from the TX FIFO or the TX +* High Priority Buffer. The Storage FIFOs and the CAN configuration +* registers are still accessible. +* - Normal Mode:In Normal Mode the CAN controller participates in bus +* communication, by transmitting and receiving messages. +* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any +* messages. However, if any other node transmits a message, then the CAN +* Controller receives the transmitted message and exits from Sleep Mode. +* If there are new transmission requests from either the TX FIFO or the +* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these +* requests are not serviced, and the CAN Controller continues to remain +* in Sleep Mode. Interrupts are generated when the CAN controller enters +* Sleep mode or Wakes up from Sleep mode. +* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus. Any message that is transmitted +* is looped back to the �Rx� line and acknowledged. The CAN controller +* thus receives any message that it transmits. It does not participate in +* normal bus communication and does not receive any messages that are +* transmitted by other CAN nodes. This mode is used for diagnostic +* purposes. +* - Snoop Mode: In Snoop mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus and does not participate +* in normal bus communication but receives messages that are transmitted +* by other CAN nodes. This mode is used for diagnostic purposes. +* +* +* Buffer Alignment +* +* It is important to note that frame buffers passed to the driver must be +* 32-bit aligned. +* +* Receive Address Filtering +* +* The device can be set to accept frames whose Identifiers match any of the +* 4 filters set in the Acceptance Filter Mask/ID registers. +* +* The incoming Identifier is masked with the bits in the Acceptance Filter Mask +* Register. This value is compared with the result of masking the bits in the +* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If +* both these values are equal, the message will be stored in the RX FIFO. +* +* Acceptance Filtering is performed by each of the defined acceptance filters. +* If the incoming identifier passes through any acceptance filter then the +* frame is stored in the RX FIFO. +* +* If the Accpetance Filters are not set up then all the received messages are +* stroed in the RX FIFO. +* +* PHY Communication +* +* This driver does not provide any mechanism for directly programming PHY. +* +* Interrupts +* +* The driver has no dependencies on the interrupt controller. The driver +* provides an interrupt handler. User of this driver needs to provide +* callback functions. An interrupt handler example is available with +* the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Device Reset +* +* Bus Off interrupt that can occur in the device requires a device reset. +* The user is responsible for resetting the device and re-configuring it +* based on its needs (the driver does not save the current configuration). +* When integrating into an RTOS, these reset and re-configure obligations are +* taken care of by the OS adapter software if it exists for that RTOS. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xcanps_g.c files. +* A table is defined where each entry contains configuration information +* for a CAN device. This information includes such things as the base address +* of the memory-mapped device. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCanPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

    +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*			Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*			SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk     09/12/14  Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.1 adk     10/11/15  Fixed CR#911958 Add support for Tx Watermark example.
+*			Data mismatch while sending data less than 8 bytes.
+* 3.1 nsk     12/21/15  Updated XCanPs_IntrHandler in xcanps_intr.c to handle
+*			error interrupts correctly. CR#925615
+*     ms      03/17/17  Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
    +* +******************************************************************************/ +#ifndef XCANPS_H /* prevent circular inclusions */ +#define XCANPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xcanps_hw.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +/** @name CAN operation modes + * @{ + */ +#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */ +#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */ +#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */ +#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */ +#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */ +/* @} */ + +/** @name Callback identifiers used as parameters to XCanPs_SetHandler() + * @{ + */ +#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */ +#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/ +#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */ +#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XCanPs_Config; + +/******************************************************************************/ +/** + * Callback type for frame sending and reception interrupts. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. +*******************************************************************************/ +typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef); + +/******************************************************************************/ +/** + * Callback type for error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param ErrorMask is a bit mask indicating the cause of the error. Its + * value equals 'OR'ing one or more XCANPS_ESR_* values defined in + * xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask); + +/******************************************************************************/ +/** + * Callback type for all kinds of interrupts except sending frame interrupt, + * receiving frame interrupt, and error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param Mask is a bit mask indicating the pending interrupts. Its value + * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask); + +/** + * The XCanPs driver instance data. The user is required to allocate a + * variable of this type for every CAN device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XCanPs_Config CanConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + + /** + * Callback and callback reference for TXOK interrupt. + */ + XCanPs_SendRecvHandler SendHandler; + void *SendRef; + + /** + * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts. + */ + XCanPs_SendRecvHandler RecvHandler; + void *RecvRef; + + /** + * Callback and callback reference for ERROR interrupt. + */ + XCanPs_ErrorHandler ErrorHandler; + void *ErrorRef; + + /** + * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/ + * Wakeup/Sleep/Bus off/ARBLST interrupts. + */ + XCanPs_EventHandler EventHandler; + void *EventRef; + +} XCanPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the transmission is complete. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the transmission is done. +* - FALSE if the transmission is not done. +* +* @note C-Style signature: +* int XCanPs_IsTxDone(XCanPs *InstancePtr) +* +*******************************************************************************/ +#define XCanPs_IsTxDone(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the transmission FIFO is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if TX FIFO is full. +* - FALSE if the TX FIFO is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsTxFifoFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the Transmission High Priority Buffer is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the TX High Priority Buffer is full. +* - FALSE if the TX High Priority Buffer is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsHighPriorityBufFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the receive FIFO is empty. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if RX FIFO is empty. +* - FALSE if the RX FIFO is NOT empty. +* +* @note C-Style signature: +* int XCanPs_IsRxEmpty(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsRxEmpty(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE) + + +/****************************************************************************/ +/** +* +* This macro checks if the CAN device is ready for the driver to change +* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask +* Registers (AFMR). +* +* AFIR and AFMR for a filter are changeable only after the filter is disabled +* and this routine returns FALSE. The filter can be disabled using the +* XCanPs_AcceptFilterDisable function. +* +* Use the XCanPs_Accept_* functions for configuring the acceptance filters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the device is busy and NOT ready to accept writes to +* AFIR and AFMR. +* - FALSE if the device is ready to accept writes to AFIR and +* AFMR. +* +* @note C-Style signature: +* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsAcceptFilterBusy(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro calculates CAN message identifier value given identifier field +* values. +* +* @param StandardId contains Standard Message ID value. +* @param SubRemoteTransReq contains Substitute Remote Transmission +* Request value. +* @param IdExtension contains Identifier Extension value. +* @param ExtendedId contains Extended Message ID value. +* @param RemoteTransReq contains Remote Transmission Request value. +* +* @return Message Identifier value. +* +* @note C-Style signature: +* u32 XCanPs_CreateIdValue(u32 StandardId, +* u32 SubRemoteTransReq, +* u32 IdExtension, u32 ExtendedId, +* u32 RemoteTransReq) +* +* Read the CAN specification for meaning of each parameter. +* +*****************************************************************************/ +#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \ + ExtendedId, RemoteTransReq) \ + ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \ + (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\ + (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \ + (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \ + ((RemoteTransReq) & XCANPS_IDR_RTR_MASK)) + + +/****************************************************************************/ +/** +* +* This macro calculates value for Data Length Code register given Data +* Length Code value. +* +* @param DataLengCode indicates Data Length Code value. +* +* @return Value that can be assigned to Data Length Code register. +* +* @note C-Style signature: +* u32 XCanPs_CreateDlcValue(u32 DataLengCode) +* +* Read the CAN specification for meaning of Data Length Code. +* +*****************************************************************************/ +#define XCanPs_CreateDlcValue(DataLengCode) \ + (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK) + + +/****************************************************************************/ +/** +* +* This macro clears the timestamp in the Timestamp Control Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XCanPs_ClearTimestamp(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_ClearTimestamp(InstancePtr) \ + XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \ + XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xcanps.c + */ +s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr); + +void XCanPs_Reset(XCanPs *InstancePtr); +u8 XCanPs_GetMode(XCanPs *InstancePtr); +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode); +u32 XCanPs_GetStatus(XCanPs *InstancePtr); +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount); +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr); +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask); +s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr); +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes); +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes); +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr); +s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue); +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue); + +s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler); +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr); +s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1); +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1); + +s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr); +s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr); + +/* + * Diagnostic functions in xcanps_selftest.c + */ +s32 XCanPs_SelfTest(XCanPs *InstancePtr); + +/* + * Functions in xcanps_intr.c + */ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask); +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr); +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr); +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrHandler(void *InstancePtr); +s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef); + +/* + * Functions in xcanps_sinit.c + */ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c new file mode 100644 index 0000000..bd2b197 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c @@ -0,0 +1,55 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xcanps.h" + +/* +* The configuration table for devices +*/ + +XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_CAN_0_DEVICE_ID, + XPAR_PS7_CAN_0_BASEADDR + } +}; + + diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c new file mode 100644 index 0000000..7ca2f81 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c @@ -0,0 +1,93 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.c +* @addtogroup canps_v3_2 +* @{ +* +* This file contains the implementation of the canps interface reset sequence +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.02a adk  08/08/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps_hw.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* This function resets the CAN device. Calling this function resets the device +* immediately, and any pending transmission or reception is terminated at once. +* Both Object Layer and Transfer Layer are reset. This function does not reset +* the Physical Layer. All registers are reset to the default values, and no +* previous status will be restored. TX FIFO, RX FIFO and TX High Priority +* Buffer are also reset. +* +* The CAN device will be in Configuration Mode immediately after this function +* returns. +* +* @param BaseAddr is the baseaddress of the interface. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_ResetHw(u32 BaseAddr) +{ + XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \ + XCANPS_SRR_SRST_MASK); +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h new file mode 100644 index 0000000..30ec68a --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h @@ -0,0 +1,369 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.h +* @addtogroup canps_v3_2 +* @{ +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xcanps.h. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a sbs    12/27/11 Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk   08/08/13  Updated for inclding the function prototype
+* 3.00  kvn   02/13/15  Modified code for MISRA-C:2012 compliance.
+*
    +* +******************************************************************************/ + +#ifndef XCANPS_HW_H /* prevent circular inclusions */ +#define XCANPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the CAN. Each register is 32 bits. + * @{ + */ +#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */ +#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */ +#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */ +#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */ +#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */ +#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */ +#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */ + +#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */ +#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */ +#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */ +#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */ +#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */ + +#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */ +#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */ +#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */ +#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */ + +#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */ +#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */ +#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */ +#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */ + +#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */ +#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */ +#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */ +#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */ + +#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */ +#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */ +#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */ +#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */ +#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */ +#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */ +#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */ +#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */ +#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */ +/* @} */ + +/** @name Software Reset Register (SRR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */ +#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */ +/* @} */ + +/** @name Mode Select Register (MSR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */ +#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */ +#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */ +/* @} */ + +/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */ +/* @} */ + +/** @name Bit Timing Register (BTR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */ +#define XCANPS_BTR_SJW_SHIFT 7U +#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */ +#define XCANPS_BTR_TS2_SHIFT 4U +#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */ +/* @} */ + +/** @name Error Counter Register (ECR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */ +#define XCANPS_ECR_REC_SHIFT 8U +#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */ +/* @} */ + +/** @name Error Status Register (ESR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */ +#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */ +#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */ +#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */ +#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */ +/* @} */ + +/** @name Status Register (SR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */ +#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */ +#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */ +#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */ +#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */ +#define XCANPS_SR_ESTAT_SHIFT 7U +#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */ +#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */ +#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */ +#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */ +#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */ +#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */ +#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */ +/* @} */ + +/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks + * @{ + */ +#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */ +#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */ +#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */ +#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */ +#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */ +#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */ +#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */ +#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */ +#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */ +#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */ +#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */ +#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */ +#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */ +#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */ +#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */ +#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \ + (u32)XCANPS_IXR_WKUP_MASK | \ + (u32)XCANPS_IXR_SLP_MASK | \ + (u32)XCANPS_IXR_BSOFF_MASK | \ + (u32)XCANPS_IXR_ERROR_MASK | \ + (u32)XCANPS_IXR_RXNEMP_MASK | \ + (u32)XCANPS_IXR_RXOFLW_MASK | \ + (u32)XCANPS_IXR_RXUFLW_MASK | \ + (u32)XCANPS_IXR_RXOK_MASK | \ + (u32)XCANPS_IXR_TXBFLL_MASK | \ + (u32)XCANPS_IXR_TXFLL_MASK | \ + (u32)XCANPS_IXR_TXOK_MASK | \ + (u32)XCANPS_IXR_ARBLST_MASK) +/* @} */ + +/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */ +/* @} */ + +/** @name CAN Watermark Register (WIR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */ +#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */ +#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */ + +/* @} */ + +/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter + Mask/Acceptance Filter ID) + * @{ + */ +#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */ +#define XCANPS_IDR_ID1_SHIFT 21U +#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */ +#define XCANPS_IDR_SRR_SHIFT 20U +#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */ +#define XCANPS_IDR_IDE_SHIFT 19U +#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */ +#define XCANPS_IDR_ID2_SHIFT 1U +#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */ +/* @} */ + +/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */ +#define XCANPS_DLCR_DLC_SHIFT 28U +#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */ + +/* @} */ + +/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */ +#define XCANPS_DW1R_DB0_SHIFT 24U +#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */ +#define XCANPS_DW1R_DB1_SHIFT 16U +#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */ +#define XCANPS_DW1R_DB2_SHIFT 8U +#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */ +/* @} */ + +/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */ +#define XCANPS_DW2R_DB4_SHIFT 24U +#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */ +#define XCANPS_DW2R_DB5_SHIFT 16U +#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */ +#define XCANPS_DW2R_DB6_SHIFT 8U +#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */ +/* @} */ + +/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */ +#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */ +#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */ +#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */ +#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \ + (u32)XCANPS_AFR_UAF3_MASK | \ + (u32)XCANPS_AFR_UAF2_MASK | \ + (u32)XCANPS_AFR_UAF1_MASK) +/* @} */ + +/** @name CAN frame length constants + * @{ + */ +#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */ +/* @} */ + +/* For backwards compatibilty */ +#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET +#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET +#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET +#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET + +#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK +#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET +#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK + + + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the CanPs interface + */ +void XCanPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c new file mode 100644 index 0000000..715b35e --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c @@ -0,0 +1,421 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_intr.c +* @addtogroup canps_v3_2 +* @{ +* +* This file contains functions related to CAN interrupt handling. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1   nsk    12/21/15 Updated XCanPs_IntrHandler to handle error
+*			interrupts correctly. CR#925615
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/****************************************************************************/ +/** +* +* This routine enables interrupt(s). Use the XCANPS_IXR_* constants defined in +* xcanps_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to enable. Bit positions of 1 will be enabled. +* Bit positions of 0 will keep the previous setting. This mask is +* formed by OR'ing XCANPS_IXR_* bits defined in xcanps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write to the IER to enable the specified interrupts. + */ + IntrValue = XCanPs_IntrGetEnabled(InstancePtr); + IntrValue |= Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET, IntrValue); +} + +/****************************************************************************/ +/** +* +* This routine disables interrupt(s). Use the XCANPS_IXR_* constants defined in +* xcanps_hw.h to create the bit-mask to disable interrupt(s). +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to disable. Bit positions of 1 will be +* disabled. Bit positions of 0 will keep the previous setting. +* This mask is formed by OR'ing XCANPS_IXR_* bits defined in +* xcanps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write to the IER to disable the specified interrupts. + */ + IntrValue = XCanPs_IntrGetEnabled(InstancePtr); + IntrValue &= ~Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET, IntrValue); +} + +/****************************************************************************/ +/** +* +* This routine returns enabled interrupt(s). Use the XCANPS_IXR_* constants +* defined in xcanps_hw.h to interpret the returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return Enabled interrupt(s) in a 32-bit format. +* +* @note None. +* +*****************************************************************************/ +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET); +} + + +/****************************************************************************/ +/** +* +* This routine returns interrupt status read from Interrupt Status Register. +* Use the XCANPS_IXR_* constants defined in xcanps_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The value stored in Interrupt Status Register. +* +* @note None. +* +*****************************************************************************/ +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ISR_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function clears interrupt(s). Every bit set in Interrupt Status +* Register indicates that a specific type of interrupt is occurring, and this +* function clears one or more interrupts by writing a bit mask to Interrupt +* Clear Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* Bit positions of 0 will not change the previous interrupt +* status. This mask is formed by OR'ing XCANPS_IXR_* bits defined +* in xcanps_hw.h. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Clear the currently pending interrupts. + */ + IntrValue = XCanPs_IntrGetStatus(InstancePtr); + IntrValue &= Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_ICR_OFFSET, + IntrValue); +} + +/*****************************************************************************/ +/** +* +* This routine is the interrupt handler for the CAN driver. +* +* This handler reads the interrupt status from the ISR, determines the source of +* the interrupts, calls according callbacks, and finally clears the interrupts. +* +* Application beyond this driver is responsible for providing callbacks to +* handle interrupts and installing the callbacks using XCanPs_SetHandler() +* during initialization phase. An example delivered with this driver +* demonstrates how this could be done. +* +* @param InstancePtr is a pointer to the XCanPs instance that just +* interrupted. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_IntrHandler(void *InstancePtr) +{ + u32 PendingIntr; + u32 EventIntr; + u32 ErrorStatus; + XCanPs *CanPtr = (XCanPs *) ((void *)InstancePtr); + + Xil_AssertVoid(CanPtr != NULL); + Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY); + + PendingIntr = XCanPs_IntrGetStatus(CanPtr); + PendingIntr &= XCanPs_IntrGetEnabled(CanPtr); + + /* + * Clear all pending interrupts. + * Rising Edge interrupt + */ + XCanPs_IntrClear(CanPtr, PendingIntr); + + /* + * An error interrupt is occurring. + */ + if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) && + (CanPtr->ErrorHandler != NULL)) { + ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr); + CanPtr->ErrorHandler(CanPtr->ErrorRef,ErrorStatus); + /* + * Clear Error Status Register. + */ + XCanPs_ClearBusErrorStatus(CanPtr,ErrorStatus); + } + + /* + * Check if any following event interrupt is pending: + * - RX FIFO Overflow + * - RX FIFO Underflow + * - TX High Priority Buffer full + * - TX FIFO Full + * - Wake up from sleep mode + * - Enter sleep mode + * - Enter Bus off status + * - Arbitration is lost + * + * If so, call event callback provided by upper level. + */ + EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK | + (u32)XCANPS_IXR_RXUFLW_MASK | + (u32)XCANPS_IXR_TXBFLL_MASK | + (u32)XCANPS_IXR_TXFLL_MASK | + (u32)XCANPS_IXR_WKUP_MASK | + (u32)XCANPS_IXR_SLP_MASK | + (u32)XCANPS_IXR_BSOFF_MASK | + (u32)XCANPS_IXR_ARBLST_MASK); + if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) { + CanPtr->EventHandler(CanPtr->EventRef, EventIntr); + + if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) { + /* + * Event callback should reset whole device if "Enter + * Bus Off Status" interrupt occurred. All pending + * interrupts are cleared and no further checking and + * handling of other interrupts is needed any more. + */ + return; + } else { + /*This else was made for misra-c compliance*/ + ; + } + } + + + if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK | + XCANPS_IXR_RXNEMP_MASK)) != (u32)0) && + (CanPtr->RecvHandler != NULL)) { + + /* + * This case happens when + * A number of frames depending on the Rx FIFO Watermark + * threshold are received. + * And also when frame was received and is sitting in RX FIFO. + * + * XCANPS_IXR_RXOK_MASK is not used because the bit is set + * just once even if there are multiple frames sitting + * in the RX FIFO. + * + * XCANPS_IXR_RXNEMP_MASK is used because the bit can be + * set again and again automatically as long as there is + * at least one frame in RX FIFO. + */ + CanPtr->RecvHandler(CanPtr->RecvRef); + } + + /* + * A frame was transmitted successfully. + */ + if (((PendingIntr & (XCANPS_IXR_TXOK_MASK | XCANPS_IXR_TXFWMEMP_MASK)) != (u32)0) && + (CanPtr->SendHandler != NULL)) { + CanPtr->SendHandler(CanPtr->SendRef); + } +} + + +/*****************************************************************************/ +/** +* +* This routine installs an asynchronous callback function for the given +* HandlerType: +* +* 
    +* HandlerType			Callback Function Type
+* -----------------------	------------------------
+* XCANPS_HANDLER_SEND		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_RECV		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_ERROR		XCanPs_ErrorHandler
+* XCANPS_HANDLER_EVENT		XCanPs_EventHandler
+*
+* HandlerType			Invoked by this driver when:
+* -------------------------------------------------------------------------
+* XCANPS_HANDLER_SEND		A frame transmitted by a call to
+*				XCanPs_Send() has been sent successfully.
+*
+* XCANPS_HANDLER_RECV		A frame(s) has been received and is sitting in
+*				the RX FIFO.
+*
+* XCANPS_HANDLER_ERROR		An error interrupt is occurring.
+*
+* XCANPS_HANDLER_EVENT		Any other kind of interrupt is occurring.
+*
    +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param HandlerType specifies which handler is to be attached. +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return +* - XST_SUCCESS when handler is installed. +* - XST_INVALID_PARAM when HandlerType is invalid. +* +* @note +* Invoking this function for a handler that already has been installed replaces +* it with the new handler. +* +******************************************************************************/ +s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + switch (HandlerType) { + case XCANPS_HANDLER_SEND: + InstancePtr->SendHandler = + (XCanPs_SendRecvHandler) CallBackFunc; + InstancePtr->SendRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_RECV: + InstancePtr->RecvHandler = + (XCanPs_SendRecvHandler) CallBackFunc; + InstancePtr->RecvRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_ERROR: + InstancePtr->ErrorHandler = + (XCanPs_ErrorHandler) CallBackFunc; + InstancePtr->ErrorRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_EVENT: + InstancePtr->EventHandler = + (XCanPs_EventHandler) CallBackFunc; + InstancePtr->EventRef = CallBackRef; + Status = XST_SUCCESS; + break; + + default: + Status = XST_INVALID_PARAM; + break; + } + return Status; +} + +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c new file mode 100644 index 0000000..26c9fcb --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c @@ -0,0 +1,234 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_selftest.c +* @addtogroup canps_v3_2 +* @{ +* +* This file contains a diagnostic self-test function for the XCanPs driver. +* +* Read xcanps.h file for more information. +* +* @note +* The Baud Rate Prescaler Register (BRPR) and Bit Timing Register(BTR) +* are setup such that CAN baud rate equals 40Kbps, given the CAN clock +* equal to 24MHz. These need to be changed based on the desired baudrate +* and CAN clock frequency. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*						 SDK claims a 40kbps baud rate but it's not.
+* 3.00  kvn    02/13/15 Modified code for MISRA_C:2012 compliance.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xstatus.h" +#include "xcanps.h" + +/************************** Constant Definitions ****************************/ + +#define XCANPS_MAX_FRAME_SIZE_IN_WORDS ((XCANPS_MAX_FRAME_SIZE) / (sizeof(u32))) + +#define FRAME_DATA_LENGTH 8U /* Frame Data field length */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/* + * Buffers to hold frames to send and receive. These are declared as global so + * that they are not on the stack. + */ +static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; +static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the CAN driver/device. The test resets +* the device, sets up the Loop Back mode, sends a standard frame, receives the +* frame, verifies the contents, and resets the device again. +* +* Note that this is a destructive test in that resets of the device are +* performed. Refer the device specification for the device status after +* the reset operation. +* +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - XST_SUCCESS if the self-test passed. i.e., the frame +* received via the internal loop back has the same contents as +* the frame sent. +* - XST_FAILURE Otherwise. +* +* @note +* +* If the CAN device does not work properly, this function may enter an +* infinite loop and will never return to the caller. +*

    +* If XST_FAILURE is returned, the device is not reset so that the caller could +* have a chance to check reason(s) causing the failure. +* +******************************************************************************/ +s32 XCanPs_SelfTest(XCanPs *InstancePtr) +{ + u8 *FramePtr; + s32 Status; + u32 Index; + u8 GetModeResult; + u32 RxEmptyResult; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_Reset(InstancePtr); + + /* + * The device should enter Configuration Mode immediately after + * reset above is finished. Now check the mode and return error code if + * it is not Configuration Mode. + */ + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + return Status; + } + + /* + * Setup Baud Rate Prescaler Register (BRPR) and Bit Timing Register + * (BTR) such that CAN baud rate equals 40Kbps, given the CAN clock + * equal to 24MHz. For more information see the CAN 2.0A, CAN 2.0B, + * ISO 11898-1 specifications. + */ + (void)XCanPs_SetBaudRatePrescaler(InstancePtr, (u8)29U); + (void)XCanPs_SetBitTiming(InstancePtr, (u8)3U, (u8)2U, (u8)15U); + + /* + * Enter the loop back mode. + */ + XCanPs_EnterMode(InstancePtr, XCANPS_MODE_LOOPBACK); + GetModeResult = XCanPs_GetMode(InstancePtr); + while (GetModeResult != ((u8)XCANPS_MODE_LOOPBACK)) { + GetModeResult = XCanPs_GetMode(InstancePtr); + } + + /* + * Create a frame to send with known values so we can verify them + * on receive. + */ + TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U); + TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8U); + + FramePtr = (u8 *)((void *)(&TxFrame[2])); + for (Index = 0U; Index < 8U; Index++) { + if(*FramePtr != 0U) { + *FramePtr = (u8)Index; + FramePtr++; + } + } + + /* + * Send the frame. + */ + Status = XCanPs_Send(InstancePtr, TxFrame); + if (Status != (s32)XST_SUCCESS) { + Status = XST_FAILURE; + return Status; + } + + /* + * Wait until the frame arrives RX FIFO via internal loop back. + */ + RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK; + + while (RxEmptyResult == (u32)0U) { + RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK; + } + + /* + * Receive the frame. + */ + Status = XCanPs_Recv(InstancePtr, RxFrame); + if (Status != (s32)XST_SUCCESS) { + Status = XST_FAILURE; + return Status; + } + + /* + * Verify Identifier and Data Length Code. + */ + if (RxFrame[0] != + (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U)) { + Status = XST_FAILURE; + return Status; + } + + if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) { + Status = XST_FAILURE; + return Status; + } + + + for (Index = 2U; Index < (XCANPS_MAX_FRAME_SIZE_IN_WORDS); Index++) { + if (RxFrame[Index] != TxFrame[Index]) { + Status = XST_FAILURE; + return Status; + } + } + + /* + * Reset device again before returning to the caller. + */ + XCanPs_Reset(InstancePtr); + + Status = XST_SUCCESS; + return Status; +} + + +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c new file mode 100644 index 0000000..5321669 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_sinit.c +* @addtogroup canps_v3_2 +* @{ +* +* This file contains the implementation of the XCanPs driver's static +* initialization functionality. +* +* @note None. +* +* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +extern XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES]; + +/*****************************************************************************/ +/** +* +* This function looks for the device configuration based on the unique device +* ID. The table XCanPs_ConfigTable[] contains the configuration information for +* each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId) +{ + XCanPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < (u32)XPAR_XCANPS_NUM_INSTANCES; Index++) { + if (XCanPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XCanPs_ConfigTable[Index]; + break; + } + } + + return (XCanPs_Config *)CfgPtr; +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c new file mode 100644 index 0000000..fca26ca --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c @@ -0,0 +1,188 @@ +/****************************************************************************** +* +* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcoresightpsdcc.c +* @addtogroup coresightps_dcc_v1_4 +* @{ +* +* Functions in this file are the minimum required functions for the +* XCoreSightPs driver. +* +* @note None. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.2   kvn    10/09/15 Add support for IAR Compiler.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifdef __MICROBLAZE__ +#warning "The driver is supported only for ARM architecture" +#else + +#include +#include + +#ifdef __ICCARM__ +#define INLINE +#else +#define INLINE __inline +#endif + +/* DCC Status Bits */ +#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30) +#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29) + +static INLINE u32 XCoresightPs_DccGetStatus(void); + +/****************************************************************************/ +/** +* +* This functions sends a single byte using the DCC. It is blocking in that it +* waits for the transmitter to become non-full before it writes the byte to +* the transmit register. +* +* @param BaseAddress is a dummy parameter to match the function proto +* of functions for other stdio devices. +* @param Data is the byte of data to send +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data) +{ + (void) BaseAddress; + while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX) + dsb(); +#ifdef __aarch64__ + asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mcr p14, 0, %0, c0, c5, 0" + : : "r" (Data)); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c5:0"); + Reg = Data; + } +#endif + isb(); + +} + +/****************************************************************************/ +/** +* +* This functions receives a single byte using the DCC. It is blocking in that +* it waits for the receiver to become non-empty before it reads from the +* receive register. +* +* @param BaseAddress is a dummy parameter to match the function proto +* of functions for other stdio devices. +* +* @return The byte of data received. +* +* @note None. +* +******************************************************************************/ +u8 XCoresightPs_DccRecvByte(u32 BaseAddress) +{ + u8 Data = 0U; + (void) BaseAddress; + + while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX)) + dsb(); + +#ifdef __aarch64__ + asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mrc p14, 0, %0, c0, c5, 0" + : "=r" (Data)); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c5:0"); + Data = Reg; + } +#endif + isb(); + + return Data; +} + + +/****************************************************************************/ +/**INLINE +* +* This functions read the status register of the DCC. +* +* @param BaseAddress is the base address of the device +* +* @return The contents of the Status Register. +* +* @note None. +* +******************************************************************************/ +static INLINE u32 XCoresightPs_DccGetStatus(void) +{ + u32 Status = 0U; + +#ifdef __aarch64__ + asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mrc p14, 0, %0, c0, c1, 0" + : "=r" (Status) : : "cc"); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c1:0"); + Status = Reg; + } +#endif + return Status; +#endif +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h new file mode 100644 index 0000000..67959e3 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h @@ -0,0 +1,74 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcoresightpsdcc.h +* @addtogroup coresightps_dcc_v1_4 +* @{ +* @details +* +* CoreSight driver component. +* +* The coresight is a part of debug communication channel (DCC) group. Jtag UART +* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an +* ARM target in XSDB console before running the jtag terminal command. Using the +* coresight driver component, the output stream can be directed to a log file. +* +* @note None. +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.3   asa    07/01/16 Made changes to ensure that the file does not compile
+*                       for MB BSPs. Instead it throws up a warning. This
+*                       fixes the CR#953056.
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifndef __MICROBLAZE__ +#include + +void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data); + +u8 XCoresightPs_DccRecvByte(u32 BaseAddress); +#endif +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h new file mode 100644 index 0000000..95c8ba5 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h @@ -0,0 +1,48 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexa9.h +* @addtogroup cpu_cortexa9_v2_5 +* @{ +* @details +* +* dummy file +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h +******************************************************************************/ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h new file mode 100644 index 0000000..c8804d2 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h @@ -0,0 +1,66 @@ +/******************************************************************************* + * + * Copyright (C) 2015 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xddrps.h + * @addtogroup ddrps_v1_0 + * @{ + * @details + * + * The Xilinx DdrPs driver. This driver supports the Xilinx ddrps + * IP core. + * + * @note None. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 nsk  08/06/15 First Release
+ * 1.0	 nsk  08/20/15 Updated define_addr_params in ddrps.tcl
+ *		       to support PBD Designs (CR #876857)
+ *
+ *
    + * +*******************************************************************************/ + +#ifndef XDDRPS_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XDDRPS_H_ + +/******************************* Include Files ********************************/ + + +#endif /* XDDRPS_H_ */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c new file mode 100644 index 0000000..e9447e7 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c @@ -0,0 +1,945 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.c +* @addtogroup devcfg_v3_5 +* @{ +* +* This file contains the implementation of the interface functions for XDcfg +* driver. Refer to the header file xdevcfg.h for more detailed information. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Updated the XDcfg_Transfer function to use the
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  08/27/12 Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   kpc 21/02/14 Implemented new function XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* Initialize the Device Config Interface driver. This function +* must be called before other functions of the driver are called. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param ConfigPtr is the config structure. +* @param EffectiveAddress is the base address for the device. It could be +* a virtual address if address translation is supported in the +* system, otherwise it is the physical address. +* +* @return +* - XST_SUCCESS if initialization was successful. +* - XST_DEVICE_IS_STARTED if the device has already been started. +* +* @note The very first APB access to the Device Configuration Interface +* block needs to be a write to the UNLOCK register with the value +* of 0x757BDF0D. This step is to be done once after reset, any +* other APB access has to come after this. The APB access is +* considered illegal if the step is not done or if it is done +* incorrectly. Furthermore, if any of efuse_sec_cfg[5:0] is high, +* the following additional actions would be carried out. +* In other words, if all bits are low, the following steps are not +* done. +* 1. AES is disabled +* 2. All APB writes disabled +* 3. SoC debug fully enabled +* +******************************************************************************/ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * If the device is started, disallow the initialize and return a + * status indicating it is started. This allows the user to stop the + * device and reinitialize, but prevents a user from inadvertently + * initializing. + */ + if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) { + return XST_DEVICE_IS_STARTED; + } + + /* + * Copy configuration into instance. + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + + /* + * Save the base address pointer such that the registers of the block + * can be accessed and indicate it has not been started yet. + */ + InstancePtr->Config.BaseAddr = EffectiveAddress; + InstancePtr->IsStarted = 0; + + + /* Unlock the Device Configuration Interface */ + XDcfg_Unlock(InstancePtr); + + /* + * Indicate the instance is ready to use, successfully initialized. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* The functions enables the PCAP interface by setting the PCAP mode bit in the +* control register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note Enable FPGA programming from PCAP interface. Enabling this bit +* disables all the external interfaces from programming of FPGA +* except for ICAP. The user needs to ensure that the FPGA is +* programmed through either PCAP or ICAP. +* +*****************************************************************************/ +void XDcfg_EnablePCAP(XDcfg *InstancePtr) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg | XDCFG_CTRL_PCAP_MODE_MASK)); + +} + +/****************************************************************************/ +/** +* +* The functions disables the PCAP interface by clearing the PCAP mode bit in +* the control register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_DisablePCAP(XDcfg *InstancePtr) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg & ( ~XDCFG_CTRL_PCAP_MODE_MASK))); + +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the 32 bit mask data to be written to the Register. +* The mask definitions are defined in the xdevcfg_hw.h file. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg | Mask)); + +} + +/****************************************************************************/ +/** +* +* The function Clears the specified bit positions of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the 32 bit value which holds the bit positions to be cleared. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 CtrlReg; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (CtrlReg & ~Mask)); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Control +* Register. +* Use the XDCFG_CTRL_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Control Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CTRL_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Lock Register. These bits +* can only be set to a 1. They will be cleared after a Power On Reset. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Lock Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Lock +* Register. +* Use the XDCFG_CR_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Lock Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_LOCK_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Configuration Register with the +* given value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Configuration Register with the +* given value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Config +* Register. +* Use the XDCFG_CFG_*_MASK constants defined in xdevcfg_hw.h to +* interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_CFG_OFFSET); + +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET, Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Status +* Register. +* Use the XDCFG_STATUS_*_MASK constants defined in +* xdevcfg_hw.h to interpret the returned value. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Status Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the contents of the ROM Shadow Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Data is the 32 bit data to be written to the Register. +* +* @return None. +* +* @note This register is can only be written and is used to control the +* RAM shadow of 32 bit 4K page ROM pages in user mode +* +*****************************************************************************/ +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_ROM_SHADOW_OFFSET, + Data); + +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Software ID Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return 32 Bit boot software ID. +* +* @note This register is locked for write once the system enters +* usermode. Hence API for reading the register only is provided. +* +*****************************************************************************/ +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Software ID Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_SW_ID_OFFSET); +} + +/****************************************************************************/ +/** +* +* The function sets the bit mask for the feature in Miscellaneous Control +* Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the feature to be set. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegData; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET, + (RegData | Mask)); +} + +/****************************************************************************/ +/** +* +* The function reads the contents of the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return 32 Bit boot software ID. +* +* @note This register is locked for write once the system enters +* usermode. Hence API to reading the register only is provided. +* +*****************************************************************************/ +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Miscellaneous Control Register and return the value. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_MCTRL_OFFSET); +} + +/******************************************************************************/ +/** +* +* This function checks if DMA command queue is full. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return XST_SUCCESS is the DMA is busy +* XST_FAILURE if the DMA is idle +* +* @note The DMA queue has a depth of two. +* +****************************************************************************/ +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr) +{ + + u32 RegData; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* Read the PCAP status register for DMA status */ + RegData = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_STATUS_OFFSET); + + if ((RegData & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK){ + return XST_SUCCESS; + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** +* +* This function initiates the DMA transfer. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* +* @return None. +* +* @note It is the responsibility of the caller function to ensure that +* correct values are passed to this function. +* +* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) +* address when equal to 2�b01 indicates the last DMA command of +* an overall transfer. +* +****************************************************************************/ +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength) +{ + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_SRC_ADDR_OFFSET, + SourcePtr); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_DEST_ADDR_OFFSET, + DestPtr); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_SRC_LEN_OFFSET, + SrcWordLength); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_DMA_DEST_LEN_OFFSET, + DestWordLength); +} + +/******************************************************************************/ +/** +* +* This function Implements the DMA Read Command. This command is used to +* transfer the image data from FPGA to the external memory. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* +* @return - XST_INVALID_PARAM if source address/length is invalid. +* - XST_SUCCESS if DMA transfer initiated properly. +* +* @note None. +* +****************************************************************************/ +static u32 XDcfg_PcapReadback(XDcfg *InstancePtr, u32 SourcePtr, + u32 SrcWordLength, u32 DestPtr, + u32 DestWordLength) +{ + u32 IntrReg; + + /* + * Send READ Frame command to FPGA + */ + XDcfg_InitiateDma(InstancePtr, SourcePtr, XDCFG_DMA_INVALID_ADDRESS, + SrcWordLength, 0); + + /* + * Store the enabled interrupts to enable before the actual read + * transfer is initiated and Disable all the interrupts temporarily. + */ + IntrReg = XDcfg_IntrGetEnabled(InstancePtr); + XDcfg_IntrDisable(InstancePtr, XDCFG_IXR_ALL_MASK); + + /* + * Wait till you get the DMA done for the read command sent + */ + while ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET) & + XDCFG_IXR_D_P_DONE_MASK) != + XDCFG_IXR_D_P_DONE_MASK); + /* + * Enable the previously stored Interrupts . + */ + XDcfg_IntrEnable(InstancePtr, IntrReg); + + /* + * Initiate the DMA write command. + */ + XDcfg_InitiateDma(InstancePtr, XDCFG_DMA_INVALID_ADDRESS, (u32)DestPtr, + 0, DestWordLength); + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** +* +* This function starts the DMA transfer. This function only starts the +* operation and returns before the operation may be completed. +* If the interrupt is enabled, an interrupt will be generated when the +* operation is completed, otherwise it is necessary to poll the Status register +* to determine when it is completed. It is the responsibility of the caller to +* determine when the operation is completed by handling the generated interrupt +* or polling the Status Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param SourcePtr contains a pointer to the source memory where the data +* is to be transferred from. +* @param SrcWordLength is the number of words (32 bit) to be transferred +* for the source transfer. +* @param DestPtr contains a pointer to the destination memory +* where the data is to be transferred to. +* @param DestWordLength is the number of words (32 bit) to be transferred +* for the Destination transfer. +* @param TransferType contains the type of PCAP transfer being requested. +* The definitions can be found in the xdevcfg.h file. +* @return +* - XST_SUCCESS.if DMA transfer initiated successfully +* - XST_DEVICE_BUSY if DMA is busy +* - XST_INVALID_PARAM if invalid Source / Destination address +* is sent or an invalid Source / Destination length is +* sent +* +* @note It is the responsibility of the caller to ensure that the cache +* is flushed and invalidated both before the DMA operation is +* started and after the DMA operation completes if the memory +* pointed to is cached. The caller must also ensure that the +* pointers contain physical address rather than a virtual address +* if address translation is being used. +* +* The 2 LSBs of the SourcePtr (Source)/ DestPtr (Destination) +* address when equal to 2�b01 indicates the last DMA command of +* an overall transfer. +* +*****************************************************************************/ +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType) +{ + + u32 CtrlReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + if (XDcfg_IsDmaBusy(InstancePtr) == XST_SUCCESS) { + return XST_DEVICE_BUSY; + } + + /* + * Check whether the fabric is in initialized state + */ + if ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr, XDCFG_STATUS_OFFSET) + & XDCFG_STATUS_PCFG_INIT_MASK) == 0) { + /* + * We don't need to check PCFG_INIT to be high for + * non-encrypted loopback transfers. + */ + if (TransferType != XDCFG_CONCURRENT_NONSEC_READ_WRITE) { + return XST_FAILURE; + } + } + + if ((TransferType == XDCFG_SECURE_PCAP_WRITE) || + (TransferType == XDCFG_NON_SECURE_PCAP_WRITE)) { + + /* Check for valid source pointer and length */ + if ((!SourcePtr) || (SrcWordLength == 0)) { + return XST_INVALID_PARAM; + } + + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + if (TransferType == XDCFG_NON_SECURE_PCAP_WRITE) { + /* + * Clear QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every clock + */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + + } + if (TransferType == XDCFG_SECURE_PCAP_WRITE) { + /* + * AES engine handles only 8 bit data every clock cycle. + * Hence, Encrypted PCAP data which is 32 bit data can + * only be sent in every 4 clock cycles. Set the control + * register QUARTER_PCAP_RATE_EN bit to achieve this + * operation. + */ + XDcfg_SetControlRegister(InstancePtr, + XDCFG_CTRL_PCAP_RATE_EN_MASK); + } + + XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, + (u32)DestPtr, SrcWordLength, DestWordLength); + + } + + if (TransferType == XDCFG_PCAP_READBACK) { + + if ((!DestPtr) || (DestWordLength == 0)) { + + return XST_INVALID_PARAM; + } + + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + /* + * For PCAP readback of FPGA configuration register or memory, + * the read command is first sent (written) to the FPGA fabric + * which responds by returning the required read data. Read data + * from the FPGA is captured if pcap_radata_v is active.A DMA + * read transfer is required to obtain the readback command, + * which is then sent to the FPGA, followed by a DMA write + * transfer to support this mode of operation. + */ + return XDcfg_PcapReadback(InstancePtr, + (u32)SourcePtr, SrcWordLength, + (u32)DestPtr, DestWordLength); + } + + + if ((TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) || + (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE)) { + + if ((!SourcePtr) || (SrcWordLength == 0) || + (!DestPtr) || (DestWordLength == 0)) { + return XST_INVALID_PARAM; + } + + if (TransferType == XDCFG_CONCURRENT_NONSEC_READ_WRITE) { + /* Enable internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg | + XDCFG_MCTRL_PCAP_LPBK_MASK)); + + /* + * Clear QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every clock + */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET, (CtrlReg & + ~XDCFG_CTRL_PCAP_RATE_EN_MASK)); + + } + if (TransferType == XDCFG_CONCURRENT_SECURE_READ_WRITE) { + /* Clear internal PCAP loopback */ + CtrlReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_MCTRL_OFFSET, (CtrlReg & + ~(XDCFG_MCTRL_PCAP_LPBK_MASK))); + + /* + * Set the QUARTER_PCAP_RATE_EN bit + * so that the PCAP data is transmitted every 4 clock + * cycles, this is required for encrypted data. + */ + XDcfg_SetControlRegister(InstancePtr, + XDCFG_CTRL_PCAP_RATE_EN_MASK); + } + + XDcfg_InitiateDma(InstancePtr, (u32)SourcePtr, + (u32)DestPtr, SrcWordLength, DestWordLength); + } + + return XST_SUCCESS; +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h new file mode 100644 index 0000000..b9a0111 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h @@ -0,0 +1,403 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg.h +* @addtogroup devcfg_v3_5 +* @{ +* @details +* +* The is the main header file for the Device Configuration Interface of the Zynq +* device. The device configuration interface has three main functionality. +* 1. AXI-PCAP +* 2. Security Policy +* 3. XADC +* This current version of the driver supports only the AXI-PCAP and Security +* Policy blocks. There is a separate driver for XADC. +* +* AXI-PCAP is used for download/upload an encrypted or decrypted bitstream. +* DMA embedded in the AXI PCAP provides the master interface to +* the Device configuration block for any DMA transfers. The data transfer can +* take place between the Tx/RxFIFOs of AXI-PCAP and memory (on chip +* RAM/DDR/peripheral memory). +* +* The current driver only supports the downloading the FPGA bitstream and +* readback of the decrypted image (sort of loopback). +* The driver does not know what information needs to be written to the FPGA to +* readback FPGA configuration register or memory data. The application above the +* driver should take care of creating the data that needs to be downloaded to +* the FPGA so that the bitstream can be readback. +* This driver also does not support the reading of the internal registers of the +* PCAP. The driver has no knowledge of the PCAP internals. +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate with the Device Configuration device. +* +* XDcfg_CfgInitialize() API is used to initialize the Device Configuration +* Interface. The user needs to first call the XDcfg_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XDcfg_CfgInitialize() API. +* +* Interrupts +* The Driver implements an interrupt handler to support the interrupts provided +* by this interface. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XDcfg driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +*

    +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.00a nm  05/31/12 Updated the driver for CR 660835 so that input length for
+*		     source/destination to the XDcfg_InitiateDma, XDcfg_Transfer
+*		     APIs is words (32 bit) and not bytes.
+* 		     Updated the notes for XDcfg_InitiateDma/XDcfg_Transfer APIs
+*		     to add information that 2 LSBs of the Source/Destination
+*		     address when equal to 2�b01 indicate the last DMA command
+*		     of an overall transfer.
+*		     Destination Address passed to this API for secure transfers
+*		     instead of using 0xFFFFFFFF for CR 662197. This issue was
+*		     resulting in the failure of secure transfers of
+*		     non-bitstream images.
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+* 		     Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg.
+*		     Added XDcfg_GetPsVersion, XDcfg_SelectIcapInterface
+*		     and XDcfg_SelectPcapInterface APIs for CR 643295
+*		     The user has to call the XDcfg_SelectIcapInterface API
+*		     for the PL reconfiguration using AXI HwIcap.
+*		     Updated the XDcfg_Transfer API to clear the
+*		     QUARTER_PCAP_RATE_EN bit in the control register for
+*		     non secure writes for CR 675543.
+* 2.02a nm  01/31/13 Fixed CR# 679335.
+* 		     Added Setting and Clearing the internal PCAP loopback.
+*		     Removed code for enabling/disabling AES engine as BootROM
+*		     locks down this setting.
+*		     Fixed CR# 681976.
+*		     Skip Checking the PCFG_INIT in case of non-secure DMA
+*		     loopback.
+*		     Fixed CR# 699558.
+*		     XDcfg_Transfer fails to transfer data in loopback mode.
+*		     Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 3.0   adk 10/12/13 Updated as per the New Tcl API's
+* 3.0   kpc 21/02/14 Added function prototype for XDcfg_ClearControlRegister
+* 3.2   sb  08/25/14 Fixed XDcfg_PcapReadback() function
+*		     updated driver code with != instead of ==,
+*		     while checking for Interrupt Status with DMA and
+*		     PCAP Done Mask
+*		     ((XDcfg_ReadReg(InstancePtr->Config.BaseAddr,
+*			XDCFG_INT_STS_OFFSET) &
+*			XDCFG_IXR_D_P_DONE_MASK) !=
+*			XDCFG_IXR_D_P_DONE_MASK);
+*		     A new example has been added to read back the
+*		     configuration registers from the PL region.
+*		     xdevcfg_reg_readback_example.c
+* 3.3   sk  04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*       ms  04/10/17 Modified filename tag in interrupt and polled examples
+*                    to include them in doxygen examples.
+* 3.5   ms  04/18/17 Modified tcl file to add suffix U for all macros
+*                    definitions of devcfg in xparameters.h
+*       ms  08/07/17 Fixed compilation warnings in xdevcfg_sinit.c
+*
    +* +******************************************************************************/ +#ifndef XDCFG_H /* prevent circular inclusions */ +#define XDCFG_H /* by using protection macros */ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" +#include "xstatus.h" +#include "xil_assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ + +/* Types of PCAP transfers */ + +#define XDCFG_NON_SECURE_PCAP_WRITE 1 +#define XDCFG_SECURE_PCAP_WRITE 2 +#define XDCFG_PCAP_READBACK 3 +#define XDCFG_CONCURRENT_SECURE_READ_WRITE 4 +#define XDCFG_CONCURRENT_NONSEC_READ_WRITE 5 + + +/**************************** Type Definitions *******************************/ +/** +* The handler data type allows the user to define a callback function to +* respond to interrupt events in the system. This function is executed +* in interrupt context, so amount of processing should be minimized. +* +* @param CallBackRef is the callback reference passed in by the upper +* layer when setting the callback functions, and passed back to +* the upper layer when the callback is invoked. Its type is +* unimportant to the driver component, so it is a void pointer. +* @param Status is the Interrupt status of the XDcfg device. +*/ +typedef void (*XDcfg_IntrHandler) (void *CallBackRef, u32 Status); + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Base address of the device */ +} XDcfg_Config; + +/** + * The XDcfg driver instance data. + */ +typedef struct { + XDcfg_Config Config; /**< Hardware Configuration */ + u32 IsReady; /**< Device is initialized and ready */ + u32 IsStarted; /**< Device Configuration Interface + * is running + */ + XDcfg_IntrHandler StatusHandler; /* Event handler function */ + void *CallBackRef; /* Callback reference for event handler */ +} XDcfg; + +/****************************************************************************/ +/** +* +* Unlock the Device Config Interface block. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_Unlock(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_Unlock(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_UNLOCK_OFFSET, XDCFG_UNLOCK_DATA) + + + +/****************************************************************************/ +/** +* +* Get the version number of the PS from the Miscellaneous Control Register. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return Version of the PS. +* +* @note C-style signature: +* void XDcfg_GetPsVersion(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_GetPsVersion(InstancePtr) \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MCTRL_OFFSET)) & \ + XDCFG_MCTRL_PCAP_PS_VERSION_MASK) >> \ + XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT + + + +/****************************************************************************/ +/** +* +* Read the multiboot config register value. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* u32 XDcfg_ReadMultiBootConfig(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_ReadMultiBootConfig(InstancePtr) \ + XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, \ + XDCFG_MULTIBOOT_ADDR_OFFSET) + + +/****************************************************************************/ +/** +* +* Selects ICAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectIcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectIcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + & ( ~XDCFG_CTRL_PCAP_PR_MASK))) + +/****************************************************************************/ +/** +* +* Selects PCAP interface for reconfiguration after the initial configuration +* of the PL. +* +* @param InstancePtr is a pointer to the instance of XDcfg driver. +* +* @return None. +* +* @note C-style signature: +* void XDcfg_SelectPcapInterface(XDcfg* InstancePtr) +* +*****************************************************************************/ +#define XDcfg_SelectPcapInterface(InstancePtr) \ + XDcfg_WriteReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET, \ + ((XDcfg_ReadReg((InstancePtr)->Config.BaseAddr, XDCFG_CTRL_OFFSET)) \ + | XDCFG_CTRL_PCAP_PR_MASK)) + + + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xdevcfg_sinit.c. + */ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId); + +/* + * Selftest function in xdevcfg_selftest.c + */ +int XDcfg_SelfTest(XDcfg *InstancePtr); + +/* + * Interface functions in xdevcfg.c + */ +int XDcfg_CfgInitialize(XDcfg *InstancePtr, + XDcfg_Config *ConfigPtr, u32 EffectiveAddress); + +void XDcfg_EnablePCAP(XDcfg *InstancePtr); + +void XDcfg_DisablePCAP(XDcfg *InstancePtr); + +void XDcfg_SetControlRegister(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_ClearControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetControlRegister(XDcfg *InstancePtr); + +void XDcfg_SetLockRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetLockRegister(XDcfg *InstancePtr); + +void XDcfg_SetConfigRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetConfigRegister(XDcfg *InstancePtr); + +void XDcfg_SetStatusRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetStatusRegister(XDcfg *InstancePtr); + +void XDcfg_SetRomShadowRegister(XDcfg *InstancePtr, u32 Data); + +u32 XDcfg_GetSoftwareIdRegister(XDcfg *InstancePtr); + +void XDcfg_SetMiscControlRegister(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_GetMiscControlRegister(XDcfg *InstancePtr); + +u32 XDcfg_IsDmaBusy(XDcfg *InstancePtr); + +void XDcfg_InitiateDma(XDcfg *InstancePtr, u32 SourcePtr, u32 DestPtr, + u32 SrcWordLength, u32 DestWordLength); + +u32 XDcfg_Transfer(XDcfg *InstancePtr, + void *SourcePtr, u32 SrcWordLength, + void *DestPtr, u32 DestWordLength, + u32 TransferType); + +/* + * Interrupt related function prototypes implemented in xdevcfg_intr.c + */ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask); + +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr); + +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr); + +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask); + +void XDcfg_InterruptHandler(XDcfg *InstancePtr); + +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c new file mode 100644 index 0000000..e96911d --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c @@ -0,0 +1,55 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdevcfg.h" + +/* +* The configuration table for devices +*/ + +XDcfg_Config XDcfg_ConfigTable[] = +{ + { + XPAR_PS7_DEV_CFG_0_DEVICE_ID, + XPAR_PS7_DEV_CFG_0_BASEADDR + } +}; + + diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c new file mode 100644 index 0000000..bcb238f --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c @@ -0,0 +1,113 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.c +* @addtogroup devcfg_v3_5 +* @{ +* +* This file contains the implementation of the interface reset functionality +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 2.04a kpc 10/07/13 First release
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg_hw.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** +* This function perform the reset sequence to the given devcfg interface by +* configuring the appropriate control bits in the devcfg specifc registers +* the devcfg reset squence involves the following steps +* Disable all the interuupts +* Clear the status +* Update relevant config registers with reset values +* Disbale the looopback mode and pcap rate enable +* +* @param BaseAddress of the interface +* +* @return N/A +* +* @note +* This function will not modify the slcr registers that are relavant for +* devcfg controller +******************************************************************************/ +void XDcfg_ResetHw(u32 BaseAddr) +{ + u32 Regval = 0; + + /* Mask the interrupts */ + XDcfg_WriteReg(BaseAddr, XDCFG_INT_MASK_OFFSET, + XDCFG_IXR_ALL_MASK); + /* Clear the interuupt status */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_INT_STS_OFFSET); + XDcfg_WriteReg(BaseAddr, XDCFG_INT_STS_OFFSET, Regval); + /* Clear the source address register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_ADDR_OFFSET, 0x0); + /* Clear the destination address register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_ADDR_OFFSET, 0x0); + /* Clear the source length register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_SRC_LEN_OFFSET, 0x0); + /* Clear the destination length register */ + XDcfg_WriteReg(BaseAddr, XDCFG_DMA_DEST_LEN_OFFSET, 0x0); + /* Clear the loopback enable bit */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_MCTRL_OFFSET); + Regval = Regval & ~XDCFG_MCTRL_PCAP_LPBK_MASK; + XDcfg_WriteReg(BaseAddr, XDCFG_MCTRL_OFFSET, Regval); + /*Reset the configuration register to reset value */ + XDcfg_WriteReg(BaseAddr, XDCFG_CFG_OFFSET, + XDCFG_CONFIG_RESET_VALUE); + /*Disable the PCAP rate enable bit */ + Regval = XDcfg_ReadReg(BaseAddr, XDCFG_CTRL_OFFSET); + Regval = Regval & ~XDCFG_CTRL_PCAP_RATE_EN_MASK; + XDcfg_WriteReg(BaseAddr, XDCFG_CTRL_OFFSET, Regval); + +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h new file mode 100644 index 0000000..c506ca5 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h @@ -0,0 +1,395 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_hw.h +* @addtogroup devcfg_v3_3 +* @{ +* +* This file contains the hardware interface to the Device Config Interface. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  08/01/12 Added defines for the PS Version bits,
+*	             removed the FIFO Flush bits from the
+*		     Miscellaneous Control Reg
+* 2.03a nm  04/19/13 Fixed CR# 703728.
+*		     Updated the register definitions as per the latest TRM
+*		     version UG585 (v1.4) November 16, 2012.
+* 2.04a	kpc	10/07/13 Added function prototype.
+* 3.00a	kpc	25/02/14 Corrected the XDCFG_BASE_ADDRESS macro value.
+*
    +* +******************************************************************************/ +#ifndef XDCFG_HW_H /* prevent circular inclusions */ +#define XDCFG_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * Offsets of registers from the start of the device + * @{ + */ + +#define XDCFG_CTRL_OFFSET 0x00 /**< Control Register */ +#define XDCFG_LOCK_OFFSET 0x04 /**< Lock Register */ +#define XDCFG_CFG_OFFSET 0x08 /**< Configuration Register */ +#define XDCFG_INT_STS_OFFSET 0x0C /**< Interrupt Status Register */ +#define XDCFG_INT_MASK_OFFSET 0x10 /**< Interrupt Mask Register */ +#define XDCFG_STATUS_OFFSET 0x14 /**< Status Register */ +#define XDCFG_DMA_SRC_ADDR_OFFSET 0x18 /**< DMA Source Address Register */ +#define XDCFG_DMA_DEST_ADDR_OFFSET 0x1C /**< DMA Destination Address Reg */ +#define XDCFG_DMA_SRC_LEN_OFFSET 0x20 /**< DMA Source Transfer Length */ +#define XDCFG_DMA_DEST_LEN_OFFSET 0x24 /**< DMA Destination Transfer */ +#define XDCFG_ROM_SHADOW_OFFSET 0x28 /**< DMA ROM Shadow Register */ +#define XDCFG_MULTIBOOT_ADDR_OFFSET 0x2C /**< Multi BootAddress Pointer */ +#define XDCFG_SW_ID_OFFSET 0x30 /**< Software ID Register */ +#define XDCFG_UNLOCK_OFFSET 0x34 /**< Unlock Register */ +#define XDCFG_MCTRL_OFFSET 0x80 /**< Miscellaneous Control Reg */ + +/* @} */ + +/** @name Control Register Bit definitions + * @{ + */ + +#define XDCFG_CTRL_FORCE_RST_MASK 0x80000000 /**< Force into + * Secure Reset + */ +#define XDCFG_CTRL_PCFG_PROG_B_MASK 0x40000000 /**< Program signal to + * Reset FPGA + */ +#define XDCFG_CTRL_PCFG_POR_CNT_4K_MASK 0x20000000 /**< Control PL POR timer */ +#define XDCFG_CTRL_PCAP_PR_MASK 0x08000000 /**< Enable PCAP for PR */ +#define XDCFG_CTRL_PCAP_MODE_MASK 0x04000000 /**< Enable PCAP */ +#define XDCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000 /**< Enable PCAP send data + * to FPGA every 4 PCAP + * cycles + */ +#define XDCFG_CTRL_MULTIBOOT_EN_MASK 0x01000000 /**< Multiboot Enable */ +#define XDCFG_CTRL_JTAG_CHAIN_DIS_MASK 0x00800000 /**< JTAG Chain Disable */ +#define XDCFG_CTRL_USER_MODE_MASK 0x00008000 /**< User Mode Mask */ +#define XDCFG_CTRL_PCFG_AES_FUSE_MASK 0x00001000 /**< AES key source */ +#define XDCFG_CTRL_PCFG_AES_EN_MASK 0x00000E00 /**< AES Enable Mask */ +#define XDCFG_CTRL_SEU_EN_MASK 0x00000100 /**< SEU Enable Mask */ +#define XDCFG_CTRL_SEC_EN_MASK 0x00000080 /**< Secure/Non Secure + * Status mask + */ +#define XDCFG_CTRL_SPNIDEN_MASK 0x00000040 /**< Secure Non Invasive + * Debug Enable + */ +#define XDCFG_CTRL_SPIDEN_MASK 0x00000020 /**< Secure Invasive + * Debug Enable + */ +#define XDCFG_CTRL_NIDEN_MASK 0x00000010 /**< Non-Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DBGEN_MASK 0x00000008 /**< Invasive Debug + * Enable + */ +#define XDCFG_CTRL_DAP_EN_MASK 0x00000007 /**< DAP Enable Mask */ + +/* @} */ + +/** @name Lock register bit definitions + * @{ + */ + +#define XDCFG_LOCK_AES_EFUSE_MASK 0x00000010 /**< Lock AES Efuse bit */ +#define XDCFG_LOCK_AES_EN_MASK 0x00000008 /**< Lock AES_EN update */ +#define XDCFG_LOCK_SEU_MASK 0x00000004 /**< Lock SEU_En update */ +#define XDCFG_LOCK_SEC_MASK 0x00000002 /**< Lock SEC_EN and + * USER_MODE + */ +#define XDCFG_LOCK_DBG_MASK 0x00000001 /**< This bit locks + * security config + * including: DAP_En, + * DBGEN,, + * NIDEN, SPNIEN + */ +/*@}*/ + + + +/** @name Config Register Bit definitions + * @{ + */ +#define XDCFG_CFG_RFIFO_TH_MASK 0x00000C00 /**< Read FIFO + * Threshold Mask + */ +#define XDCFG_CFG_WFIFO_TH_MASK 0x00000300 /**< Write FIFO Threshold + * Mask + */ +#define XDCFG_CFG_RCLK_EDGE_MASK 0x00000080 /**< Read data active + * clock edge + */ +#define XDCFG_CFG_WCLK_EDGE_MASK 0x00000040 /**< Write data active + * clock edge + */ +#define XDCFG_CFG_DISABLE_SRC_INC_MASK 0x00000020 /**< Disable Source address + * increment mask + */ +#define XDCFG_CFG_DISABLE_DST_INC_MASK 0x00000010 /**< Disable Destination + * address increment + * mask + */ +/* @} */ + + +/** @name Interrupt Status/Mask Register Bit definitions + * @{ + */ +#define XDCFG_IXR_PSS_GTS_USR_B_MASK 0x80000000 /**< Tri-state IO during + * HIZ + */ +#define XDCFG_IXR_PSS_FST_CFG_B_MASK 0x40000000 /**< First configuration + * done + */ +#define XDCFG_IXR_PSS_GPWRDWN_B_MASK 0x20000000 /**< Global power down */ +#define XDCFG_IXR_PSS_GTS_CFG_B_MASK 0x10000000 /**< Tri-state IO during + * configuration + */ +#define XDCFG_IXR_PSS_CFG_RESET_B_MASK 0x08000000 /**< PL configuration + * reset + */ +#define XDCFG_IXR_AXI_WTO_MASK 0x00800000 /**< AXI Write Address + * or Data or response + * timeout + */ +#define XDCFG_IXR_AXI_WERR_MASK 0x00400000 /**< AXI Write response + * error + */ +#define XDCFG_IXR_AXI_RTO_MASK 0x00200000 /**< AXI Read Address or + * response timeout + */ +#define XDCFG_IXR_AXI_RERR_MASK 0x00100000 /**< AXI Read response + * error + */ +#define XDCFG_IXR_RX_FIFO_OV_MASK 0x00040000 /**< Rx FIFO Overflow */ +#define XDCFG_IXR_WR_FIFO_LVL_MASK 0x00020000 /**< Tx FIFO less than + * threshold */ +#define XDCFG_IXR_RD_FIFO_LVL_MASK 0x00010000 /**< Rx FIFO greater than + * threshold */ +#define XDCFG_IXR_DMA_CMD_ERR_MASK 0x00008000 /**< Illegal DMA command */ +#define XDCFG_IXR_DMA_Q_OV_MASK 0x00004000 /**< DMA command queue + * overflow + */ +#define XDCFG_IXR_DMA_DONE_MASK 0x00002000 /**< DMA Command Done */ +#define XDCFG_IXR_D_P_DONE_MASK 0x00001000 /**< DMA and PCAP + * transfers Done + */ +#define XDCFG_IXR_P2D_LEN_ERR_MASK 0x00000800 /**< PCAP to DMA transfer + * length error + */ +#define XDCFG_IXR_PCFG_HMAC_ERR_MASK 0x00000040 /**< HMAC error mask */ +#define XDCFG_IXR_PCFG_SEU_ERR_MASK 0x00000020 /**< SEU Error mask */ +#define XDCFG_IXR_PCFG_POR_B_MASK 0x00000010 /**< FPGA POR mask */ +#define XDCFG_IXR_PCFG_CFG_RST_MASK 0x00000008 /**< FPGA Reset mask */ +#define XDCFG_IXR_PCFG_DONE_MASK 0x00000004 /**< Done Signal Mask */ +#define XDCFG_IXR_PCFG_INIT_PE_MASK 0x00000002 /**< Detect Positive edge + * of Init Signal + */ +#define XDCFG_IXR_PCFG_INIT_NE_MASK 0x00000001 /**< Detect Negative edge + * of Init Signal + */ +#define XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WTO_MASK | \ + XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + + +#define XDCFG_IXR_ALL_MASK 0x00F7F8EF + + + +/* @} */ + + +/** @name Status Register Bit definitions + * @{ + */ +#define XDCFG_STATUS_DMA_CMD_Q_F_MASK 0x80000000 /**< DMA command + * Queue full + */ +#define XDCFG_STATUS_DMA_CMD_Q_E_MASK 0x40000000 /**< DMA command + * Queue empty + */ +#define XDCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000 /**< Number of + * completed DMA + * transfers + */ +#define XDCFG_STATUS_RX_FIFO_LVL_MASK 0x01F000000 /**< Rx FIFO level */ +#define XDCFG_STATUS_TX_FIFO_LVL_MASK 0x0007F000 /**< Tx FIFO level */ + +#define XDCFG_STATUS_PSS_GTS_USR_B 0x00000800 /**< Tri-state IO + * during HIZ + */ +#define XDCFG_STATUS_PSS_FST_CFG_B 0x00000400 /**< First PL config + * done + */ +#define XDCFG_STATUS_PSS_GPWRDWN_B 0x00000200 /**< Global power down */ +#define XDCFG_STATUS_PSS_GTS_CFG_B 0x00000100 /**< Tri-state IO during + * config + */ +#define XDCFG_STATUS_SECURE_RST_MASK 0x00000080 /**< Secure Reset + * POR Status + */ +#define XDCFG_STATUS_ILLEGAL_APB_ACCESS_MASK 0x00000040 /**< Illegal APB + * access + */ +#define XDCFG_STATUS_PSS_CFG_RESET_B 0x00000020 /**< PL config + * reset status + */ +#define XDCFG_STATUS_PCFG_INIT_MASK 0x00000010 /**< FPGA Init + * Status + */ +#define XDCFG_STATUS_EFUSE_BBRAM_KEY_DISABLE_MASK 0x00000008 + /**< BBRAM key + * disable + */ +#define XDCFG_STATUS_EFUSE_SEC_EN_MASK 0x00000004 /**< Efuse Security + * Enable Status + */ +#define XDCFG_STATUS_EFUSE_JTAG_DIS_MASK 0x00000002 /**< EFuse JTAG + * Disable + * status + */ +/* @} */ + + +/** @name DMA Source/Destination Transfer Length Register Bit definitions + * @{ + */ +#define XDCFG_DMA_LEN_MASK 0x7FFFFFF /**< Length Mask */ +/*@}*/ + + + + +/** @name Miscellaneous Control Register Bit definitions + * @{ + */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_MASK 0xF0000000 /**< PS Version Mask */ +#define XDCFG_MCTRL_PCAP_PS_VERSION_SHIFT 28 /**< PS Version Shift */ +#define XDCFG_MCTRL_PCAP_LPBK_MASK 0x00000010 /**< PCAP loopback mask */ +/* @} */ + +/** @name FIFO Threshold Bit definitions + * @{ + */ + +#define XDCFG_CFG_FIFO_QUARTER 0x0 /**< Quarter empty */ +#define XDCFG_CFG_FIFO_HALF 0x1 /**< Half empty */ +#define XDCFG_CFG_FIFO_3QUARTER 0x2 /**< 3/4 empty */ +#define XDCFG_CFG_FIFO_EMPTY 0x4 /**< Empty */ +/* @}*/ + + +/* Miscellaneous constant values */ +#define XDCFG_DMA_INVALID_ADDRESS 0xFFFFFFFF /**< Invalid DMA address */ +#define XDCFG_UNLOCK_DATA 0x757BDF0D /**< First APB access data*/ +#define XDCFG_BASE_ADDRESS 0xF8007000 /**< Device Config base + * address + */ +#define XDCFG_CONFIG_RESET_VALUE 0x508 /**< Config reg reset value */ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be read +* +* @return The 32-bit value of the register +* +* @note C-style signature: +* u32 XDcfg_ReadReg(u32 BaseAddr, u32 RegOffset) +* +*****************************************************************************/ +#define XDcfg_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (RegOffset)) + +/****************************************************************************/ +/** +* +* Write to the given register. +* +* @param BaseAddr is the base address of the device +* @param RegOffset is the register offset to be written +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note C-style signature: +* void XDcfg_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data) +* +*****************************************************************************/ +#define XDcfg_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (RegOffset), (Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the devcfg interface + */ +void XDcfg_ResetHw(u32 BaseAddr); +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c new file mode 100644 index 0000000..b41b7ea --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c @@ -0,0 +1,310 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_intr.c +* @addtogroup devcfg_v3_5 +* @{ +* +* Contains the implementation of interrupt related functions of the XDcfg +* driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.01a nm  07/07/12 Updated the XDcfg_IntrClear function to directly
+*		     set the mask instead of oring it with the
+*		     value read from the interrupt status register
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* This function enables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be enabled. +* Bit positions of 1 will be enabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XDCFG_INT_* bits defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrEnable(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Enable the specified interrupts in the Interrupt Mask Register. + */ + RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET); + RegValue &= ~(Mask & XDCFG_IXR_ALL_MASK); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET, + RegValue); +} + + +/****************************************************************************/ +/** +* +* This function disables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be disabled. +* Bit positions of 1 will be disabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XDCFG_INT_* bits defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrDisable(XDcfg *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Disable the specified interrupts in the Interrupt Mask Register. + */ + RegValue = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET); + RegValue |= (Mask & XDCFG_IXR_ALL_MASK); + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET, + RegValue); +} +/****************************************************************************/ +/** +* +* This function returns the enabled interrupts read from the Interrupt Mask +* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the IMR. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_IntrGetEnabled(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Mask Register. + */ + return (~ XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_MASK_OFFSET)); +} + +/****************************************************************************/ +/** +* +* This function returns the interrupt status read from Interrupt Status +* Register. Use the XDCFG_INT_* constants defined in xdevcfg_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return A 32-bit value representing the contents of the Interrupt +* Status register. +* +* @note None. +* +*****************************************************************************/ +u32 XDcfg_IntrGetStatus(XDcfg *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Status register. + */ + return XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function clears the specified interrupts in the Interrupt Status +* Register. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* @param Mask is the bit-mask of the interrupts to be cleared. +* Bit positions of 1 will be cleared. Bit positions of 0 will not +* change the previous interrupt status. This mask is formed by +* OR'ing XDCFG_INT_* bits which are defined in xdevcfg_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XDcfg_IntrClear(XDcfg *InstancePtr, u32 Mask) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET, + Mask); + +} + +/*****************************************************************************/ +/** +* The interrupt handler for the Device Config Interface. +* +* Events are signaled to upper layer for proper handling. +* +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XDcfg_InterruptHandler(XDcfg *InstancePtr) +{ + u32 IntrStatusReg; + + /* + * Assert validates the input arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Read the Interrupt status register. + */ + IntrStatusReg = XDcfg_ReadReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET); + + /* + * Write the status back to clear the interrupts so that no + * subsequent interrupts are missed while processing this interrupt. + * This also does the DMA acknowledgment automatically. + */ + XDcfg_WriteReg(InstancePtr->Config.BaseAddr, + XDCFG_INT_STS_OFFSET, IntrStatusReg); + + /* + * Signal application that there are events to handle. + */ + InstancePtr->StatusHandler(InstancePtr->CallBackRef, + IntrStatusReg); + +} + +/****************************************************************************/ +/** +* +* This function sets the handler that will be called when an event (interrupt) +* occurs that needs application's attention. +* +* @param InstancePtr is a pointer to the XDcfg instance +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return None. +* +* @note None. +* +* +*****************************************************************************/ +void XDcfg_SetHandler(XDcfg *InstancePtr, void *CallBackFunc, + void *CallBackRef) +{ + /* + * Asserts validate the input arguments + * CallBackRef not checked, no way to know what is valid + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(CallBackFunc != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + InstancePtr->StatusHandler = (XDcfg_IntrHandler) CallBackFunc; + InstancePtr->CallBackRef = CallBackRef; +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c new file mode 100644 index 0000000..40cf1de --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c @@ -0,0 +1,114 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdevcfg_selftest.c +* @addtogroup devcfg_v3_5 +* @{ +* +* Contains diagnostic self-test functions for the XDcfg driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 2.02a nm  02/27/13 Fixed CR# 701348.
+*                    Peripheral test fails with  Running
+* 		     DcfgSelfTestExample() in SECURE bootmode.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/****************************************************************************/ +/** +* +* Run a self-test on the Device Configuration Interface. This test does a +* control register write and reads back the same value. +* +* @param InstancePtr is a pointer to the XDcfg instance. +* +* @return +* - XST_SUCCESS if self-test was successful. +* - XST_FAILURE if fails. +* +* @note None. +* +******************************************************************************/ +int XDcfg_SelfTest(XDcfg *InstancePtr) +{ + u32 OldCfgReg; + u32 CfgReg; + int Status = XST_SUCCESS; + + /* + * Assert to ensure the inputs are valid and the instance has been + * initialized. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + OldCfgReg = XDcfg_GetControlRegister(InstancePtr); + + XDcfg_SetControlRegister(InstancePtr, XDCFG_CTRL_NIDEN_MASK); + + CfgReg = XDcfg_GetControlRegister(InstancePtr); + + if ((CfgReg & XDCFG_CTRL_NIDEN_MASK) != XDCFG_CTRL_NIDEN_MASK) { + + Status = XST_FAILURE; + } + + /* + * Restore the original values of the register + */ + XDcfg_SetControlRegister(InstancePtr, OldCfgReg); + + return Status; +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c new file mode 100644 index 0000000..bbc96a0 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c @@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdevcfg_sinit.c +* @addtogroup devcfg_v3_5 +* @{ +* +* This file contains method for static initialization (compile-time) of the +* driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a hvm 02/07/11 First release
+* 3.5   ms  08/07/17 Fixed compilation warnings.
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xdevcfg.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* Lookup the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId) +{ + extern XDcfg_Config XDcfg_ConfigTable[]; + XDcfg_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) { + if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XDcfg_ConfigTable[Index]; + break; + } + } + + return (CfgPtr); +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c new file mode 100644 index 0000000..9db7692 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c @@ -0,0 +1,1982 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.c +* @addtogroup dmaps_v2_3 +* @{ +* +* This file contains the implementation of the interface functions for XDmaPs +* driver. Refer to the header file xdmaps.h for more detailed information. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/2010 First Release
+* 1.00  nm     05/25/2011 Updated for minor doxygen corrections
+* 1.02a sg     05/16/2012 Made changes for doxygen and moved some function
+*			  header from the xdmaps.h file to xdmaps.c file
+*			  Other cleanup for coding guidelines and CR 657109
+*			  and CR 657898
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.01 kpc    08/23/14   Fixed the IAR compiler reported errors
+* 2.2  mus    12/08/16   Remove definition of INLINE macro to avoid re-definition,
+*                         since it is being defined in xil_io.h
+* 2.3 kpc     14/10/16   Fixed the compiler error when optimization O0 is used.
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include + +#include "xstatus.h" +#include "xdmaps.h" +#include "xil_io.h" +#include "xil_cache.h" + +#include "xil_printf.h" + + +/************************** Constant Definitions ****************************/ + +/* The following constant defines the amount of error that is allowed for + * a specified baud rate. This error is the difference between the actual + * baud rate that will be generated using the specified clock and the + * desired baud rate. + */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Function Prototypes *****************************/ +static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, + unsigned int Channel, + unsigned int Thread); + +static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf); + +static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg); + +static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel); +static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool); +static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, + unsigned CacheLength); + +static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length); + + + +/************************** Variable Definitions ****************************/ + +/****************************************************************************/ +/** +* +* Initializes a specific XDmaPs instance such that it is ready to be used. +* The data format of the device is setup for 8 data bits, 1 stop bit, and no +* parity by default. The baud rate is set to a default value specified by +* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The +* receive FIFO threshold is set for 8 bytes. The default operating mode of the +* driver is polled mode. +* +* @param InstPtr is a pointer to the XDmaPs instance. +* @param Config is a reference to a structure containing information +* about a specific XDmaPs driver. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the +* address mapping from EffectiveAddr to the device physical base +* address unchanged once this function is invoked. Unexpected +* errors may occur if the address mapping changes after this +* function is called. If address translation is not used, pass in +* the physical address instead. +* +* @return +* +* - XST_SUCCESS on initialization completion +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr) +{ + int Status = XST_SUCCESS; + unsigned int CacheLength = 0; + u32 CfgReg; + unsigned Channel; + XDmaPs_ChannelData *ChanData; + + /* + * Assert validates the input arguments + */ + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Config != NULL); + + /* + * Setup the driver instance using passed in parameters + */ + InstPtr->Config.DeviceId = Config->DeviceId; + InstPtr->Config.BaseAddress = EffectiveAddr; + + CfgReg = XDmaPs_ReadReg(EffectiveAddr, XDMAPS_CR1_OFFSET); + CacheLength = CfgReg & XDMAPS_CR1_I_CACHE_LEN_MASK; + if (CacheLength < 2 || CacheLength > 5) + CacheLength = 0; + else + CacheLength = 1 << CacheLength; + + InstPtr->CacheLength = CacheLength; + + memset(InstPtr->Chans, 0, + sizeof(XDmaPs_ChannelData[XDMAPS_CHANNELS_PER_DEV])); + + for (Channel = 0; Channel < XDMAPS_CHANNELS_PER_DEV; Channel++) { + ChanData = InstPtr->Chans + Channel; + ChanData->ChanId = Channel; + ChanData->DevId = Config->DeviceId; + } + + InstPtr->IsReady = 1; + + return Status; +} + +/****************************************************************************/ +/** +* +* Reset the DMA Manager. +* +* @param InstPtr is the DMA instance. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ResetManager(XDmaPs *InstPtr) +{ + int Status; + Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, + 0, 0); + + return Status; +} + +/****************************************************************************/ +/** +* +* Reset the specified DMA Channel. +* +* @param InstPtr is the DMA instance. +* @param Channel is the channel to be reset. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel) +{ + int Status; + Status = XDmaPs_Exec_DMAKILL(InstPtr->Config.BaseAddress, + Channel, 1); + + return Status; + +} + +/*****************************************************************************/ +/** +* +* Driver fault interrupt service routine +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_FaultISR(XDmaPs *InstPtr) +{ + + void *DmaProgBuf; + u32 Fsm; /* Fault status DMA manager register value */ + u32 Fsc; /* Fault status DMA channel register value */ + u32 FaultType; /* Fault type DMA manager register value */ + + u32 BaseAddr = InstPtr->Config.BaseAddress; + + u32 Pc; /* DMA Pc or channel Pc */ + XDmaPs_ChannelData *ChanData; + + unsigned Chan; + unsigned DevId; + + XDmaPs_Cmd *DmaCmd; + + Fsm = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSM_OFFSET) & 0x01; + Fsc = XDmaPs_ReadReg(BaseAddr, XDMAPS_FSC_OFFSET) & 0xFF; + + + DevId = InstPtr->Config.DeviceId; + + if (Fsm) { + /* + * if DMA manager is fault + */ + FaultType = XDmaPs_ReadReg(BaseAddr, XDMAPS_FTM_OFFSET); + Pc = XDmaPs_ReadReg(BaseAddr, XDMAPS_DPC_OFFSET); + + xil_printf("PL330 device %d fault with type: %x at Pc %x\n", + DevId, + FaultType, Pc); + + /* kill the DMA manager thread */ + /* Should we disable interrupt?*/ + XDmaPs_Exec_DMAKILL(BaseAddr, 0, 0); + } + + /* + * check which channel faults and kill the channel thread + */ + for (Chan = 0; + Chan < XDMAPS_CHANNELS_PER_DEV; + Chan++) { + if (Fsc & (0x01 << Chan)) { + FaultType = + XDmaPs_ReadReg(BaseAddr, + XDmaPs_FTCn_OFFSET(Chan)); + Pc = XDmaPs_ReadReg(BaseAddr, + XDmaPs_CPCn_OFFSET(Chan)); + + /* kill the channel thread */ + /* Should we disable interrupt? */ + XDmaPs_Exec_DMAKILL(BaseAddr, Chan, 1); + + /* + * get the fault type and fault Pc and invoke the + * fault callback. + */ + ChanData = InstPtr->Chans + Chan; + + DmaCmd = ChanData->DmaCmdToHw; + + /* Should we check DmaCmd is not null */ + DmaCmd->DmaStatus = -1; + DmaCmd->ChanFaultType = FaultType; + DmaCmd->ChanFaultPCAddr = Pc; + ChanData->DmaCmdFromHw = DmaCmd; + ChanData->DmaCmdToHw = NULL; + + if (!ChanData->HoldDmaProg) { + DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; + if (DmaProgBuf) + XDmaPs_BufPool_Free(ChanData->ProgBufPool, + DmaProgBuf); + DmaCmd->GeneratedDmaProg = NULL; + } + + if (InstPtr->FaultHandler) + InstPtr->FaultHandler(Chan, + DmaCmd, + InstPtr->FaultRef); + + } + } + +} + +/*****************************************************************************/ +/** +* +* Set the done handler for a channel. +* +* @param InstPtr is the DMA instance. +* @param Channel is the channel number. +* @param DoneHandler is the done interrupt handler. +* @param CallbackRef is the callback reference data. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef) +{ + XDmaPs_ChannelData *ChanData; + + Xil_AssertNonvoid(InstPtr != NULL); + + if (Channel >= XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + + ChanData = InstPtr->Chans + Channel; + + ChanData->DoneHandler = DoneHandler; + ChanData->DoneRef = CallbackRef; + + return 0; +} + +/*****************************************************************************/ +/** +* +* Set the fault handler for a channel. +* +* @param InstPtr is the DMA instance. +* @param FaultHandler is the fault interrupt handler. +* @param CallbackRef is the callback reference data. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef) +{ + Xil_AssertNonvoid(InstPtr != NULL); + + InstPtr->FaultHandler = FaultHandler; + InstPtr->FaultRef = CallbackRef; + + return XST_SUCCESS; +} + + + +/****************************************************************************/ +/** +* Construction function for DMAEND instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg the DMA program buffer, it's the starting address for +* the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg) +{ + /* + * DMAEND encoding: + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 0 0 0 + */ + *DmaProg = 0x0; + + return 1; +} + +static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src) +{ + *Dst = *Src; + *(Dst + 1) = *(Src + 1); + *(Dst + 2) = *(Src + 2); + *(Dst + 3) = *(Src + 3); +} + +/****************************************************************************/ +/** +* +* Construction function for DMAGO instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Cn is the Channel number, 0 - 7 +* @param Imm is 32-bit immediate number written to the Channel Program +* Counter. +* @param Ns is Non-secure flag. If Ns is 1, the DMA channel operates in +* the Non-secure state. If Ns is 0, the execution depends on the +* security state of the DMA manager: +* DMA manager is in the Secure state, DMA channel operates in the +* Secure state. +* DMA manager is in the Non-secure state, DMAC aborts. +* +* @return The number of bytes for this instruction which is 6. +* +* @note None +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns) +{ + /* + * DMAGO encoding: + * 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 + * 0 0 0 0 0 |cn[2:0]| 1 0 1 0 0 0 ns 0 + * + * 47 ... 16 + * imm[32:0] + */ + *DmaProg = 0xA0 | ((Ns << 1) & 0x02); + + *(DmaProg + 1) = (u8)(Cn & 0x07); + + // *((u32 *)(DmaProg + 2)) = Imm; + XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm); + + /* success */ + return 6; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALD instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg the DMA program buffer, it's the starting address for the +* instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMALD(char *DmaProg) +{ + /* + * DMALD encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 1 bs x + * + * Note: this driver doesn't support conditional load or store, + * so the bs bit is 0 and x bit is 0. + */ + *DmaProg = 0x04; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALP instruction. This function fills the program +* buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Lc is the Loop counter register, can either be 0 or 1. +* @param LoopIterations: the number of interations, LoopInterations - 1 +* will be encoded in the DMALP instruction. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations) +{ + /* + * DMALP encoding + * 15 ... 8 7 6 5 4 3 2 1 0 + * | iter[7:0] |0 0 1 0 0 0 lc 0 + */ + *DmaProg = (u8)(0x20 | ((Lc & 1) << 1)); + *(DmaProg + 1) = (u8)(LoopIterations - 1); + return 2; +} + +/****************************************************************************/ +/** +* +* Construction function for DMALPEND instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param BodyStart is the starting address of the loop body. It is used +* to calculate the bytes of backward jump. +* @param Lc is the Loop counter register, can either be 0 or 1. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc) +{ + /* + * DMALPEND encoding + * 15 ... 8 7 6 5 4 3 2 1 0 + * | backward_jump[7:0] |0 0 1 nf 1 lc bs x + * + * lc: loop counter + * nf is for loop forever. The driver does not support loop forever, + * so nf is 1. + * The driver does not support conditional LPEND, so bs is 0, x is 0. + */ + *DmaProg = 0x38 | ((Lc & 1) << 2); + *(DmaProg + 1) = (u8)(DmaProg - BodyStart); + + return 2; +} + +/* + * Register number for the DMAMOV instruction + */ +#define XDMAPS_MOV_SAR 0x0 +#define XDMAPS_MOV_CCR 0x1 +#define XDMAPS_MOV_DAR 0x2 + +/****************************************************************************/ +/** +* +* Construction function for DMAMOV instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param Rd is the register id, 0 for SAR, 1 for CCR, and 2 for DAR +* @param Imm is the 32-bit immediate number +* +* @return The number of bytes for this instruction which is 6. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm) +{ + /* + * DMAMOV encoding + * 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0 + * 0 0 0 0 0 |rd[2:0]|1 0 1 1 1 1 0 0 + * + * 47 ... 16 + * imm[32:0] + * + * rd: b000 for SAR, b001 CCR, b010 DAR + */ + *DmaProg = 0xBC; + *(DmaProg + 1) = Rd & 0x7; + // *((u32 *)(DmaProg + 2)) = Imm; + XDmaPs_Memcpy4(DmaProg + 2, (char *)&Imm); + + return 6; +} + +/****************************************************************************/ +/** +* +* Construction function for DMANOP instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg) +{ + /* + * DMANOP encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 1 0 0 0 + */ + *DmaProg = 0x18; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMARMB instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMARMB(char *DmaProg) +{ + /* + * DMARMB encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 0 0 1 0 + */ + *DmaProg = 0x12; + return 1; +} + +/****************************************************************************/ +/** +* +* Construction function for DMASEV instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* @param EventNumber is the Event number to signal. +* +* @return The number of bytes for this instruction which is 2. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber) +{ + /* + * DMASEV encoding + * 15 4 3 2 1 10 9 8 7 6 5 4 3 2 1 0 + * |event[4:0]| 0 0 0 0 0 1 1 0 1 0 0 + */ + *DmaProg = 0x34; + *(DmaProg + 1) = (u8)(EventNumber << 3); + + return 2; +} + + +/****************************************************************************/ +/** +* +* Construction function for DMAST instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAST(char *DmaProg) +{ + /* + * DMAST encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 0 1 0 bs x + * + * Note: this driver doesn't support conditional load or store, + * so the bs bit is 0 and x bit is 0. + */ + *DmaProg = 0x08; + return 1; +} + + +/****************************************************************************/ +/** +* +* Construction function for DMAWMB instruction. This function fills the +* program buffer with the constructed instruction. +* +* @param DmaProg is the DMA program buffer, it's the starting address +* for the instruction being constructed +* +* @return The number of bytes for this instruction which is 1. +* +* @note None. +* +*****************************************************************************/ +static INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg) +{ + /* + * DMAWMB encoding + * 7 6 5 4 3 2 1 0 + * 0 0 0 1 0 0 1 0 + */ + *DmaProg = 0x13; + return 1; +} + +/****************************************************************************/ +/** +* +* Conversion function from the endian swap size to the bit encoding of the CCR +* +* @param EndianSwapSize is the endian swap size, in terms of bits, it +* could be 8, 16, 32, 64, or 128(We are using DMA assembly syntax) +* +* @return The endian swap size bit encoding for the CCR. +* +* @note None. +* +*****************************************************************************/ +static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) +{ + switch (EndianSwapSize) { + case 0: + case 8: + return 0; + case 16: + return 1; + case 32: + return 2; + case 64: + return 3; + case 128: + return 4; + default: + return 0; + } + +} + +/****************************************************************************/ +/** +* +* Conversion function from the burst size to the bit encoding of the CCR +* +* @param BurstSize is the burst size. It's the data width. +* In terms of bytes, it could be 1, 2, 4, 8, 16, 32, 64, or 128. +* It must be no larger than the bus width. +* (We are using DMA assembly syntax.) +* +* @note None. +* +*****************************************************************************/ +static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize) +{ + switch (BurstSize) { + case 1: + return 0; + case 2: + return 1; + case 4: + return 2; + case 8: + return 3; + case 16: + return 4; + case 32: + return 5; + case 64: + return 6; + case 128: + return 7; + default: + return 0; + } +} + + +/****************************************************************************/ +/** +* +* Conversion function from PL330 bus transfer descriptors to CCR value. All the +* values passed to the functions are in terms of assembly languages, not in +* terms of the register bit encoding. +* +* @param ChanCtrl is the Instance of XDmaPs_ChanCtrl. +* +* @return The 32-bit CCR value. +* +* @note None. +* +*****************************************************************************/ +u32 XDmaPs_ToCCRValue(XDmaPs_ChanCtrl *ChanCtrl) +{ + /* + * Channel Control Register encoding + * [31:28] - endian_swap_size + * [27:25] - dst_cache_ctrl + * [24:22] - dst_prot_ctrl + * [21:18] - dst_burst_len + * [17:15] - dst_burst_size + * [14] - dst_inc + * [13:11] - src_cache_ctrl + * [10:8] - src_prot_ctrl + * [7:4] - src_burst_len + * [3:1] - src_burst_size + * [0] - src_inc + */ + + unsigned es = + XDmaPs_ToEndianSwapSizeBits(ChanCtrl->EndianSwapSize); + + unsigned dst_burst_size = + XDmaPs_ToBurstSizeBits(ChanCtrl->DstBurstSize); + unsigned dst_burst_len = (ChanCtrl->DstBurstLen - 1) & 0x0F; + unsigned dst_cache_ctrl = (ChanCtrl->DstCacheCtrl & 0x03) + | ((ChanCtrl->DstCacheCtrl & 0x08) >> 1); + unsigned dst_prot_ctrl = ChanCtrl->DstProtCtrl & 0x07; + unsigned dst_inc_bit = ChanCtrl->DstInc & 1; + + unsigned src_burst_size = + XDmaPs_ToBurstSizeBits(ChanCtrl->SrcBurstSize); + unsigned src_burst_len = (ChanCtrl->SrcBurstLen - 1) & 0x0F; + unsigned src_cache_ctrl = (ChanCtrl->SrcCacheCtrl & 0x03) + | ((ChanCtrl->SrcCacheCtrl & 0x08) >> 1); + unsigned src_prot_ctrl = ChanCtrl->SrcProtCtrl & 0x07; + unsigned src_inc_bit = ChanCtrl->SrcInc & 1; + + u32 ccr_value = (es << 28) + | (dst_cache_ctrl << 25) + | (dst_prot_ctrl << 22) + | (dst_burst_len << 18) + | (dst_burst_size << 15) + | (dst_inc_bit << 14) + | (src_cache_ctrl << 11) + | (src_prot_ctrl << 8) + | (src_burst_len << 4) + | (src_burst_size << 1) + | (src_inc_bit); + + return ccr_value; +} + +/****************************************************************************/ +/** +* Construct a loop with only DMALD and DMAST as the body using loop counter 0. +* The function also makes sure the loop body and the lpend is in the same +* cache line. +* +* @param DmaProgStart is the very start address of the DMA program. +* This is used to calculate whether the loop is in a cache line. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* @param DmaProgLoopStart The starting address of the loop (DMALP). +* @param LoopCount The inner loop count. Loop count - 1 will be used to +* initialize the loop counter. +* +* @return The number of bytes the loop has. +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ConstructSingleLoop(char *DmaProgStart, + int CacheLength, + char *DmaProgLoopStart, + int LoopCount) +{ + int CacheStartOffset; + int CacheEndOffset; + int NumNops; + char *DmaProgBuf = DmaProgLoopStart; + + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCount); + + if (CacheLength > 0) { + /* + * the CacheLength > 0 switch is ued to turn on/off nop + * insertion + */ + CacheStartOffset = DmaProgBuf - DmaProgStart; + CacheEndOffset = CacheStartOffset + 3; + + /* + * check whether the body and lpend fit in one cache line + */ + if (CacheStartOffset / CacheLength + != CacheEndOffset / CacheLength) { + /* insert the nops */ + NumNops = CacheLength + - CacheStartOffset % CacheLength; + while (NumNops--) { + DmaProgBuf += + XDmaPs_Instr_DMANOP(DmaProgBuf); + } + } + } + + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + DmaProgBuf - 2, 0); + + return DmaProgBuf - DmaProgLoopStart; +} + +/****************************************************************************/ +/** +* Construct a nested loop with only DMALD and DMAST in the inner loop body. +* It uses loop counter 1 for the outer loop and loop counter 0 for the +* inner loop. +* +* @param DmaProgStart is the very start address of the DMA program. +* This is used to calculate whether the loop is in a cache line. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* @param DmaProgLoopStart The starting address of the loop (DMALP). +* @param LoopCountOuter The outer loop count. Loop count - 1 will be +* used to initialize the loop counter. +* @param LoopCountInner The inner loop count. Loop count - 1 will be +* used to initialize the loop counter. +* +* @return The number byes the nested loop program has. +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_ConstructNestedLoop(char *DmaProgStart, + int CacheLength, + char *DmaProgLoopStart, + unsigned int LoopCountOuter, + unsigned int LoopCountInner) +{ + int CacheStartOffset; + int CacheEndOffset; + int NumNops; + char *InnerLoopStart; + char *DmaProgBuf = DmaProgLoopStart; + + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 1, LoopCountOuter); + InnerLoopStart = DmaProgBuf; + + if (CacheLength > 0) { + /* + * the CacheLength > 0 switch is ued to turn on/off nop + * insertion + */ + if (CacheLength < 8) { + /* + * if the cache line is too small to fit both loops + * just align the inner loop + */ + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCountInner); + /* outer loop end */ + DmaProgBuf += + XDmaPs_Instr_DMALPEND(DmaProgBuf, + InnerLoopStart, + 1); + + /* + * the nested loop is constructed for + * smaller cache line + */ + return DmaProgBuf - DmaProgLoopStart; + } + + /* + * Now let's handle the case where a cache line can + * fit the nested loops. + */ + CacheStartOffset = DmaProgBuf - DmaProgStart; + CacheEndOffset = CacheStartOffset + 7; + + /* + * check whether the body and lpend fit in one cache line + */ + if (CacheStartOffset / CacheLength + != CacheEndOffset / CacheLength) { + /* insert the nops */ + NumNops = CacheLength + - CacheStartOffset % CacheLength; + while (NumNops--) { + DmaProgBuf += + XDmaPs_Instr_DMANOP(DmaProgBuf); + } + } + } + + /* insert the inner DMALP */ + DmaProgBuf += XDmaPs_Instr_DMALP(DmaProgBuf, 0, LoopCountInner); + + /* DMALD and DMAST instructions */ + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + + /* inner DMALPEND */ + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + DmaProgBuf - 2, 0); + /* outer DMALPEND */ + DmaProgBuf += XDmaPs_Instr_DMALPEND(DmaProgBuf, + InnerLoopStart, 1); + + /* return the number of bytes */ + return DmaProgBuf - DmaProgLoopStart; +} + +/* + * [31:28] endian_swap_size b0000 + * [27:25] dst_cache_ctrl b000 + * [24:22] dst_prot_ctrl b000 + * [21:18] dst_burst_len b0000 + * [17:15] dst_burst_size b000 + * [14] dst_inc b0 + * [27:25] src_cache_ctrl b000 + * [24:22] src_prot_ctrl b000 + * [21:18] src_burst_len b0000 + * [17:15] src_burst_size b000 + * [14] src_inc b0 + */ +#define XDMAPS_CCR_SINGLE_BYTE (0x0) +#define XDMAPS_CCR_M2M_SINGLE_BYTE ((0x1 << 14) | 0x1) + + +/****************************************************************************/ +/** +* +* Construct the DMA program based on the descriptions of the DMA transfer. +* The function handles memory to memory DMA transfers. +* It also handles unalgined head and small amount of residue tail. +* +* @param Channel DMA channel number +* @param Cmd is the DMA command. +* @param CacheLength is the icache line length, in terms of bytes. +* If it's zero, the performance enhancement feature will be +* turned off. +* +* @returns The number of bytes for the program. +* +* @note None. +* +*****************************************************************************/ +static int XDmaPs_BuildDmaProg(unsigned Channel, XDmaPs_Cmd *Cmd, + unsigned CacheLength) +{ + /* + * unpack arguments + */ + char *DmaProgBuf = (char *)Cmd->GeneratedDmaProg; + unsigned DevChan = Channel; + unsigned long DmaLength = Cmd->BD.Length; + u32 SrcAddr = Cmd->BD.SrcAddr; + + unsigned SrcInc = Cmd->ChanCtrl.SrcInc; + u32 DstAddr = Cmd->BD.DstAddr; + unsigned DstInc = Cmd->ChanCtrl.DstInc; + + char *DmaProgStart = DmaProgBuf; + + unsigned int BurstBytes; + unsigned int LoopCount; + unsigned int LoopCount1 = 0; + unsigned int LoopResidue = 0; + unsigned int TailBytes; + unsigned int TailWords; + int DmaProgBytes; + u32 CCRValue; + unsigned int Unaligned; + unsigned int UnalignedCount; + unsigned int MemBurstSize = 1; + u32 MemAddr = 0; + unsigned int Index; + unsigned int SrcUnaligned = 0; + unsigned int DstUnaligned = 0; + + XDmaPs_ChanCtrl *ChanCtrl; + XDmaPs_ChanCtrl WordChanCtrl; + static XDmaPs_ChanCtrl Mem2MemByteCC; + + Mem2MemByteCC.EndianSwapSize = 0; + Mem2MemByteCC.DstCacheCtrl = 0; + Mem2MemByteCC.DstProtCtrl = 0; + Mem2MemByteCC.DstBurstLen = 1; + Mem2MemByteCC.DstBurstSize = 1; + Mem2MemByteCC.DstInc = 1; + Mem2MemByteCC.SrcCacheCtrl = 0; + Mem2MemByteCC.SrcProtCtrl = 0; + Mem2MemByteCC.SrcBurstLen = 1; + Mem2MemByteCC.SrcBurstSize = 1; + Mem2MemByteCC.SrcInc = 1; + + ChanCtrl = &Cmd->ChanCtrl; + + /* insert DMAMOV for SAR and DAR */ + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_SAR, + SrcAddr); + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_DAR, + DstAddr); + + + if (ChanCtrl->SrcInc) + SrcUnaligned = SrcAddr % ChanCtrl->SrcBurstSize; + + if (ChanCtrl->DstInc) + DstUnaligned = DstAddr % ChanCtrl->DstBurstSize; + + if ((SrcUnaligned && DstInc) || (DstUnaligned && SrcInc)) { + ChanCtrl = &Mem2MemByteCC; + } + + if (ChanCtrl->SrcInc) { + MemBurstSize = ChanCtrl->SrcBurstSize; + MemAddr = SrcAddr; + + } else if (ChanCtrl->DstInc) { + MemBurstSize = ChanCtrl->DstBurstSize; + MemAddr = DstAddr; + } + + /* check whether the head is aligned or not */ + Unaligned = MemAddr % MemBurstSize; + + if (Unaligned) { + /* if head is unaligned, transfer head in bytes */ + UnalignedCount = MemBurstSize - Unaligned; + CCRValue = XDMAPS_CCR_SINGLE_BYTE + | (SrcInc & 1) + | ((DstInc & 1) << 14); + + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + for (Index = 0; Index < UnalignedCount; Index++) { + DmaProgBuf += XDmaPs_Instr_DMALD(DmaProgBuf); + DmaProgBuf += XDmaPs_Instr_DMAST(DmaProgBuf); + } + + DmaLength -= UnalignedCount; + } + + /* now the burst transfer part */ + CCRValue = XDmaPs_ToCCRValue(ChanCtrl); + DmaProgBuf += XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + BurstBytes = ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen; + + LoopCount = DmaLength / BurstBytes; + TailBytes = DmaLength % BurstBytes; + + /* + * the loop count register is 8-bit wide, so if we need + * a larger loop, we need to have nested loops + */ + if (LoopCount > 256) { + LoopCount1 = LoopCount / 256; + if (LoopCount1 > 256) { + xil_printf("DMA operation cannot fit in a 2-level " + "loop for channel %d, please reduce the " + "DMA length or increase the burst size or " + "length", + Channel); + return 0; + } + LoopResidue = LoopCount % 256; + + if (LoopCount1 > 1) + DmaProgBuf += + XDmaPs_ConstructNestedLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCount1, + 256); + else + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + 256); + + /* there will be some that cannot be covered by + * nested loops + */ + LoopCount = LoopResidue; + } + + if (LoopCount > 0) { + DmaProgBuf += XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + LoopCount); + } + + if (TailBytes) { + /* handle the tail */ + TailWords = TailBytes / MemBurstSize; + TailBytes = TailBytes % MemBurstSize; + + if (TailWords) { + WordChanCtrl = *ChanCtrl; + /* + * if we can transfer the tail in words, we will + * transfer words as much as possible + */ + WordChanCtrl.SrcBurstSize = MemBurstSize; + WordChanCtrl.SrcBurstLen = 1; + WordChanCtrl.DstBurstSize = MemBurstSize; + WordChanCtrl.DstBurstLen = 1; + + + /* + * the burst length is 1 + */ + CCRValue = XDmaPs_ToCCRValue(&WordChanCtrl); + + DmaProgBuf += + XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + TailWords); + + } + + if (TailBytes) { + /* + * for the rest, we'll tranfer in bytes + */ + /* + * So far just to be safe, the tail bytes + * are transfered in a loop. We can optimize a little + * to perform a burst. + */ + CCRValue = XDMAPS_CCR_SINGLE_BYTE + | (SrcInc & 1) + | ((DstInc & 1) << 14); + + DmaProgBuf += + XDmaPs_Instr_DMAMOV(DmaProgBuf, + XDMAPS_MOV_CCR, + CCRValue); + + DmaProgBuf += + XDmaPs_ConstructSingleLoop(DmaProgStart, + CacheLength, + DmaProgBuf, + TailBytes); + + } + } + + DmaProgBuf += XDmaPs_Instr_DMASEV(DmaProgBuf, DevChan); + DmaProgBuf += XDmaPs_Instr_DMAEND(DmaProgBuf); + + DmaProgBytes = DmaProgBuf - DmaProgStart; + + Xil_DCacheFlushRange((u32)DmaProgStart, DmaProgBytes); + + return DmaProgBytes; + +} + + +/****************************************************************************/ +/** +* +* Generate a DMA program based for the DMA command, the buffer will be pointed +* by the GeneratedDmaProg field of the command. +* +* @param InstPtr is then DMA instance. +* @param Channel is the DMA channel number. +* @param Cmd is the DMA command. +* +* @return - XST_SUCCESS on success. +* - XST_FAILURE if it fails +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) +{ + void *Buf; + int ProgLen; + XDmaPs_ChannelData *ChanData; + XDmaPs_ChanCtrl *ChanCtrl; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + ChanData = InstPtr->Chans + Channel; + ChanCtrl = &Cmd->ChanCtrl; + + if (ChanCtrl->SrcBurstSize * ChanCtrl->SrcBurstLen + != ChanCtrl->DstBurstSize * ChanCtrl->DstBurstLen) { + return XST_FAILURE; + } + + + /* + * unaligned fixed address is not supported + */ + if (!ChanCtrl->SrcInc && Cmd->BD.SrcAddr % ChanCtrl->SrcBurstSize) { + return XST_FAILURE; + } + + if (!ChanCtrl->DstInc && Cmd->BD.DstAddr % ChanCtrl->DstBurstSize) { + return XST_FAILURE; + } + + Buf = XDmaPs_BufPool_Allocate(ChanData->ProgBufPool); + if (Buf == NULL) { + return XST_FAILURE; + } + + Cmd->GeneratedDmaProg = Buf; + ProgLen = XDmaPs_BuildDmaProg(Channel, Cmd, + InstPtr->CacheLength); + Cmd->GeneratedDmaProgLength = ProgLen; + + +#ifdef XDMAPS_DEBUG + XDmaPs_Print_DmaProg(Cmd); +#endif + + if (ProgLen <= 0) { + /* something wrong, release the buffer */ + XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf); + Cmd->GeneratedDmaProgLength = 0; + Cmd->GeneratedDmaProg = NULL; + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** + * Free the DMA program buffer that is pointed by the GeneratedDmaProg field + * of the command. + * + * @param InstPtr is then DMA instance. + * @param Channel is the DMA channel number. + * @param Cmd is the DMA command. + * + * @return XST_SUCCESS on success. + * XST_FAILURE if there is any error. + * + * @note None. + * + ****************************************************************************/ +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, XDmaPs_Cmd *Cmd) +{ + + void *Buf; + XDmaPs_ChannelData *ChanData; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return XST_FAILURE; + + Buf = (void *)Cmd->GeneratedDmaProg; + ChanData = InstPtr->Chans + Channel; + + if (Buf) { + XDmaPs_BufPool_Free(ChanData->ProgBufPool, Buf); + Cmd->GeneratedDmaProg = 0; + Cmd->GeneratedDmaProgLength = 0; + } + + return XST_SUCCESS; +} + + +/****************************************************************************/ +/** +* +* Start a DMA command. The command can only be invoked when the channel +* is idle. The driver takes the command, generates DMA program if needed, +* then pass the program to DMAC to execute. +* +* @param InstPtr is then DMA instance. +* @param Channel is the DMA channel number. +* @param Cmd is the DMA command. +* @param HoldDmaProg is tag indicating whether the driver can release +* the allocated DMA buffer or not. If a user wants to examine the +* generated DMA program, the flag should be set to 1. After the +* DMA program is finished, a user needs to explicity free the +* buffer. +* +* @return +* - XST_SUCCESS on success +* - XST_DEVICE_BUSY if DMA is busy +* - XST_FAILURE on other failures +* +* @note None. +* +****************************************************************************/ +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg) +{ + int Status; + u32 DmaProg = 0; + u32 Inten; + + Xil_AssertNonvoid(InstPtr != NULL); + Xil_AssertNonvoid(Cmd != NULL); + + + Cmd->DmaStatus = XST_FAILURE; + + if (XDmaPs_IsActive(InstPtr, Channel)) + return XST_DEVICE_BUSY; + + if (!Cmd->UserDmaProg && !Cmd->GeneratedDmaProg) { + Status = XDmaPs_GenDmaProg(InstPtr, Channel, Cmd); + if (Status) + return XST_FAILURE; + } + + InstPtr->Chans[Channel].HoldDmaProg = HoldDmaProg; + + if (Cmd->UserDmaProg) + DmaProg = (u32)Cmd->UserDmaProg; + else if (Cmd->GeneratedDmaProg) + DmaProg = (u32)Cmd->GeneratedDmaProg; + + if (DmaProg) { + /* enable the interrupt */ + Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET); + Inten |= 0x01 << Channel; /* set the correpsonding bit */ + XDmaPs_WriteReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET, + Inten); + Inten = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTEN_OFFSET); + + InstPtr->Chans[Channel].DmaCmdToHw = Cmd; + + if (Cmd->ChanCtrl.SrcInc) { + Xil_DCacheFlushRange(Cmd->BD.SrcAddr, Cmd->BD.Length); + } + if (Cmd->ChanCtrl.DstInc) { + Xil_DCacheInvalidateRange(Cmd->BD.DstAddr, + Cmd->BD.Length); + } + + Status = XDmaPs_Exec_DMAGO(InstPtr->Config.BaseAddress, + Channel, DmaProg); + } + else { + InstPtr->Chans[Channel].DmaCmdToHw = NULL; + Status = XST_FAILURE; + } + + return Status; +} + +/****************************************************************************/ +/** +* +* Checks whether the DMA channel is active or idle. +* +* @param InstPtr is the DMA instance. +* @param Channel is the DMA channel number. +* +* @return 0: if the channel is idle +* 1: otherwise +* +* @note None. +* +*****************************************************************************/ +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel) +{ + Xil_AssertNonvoid(InstPtr != NULL); + + /* Need to assert Channel is in range */ + if (Channel > XDMAPS_CHANNELS_PER_DEV) + return 0; + + return InstPtr->Chans[Channel].DmaCmdToHw != NULL; +} + + + +/****************************************************************************/ +/** +* +* Allocate a buffer of the DMA program buffer from the pool. +* +* @param Pool the DMA program pool. +* +* @return The allocated buffer, NULL if there is any error. +* +* @note None. +* +*****************************************************************************/ +static void *XDmaPs_BufPool_Allocate(XDmaPs_ProgBuf *Pool) +{ + int Index; + + Xil_AssertNonvoid(Pool != NULL); + + for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) { + if (!Pool[Index].Allocated) { + Pool[Index].Allocated = 1; + return Pool[Index].Buf; + } + } + + return NULL; + +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 0. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 0); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 1. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_1(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 1); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 2. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_2(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 2); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 3. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_3(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 3); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 4. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_4(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 4); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 5. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_5(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 5); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 6. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_6(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 6); +} + +/*****************************************************************************/ +/** +* +* Driver done interrupt service routine for channel 7. We need this done ISR +* mainly because the driver needs to release the DMA program buffer. +* This is the one that connects the GIC +* +* @param InstPtr is the DMA instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XDmaPs_DoneISR_7(XDmaPs *InstPtr) +{ + XDmaPs_DoneISR_n(InstPtr, 7); +} + +#ifndef XDMAPS_MAX_WAIT +#define XDMAPS_MAX_WAIT 4000 +#endif + +/****************************************************************************/ +/** +* Use the debug registers to kill the DMA thread. +* +* @param BaseAddr is DMA device base address. +* @param Channel is the DMA channel number. +* @param Thread is Debug thread encoding. +* 0: DMA manager thread, 1: DMA channel. +* +* @return 0 on success, -1 on time out +* +* @note None. +* +*****************************************************************************/ +static int XDmaPs_Exec_DMAKILL(u32 BaseAddr, + unsigned int Channel, + unsigned int Thread) +{ + u32 DbgInst0; + int WaitCount; + + DbgInst0 = XDmaPs_DBGINST0(0, 0x01, Channel, Thread); + + /* wait while debug status is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) + WaitCount++; + + if (WaitCount >= XDMAPS_MAX_WAIT) { + /* wait time out */ + xil_printf("PL330 device at %x debug status busy time out\n", + BaseAddr); + + return -1; + } + + /* write debug instruction 0 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0); + + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, 0); + + + /* run the command in DbgInst0 and DbgInst1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0); + + return 0; +} + +/****************************************************************************/ +/** +* +* +* Free a buffer of the DMA program buffer. +* @param Pool the DMA program pool. +* @param Buf the DMA program buffer to be release. +* +* @return None +* +* @note None. +* +*****************************************************************************/ +static void XDmaPs_BufPool_Free(XDmaPs_ProgBuf *Pool, void *Buf) +{ + int Index; + Xil_AssertVoid(Pool != NULL); + + for (Index = 0; Index < XDMAPS_MAX_CHAN_BUFS; Index++) { + if (Pool[Index].Buf == Buf) { + if (Pool[Index].Allocated) { + Pool[Index].Allocated = 0; + } + } + } +} + +/*****************************************************************************/ +/** +* XDmaPs_Exec_DMAGO - Execute the DMAGO to start a channel. +* +* @param BaseAddr PL330 device base address +* @param Channel Channel number for the device +* @param DmaProg DMA program starting address, this should be DMA address +* +* @return 0 on success, -1 on time out +* +* @note None. +* +****************************************************************************/ +static int XDmaPs_Exec_DMAGO(u32 BaseAddr, unsigned int Channel, u32 DmaProg) +{ + char DmaGoProg[8]; + u32 DbgInst0; + u32 DbgInst1; + + int WaitCount; + + XDmaPs_Instr_DMAGO(DmaGoProg, Channel, DmaProg, 0); + + DbgInst0 = XDmaPs_DBGINST0(*(DmaGoProg + 1), *DmaGoProg, 0, 0); + DbgInst1 = (u32)DmaProg; + + /* wait while debug status is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) { + + WaitCount++; + } + + if (WaitCount >= XDMAPS_MAX_WAIT) { + xil_printf("PL330 device at %x debug status busy time out\r\n", + BaseAddr); + return -1; + } + + /* write debug instruction 0 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST0_OFFSET, DbgInst0); + /* write debug instruction 1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGINST1_OFFSET, DbgInst1); + + + /* wait while the DMA Manager is busy */ + WaitCount = 0; + while ((XDmaPs_ReadReg(BaseAddr, + XDMAPS_DS_OFFSET) & XDMAPS_DS_DMA_STATUS) + != XDMAPS_DS_DMA_STATUS_STOPPED + && WaitCount <= XDMAPS_MAX_WAIT) { + WaitCount++; + } + + if (WaitCount >= XDMAPS_MAX_WAIT) { + xil_printf("PL330 device at %x debug status busy time out\r\n", + BaseAddr); + return -1; + } + + /* run the command in DbgInst0 and DbgInst1 */ + XDmaPs_WriteReg(BaseAddr, XDMAPS_DBGCMD_OFFSET, 0); + + return 0; +} + + +/****************************************************************************/ +/** +* +* It's the generic Done ISR. +* @param InstPtr is the DMA instance. +* @param Channel is the DMA channel numer. +* +* @return None.* +* +* @note None. +* +*****************************************************************************/ +static void XDmaPs_DoneISR_n(XDmaPs *InstPtr, unsigned Channel) +{ + + void *DmaProgBuf; + XDmaPs_ChannelData *ChanData; + XDmaPs_Cmd *DmaCmd; + //u32 Value; + + ChanData = InstPtr->Chans + Channel; + + /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTSTATUS_OFFSET);*/ + + /* clear the interrupt status */ + XDmaPs_WriteReg(InstPtr->Config.BaseAddress, + XDMAPS_INTCLR_OFFSET, + 1 << ChanData->ChanId); + + /*Value = XDmaPs_ReadReg(InstPtr->Config.BaseAddress, + XDMAPS_INTSTATUS_OFFSET);*/ + + + DmaCmd = ChanData->DmaCmdToHw; + if (DmaCmd) { + if (!ChanData->HoldDmaProg) { + DmaProgBuf = (void *)DmaCmd->GeneratedDmaProg; + if (DmaProgBuf) + XDmaPs_BufPool_Free(ChanData->ProgBufPool, + DmaProgBuf); + DmaCmd->GeneratedDmaProg = NULL; + } + + DmaCmd->DmaStatus = 0; + ChanData->DmaCmdToHw = NULL; + ChanData->DmaCmdFromHw = DmaCmd; + + if (ChanData->DoneHandler) + ChanData->DoneHandler(Channel, DmaCmd, + ChanData->DoneRef); + } + +} + + +/****************************************************************************/ +/** +* Prints the content of the buffer in bytes +* @param Buf is the buffer. +* @param Length is the length of the DMA program. +* +* @return None. +* +* @note None. +****************************************************************************/ +static void XDmaPs_Print_DmaProgBuf(char *Buf, int Length) +{ + int Index; + for (Index = 0; Index < Length; Index++) + xil_printf("[%x] %x\r\n", Index, Buf[Index]); + +} +/****************************************************************************/ +/** +* Print the Dma Prog Contents. +* +* @param Cmd is the command buffer. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ + void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd) +{ + if (Cmd->GeneratedDmaProg && Cmd->GeneratedDmaProgLength) { + xil_printf("Generated DMA program (%d):\r\n", + Cmd->GeneratedDmaProgLength); + XDmaPs_Print_DmaProgBuf((char *)Cmd->GeneratedDmaProg, + Cmd->GeneratedDmaProgLength); + } + + if (Cmd->UserDmaProg && Cmd->UserDmaProgLength) { + xil_printf("User defined DMA program (%d):\r\n", + Cmd->UserDmaProgLength); + XDmaPs_Print_DmaProgBuf((char *)Cmd->UserDmaProg, + Cmd->UserDmaProgLength); + } +} + + +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h new file mode 100644 index 0000000..5a0c1a2 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h @@ -0,0 +1,352 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps.h +* @addtogroup dmaps_v2_3 +* @{ +* @details +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	hbm    08/19/10 First Release
+* 1.01a nm     12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		        the maximum number of channels.
+*		        Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                       with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h.
+*			Added the tcl file to automatically generate the
+*			xparameters.h
+* 1.02a sg     05/16/12 Made changes for doxygen and moved some function
+*			header from the xdmaps.h file to xdmaps.c file
+*			Other cleanup for coding guidelines and CR 657109
+*			and CR 657898
+*			The xdmaps_example_no_intr.c example is removed
+*			as it is using interrupts  and is similar to
+*			the interrupt example - CR 652477
+* 1.03a sg     07/16/2012 changed inline to __inline for CR665681
+* 1.04a nm     10/22/2012 Fixed CR# 681671.
+* 1.05a nm     04/15/2013 Fixed CR# 704396. Removed warnings when compiled
+*			  with -Wall and -Wextra option in bsp.
+*	       05/01/2013 Fixed CR# 700189. Changed XDmaPs_BuildDmaProg()
+*			  function description.
+*			  Fixed CR# 704396. Removed unused variables
+*			  UseM2MByte & MemBurstLen from XDmaPs_BuildDmaProg()
+*			  function.
+* 1.07a asa    11/02/13. Made changes to fix compilation issues for iarcc.
+*			   Removed the PDBG prints. By default they were always
+*			   defined out and never used. The PDBG is non-standard for
+*			   Xilinx drivers and no other driver does something similar.
+*			   Since there is no easy way to fix compilation issues with
+*			   the IARCC compiler around PDBG, it is better to remove it.
+*			   Users can always use xil_printfs if they want to debug.
+* 2.0   adk    10/12/13  Updated as per the New Tcl API's
+* 2.01  kpc    08/23/14  Fixed the IAR compiler reported errors
+* 2.2   mus    08/12/16  Declared all inline functions in xdmaps.c as extern, to avoid
+*                        linker error for IAR compiler
+* 2.3   ms     01/23/17 Modified xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*
    +* +*****************************************************************************/ + +#ifndef XDMAPS_H /* prevent circular inclusions */ +#define XDMAPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xparameters.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" + +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of device (IPIF) */ +} XDmaPs_Config; + + +/** DMA channle control structure. It's for AXI bus transaction. + * This struct will be translated into a 32-bit channel control register value. + */ +typedef struct { + unsigned int EndianSwapSize; /**< Endian swap size. */ + unsigned int DstCacheCtrl; /**< Destination cache control */ + unsigned int DstProtCtrl; /**< Destination protection control */ + unsigned int DstBurstLen; /**< Destination burst length */ + unsigned int DstBurstSize; /**< Destination burst size */ + unsigned int DstInc; /**< Destination incrementing or fixed + * address */ + unsigned int SrcCacheCtrl; /**< Source cache control */ + unsigned int SrcProtCtrl; /**< Source protection control */ + unsigned int SrcBurstLen; /**< Source burst length */ + unsigned int SrcBurstSize; /**< Source burst size */ + unsigned int SrcInc; /**< Source incrementing or fixed + * address */ +} XDmaPs_ChanCtrl; + +/** DMA block descriptor stucture. + */ +typedef struct { + u32 SrcAddr; /**< Source starting address */ + u32 DstAddr; /**< Destination starting address */ + unsigned int Length; /**< Number of bytes for the block */ +} XDmaPs_BD; + +/** + * A DMA command consisits of a channel control struct, a block descriptor, + * a user defined program, a pointer pointing to generated DMA program, and + * execution result. + * + */ +typedef struct { + XDmaPs_ChanCtrl ChanCtrl; /**< Channel Control Struct */ + XDmaPs_BD BD; /**< Together with SgLength field, + * it's a scatter-gather list. + */ + void *UserDmaProg; /**< If user wants the driver to + * execute their own DMA program, + * this field points to the DMA + * program. + */ + int UserDmaProgLength; /**< The length of user defined + * DMA program. + */ + + void *GeneratedDmaProg; /**< The DMA program genreated + * by the driver. This field will be + * set if a user invokes the DMA + * program generation function. Or + * the DMA command is finished and + * a user informs the driver not to + * release the program buffer. + * This field has two purposes, one + * is to ask the driver to generate + * a DMA program while the DMAC is + * performaning DMA transactions. The + * other purpose is to debug the + * driver. + */ + int GeneratedDmaProgLength; /**< The length of the DMA program + * generated by the driver + */ + int DmaStatus; /**< 0 on success, otherwise error code + */ + u32 ChanFaultType; /**< Channel fault type in case of fault + */ + u32 ChanFaultPCAddr; /**< Channel fault PC address + */ +} XDmaPs_Cmd; + +/** + * It's the done handler a user can set for a channel + */ +typedef void (*XDmaPsDoneHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +/** + * It's the fault handler a user can set for a channel + */ +typedef void (*XDmaPsFaultHandler) (unsigned int Channel, + XDmaPs_Cmd *DmaCmd, + void *CallbackRef); + +#define XDMAPS_MAX_CHAN_BUFS 2 +#define XDMAPS_CHAN_BUF_LEN 128 + +/** + * The XDmaPs_ProgBuf is the struct for a DMA program buffer. + */ +typedef struct { + char Buf[XDMAPS_CHAN_BUF_LEN]; /**< The actual buffer the holds the + * content */ + unsigned Len; /**< The actual length of the DMA + * program in bytes. */ + int Allocated; /**< A tag indicating whether the + * buffer is allocated or not */ +} XDmaPs_ProgBuf; + +/** + * The XDmaPs_ChannelData is a struct to book keep individual channel of + * the DMAC. + */ +typedef struct { + unsigned DevId; /**< Device id indicating which DMAC */ + unsigned ChanId; /**< Channel number of the DMAC */ + XDmaPs_ProgBuf ProgBufPool[XDMAPS_MAX_CHAN_BUFS]; /**< A pool of + program buffers*/ + XDmaPsDoneHandler DoneHandler; /**< Done interrupt handler */ + void *DoneRef; /**< Done interrupt callback data */ + XDmaPs_Cmd *DmaCmdToHw; /**< DMA command being executed */ + XDmaPs_Cmd *DmaCmdFromHw; /**< DMA command that is finished. + * This field is for debugging purpose + */ + int HoldDmaProg; /**< A tag indicating whether to hold the + * DMA program after the DMA is done. + */ + +} XDmaPs_ChannelData; + +/** + * The XDmaPs driver instance data structure. A pointer to an instance data + * structure is passed around by functions to refer to a specific driver + * instance. + */ +typedef struct { + XDmaPs_Config Config; /**< Configuration data structure */ + int IsReady; /**< Device is Ready */ + int CacheLength; /**< icache length */ + XDmaPsFaultHandler FaultHandler; /**< fault interrupt handler */ + void *FaultRef; /**< fault call back data */ + XDmaPs_ChannelData Chans[XDMAPS_CHANNELS_PER_DEV]; + /**< + * channel data + */ +} XDmaPs; + +/* + * Functions implemented in xdmaps.c + */ +int XDmaPs_CfgInitialize(XDmaPs *InstPtr, + XDmaPs_Config *Config, + u32 EffectiveAddr); + +int XDmaPs_Start(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd, + int HoldDmaProg); + +int XDmaPs_IsActive(XDmaPs *InstPtr, unsigned int Channel); +int XDmaPs_GenDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +int XDmaPs_FreeDmaProg(XDmaPs *InstPtr, unsigned int Channel, + XDmaPs_Cmd *Cmd); +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + + +int XDmaPs_ResetManager(XDmaPs *InstPtr); +int XDmaPs_ResetChannel(XDmaPs *InstPtr, unsigned int Channel); + + +int XDmaPs_SetDoneHandler(XDmaPs *InstPtr, + unsigned Channel, + XDmaPsDoneHandler DoneHandler, + void *CallbackRef); + +int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, + XDmaPsFaultHandler FaultHandler, + void *CallbackRef); + +void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); + +/** + * To avoid linking error,Declare all inline functions as extern for + * IAR compiler + */ +#ifdef __ICCARM__ +extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg); +extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src); +extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns); +extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations); +extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc); +extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm); +extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber); +extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg); +extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize); +extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize); +#endif + +/** + * Driver done interrupt service routines for the channels. + * We need this done ISR mainly because the driver needs to release the + * DMA program buffer. This is the one that connects the GIC + */ +void XDmaPs_DoneISR_0(XDmaPs *InstPtr); +void XDmaPs_DoneISR_1(XDmaPs *InstPtr); +void XDmaPs_DoneISR_2(XDmaPs *InstPtr); +void XDmaPs_DoneISR_3(XDmaPs *InstPtr); +void XDmaPs_DoneISR_4(XDmaPs *InstPtr); +void XDmaPs_DoneISR_5(XDmaPs *InstPtr); +void XDmaPs_DoneISR_6(XDmaPs *InstPtr); +void XDmaPs_DoneISR_7(XDmaPs *InstPtr); + +/** + * Driver fault interrupt service routine + */ +void XDmaPs_FaultISR(XDmaPs *InstPtr); + + +/* + * Static loopup function implemented in xdmaps_sinit.c + */ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId); + + +/* + * self-test functions in xdmaps_selftest.c + */ +int XDmaPs_SelfTest(XDmaPs *InstPtr); + + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c new file mode 100644 index 0000000..bab1556 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c @@ -0,0 +1,59 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xdmaps.h" + +/* +* The configuration table for devices +*/ + +XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] = +{ + { + XPAR_PS7_DMA_NS_DEVICE_ID, + XPAR_PS7_DMA_NS_BASEADDR + }, + { + XPAR_PS7_DMA_S_DEVICE_ID, + XPAR_PS7_DMA_S_BASEADDR + } +}; + + diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c new file mode 100644 index 0000000..4c0cfbf --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c @@ -0,0 +1,116 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_hw.c +* @addtogroup dmaps_v2_3 +* @{ +* +* This file contains the implementation of the interface reset functionality +* for XDmaPs driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  	Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.06a kpc 10/07/13 First release
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ +#include "xdmaps_hw.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ +#ifndef XDMAPS_MAX_WAIT +#define XDMAPS_MAX_WAIT 4000 +#endif +/************************** Function Prototypes *****************************/ + +/************************** Variable Definitions ****************************/ + +/*****************************************************************************/ +/** +* This function perform the reset sequence to the given dmaps interface by +* configuring the appropriate control bits in the dmaps specifc registers +* the dmaps reset squence involves the following steps +* Disable all the interuupts +* Clear the pending interrupts +* Kill all the active channel threads +* Kill the manager thread +* +* @param BaseAddress of the interface +* +* @return N/A +* +* @note +* This function will not modify the slcr registers that are relavant for +* dmaps controller +******************************************************************************/ +void XDmaPs_ResetHw(u32 BaseAddress) +{ + u32 DbgInst; + u32 WaitCount = 0; + u32 ChanIndex; + + /* Disable all the interrupts */ + XDmaPs_WriteReg(BaseAddress, XDMAPS_INTEN_OFFSET, 0x00); + /* Clear the interrupts */ + XDmaPs_WriteReg(BaseAddress, XDMAPS_INTCLR_OFFSET, XDMAPS_INTCLR_ALL_MASK); + /* Kill the dma channel threads */ + for (ChanIndex=0; ChanIndex < XDMAPS_CHANNELS_PER_DEV; ChanIndex++) { + while ((XDmaPs_ReadReg(BaseAddress, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + && (WaitCount < XDMAPS_MAX_WAIT)) + WaitCount++; + + DbgInst = XDmaPs_DBGINST0(0, 0x01, ChanIndex, 1); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0); + } + /* Kill the manager thread */ + DbgInst = XDmaPs_DBGINST0(0, 0x01, 0, 0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST0_OFFSET, DbgInst); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGINST1_OFFSET, 0x0); + XDmaPs_WriteReg(BaseAddress, XDMAPS_DBGCMD_OFFSET, 0x0); +} + + + +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h new file mode 100644 index 0000000..628f1ec --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h @@ -0,0 +1,293 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xdmaps_hw.h +* @addtogroup dmaps_v2_3 +* @{ +* +* This header file contains the hardware interface of an XDmaPs device. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who   Date     Changes
+* ----- ----  -------- ----------------------------------------------
+* 1.00a	hbm   08/18/10 First Release
+* 1.01a nm    12/20/12 Added definition XDMAPS_CHANNELS_PER_DEV which specifies
+*		       the maximum number of channels.
+*		       Replaced the usage of XPAR_XDMAPS_CHANNELS_PER_DEV
+*                      with XDMAPS_CHANNELS_PER_DEV defined in xdmaps_hw.h
+* 1.02a sg    05/16/12 Made changes for doxygen
+* 1.06a kpc   07/10/13 Added function prototype
+*
    +* +******************************************************************************/ + +#ifndef XDMAPS_HW_H /* prevent circular inclusions */ +#define XDMAPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register Map + * + * Register offsets for the DMAC. + * @{ + */ + +#define XDMAPS_DS_OFFSET 0x000 /* DMA Status Register */ +#define XDMAPS_DPC_OFFSET 0x004 /* DMA Program Counter Rregister */ +#define XDMAPS_INTEN_OFFSET 0X020 /* DMA Interrupt Enable Register */ +#define XDMAPS_ES_OFFSET 0x024 /* DMA Event Status Register */ +#define XDMAPS_INTSTATUS_OFFSET 0x028 /* DMA Interrupt Status Register + */ +#define XDMAPS_INTCLR_OFFSET 0x02c /* DMA Interrupt Clear Register */ +#define XDMAPS_FSM_OFFSET 0x030 /* DMA Fault Status DMA Manager + * Register + */ +#define XDMAPS_FSC_OFFSET 0x034 /* DMA Fault Status DMA Chanel Register + */ +#define XDMAPS_FTM_OFFSET 0x038 /* DMA Fault Type DMA Manager Register */ + +#define XDMAPS_FTC0_OFFSET 0x040 /* DMA Fault Type for DMA Channel 0 */ +/* + * The offset for the rest of the FTC registers is calculated as + * FTC0 + dev_chan_num * 4 + */ +#define XDmaPs_FTCn_OFFSET(ch) (XDMAPS_FTC0_OFFSET + (ch) * 4) + +#define XDMAPS_CS0_OFFSET 0x100 /* Channel Status for DMA Channel 0 */ +/* + * The offset for the rest of the CS registers is calculated as + * CS0 + * dev_chan_num * 0x08 + */ +#define XDmaPs_CSn_OFFSET(ch) (XDMAPS_CS0_OFFSET + (ch) * 8) + +#define XDMAPS_CPC0_OFFSET 0x104 /* Channel Program Counter for DMA + * Channel 0 + */ +/* + * The offset for the rest of the CPC registers is calculated as + * CPC0 + dev_chan_num * 0x08 + */ +#define XDmaPs_CPCn_OFFSET(ch) (XDMAPS_CPC0_OFFSET + (ch) * 8) + +#define XDMAPS_SA_0_OFFSET 0x400 /* Source Address Register for DMA + * Channel 0 + */ +/* The offset for the rest of the SA registers is calculated as + * SA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_SA_n_OFFSET(ch) (XDMAPS_SA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DA_0_OFFSET 0x404 /* Destination Address Register for + * DMA Channel 0 + */ +/* The offset for the rest of the DA registers is calculated as + * DA_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_DA_n_OFFSET(ch) (XDMAPS_DA_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_CC_0_OFFSET 0x408 /* Channel Control Register for + * DMA Channel 0 + */ +/* + * The offset for the rest of the CC registers is calculated as + * CC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_CC_n_OFFSET(ch) (XDMAPS_CC_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_LC0_0_OFFSET 0x40C /* Loop Counter 0 for DMA Channel 0 */ +/* + * The offset for the rest of the LC0 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC0_n_OFFSET(ch) (XDMAPS_LC0_0_OFFSET + (ch) * 0x20) +#define XDMAPS_LC1_0_OFFSET 0x410 /* Loop Counter 1 for DMA Channel 0 */ +/* + * The offset for the rest of the LC1 registers is calculated as + * LC_0 + dev_chan_num * 0x20 + */ +#define XDmaPs_LC1_n_OFFSET(ch) (XDMAPS_LC1_0_OFFSET + (ch) * 0x20) + +#define XDMAPS_DBGSTATUS_OFFSET 0xD00 /* Debug Status Register */ +#define XDMAPS_DBGCMD_OFFSET 0xD04 /* Debug Command Register */ +#define XDMAPS_DBGINST0_OFFSET 0xD08 /* Debug Instruction 0 Register */ +#define XDMAPS_DBGINST1_OFFSET 0xD0C /* Debug Instruction 1 Register */ + +#define XDMAPS_CR0_OFFSET 0xE00 /* Configuration Register 0 */ +#define XDMAPS_CR1_OFFSET 0xE04 /* Configuration Register 1 */ +#define XDMAPS_CR2_OFFSET 0xE08 /* Configuration Register 2 */ +#define XDMAPS_CR3_OFFSET 0xE0C /* Configuration Register 3 */ +#define XDMAPS_CR4_OFFSET 0xE10 /* Configuration Register 4 */ +#define XDMAPS_CRDN_OFFSET 0xE14 /* Configuration Register Dn */ + +#define XDMAPS_PERIPH_ID_0_OFFSET 0xFE0 /* Peripheral Identification + * Register 0 + */ +#define XDMAPS_PERIPH_ID_1_OFFSET 0xFE4 /* Peripheral Identification + * Register 1 + */ +#define XDMAPS_PERIPH_ID_2_OFFSET 0xFE8 /* Peripheral Identification + * Register 2 + */ +#define XDMAPS_PERIPH_ID_3_OFFSET 0xFEC /* Peripheral Identification + * Register 3 + */ +#define XDMAPS_PCELL_ID_0_OFFSET 0xFF0 /* PrimeCell Identification + * Register 0 + */ +#define XDMAPS_PCELL_ID_1_OFFSET 0xFF4 /* PrimeCell Identification + * Register 1 + */ +#define XDMAPS_PCELL_ID_2_OFFSET 0xFF8 /* PrimeCell Identification + * Register 2 + */ +#define XDMAPS_PCELL_ID_3_OFFSET 0xFFC /* PrimeCell Identification + * Register 3 + */ + +/* + * Some useful register masks + */ +#define XDMAPS_DS_DMA_STATUS 0x0F /* DMA status mask */ +#define XDMAPS_DS_DMA_STATUS_STOPPED 0x00 /* debug status busy mask */ + +#define XDMAPS_DBGSTATUS_BUSY 0x01 /* debug status busy mask */ + +#define XDMAPS_CS_ACTIVE_MASK 0x07 /* channel status active mask, + * llast 3 bits of CS register + */ + +#define XDMAPS_CR1_I_CACHE_LEN_MASK 0x07 /* i_cache_len mask */ + + +/* + * XDMAPS_DBGINST0 - constructs the word for the Debug Instruction-0 Register. + * @b1: Instruction byte 1 + * @b0: Instruction byte 0 + * @ch: Channel number + * @dbg_th: Debug thread encoding: 0 = DMA manager thread, 1 = DMA channel + */ +#define XDmaPs_DBGINST0(b1, b0, ch, dbg_th) \ + (((b1) << 24) | ((b0) << 16) | (((ch) & 0x7) << 8) | ((dbg_th & 0x1))) + +/* @} */ + +/** @name Control Register + * + * The Control register (CR) controls the major functions of the device. + * + * Control Register Bit Definition + */ + +/* @}*/ + + +#define XDMAPS_CHANNELS_PER_DEV 8 + + +/** @name Mode Register + * + * The mode register (MR) defines the mode of transfer as well as the data + * format. If this register is modified during transmission or reception, + * data validity cannot be guaranteed. + * + * Mode Register Bit Definition + * @{ + */ + +/* @} */ + + +/** @name Interrupt Registers + * + * Interrupt control logic uses the interrupt enable register (IER) and the + * interrupt disable register (IDR) to set the value of the bits in the + * interrupt mask register (IMR). The IMR determines whether to pass an + * interrupt to the interrupt status register (ISR). + * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an + * interrupt. IMR and ISR are read only, and IER and IDR are write only. + * Reading either IER or IDR returns 0x00. + * + * All four registers have the same bit definitions. + * + * @{ + */ + +/* @} */ +#define XDMAPS_INTCLR_ALL_MASK 0xFF + +#define XDmaPs_ReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/***************************************************************************/ +/** +* Write a DMAC register. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset contains the offset from the base address of the device. +* @param RegisterValue is the value to be written to the register. +* +* @return None. +* +* @note +* C-Style signature: +* void XDmaPs_WriteReg(u32 BaseAddress, int RegOffset, +* u32 RegisterValue) +******************************************************************************/ +#define XDmaPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \ + Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue)) +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes *****************************/ +/* + * Perform reset operation to the dmaps interface + */ +void XDmaPs_ResetHw(u32 BaseAddr); +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c new file mode 100644 index 0000000..daebd99 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c @@ -0,0 +1,110 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_selftest.c +* @addtogroup dmaps_v2_3 +* @{ +* +* This file contains the self-test functions for the XDmaPs driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	hbm 	03/29/2010 First Release
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xdmaps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + + +/****************************************************************************/ +/** +* +* This function runs a self-test on the driver and hardware device. This self +* test performs a local loopback and verifies data can be sent and received. +* +* The time for this test is proportional to the baud rate that has been set +* prior to calling this function. +* +* The mode and control registers are restored before return. +* +* @param InstPtr is a pointer to the XDmaPs instance +* +* @return +* +* - XST_SUCCESS if the test was successful +* - XST_FAILURE if the test failed +* +* @note +* +* This function can hang if the hardware is not functioning properly. +* +******************************************************************************/ +int XDmaPs_SelfTest(XDmaPs *InstPtr) +{ + u32 BaseAddr = InstPtr->Config.BaseAddress; + int i; + + if (XDmaPs_ReadReg(BaseAddr, XDMAPS_DBGSTATUS_OFFSET) + & XDMAPS_DBGSTATUS_BUSY) + return XST_FAILURE; + + for (i = 0; i < XDMAPS_CHANNELS_PER_DEV; i++) { + if (XDmaPs_ReadReg(BaseAddr, + XDmaPs_CSn_OFFSET(i))) + return XST_FAILURE; + } + return XST_SUCCESS; +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c new file mode 100644 index 0000000..b92ee53 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* +* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xdmaps_sinit.c +* @addtogroup dmaps_v2_3 +* @{ +* +* The implementation of the XDmaPs driver's static initialzation +* functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00  hbm  08/13/10 First Release
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xstatus.h" +#include "xparameters.h" +#include "xdmaps.h" + +/************************** Constant Definitions ****************************/ + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Variable Definitions ****************************/ +extern XDmaPs_Config XDmaPs_ConfigTable[]; + +/************************** Function Prototypes *****************************/ + +/****************************************************************************/ +/** +* +* Looks up the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId contains the ID of the device +* +* @return +* +* A pointer to the configuration structure or NULL if the specified device +* is not in the system. +* +* @note +* +* None. +* +******************************************************************************/ +XDmaPs_Config *XDmaPs_LookupConfig(u16 DeviceId) +{ + XDmaPs_Config *CfgPtr = NULL; + + int i; + + for (i = 0; i < XPAR_XDMAPS_NUM_INSTANCES; i++) { + if (XDmaPs_ConfigTable[i].DeviceId == DeviceId) { + CfgPtr = &XDmaPs_ConfigTable[i]; + break; + } + } + + return CfgPtr; +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c new file mode 100644 index 0000000..c013c49 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c @@ -0,0 +1,492 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps.c +* @addtogroup emacps_v3_7 +* @{ +* +* The XEmacPs driver. Functions in this file are the minimum required functions +* for this driver. See xemacps.h for a detailed description of the driver. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1  srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+*		      64-bit changes.
+* 3.00 kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
+*                    Disable extended mode. Perform all 64 bit changes under
+*                    check for arch64.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5  hk   08/14/17 Update cache coherency information of the interface in
+*                    its config structure.
+*
+*
    +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xemacps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +void XEmacPs_StubHandler(void); /* Default handler routine */ + +/************************** Variable Definitions *****************************/ + + +/*****************************************************************************/ +/** +* Initialize a specific XEmacPs instance/driver. The initialization entails: +* - Initialize fields of the XEmacPs instance structure +* - Reset hardware and apply default options +* - Configure the DMA channels +* +* The PHY is setup independently from the device. Use the MII or whatever other +* interface may be present for setup. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param CfgPtr is the device configuration structure containing required +* hardware build data. +* @param EffectiveAddress is the base address of the device. If address +* translation is not utilized, this parameter can be passed in using +* CfgPtr->Config.BaseAddress to specify the physical base address. +* +* @return +* - XST_SUCCESS if initialization was successful +* +******************************************************************************/ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr, + UINTPTR EffectiveAddress) +{ + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + + /* Set device base address and ID */ + InstancePtr->Config.DeviceId = CfgPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddress; + InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent; + + /* Set callbacks to an initial stub routine */ + InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler)); + InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler); + InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler); + + /* Reset the hardware and set default options */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + XEmacPs_Reset(InstancePtr); + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** +* Start the Ethernet controller as follows: +* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set +* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set +* - Start the SG DMA send and receive channels and enable the device +* interrupt +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return N/A +* +* @note +* Hardware is configured with scatter-gather DMA, the driver expects to start +* the scatter-gather channels and expects that the user has previously set up +* the buffer descriptor lists. +* +* This function makes use of internal resources that are shared between the +* Start, Stop, and Set/ClearOptions functions. So if one task might be setting +* device options while another is trying to start the device, the user is +* required to provide protection of this shared data (typically using a +* semaphore). +* +* This function must not be preempted by an interrupt that may service the +* device. +* +******************************************************************************/ +void XEmacPs_Start(XEmacPs *InstancePtr) +{ + u32 Reg; + + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Start DMA */ + /* When starting the DMA channels, both transmit and receive sides + * need an initialized BD list. + */ + if (InstancePtr->Version == 2) { + Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0); + Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + InstancePtr->RxBdRing.BaseBdAddr); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + InstancePtr->TxBdRing.BaseBdAddr); + } + + /* clear any existed int status */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Enable transmitter if not already enabled */ + if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK); + } + } + + /* Enable receiver if not already enabled */ + if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK); + } + } + + /* Enable TX and RX interrupts */ + XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK | + XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK | + (u32)XEMACPS_IXR_TXCOMPL_MASK)); + + /* Enable TX Q1 Interrupts */ + if (InstancePtr->Version > 2) + XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK); + + /* Mark as started */ + InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; + + return; +} + + +/*****************************************************************************/ +/** +* Gracefully stop the Ethernet MAC as follows: +* - Disable all interrupts from this device +* - Stop DMA channels +* - Disable the tansmitter and receiver +* +* Device options currently in effect are not changed. +* +* This function will disable all interrupts. Default interrupts settings that +* had been enabled will be restored when XEmacPs_Start() is called. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @note +* This function makes use of internal resources that are shared between the +* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be +* setting device options while another is trying to start the device, the user +* is required to provide protection of this shared data (typically using a +* semaphore). +* +* Stopping the DMA channels causes this function to block until the DMA +* operation is complete. +* +******************************************************************************/ +void XEmacPs_Stop(XEmacPs *InstancePtr) +{ + u32 Reg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Disable all interrupts */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Disable the receiver & transmitter */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK); + Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Mark as stopped */ + InstancePtr->IsStarted = 0U; +} + + +/*****************************************************************************/ +/** +* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the +* transmitter, and the receiver. +* +* Steps to reset +* - Stops transmit and receive channels +* - Stops DMA +* - Configure transmit and receive buffer size to default +* - Clear transmit and receive status register and counters +* - Clear all interrupt sources +* - Clear phy (if there is any previously detected) address +* - Clear MAC addresses (1-4) as well as Type IDs and hash value +* +* All options are placed in their default state. Any frames in the +* descriptor lists will remain in the lists. The side effect of doing +* this is that after a reset and following a restart of the device, frames +* were in the list before the reset may be transmitted or received. +* +* The upper layer software is responsible for re-configuring (if necessary) +* and restarting the MAC after the reset. Note also that driver statistics +* are not cleared on reset. It is up to the upper layer software to clear the +* statistics if needed. +* +* When a reset is required, the driver notifies the upper layer software of +* this need through the ErrorHandler callback and specific status codes. +* The upper layer software is responsible for calling this Reset function +* and then re-configuring the device. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +******************************************************************************/ +void XEmacPs_Reset(XEmacPs *InstancePtr) +{ + u32 Reg; + u8 i; + s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Stop the device and reset hardware */ + XEmacPs_Stop(InstancePtr); + InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS; + + InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC); + + InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF; + + InstancePtr->MaxMtuSize = XEMACPS_MTU; + InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE + + XEMACPS_TRL_SIZE; + InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize + + XEMACPS_HDR_VLAN_SIZE; + InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK; + + /* Setup hardware with default values */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + (XEMACPS_NWCTRL_STATCLR_MASK | + XEMACPS_NWCTRL_MDEN_MASK) & + (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK)); + + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCFG_OFFSET); + Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK; + + Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK | + (u32)XEMACPS_NWCFG_FDEN_MASK | + (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK; + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCFG_OFFSET, Reg); + if (InstancePtr->Version > 2) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET, + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) | + XEMACPS_NWCFG_DWIDTH_64_MASK)); + } + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_DMACR_OFFSET, + (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) + + (((((u32)XEMACPS_RX_BUF_SIZE % + (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) << + (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) & + (u32)(XEMACPS_DMACR_RXBUF_MASK)) | + (u32)XEMACPS_DMACR_RXSIZE_MASK | + (u32)XEMACPS_DMACR_TXSIZE_MASK); + + + /* Single bursts */ + /* FIXME: Why Single bursts? */ + if (InstancePtr->Version > 2) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) | +#ifdef __aarch64__ + (u32)XEMACPS_DMACR_ADDR_WIDTH_64 | +#endif + (u32)XEMACPS_DMACR_INCR16_AHB_BURST)); + } + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXSR_OFFSET, 0x0U); + + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND); + if (InstancePtr->Version > 2) + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND); + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXSR_OFFSET, 0x0U); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_ISR_OFFSET); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + Reg); + + XEmacPs_ClearHash(InstancePtr); + + for (i = 1U; i < 5U; i++) { + (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i); + (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i); + } + + /* clear all counters */ + for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U); + i++) { + (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4))); + } + + /* Disable the receiver */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Sync default options with hardware but leave receiver and + * transmitter disabled. They get enabled with XEmacPs_Start() if + * XEMACPS_TRANSMITTER_ENABLE_OPTION and + * XEMACPS_RECEIVER_ENABLE_OPTION are set. + */ + (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options & + ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | + (u32)XEMACPS_RECEIVER_ENABLE_OPTION)); + + (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options); +} + + +/******************************************************************************/ +/** + * This is a stub for the asynchronous callbacks. The stub is here in case the + * upper layer forgot to set the handler(s). On initialization, all handlers are + * set to this callback. It is considered an error for this handler to be + * invoked. + * + ******************************************************************************/ +void XEmacPs_StubHandler(void) +{ + Xil_AssertVoidAlways(); +} + +/*****************************************************************************/ +/** +* This function sets the start address of the transmit/receive buffer queue. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @QPtr Address of the Queue to be written +* @QueueNum Buffer Queue Index +* @Direction Transmit/Recive +* +* @note +* The buffer queue addresses has to be set before starting the transfer, so +* this function has to be called in prior to XEmacPs_Start() +* +******************************************************************************/ +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction) +{ + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* If already started, then there is nothing to do */ + if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) { + return; + } + + if (QueueNum == 0x00U) { + if (Direction == XEMACPS_SEND) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } else { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } + } + else { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQ1BASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } +#ifdef __aarch64__ + if (Direction == XEMACPS_SEND) { + /* Set the MSB of TX Queue start address */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_MSBBUF_TXQBASE_OFFSET, + (u32)((QPtr & ULONG64_HI_MASK) >> 32U)); + } else { + /* Set the MSB of RX Queue start address */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_MSBBUF_RXQBASE_OFFSET, + (u32)((QPtr & ULONG64_HI_MASK) >> 32U)); + } +#endif +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h new file mode 100644 index 0000000..6d4b15b --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h @@ -0,0 +1,809 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h +* @addtogroup emacps_v3_7 +* @{ +* @details + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+ *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4   ms   01/23/17 Modified xil_printf statement in main function for all
+ *                     examples to ensure that "Successfully ran" and "Failed"
+ *                     strings are available in all examples. This is a fix
+ *                     for CR-965028.
+ *       ms   03/17/17 Modified text file in examples folder for doxygen
+ *                     generation.
+ *       ms   04/05/17 Added tabspace for return statements in functions of
+ *                     xemacps_ieee1588_example.c for proper documentation
+ *                     while generating doxygen.
+ * 3.5   hk   08/14/17 Update cache coherency information of the interface in
+ *                     its config structure.
+ * 3.6   rb   09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ *		       changed to volatile.
+ *		       Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *
+ *
    + * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001U +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002U +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004U +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020U +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040U +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400U +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800U +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U +#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U + +#define XEMACPS_DEFAULT_OPTIONS \ + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1U +#define XEMACPS_HANDLER_DMARECV 2U +#define XEMACPS_HANDLER_ERROR 3U +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ + +#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ +#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 0x00000001 +#define XEMACPS_4BYTE_BURST 0x00000004 +#define XEMACPS_8BYTE_BURST 0x00000008 +#define XEMACPS_16BYTE_BURST 0x00000010 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ + u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; + * describes whether Cache Coherent or not */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs_Instance { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + u32 Version; + u32 RxBufMask; + u32 MaxMtuSize; + u32 MaxFrameSize; + u32 MaxVlanFrameSize; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + UINTPTR EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPointer, void *CallBackRef); +void XEmacPs_IntrHandler(void *XEmacPsPtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h new file mode 100644 index 0000000..83f9a87 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h @@ -0,0 +1,804 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h +* @addtogroup emacps_v3_7 +* @{ + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ * 3.2   hk   11/18/15 Change BD typedef and number of words.
+ *
+ *
    + * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ +#ifdef __aarch64__ +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U +#define XEMACPS_BD_NUM_WORDS 4U +#else +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U +#define XEMACPS_BD_NUM_WORDS 2U +#endif + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + (u32)((Addr) & ULONG64_LO_MASK)); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr))) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data)) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U) +#else +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) +#endif + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + +/*****************************************************************************/ +/** + * Retrieve the RX frame size. + * + * The returned value is the size of the received packet. + * This API supports jumbo frame sizes if enabled. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr) + * RxBufMask is dependent on whether jumbo is enabled or not. + * + *****************************************************************************/ +#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + (InstancePtr)->RxBufMask) + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c new file mode 100644 index 0000000..3536873 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c @@ -0,0 +1,1102 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.c +* @addtogroup emacps_v3_7 +* @{ +* +* This file implements buffer descriptor ring related functions. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+*		      Earlier it used to search in "BdLimit" number of BDs to
+*		      know which BDs are processed. Now one more check is
+*		      added. It looks for BDs till the current BD pointer
+*		      reaches HwTail. By doing this processing time is saved.
+* 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+*		      xemacps_bdring.c is modified. Now start of packet is
+*		      searched for returning the number of BDs processed.
+* 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+*		      removed. It is expected that all BDs are allocated in
+*		      from uncached area. Fix for CR #663885.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6   rb   09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
+* 		      pointers
+*
+*
    +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_cache.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************************************************************** + * Compute the virtual address of a descriptor from its physical address + * + * @param BdPtr is the physical address of the BD + * + * @returns Virtual address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_PHYS_TO_VIRT(BdPtr) \ + ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Compute the physical address of a descriptor from its virtual address + * + * @param BdPtr is the physical address of the BD + * + * @returns Physical address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_VIRT_TO_PHYS(BdPtr) \ + ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around + * to the beginning of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is greater than + * the high address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \ + { \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ + \ + Addr += ((RingPtr)->Separation * (NumBd)); \ + if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \ + { \ + Addr -= (RingPtr)->Length; \ + } \ + \ + (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \ + } + +/**************************************************************************** + * Move the BdPtr argument backwards an arbitrary number of BDs wrapping + * around to the end of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is less than + * the base address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \ + { \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ + \ + Addr -= ((RingPtr)->Separation * (NumBd)); \ + if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \ + { \ + Addr += (RingPtr)->Length; \ + } \ + \ + (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \ + } + + +/************************** Function Prototypes ******************************/ + +static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr); +static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr); + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** + * Using a memory segment allocated by the caller, create and setup the BD list + * for the given DMA channel. + * + * @param RingPtr is the instance to be worked on. + * @param PhysAddr is the physical base address of user memory region. + * @param VirtAddr is the virtual base address of the user memory region. If + * address translation is not being utilized, then VirtAddr should be + * equivalent to PhysAddr. + * @param Alignment governs the byte alignment of individual BDs. This function + * will enforce a minimum alignment of 4 bytes with no maximum as long + * as it is specified as a power of 2. + * @param BdCount is the number of BDs to setup in the user memory region. It + * is assumed the region is large enough to contain the BDs. + * + * @return + * + * - XST_SUCCESS if initialization was successful + * - XST_NO_FEATURE if the provided instance is a non DMA type + * channel. + * - XST_INVALID_PARAM under any of the following conditions: + * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment + * parameter. + * 2) Alignment parameter does not meet minimum requirements or is not a + * power of 2 value. + * 3) BdCount is 0. + * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans + * over address 0x00000000 in virtual address space. + * + * @note + * Make sure to pass in the right alignment value. + *****************************************************************************/ +LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, u32 BdCount) +{ + u32 i; + UINTPTR BdVirtAddr; + UINTPTR BdPhyAddr; + UINTPTR VirtAddrLoc = VirtAddr; + + /* In case there is a failure prior to creating list, make sure the + * following attributes are 0 to prevent calls to other functions + * from doing anything. + */ + RingPtr->AllCnt = 0U; + RingPtr->FreeCnt = 0U; + RingPtr->HwCnt = 0U; + RingPtr->PreCnt = 0U; + RingPtr->PostCnt = 0U; + + /* Make sure Alignment parameter meets minimum requirements */ + if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Make sure Alignment is a power of 2 */ + if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Make sure PhysAddr and VirtAddr are on same Alignment */ + if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Is BdCount reasonable? */ + if (BdCount == 0x00000000U) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Figure out how many bytes will be between the start of adjacent BDs */ + RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd)); + + /* Must make sure the ring doesn't span address 0x00000000. If it does, + * then the next/prev BD traversal macros will fail. + */ + if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) { + return (LONG)(XST_DMA_SG_LIST_ERROR); + } + + /* Initial ring setup: + * - Clear the entire space + * - Setup each BD's BDA field with the physical address of the next BD + */ + (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount)); + + BdVirtAddr = VirtAddrLoc; + BdPhyAddr = PhysAddr + RingPtr->Separation; + for (i = 1U; i < BdCount; i++) { + BdVirtAddr += RingPtr->Separation; + BdPhyAddr += RingPtr->Separation; + } + + /* Setup and initialize pointers and counters */ + RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED); + RingPtr->BaseBdAddr = VirtAddrLoc; + RingPtr->PhysBaseAddr = PhysAddr; + RingPtr->HighBdAddr = BdVirtAddr; + RingPtr->Length = + ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation); + RingPtr->AllCnt = (u32)BdCount; + RingPtr->FreeCnt = (u32)BdCount; + RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc; + RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr; + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Clone the given BD into every BD in the list. + * every field of the source BD is replicated in every BD of the list. + * + * This function can be called only when all BDs are in the free group such as + * they are immediately after initialization with XEmacPs_BdRingCreate(). + * This prevents modification of BDs while they are in use by hardware or the + * user. + * + * @param RingPtr is the pointer of BD ring instance to be worked on. + * @param SrcBdPtr is the source BD template to be cloned into the list. This + * BD will be modified. + * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates + * which direction. + * + * @return + * - XST_SUCCESS if the list was modified. + * - XST_DMA_SG_NO_LIST if a list has not been created. + * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under + * hardware or user control. + * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped. + * + *****************************************************************************/ +LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction) +{ + u32 i; + UINTPTR CurBd; + + /* Can't do this function if there isn't a ring */ + if (RingPtr->AllCnt == 0x00000000U) { + return (LONG)(XST_DMA_SG_NO_LIST); + } + + /* Can't do this function with the channel running */ + if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) { + return (LONG)(XST_DEVICE_IS_STARTED); + } + + /* Can't do this function with some of the BDs in use */ + if (RingPtr->FreeCnt != RingPtr->AllCnt) { + return (LONG)(XST_DMA_SG_LIST_ERROR); + } + + if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Starting from the top of the ring, save BD.Next, overwrite the entire + * BD with the template, then restore BD.Next + */ + CurBd = RingPtr->BaseBdAddr; + for (i = 0U; i < RingPtr->AllCnt; i++) { + memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd)); + CurBd += RingPtr->Separation; + } + + CurBd -= RingPtr->Separation; + + if (Direction == XEMACPS_RECV) { + XEmacPs_BdSetRxWrap(CurBd); + } + else { + XEmacPs_BdSetTxWrap(CurBd); + } + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Reserve locations in the BD list. The set of returned BDs may be modified + * in preparation for future DMA transaction(s). Once the BDs are ready to be + * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same + * order which they were allocated here. Example: + * + *     +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xadcps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + + +/****************************************************************************/ +/** +* +* This function enables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* @param Mask is the bit-mask of the interrupts to be enabled. +* Bit positions of 1 will be enabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XADCPS_INTX_* bits defined in xadcps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Disable the specified interrupts in the IPIER. + */ + RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, + XADCPS_INT_MASK_OFFSET); + RegValue &= ~(Mask & XADCPS_INTX_ALL_MASK); + XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, + XADCPS_INT_MASK_OFFSET, + RegValue); +} + + +/****************************************************************************/ +/** +* +* This function disables the specified interrupts in the device. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* @param Mask is the bit-mask of the interrupts to be disabled. +* Bit positions of 1 will be disabled. Bit positions of 0 will +* keep the previous setting. This mask is formed by OR'ing +* XADCPS_INTX_* bits defined in xadcps_hw.h. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Enable the specified interrupts in the IPIER. + */ + RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, + XADCPS_INT_MASK_OFFSET); + RegValue |= (Mask & XADCPS_INTX_ALL_MASK); + XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, + XADCPS_INT_MASK_OFFSET, + RegValue); +} +/****************************************************************************/ +/** +* +* This function returns the enabled interrupts read from the Interrupt Mask +* Register (IPIER). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h to +* interpret the returned value. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return A 32-bit value representing the contents of the I. +* +* @note None. +* +*****************************************************************************/ +u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Enable Register. + */ + return (~ XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, + XADCPS_INT_MASK_OFFSET) & XADCPS_INTX_ALL_MASK); +} + +/****************************************************************************/ +/** +* +* This function returns the interrupt status read from Interrupt Status +* Register(IPISR). Use the XADCPS_IPIXR_* constants defined in xadcps_hw.h +* to interpret the returned value. +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return A 32-bit value representing the contents of the IPISR. +* +* @note The device must be configured at hardware build time to include +* interrupt component for this function to work. +* +*****************************************************************************/ +u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr) +{ + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Return the value read from the Interrupt Status register. + */ + return XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, + XADCPS_INT_STS_OFFSET) & XADCPS_INTX_ALL_MASK; +} + +/****************************************************************************/ +/** +* +* This function clears the specified interrupts in the Interrupt Status +* Register (IPISR). +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* @param Mask is the bit-mask of the interrupts to be cleared. +* Bit positions of 1 will be cleared. Bit positions of 0 will not +* change the previous interrupt status. This mask is formed by +* OR'ing XADCPS_IPIXR_* bits which are defined in xadcps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Clear the specified interrupts in the Interrupt Status register. + */ + RegValue = XAdcPs_ReadReg(InstancePtr->Config.BaseAddress, + XADCPS_INT_STS_OFFSET); + RegValue &= (Mask & XADCPS_INTX_ALL_MASK); + XAdcPs_WriteReg(InstancePtr->Config.BaseAddress, XADCPS_INT_STS_OFFSET, + RegValue); + +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c new file mode 100644 index 0000000..7f171b4 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_selftest.c @@ -0,0 +1,141 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xadcps_selftest.c +* @addtogroup xadcps_v2_2 +* @{ +* +* This file contains a diagnostic self test function for the XAdcPs driver. +* The self test function does a simple read/write test of the Alarm Threshold +* Register. +* +* See xadcps.h for more information. +* +* @note None. +* +* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+*
    +* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xadcps.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constant defines the test value to be written + * to the Alarm Threshold Register + */ +#define XADCPS_ATR_TEST_VALUE 0x55 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* Run a self-test on the driver/device. The test +* - Resets the device, +* - Writes a value into the Alarm Threshold register and reads it back +* for comparison. +* - Resets the device again. +* +* +* @param InstancePtr is a pointer to the XAdcPs instance. +* +* @return +* - XST_SUCCESS if the value read from the Alarm Threshold +* register is the same as the value written. +* - XST_FAILURE Otherwise +* +* @note This is a destructive test in that resets of the device are +* performed. Refer to the device specification for the +* device status after the reset operation. +* +******************************************************************************/ +int XAdcPs_SelfTest(XAdcPs *InstancePtr) +{ + int Status; + u32 RegValue; + + /* + * Assert the argument + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + /* + * Reset the device to get it back to its default state + */ + XAdcPs_Reset(InstancePtr); + + /* + * Write a value into the Alarm Threshold registers, read it back, and + * do the comparison + */ + XAdcPs_SetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER, + XADCPS_ATR_TEST_VALUE); + RegValue = XAdcPs_GetAlarmThreshold(InstancePtr, XADCPS_ATR_VCCINT_UPPER); + + if (RegValue == XADCPS_ATR_TEST_VALUE) { + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + + /* + * Reset the device again to its default state. + */ + XAdcPs_Reset(InstancePtr); + /* + * Return the test result. + */ + return Status; +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c new file mode 100644 index 0000000..5fb7cde --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_sinit.c @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xadcps_sinit.c +* @addtogroup xadcps_v2_2 +* @{ +* +* This file contains the implementation of the XAdcPs driver's static +* initialization functionality. +* +* @note None. +* +* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI XADC driver
+*
+*
    +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xadcps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern XAdcPs_Config XAdcPs_ConfigTable[]; + +/*****************************************************************************/ +/** +* +* This function looks up the device configuration based on the unique device ID. +* The table XAdcPs_ConfigTable contains the configuration info for each device +* in the system. +* +* @param DeviceId contains the ID of the device for which the +* device configuration pointer is to be returned. +* +* @return +* - A pointer to the configuration found. +* - NULL if the specified device ID was not found. +* +* @note None. +* +******************************************************************************/ +XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId) +{ + XAdcPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index=0; Index < 1; Index++) { + if (XAdcPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XAdcPs_ConfigTable[Index]; + break; + } + } + + return CfgPtr; +} +/** @} */ diff --git a/LED_Blink/LED_Blink.sdk/webtalk/sdk_webtalk.tcl b/LED_Blink/LED_Blink.sdk/webtalk/sdk_webtalk.tcl new file mode 100644 index 0000000..cc242e3 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/webtalk/sdk_webtalk.tcl @@ -0,0 +1,71 @@ +webtalk_init -webtalk_dir C:\\Users\\qwpmb\\Documents\\summercamp2018\\LED_Blink\\LED_Blink.sdk\\webtalk +webtalk_register_client -client project +webtalk_add_data -client project -key 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Core(TM) i5-6200U CPU @ 2.30GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2400 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "8.419 GB" -context "user_environment" +webtalk_register_client -client sdk +webtalk_add_data -client sdk -key uid -value "1534495721041" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key VivadoVersion -value "2018.2" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key Device -value "7z010" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1534495721041" +webtalk_add_data -client sdk -key uid -value "1534495750592" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key isZynq -value "true" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key isZynqMP -value "false" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key Processors -value "2" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key VivadoVersion -value "2016.3.0" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key Arch -value "zynq" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key Device -value "7z020" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key IsHandoff -value "true" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key os -value "NA" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key apptemplate -value "NA" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key RecordType -value "HWCreation" -context "sdk\\\\hardware/1534495750592" +webtalk_add_data -client sdk -key uid -value "1534495751307" -context "sdk\\\\bsp/1534495751307" +webtalk_add_data -client sdk -key hwid -value "1534495750592" -context "sdk\\\\bsp/1534495751307" +webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\bsp/1534495751307" +webtalk_add_data -client sdk -key apptemplate -value "hello_world" -context "sdk\\\\bsp/1534495751307" +webtalk_add_data -client sdk -key RecordType -value "BSPCreation" -context "sdk\\\\bsp/1534495751307" +webtalk_add_data -client sdk -key uid -value "1534495762619" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key hwid -value "1534495750592" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key bspid -value "1534495751307" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key newbsp -value "true" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key os -value "standalone" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key apptemplate -value "hello_world" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key RecordType -value "APPCreation" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key LangUsed -value "C" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key Procused -value "ps7_cortexa9" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key projSize -value "202.0078125" -context "sdk\\\\application/1534495762619" +webtalk_add_data -client sdk -key uid -value "NA" -context "sdk\\\\bsp/1534496009840" +webtalk_add_data -client sdk -key RecordType -value "ToolUsage" -context "sdk\\\\bsp/1534496009840" +webtalk_add_data -client sdk -key BootgenCount -value "0" -context "sdk\\\\bsp/1534496009840" +webtalk_add_data -client sdk -key DebugCount -value "0" -context "sdk\\\\bsp/1534496009840" +webtalk_add_data -client sdk -key PerfCount -value "0" -context "sdk\\\\bsp/1534496009840" +webtalk_add_data -client sdk -key FlashCount -value "0" -context "sdk\\\\bsp/1534496009840" +webtalk_add_data -client sdk -key CrossTriggCount -value "0" -context "sdk\\\\bsp/1534496009840" +webtalk_add_data -client sdk -key QemuDebugCount -value "0" -context "sdk\\\\bsp/1534496009840" +webtalk_transmit -clientid 3983968469 -regid "" -xml C:\\Users\\qwpmb\\Documents\\summercamp2018\\LED_Blink\\LED_Blink.sdk\\webtalk\\usage_statistics_ext_sdk.xml -html C:\\Users\\qwpmb\\Documents\\summercamp2018\\LED_Blink\\LED_Blink.sdk\\webtalk\\usage_statistics_ext_sdk.html -wdm C:\\Users\\qwpmb\\Documents\\summercamp2018\\LED_Blink\\LED_Blink.sdk\\webtalk\\sdk_webtalk.wdm -intro "

    SDK Usage Report


    " +webtalk_terminate diff --git a/LED_Blink/LED_Blink.sdk/webtalk/usage_statistics_ext_sdk.xml b/LED_Blink/LED_Blink.sdk/webtalk/usage_statistics_ext_sdk.xml new file mode 100644 index 0000000..97d8c16 --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/webtalk/usage_statistics_ext_sdk.xml @@ -0,0 +1,89 @@ + + +
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    +     diff --git a/LED_Blink/LED_Blink.sdk/webtalk/webtalk.jou b/LED_Blink/LED_Blink.sdk/webtalk/webtalk.jou new file mode 100644 index 0000000..043089e --- /dev/null +++ b/LED_Blink/LED_Blink.sdk/webtalk/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.2 (64-bit) +# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018 +# +# Start of session at: Fri Aug 17 17:53:31 2018 +# Process ID: 14020 +# Current directory: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.sdk/webtalk +# Command line: wbtcv.exe -mode batch -source sdk_webtalk.tcl +# Log file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.sdk/webtalk/webtalk.log +# Journal file: C:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.sdk/webtalk\webtalk.jou +#----------------------------------------------------------- +source sdk_webtalk.tcl diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1.bd b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1.bd new file mode 100644 index 0000000..d3d427b --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1.bd @@ -0,0 +1,491 @@ + + + + + xilinx.com + BlockDiagram + design_1 + 1.00.a + + + isTop + true + + + + + DDR + + + + + + CAN_DEBUG + false + + + + + + + + TIMEPERIOD_PS + 1250 + + + + + + + + MEMORY_TYPE + COMPONENTS + + + + + + + + DATA_WIDTH + 8 + + + + + + + + CS_ENABLED + true + + + + + + + + DATA_MASK_ENABLED + true + + + + + + + + SLOT + Single + + + + + + + + MEM_ADDR_MAP + ROW_COLUMN_BANK + + + + + + + + BURST_LENGTH + 8 + + + + + + + + AXI_ARBITRATION_SCHEME + TDM + + + + + + + + CAS_LATENCY + 11 + + + + + + + + CAS_WRITE_LATENCY + 11 + + + + + + + + + + FIXED_IO + + + + + + CAN_DEBUG + false + + + + + + + + + + DATA.LED_OP + Data + Data + + + + + + + DATA + + + led_op + + + + + + LAYERED_METADATA + undef + + + + + + + + + + + + + BlockDiagram + :vivado.xilinx.com: + + + + + + led_op + + out + + + + + + + + xilinx.com + BlockDiagram + design_1_imp + 1.00.a + + + processing_system7_0 + + + design_1_processing_system7_0_0 + 0x1FFFFFFF + TRUE + 200 + 100 + 100 + 166.666666 + 111.111115 + 50 + 100 + 666.666687 + 533.333374 + 10.158730 + 200.000000 + 10.000000 + 125.000000 + 10.000000 + 100.000000 + 100.000000 + 166.666672 + 10.000000 + 111.111115 + 200.000000 + 200.000000 + 50.000000 + 100.000000 + 10.000000 + 10.000000 + 111.111115 + 111.111115 + 111.111115 + 111.111115 + 111.111115 + 111.111115 + 50000000 + 100000000 + 10000000 + 10000000 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + DDR 3 (Low Voltage) + 8 + MT41J256M16 RE-125 + 1 + MIO 1 .. 6 + 1 + MIO 1 .. 6 + 0 + x4 + 0 + 0 + 1 + EMIO + 0 + 1 + MIO 10 .. 15 + 1 + MIO 0 + 0 + 0 + 1 + EMIO + 0 + 1 + MIO 8 .. 9 + 0 + 1 + EMIO + 1 + EMIO + 1 + EMIO + 1 + EMIO + 1 + MIO 28 .. 39 + 1 + Share reset pin + 1 + MIO 7 + 1 + EMIO + 0 + 1 + MIO 48 .. 49 + 1 + EMIO + 1 + Share reset pin + 1 + MIO + 1 + 64 + 0.251400462962963 + External + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + LVCMOS 3.3V + slow + LVCMOS 3.3V + slow + LVCMOS 3.3V + slow + LVCMOS 3.3V + slow + LVCMOS 3.3V + slow + LVCMOS 3.3V + slow + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + disabled + LVCMOS 3.3V + slow + disabled + LVCMOS 3.3V + slow + disabled + LVCMOS 3.3V + slow + disabled + LVCMOS 3.3V + slow + disabled + LVCMOS 3.3V + slow + disabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + enabled + LVCMOS 3.3V + slow + NONE + SD 1#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#USB Reset#UART 1#UART 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#I2C 1#I2C 1#Unbonded#Unbonded#GPIO#GPIO + cd#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#tx#rx#data[0]#cmd#clk#data[1]#data[2]#data[3]#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#scl#sda#Unbonded#Unbonded#gpio[52]#gpio[53] + 1 + 1 + + + + led_0 + + + design_1_led_0_0 + led + + hdl + 0x0 + + + + + + + processing_system7_0_FCLK_CLK0 + + + + + + led_0_led_op + + + + + + + + + + + + + + + + xilinx.com + Addressing/processing_system7_0 + processing_system7 + 5.5 + + + M_AXI_GP0 + + + 0x40000000 + + + + + + + + Data + 4G + 32 + + + + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1.bxml b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1.bxml new file mode 100644 index 0000000..61097c8 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1.bxml @@ -0,0 +1,61 @@ + + + + Composite Fileset + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1_ooc.xdc b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1_ooc.xdc new file mode 100644 index 0000000..b3f8786 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/design_1_ooc.xdc @@ -0,0 +1,12 @@ +################################################################################ + +# This XDC is used only for OOC mode of synthesis, implementation +# This constraints file contains default clock frequencies to be used during +# out-of-context flows such as OOC Synthesis and Hierarchical Designs. +# This constraints file is not used in normal top-down synthesis (default flow +# of Vivado) +################################################################################ +create_clock -name processing_system7_0_FCLK_CLK0 -period 20 [get_pins processing_system7_0/FCLK_CLK0] +create_clock -name processing_system7_0_FCLK_CLK1 -period 10 [get_pins processing_system7_0/FCLK_CLK1] + +################################################################################ \ No newline at end of file diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v new file mode 100644 index 0000000..73827c2 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v @@ -0,0 +1,104 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +//Date : Fri Aug 17 17:41:43 2018 +//Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +//Command : generate_target design_1_wrapper.bd +//Design : design_1_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module design_1_wrapper + (DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + led_op); + inout [14:0]DDR_addr; + inout [2:0]DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [1:0]DDR_dm; + inout [15:0]DDR_dq; + inout [1:0]DDR_dqs_n; + inout [1:0]DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [31:0]FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + output led_op; + + wire [14:0]DDR_addr; + wire [2:0]DDR_ba; + wire DDR_cas_n; + wire DDR_ck_n; + wire DDR_ck_p; + wire DDR_cke; + wire DDR_cs_n; + wire [1:0]DDR_dm; + wire [15:0]DDR_dq; + wire [1:0]DDR_dqs_n; + wire [1:0]DDR_dqs_p; + wire DDR_odt; + wire DDR_ras_n; + wire DDR_reset_n; + wire DDR_we_n; + wire FIXED_IO_ddr_vrn; + wire FIXED_IO_ddr_vrp; + wire [31:0]FIXED_IO_mio; + wire FIXED_IO_ps_clk; + wire FIXED_IO_ps_porb; + wire FIXED_IO_ps_srstb; + wire led_op; + + design_1 design_1_i + (.DDR_addr(DDR_addr), + .DDR_ba(DDR_ba), + .DDR_cas_n(DDR_cas_n), + .DDR_ck_n(DDR_ck_n), + .DDR_ck_p(DDR_ck_p), + .DDR_cke(DDR_cke), + .DDR_cs_n(DDR_cs_n), + .DDR_dm(DDR_dm), + .DDR_dq(DDR_dq), + .DDR_dqs_n(DDR_dqs_n), + .DDR_dqs_p(DDR_dqs_p), + .DDR_odt(DDR_odt), + .DDR_ras_n(DDR_ras_n), + .DDR_reset_n(DDR_reset_n), + .DDR_we_n(DDR_we_n), + .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp), + .FIXED_IO_mio(FIXED_IO_mio), + .FIXED_IO_ps_clk(FIXED_IO_ps_clk), + .FIXED_IO_ps_porb(FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb), + .led_op(led_op)); +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl new file mode 100644 index 0000000..68fe1fd --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl @@ -0,0 +1,562 @@ + +################################################################ +# This is a generated script based on design: design_1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2018.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + + +# The design that will be created by this Tcl script contains the following +# module references: +# led + +# Please add the sources of those modules before sourcing this Tcl script. + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z010clg225-1 +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name design_1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + # Create ports + set led_op [ create_bd_port -dir O -type data led_op ] + + # Create instance: led_0, and set properties + set block_name led + set block_cell_name led_0 + if { [catch {set led_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $led_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {50.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {166.666672} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_APU_CLK_RATIO_ENABLE {0.251400462962963} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CLK0_FREQ {50000000} \ + CONFIG.PCW_CLK1_FREQ {100000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_RESET_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {0} \ + CONFIG.PCW_EN_CLK1_PORT {1} \ + CONFIG.PCW_EN_EMIO_CD_SDIO0 {1} \ + CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_GPIO {1} \ + CONFIG.PCW_EN_EMIO_I2C0 {1} \ + CONFIG.PCW_EN_EMIO_SDIO0 {1} \ + CONFIG.PCW_EN_EMIO_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_SPI0 {1} \ + CONFIG.PCW_EN_EMIO_SPI1 {1} \ + CONFIG.PCW_EN_EMIO_TTC0 {1} \ + CONFIG.PCW_EN_EMIO_TTC1 {1} \ + CONFIG.PCW_EN_EMIO_UART0 {1} \ + CONFIG.PCW_EN_EMIO_WP_SDIO0 {1} \ + CONFIG.PCW_EN_GPIO {1} \ + CONFIG.PCW_EN_I2C0 {1} \ + CONFIG.PCW_EN_I2C1 {1} \ + CONFIG.PCW_EN_QSPI {1} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SDIO1 {1} \ + CONFIG.PCW_EN_SPI0 {1} \ + CONFIG.PCW_EN_SPI1 {1} \ + CONFIG.PCW_EN_TTC0 {1} \ + CONFIG.PCW_EN_TTC1 {1} \ + CONFIG.PCW_EN_UART0 {1} \ + CONFIG.PCW_EN_UART1 {1} \ + CONFIG.PCW_EN_USB0 {1} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {4} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {2} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ + CONFIG.PCW_FTM_CTI_IN0 {} \ + CONFIG.PCW_FTM_CTI_IN2 {} \ + CONFIG.PCW_FTM_CTI_OUT0 {} \ + CONFIG.PCW_FTM_CTI_OUT2 {} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ + CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \ + CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \ + CONFIG.PCW_I2C0_I2C0_IO {EMIO} \ + CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C0_RESET_ENABLE {0} \ + CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \ + CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \ + CONFIG.PCW_I2C1_I2C1_IO {MIO 48 .. 49} \ + CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_I2C1_RESET_ENABLE {0} \ + CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_I2C_RESET_ENABLE {1} \ + CONFIG.PCW_I2C_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \ + CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ + CONFIG.PCW_IRQ_F2P_INTR {1} \ + CONFIG.PCW_MIO_0_DIRECTION {in} \ + CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_0_PULLUP {enabled} \ + CONFIG.PCW_MIO_0_SLEW {slow} \ + CONFIG.PCW_MIO_10_DIRECTION {inout} \ + CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_10_PULLUP {disabled} \ + CONFIG.PCW_MIO_10_SLEW {slow} \ + CONFIG.PCW_MIO_11_DIRECTION {inout} \ + CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_11_PULLUP {disabled} \ + CONFIG.PCW_MIO_11_SLEW {slow} \ + CONFIG.PCW_MIO_12_DIRECTION {inout} \ + CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_12_PULLUP {disabled} \ + CONFIG.PCW_MIO_12_SLEW {slow} \ + CONFIG.PCW_MIO_13_DIRECTION {inout} \ + CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_13_PULLUP {disabled} \ + CONFIG.PCW_MIO_13_SLEW {slow} \ + CONFIG.PCW_MIO_14_DIRECTION {inout} \ + CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_14_PULLUP {disabled} \ + CONFIG.PCW_MIO_14_SLEW {slow} \ + CONFIG.PCW_MIO_15_DIRECTION {inout} \ + CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_15_PULLUP {disabled} \ + CONFIG.PCW_MIO_15_SLEW {slow} \ + CONFIG.PCW_MIO_1_DIRECTION {out} \ + CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_1_PULLUP {enabled} \ + CONFIG.PCW_MIO_1_SLEW {slow} \ + CONFIG.PCW_MIO_28_DIRECTION {inout} \ + CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_28_PULLUP {enabled} \ + CONFIG.PCW_MIO_28_SLEW {slow} \ + CONFIG.PCW_MIO_29_DIRECTION {in} \ + CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_29_PULLUP {enabled} \ + CONFIG.PCW_MIO_29_SLEW {slow} \ + CONFIG.PCW_MIO_2_DIRECTION {inout} \ + CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_2_PULLUP {disabled} \ + CONFIG.PCW_MIO_2_SLEW {slow} \ + CONFIG.PCW_MIO_30_DIRECTION {out} \ + CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_30_PULLUP {enabled} \ + CONFIG.PCW_MIO_30_SLEW {slow} \ + CONFIG.PCW_MIO_31_DIRECTION {in} \ + CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_31_PULLUP {enabled} \ + CONFIG.PCW_MIO_31_SLEW {slow} \ + CONFIG.PCW_MIO_32_DIRECTION {inout} \ + CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_32_PULLUP {enabled} \ + CONFIG.PCW_MIO_32_SLEW {slow} \ + CONFIG.PCW_MIO_33_DIRECTION {inout} \ + CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_33_PULLUP {enabled} \ + CONFIG.PCW_MIO_33_SLEW {slow} \ + CONFIG.PCW_MIO_34_DIRECTION {inout} \ + CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_34_PULLUP {enabled} \ + CONFIG.PCW_MIO_34_SLEW {slow} \ + CONFIG.PCW_MIO_35_DIRECTION {inout} \ + CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_35_PULLUP {enabled} \ + CONFIG.PCW_MIO_35_SLEW {slow} \ + CONFIG.PCW_MIO_36_DIRECTION {in} \ + CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_36_PULLUP {enabled} \ + CONFIG.PCW_MIO_36_SLEW {slow} \ + CONFIG.PCW_MIO_37_DIRECTION {inout} \ + CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_37_PULLUP {enabled} \ + CONFIG.PCW_MIO_37_SLEW {slow} \ + CONFIG.PCW_MIO_38_DIRECTION {inout} \ + CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_38_PULLUP {enabled} \ + CONFIG.PCW_MIO_38_SLEW {slow} \ + CONFIG.PCW_MIO_39_DIRECTION {inout} \ + CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_39_PULLUP {enabled} \ + CONFIG.PCW_MIO_39_SLEW {slow} \ + CONFIG.PCW_MIO_3_DIRECTION {inout} \ + CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_3_PULLUP {disabled} \ + CONFIG.PCW_MIO_3_SLEW {slow} \ + CONFIG.PCW_MIO_48_DIRECTION {inout} \ + CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_48_PULLUP {enabled} \ + CONFIG.PCW_MIO_48_SLEW {slow} \ + CONFIG.PCW_MIO_49_DIRECTION {inout} \ + CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_49_PULLUP {enabled} \ + CONFIG.PCW_MIO_49_SLEW {slow} \ + CONFIG.PCW_MIO_4_DIRECTION {inout} \ + CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_4_PULLUP {disabled} \ + CONFIG.PCW_MIO_4_SLEW {slow} \ + CONFIG.PCW_MIO_52_DIRECTION {inout} \ + CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_52_PULLUP {enabled} \ + CONFIG.PCW_MIO_52_SLEW {slow} \ + CONFIG.PCW_MIO_53_DIRECTION {inout} \ + CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_53_PULLUP {enabled} \ + CONFIG.PCW_MIO_53_SLEW {slow} \ + CONFIG.PCW_MIO_5_DIRECTION {inout} \ + CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_5_PULLUP {disabled} \ + CONFIG.PCW_MIO_5_SLEW {slow} \ + CONFIG.PCW_MIO_6_DIRECTION {out} \ + CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_6_PULLUP {disabled} \ + CONFIG.PCW_MIO_6_SLEW {slow} \ + CONFIG.PCW_MIO_7_DIRECTION {out} \ + CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_7_PULLUP {disabled} \ + CONFIG.PCW_MIO_7_SLEW {slow} \ + CONFIG.PCW_MIO_8_DIRECTION {out} \ + CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_8_PULLUP {disabled} \ + CONFIG.PCW_MIO_8_SLEW {slow} \ + CONFIG.PCW_MIO_9_DIRECTION {in} \ + CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ + CONFIG.PCW_MIO_9_PULLUP {enabled} \ + CONFIG.PCW_MIO_9_SLEW {slow} \ + CONFIG.PCW_MIO_TREE_PERIPHERALS {SD 1#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#USB Reset#UART 1#UART 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#I2C 1#I2C 1#Unbonded#Unbonded#GPIO#GPIO} \ + CONFIG.PCW_MIO_TREE_SIGNALS {cd#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#tx#rx#data[0]#cmd#clk#data[1]#data[2]#data[3]#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#scl#sda#Unbonded#Unbonded#gpio[52]#gpio[53]} \ + CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ + CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ + CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ + CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ + CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ + CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ + CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ + CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ + CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ + CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ + CONFIG.PCW_SD0_GRP_CD_IO {EMIO} \ + CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \ + CONFIG.PCW_SD0_GRP_WP_IO {EMIO} \ + CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD0_SD0_IO {EMIO} \ + CONFIG.PCW_SD1_GRP_CD_ENABLE {1} \ + CONFIG.PCW_SD1_GRP_CD_IO {MIO 0} \ + CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ + CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ + CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \ + CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ + CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \ + CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI0_SPI0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI1_SPI1_IO {EMIO} \ + CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {6} \ + CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ + CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \ + CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_TTC0_TTC0_IO {EMIO} \ + CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ + CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_TTC1_TTC1_IO {EMIO} \ + CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART0_UART0_IO {EMIO} \ + CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ + CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ + CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ + CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ + CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \ + CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ + CONFIG.PCW_UIPARAM_DDR_BL {8} \ + CONFIG.PCW_UIPARAM_DDR_CL {7} \ + CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ + CONFIG.PCW_UIPARAM_DDR_CWL {6} \ + CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ + CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ + CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \ + CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ + CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ + CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ + CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ + CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ + CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ + CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ + CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NONE} \ + CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_USB0_RESET_ENABLE {1} \ + CONFIG.PCW_USB0_RESET_IO {MIO 7} \ + CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ + CONFIG.PCW_USB1_RESET_ENABLE {0} \ + CONFIG.PCW_USB_RESET_ENABLE {1} \ + CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ + CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ + ] $processing_system7_0 + + # Create interface connections + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] + + # Create port connections + connect_bd_net -net led_0_led_op [get_bd_ports led_op] [get_bd_pins led_0/led_op] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins led_0/m_clock] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] + + # Create address segments + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.dcp b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..acbdf8ac61273db8fb2a7366576c20a91e3885a6 GIT binary patch literal 13314 zcmaL819&CPx9GiN+s4H9#F^N(ZQHgc*2K1L+Y?(8+fHuYd+zF2w z)vBu9^;E63T22xK6cqpfKmt^wk)$mn2;FLd000|M0081E*T~S0&du5?I&sn_p8-{5 zDWSMV%^AJ$huCUqyb@4C2ofKXKZ~|HX!;OU?KcK2PFcPJ`{I*;h{DTf_N5eR_nR49 zXggwKVUBdFwlYeD`rd)fgtPk*N))}@Y;))<%DsK1*~FFY;QGtzoykE>TY-~ABw9&)y{S;{Gb z!to@BL$VYmdXFcRLA0VLPw~+Bj9F-dCs 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b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.xci new file mode 100644 index 0000000..215f9f1 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.xci @@ -0,0 +1,48 @@ + + + xilinx.com + xci + unknown + 1.0 + + + design_1_led_0_0 + + + + + design_1_processing_system7_0_0_FCLK_CLK0 + 50000000 + 0.000 + design_1_led_0_0 + zynq + + xc7z010 + clg225 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 1 + TRUE + . + + ../../ipshared + 2018.2 + OOC_HIERARCHICAL + + + + + + + + + + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.xml b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.xml new file mode 100644 index 0000000..bead073 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0.xml @@ -0,0 +1,261 @@ + + + xilinx.com + customized_ip + design_1_led_0_0 + 1.0 + + + m_clock + + + + + + + CLK + + + m_clock + + + + + + FREQ_HZ + 50000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + design_1_processing_system7_0_0_FCLK_CLK0 + + + none + + + + + ASSOCIATED_BUSIF + + + + none + + + + + ASSOCIATED_RESET + + + + none + + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + led + + + outputProductCRC + 8:bbe84eb5 + + + + + xilinx_verilogsynthesiswrapper + Verilog Synthesis Wrapper + verilogSource:vivado.xilinx.com:synthesis.wrapper + verilog + design_1_led_0_0 + + xilinx_verilogsynthesiswrapper_view_fileset + + + + GENtimestamp + Fri Aug 17 08:41:43 UTC 2018 + + + outputProductCRC + 8:bbe84eb5 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + led + + + outputProductCRC + 8:e2721815 + + + + + xilinx_verilogsimulationwrapper + Verilog Simulation Wrapper + verilogSource:vivado.xilinx.com:simulation.wrapper + verilog + design_1_led_0_0 + + xilinx_verilogsimulationwrapper_view_fileset + + + + GENtimestamp + Fri Aug 17 08:41:43 UTC 2018 + + + outputProductCRC + 8:e2721815 + + + + + xilinx_externalfiles + External Files + :vivado.xilinx.com:external.files + + xilinx_externalfiles_view_fileset + + + + GENtimestamp + Fri Aug 17 08:42:47 UTC 2018 + + + outputProductCRC + 8:bbe84eb5 + + + + + + + m_clock + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + led_op + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_verilogsynthesiswrapper_view_fileset + + synth/design_1_led_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_verilogsimulationwrapper_view_fileset + + sim/design_1_led_0_0.v + verilogSource + xil_defaultlib + + + + xilinx_externalfiles_view_fileset + + design_1_led_0_0.dcp + dcp + USED_IN_implementation + USED_IN_synthesis + xil_defaultlib + + + design_1_led_0_0_stub.v + verilogSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_led_0_0_stub.vhdl + vhdlSource + USED_IN_synth_blackbox_stub + xil_defaultlib + + + design_1_led_0_0_sim_netlist.v + verilogSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + design_1_led_0_0_sim_netlist.vhdl + vhdlSource + USED_IN_simulation + USED_IN_single_language + xil_defaultlib + + + + xilinx.com:module_ref:led:1.0 + + + Component_Name + design_1_led_0_0 + + + + + led_v1_0 + module_ref + 1 + + + + + + + 2018.2 + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_sim_netlist.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_sim_netlist.v new file mode 100644 index 0000000..320c7ca --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_sim_netlist.v @@ -0,0 +1,504 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Fri Aug 17 17:42:47 2018 +// Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_sim_netlist.v +// Design : design_1_led_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg225-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_led_0_0,led,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *) +(* X_CORE_INFO = "led,Vivado 2018.2" *) +(* NotValidForBitStream *) +module design_1_led_0_0 + (m_clock, + led_op); + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_clock CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_clock, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) input m_clock; + output led_op; + + wire led_op; + wire m_clock; + + design_1_led_0_0_led inst + (.led_op(led_op), + .m_clock(m_clock)); +endmodule + +(* ORIG_REF_NAME = "led" *) +module design_1_led_0_0_led + (led_op, + m_clock); + output led_op; + input m_clock; + + wire clear; + wire \cnt[0]_i_3_n_0 ; + wire \cnt[0]_i_4_n_0 ; + wire \cnt[0]_i_5_n_0 ; + wire [24:6]cnt_reg; + wire \cnt_reg[0]_i_2_n_0 ; + wire \cnt_reg[0]_i_2_n_1 ; + wire \cnt_reg[0]_i_2_n_2 ; + wire \cnt_reg[0]_i_2_n_3 ; + wire \cnt_reg[0]_i_2_n_4 ; + wire \cnt_reg[0]_i_2_n_5 ; + wire \cnt_reg[0]_i_2_n_6 ; + wire \cnt_reg[0]_i_2_n_7 ; + wire \cnt_reg[12]_i_1_n_0 ; + wire \cnt_reg[12]_i_1_n_1 ; + wire \cnt_reg[12]_i_1_n_2 ; + wire \cnt_reg[12]_i_1_n_3 ; + wire \cnt_reg[12]_i_1_n_4 ; + wire \cnt_reg[12]_i_1_n_5 ; + wire \cnt_reg[12]_i_1_n_6 ; + wire \cnt_reg[12]_i_1_n_7 ; + wire \cnt_reg[16]_i_1_n_0 ; + wire \cnt_reg[16]_i_1_n_1 ; + wire \cnt_reg[16]_i_1_n_2 ; + wire \cnt_reg[16]_i_1_n_3 ; + wire \cnt_reg[16]_i_1_n_4 ; + wire \cnt_reg[16]_i_1_n_5 ; + wire \cnt_reg[16]_i_1_n_6 ; + wire \cnt_reg[16]_i_1_n_7 ; + wire \cnt_reg[20]_i_1_n_0 ; + wire \cnt_reg[20]_i_1_n_1 ; + wire \cnt_reg[20]_i_1_n_2 ; + wire \cnt_reg[20]_i_1_n_3 ; + wire \cnt_reg[20]_i_1_n_4 ; + wire \cnt_reg[20]_i_1_n_5 ; + wire \cnt_reg[20]_i_1_n_6 ; + wire \cnt_reg[20]_i_1_n_7 ; + wire \cnt_reg[24]_i_1_n_7 ; + wire \cnt_reg[4]_i_1_n_0 ; + wire \cnt_reg[4]_i_1_n_1 ; + wire \cnt_reg[4]_i_1_n_2 ; + wire \cnt_reg[4]_i_1_n_3 ; + wire \cnt_reg[4]_i_1_n_4 ; + wire \cnt_reg[4]_i_1_n_5 ; + wire \cnt_reg[4]_i_1_n_6 ; + wire \cnt_reg[4]_i_1_n_7 ; + wire \cnt_reg[8]_i_1_n_0 ; + wire \cnt_reg[8]_i_1_n_1 ; + wire \cnt_reg[8]_i_1_n_2 ; + wire \cnt_reg[8]_i_1_n_3 ; + wire \cnt_reg[8]_i_1_n_4 ; + wire \cnt_reg[8]_i_1_n_5 ; + wire \cnt_reg[8]_i_1_n_6 ; + wire \cnt_reg[8]_i_1_n_7 ; + wire \cnt_reg_n_0_[0] ; + wire \cnt_reg_n_0_[1] ; + wire \cnt_reg_n_0_[2] ; + wire \cnt_reg_n_0_[3] ; + wire \cnt_reg_n_0_[4] ; + wire \cnt_reg_n_0_[5] ; + wire led_op; + wire led_op_r_i_1_n_0; + wire led_op_r_i_2_n_0; + wire led_op_r_i_3_n_0; + wire led_op_r_i_4_n_0; + wire m_clock; + wire [3:0]\NLW_cnt_reg[24]_i_1_CO_UNCONNECTED ; + wire [3:1]\NLW_cnt_reg[24]_i_1_O_UNCONNECTED ; + + LUT6 #( + .INIT(64'hFFFF0000A8880000)) + \cnt[0]_i_1 + (.I0(\cnt[0]_i_3_n_0 ), + .I1(cnt_reg[17]), + .I2(\cnt[0]_i_4_n_0 ), + .I3(cnt_reg[16]), + .I4(cnt_reg[24]), + .I5(cnt_reg[23]), + .O(clear)); + LUT5 #( + .INIT(32'h80000000)) + \cnt[0]_i_3 + (.I0(cnt_reg[18]), + .I1(cnt_reg[19]), + .I2(cnt_reg[20]), + .I3(cnt_reg[22]), + .I4(cnt_reg[21]), + .O(\cnt[0]_i_3_n_0 )); + LUT6 #( + .INIT(64'hFFFFFFFF80000000)) + \cnt[0]_i_4 + (.I0(led_op_r_i_4_n_0), + .I1(cnt_reg[12]), + .I2(cnt_reg[11]), + .I3(cnt_reg[14]), + .I4(cnt_reg[13]), + .I5(cnt_reg[15]), + .O(\cnt[0]_i_4_n_0 )); + LUT1 #( + .INIT(2'h1)) + \cnt[0]_i_5 + (.I0(\cnt_reg_n_0_[0] ), + .O(\cnt[0]_i_5_n_0 )); + FDRE #( + .INIT(1'b0)) + \cnt_reg[0] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[0]_i_2_n_7 ), + .Q(\cnt_reg_n_0_[0] ), + .R(clear)); + CARRY4 \cnt_reg[0]_i_2 + (.CI(1'b0), + .CO({\cnt_reg[0]_i_2_n_0 ,\cnt_reg[0]_i_2_n_1 ,\cnt_reg[0]_i_2_n_2 ,\cnt_reg[0]_i_2_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b1}), + .O({\cnt_reg[0]_i_2_n_4 ,\cnt_reg[0]_i_2_n_5 ,\cnt_reg[0]_i_2_n_6 ,\cnt_reg[0]_i_2_n_7 }), + .S({\cnt_reg_n_0_[3] ,\cnt_reg_n_0_[2] ,\cnt_reg_n_0_[1] ,\cnt[0]_i_5_n_0 })); + FDRE #( + .INIT(1'b0)) + \cnt_reg[10] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[8]_i_1_n_5 ), + .Q(cnt_reg[10]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[11] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[8]_i_1_n_4 ), + .Q(cnt_reg[11]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[12] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[12]_i_1_n_7 ), + .Q(cnt_reg[12]), + .R(clear)); + CARRY4 \cnt_reg[12]_i_1 + (.CI(\cnt_reg[8]_i_1_n_0 ), + .CO({\cnt_reg[12]_i_1_n_0 ,\cnt_reg[12]_i_1_n_1 ,\cnt_reg[12]_i_1_n_2 ,\cnt_reg[12]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[12]_i_1_n_4 ,\cnt_reg[12]_i_1_n_5 ,\cnt_reg[12]_i_1_n_6 ,\cnt_reg[12]_i_1_n_7 }), + .S(cnt_reg[15:12])); + FDRE #( + .INIT(1'b0)) + \cnt_reg[13] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[12]_i_1_n_6 ), + .Q(cnt_reg[13]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[14] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[12]_i_1_n_5 ), + .Q(cnt_reg[14]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[15] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[12]_i_1_n_4 ), + .Q(cnt_reg[15]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[16] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[16]_i_1_n_7 ), + .Q(cnt_reg[16]), + .R(clear)); + CARRY4 \cnt_reg[16]_i_1 + (.CI(\cnt_reg[12]_i_1_n_0 ), + .CO({\cnt_reg[16]_i_1_n_0 ,\cnt_reg[16]_i_1_n_1 ,\cnt_reg[16]_i_1_n_2 ,\cnt_reg[16]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[16]_i_1_n_4 ,\cnt_reg[16]_i_1_n_5 ,\cnt_reg[16]_i_1_n_6 ,\cnt_reg[16]_i_1_n_7 }), + .S(cnt_reg[19:16])); + FDRE #( + .INIT(1'b0)) + \cnt_reg[17] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[16]_i_1_n_6 ), + .Q(cnt_reg[17]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[18] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[16]_i_1_n_5 ), + .Q(cnt_reg[18]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[19] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[16]_i_1_n_4 ), + .Q(cnt_reg[19]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[1] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[0]_i_2_n_6 ), + .Q(\cnt_reg_n_0_[1] ), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[20] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[20]_i_1_n_7 ), + .Q(cnt_reg[20]), + .R(clear)); + CARRY4 \cnt_reg[20]_i_1 + (.CI(\cnt_reg[16]_i_1_n_0 ), + .CO({\cnt_reg[20]_i_1_n_0 ,\cnt_reg[20]_i_1_n_1 ,\cnt_reg[20]_i_1_n_2 ,\cnt_reg[20]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[20]_i_1_n_4 ,\cnt_reg[20]_i_1_n_5 ,\cnt_reg[20]_i_1_n_6 ,\cnt_reg[20]_i_1_n_7 }), + .S(cnt_reg[23:20])); + FDRE #( + .INIT(1'b0)) + \cnt_reg[21] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[20]_i_1_n_6 ), + .Q(cnt_reg[21]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[22] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[20]_i_1_n_5 ), + .Q(cnt_reg[22]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[23] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[20]_i_1_n_4 ), + .Q(cnt_reg[23]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[24] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[24]_i_1_n_7 ), + .Q(cnt_reg[24]), + .R(clear)); + CARRY4 \cnt_reg[24]_i_1 + (.CI(\cnt_reg[20]_i_1_n_0 ), + .CO(\NLW_cnt_reg[24]_i_1_CO_UNCONNECTED [3:0]), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\NLW_cnt_reg[24]_i_1_O_UNCONNECTED [3:1],\cnt_reg[24]_i_1_n_7 }), + .S({1'b0,1'b0,1'b0,cnt_reg[24]})); + FDRE #( + .INIT(1'b0)) + \cnt_reg[2] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[0]_i_2_n_5 ), + .Q(\cnt_reg_n_0_[2] ), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[3] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[0]_i_2_n_4 ), + .Q(\cnt_reg_n_0_[3] ), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[4] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[4]_i_1_n_7 ), + .Q(\cnt_reg_n_0_[4] ), + .R(clear)); + CARRY4 \cnt_reg[4]_i_1 + (.CI(\cnt_reg[0]_i_2_n_0 ), + .CO({\cnt_reg[4]_i_1_n_0 ,\cnt_reg[4]_i_1_n_1 ,\cnt_reg[4]_i_1_n_2 ,\cnt_reg[4]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[4]_i_1_n_4 ,\cnt_reg[4]_i_1_n_5 ,\cnt_reg[4]_i_1_n_6 ,\cnt_reg[4]_i_1_n_7 }), + .S({cnt_reg[7:6],\cnt_reg_n_0_[5] ,\cnt_reg_n_0_[4] })); + FDRE #( + .INIT(1'b0)) + \cnt_reg[5] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[4]_i_1_n_6 ), + .Q(\cnt_reg_n_0_[5] ), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[6] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[4]_i_1_n_5 ), + .Q(cnt_reg[6]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[7] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[4]_i_1_n_4 ), + .Q(cnt_reg[7]), + .R(clear)); + FDRE #( + .INIT(1'b0)) + \cnt_reg[8] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[8]_i_1_n_7 ), + .Q(cnt_reg[8]), + .R(clear)); + CARRY4 \cnt_reg[8]_i_1 + (.CI(\cnt_reg[4]_i_1_n_0 ), + .CO({\cnt_reg[8]_i_1_n_0 ,\cnt_reg[8]_i_1_n_1 ,\cnt_reg[8]_i_1_n_2 ,\cnt_reg[8]_i_1_n_3 }), + .CYINIT(1'b0), + .DI({1'b0,1'b0,1'b0,1'b0}), + .O({\cnt_reg[8]_i_1_n_4 ,\cnt_reg[8]_i_1_n_5 ,\cnt_reg[8]_i_1_n_6 ,\cnt_reg[8]_i_1_n_7 }), + .S(cnt_reg[11:8])); + FDRE #( + .INIT(1'b0)) + \cnt_reg[9] + (.C(m_clock), + .CE(1'b1), + .D(\cnt_reg[8]_i_1_n_6 ), + .Q(cnt_reg[9]), + .R(clear)); + LUT4 #( + .INIT(16'h37C8)) + led_op_r_i_1 + (.I0(cnt_reg[23]), + .I1(cnt_reg[24]), + .I2(led_op_r_i_2_n_0), + .I3(led_op), + .O(led_op_r_i_1_n_0)); + LUT6 #( + .INIT(64'hAAA8A8A888888888)) + led_op_r_i_2 + (.I0(\cnt[0]_i_3_n_0 ), + .I1(cnt_reg[17]), + .I2(cnt_reg[15]), + .I3(led_op_r_i_3_n_0), + .I4(led_op_r_i_4_n_0), + .I5(cnt_reg[16]), + .O(led_op_r_i_2_n_0)); + LUT4 #( + .INIT(16'h8000)) + led_op_r_i_3 + (.I0(cnt_reg[12]), + .I1(cnt_reg[11]), + .I2(cnt_reg[14]), + .I3(cnt_reg[13]), + .O(led_op_r_i_3_n_0)); + LUT5 #( + .INIT(32'hFFFFFFFE)) + led_op_r_i_4 + (.I0(cnt_reg[6]), + .I1(cnt_reg[9]), + .I2(cnt_reg[10]), + .I3(cnt_reg[8]), + .I4(cnt_reg[7]), + .O(led_op_r_i_4_n_0)); + FDRE #( + .INIT(1'b0)) + led_op_r_reg + (.C(m_clock), + .CE(1'b1), + .D(led_op_r_i_1_n_0), + .Q(led_op), + .R(1'b0)); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.v new file mode 100644 index 0000000..81f63f1 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.v @@ -0,0 +1,21 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Fri Aug 17 17:42:47 2018 +// Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/design_1_led_0_0_stub.v +// Design : design_1_led_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg225-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "led,Vivado 2018.2" *) +module design_1_led_0_0(m_clock, led_op) +/* synthesis syn_black_box black_box_pad_pin="m_clock,led_op" */; + input m_clock; + output led_op; +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/sim/design_1_led_0_0.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/sim/design_1_led_0_0.v new file mode 100644 index 0000000..26f79de --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/sim/design_1_led_0_0.v @@ -0,0 +1,71 @@ +// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:module_ref:led:1.0 +// IP Revision: 1 + +`timescale 1ns/1ps + +(* IP_DEFINITION_SOURCE = "module_ref" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_led_0_0 ( + m_clock, + led_op +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_clock, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_clock CLK" *) +input wire m_clock; +output wire led_op; + + led inst ( + .m_clock(m_clock), + .led_op(led_op) + ); +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/synth/design_1_led_0_0.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/synth/design_1_led_0_0.v new file mode 100644 index 0000000..860b81e --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_led_0_0/synth/design_1_led_0_0.v @@ -0,0 +1,72 @@ +// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:module_ref:led:1.0 +// IP Revision: 1 + +(* X_CORE_INFO = "led,Vivado 2018.2" *) +(* CHECK_LICENSE_TYPE = "design_1_led_0_0,led,{}" *) +(* CORE_GENERATION_INFO = "design_1_led_0_0,led,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=led,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *) +(* IP_DEFINITION_SOURCE = "module_ref" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_led_0_0 ( + m_clock, + led_op +); + +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_clock, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_clock CLK" *) +input wire m_clock; +output wire led_op; + + led inst ( + .m_clock(m_clock), + .led_op(led_op) + ); +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..55b8336e3f59ba2180926c25bb9427fd6e5e61fd GIT binary patch literal 217020 zcmd43bx<8m_bwV-f)m``-3bzcySuwL6+?x|CC z|GQO8chBnSwN^j<^qQHT-Y7^zKz{o0;REc4lt@(BYmZIpaj*{`OrSn|fB{KOj2#%= zZEdm=we2&Qv4g8p^bH;7^b&EUrYohCehA}IBE0>e|%0 z4&S%)F$shoDf`j)gv}!E*%VsPs$}oymADWu-G?jB2aef8V{9r90@A>f9uG%nWppM6 zg|;)0z=b@?*+dtHkkO5Qt!6*6Uh=&VqOp5|nTe0$hhlFc^oJmM1F$C%e)fsG-xnWs zH|=Z*c{N+iQ`e)@VMZhJ7x2Iov8lT_aIo09)^}h|)!T_yPMrCDMKs&_iFH#lyrjXE+iJ zhjJ{7H7_=v_#Ve=EBQvHw*+9d{isJYprc~9(0Pz<5ui8VjlEgWh5!uk8A6^aTl}Vl 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+## +## Details : Constraints file +## FPGA family: zynq +## FPGA: xc7z010clg225-1 +## Device Size: xc7z010 +## Package: clg225 +## Speedgrade: -1 +## +## +############################################################################ +############################################################################ +############################################################################ +# Clock constraints # +############################################################################ +create_clock -name clk_fpga_0 -period "20" [get_pins "PS7_i/FCLKCLK[0]"] +set_input_jitter clk_fpga_0 0.6 +#The clocks are asynchronous, user should constrain them appropriately.# +create_clock -name clk_fpga_1 -period "10" [get_pins "PS7_i/FCLKCLK[1]"] +set_input_jitter clk_fpga_1 0.3 +#The clocks are asynchronous, user should constrain them appropriately.# + + +############################################################################ +# I/O STANDARDS and Location Constraints # +############################################################################ + +# GPIO / gpio[53] / MIO[53] +set_property iostandard "LVCMOS33" [get_ports "MIO[31]"] +set_property PACKAGE_PIN "C13" [get_ports "MIO[31]"] +set_property slew "slow" [get_ports "MIO[31]"] +set_property drive "8" [get_ports "MIO[31]"] +set_property pullup "TRUE" [get_ports "MIO[31]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[31]"] +# GPIO / gpio[52] / MIO[52] +set_property iostandard "LVCMOS33" [get_ports "MIO[30]"] +set_property PACKAGE_PIN "A12" [get_ports "MIO[30]"] +set_property slew "slow" [get_ports "MIO[30]"] +set_property drive "8" [get_ports "MIO[30]"] +set_property pullup "TRUE" [get_ports "MIO[30]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[30]"] +# I2C 1 / sda / MIO[49] +set_property iostandard "LVCMOS33" [get_ports "MIO[29]"] +set_property PACKAGE_PIN "D13" [get_ports "MIO[29]"] +set_property slew "slow" [get_ports "MIO[29]"] +set_property drive "8" [get_ports "MIO[29]"] +set_property pullup "TRUE" [get_ports "MIO[29]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[29]"] +# I2C 1 / scl / MIO[48] +set_property iostandard "LVCMOS33" [get_ports "MIO[28]"] +set_property PACKAGE_PIN "B12" [get_ports "MIO[28]"] +set_property slew "slow" [get_ports "MIO[28]"] +set_property drive "8" [get_ports "MIO[28]"] +set_property pullup "TRUE" [get_ports "MIO[28]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"] +# USB 0 / data[7] / MIO[39] +set_property iostandard "LVCMOS33" [get_ports "MIO[27]"] +set_property PACKAGE_PIN "D14" [get_ports "MIO[27]"] +set_property slew "slow" [get_ports "MIO[27]"] +set_property drive "8" [get_ports "MIO[27]"] +set_property pullup "TRUE" [get_ports "MIO[27]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[27]"] +# USB 0 / data[6] / MIO[38] +set_property iostandard "LVCMOS33" [get_ports "MIO[26]"] +set_property PACKAGE_PIN "A13" [get_ports "MIO[26]"] +set_property slew "slow" [get_ports "MIO[26]"] +set_property drive "8" [get_ports "MIO[26]"] +set_property pullup "TRUE" [get_ports "MIO[26]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[26]"] +# USB 0 / data[5] / MIO[37] +set_property iostandard "LVCMOS33" [get_ports "MIO[25]"] +set_property PACKAGE_PIN "C14" [get_ports "MIO[25]"] +set_property slew "slow" [get_ports "MIO[25]"] +set_property drive "8" [get_ports "MIO[25]"] +set_property pullup "TRUE" [get_ports "MIO[25]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[25]"] +# USB 0 / clk / MIO[36] +set_property iostandard "LVCMOS33" [get_ports "MIO[24]"] +set_property PACKAGE_PIN "B14" [get_ports "MIO[24]"] +set_property slew "slow" [get_ports "MIO[24]"] +set_property drive "8" [get_ports "MIO[24]"] +set_property pullup "TRUE" [get_ports "MIO[24]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[24]"] +# USB 0 / data[3] / MIO[35] +set_property iostandard "LVCMOS33" [get_ports "MIO[23]"] +set_property PACKAGE_PIN "A14" [get_ports "MIO[23]"] +set_property slew "slow" [get_ports "MIO[23]"] +set_property drive "8" [get_ports "MIO[23]"] +set_property pullup "TRUE" [get_ports "MIO[23]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[23]"] +# USB 0 / data[2] / MIO[34] +set_property iostandard "LVCMOS33" [get_ports "MIO[22]"] +set_property PACKAGE_PIN "D15" [get_ports "MIO[22]"] +set_property slew "slow" [get_ports "MIO[22]"] +set_property drive "8" [get_ports "MIO[22]"] +set_property pullup "TRUE" [get_ports "MIO[22]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[22]"] +# USB 0 / data[1] / MIO[33] +set_property iostandard "LVCMOS33" [get_ports "MIO[21]"] +set_property PACKAGE_PIN "C11" [get_ports "MIO[21]"] +set_property slew "slow" [get_ports "MIO[21]"] +set_property drive "8" [get_ports "MIO[21]"] +set_property pullup "TRUE" [get_ports "MIO[21]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[21]"] +# USB 0 / data[0] / MIO[32] +set_property iostandard "LVCMOS33" [get_ports "MIO[20]"] +set_property PACKAGE_PIN "E15" [get_ports "MIO[20]"] +set_property slew "slow" [get_ports "MIO[20]"] +set_property drive "8" [get_ports "MIO[20]"] +set_property pullup "TRUE" [get_ports "MIO[20]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[20]"] +# USB 0 / nxt / MIO[31] +set_property iostandard "LVCMOS33" [get_ports "MIO[19]"] +set_property PACKAGE_PIN "C12" [get_ports "MIO[19]"] +set_property slew "slow" [get_ports "MIO[19]"] +set_property drive "8" [get_ports "MIO[19]"] +set_property pullup "TRUE" [get_ports "MIO[19]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[19]"] +# USB 0 / stp / MIO[30] +set_property iostandard "LVCMOS33" [get_ports "MIO[18]"] +set_property PACKAGE_PIN "B15" [get_ports "MIO[18]"] +set_property slew "slow" [get_ports "MIO[18]"] +set_property drive "8" [get_ports "MIO[18]"] +set_property pullup "TRUE" [get_ports "MIO[18]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[18]"] +# USB 0 / dir / MIO[29] +set_property iostandard "LVCMOS33" [get_ports "MIO[17]"] +set_property PACKAGE_PIN "D11" [get_ports "MIO[17]"] +set_property slew "slow" [get_ports "MIO[17]"] +set_property drive "8" [get_ports "MIO[17]"] +set_property pullup "TRUE" [get_ports "MIO[17]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[17]"] +# USB 0 / data[4] / MIO[28] +set_property iostandard "LVCMOS33" [get_ports "MIO[16]"] +set_property PACKAGE_PIN "A15" [get_ports "MIO[16]"] +set_property slew "slow" [get_ports "MIO[16]"] +set_property drive "8" [get_ports "MIO[16]"] +set_property pullup "TRUE" [get_ports "MIO[16]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[16]"] +# SD 1 / data[3] / MIO[15] +set_property iostandard "LVCMOS33" [get_ports "MIO[15]"] +set_property PACKAGE_PIN "D10" [get_ports "MIO[15]"] +set_property slew "slow" [get_ports "MIO[15]"] +set_property drive "8" [get_ports "MIO[15]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"] +# SD 1 / data[2] / MIO[14] +set_property iostandard "LVCMOS33" [get_ports "MIO[14]"] +set_property PACKAGE_PIN "B9" [get_ports "MIO[14]"] +set_property slew "slow" [get_ports "MIO[14]"] +set_property drive "8" [get_ports "MIO[14]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"] +# SD 1 / data[1] / MIO[13] +set_property iostandard "LVCMOS33" [get_ports "MIO[13]"] +set_property PACKAGE_PIN "C6" [get_ports "MIO[13]"] +set_property slew "slow" [get_ports "MIO[13]"] +set_property drive "8" [get_ports "MIO[13]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"] +# SD 1 / clk / MIO[12] +set_property iostandard "LVCMOS33" [get_ports "MIO[12]"] +set_property PACKAGE_PIN "B7" [get_ports "MIO[12]"] +set_property slew "slow" [get_ports "MIO[12]"] +set_property drive "8" [get_ports "MIO[12]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"] +# SD 1 / cmd / MIO[11] +set_property iostandard "LVCMOS33" [get_ports "MIO[11]"] +set_property PACKAGE_PIN "B10" [get_ports "MIO[11]"] +set_property slew "slow" [get_ports "MIO[11]"] +set_property drive "8" [get_ports "MIO[11]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"] +# SD 1 / data[0] / MIO[10] +set_property iostandard "LVCMOS33" [get_ports "MIO[10]"] +set_property PACKAGE_PIN "D6" [get_ports "MIO[10]"] +set_property slew "slow" [get_ports "MIO[10]"] +set_property drive "8" [get_ports "MIO[10]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"] +# UART 1 / rx / MIO[9] +set_property iostandard "LVCMOS33" [get_ports "MIO[9]"] +set_property PACKAGE_PIN "B5" [get_ports "MIO[9]"] +set_property slew "slow" [get_ports "MIO[9]"] +set_property drive "8" [get_ports "MIO[9]"] +set_property pullup "TRUE" [get_ports "MIO[9]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[9]"] +# UART 1 / tx / MIO[8] +set_property iostandard "LVCMOS33" [get_ports "MIO[8]"] +set_property PACKAGE_PIN "B6" [get_ports "MIO[8]"] +set_property slew "slow" [get_ports "MIO[8]"] +set_property drive "8" [get_ports "MIO[8]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"] +# USB Reset / reset / MIO[7] +set_property iostandard "LVCMOS33" [get_ports "MIO[7]"] +set_property PACKAGE_PIN "D9" [get_ports "MIO[7]"] +set_property slew "slow" [get_ports "MIO[7]"] +set_property drive "8" [get_ports "MIO[7]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"] +# Quad SPI Flash / qspi0_sclk / MIO[6] +set_property iostandard "LVCMOS33" [get_ports "MIO[6]"] +set_property PACKAGE_PIN "A10" [get_ports "MIO[6]"] +set_property slew "slow" [get_ports "MIO[6]"] +set_property drive "8" [get_ports "MIO[6]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"] +# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5] +set_property iostandard "LVCMOS33" [get_ports "MIO[5]"] +set_property PACKAGE_PIN "A9" [get_ports "MIO[5]"] +set_property slew "slow" [get_ports "MIO[5]"] +set_property drive "8" [get_ports "MIO[5]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"] +# Quad SPI Flash / qspi0_io[2] / MIO[4] +set_property iostandard "LVCMOS33" [get_ports "MIO[4]"] +set_property PACKAGE_PIN "C8" [get_ports "MIO[4]"] +set_property slew "slow" [get_ports "MIO[4]"] +set_property drive "8" [get_ports "MIO[4]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"] +# Quad SPI Flash / qspi0_io[1] / MIO[3] +set_property iostandard "LVCMOS33" [get_ports "MIO[3]"] +set_property PACKAGE_PIN "A7" [get_ports "MIO[3]"] +set_property slew "slow" [get_ports "MIO[3]"] +set_property drive "8" [get_ports "MIO[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"] +# Quad SPI Flash / qspi0_io[0] / MIO[2] +set_property iostandard "LVCMOS33" [get_ports "MIO[2]"] +set_property PACKAGE_PIN "A8" [get_ports "MIO[2]"] +set_property slew "slow" [get_ports "MIO[2]"] +set_property drive "8" [get_ports "MIO[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"] +# Quad SPI Flash / qspi0_ss_b / MIO[1] +set_property iostandard "LVCMOS33" [get_ports "MIO[1]"] +set_property PACKAGE_PIN "A5" [get_ports "MIO[1]"] +set_property slew "slow" [get_ports "MIO[1]"] +set_property drive "8" [get_ports "MIO[1]"] +set_property pullup "TRUE" [get_ports "MIO[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"] +# SD 1 / cd / MIO[0] +set_property iostandard "LVCMOS33" [get_ports "MIO[0]"] +set_property PACKAGE_PIN "D8" [get_ports "MIO[0]"] +set_property slew "slow" [get_ports "MIO[0]"] +set_property drive "8" [get_ports "MIO[0]"] +set_property pullup "TRUE" [get_ports "MIO[0]"] +set_property PIO_DIRECTION "INPUT" [get_ports "MIO[0]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRP"] +set_property PACKAGE_PIN "H3" [get_ports "DDR_VRP"] +set_property slew "FAST" [get_ports "DDR_VRP"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_VRN"] +set_property PACKAGE_PIN "J3" [get_ports "DDR_VRN"] +set_property slew "FAST" [get_ports "DDR_VRN"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"] +set_property iostandard "SSTL135" [get_ports "DDR_WEB"] +set_property PACKAGE_PIN "R3" [get_ports "DDR_WEB"] +set_property slew "SLOW" [get_ports "DDR_WEB"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"] +set_property iostandard "SSTL135" [get_ports "DDR_RAS_n"] +set_property PACKAGE_PIN "R6" [get_ports "DDR_RAS_n"] +set_property slew "SLOW" [get_ports "DDR_RAS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"] +set_property iostandard "SSTL135" [get_ports "DDR_ODT"] +set_property PACKAGE_PIN "K3" [get_ports "DDR_ODT"] +set_property slew "SLOW" [get_ports "DDR_ODT"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"] +set_property iostandard "SSTL135" [get_ports "DDR_DRSTB"] +set_property PACKAGE_PIN "L4" [get_ports "DDR_DRSTB"] +set_property slew "FAST" [get_ports "DDR_DRSTB"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[1]"] +set_property PACKAGE_PIN "G2" [get_ports "DDR_DQS[1]"] +set_property slew "FAST" [get_ports "DDR_DQS[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS[0]"] +set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"] +set_property slew "FAST" [get_ports "DDR_DQS[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[1]"] +set_property PACKAGE_PIN "F2" [get_ports "DDR_DQS_n[1]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"] +set_property iostandard "DIFF_SSTL135_T_DCI" [get_ports "DDR_DQS_n[0]"] +set_property PACKAGE_PIN "B2" [get_ports "DDR_DQS_n[0]"] +set_property slew "FAST" [get_ports "DDR_DQS_n[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[9]"] +set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[9]"] +set_property slew "FAST" [get_ports "DDR_DQ[9]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[8]"] +set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[8]"] +set_property slew "FAST" [get_ports "DDR_DQ[8]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[7]"] +set_property PACKAGE_PIN "A3" [get_ports "DDR_DQ[7]"] +set_property slew "FAST" [get_ports "DDR_DQ[7]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[6]"] +set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[6]"] +set_property slew "FAST" [get_ports "DDR_DQ[6]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[5]"] +set_property PACKAGE_PIN "A4" [get_ports "DDR_DQ[5]"] +set_property slew "FAST" [get_ports "DDR_DQ[5]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[4]"] +set_property PACKAGE_PIN "B4" [get_ports "DDR_DQ[4]"] +set_property slew "FAST" [get_ports "DDR_DQ[4]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[3]"] +set_property PACKAGE_PIN "C1" [get_ports "DDR_DQ[3]"] +set_property slew "FAST" [get_ports "DDR_DQ[3]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[2]"] +set_property PACKAGE_PIN "C4" [get_ports "DDR_DQ[2]"] +set_property slew "FAST" [get_ports "DDR_DQ[2]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[1]"] +set_property PACKAGE_PIN "A2" [get_ports "DDR_DQ[1]"] +set_property slew "FAST" [get_ports "DDR_DQ[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[15]"] +set_property PACKAGE_PIN "H2" [get_ports "DDR_DQ[15]"] +set_property slew "FAST" [get_ports "DDR_DQ[15]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[14]"] +set_property PACKAGE_PIN "H1" [get_ports "DDR_DQ[14]"] +set_property slew "FAST" [get_ports "DDR_DQ[14]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[13]"] +set_property PACKAGE_PIN "G1" [get_ports "DDR_DQ[13]"] +set_property slew "FAST" [get_ports "DDR_DQ[13]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[12]"] +set_property PACKAGE_PIN "F3" [get_ports "DDR_DQ[12]"] +set_property slew "FAST" [get_ports "DDR_DQ[12]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[11]"] +set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[11]"] +set_property slew "FAST" [get_ports "DDR_DQ[11]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[10]"] +set_property PACKAGE_PIN "E2" [get_ports "DDR_DQ[10]"] +set_property slew "FAST" [get_ports "DDR_DQ[10]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DQ[0]"] +set_property PACKAGE_PIN "D4" [get_ports "DDR_DQ[0]"] +set_property slew "FAST" [get_ports "DDR_DQ[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[1]"] +set_property PACKAGE_PIN "D3" [get_ports "DDR_DM[1]"] +set_property slew "FAST" [get_ports "DDR_DM[1]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"] +set_property iostandard "SSTL135_T_DCI" [get_ports "DDR_DM[0]"] +set_property PACKAGE_PIN "B1" [get_ports "DDR_DM[0]"] +set_property slew "FAST" [get_ports "DDR_DM[0]"] +set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"] +set_property iostandard "SSTL135" [get_ports "DDR_CS_n"] +set_property PACKAGE_PIN "R2" [get_ports "DDR_CS_n"] +set_property slew "SLOW" [get_ports "DDR_CS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"] +set_property iostandard "SSTL135" [get_ports "DDR_CKE"] +set_property PACKAGE_PIN "L3" [get_ports "DDR_CKE"] +set_property slew "SLOW" [get_ports "DDR_CKE"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"] +set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk"] +set_property PACKAGE_PIN "N3" [get_ports "DDR_Clk"] +set_property slew "FAST" [get_ports "DDR_Clk"] +set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"] +set_property iostandard "DIFF_SSTL135" [get_ports "DDR_Clk_n"] +set_property PACKAGE_PIN "N2" [get_ports "DDR_Clk_n"] +set_property slew "FAST" [get_ports "DDR_Clk_n"] +set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"] +set_property iostandard "SSTL135" [get_ports "DDR_CAS_n"] +set_property PACKAGE_PIN "R5" [get_ports "DDR_CAS_n"] +set_property slew "SLOW" [get_ports "DDR_CAS_n"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"] +set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[2]"] +set_property PACKAGE_PIN "N6" [get_ports "DDR_BankAddr[2]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"] +set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[1]"] +set_property PACKAGE_PIN "R1" [get_ports "DDR_BankAddr[1]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"] +set_property iostandard "SSTL135" [get_ports "DDR_BankAddr[0]"] +set_property PACKAGE_PIN "M6" [get_ports "DDR_BankAddr[0]"] +set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[9]"] +set_property PACKAGE_PIN "N4" [get_ports "DDR_Addr[9]"] +set_property slew "SLOW" [get_ports "DDR_Addr[9]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[8]"] +set_property PACKAGE_PIN "P6" [get_ports "DDR_Addr[8]"] +set_property slew "SLOW" [get_ports "DDR_Addr[8]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[7]"] +set_property PACKAGE_PIN "M5" [get_ports "DDR_Addr[7]"] +set_property slew "SLOW" [get_ports "DDR_Addr[7]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[6]"] +set_property PACKAGE_PIN "P5" [get_ports "DDR_Addr[6]"] +set_property slew "SLOW" [get_ports "DDR_Addr[6]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[5]"] +set_property PACKAGE_PIN "P4" [get_ports "DDR_Addr[5]"] +set_property slew "SLOW" [get_ports "DDR_Addr[5]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[4]"] +set_property PACKAGE_PIN "P3" [get_ports "DDR_Addr[4]"] +set_property slew "SLOW" [get_ports "DDR_Addr[4]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[3]"] +set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[3]"] +set_property slew "SLOW" [get_ports "DDR_Addr[3]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[2]"] +set_property PACKAGE_PIN "M1" [get_ports "DDR_Addr[2]"] +set_property slew "SLOW" [get_ports "DDR_Addr[2]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[1]"] +set_property PACKAGE_PIN "N1" [get_ports "DDR_Addr[1]"] +set_property slew "SLOW" [get_ports "DDR_Addr[1]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[14]"] +set_property PACKAGE_PIN "K1" [get_ports "DDR_Addr[14]"] +set_property slew "SLOW" [get_ports "DDR_Addr[14]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[13]"] +set_property PACKAGE_PIN "K2" [get_ports "DDR_Addr[13]"] +set_property slew "SLOW" [get_ports "DDR_Addr[13]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[12]"] +set_property PACKAGE_PIN "M2" [get_ports "DDR_Addr[12]"] +set_property slew "SLOW" [get_ports "DDR_Addr[12]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[11]"] +set_property PACKAGE_PIN "L2" [get_ports "DDR_Addr[11]"] +set_property slew "SLOW" [get_ports "DDR_Addr[11]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[10]"] +set_property PACKAGE_PIN "J1" [get_ports "DDR_Addr[10]"] +set_property slew "SLOW" [get_ports "DDR_Addr[10]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"] +set_property iostandard "SSTL135" [get_ports "DDR_Addr[0]"] +set_property PACKAGE_PIN "P1" [get_ports "DDR_Addr[0]"] +set_property slew "SLOW" [get_ports "DDR_Addr[0]"] +set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"] +set_property iostandard "LVCMOS33" [get_ports "PS_PORB"] +set_property PACKAGE_PIN "C9" [get_ports "PS_PORB"] +set_property slew "fast" [get_ports "PS_PORB"] +set_property iostandard "LVCMOS33" [get_ports "PS_SRSTB"] +set_property PACKAGE_PIN "B11" [get_ports "PS_SRSTB"] +set_property slew "fast" [get_ports "PS_SRSTB"] +set_property iostandard "LVCMOS33" [get_ports "PS_CLK"] +set_property PACKAGE_PIN "C7" [get_ports "PS_CLK"] +set_property slew "fast" [get_ports "PS_CLK"] + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml new file mode 100644 index 0000000..0f78fce --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xml @@ -0,0 +1,39167 @@ + + + xilinx.com + customized_ip + design_1_processing_system7_0_0 + 1.0 + + + GMII_ETHERNET_0 + + + + + + + TX_EN + + + ENET0_GMII_TX_EN + + + + + TX_ER + + + ENET0_GMII_TX_ER + + + + + TXD + + + ENET0_GMII_TXD + + + + + COL + + + ENET0_GMII_COL + + + + + CRS + + + ENET0_GMII_CRS + + + + + RX_CLK + + + ENET0_GMII_RX_CLK + + + + + RX_DV + + + ENET0_GMII_RX_DV + + + + + RX_ER + + + ENET0_GMII_RX_ER + + + + + TX_CLK + + + ENET0_GMII_TX_CLK + + + + + RXD + + + ENET0_GMII_RXD + + + + + + + false + + + + + + MDIO_ETHERNET_0 + + + + + + + MDC + + + ENET0_MDIO_MDC + + + + + MDIO_O + + + ENET0_MDIO_O + + + + + MDIO_T + + + ENET0_MDIO_T + + + + + MDIO_I + + + ENET0_MDIO_I + + + + + + CAN_DEBUG + false + + + none + + + + + + + + false + + + + + + PTP_ETHERNET_0 + + + + + + + DELAY_REQ_RX + + + ENET0_PTP_DELAY_REQ_RX + + + + + DELAY_REQ_TX + + + ENET0_PTP_DELAY_REQ_TX + + + + + PDELAY_REQ_RX + + + ENET0_PTP_PDELAY_REQ_RX + + + + + PDELAY_REQ_TX + + + ENET0_PTP_PDELAY_REQ_TX + + + + + PDELAY_RESP_RX + + + ENET0_PTP_PDELAY_RESP_RX + + + + + PDELAY_RESP_TX + + + ENET0_PTP_PDELAY_RESP_TX + + + + + SYNC_FRAME_RX + + + ENET0_PTP_SYNC_FRAME_RX + + + + + SYNC_FRAME_TX + + + ENET0_PTP_SYNC_FRAME_TX + + + + + SOF_RX + + + ENET0_SOF_RX + + + + + SOF_TX + + + ENET0_SOF_TX + + + + + + + false + + + + + + ENET0_EXT_INTIN + + + + + + + INTERRUPT + + + ENET0_EXT_INTIN + + + + + + SENSITIVITY + LEVEL_HIGH + + + none + + + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + GMII_ETHERNET_1 + + + + + + + TX_EN + + + ENET1_GMII_TX_EN + + + + + TX_ER + + + ENET1_GMII_TX_ER + + + + + TXD + + + ENET1_GMII_TXD + + + + + COL + + + ENET1_GMII_COL + + + + + CRS + + + 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+ PCW UART0 BASEADDR + 0xE0000000 + + + + true + + + + + + PCW_UART0_HIGHADDR + PCW UART0 HIGHADDR + 0xE0000FFF + + + + true + + + + + + PCW_UART1_BASEADDR + PCW UART1 BASEADDR + 0xE0001000 + + + + true + + + + + + PCW_UART1_HIGHADDR + PCW UART1 HIGHADDR + 0xE0001FFF + + + + true + + + + + + PCW_I2C0_BASEADDR + PCW I2C0 BASEADDR + 0xE0004000 + + + + true + + + + + + PCW_I2C0_HIGHADDR + PCW I2C0 HIGHADDR + 0xE0004FFF + + + + true + + + + + + PCW_I2C1_BASEADDR + PCW I2C1 BASEADDR + 0xE0005000 + + + + true + + + + + + PCW_I2C1_HIGHADDR + PCW I2C1 HIGHADDR + 0xE0005FFF + + + + true + + + + + + PCW_SPI0_BASEADDR + PCW SPI0 BASEADDR + 0xE0006000 + + + + true + + + + + + PCW_SPI0_HIGHADDR + PCW SPI0 HIGHADDR + 0xE0006FFF + + + + true + + + + + + PCW_SPI1_BASEADDR + PCW SPI1 BASEADDR + 0xE0007000 + + + + true + + + + + + PCW_SPI1_HIGHADDR + PCW SPI1 HIGHADDR + 0xE0007FFF + + + + true + + + + + + PCW_CAN0_BASEADDR + PCW CAN0 BASEADDR + 0xE0008000 + + + + false + + + + + + PCW_CAN0_HIGHADDR + PCW CAN0 HIGHADDR + 0xE0008FFF + + + + false + + + + + + PCW_CAN1_BASEADDR + PCW CAN1 BASEADDR + 0xE0009000 + + + + false + + + + + + PCW_CAN1_HIGHADDR + PCW CAN1 HIGHADDR + 0xE0009FFF + + + + false + + + + + + PCW_GPIO_BASEADDR + PCW GPIO BASEADDR + 0xE000A000 + + + + true + + + + + + PCW_GPIO_HIGHADDR + PCW GPIO HIGHADDR + 0xE000AFFF + + + + true + + + + + + PCW_ENET0_BASEADDR + PCW ENET0 BASEADDR + 0xE000B000 + + + + false + + + + + + PCW_ENET0_HIGHADDR + PCW ENET0 HIGHADDR + 0xE000BFFF + + + + false + + + + + + PCW_ENET1_BASEADDR + PCW ENET1 BASEADDR + 0xE000C000 + + + + false + + + + + + PCW_ENET1_HIGHADDR + PCW ENET1 HIGHADDR + 0xE000CFFF + + + + false + + + + + + PCW_SDIO0_BASEADDR + PCW SDIO0 BASEADDR + 0xE0100000 + + + + true + + + + + + PCW_SDIO0_HIGHADDR + PCW SDIO0 HIGHADDR + 0xE0100FFF + + + + true + + + + + + PCW_SDIO1_BASEADDR + PCW SDIO1 BASEADDR + 0xE0101000 + + + + true + + + + + + PCW_SDIO1_HIGHADDR + PCW SDIO1 HIGHADDR + 0xE0101FFF + + + + true + + + + + + PCW_USB0_BASEADDR + PCW USB0 BASEADDR + 0xE0102000 + + + + true + + + + + + PCW_USB0_HIGHADDR + PCW USB0 HIGHADDR + 0xE0102fff + + + + true + + + + + + PCW_USB1_BASEADDR + PCW USB1 BASEADDR + 0xE0103000 + + + + false + + + + + + PCW_USB1_HIGHADDR + PCW USB1 HIGHADDR + 0xE0103fff + + + + false + + + + + + PCW_TTC0_BASEADDR + PCW TTC0 BASEADDR + 0xE0104000 + + + + true + + + + + + PCW_TTC0_HIGHADDR + PCW TTC0 HIGHADDR + 0xE0104fff + + + + true + + + + + + PCW_TTC1_BASEADDR + PCW TTC1 BASEADDR + 0xE0105000 + + + + true + + + + + + PCW_TTC1_HIGHADDR + PCW TTC1 HIGHADDR + 0xE0105fff + + + + true + + + + + + PCW_FCLK_CLK0_BUF + PCW FCLK CLK0 BUF + TRUE + + + + true + + + + + + PCW_FCLK_CLK1_BUF + PCW FCLK CLK1 BUF + TRUE + + + + true + + + + + + PCW_FCLK_CLK2_BUF + PCW FCLK CLK2 BUF + FALSE + + + + false + + + + + + PCW_FCLK_CLK3_BUF + PCW FCLK CLK3 BUF + FALSE + + + + false + + + + + + PCW_UIPARAM_DDR_FREQ_MHZ + PCW UIPARAM DDR FREQ MHZ + 533.333333 + + + PCW_UIPARAM_DDR_BANK_ADDR_COUNT + PCW UIPARAM DDR BANK ADDR COUNT + 3 + + + + false + + + + + + PCW_UIPARAM_DDR_ROW_ADDR_COUNT + PCW UIPARAM DDR ROW ADDR COUNT + 15 + + + + false + + + + + + PCW_UIPARAM_DDR_COL_ADDR_COUNT + PCW UIPARAM DDR COL ADDR COUNT + 10 + + + + false + + + + + + PCW_UIPARAM_DDR_CL + PCW UIPARAM DDR CL + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_CWL + PCW UIPARAM DDR CWL + 6 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RCD + PCW UIPARAM DDR T RCD + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RP + PCW UIPARAM DDR T RP + 7 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RC + PCW UIPARAM DDR T RC + 48.91 + + + + false + + + + + + PCW_UIPARAM_DDR_T_RAS_MIN + PCW UIPARAM DDR T RAS MIN + 35.0 + + + + false + + + + + + PCW_UIPARAM_DDR_T_FAW + PCW UIPARAM DDR T FAW + 40.0 + + + + false + + + + + + PCW_UIPARAM_DDR_AL + PCW UIPARAM DDR AL + 0 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 + PCW UIPARAM DDR DQS TO CLK DELAY 0 + 0.0 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 + PCW UIPARAM DDR DQS TO CLK DELAY 1 + 0.0 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 + PCW UIPARAM DDR DQS TO CLK DELAY 2 + 0.0 + + + PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 + PCW UIPARAM DDR DQS TO CLK DELAY 3 + 0.0 + + + PCW_UIPARAM_DDR_BOARD_DELAY0 + PCW UIPARAM DDR BOARD DELAY0 + 0.25 + + + PCW_UIPARAM_DDR_BOARD_DELAY1 + PCW UIPARAM DDR BOARD DELAY1 + 0.25 + + + PCW_UIPARAM_DDR_BOARD_DELAY2 + PCW UIPARAM DDR BOARD DELAY2 + 0.25 + + + PCW_UIPARAM_DDR_BOARD_DELAY3 + PCW UIPARAM DDR BOARD DELAY3 + 0.25 + + + PCW_UIPARAM_DDR_DQS_0_LENGTH_MM + PCW UIPARAM DDR DQS 0 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_DQS_1_LENGTH_MM + PCW UIPARAM DDR DQS 1 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_DQS_2_LENGTH_MM + PCW UIPARAM DDR DQS 2 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_DQS_3_LENGTH_MM + PCW UIPARAM DDR DQS 3 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_DQ_0_LENGTH_MM + PCW UIPARAM DDR DQ 0 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_DQ_1_LENGTH_MM + PCW UIPARAM DDR DQ 1 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_DQ_2_LENGTH_MM + PCW UIPARAM DDR DQ 2 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_DQ_3_LENGTH_MM + PCW UIPARAM DDR DQ 3 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM + PCW UIPARAM DDR CLOCK 0 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM + PCW UIPARAM DDR CLOCK 1 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM + PCW UIPARAM DDR CLOCK 2 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM + PCW UIPARAM DDR CLOCK 3 LENGTH MM + 0 + + + PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 0 PACKAGE LENGTH + 81.244 + + + PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 1 PACKAGE LENGTH + 57.044 + + + PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 2 PACKAGE LENGTH + 520 + + + PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH + PCW UIPARAM DDR DQS 3 PACKAGE LENGTH + 700 + + + PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 0 PACKAGE LENGTH + 77.166 + + + PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 1 PACKAGE LENGTH + 53.995 + + + PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 2 PACKAGE LENGTH + 550 + + + PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH + PCW UIPARAM DDR DQ 3 PACKAGE LENGTH + 780 + + + PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 0 PACKAGE LENGTH + 86.1835 + + + PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 1 PACKAGE LENGTH + 86.1835 + + + PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 2 PACKAGE LENGTH + 86.1835 + + + PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH + PCW UIPARAM DDR CLOCK 3 PACKAGE LENGTH + 86.1835 + + + PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY + PCW UIPARAM DDR DQS 3 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY + PCW UIPARAM DDR DQ 3 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 0 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 1 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 2 PROPOGATION DELAY + 160 + + + PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY + PCW UIPARAM DDR CLOCK 3 PROPOGATION DELAY + 160 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 + PCW PACKAGE DDR DQS TO CLK DELAY 0 + 0.005 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 + PCW PACKAGE DDR DQS TO CLK DELAY 1 + 0.029 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 + PCW PACKAGE DDR DQS TO CLK DELAY 2 + -0.434 + + + PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 + PCW PACKAGE DDR DQS TO CLK DELAY 3 + -0.614 + + + PCW_PACKAGE_DDR_BOARD_DELAY0 + PCW PACKAGE DDR BOARD DELAY0 + 0.082 + + + PCW_PACKAGE_DDR_BOARD_DELAY1 + PCW PACKAGE DDR BOARD DELAY1 + 0.070 + + + PCW_PACKAGE_DDR_BOARD_DELAY2 + PCW PACKAGE DDR BOARD DELAY2 + 0.318 + + + PCW_PACKAGE_DDR_BOARD_DELAY3 + PCW PACKAGE DDR BOARD DELAY3 + 0.433 + + + PCW_CPU_CPU_6X4X_MAX_RANGE + PCW CPU CPU 6X4X MAX RANGE + 667 + + + PCW_CRYSTAL_PERIPHERAL_FREQMHZ + PCW CRYSTAL PERIPHERAL FREQMHZ + 33.333333 + + + PCW_APU_PERIPHERAL_FREQMHZ + PCW APU PERIPHERAL FREQMHZ + 666.666666 + + + PCW_DCI_PERIPHERAL_FREQMHZ + PCW DCI PERIPHERAL FREQMHZ + 10.159 + + + PCW_QSPI_PERIPHERAL_FREQMHZ + PCW QSPI PERIPHERAL FREQMHZ + 200 + + + PCW_SMC_PERIPHERAL_FREQMHZ + PCW SMC PERIPHERAL FREQMHZ + 100 + + + + false + + + + + + PCW_USB0_PERIPHERAL_FREQMHZ + PCW USB0 PERIPHERAL FREQMHZ + 60 + + + + false + + + + + + PCW_USB1_PERIPHERAL_FREQMHZ + PCW USB1 PERIPHERAL FREQMHZ + 60 + + + + false + + + + + + PCW_SDIO_PERIPHERAL_FREQMHZ + PCW SDIO PERIPHERAL FREQMHZ + 100 + + + PCW_UART_PERIPHERAL_FREQMHZ + PCW UART PERIPHERAL FREQMHZ + 100 + + + PCW_SPI_PERIPHERAL_FREQMHZ + PCW SPI PERIPHERAL FREQMHZ + 166.666666 + + + PCW_CAN_PERIPHERAL_FREQMHZ + PCW CAN PERIPHERAL FREQMHZ + 100 + + + + false + + + + + + PCW_CAN0_PERIPHERAL_FREQMHZ + PCW CAN0 PERIPHERAL FREQMHZ + -1 + + + + false + + + + + + PCW_CAN1_PERIPHERAL_FREQMHZ + PCW CAN1 PERIPHERAL FREQMHZ + -1 + + + + false + + + + + + PCW_I2C_PERIPHERAL_FREQMHZ + PCW I2C PERIPHERAL FREQMHZ + 111.111115 + + + PCW_WDT_PERIPHERAL_FREQMHZ + PCW WDT PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC_PERIPHERAL_FREQMHZ + PCW TTC PERIPHERAL FREQMHZ + 50 + + + PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ + PCW TTC0 CLK0 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ + PCW TTC0 CLK1 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ + PCW TTC0 CLK2 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ + PCW TTC1 CLK0 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ + PCW TTC1 CLK1 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ + PCW TTC1 CLK2 PERIPHERAL FREQMHZ + 133.333333 + + + + false + + + + + + PCW_PCAP_PERIPHERAL_FREQMHZ + PCW PCAP PERIPHERAL FREQMHZ + 200 + + + PCW_TPIU_PERIPHERAL_FREQMHZ + PCW TPIU PERIPHERAL FREQMHZ + 200 + + + + false + + + + + + PCW_FPGA0_PERIPHERAL_FREQMHZ + PCW FPGA0 PERIPHERAL FREQMHZ + 50 + + + PCW_FPGA1_PERIPHERAL_FREQMHZ + PCW FPGA1 PERIPHERAL FREQMHZ + 100 + + + PCW_FPGA2_PERIPHERAL_FREQMHZ + PCW FPGA2 PERIPHERAL FREQMHZ + 50 + + + PCW_FPGA3_PERIPHERAL_FREQMHZ + PCW FPGA3 PERIPHERAL FREQMHZ + 50 + + + PCW_ACT_APU_PERIPHERAL_FREQMHZ + PCW ACT APU PERIPHERAL FREQMHZ + 666.666687 + + + PCW_UIPARAM_ACT_DDR_FREQ_MHZ + PCW UIPARAM ACT DDR FREQ MHZ + 533.333374 + + + PCW_ACT_DCI_PERIPHERAL_FREQMHZ + PCW ACT DCI PERIPHERAL FREQMHZ + 10.158730 + + + PCW_ACT_QSPI_PERIPHERAL_FREQMHZ + PCW ACT QSPI PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_SMC_PERIPHERAL_FREQMHZ + PCW ACT SMC PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_ENET0_PERIPHERAL_FREQMHZ + PCW ACT ENET0 PERIPHERAL FREQMHZ + 125.000000 + + + PCW_ACT_ENET1_PERIPHERAL_FREQMHZ + PCW ACT ENET1 PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_USB0_PERIPHERAL_FREQMHZ + PCW ACT USB0 PERIPHERAL FREQMHZ + 60 + + + PCW_ACT_USB1_PERIPHERAL_FREQMHZ + PCW ACT USB1 PERIPHERAL FREQMHZ + 60 + + + PCW_ACT_SDIO_PERIPHERAL_FREQMHZ + PCW ACT SDIO PERIPHERAL FREQMHZ + 100.000000 + + + PCW_ACT_UART_PERIPHERAL_FREQMHZ + PCW ACT UART PERIPHERAL FREQMHZ + 100.000000 + + + PCW_ACT_SPI_PERIPHERAL_FREQMHZ + PCW ACT SPI PERIPHERAL FREQMHZ + 166.666672 + + + PCW_ACT_CAN_PERIPHERAL_FREQMHZ + PCW ACT CAN PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_CAN0_PERIPHERAL_FREQMHZ + PCW ACT CAN0 PERIPHERAL FREQMHZ + 23.8095 + + + PCW_ACT_CAN1_PERIPHERAL_FREQMHZ + PCW ACT CAN0 PERIPHERAL FREQMHZ + 23.8095 + + + PCW_ACT_I2C_PERIPHERAL_FREQMHZ + PCW ACT I2C PERIPHERAL FREQMHZ + 50 + + + PCW_ACT_WDT_PERIPHERAL_FREQMHZ + PCW ACT WDT PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC_PERIPHERAL_FREQMHZ + PCW ACT TTC PERIPHERAL FREQMHZ + 50 + + + PCW_ACT_PCAP_PERIPHERAL_FREQMHZ + PCW ACT PCAP PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_TPIU_PERIPHERAL_FREQMHZ + PCW ACT TPIU PERIPHERAL FREQMHZ + 200.000000 + + + PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ + PCW ACT FPGA0 PERIPHERAL FREQMHZ + 50.000000 + + + PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ + PCW ACT FPGA1 PERIPHERAL FREQMHZ + 100.000000 + + + PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ + PCW ACT FPGA2 PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ + PCW ACT FPGA3 PERIPHERAL FREQMHZ + 10.000000 + + + PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK0 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK1 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ + PCW ACT TTC0 CLK2 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK0 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK1 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ + PCW ACT TTC1 CLK2 PERIPHERAL FREQMHZ + 111.111115 + + + PCW_CLK0_FREQ + PCW CLK0 FREQ + 50000000 + + + PCW_CLK1_FREQ + PCW CLK1 FREQ + 100000000 + + + PCW_CLK2_FREQ + PCW CLK2 FREQ + 10000000 + + + PCW_CLK3_FREQ + PCW CLK3 FREQ + 10000000 + + + PCW_OVERRIDE_BASIC_CLOCK + PCW OVERRIDE FREQ + 0 + + + PCW_CPU_PERIPHERAL_DIVISOR0 + CLKPARAM + 2 + + + + false + + + + + + PCW_DDR_PERIPHERAL_DIVISOR0 + CLKPARAM + 2 + + + + false + + + + + + PCW_SMC_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_QSPI_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_SDIO_PERIPHERAL_DIVISOR0 + CLKPARAM + 10 + + + + false + + + + + + PCW_UART_PERIPHERAL_DIVISOR0 + CLKPARAM + 10 + + + + false + + + + + + PCW_SPI_PERIPHERAL_DIVISOR0 + CLKPARAM + 6 + + + + false + + + + + + PCW_CAN_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_CAN_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_FCLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_FCLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK3_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK0_PERIPHERAL_DIVISOR1 + CLKPARAM + 4 + + + + false + + + + + + PCW_FCLK1_PERIPHERAL_DIVISOR1 + CLKPARAM + 2 + + + + false + + + + + + PCW_FCLK2_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_FCLK3_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET0_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_ENET1_PERIPHERAL_DIVISOR1 + CLKPARAM + 1 + + + + false + + + + + + PCW_TPIU_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + + false + + + + + + PCW_DCI_PERIPHERAL_DIVISOR0 + CLKPARAM + 15 + + + + false + + + + + + PCW_DCI_PERIPHERAL_DIVISOR1 + CLKPARAM + 7 + + + + false + + + + + + PCW_PCAP_PERIPHERAL_DIVISOR0 + CLKPARAM + 5 + + + + false + + + + + + PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_WDT_PERIPHERAL_DIVISOR0 + CLKPARAM + 1 + + + PCW_ARMPLL_CTRL_FBDIV + CLKPARAM + 40 + + + + false + + + + + + PCW_IOPLL_CTRL_FBDIV + CLKPARAM + 30 + + + + false + + + + + + PCW_DDRPLL_CTRL_FBDIV + CLKPARAM + 32 + + + + false + + + + + + PCW_CPU_CPU_PLL_FREQMHZ + CLKPARAM + 1333.333 + + + + false + + + + + + PCW_IO_IO_PLL_FREQMHZ + CLKPARAM + 1000.000 + + + + false + + + + + + PCW_DDR_DDR_PLL_FREQMHZ + CLKPARAM + 1066.667 + + + + false + + + + + + PCW_SMC_PERIPHERAL_VALID + PCW SMC PERIPHERAL VALID + 0 + + + PCW_SDIO_PERIPHERAL_VALID + PCW SDIO PERIPHERAL VALID + 1 + + + PCW_SPI_PERIPHERAL_VALID + PCW SPI PERIPHERAL VALID + 1 + + + PCW_CAN_PERIPHERAL_VALID + PCW CAN PERIPHERAL VALID + 0 + + + PCW_UART_PERIPHERAL_VALID + PCW UART PERIPHERAL VALID + 1 + + + PCW_EN_EMIO_CAN0 + PCW EN EMIO CAN0 + 0 + + + PCW_EN_EMIO_CAN1 + PCW EN EMIO CAN1 + 0 + + + PCW_EN_EMIO_ENET0 + PCW EN EMIO ENET0 + 0 + + + PCW_EN_EMIO_ENET1 + PCW EN EMIO ENET1 + 0 + + + PCW_EN_PTP_ENET0 + PCW EN PTP ENET0 + 0 + + + PCW_EN_PTP_ENET1 + PCW EN PTP ENET1 + 0 + + + PCW_EN_EMIO_GPIO + PCW EN EMIO GPIO + 1 + + + PCW_EN_EMIO_I2C0 + PCW EN EMIO I2C0 + 1 + + + PCW_EN_EMIO_I2C1 + PCW EN EMIO I2C1 + 0 + + + PCW_EN_EMIO_PJTAG + PCW EN EMIO PJTAG + 0 + + + PCW_EN_EMIO_SDIO0 + PCW EN EMIO SDIO0 + 1 + + + PCW_EN_EMIO_CD_SDIO0 + PCW EN EMIO CD SDIO0 + 1 + + + PCW_EN_EMIO_WP_SDIO0 + PCW EN EMIO WP SDIO0 + 1 + + + PCW_EN_EMIO_SDIO1 + PCW EN EMIO SDIO1 + 0 + + + PCW_EN_EMIO_CD_SDIO1 + PCW EN EMIO CD SDIO1 + 0 + + + PCW_EN_EMIO_WP_SDIO1 + PCW EN EMIO WP SDIO1 + 0 + + + PCW_EN_EMIO_SPI0 + PCW EN EMIO SPI0 + 1 + + + PCW_EN_EMIO_SPI1 + PCW EN EMIO SPI1 + 1 + + + PCW_EN_EMIO_UART0 + PCW EN EMIO UART0 + 1 + + + PCW_EN_EMIO_UART1 + PCW EN EMIO UART1 + 0 + + + PCW_EN_EMIO_MODEM_UART0 + PCW EN EMIO MODEM UART0 + 0 + + + PCW_EN_EMIO_MODEM_UART1 + PCW EN EMIO MODEM UART1 + 0 + + + PCW_EN_EMIO_TTC0 + PCW EN EMIO TTC0 + 1 + + + PCW_EN_EMIO_TTC1 + PCW EN EMIO TTC1 + 1 + + + PCW_EN_EMIO_WDT + PCW EN EMIO WDT + 0 + + + PCW_EN_EMIO_TRACE + PCW EN EMIO TRACE + 0 + + + PCW_USE_AXI_NONSECURE + PCW USE AXI NON SECURE + 0 + + + PCW_USE_M_AXI_GP0 + PCW USE M AXI GP0 + 1 + + + PCW_USE_M_AXI_GP1 + PCW USE M AXI GP1 + 0 + + + PCW_USE_S_AXI_GP0 + PCW USE S AXI GP0 + 0 + + + PCW_USE_S_AXI_GP1 + PCW USE S AXI GP1 + 0 + + + PCW_USE_S_AXI_ACP + PCW USE S AXI ACP + 0 + + + PCW_USE_S_AXI_HP0 + PCW USE S AXI HP0 + 0 + + + PCW_USE_S_AXI_HP1 + PCW USE S AXI HP1 + 0 + + + PCW_USE_S_AXI_HP2 + PCW USE S AXI HP2 + 0 + + + PCW_USE_S_AXI_HP3 + PCW USE S AXI HP3 + 0 + + + PCW_M_AXI_GP0_FREQMHZ + PCW M AXI GP0 FREQMHZ + 50 + + + + true + + + + + + PCW_M_AXI_GP1_FREQMHZ + PCW M AXI GP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_GP0_FREQMHZ + PCW S AXI GP0 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_GP1_FREQMHZ + PCW S AXI GP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_ACP_FREQMHZ + PCW S AXI ACP FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_HP0_FREQMHZ + PCW S AXI HP0 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_HP1_FREQMHZ + PCW S AXI HP1 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_HP2_FREQMHZ + PCW S AXI HP2 FREQMHZ + 10 + + + + false + + + + + + PCW_S_AXI_HP3_FREQMHZ + PCW S AXI HP3 FREQMHZ + 10 + + + + false + + + + + + PCW_USE_DMA0 + PCW USE DMA0 + 0 + + + PCW_USE_DMA1 + PCW USE DMA1 + 0 + + + PCW_USE_DMA2 + PCW USE DMA2 + 0 + + + PCW_USE_DMA3 + PCW USE DMA3 + 0 + + + PCW_USE_TRACE + PCW USE TRACE + Enable FTM Trace interface used to capture data from PL to PS debug system + 0 + + + PCW_TRACE_PIPELINE_WIDTH + PCW TRACE PIPELINE WIDTH + 8 + + + + false + + + + + + PCW_INCLUDE_TRACE_BUFFER + PCW INCLUDE TRACE BUFFER + 0 + + + + false + + + + + + PCW_TRACE_BUFFER_FIFO_SIZE + PCW TRACE BUFFER FIFO SIZE + 128 + + + + false + + + + + + PCW_USE_TRACE_DATA_EDGE_DETECTOR + PCW USE TRACE DATA EDGE DETECTOR + 0 + + + + false + + + + + + PCW_TRACE_BUFFER_CLOCK_DELAY + PCW TRACE BUFFER CLOCK DELAY + 12 + + + + false + + + + + + PCW_USE_CROSS_TRIGGER + PCW USE CROSS TRIGGER + 0 + + + PCW_FTM_CTI_IN0 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN1 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN2 + <Select> + + + + false + + + + + + PCW_FTM_CTI_IN3 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT0 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT1 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT2 + <Select> + + + + false + + + + + + PCW_FTM_CTI_OUT3 + <Select> + + + + false + + + + + + PCW_USE_DEBUG + PCW USE DEBUG + 0 + + + PCW_USE_CR_FABRIC + PCW USE CR FABRIC + 1 + + + PCW_USE_AXI_FABRIC_IDLE + PCW USE AXI FABRIC IDLE + Enables idle AXI signal to the PS used to indicate that there are no outstanding AXI transactions in the PL + 0 + + + PCW_USE_DDR_BYPASS + PCW USE DDR BYPASS + Enables DDR urgent/arb signal used to signal a critical memory starvation situation to the DDR arbitration for the four AXI ports of the PS DDR memory controller + 0 + + + PCW_USE_FABRIC_INTERRUPT + PCW USE FABRIC INTERRUPT + 1 + + + PCW_USE_PROC_EVENT_BUS + PCW USE PROC EVENT BUS + 0 + + + PCW_USE_EXPANDED_IOP + PCW USE EXPANDED IOP + 0 + + + PCW_USE_HIGH_OCM + PCW USE HIGH OCM + 0 + + + PCW_USE_PS_SLCR_REGISTERS + PCW USE PS SLCR REGISTERS + 0 + + + PCW_USE_EXPANDED_PS_SLCR_REGISTERS + PCW USE EXPANDED PS SLCR REGISTERS + 0 + + + + false + + + + + + PCW_USE_CORESIGHT + PCW USE CORESIGHT + 0 + + + PCW_EN_EMIO_SRAM_INT + PCW EN EMIO SRAM INT + 0 + + + PCW_GPIO_EMIO_GPIO_WIDTH + PCW EMIO GPIO WIDTH + 64 + + + + true + + + + + + PCW_GP0_NUM_WRITE_THREADS + GP0 NUM WRITE THREADS + 4 + + + PCW_GP0_NUM_READ_THREADS + GP0 NUM READ THREADS + 4 + + + PCW_GP1_NUM_WRITE_THREADS + GP1 NUM WRITE THREADS + 4 + + + PCW_GP1_NUM_READ_THREADS + GP1 NUM READ THREADS + 4 + + + PCW_UART0_BAUD_RATE + PCW UART0 BAUD RATE + Configure baud rate to determine UART0 operating frequency + 115200 + + + + true + + + + + + PCW_UART1_BAUD_RATE + PCW UART1 BAUD RATE + Configure baud rate to determine UART1 operating frequency + 115200 + + + + true + + + + + + PCW_EN_4K_TIMER + PCW EN 4K TIMER + 0 + + + PCW_M_AXI_GP0_ID_WIDTH + PCW M AXI GP0 ID WIDTH + 12 + + + + true + + + + + + PCW_M_AXI_GP0_ENABLE_STATIC_REMAP + PCW M AXI GP0 ENABLE STATIC REMAP + 0 + + + + true + + + + + + PCW_M_AXI_GP0_SUPPORT_NARROW_BURST + PCW M AXI GP0 SUPPORT NARROW BURST + 0 + + + + true + + + + + + PCW_M_AXI_GP0_THREAD_ID_WIDTH + PCW M AXI GP0 THREAD ID WIDTH + 12 + + + + true + + + + + + PCW_M_AXI_GP1_ID_WIDTH + PCW M AXI GP1 ID WIDTH + 12 + + + + false + + + + + + PCW_M_AXI_GP1_ENABLE_STATIC_REMAP + PCW M AXI GP1 ENABLE STATIC REMAP + 0 + + + + false + + + + + + PCW_M_AXI_GP1_SUPPORT_NARROW_BURST + PCW M AXI GP1 SUPPORT NARROW BURST + 0 + + + + false + + + + + + PCW_M_AXI_GP1_THREAD_ID_WIDTH + PCW M AXI GP1 THREAD ID WIDTH + 12 + + + + false + + + + + + PCW_S_AXI_GP0_ID_WIDTH + PCW S AXI GP0 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_GP1_ID_WIDTH + PCW S AXI GP1 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_ACP_ID_WIDTH + PCW S AXI ACP ID WIDTH + 3 + + + + false + + + + + + PCW_INCLUDE_ACP_TRANS_CHECK + PCW INCLUDE ACP TRANS CHECK + 0 + + + PCW_USE_DEFAULT_ACP_USER_VAL + PCW USE DEFAULT ACP USER VAL + 0 + + + + false + + + + + + PCW_S_AXI_ACP_ARUSER_VAL + PCW S AXI ACP ARUSER VAL + 31 + + + + false + + + + + + PCW_S_AXI_ACP_AWUSER_VAL + PCW S AXI ACP AWUSER VAL + 31 + + + + false + + + + + + PCW_S_AXI_HP0_ID_WIDTH + PCW S AXI HP0 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP0_DATA_WIDTH + PCW S AXI HP0 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP1_ID_WIDTH + PCW S AXI HP1 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP1_DATA_WIDTH + PCW S AXI HP1 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP2_ID_WIDTH + PCW S AXI HP2 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP2_DATA_WIDTH + PCW S AXI HP2 DATA WIDTH + 64 + + + + true + + + + + + PCW_S_AXI_HP3_ID_WIDTH + PCW S AXI HP3 ID WIDTH + 6 + + + + false + + + + + + PCW_S_AXI_HP3_DATA_WIDTH + PCW S AXI HP3 DATA WIDTH + 64 + + + + true + + + + + + PCW_NUM_F2P_INTR_INPUTS + PCW NUM F2P INTR INPUTS + 1 + + + + true + + + + + + PCW_EN_DDR + PCW EN DDR + 1 + + + PCW_EN_SMC + PCW EN SMC + 0 + + + PCW_EN_QSPI + PCW EN QSPI + 1 + + + PCW_EN_CAN0 + PCW EN CAN0 + 0 + + + PCW_EN_CAN1 + PCW EN CAN1 + 0 + + + PCW_EN_ENET0 + PCW EN ENET0 + 0 + + + PCW_EN_ENET1 + PCW EN ENET1 + 0 + + + PCW_EN_GPIO + PCW EN GPIO + 1 + + + PCW_EN_I2C0 + PCW EN I2C0 + 1 + + + PCW_EN_I2C1 + PCW EN I2C1 + 1 + + + PCW_EN_PJTAG + PCW EN PJTAG + 0 + + + PCW_EN_SDIO0 + PCW EN SDIO0 + 1 + + + PCW_EN_SDIO1 + PCW EN SDIO1 + 1 + + + PCW_EN_SPI0 + PCW EN SPI0 + 1 + + + PCW_EN_SPI1 + PCW EN SPI1 + 1 + + + PCW_EN_UART0 + PCW EN UART0 + 1 + + + PCW_EN_UART1 + PCW EN UART1 + 1 + + + PCW_EN_MODEM_UART0 + PCW EN MODEM UART0 + 0 + + + PCW_EN_MODEM_UART1 + PCW EN MODEM UART1 + 0 + + + PCW_EN_TTC0 + PCW EN TTC0 + 1 + + + PCW_EN_TTC1 + PCW EN TTC1 + 1 + + + PCW_EN_WDT + PCW EN WDT + 0 + + + PCW_EN_TRACE + PCW EN TRACE + 0 + + + PCW_EN_USB0 + PCW EN USB0 + 1 + + + PCW_EN_USB1 + PCW EN USB1 + 0 + + + PCW_DQ_WIDTH + PCW DQ WIDTH + 16 + + + PCW_DQS_WIDTH + PCW DQS WIDTH + 2 + + + PCW_DM_WIDTH + PCW DM WIDTH + 2 + + + PCW_MIO_PRIMITIVE + PCW MIO PRIMITIVE + 32 + + + PCW_EN_CLK0_PORT + PCW EN CLK0 PORT + 1 + + + + true + + + + + + PCW_EN_CLK1_PORT + PCW EN CLK1 PORT + 1 + + + + true + + + + + + PCW_EN_CLK2_PORT + PCW EN CLK2 PORT + 0 + + + + true + + + + + + PCW_EN_CLK3_PORT + PCW EN CLK3 PORT + 0 + + + + true + + + + + + PCW_EN_RST0_PORT + PCW EN RST0 PORT + Enables general purpose reset signal 0 for PL logic + 1 + + + + true + + + + + + PCW_EN_RST1_PORT + PCW EN RST1 PORT + Enables general purpose reset signal 1 for PL logic + 0 + + + + true + + + + + + PCW_EN_RST2_PORT + PCW EN RST2 PORT + Enables general purpose reset signal 2 for PL logic + 0 + + + + true + + + + + + PCW_EN_RST3_PORT + PCW EN RST3 PORT + Enables general purpose reset signal 3 for PL logic + 0 + + + + true + + + + + + PCW_EN_CLKTRIG0_PORT + PCW EN CLKTRIG0 PORT + Enables PL clock trigger signal 0 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG1_PORT + PCW EN CLKTRIG1 PORT + Enables PL clock trigger signal 1 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG2_PORT + PCW EN CLKTRIG2 PORT + Enables PL clock trigger signal 2 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_EN_CLKTRIG3_PORT + PCW EN CLKTRIG3 PORT + Enables PL clock trigger signal 3 used to halt the PL clock when counting a programmed number of clock pulses + 0 + + + + true + + + + + + PCW_P2F_DMAC_ABORT_INTR + PCW P2F DMAC ABORT INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC0_INTR + PCW P2F DMAC0 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC1_INTR + PCW P2F DMAC1 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC2_INTR + PCW P2F DMAC2 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC3_INTR + PCW P2F DMAC3 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC4_INTR + PCW P2F DMAC4 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC5_INTR + PCW P2F DMAC5 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC6_INTR + PCW P2F DMAC6 INTR + 0 + + + + false + + + + + + PCW_P2F_DMAC7_INTR + PCW P2F DMAC7 INTR + 0 + + + + false + + + + + + PCW_P2F_SMC_INTR + PCW P2F SMC INTR + 0 + + + + false + + + + + + PCW_P2F_QSPI_INTR + PCW P2F QSPI INTR + 0 + + + + true + + + + + + PCW_P2F_CTI_INTR + PCW P2F CTI INTR + 0 + + + + false + + + + + + PCW_P2F_GPIO_INTR + PCW P2F GPIO INTR + 0 + + + + true + + + + + + PCW_P2F_USB0_INTR + PCW P2F USB0 INTR + 0 + + + + true + + + + + + PCW_P2F_ENET0_INTR + PCW P2F ENET0 INTR + 0 + + + + false + + + + + + PCW_P2F_SDIO0_INTR + PCW P2F SDIO0 INTR + 0 + + + + true + + + + + + PCW_P2F_I2C0_INTR + PCW P2F I2C0 INTR + 0 + + + + true + + + + + + PCW_P2F_SPI0_INTR + PCW P2F SPI0 INTR + 0 + + + + true + + + + + + PCW_P2F_UART0_INTR + PCW P2F UART0 INTR + 0 + + + + true + + + + + + PCW_P2F_CAN0_INTR + PCW P2F CAN0 INTR + 0 + + + + false + + + + + + PCW_P2F_USB1_INTR + PCW P2F USB1 INTR + 0 + + + + false + + + + + + PCW_P2F_ENET1_INTR + PCW P2F ENET1 INTR + 0 + + + + false + + + + + + PCW_P2F_SDIO1_INTR + PCW P2F SDIO1 INTR + 0 + + + + true + + + + + + PCW_P2F_I2C1_INTR + PCW P2F I2C1 INTR + 0 + + + + true + + + + + + PCW_P2F_SPI1_INTR + PCW P2F SPI1 INTR + 0 + + + + true + + + + + + PCW_P2F_UART1_INTR + PCW P2F UART1 INTR + 0 + + + + true + + + + + + PCW_P2F_CAN1_INTR + PCW P2F CAN1 INTR + 0 + + + + false + + + + + + PCW_IRQ_F2P_INTR + PCW IRQ F2P INTR + 1 + + + + true + + + + + + PCW_IRQ_F2P_MODE + PCW IRQ F2P MODE + DIRECT + + + + true + + + + + + PCW_CORE0_FIQ_INTR + PCW CORE0 FIQ INTR + 0 + + + + true + + + + + + PCW_CORE0_IRQ_INTR + PCW CORE0 IRQ INTR + 0 + + + + true + + + + + + PCW_CORE1_FIQ_INTR + PCW CORE1 FIQ INTR + 0 + + + + true + + + + + + PCW_CORE1_IRQ_INTR + PCW CORE1 IRQ INTR + 0 + + + + true + + + + + + PCW_VALUE_SILVERSION + PCW VALUE SILVERSION + 3 + + + PCW_GP0_EN_MODIFIABLE_TXN + PCW GP0 EN MODIFIABLE TXN + 1 + + + PCW_GP1_EN_MODIFIABLE_TXN + PCW GP1 EN MODIFIABLE TXN + 1 + + + PCW_IMPORT_BOARD_PRESET + PCW IMPORT BOARD PRESET + None + + + PCW_PERIPHERAL_BOARD_PRESET + PCW PERIPHERAL BOARD PRESET + None + + + PCW_PRESET_BANK0_VOLTAGE + PCW PRESET BANK0 VOLTAGE + LVCMOS 3.3V + + + PCW_PRESET_BANK1_VOLTAGE + PCW PRESET BANK1 VOLTAGE + LVCMOS 3.3V + + + PCW_UIPARAM_DDR_ENABLE + PCW UIPARAM DDR ENABLE + 1 + + + PCW_UIPARAM_DDR_ADV_ENABLE + PCW UIPARAM DDR ADV ENABLE + 0 + + + PCW_UIPARAM_DDR_MEMORY_TYPE + PCW UIPARAM DDR MEMORY TYPE + DDR 3 (Low Voltage) + + + PCW_UIPARAM_DDR_ECC + PCW UIPARAM DDR ECC + Disabled + + + + false + + + + + + PCW_UIPARAM_DDR_BUS_WIDTH + PCW UIPARAM DDR BUS WIDTH + 16 Bit + + + PCW_UIPARAM_DDR_BL + PCW UIPARAM DDR BL + 8 + + + PCW_UIPARAM_DDR_HIGH_TEMP + PCW UIPARAM DDR HIGH TEMP + Normal (0-85) + + + PCW_UIPARAM_DDR_PARTNO + PCW UIPARAM DDR PARTNO + MT41J256M16 RE-125 + + + PCW_UIPARAM_DDR_DRAM_WIDTH + PCW UIPARAM DDR DRAM WIDTH + 16 Bits + + + + false + + + + + + PCW_UIPARAM_DDR_DEVICE_CAPACITY + PCW UIPARAM DDR DEVICE CAPACITY + 4096 MBits + + + + false + + + + + + PCW_UIPARAM_DDR_SPEED_BIN + PCW UIPARAM DDR SPEED BIN + DDR3_1066F + + + + false + + + + + + PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL + PCW UIPARAM DDR TRAIN WRITE LEVEL + 1 + + + PCW_UIPARAM_DDR_TRAIN_READ_GATE + PCW UIPARAM DDR TRAIN READ GATE + 1 + + + PCW_UIPARAM_DDR_TRAIN_DATA_EYE + PCW UIPARAM DDR TRAIN DATA EYE + 1 + + + PCW_UIPARAM_DDR_CLOCK_STOP_EN + PCW UIPARAM DDR CLOCK STOP EN + 0 + + + PCW_UIPARAM_DDR_USE_INTERNAL_VREF + PCW UIPARAM DDR USE INTERNAL VREF + 0 + + + PCW_DDR_PRIORITY_WRITEPORT_0 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_1 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_2 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_WRITEPORT_3 + PCW DDR PRIORITY WRITEPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_0 + PCW DDR PRIORITY READPORT 0 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_1 + PCW DDR PRIORITY READPORT 1 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_2 + PCW DDR PRIORITY READPORT 2 + <Select> + + + + false + + + + + + PCW_DDR_PRIORITY_READPORT_3 + PCW DDR PRIORITY READPORT 3 + <Select> + + + + false + + + + + + PCW_DDR_PORT0_HPR_ENABLE + PCW DDR PORT0 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT1_HPR_ENABLE + PCW DDR PORT1 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT2_HPR_ENABLE + PCW DDR PORT2 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_PORT3_HPR_ENABLE + PCW DDR PORT3 ENABLE HPR + 0 + + + + false + + + + + + PCW_DDR_HPRLPR_QUEUE_PARTITION + PCW DDR HPRLPR QUEUE PARTITION + HPR(0)/LPR(32) + + + + false + + + + + + PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR LPR TO CRITICAL PRIORITY LEVEL + 2 + + + + false + + + + + + PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR HPR TO CRITICAL PRIORITY LEVEL + 15 + + + + false + + + + + + PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL + PCW DDR WRITE TO CRITICAL PRIORITY LEVEL + 2 + + + + false + + + + + + PCW_NAND_PERIPHERAL_ENABLE + PCW NAND PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_NAND_NAND_IO + PCW NAND NAND IO + <Select> + + + + false + + + + + + PCW_NAND_GRP_D8_ENABLE + 0 + + + + false + + + + + + PCW_NAND_GRP_D8_IO + PCW NAND GRP D8 IO + <Select> + + + + false + + + + + + PCW_NOR_PERIPHERAL_ENABLE + PCW NOR PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_NOR_NOR_IO + PCW NOR NOR IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_A25_ENABLE + PCW NOR GRP A25 IO + 0 + + + + false + + + + + + PCW_NOR_GRP_A25_IO + PCW NOR GRP CS0 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_CS0_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_CS0_IO + PCW NOR GRP CS1 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS0_ENABLE + PCW NOR GRP SRAM CS0 ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS0_IO + PCW NOR GRP SRAM CS1 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_CS1_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_CS1_IO + PCW NOR GRP SRAM CS0 IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS1_ENABLE + PCW NOR GRP SRAM CS1 ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_CS1_IO + <Select> + + + + false + + + + + + PCW_NOR_GRP_SRAM_INT_ENABLE + 0 + + + + false + + + + + + PCW_NOR_GRP_SRAM_INT_IO + <Select> + + + + false + + + + + + PCW_QSPI_PERIPHERAL_ENABLE + PCW QSPI PERIPHERAL ENABLE + 1 + + + PCW_QSPI_QSPI_IO + PCW QSPI QSPI IO + MIO 1 .. 6 + + + PCW_QSPI_GRP_SINGLE_SS_ENABLE + PCW QSPI GRP SINGLE SS ENABLE + 1 + + + PCW_QSPI_GRP_SINGLE_SS_IO + PCW QSPI GRP SINGLE SS IO + MIO 1 .. 6 + + + PCW_QSPI_GRP_SS1_ENABLE + 0 + + + PCW_QSPI_GRP_SS1_IO + PCW QSPI GRP SS1 IO + <Select> + + + + false + + + + + + PCW_SINGLE_QSPI_DATA_MODE + Single QSPI Data Mode + x4 + + + PCW_DUAL_STACK_QSPI_DATA_MODE + Dual Stack QSPI Data Mode + <Select> + + + + false + + + + + + PCW_DUAL_PARALLEL_QSPI_DATA_MODE + Dual Parallel QSPI Data Mode + <Select> + + + + false + + + + + + PCW_QSPI_GRP_IO1_ENABLE + 0 + + + PCW_QSPI_GRP_IO1_IO + PCW QSPI GRP IO1 IO + <Select> + + + + false + + + + + + PCW_QSPI_GRP_FBCLK_ENABLE + 0 + + + PCW_QSPI_GRP_FBCLK_IO + PCW QSPI GRP FBCLK IO + <Select> + + + + false + + + + + + PCW_QSPI_INTERNAL_HIGHADDRESS + PCW QSPI INTERNAL HIGHADDRESS + 0xFCFFFFFF + + + PCW_ENET0_PERIPHERAL_ENABLE + PCW ENET0 PERIPHERAL ENABLE + 0 + + + PCW_ENET0_ENET0_IO + PCW ENET0 ENET0 IO + <Select> + + + + false + + + + + + PCW_ENET0_GRP_MDIO_ENABLE + 0 + + + + false + + + + + + PCW_ENET0_GRP_MDIO_IO + PCW ENET0 GRP MDIO IO + <Select> + + + + false + + + + + + PCW_ENET_RESET_ENABLE + 0 + + + + false + + + + + + PCW_ENET_RESET_SELECT + <Select> + + + + false + + + + + + PCW_ENET0_RESET_ENABLE + 0 + + + + false + + + + + + PCW_ENET0_RESET_IO + <Select> + + + + false + + + + + + PCW_ENET1_PERIPHERAL_ENABLE + PCW ENET1 PERIPHERAL ENABLE + 0 + + + PCW_ENET1_ENET1_IO + PCW ENET1 ENET1 IO + <Select> + + + + false + + + + + + PCW_ENET1_GRP_MDIO_ENABLE + 0 + + + + false + + + + + + PCW_ENET1_GRP_MDIO_IO + PCW ENET1 GRP MDIO IO + <Select> + + + + false + + + + + + PCW_ENET1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_ENET1_RESET_IO + <Select> + + + + false + + + + + + PCW_SD0_PERIPHERAL_ENABLE + PCW SD0 PERIPHERAL ENABLE + 1 + + + PCW_SD0_SD0_IO + PCW SD0 SD0 IO + EMIO + + + PCW_SD0_GRP_CD_ENABLE + 1 + + + + false + + + + + + PCW_SD0_GRP_CD_IO + PCW SD0 GRP CD IO + EMIO + + + + false + + + + + + PCW_SD0_GRP_WP_ENABLE + 1 + + + + false + + + + + + PCW_SD0_GRP_WP_IO + PCW SD0 GRP WP IO + EMIO + + + + false + + + + + + PCW_SD0_GRP_POW_ENABLE + 0 + + + PCW_SD0_GRP_POW_IO + PCW SD0 GRP POW IO + <Select> + + + + false + + + + + + PCW_SD1_PERIPHERAL_ENABLE + PCW SD1 PERIPHERAL ENABLE + 1 + + + PCW_SD1_SD1_IO + PCW SD1 SD1 IO + MIO 10 .. 15 + + + PCW_SD1_GRP_CD_ENABLE + 1 + + + PCW_SD1_GRP_CD_IO + PCW SD1 GRP CD IO + MIO 0 + + + PCW_SD1_GRP_WP_ENABLE + 0 + + + PCW_SD1_GRP_WP_IO + PCW SD1 GRP WP IO + <Select> + + + + false + + + + + + PCW_SD1_GRP_POW_ENABLE + 0 + + + PCW_SD1_GRP_POW_IO + PCW SD1 GRP POW IO + <Select> + + + + false + + + + + + PCW_UART0_PERIPHERAL_ENABLE + PCW UART0 PERIPHERAL ENABLE + 1 + + + PCW_UART0_UART0_IO + PCW UART0 UART0 IO + EMIO + + + PCW_UART0_GRP_FULL_ENABLE + 0 + + + PCW_UART0_GRP_FULL_IO + <Select> + + + + false + + + + + + PCW_UART1_PERIPHERAL_ENABLE + PCW UART1 PERIPHERAL ENABLE + 1 + + + PCW_UART1_UART1_IO + PCW UART1 UART1 IO + MIO 8 .. 9 + + + PCW_UART1_GRP_FULL_ENABLE + 0 + + + PCW_UART1_GRP_FULL_IO + <Select> + + + + false + + + + + + PCW_SPI0_PERIPHERAL_ENABLE + PCW SPI0 PERIPHERAL ENABLE + 1 + + + PCW_SPI0_SPI0_IO + PCW SPI0 SPI0 IO + EMIO + + + PCW_SPI0_GRP_SS0_ENABLE + 1 + + + + false + + + + + + PCW_SPI0_GRP_SS0_IO + PCW SPI0 GRP SS0 IO + EMIO + + + + false + + + + + + PCW_SPI0_GRP_SS1_ENABLE + 1 + + + + false + + + + + + PCW_SPI0_GRP_SS1_IO + PCW SPI0 GRP SS1 IO + EMIO + + + + false + + + + + + PCW_SPI0_GRP_SS2_ENABLE + 1 + + + + false + + + + + + PCW_SPI0_GRP_SS2_IO + PCW SPI0 GRP SS2 IO + EMIO + + + + false + + + + + + PCW_SPI1_PERIPHERAL_ENABLE + PCW SPI1 PERIPHERAL ENABLE + 1 + + + PCW_SPI1_SPI1_IO + PCW SPI1 SPI1 IO + EMIO + + + PCW_SPI1_GRP_SS0_ENABLE + 1 + + + + false + + + + + + PCW_SPI1_GRP_SS0_IO + PCW SPI1 GRP SS0 IO + EMIO + + + + false + + + + + + PCW_SPI1_GRP_SS1_ENABLE + 1 + + + + false + + + + + + PCW_SPI1_GRP_SS1_IO + PCW SPI1 GRP SS1 IO + EMIO + + + + false + + + + + + PCW_SPI1_GRP_SS2_ENABLE + 1 + + + + false + + + + + + PCW_SPI1_GRP_SS2_IO + PCW SPI1 GRP SS2 IO + EMIO + + + + false + + + + + + PCW_CAN0_PERIPHERAL_ENABLE + PCW CAN0 PERIPHERAL ENABLE + 0 + + + PCW_CAN0_CAN0_IO + PCW CAN0 CAN0 IO + <Select> + + + + false + + + + + + PCW_CAN0_GRP_CLK_ENABLE + 0 + + + + false + + + + + + PCW_CAN0_GRP_CLK_IO + PCW CAN0 GRP CLK IO + <Select> + + + + false + + + + + + PCW_CAN1_PERIPHERAL_ENABLE + PCW CAN1 PERIPHERAL ENABLE + 0 + + + PCW_CAN1_CAN1_IO + PCW CAN1 CAN1 IO + <Select> + + + + false + + + + + + PCW_CAN1_GRP_CLK_ENABLE + 0 + + + + false + + + + + + PCW_CAN1_GRP_CLK_IO + PCW CAN1 GRP CLK IO + <Select> + + + + false + + + + + + PCW_TRACE_PERIPHERAL_ENABLE + PCW TRACE PERIPHERAL ENABLE + 0 + + + PCW_TRACE_TRACE_IO + PCW TRACE TRACE IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_2BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_2BIT_IO + PCW TRACE GRP 2BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_4BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_4BIT_IO + PCW TRACE GRP 4BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_8BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_8BIT_IO + PCW TRACE GRP 8BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_16BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_16BIT_IO + PCW TRACE GRP 16BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_GRP_32BIT_ENABLE + 0 + + + + false + + + + + + PCW_TRACE_GRP_32BIT_IO + PCW TRACE GRP 32BIT IO + <Select> + + + + false + + + + + + PCW_TRACE_INTERNAL_WIDTH + PCW TRACE INTERNAL WIDTH + 2 + + + PCW_WDT_PERIPHERAL_ENABLE + PCW WDT PERIPHERAL ENABLE + 0 + + + PCW_WDT_WDT_IO + PCW WDT WDT IO + <Select> + + + + false + + + + + + PCW_TTC0_PERIPHERAL_ENABLE + PCW TTC0 PERIPHERAL ENABLE + 1 + + + PCW_TTC0_TTC0_IO + PCW TTC0 TTC0 IO + EMIO + + + PCW_TTC1_PERIPHERAL_ENABLE + PCW TTC1 PERIPHERAL ENABLE + 1 + + + PCW_TTC1_TTC1_IO + PCW TTC1 TTC1 IO + EMIO + + + PCW_PJTAG_PERIPHERAL_ENABLE + PCW PJTAG PERIPHERAL ENABLE + 0 + + + PCW_PJTAG_PJTAG_IO + PCW PJTAG PJTAG IO + <Select> + + + + false + + + + + + PCW_USB0_PERIPHERAL_ENABLE + PCW USB0 PERIPHERAL ENABLE + 1 + + + PCW_USB0_USB0_IO + PCW USB0 USB0 IO + MIO 28 .. 39 + + + PCW_USB_RESET_ENABLE + 1 + + + PCW_USB_RESET_SELECT + Share reset pin + + + PCW_USB0_RESET_ENABLE + 1 + + + PCW_USB0_RESET_IO + MIO 7 + + + PCW_USB1_PERIPHERAL_ENABLE + PCW USB1 PERIPHERAL ENABLE + 0 + + + + false + + + + + + PCW_USB1_USB1_IO + PCW USB1 USB1 IO + <Select> + + + + false + + + + + + PCW_USB1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_USB1_RESET_IO + <Select> + + + + false + + + + + + PCW_I2C0_PERIPHERAL_ENABLE + PCW I2C0 PERIPHERAL ENABLE + 1 + + + PCW_I2C0_I2C0_IO + PCW I2C0 I2C0 IO + EMIO + + + PCW_I2C0_GRP_INT_ENABLE + 1 + + + + false + + + + + + PCW_I2C0_GRP_INT_IO + PCW I2C0 GRP INT IO + EMIO + + + + false + + + + + + PCW_I2C0_RESET_ENABLE + 0 + + + PCW_I2C0_RESET_IO + <Select> + + + PCW_I2C1_PERIPHERAL_ENABLE + PCW I2C1 PERIPHERAL ENABLE + 1 + + + PCW_I2C1_I2C1_IO + PCW I2C1 I2C1 IO + MIO 48 .. 49 + + + PCW_I2C1_GRP_INT_ENABLE + 1 + + + PCW_I2C1_GRP_INT_IO + PCW I2C1 GRP INT IO + EMIO + + + PCW_I2C_RESET_ENABLE + 1 + + + PCW_I2C_RESET_SELECT + Share reset pin + + + PCW_I2C1_RESET_ENABLE + 0 + + + + false + + + + + + PCW_I2C1_RESET_IO + <Select> + + + + false + + + + + + PCW_GPIO_PERIPHERAL_ENABLE + PCW GPIO PERIPHERAL ENABLE + 0 + + + PCW_GPIO_MIO_GPIO_ENABLE + 1 + + + PCW_GPIO_MIO_GPIO_IO + PCW GPIO MIO GPIO IO + MIO + + + PCW_GPIO_EMIO_GPIO_ENABLE + PCW GPIO EMIO GPIO ENABLE + 1 + + + PCW_GPIO_EMIO_GPIO_IO + PCW GPIO EMIO GPIO IO + 64 + + + PCW_APU_CLK_RATIO_ENABLE + PCW APU CLK RATIO ENABLE + 0.251400462962963 + + + PCW_ENET0_PERIPHERAL_FREQMHZ + PCW ENET0 PERIPHERAL FREQMHZ + 1000 Mbps + + + + false + + + + + + PCW_ENET1_PERIPHERAL_FREQMHZ + PCW ENET1 PERIPHERAL FREQMHZ + 1000 Mbps + + + + false + + + + + + PCW_CPU_PERIPHERAL_CLKSRC + PCW CPU PERIPHERAL CLKSRC + ARM PLL + + + PCW_DDR_PERIPHERAL_CLKSRC + PCW DDR PERIPHERAL CLKSRC + DDR PLL + + + PCW_SMC_PERIPHERAL_CLKSRC + PCW SMC PERIPHERAL CLKSRC + IO PLL + + + PCW_QSPI_PERIPHERAL_CLKSRC + PCW QSPI PERIPHERAL CLKSRC + IO PLL + + + PCW_SDIO_PERIPHERAL_CLKSRC + PCW SDIO PERIPHERAL CLKSRC + IO PLL + + + PCW_UART_PERIPHERAL_CLKSRC + PCW UART PERIPHERAL CLKSRC + IO PLL + + + PCW_SPI_PERIPHERAL_CLKSRC + PCW SPI PERIPHERAL CLKSRC + IO PLL + + + PCW_CAN_PERIPHERAL_CLKSRC + PCW CAN PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK0_PERIPHERAL_CLKSRC + PCW FCLK0 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK1_PERIPHERAL_CLKSRC + PCW FCLK1 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK2_PERIPHERAL_CLKSRC + PCW FCLK2 PERIPHERAL CLKSRC + IO PLL + + + PCW_FCLK3_PERIPHERAL_CLKSRC + PCW FCLK3 PERIPHERAL CLKSRC + IO PLL + + + PCW_ENET0_PERIPHERAL_CLKSRC + PCW ENET0 PERIPHERAL CLKSRC + External + + + PCW_ENET1_PERIPHERAL_CLKSRC + PCW ENET1 PERIPHERAL CLKSRC + IO PLL + + + PCW_CAN0_PERIPHERAL_CLKSRC + PCW CAN0 PERIPHERAL CLKSRC + External + + + PCW_CAN1_PERIPHERAL_CLKSRC + PCW CAN1 PERIPHERAL CLKSRC + External + + + PCW_TPIU_PERIPHERAL_CLKSRC + PCW TPIU PERIPHERAL CLKSRC + External + + + PCW_TTC0_CLK0_PERIPHERAL_CLKSRC + PCW TTC0 CLK0 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC0_CLK1_PERIPHERAL_CLKSRC + PCW TTC0 CLK1 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC0_CLK2_PERIPHERAL_CLKSRC + PCW TTC0 CLK2 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK0_PERIPHERAL_CLKSRC + PCW TTC1 CLK0 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK1_PERIPHERAL_CLKSRC + PCW TTC1 CLK1 PERIPHERAL CLKSRC + CPU_1X + + + PCW_TTC1_CLK2_PERIPHERAL_CLKSRC + PCW TTC1 CLK2 PERIPHERAL CLKSRC + CPU_1X + + + PCW_WDT_PERIPHERAL_CLKSRC + PCW WDT PERIPHERAL CLKSRC + CPU_1X + + + PCW_DCI_PERIPHERAL_CLKSRC + PCW DCI PERIPHERAL CLKSRC + DDR PLL + + + PCW_PCAP_PERIPHERAL_CLKSRC + PCW PCAP PERIPHERAL CLKSRC + IO PLL + + + PCW_USB_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_ENET_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_I2C_RESET_POLARITY + PCW USB RESET POLARITY + Active Low + + + PCW_MIO_0_PULLUP + PCW MIO 0 PULLUP + enabled + + + PCW_MIO_0_IOTYPE + PCW MIO 0 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_0_DIRECTION + PCW MIO 0 DIRECTION + in + + + + false + + + + + + PCW_MIO_0_SLEW + PCW MIO 0 SLEW + slow + + + PCW_MIO_1_PULLUP + PCW MIO 1 PULLUP + enabled + + + PCW_MIO_1_IOTYPE + PCW MIO 1 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_1_DIRECTION + PCW MIO 1 DIRECTION + out + + + + false + + + + + + PCW_MIO_1_SLEW + PCW MIO 1 SLEW + slow + + + PCW_MIO_2_PULLUP + PCW MIO 2 PULLUP + disabled + + + + false + + + + + + PCW_MIO_2_IOTYPE + PCW MIO 2 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_2_DIRECTION + PCW MIO 2 DIRECTION + inout + + + + false + + + + + + PCW_MIO_2_SLEW + PCW MIO 2 SLEW + slow + + + PCW_MIO_3_PULLUP + PCW MIO 3 PULLUP + disabled + + + + false + + + + + + PCW_MIO_3_IOTYPE + PCW MIO 3 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_3_DIRECTION + PCW MIO 3 DIRECTION + inout + + + + false + + + + + + PCW_MIO_3_SLEW + PCW MIO 3 SLEW + slow + + + PCW_MIO_4_PULLUP + PCW MIO 4 PULLUP + disabled + + + + false + + + + + + PCW_MIO_4_IOTYPE + PCW MIO 4 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_4_DIRECTION + PCW MIO 4 DIRECTION + inout + + + + false + + + + + + PCW_MIO_4_SLEW + PCW MIO 4 SLEW + slow + + + PCW_MIO_5_PULLUP + PCW MIO 5 PULLUP + disabled + + + + false + + + + + + PCW_MIO_5_IOTYPE + PCW MIO 5 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_5_DIRECTION + PCW MIO 5 DIRECTION + inout + + + + false + + + + + + PCW_MIO_5_SLEW + PCW MIO 5 SLEW + slow + + + PCW_MIO_6_PULLUP + PCW MIO 6 PULLUP + disabled + + + + false + + + + + + PCW_MIO_6_IOTYPE + PCW MIO 6 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_6_DIRECTION + PCW MIO 6 DIRECTION + out + + + + false + + + + + + PCW_MIO_6_SLEW + PCW MIO 6 SLEW + slow + + + PCW_MIO_7_PULLUP + PCW MIO 7 PULLUP + disabled + + + + false + + + + + + PCW_MIO_7_IOTYPE + PCW MIO 7 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_7_DIRECTION + PCW MIO 7 DIRECTION + out + + + + false + + + + + + PCW_MIO_7_SLEW + PCW MIO 7 SLEW + slow + + + PCW_MIO_8_PULLUP + PCW MIO 8 PULLUP + disabled + + + + false + + + + + + PCW_MIO_8_IOTYPE + PCW MIO 8 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_8_DIRECTION + PCW MIO 8 DIRECTION + out + + + + false + + + + + + PCW_MIO_8_SLEW + PCW MIO 8 SLEW + slow + + + PCW_MIO_9_PULLUP + PCW MIO 9 PULLUP + enabled + + + PCW_MIO_9_IOTYPE + PCW MIO 9 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_9_DIRECTION + PCW MIO 9 DIRECTION + in + + + + false + + + + + + PCW_MIO_9_SLEW + PCW MIO 9 SLEW + slow + + + PCW_MIO_10_PULLUP + PCW MIO 10 PULLUP + disabled + + + PCW_MIO_10_IOTYPE + PCW MIO 10 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_10_DIRECTION + PCW MIO 10 DIRECTION + inout + + + + false + + + + + + PCW_MIO_10_SLEW + PCW MIO 10 SLEW + slow + + + PCW_MIO_11_PULLUP + PCW MIO 11 PULLUP + disabled + + + PCW_MIO_11_IOTYPE + PCW MIO 11 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_11_DIRECTION + PCW MIO 11 DIRECTION + inout + + + + false + + + + + + PCW_MIO_11_SLEW + PCW MIO 11 SLEW + slow + + + PCW_MIO_12_PULLUP + PCW MIO 12 PULLUP + disabled + + + PCW_MIO_12_IOTYPE + PCW MIO 12 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_12_DIRECTION + PCW MIO 12 DIRECTION + inout + + + + false + + + + + + PCW_MIO_12_SLEW + PCW MIO 12 SLEW + slow + + + PCW_MIO_13_PULLUP + PCW MIO 13 PULLUP + disabled + + + PCW_MIO_13_IOTYPE + PCW MIO 13 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_13_DIRECTION + PCW MIO 13 DIRECTION + inout + + + + false + + + + + + PCW_MIO_13_SLEW + PCW MIO 13 SLEW + slow + + + PCW_MIO_14_PULLUP + PCW MIO 14 PULLUP + disabled + + + PCW_MIO_14_IOTYPE + PCW MIO 14 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_14_DIRECTION + PCW MIO 14 DIRECTION + inout + + + + false + + + + + + PCW_MIO_14_SLEW + PCW MIO 14 SLEW + slow + + + PCW_MIO_15_PULLUP + PCW MIO 15 PULLUP + disabled + + + PCW_MIO_15_IOTYPE + PCW MIO 15 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_15_DIRECTION + PCW MIO 15 DIRECTION + inout + + + + false + + + + + + PCW_MIO_15_SLEW + PCW MIO 15 SLEW + slow + + + PCW_MIO_16_PULLUP + PCW MIO 16 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_16_IOTYPE + PCW MIO 16 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_16_DIRECTION + PCW MIO 16 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_16_SLEW + PCW MIO 16 SLEW + <Select> + + + + false + + + + + + PCW_MIO_17_PULLUP + PCW MIO 17 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_17_IOTYPE + PCW MIO 17 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_17_DIRECTION + PCW MIO 17 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_17_SLEW + PCW MIO 17 SLEW + <Select> + + + + false + + + + + + PCW_MIO_18_PULLUP + PCW MIO 18 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_18_IOTYPE + PCW MIO 18 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_18_DIRECTION + PCW MIO 18 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_18_SLEW + PCW MIO 18 SLEW + <Select> + + + + false + + + + + + PCW_MIO_19_PULLUP + PCW MIO 19 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_19_IOTYPE + PCW MIO 19 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_19_DIRECTION + PCW MIO 19 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_19_SLEW + PCW MIO 19 SLEW + <Select> + + + + false + + + + + + PCW_MIO_20_PULLUP + PCW MIO 20 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_20_IOTYPE + PCW MIO 20 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_20_DIRECTION + PCW MIO 20 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_20_SLEW + PCW MIO 20 SLEW + <Select> + + + + false + + + + + + PCW_MIO_21_PULLUP + PCW MIO 21 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_21_IOTYPE + PCW MIO 21 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_21_DIRECTION + PCW MIO 21 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_21_SLEW + PCW MIO 21 SLEW + <Select> + + + + false + + + + + + PCW_MIO_22_PULLUP + PCW MIO 22 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_22_IOTYPE + PCW MIO 22 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_22_DIRECTION + PCW MIO 22 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_22_SLEW + PCW MIO 22 SLEW + <Select> + + + + false + + + + + + PCW_MIO_23_PULLUP + PCW MIO 23 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_23_IOTYPE + PCW MIO 23 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_23_DIRECTION + PCW MIO 23 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_23_SLEW + PCW MIO 23 SLEW + <Select> + + + + false + + + + + + PCW_MIO_24_PULLUP + PCW MIO 24 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_24_IOTYPE + PCW MIO 24 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_24_DIRECTION + PCW MIO 24 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_24_SLEW + PCW MIO 24 SLEW + <Select> + + + + false + + + + + + PCW_MIO_25_PULLUP + PCW MIO 25 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_25_IOTYPE + PCW MIO 25 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_25_DIRECTION + PCW MIO 25 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_25_SLEW + PCW MIO 25 SLEW + <Select> + + + + false + + + + + + PCW_MIO_26_PULLUP + PCW MIO 26 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_26_IOTYPE + PCW MIO 26 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_26_DIRECTION + PCW MIO 26 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_26_SLEW + PCW MIO 26 SLEW + <Select> + + + + false + + + + + + PCW_MIO_27_PULLUP + PCW MIO 27 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_27_IOTYPE + PCW MIO 27 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_27_DIRECTION + PCW MIO 27 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_27_SLEW + PCW MIO 27 SLEW + <Select> + + + + false + + + + + + PCW_MIO_28_PULLUP + PCW MIO 28 PULLUP + enabled + + + PCW_MIO_28_IOTYPE + PCW MIO 28 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_28_DIRECTION + PCW MIO 28 DIRECTION + inout + + + + false + + + + + + PCW_MIO_28_SLEW + PCW MIO 28 SLEW + slow + + + PCW_MIO_29_PULLUP + PCW MIO 29 PULLUP + enabled + + + PCW_MIO_29_IOTYPE + PCW MIO 29 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_29_DIRECTION + PCW MIO 29 DIRECTION + in + + + + false + + + + + + PCW_MIO_29_SLEW + PCW MIO 29 SLEW + slow + + + PCW_MIO_30_PULLUP + PCW MIO 30 PULLUP + enabled + + + PCW_MIO_30_IOTYPE + PCW MIO 30 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_30_DIRECTION + PCW MIO 30 DIRECTION + out + + + + false + + + + + + PCW_MIO_30_SLEW + PCW MIO 30 SLEW + slow + + + PCW_MIO_31_PULLUP + PCW MIO 31 PULLUP + enabled + + + PCW_MIO_31_IOTYPE + PCW MIO 31 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_31_DIRECTION + PCW MIO 31 DIRECTION + in + + + + false + + + + + + PCW_MIO_31_SLEW + PCW MIO 31 SLEW + slow + + + PCW_MIO_32_PULLUP + PCW MIO 32 PULLUP + enabled + + + PCW_MIO_32_IOTYPE + PCW MIO 32 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_32_DIRECTION + PCW MIO 32 DIRECTION + inout + + + + false + + + + + + PCW_MIO_32_SLEW + PCW MIO 32 SLEW + slow + + + PCW_MIO_33_PULLUP + PCW MIO 33 PULLUP + enabled + + + PCW_MIO_33_IOTYPE + PCW MIO 33 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_33_DIRECTION + PCW MIO 33 DIRECTION + inout + + + + false + + + + + + PCW_MIO_33_SLEW + PCW MIO 33 SLEW + slow + + + PCW_MIO_34_PULLUP + PCW MIO 34 PULLUP + enabled + + + PCW_MIO_34_IOTYPE + PCW MIO 34 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_34_DIRECTION + PCW MIO 34 DIRECTION + inout + + + + false + + + + + + PCW_MIO_34_SLEW + PCW MIO 34 SLEW + slow + + + PCW_MIO_35_PULLUP + PCW MIO 35 PULLUP + enabled + + + PCW_MIO_35_IOTYPE + PCW MIO 35 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_35_DIRECTION + PCW MIO 35 DIRECTION + inout + + + + false + + + + + + PCW_MIO_35_SLEW + PCW MIO 35 SLEW + slow + + + PCW_MIO_36_PULLUP + PCW MIO 36 PULLUP + enabled + + + PCW_MIO_36_IOTYPE + PCW MIO 36 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_36_DIRECTION + PCW MIO 36 DIRECTION + in + + + + false + + + + + + PCW_MIO_36_SLEW + PCW MIO 36 SLEW + slow + + + PCW_MIO_37_PULLUP + PCW MIO 37 PULLUP + enabled + + + PCW_MIO_37_IOTYPE + PCW MIO 37 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_37_DIRECTION + PCW MIO 37 DIRECTION + inout + + + + false + + + + + + PCW_MIO_37_SLEW + PCW MIO 37 SLEW + slow + + + PCW_MIO_38_PULLUP + PCW MIO 38 PULLUP + enabled + + + PCW_MIO_38_IOTYPE + PCW MIO 38 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_38_DIRECTION + PCW MIO 38 DIRECTION + inout + + + + false + + + + + + PCW_MIO_38_SLEW + PCW MIO 38 SLEW + slow + + + PCW_MIO_39_PULLUP + PCW MIO 39 PULLUP + enabled + + + PCW_MIO_39_IOTYPE + PCW MIO 39 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_39_DIRECTION + PCW MIO 39 DIRECTION + inout + + + + false + + + + + + PCW_MIO_39_SLEW + PCW MIO 39 SLEW + slow + + + PCW_MIO_40_PULLUP + PCW MIO 40 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_40_IOTYPE + PCW MIO 40 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_40_DIRECTION + PCW MIO 40 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_40_SLEW + PCW MIO 40 SLEW + <Select> + + + + false + + + + + + PCW_MIO_41_PULLUP + PCW MIO 41 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_41_IOTYPE + PCW MIO 41 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_41_DIRECTION + PCW MIO 41 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_41_SLEW + PCW MIO 41 SLEW + <Select> + + + + false + + + + + + PCW_MIO_42_PULLUP + PCW MIO 42 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_42_IOTYPE + PCW MIO 42 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_42_DIRECTION + PCW MIO 42 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_42_SLEW + PCW MIO 42 SLEW + <Select> + + + + false + + + + + + PCW_MIO_43_PULLUP + PCW MIO 43 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_43_IOTYPE + PCW MIO 43 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_43_DIRECTION + PCW MIO 43 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_43_SLEW + PCW MIO 43 SLEW + <Select> + + + + false + + + + + + PCW_MIO_44_PULLUP + PCW MIO 44 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_44_IOTYPE + PCW MIO 44 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_44_DIRECTION + PCW MIO 44 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_44_SLEW + PCW MIO 44 SLEW + <Select> + + + + false + + + + + + PCW_MIO_45_PULLUP + PCW MIO 45 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_45_IOTYPE + PCW MIO 45 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_45_DIRECTION + PCW MIO 45 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_45_SLEW + PCW MIO 45 SLEW + <Select> + + + + false + + + + + + PCW_MIO_46_PULLUP + PCW MIO 46 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_46_IOTYPE + PCW MIO 46 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_46_DIRECTION + PCW MIO 46 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_46_SLEW + PCW MIO 46 SLEW + <Select> + + + + false + + + + + + PCW_MIO_47_PULLUP + PCW MIO 47 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_47_IOTYPE + PCW MIO 47 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_47_DIRECTION + PCW MIO 47 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_47_SLEW + PCW MIO 47 SLEW + <Select> + + + + false + + + + + + PCW_MIO_48_PULLUP + PCW MIO 48 PULLUP + enabled + + + PCW_MIO_48_IOTYPE + PCW MIO 48 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_48_DIRECTION + PCW MIO 48 DIRECTION + inout + + + + false + + + + + + PCW_MIO_48_SLEW + PCW MIO 48 SLEW + slow + + + PCW_MIO_49_PULLUP + PCW MIO 49 PULLUP + enabled + + + PCW_MIO_49_IOTYPE + PCW MIO 49 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_49_DIRECTION + PCW MIO 49 DIRECTION + inout + + + + false + + + + + + PCW_MIO_49_SLEW + PCW MIO 49 SLEW + slow + + + PCW_MIO_50_PULLUP + PCW MIO 50 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_50_IOTYPE + PCW MIO 50 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_50_DIRECTION + PCW MIO 50 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_50_SLEW + PCW MIO 50 SLEW + <Select> + + + + false + + + + + + PCW_MIO_51_PULLUP + PCW MIO 51 PULLUP + <Select> + + + + false + + + + + + PCW_MIO_51_IOTYPE + PCW MIO 51 IOTYPE + <Select> + + + + false + + + + + + PCW_MIO_51_DIRECTION + PCW MIO 51 DIRECTION + <Select> + + + + false + + + + + + PCW_MIO_51_SLEW + PCW MIO 51 SLEW + <Select> + + + + false + + + + + + PCW_MIO_52_PULLUP + PCW MIO 52 PULLUP + enabled + + + PCW_MIO_52_IOTYPE + PCW MIO 52 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_52_DIRECTION + PCW MIO 52 DIRECTION + inout + + + + false + + + + + + PCW_MIO_52_SLEW + PCW MIO 52 SLEW + slow + + + PCW_MIO_53_PULLUP + PCW MIO 53 PULLUP + enabled + + + PCW_MIO_53_IOTYPE + PCW MIO 53 IOTYPE + LVCMOS 3.3V + + + PCW_MIO_53_DIRECTION + PCW MIO 53 DIRECTION + inout + + + + false + + + + + + PCW_MIO_53_SLEW + PCW MIO 53 SLEW + slow + + + preset + preset + None + + + PCW_UIPARAM_GENERATE_SUMMARY + PCW UIPARAM GENERATE SUMMARY + NONE + + + PCW_MIO_TREE_PERIPHERALS + PCW MIO TREE PERIPHERALS + SD 1#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#USB Reset#UART 1#UART 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#I2C 1#I2C 1#Unbonded#Unbonded#GPIO#GPIO + + + PCW_MIO_TREE_SIGNALS + PCW MIO TREE SIGNALS + cd#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#tx#rx#data[0]#cmd#clk#data[1]#data[2]#data[3]#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#Unbonded#scl#sda#Unbonded#Unbonded#gpio[52]#gpio[53] + + + PCW_PS7_SI_REV + PCW PS7 SI REV + PRODUCTION + + + PCW_FPGA_FCLK0_ENABLE + PCW FPGA FCLK0 ENABLE + 1 + + + + true + + + + + + PCW_FPGA_FCLK1_ENABLE + PCW FPGA FCLK1 ENABLE + 1 + + + + true + + + + + + PCW_FPGA_FCLK2_ENABLE + PCW FPGA FCLK2 ENABLE + 0 + + + + false + + + + + + PCW_FPGA_FCLK3_ENABLE + PCW FPGA FCLK3 ENABLE + 0 + + + + false + + + + + + PCW_NOR_SRAM_CS0_T_TR + PCW NOR SRAM CS0 T TR + 1 + + + PCW_NOR_SRAM_CS0_T_PC + PCW NOR SRAM CS0 T PC + 1 + + + PCW_NOR_SRAM_CS0_T_WP + PCW NOR SRAM CS0 T WP + 1 + + + PCW_NOR_SRAM_CS0_T_CEOE + PCW NOR SRAM CS0 T CEOE + 1 + + + PCW_NOR_SRAM_CS0_T_WC + PCW NOR SRAM CS0 T WC + 11 + + + PCW_NOR_SRAM_CS0_T_RC + PCW NOR SRAM CS0 T RC + 11 + + + PCW_NOR_SRAM_CS0_WE_TIME + PCW NOR SRAM CS0 WE TIME + 0 + + + PCW_NOR_SRAM_CS1_T_TR + PCW NOR SRAM CS1 T TR + 1 + + + PCW_NOR_SRAM_CS1_T_PC + PCW NOR SRAM CS1 T PC + 1 + + + PCW_NOR_SRAM_CS1_T_WP + PCW NOR SRAM CS1 T WP + 1 + + + PCW_NOR_SRAM_CS1_T_CEOE + PCW NOR SRAM CS1 T CEOE + 1 + + + PCW_NOR_SRAM_CS1_T_WC + PCW NOR SRAM CS1 T WC + 11 + + + PCW_NOR_SRAM_CS1_T_RC + PCW NOR SRAM CS1 T RC + 11 + + + PCW_NOR_SRAM_CS1_WE_TIME + PCW NOR SRAM CS1 WE TIME + 0 + + + PCW_NOR_CS0_T_TR + PCW NOR CS0 T TR + 1 + + + PCW_NOR_CS0_T_PC + PCW NOR CS0 T PC + 1 + + + PCW_NOR_CS0_T_WP + PCW NOR CS0 T WP + 1 + + + PCW_NOR_CS0_T_CEOE + PCW NOR CS0 T CEOE + 1 + + + PCW_NOR_CS0_T_WC + PCW NOR CS0 T WC + 11 + + + PCW_NOR_CS0_T_RC + PCW NOR CS0 T RC + 11 + + + PCW_NOR_CS0_WE_TIME + PCW NOR CS0 WE TIME + 0 + + + PCW_NOR_CS1_T_TR + PCW NOR CS1 T TR + 1 + + + PCW_NOR_CS1_T_PC + PCW NOR CS1 T PC + 1 + + + PCW_NOR_CS1_T_WP + PCW NOR CS1 T WP + 1 + + + PCW_NOR_CS1_T_CEOE + PCW NOR CS1 T CEOE + 1 + + + PCW_NOR_CS1_T_WC + PCW NOR CS1 T WC + 11 + + + PCW_NOR_CS1_T_RC + PCW NOR CS1 T RC + 11 + + + PCW_NOR_CS1_WE_TIME + PCW NOR CS1 WE TIME + 0 + + + PCW_NAND_CYCLES_T_RR + PCW NAND CYCLES T RR + 1 + + + PCW_NAND_CYCLES_T_AR + PCW NAND CYCLES T AR + 1 + + + PCW_NAND_CYCLES_T_CLR + PCW NAND CYCLES T CLR + 1 + + + PCW_NAND_CYCLES_T_WP + PCW NAND CYCLES T WP + 1 + + + PCW_NAND_CYCLES_T_REA + PCW NAND CYCLES T REA + 1 + + + PCW_NAND_CYCLES_T_WC + PCW NAND CYCLES T WC + 11 + + + PCW_NAND_CYCLES_T_RC + PCW NAND CYCLES T RC + 11 + + + PCW_SMC_CYCLE_T0 + PCW SMC CYCLE T0 + NA + + + PCW_SMC_CYCLE_T1 + PCW SMC CYCLE T1 + NA + + + PCW_SMC_CYCLE_T2 + PCW SMC CYCLE T2 + NA + + + PCW_SMC_CYCLE_T3 + PCW SMC CYCLE T3 + NA + + + PCW_SMC_CYCLE_T4 + PCW SMC CYCLE T4 + NA + + + PCW_SMC_CYCLE_T5 + PCW SMC CYCLE T5 + NA + + + PCW_SMC_CYCLE_T6 + PCW SMC CYCLE T6 + NA + + + PCW_PACKAGE_NAME + PCW PACKAGE NAME + clg225 + + + PCW_PLL_BYPASSMODE_ENABLE + PCW PLL BYPASSMODE ENABLE + 0 + + + Component_Name + design_1_processing_system7_0_0 + + + + + ZYNQ7 Processing System + + XPM_MEMORY + XPM_FIFO + + 6 + true + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2018.2 + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v new file mode 100644 index 0000000..5af2606 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v @@ -0,0 +1,5171 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Fri Aug 17 17:36:46 2018 +// Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +// Command : write_verilog -force -mode funcsim +// c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v +// Design : design_1_processing_system7_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg225-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *) +(* NotValidForBitStream *) +module design_1_processing_system7_0_0 + (GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_TX, + UART0_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + IRQ_F2P, + FCLK_CLK0, + FCLK_CLK1, + FCLK_RESET0_N, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB); + (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *) input [63:0]GPIO_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *) output [63:0]GPIO_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *) output [63:0]GPIO_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) input I2C0_SDA_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) output I2C0_SDA_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) output I2C0_SDA_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) input I2C0_SCL_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) output I2C0_SCL_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output I2C0_SCL_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CLK" *) output SDIO0_CLK; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CLK_FB" *) input SDIO0_CLK_FB; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_O" *) output SDIO0_CMD_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_I" *) input SDIO0_CMD_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_T" *) output SDIO0_CMD_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_I" *) input [3:0]SDIO0_DATA_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_O" *) output [3:0]SDIO0_DATA_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_T" *) output [3:0]SDIO0_DATA_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 LED" *) output SDIO0_LED; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CDN" *) input SDIO0_CDN; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) input SDIO0_WP; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 BUSPOW" *) output SDIO0_BUSPOW; + (* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 BUSVOLT" *) output [2:0]SDIO0_BUSVOLT; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_I" *) input SPI0_SCLK_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_O" *) output SPI0_SCLK_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_T" *) output SPI0_SCLK_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_I" *) input SPI0_MOSI_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_O" *) output SPI0_MOSI_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_T" *) output SPI0_MOSI_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_I" *) input SPI0_MISO_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_O" *) output SPI0_MISO_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_T" *) output SPI0_MISO_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_I" *) input SPI0_SS_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_O" *) output SPI0_SS_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS1_O" *) output SPI0_SS1_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS2_O" *) output SPI0_SS2_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_T" *) output SPI0_SS_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *) input SPI1_SCLK_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *) output SPI1_SCLK_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *) output SPI1_SCLK_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *) input SPI1_MOSI_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *) output SPI1_MOSI_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *) output SPI1_MOSI_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *) input SPI1_MISO_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *) output SPI1_MISO_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *) output SPI1_MISO_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *) input SPI1_SS_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *) output SPI1_SS_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *) output SPI1_SS1_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *) output SPI1_SS2_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *) output SPI1_SS_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 UART_0 TxD" *) output UART0_TX; + (* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 UART_0 RxD" *) input UART0_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) input M_AXI_GP0_ACLK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA; + (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) output FCLK_CLK0; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK1" *) output FCLK_CLK1; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [31:0]MIO; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [1:0]DDR_DM; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [15:0]DDR_DQ; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [1:0]DDR_DQS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [1:0]DDR_DQS; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB; + + wire [14:0]DDR_Addr; + wire [2:0]DDR_BankAddr; + wire DDR_CAS_n; + wire DDR_CKE; + wire DDR_CS_n; + wire DDR_Clk; + wire DDR_Clk_n; + wire [1:0]DDR_DM; + wire [15:0]DDR_DQ; + wire [1:0]DDR_DQS; + wire [1:0]DDR_DQS_n; + wire DDR_DRSTB; + wire DDR_ODT; + wire DDR_RAS_n; + wire DDR_VRN; + wire DDR_VRP; + wire DDR_WEB; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_RESET0_N; + wire [63:0]GPIO_I; + wire [63:0]GPIO_O; + wire [63:0]GPIO_T; + wire I2C0_SCL_I; + wire I2C0_SCL_O; + wire I2C0_SCL_T; + wire I2C0_SDA_I; + wire I2C0_SDA_O; + wire I2C0_SDA_T; + wire [0:0]IRQ_F2P; + wire [31:0]MIO; + wire M_AXI_GP0_ACLK; + wire [31:0]M_AXI_GP0_ARADDR; + wire [1:0]M_AXI_GP0_ARBURST; + wire [3:0]M_AXI_GP0_ARCACHE; + wire [11:0]M_AXI_GP0_ARID; + wire [3:0]M_AXI_GP0_ARLEN; + wire [1:0]M_AXI_GP0_ARLOCK; + wire [2:0]M_AXI_GP0_ARPROT; + wire [3:0]M_AXI_GP0_ARQOS; + wire M_AXI_GP0_ARREADY; + wire [2:0]M_AXI_GP0_ARSIZE; + wire M_AXI_GP0_ARVALID; + wire [31:0]M_AXI_GP0_AWADDR; + wire [1:0]M_AXI_GP0_AWBURST; + wire [3:0]M_AXI_GP0_AWCACHE; + wire [11:0]M_AXI_GP0_AWID; + wire [3:0]M_AXI_GP0_AWLEN; + wire [1:0]M_AXI_GP0_AWLOCK; + wire [2:0]M_AXI_GP0_AWPROT; + wire [3:0]M_AXI_GP0_AWQOS; + wire M_AXI_GP0_AWREADY; + wire [2:0]M_AXI_GP0_AWSIZE; + wire M_AXI_GP0_AWVALID; + wire [11:0]M_AXI_GP0_BID; + wire M_AXI_GP0_BREADY; + wire [1:0]M_AXI_GP0_BRESP; + wire M_AXI_GP0_BVALID; + wire [31:0]M_AXI_GP0_RDATA; + wire [11:0]M_AXI_GP0_RID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RREADY; + wire [1:0]M_AXI_GP0_RRESP; + wire M_AXI_GP0_RVALID; + wire [31:0]M_AXI_GP0_WDATA; + wire [11:0]M_AXI_GP0_WID; + wire M_AXI_GP0_WLAST; + wire M_AXI_GP0_WREADY; + wire [3:0]M_AXI_GP0_WSTRB; + wire M_AXI_GP0_WVALID; + wire PS_CLK; + wire PS_PORB; + wire PS_SRSTB; + wire SDIO0_BUSPOW; + wire [2:0]SDIO0_BUSVOLT; + wire SDIO0_CDN; + wire SDIO0_CLK; + wire SDIO0_CLK_FB; + wire SDIO0_CMD_I; + wire SDIO0_CMD_O; + wire SDIO0_CMD_T; + wire [3:0]SDIO0_DATA_I; + wire [3:0]SDIO0_DATA_O; + wire [3:0]SDIO0_DATA_T; + wire SDIO0_LED; + wire SDIO0_WP; + wire SPI0_MISO_I; + wire SPI0_MISO_O; + wire SPI0_MISO_T; + wire SPI0_MOSI_I; + wire SPI0_MOSI_O; + wire SPI0_MOSI_T; + wire SPI0_SCLK_I; + wire SPI0_SCLK_O; + wire SPI0_SCLK_T; + wire SPI0_SS1_O; + wire SPI0_SS2_O; + wire SPI0_SS_I; + wire SPI0_SS_O; + wire SPI0_SS_T; + wire SPI1_MISO_I; + wire SPI1_MISO_O; + wire SPI1_MISO_T; + wire SPI1_MOSI_I; + wire SPI1_MOSI_O; + wire SPI1_MOSI_T; + wire SPI1_SCLK_I; + wire SPI1_SCLK_O; + wire SPI1_SCLK_T; + wire SPI1_SS1_O; + wire SPI1_SS2_O; + wire SPI1_SS_I; + wire SPI1_SS_O; + wire SPI1_SS_T; + wire TTC0_WAVE0_OUT; + wire TTC0_WAVE1_OUT; + wire TTC0_WAVE2_OUT; + wire TTC1_WAVE0_OUT; + wire TTC1_WAVE1_OUT; + wire TTC1_WAVE2_OUT; + wire UART0_RX; + wire UART0_TX; + wire [1:0]USB0_PORT_INDCTL; + wire USB0_VBUS_PWRFAULT; + wire USB0_VBUS_PWRSELECT; + wire NLW_inst_CAN0_PHY_TX_UNCONNECTED; + wire NLW_inst_CAN1_PHY_TX_UNCONNECTED; + wire NLW_inst_DMA0_DAVALID_UNCONNECTED; + wire NLW_inst_DMA0_DRREADY_UNCONNECTED; + wire NLW_inst_DMA0_RSTN_UNCONNECTED; + wire NLW_inst_DMA1_DAVALID_UNCONNECTED; + wire NLW_inst_DMA1_DRREADY_UNCONNECTED; + wire NLW_inst_DMA1_RSTN_UNCONNECTED; + wire NLW_inst_DMA2_DAVALID_UNCONNECTED; + wire NLW_inst_DMA2_DRREADY_UNCONNECTED; + wire NLW_inst_DMA2_RSTN_UNCONNECTED; + wire NLW_inst_DMA3_DAVALID_UNCONNECTED; + wire NLW_inst_DMA3_DRREADY_UNCONNECTED; + wire NLW_inst_DMA3_RSTN_UNCONNECTED; + wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED; + wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_O_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_T_UNCONNECTED; + wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED; + wire NLW_inst_ENET0_SOF_RX_UNCONNECTED; + wire NLW_inst_ENET0_SOF_TX_UNCONNECTED; + wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED; + wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_O_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_T_UNCONNECTED; + wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED; + wire NLW_inst_ENET1_SOF_RX_UNCONNECTED; + wire NLW_inst_ENET1_SOF_TX_UNCONNECTED; + wire NLW_inst_EVENT_EVENTO_UNCONNECTED; + wire NLW_inst_FCLK_CLK2_UNCONNECTED; + wire NLW_inst_FCLK_CLK3_UNCONNECTED; + wire NLW_inst_FCLK_RESET1_N_UNCONNECTED; + wire NLW_inst_FCLK_RESET2_N_UNCONNECTED; + wire NLW_inst_FCLK_RESET3_N_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED; + wire NLW_inst_I2C1_SCL_O_UNCONNECTED; + wire NLW_inst_I2C1_SCL_T_UNCONNECTED; + wire NLW_inst_I2C1_SDA_O_UNCONNECTED; + wire NLW_inst_I2C1_SDA_T_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED; + wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED; + wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED; + wire NLW_inst_PJTAG_TDO_UNCONNECTED; + wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED; + wire NLW_inst_SDIO1_CLK_UNCONNECTED; + wire NLW_inst_SDIO1_CMD_O_UNCONNECTED; + wire NLW_inst_SDIO1_CMD_T_UNCONNECTED; + wire NLW_inst_SDIO1_LED_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED; + wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED; + wire NLW_inst_TRACE_CTL_UNCONNECTED; + wire NLW_inst_UART0_DTRN_UNCONNECTED; + wire NLW_inst_UART0_RTSN_UNCONNECTED; + wire NLW_inst_UART1_DTRN_UNCONNECTED; + wire NLW_inst_UART1_RTSN_UNCONNECTED; + wire NLW_inst_UART1_TX_UNCONNECTED; + wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED; + wire NLW_inst_WDT_RST_OUT_UNCONNECTED; + wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED; + wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED; + wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED; + wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED; + wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED; + wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED; + wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED; + wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED; + wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED; + wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED; + wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED; + wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED; + wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED; + + (* C_DM_WIDTH = "2" *) + (* C_DQS_WIDTH = "2" *) + (* C_DQ_WIDTH = "16" *) + (* C_EMIO_GPIO_WIDTH = "64" *) + (* C_EN_EMIO_ENET0 = "0" *) + (* C_EN_EMIO_ENET1 = "0" *) + (* C_EN_EMIO_PJTAG = "0" *) + (* C_EN_EMIO_TRACE = "0" *) + (* C_FCLK_CLK0_BUF = "TRUE" *) + (* C_FCLK_CLK1_BUF = "TRUE" *) + (* C_FCLK_CLK2_BUF = "FALSE" *) + (* C_FCLK_CLK3_BUF = "FALSE" *) + (* C_GP0_EN_MODIFIABLE_TXN = "1" *) + (* C_GP1_EN_MODIFIABLE_TXN = "1" *) + (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) + (* C_INCLUDE_TRACE_BUFFER = "0" *) + (* C_IRQ_F2P_MODE = "DIRECT" *) + (* C_MIO_PRIMITIVE = "32" *) + (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) + (* C_M_AXI_GP0_ID_WIDTH = "12" *) + (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) + (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) + (* C_M_AXI_GP1_ID_WIDTH = "12" *) + (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) + (* C_NUM_F2P_INTR_INPUTS = "1" *) + (* C_PACKAGE_NAME = "clg225" *) + (* C_PS7_SI_REV = "PRODUCTION" *) + (* C_S_AXI_ACP_ARUSER_VAL = "31" *) + (* C_S_AXI_ACP_AWUSER_VAL = "31" *) + (* C_S_AXI_ACP_ID_WIDTH = "3" *) + (* C_S_AXI_GP0_ID_WIDTH = "6" *) + (* C_S_AXI_GP1_ID_WIDTH = "6" *) + (* C_S_AXI_HP0_DATA_WIDTH = "64" *) + (* C_S_AXI_HP0_ID_WIDTH = "6" *) + (* C_S_AXI_HP1_DATA_WIDTH = "64" *) + (* C_S_AXI_HP1_ID_WIDTH = "6" *) + (* C_S_AXI_HP2_DATA_WIDTH = "64" *) + (* C_S_AXI_HP2_ID_WIDTH = "6" *) + (* C_S_AXI_HP3_DATA_WIDTH = "64" *) + (* C_S_AXI_HP3_ID_WIDTH = "6" *) + (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) + (* C_TRACE_BUFFER_FIFO_SIZE = "128" *) + (* C_TRACE_INTERNAL_WIDTH = "2" *) + (* C_TRACE_PIPELINE_WIDTH = "8" *) + (* C_USE_AXI_NONSECURE = "0" *) + (* C_USE_DEFAULT_ACP_USER_VAL = "0" *) + (* C_USE_M_AXI_GP0 = "1" *) + (* C_USE_M_AXI_GP1 = "0" *) + (* C_USE_S_AXI_ACP = "0" *) + (* C_USE_S_AXI_GP0 = "0" *) + (* C_USE_S_AXI_GP1 = "0" *) + (* C_USE_S_AXI_HP0 = "0" *) + (* C_USE_S_AXI_HP1 = "0" *) + (* C_USE_S_AXI_HP2 = "0" *) + (* C_USE_S_AXI_HP3 = "0" *) + (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) + (* POWER = "/>" *) + (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) + design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst + (.CAN0_PHY_RX(1'b0), + .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED), + .CAN1_PHY_RX(1'b0), + .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED), + .Core0_nFIQ(1'b0), + .Core0_nIRQ(1'b0), + .Core1_nFIQ(1'b0), + .Core1_nIRQ(1'b0), + .DDR_ARB({1'b0,1'b0,1'b0,1'b0}), + .DDR_Addr(DDR_Addr), + .DDR_BankAddr(DDR_BankAddr), + .DDR_CAS_n(DDR_CAS_n), + .DDR_CKE(DDR_CKE), + .DDR_CS_n(DDR_CS_n), + .DDR_Clk(DDR_Clk), + .DDR_Clk_n(DDR_Clk_n), + .DDR_DM(DDR_DM), + .DDR_DQ(DDR_DQ), + .DDR_DQS(DDR_DQS), + .DDR_DQS_n(DDR_DQS_n), + .DDR_DRSTB(DDR_DRSTB), + .DDR_ODT(DDR_ODT), + .DDR_RAS_n(DDR_RAS_n), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_WEB(DDR_WEB), + .DMA0_ACLK(1'b0), + .DMA0_DAREADY(1'b0), + .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]), + .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED), + .DMA0_DRLAST(1'b0), + .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED), + .DMA0_DRTYPE({1'b0,1'b0}), + .DMA0_DRVALID(1'b0), + .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED), + .DMA1_ACLK(1'b0), + .DMA1_DAREADY(1'b0), + .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]), + .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED), + .DMA1_DRLAST(1'b0), + .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED), + .DMA1_DRTYPE({1'b0,1'b0}), + .DMA1_DRVALID(1'b0), + .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED), + .DMA2_ACLK(1'b0), + .DMA2_DAREADY(1'b0), + .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]), + .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED), + .DMA2_DRLAST(1'b0), + .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED), + .DMA2_DRTYPE({1'b0,1'b0}), + .DMA2_DRVALID(1'b0), + .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED), + .DMA3_ACLK(1'b0), + .DMA3_DAREADY(1'b0), + .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]), + .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED), + .DMA3_DRLAST(1'b0), + .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED), + .DMA3_DRTYPE({1'b0,1'b0}), + .DMA3_DRVALID(1'b0), + .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED), + .ENET0_EXT_INTIN(1'b0), + .ENET0_GMII_COL(1'b0), + .ENET0_GMII_CRS(1'b0), + .ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ENET0_GMII_RX_CLK(1'b0), + .ENET0_GMII_RX_DV(1'b0), + .ENET0_GMII_RX_ER(1'b0), + .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]), + .ENET0_GMII_TX_CLK(1'b0), + .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED), + .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED), + .ENET0_MDIO_I(1'b0), + .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED), + .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED), + .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED), + .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED), + .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED), + .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED), + .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED), + .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED), + .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED), + .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED), + .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED), + .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED), + .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED), + .ENET1_EXT_INTIN(1'b0), + .ENET1_GMII_COL(1'b0), + .ENET1_GMII_CRS(1'b0), + .ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ENET1_GMII_RX_CLK(1'b0), + .ENET1_GMII_RX_DV(1'b0), + .ENET1_GMII_RX_ER(1'b0), + .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]), + .ENET1_GMII_TX_CLK(1'b0), + .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED), + .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED), + .ENET1_MDIO_I(1'b0), + .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED), + .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED), + .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED), + .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED), + .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED), + .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED), + .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED), + .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED), + .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED), + .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED), + .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED), + .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED), + .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED), + .EVENT_EVENTI(1'b0), + .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED), + .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]), + .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]), + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED), + .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED), + .FCLK_CLKTRIG0_N(1'b0), + .FCLK_CLKTRIG1_N(1'b0), + .FCLK_CLKTRIG2_N(1'b0), + .FCLK_CLKTRIG3_N(1'b0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED), + .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED), + .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED), + .FPGA_IDLE_N(1'b0), + .FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}), + .FTMD_TRACEIN_CLK(1'b0), + .FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMD_TRACEIN_VALID(1'b0), + .FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED), + .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED), + .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED), + .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED), + .FTMT_F2P_TRIG_0(1'b0), + .FTMT_F2P_TRIG_1(1'b0), + .FTMT_F2P_TRIG_2(1'b0), + .FTMT_F2P_TRIG_3(1'b0), + .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]), + .FTMT_P2F_TRIGACK_0(1'b0), + .FTMT_P2F_TRIGACK_1(1'b0), + .FTMT_P2F_TRIGACK_2(1'b0), + .FTMT_P2F_TRIGACK_3(1'b0), + .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED), + .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED), + .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED), + .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED), + .GPIO_I(GPIO_I), + .GPIO_O(GPIO_O), + .GPIO_T(GPIO_T), + .I2C0_SCL_I(I2C0_SCL_I), + .I2C0_SCL_O(I2C0_SCL_O), + .I2C0_SCL_T(I2C0_SCL_T), + .I2C0_SDA_I(I2C0_SDA_I), + .I2C0_SDA_O(I2C0_SDA_O), + .I2C0_SDA_T(I2C0_SDA_T), + .I2C1_SCL_I(1'b0), + .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED), + .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED), + .I2C1_SDA_I(1'b0), + .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED), + .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED), + .IRQ_F2P(IRQ_F2P), + .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED), + .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED), + .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED), + .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED), + .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED), + .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED), + .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED), + .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED), + .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED), + .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED), + .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED), + .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED), + .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED), + .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED), + .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED), + .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED), + .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED), + .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED), + .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED), + .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED), + .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED), + .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED), + .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED), + .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED), + .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED), + .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED), + .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED), + .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED), + .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED), + .MIO(MIO), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP1_ACLK(1'b0), + .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]), + .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]), + .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]), + .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED), + .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]), + .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]), + .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]), + .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]), + .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]), + .M_AXI_GP1_ARREADY(1'b0), + .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]), + .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED), + .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]), + .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]), + .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]), + .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]), + .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]), + .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]), + .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]), + .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]), + .M_AXI_GP1_AWREADY(1'b0), + .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]), + .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED), + .M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED), + .M_AXI_GP1_BRESP({1'b0,1'b0}), + .M_AXI_GP1_BVALID(1'b0), + .M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_RLAST(1'b0), + .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED), + .M_AXI_GP1_RRESP({1'b0,1'b0}), + .M_AXI_GP1_RVALID(1'b0), + .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]), + .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]), + .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED), + .M_AXI_GP1_WREADY(1'b0), + .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]), + .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED), + .PJTAG_TCK(1'b0), + .PJTAG_TDI(1'b0), + .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED), + .PJTAG_TMS(1'b0), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB), + .PS_SRSTB(PS_SRSTB), + .SDIO0_BUSPOW(SDIO0_BUSPOW), + .SDIO0_BUSVOLT(SDIO0_BUSVOLT), + .SDIO0_CDN(SDIO0_CDN), + .SDIO0_CLK(SDIO0_CLK), + .SDIO0_CLK_FB(SDIO0_CLK_FB), + .SDIO0_CMD_I(SDIO0_CMD_I), + .SDIO0_CMD_O(SDIO0_CMD_O), + .SDIO0_CMD_T(SDIO0_CMD_T), + .SDIO0_DATA_I(SDIO0_DATA_I), + .SDIO0_DATA_O(SDIO0_DATA_O), + .SDIO0_DATA_T(SDIO0_DATA_T), + .SDIO0_LED(SDIO0_LED), + .SDIO0_WP(SDIO0_WP), + .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED), + .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]), + .SDIO1_CDN(1'b0), + .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED), + .SDIO1_CLK_FB(1'b0), + .SDIO1_CMD_I(1'b0), + .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED), + .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED), + .SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}), + .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]), + .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]), + .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED), + .SDIO1_WP(1'b0), + .SPI0_MISO_I(SPI0_MISO_I), + .SPI0_MISO_O(SPI0_MISO_O), + .SPI0_MISO_T(SPI0_MISO_T), + .SPI0_MOSI_I(SPI0_MOSI_I), + .SPI0_MOSI_O(SPI0_MOSI_O), + .SPI0_MOSI_T(SPI0_MOSI_T), + .SPI0_SCLK_I(SPI0_SCLK_I), + .SPI0_SCLK_O(SPI0_SCLK_O), + .SPI0_SCLK_T(SPI0_SCLK_T), + .SPI0_SS1_O(SPI0_SS1_O), + .SPI0_SS2_O(SPI0_SS2_O), + .SPI0_SS_I(SPI0_SS_I), + .SPI0_SS_O(SPI0_SS_O), + .SPI0_SS_T(SPI0_SS_T), + .SPI1_MISO_I(SPI1_MISO_I), + .SPI1_MISO_O(SPI1_MISO_O), + .SPI1_MISO_T(SPI1_MISO_T), + .SPI1_MOSI_I(SPI1_MOSI_I), + .SPI1_MOSI_O(SPI1_MOSI_O), + .SPI1_MOSI_T(SPI1_MOSI_T), + .SPI1_SCLK_I(SPI1_SCLK_I), + .SPI1_SCLK_O(SPI1_SCLK_O), + .SPI1_SCLK_T(SPI1_SCLK_T), + .SPI1_SS1_O(SPI1_SS1_O), + .SPI1_SS2_O(SPI1_SS2_O), + .SPI1_SS_I(SPI1_SS_I), + .SPI1_SS_O(SPI1_SS_O), + .SPI1_SS_T(SPI1_SS_T), + .SRAM_INTIN(1'b0), + .S_AXI_ACP_ACLK(1'b0), + .S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARBURST({1'b0,1'b0}), + .S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED), + .S_AXI_ACP_ARID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARLOCK({1'b0,1'b0}), + .S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED), + .S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARVALID(1'b0), + .S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWBURST({1'b0,1'b0}), + .S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWLOCK({1'b0,1'b0}), + .S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED), + .S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWVALID(1'b0), + .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]), + .S_AXI_ACP_BREADY(1'b0), + .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]), + .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED), + .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]), + .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]), + .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED), + .S_AXI_ACP_RREADY(1'b0), + .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]), + .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED), + .S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_WID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_WLAST(1'b0), + .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED), + .S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_WVALID(1'b0), + .S_AXI_GP0_ACLK(1'b0), + .S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARBURST({1'b0,1'b0}), + .S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED), + .S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARLOCK({1'b0,1'b0}), + .S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED), + .S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARVALID(1'b0), + .S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWBURST({1'b0,1'b0}), + .S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWLOCK({1'b0,1'b0}), + .S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED), + .S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWVALID(1'b0), + .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]), + .S_AXI_GP0_BREADY(1'b0), + .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]), + .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED), + .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]), + .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]), + .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED), + .S_AXI_GP0_RREADY(1'b0), + .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]), + .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED), + .S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WLAST(1'b0), + .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED), + .S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WVALID(1'b0), + .S_AXI_GP1_ACLK(1'b0), + .S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARBURST({1'b0,1'b0}), + .S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED), + .S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARLOCK({1'b0,1'b0}), + .S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED), + .S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARVALID(1'b0), + .S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWBURST({1'b0,1'b0}), + .S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWLOCK({1'b0,1'b0}), + .S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED), + .S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWVALID(1'b0), + .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]), + .S_AXI_GP1_BREADY(1'b0), + .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]), + .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED), + .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]), + .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]), + .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED), + .S_AXI_GP1_RREADY(1'b0), + .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]), + .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED), + .S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WLAST(1'b0), + .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED), + .S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WVALID(1'b0), + .S_AXI_HP0_ACLK(1'b0), + .S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARBURST({1'b0,1'b0}), + .S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED), + .S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARLOCK({1'b0,1'b0}), + .S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED), + .S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP0_ARVALID(1'b0), + .S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWBURST({1'b0,1'b0}), + .S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWLOCK({1'b0,1'b0}), + .S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED), + .S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP0_AWVALID(1'b0), + .S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]), + .S_AXI_HP0_BREADY(1'b0), + .S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED), + .S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP0_RDISSUECAP1_EN(1'b0), + .S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]), + .S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED), + .S_AXI_HP0_RREADY(1'b0), + .S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED), + .S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WLAST(1'b0), + .S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED), + .S_AXI_HP0_WRISSUECAP1_EN(1'b0), + .S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP0_WVALID(1'b0), + .S_AXI_HP1_ACLK(1'b0), + .S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARBURST({1'b0,1'b0}), + .S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED), + .S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARLOCK({1'b0,1'b0}), + .S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED), + .S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARVALID(1'b0), + .S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWBURST({1'b0,1'b0}), + .S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWLOCK({1'b0,1'b0}), + .S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED), + .S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWVALID(1'b0), + .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]), + .S_AXI_HP1_BREADY(1'b0), + .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED), + .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP1_RDISSUECAP1_EN(1'b0), + .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]), + .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED), + .S_AXI_HP1_RREADY(1'b0), + .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED), + .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WLAST(1'b0), + .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED), + .S_AXI_HP1_WRISSUECAP1_EN(1'b0), + .S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WVALID(1'b0), + .S_AXI_HP2_ACLK(1'b0), + .S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARBURST({1'b0,1'b0}), + .S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED), + .S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARLOCK({1'b0,1'b0}), + .S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED), + .S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARVALID(1'b0), + .S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWBURST({1'b0,1'b0}), + .S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWLOCK({1'b0,1'b0}), + .S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED), + .S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWVALID(1'b0), + .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]), + .S_AXI_HP2_BREADY(1'b0), + .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED), + .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP2_RDISSUECAP1_EN(1'b0), + .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]), + .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED), + .S_AXI_HP2_RREADY(1'b0), + .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED), + .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WLAST(1'b0), + .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED), + .S_AXI_HP2_WRISSUECAP1_EN(1'b0), + .S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WVALID(1'b0), + .S_AXI_HP3_ACLK(1'b0), + .S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARBURST({1'b0,1'b0}), + .S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED), + .S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARLOCK({1'b0,1'b0}), + .S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED), + .S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARVALID(1'b0), + .S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWBURST({1'b0,1'b0}), + .S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWLOCK({1'b0,1'b0}), + .S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED), + .S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWVALID(1'b0), + .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]), + .S_AXI_HP3_BREADY(1'b0), + .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED), + .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP3_RDISSUECAP1_EN(1'b0), + .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]), + .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED), + .S_AXI_HP3_RREADY(1'b0), + .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED), + .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WLAST(1'b0), + .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED), + .S_AXI_HP3_WRISSUECAP1_EN(1'b0), + .S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WVALID(1'b0), + .TRACE_CLK(1'b0), + .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED), + .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED), + .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]), + .TTC0_CLK0_IN(1'b0), + .TTC0_CLK1_IN(1'b0), + .TTC0_CLK2_IN(1'b0), + .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT), + .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT), + .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT), + .TTC1_CLK0_IN(1'b0), + .TTC1_CLK1_IN(1'b0), + .TTC1_CLK2_IN(1'b0), + .TTC1_WAVE0_OUT(TTC1_WAVE0_OUT), + .TTC1_WAVE1_OUT(TTC1_WAVE1_OUT), + .TTC1_WAVE2_OUT(TTC1_WAVE2_OUT), + .UART0_CTSN(1'b0), + .UART0_DCDN(1'b0), + .UART0_DSRN(1'b0), + .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED), + .UART0_RIN(1'b0), + .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED), + .UART0_RX(UART0_RX), + .UART0_TX(UART0_TX), + .UART1_CTSN(1'b0), + .UART1_DCDN(1'b0), + .UART1_DSRN(1'b0), + .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED), + .UART1_RIN(1'b0), + .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED), + .UART1_RX(1'b1), + .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED), + .USB0_PORT_INDCTL(USB0_PORT_INDCTL), + .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), + .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), + .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]), + .USB1_VBUS_PWRFAULT(1'b0), + .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED), + .WDT_CLK_IN(1'b0), + .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED)); +endmodule + +(* C_DM_WIDTH = "2" *) (* C_DQS_WIDTH = "2" *) (* C_DQ_WIDTH = "16" *) +(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *) +(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *) +(* C_FCLK_CLK1_BUF = "TRUE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *) +(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) +(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "32" *) +(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) +(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) +(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg225" *) (* C_PS7_SI_REV = "PRODUCTION" *) +(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *) +(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *) +(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *) +(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *) +(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *) +(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *) +(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *) +(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *) +(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *) +(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *) +(* POWER = "/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) +module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 + (CAN0_PHY_TX, + CAN0_PHY_RX, + CAN1_PHY_TX, + CAN1_PHY_RX, + ENET0_GMII_TX_EN, + ENET0_GMII_TX_ER, + ENET0_MDIO_MDC, + ENET0_MDIO_O, + ENET0_MDIO_T, + ENET0_PTP_DELAY_REQ_RX, + ENET0_PTP_DELAY_REQ_TX, + ENET0_PTP_PDELAY_REQ_RX, + ENET0_PTP_PDELAY_REQ_TX, + ENET0_PTP_PDELAY_RESP_RX, + ENET0_PTP_PDELAY_RESP_TX, + ENET0_PTP_SYNC_FRAME_RX, + ENET0_PTP_SYNC_FRAME_TX, + ENET0_SOF_RX, + ENET0_SOF_TX, + ENET0_GMII_TXD, + ENET0_GMII_COL, + ENET0_GMII_CRS, + ENET0_GMII_RX_CLK, + ENET0_GMII_RX_DV, + ENET0_GMII_RX_ER, + ENET0_GMII_TX_CLK, + ENET0_MDIO_I, + ENET0_EXT_INTIN, + ENET0_GMII_RXD, + ENET1_GMII_TX_EN, + ENET1_GMII_TX_ER, + ENET1_MDIO_MDC, + ENET1_MDIO_O, + ENET1_MDIO_T, + ENET1_PTP_DELAY_REQ_RX, + ENET1_PTP_DELAY_REQ_TX, + ENET1_PTP_PDELAY_REQ_RX, + ENET1_PTP_PDELAY_REQ_TX, + ENET1_PTP_PDELAY_RESP_RX, + ENET1_PTP_PDELAY_RESP_TX, + ENET1_PTP_SYNC_FRAME_RX, + ENET1_PTP_SYNC_FRAME_TX, + ENET1_SOF_RX, + ENET1_SOF_TX, + ENET1_GMII_TXD, + ENET1_GMII_COL, + ENET1_GMII_CRS, + ENET1_GMII_RX_CLK, + ENET1_GMII_RX_DV, + ENET1_GMII_RX_ER, + ENET1_GMII_TX_CLK, + ENET1_MDIO_I, + ENET1_EXT_INTIN, + ENET1_GMII_RXD, + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + I2C1_SDA_I, + I2C1_SDA_O, + I2C1_SDA_T, + I2C1_SCL_I, + I2C1_SCL_O, + I2C1_SCL_T, + PJTAG_TCK, + PJTAG_TMS, + PJTAG_TDI, + PJTAG_TDO, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SDIO1_CLK, + SDIO1_CLK_FB, + SDIO1_CMD_O, + SDIO1_CMD_I, + SDIO1_CMD_T, + SDIO1_DATA_I, + SDIO1_DATA_O, + SDIO1_DATA_T, + SDIO1_LED, + SDIO1_CDN, + SDIO1_WP, + SDIO1_BUSPOW, + SDIO1_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_DTRN, + UART0_RTSN, + UART0_TX, + UART0_CTSN, + UART0_DCDN, + UART0_DSRN, + UART0_RIN, + UART0_RX, + UART1_DTRN, + UART1_RTSN, + UART1_TX, + UART1_CTSN, + UART1_DCDN, + UART1_DSRN, + UART1_RIN, + UART1_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC0_CLK0_IN, + TTC0_CLK1_IN, + TTC0_CLK2_IN, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + TTC1_CLK0_IN, + TTC1_CLK1_IN, + TTC1_CLK2_IN, + WDT_CLK_IN, + WDT_RST_OUT, + TRACE_CLK, + TRACE_CTL, + TRACE_DATA, + TRACE_CLK_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + USB1_PORT_INDCTL, + USB1_VBUS_PWRSELECT, + USB1_VBUS_PWRFAULT, + SRAM_INTIN, + M_AXI_GP0_ARESETN, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + M_AXI_GP1_ARESETN, + M_AXI_GP1_ARVALID, + M_AXI_GP1_AWVALID, + M_AXI_GP1_BREADY, + M_AXI_GP1_RREADY, + M_AXI_GP1_WLAST, + M_AXI_GP1_WVALID, + M_AXI_GP1_ARID, + M_AXI_GP1_AWID, + M_AXI_GP1_WID, + M_AXI_GP1_ARBURST, + M_AXI_GP1_ARLOCK, + M_AXI_GP1_ARSIZE, + M_AXI_GP1_AWBURST, + M_AXI_GP1_AWLOCK, + M_AXI_GP1_AWSIZE, + M_AXI_GP1_ARPROT, + M_AXI_GP1_AWPROT, + M_AXI_GP1_ARADDR, + M_AXI_GP1_AWADDR, + M_AXI_GP1_WDATA, + M_AXI_GP1_ARCACHE, + M_AXI_GP1_ARLEN, + M_AXI_GP1_ARQOS, + M_AXI_GP1_AWCACHE, + M_AXI_GP1_AWLEN, + M_AXI_GP1_AWQOS, + M_AXI_GP1_WSTRB, + M_AXI_GP1_ACLK, + M_AXI_GP1_ARREADY, + M_AXI_GP1_AWREADY, + M_AXI_GP1_BVALID, + M_AXI_GP1_RLAST, + M_AXI_GP1_RVALID, + M_AXI_GP1_WREADY, + M_AXI_GP1_BID, + M_AXI_GP1_RID, + M_AXI_GP1_BRESP, + M_AXI_GP1_RRESP, + M_AXI_GP1_RDATA, + S_AXI_GP0_ARESETN, + S_AXI_GP0_ARREADY, + S_AXI_GP0_AWREADY, + S_AXI_GP0_BVALID, + S_AXI_GP0_RLAST, + S_AXI_GP0_RVALID, + S_AXI_GP0_WREADY, + S_AXI_GP0_BRESP, + S_AXI_GP0_RRESP, + S_AXI_GP0_RDATA, + S_AXI_GP0_BID, + S_AXI_GP0_RID, + S_AXI_GP0_ACLK, + S_AXI_GP0_ARVALID, + S_AXI_GP0_AWVALID, + S_AXI_GP0_BREADY, + S_AXI_GP0_RREADY, + S_AXI_GP0_WLAST, + S_AXI_GP0_WVALID, + S_AXI_GP0_ARBURST, + S_AXI_GP0_ARLOCK, + S_AXI_GP0_ARSIZE, + S_AXI_GP0_AWBURST, + S_AXI_GP0_AWLOCK, + S_AXI_GP0_AWSIZE, + S_AXI_GP0_ARPROT, + S_AXI_GP0_AWPROT, + S_AXI_GP0_ARADDR, + S_AXI_GP0_AWADDR, + S_AXI_GP0_WDATA, + S_AXI_GP0_ARCACHE, + S_AXI_GP0_ARLEN, + S_AXI_GP0_ARQOS, + S_AXI_GP0_AWCACHE, + S_AXI_GP0_AWLEN, + S_AXI_GP0_AWQOS, + S_AXI_GP0_WSTRB, + S_AXI_GP0_ARID, + S_AXI_GP0_AWID, + S_AXI_GP0_WID, + S_AXI_GP1_ARESETN, + S_AXI_GP1_ARREADY, + S_AXI_GP1_AWREADY, + S_AXI_GP1_BVALID, + S_AXI_GP1_RLAST, + S_AXI_GP1_RVALID, + S_AXI_GP1_WREADY, + S_AXI_GP1_BRESP, + S_AXI_GP1_RRESP, + S_AXI_GP1_RDATA, + S_AXI_GP1_BID, + S_AXI_GP1_RID, + S_AXI_GP1_ACLK, + S_AXI_GP1_ARVALID, + S_AXI_GP1_AWVALID, + S_AXI_GP1_BREADY, + S_AXI_GP1_RREADY, + S_AXI_GP1_WLAST, + S_AXI_GP1_WVALID, + S_AXI_GP1_ARBURST, + S_AXI_GP1_ARLOCK, + S_AXI_GP1_ARSIZE, + S_AXI_GP1_AWBURST, + S_AXI_GP1_AWLOCK, + S_AXI_GP1_AWSIZE, + S_AXI_GP1_ARPROT, + S_AXI_GP1_AWPROT, + S_AXI_GP1_ARADDR, + S_AXI_GP1_AWADDR, + S_AXI_GP1_WDATA, + S_AXI_GP1_ARCACHE, + S_AXI_GP1_ARLEN, + S_AXI_GP1_ARQOS, + S_AXI_GP1_AWCACHE, + S_AXI_GP1_AWLEN, + S_AXI_GP1_AWQOS, + S_AXI_GP1_WSTRB, + S_AXI_GP1_ARID, + S_AXI_GP1_AWID, + S_AXI_GP1_WID, + S_AXI_ACP_ARESETN, + S_AXI_ACP_ARREADY, + S_AXI_ACP_AWREADY, + S_AXI_ACP_BVALID, + S_AXI_ACP_RLAST, + S_AXI_ACP_RVALID, + S_AXI_ACP_WREADY, + S_AXI_ACP_BRESP, + S_AXI_ACP_RRESP, + S_AXI_ACP_BID, + S_AXI_ACP_RID, + S_AXI_ACP_RDATA, + S_AXI_ACP_ACLK, + S_AXI_ACP_ARVALID, + S_AXI_ACP_AWVALID, + S_AXI_ACP_BREADY, + S_AXI_ACP_RREADY, + S_AXI_ACP_WLAST, + S_AXI_ACP_WVALID, + S_AXI_ACP_ARID, + S_AXI_ACP_ARPROT, + S_AXI_ACP_AWID, + S_AXI_ACP_AWPROT, + S_AXI_ACP_WID, + S_AXI_ACP_ARADDR, + S_AXI_ACP_AWADDR, + S_AXI_ACP_ARCACHE, + S_AXI_ACP_ARLEN, + S_AXI_ACP_ARQOS, + S_AXI_ACP_AWCACHE, + S_AXI_ACP_AWLEN, + S_AXI_ACP_AWQOS, + S_AXI_ACP_ARBURST, + S_AXI_ACP_ARLOCK, + S_AXI_ACP_ARSIZE, + S_AXI_ACP_AWBURST, + S_AXI_ACP_AWLOCK, + S_AXI_ACP_AWSIZE, + S_AXI_ACP_ARUSER, + S_AXI_ACP_AWUSER, + S_AXI_ACP_WDATA, + S_AXI_ACP_WSTRB, + S_AXI_HP0_ARESETN, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + S_AXI_HP1_ARESETN, + S_AXI_HP1_ARREADY, + S_AXI_HP1_AWREADY, + S_AXI_HP1_BVALID, + S_AXI_HP1_RLAST, + S_AXI_HP1_RVALID, + S_AXI_HP1_WREADY, + S_AXI_HP1_BRESP, + S_AXI_HP1_RRESP, + S_AXI_HP1_BID, + S_AXI_HP1_RID, + S_AXI_HP1_RDATA, + S_AXI_HP1_RCOUNT, + S_AXI_HP1_WCOUNT, + S_AXI_HP1_RACOUNT, + S_AXI_HP1_WACOUNT, + S_AXI_HP1_ACLK, + S_AXI_HP1_ARVALID, + S_AXI_HP1_AWVALID, + S_AXI_HP1_BREADY, + S_AXI_HP1_RDISSUECAP1_EN, + S_AXI_HP1_RREADY, + S_AXI_HP1_WLAST, + S_AXI_HP1_WRISSUECAP1_EN, + S_AXI_HP1_WVALID, + S_AXI_HP1_ARBURST, + S_AXI_HP1_ARLOCK, + S_AXI_HP1_ARSIZE, + S_AXI_HP1_AWBURST, + S_AXI_HP1_AWLOCK, + S_AXI_HP1_AWSIZE, + S_AXI_HP1_ARPROT, + S_AXI_HP1_AWPROT, + S_AXI_HP1_ARADDR, + S_AXI_HP1_AWADDR, + S_AXI_HP1_ARCACHE, + S_AXI_HP1_ARLEN, + S_AXI_HP1_ARQOS, + S_AXI_HP1_AWCACHE, + S_AXI_HP1_AWLEN, + S_AXI_HP1_AWQOS, + S_AXI_HP1_ARID, + S_AXI_HP1_AWID, + S_AXI_HP1_WID, + S_AXI_HP1_WDATA, + S_AXI_HP1_WSTRB, + S_AXI_HP2_ARESETN, + S_AXI_HP2_ARREADY, + S_AXI_HP2_AWREADY, + S_AXI_HP2_BVALID, + S_AXI_HP2_RLAST, + S_AXI_HP2_RVALID, + S_AXI_HP2_WREADY, + S_AXI_HP2_BRESP, + S_AXI_HP2_RRESP, + S_AXI_HP2_BID, + S_AXI_HP2_RID, + S_AXI_HP2_RDATA, + S_AXI_HP2_RCOUNT, + S_AXI_HP2_WCOUNT, + S_AXI_HP2_RACOUNT, + S_AXI_HP2_WACOUNT, + S_AXI_HP2_ACLK, + S_AXI_HP2_ARVALID, + S_AXI_HP2_AWVALID, + S_AXI_HP2_BREADY, + S_AXI_HP2_RDISSUECAP1_EN, + S_AXI_HP2_RREADY, + S_AXI_HP2_WLAST, + S_AXI_HP2_WRISSUECAP1_EN, + S_AXI_HP2_WVALID, + S_AXI_HP2_ARBURST, + S_AXI_HP2_ARLOCK, + S_AXI_HP2_ARSIZE, + S_AXI_HP2_AWBURST, + S_AXI_HP2_AWLOCK, + S_AXI_HP2_AWSIZE, + S_AXI_HP2_ARPROT, + S_AXI_HP2_AWPROT, + S_AXI_HP2_ARADDR, + S_AXI_HP2_AWADDR, + S_AXI_HP2_ARCACHE, + S_AXI_HP2_ARLEN, + S_AXI_HP2_ARQOS, + S_AXI_HP2_AWCACHE, + S_AXI_HP2_AWLEN, + S_AXI_HP2_AWQOS, + S_AXI_HP2_ARID, + S_AXI_HP2_AWID, + S_AXI_HP2_WID, + S_AXI_HP2_WDATA, + S_AXI_HP2_WSTRB, + S_AXI_HP3_ARESETN, + S_AXI_HP3_ARREADY, + S_AXI_HP3_AWREADY, + S_AXI_HP3_BVALID, + S_AXI_HP3_RLAST, + S_AXI_HP3_RVALID, + S_AXI_HP3_WREADY, + S_AXI_HP3_BRESP, + S_AXI_HP3_RRESP, + S_AXI_HP3_BID, + S_AXI_HP3_RID, + S_AXI_HP3_RDATA, + S_AXI_HP3_RCOUNT, + S_AXI_HP3_WCOUNT, + S_AXI_HP3_RACOUNT, + S_AXI_HP3_WACOUNT, + S_AXI_HP3_ACLK, + S_AXI_HP3_ARVALID, + S_AXI_HP3_AWVALID, + S_AXI_HP3_BREADY, + S_AXI_HP3_RDISSUECAP1_EN, + S_AXI_HP3_RREADY, + S_AXI_HP3_WLAST, + S_AXI_HP3_WRISSUECAP1_EN, + S_AXI_HP3_WVALID, + S_AXI_HP3_ARBURST, + S_AXI_HP3_ARLOCK, + S_AXI_HP3_ARSIZE, + S_AXI_HP3_AWBURST, + S_AXI_HP3_AWLOCK, + S_AXI_HP3_AWSIZE, + S_AXI_HP3_ARPROT, + S_AXI_HP3_AWPROT, + S_AXI_HP3_ARADDR, + S_AXI_HP3_AWADDR, + S_AXI_HP3_ARCACHE, + S_AXI_HP3_ARLEN, + S_AXI_HP3_ARQOS, + S_AXI_HP3_AWCACHE, + S_AXI_HP3_AWLEN, + S_AXI_HP3_AWQOS, + S_AXI_HP3_ARID, + S_AXI_HP3_AWID, + S_AXI_HP3_WID, + S_AXI_HP3_WDATA, + S_AXI_HP3_WSTRB, + IRQ_P2F_DMAC_ABORT, + IRQ_P2F_DMAC0, + IRQ_P2F_DMAC1, + IRQ_P2F_DMAC2, + IRQ_P2F_DMAC3, + IRQ_P2F_DMAC4, + IRQ_P2F_DMAC5, + IRQ_P2F_DMAC6, + IRQ_P2F_DMAC7, + IRQ_P2F_SMC, + IRQ_P2F_QSPI, + IRQ_P2F_CTI, + IRQ_P2F_GPIO, + IRQ_P2F_USB0, + IRQ_P2F_ENET0, + IRQ_P2F_ENET_WAKE0, + IRQ_P2F_SDIO0, + IRQ_P2F_I2C0, + IRQ_P2F_SPI0, + IRQ_P2F_UART0, + IRQ_P2F_CAN0, + IRQ_P2F_USB1, + IRQ_P2F_ENET1, + IRQ_P2F_ENET_WAKE1, + IRQ_P2F_SDIO1, + IRQ_P2F_I2C1, + IRQ_P2F_SPI1, + IRQ_P2F_UART1, + IRQ_P2F_CAN1, + IRQ_F2P, + Core0_nFIQ, + Core0_nIRQ, + Core1_nFIQ, + Core1_nIRQ, + DMA0_DATYPE, + DMA0_DAVALID, + DMA0_DRREADY, + DMA0_RSTN, + DMA1_DATYPE, + DMA1_DAVALID, + DMA1_DRREADY, + DMA1_RSTN, + DMA2_DATYPE, + DMA2_DAVALID, + DMA2_DRREADY, + DMA2_RSTN, + DMA3_DATYPE, + DMA3_DAVALID, + DMA3_DRREADY, + DMA3_RSTN, + DMA0_ACLK, + DMA0_DAREADY, + DMA0_DRLAST, + DMA0_DRVALID, + DMA1_ACLK, + DMA1_DAREADY, + DMA1_DRLAST, + DMA1_DRVALID, + DMA2_ACLK, + DMA2_DAREADY, + DMA2_DRLAST, + DMA2_DRVALID, + DMA3_ACLK, + DMA3_DAREADY, + DMA3_DRLAST, + DMA3_DRVALID, + DMA0_DRTYPE, + DMA1_DRTYPE, + DMA2_DRTYPE, + DMA3_DRTYPE, + FCLK_CLK3, + FCLK_CLK2, + FCLK_CLK1, + FCLK_CLK0, + FCLK_CLKTRIG3_N, + FCLK_CLKTRIG2_N, + FCLK_CLKTRIG1_N, + FCLK_CLKTRIG0_N, + FCLK_RESET3_N, + FCLK_RESET2_N, + FCLK_RESET1_N, + FCLK_RESET0_N, + FTMD_TRACEIN_DATA, + FTMD_TRACEIN_VALID, + FTMD_TRACEIN_CLK, + FTMD_TRACEIN_ATID, + FTMT_F2P_TRIG_0, + FTMT_F2P_TRIGACK_0, + FTMT_F2P_TRIG_1, + FTMT_F2P_TRIGACK_1, + FTMT_F2P_TRIG_2, + FTMT_F2P_TRIGACK_2, + FTMT_F2P_TRIG_3, + FTMT_F2P_TRIGACK_3, + FTMT_F2P_DEBUG, + FTMT_P2F_TRIGACK_0, + FTMT_P2F_TRIG_0, + FTMT_P2F_TRIGACK_1, + FTMT_P2F_TRIG_1, + FTMT_P2F_TRIGACK_2, + FTMT_P2F_TRIG_2, + FTMT_P2F_TRIGACK_3, + FTMT_P2F_TRIG_3, + FTMT_P2F_DEBUG, + FPGA_IDLE_N, + EVENT_EVENTO, + EVENT_STANDBYWFE, + EVENT_STANDBYWFI, + EVENT_EVENTI, + DDR_ARB, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB); + output CAN0_PHY_TX; + input CAN0_PHY_RX; + output CAN1_PHY_TX; + input CAN1_PHY_RX; + output ENET0_GMII_TX_EN; + output ENET0_GMII_TX_ER; + output ENET0_MDIO_MDC; + output ENET0_MDIO_O; + output ENET0_MDIO_T; + output ENET0_PTP_DELAY_REQ_RX; + output ENET0_PTP_DELAY_REQ_TX; + output ENET0_PTP_PDELAY_REQ_RX; + output ENET0_PTP_PDELAY_REQ_TX; + output ENET0_PTP_PDELAY_RESP_RX; + output ENET0_PTP_PDELAY_RESP_TX; + output ENET0_PTP_SYNC_FRAME_RX; + output ENET0_PTP_SYNC_FRAME_TX; + output ENET0_SOF_RX; + output ENET0_SOF_TX; + output [7:0]ENET0_GMII_TXD; + input ENET0_GMII_COL; + input ENET0_GMII_CRS; + input ENET0_GMII_RX_CLK; + input ENET0_GMII_RX_DV; + input ENET0_GMII_RX_ER; + input ENET0_GMII_TX_CLK; + input ENET0_MDIO_I; + input ENET0_EXT_INTIN; + input [7:0]ENET0_GMII_RXD; + output ENET1_GMII_TX_EN; + output ENET1_GMII_TX_ER; + output ENET1_MDIO_MDC; + output ENET1_MDIO_O; + output ENET1_MDIO_T; + output ENET1_PTP_DELAY_REQ_RX; + output ENET1_PTP_DELAY_REQ_TX; + output ENET1_PTP_PDELAY_REQ_RX; + output ENET1_PTP_PDELAY_REQ_TX; + output ENET1_PTP_PDELAY_RESP_RX; + output ENET1_PTP_PDELAY_RESP_TX; + output ENET1_PTP_SYNC_FRAME_RX; + output ENET1_PTP_SYNC_FRAME_TX; + output ENET1_SOF_RX; + output ENET1_SOF_TX; + output [7:0]ENET1_GMII_TXD; + input ENET1_GMII_COL; + input ENET1_GMII_CRS; + input ENET1_GMII_RX_CLK; + input ENET1_GMII_RX_DV; + input ENET1_GMII_RX_ER; + input ENET1_GMII_TX_CLK; + input ENET1_MDIO_I; + input ENET1_EXT_INTIN; + input [7:0]ENET1_GMII_RXD; + input [63:0]GPIO_I; + output [63:0]GPIO_O; + output [63:0]GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + input I2C1_SDA_I; + output I2C1_SDA_O; + output I2C1_SDA_T; + input I2C1_SCL_I; + output I2C1_SCL_O; + output I2C1_SCL_T; + input PJTAG_TCK; + input PJTAG_TMS; + input PJTAG_TDI; + output PJTAG_TDO; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0]SDIO0_DATA_I; + output [3:0]SDIO0_DATA_O; + output [3:0]SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0]SDIO0_BUSVOLT; + output SDIO1_CLK; + input SDIO1_CLK_FB; + output SDIO1_CMD_O; + input SDIO1_CMD_I; + output SDIO1_CMD_T; + input [3:0]SDIO1_DATA_I; + output [3:0]SDIO1_DATA_O; + output [3:0]SDIO1_DATA_T; + output SDIO1_LED; + input SDIO1_CDN; + input SDIO1_WP; + output SDIO1_BUSPOW; + output [2:0]SDIO1_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_DTRN; + output UART0_RTSN; + output UART0_TX; + input UART0_CTSN; + input UART0_DCDN; + input UART0_DSRN; + input UART0_RIN; + input UART0_RX; + output UART1_DTRN; + output UART1_RTSN; + output UART1_TX; + input UART1_CTSN; + input UART1_DCDN; + input UART1_DSRN; + input UART1_RIN; + input UART1_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + input TTC0_CLK0_IN; + input TTC0_CLK1_IN; + input TTC0_CLK2_IN; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + input TTC1_CLK0_IN; + input TTC1_CLK1_IN; + input TTC1_CLK2_IN; + input WDT_CLK_IN; + output WDT_RST_OUT; + input TRACE_CLK; + output TRACE_CTL; + output [1:0]TRACE_DATA; + output TRACE_CLK_OUT; + output [1:0]USB0_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + output [1:0]USB1_PORT_INDCTL; + output USB1_VBUS_PWRSELECT; + input USB1_VBUS_PWRFAULT; + input SRAM_INTIN; + output M_AXI_GP0_ARESETN; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [11:0]M_AXI_GP0_ARID; + output [11:0]M_AXI_GP0_AWID; + output [11:0]M_AXI_GP0_WID; + output [1:0]M_AXI_GP0_ARBURST; + output [1:0]M_AXI_GP0_ARLOCK; + output [2:0]M_AXI_GP0_ARSIZE; + output [1:0]M_AXI_GP0_AWBURST; + output [1:0]M_AXI_GP0_AWLOCK; + output [2:0]M_AXI_GP0_AWSIZE; + output [2:0]M_AXI_GP0_ARPROT; + output [2:0]M_AXI_GP0_AWPROT; + output [31:0]M_AXI_GP0_ARADDR; + output [31:0]M_AXI_GP0_AWADDR; + output [31:0]M_AXI_GP0_WDATA; + output [3:0]M_AXI_GP0_ARCACHE; + output [3:0]M_AXI_GP0_ARLEN; + output [3:0]M_AXI_GP0_ARQOS; + output [3:0]M_AXI_GP0_AWCACHE; + output [3:0]M_AXI_GP0_AWLEN; + output [3:0]M_AXI_GP0_AWQOS; + output [3:0]M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [11:0]M_AXI_GP0_BID; + input [11:0]M_AXI_GP0_RID; + input [1:0]M_AXI_GP0_BRESP; + input [1:0]M_AXI_GP0_RRESP; + input [31:0]M_AXI_GP0_RDATA; + output M_AXI_GP1_ARESETN; + output M_AXI_GP1_ARVALID; + output M_AXI_GP1_AWVALID; + output M_AXI_GP1_BREADY; + output M_AXI_GP1_RREADY; + output M_AXI_GP1_WLAST; + output M_AXI_GP1_WVALID; + output [11:0]M_AXI_GP1_ARID; + output [11:0]M_AXI_GP1_AWID; + output [11:0]M_AXI_GP1_WID; + output [1:0]M_AXI_GP1_ARBURST; + output [1:0]M_AXI_GP1_ARLOCK; + output [2:0]M_AXI_GP1_ARSIZE; + output [1:0]M_AXI_GP1_AWBURST; + output [1:0]M_AXI_GP1_AWLOCK; + output [2:0]M_AXI_GP1_AWSIZE; + output [2:0]M_AXI_GP1_ARPROT; + output [2:0]M_AXI_GP1_AWPROT; + output [31:0]M_AXI_GP1_ARADDR; + output [31:0]M_AXI_GP1_AWADDR; + output [31:0]M_AXI_GP1_WDATA; + output [3:0]M_AXI_GP1_ARCACHE; + output [3:0]M_AXI_GP1_ARLEN; + output [3:0]M_AXI_GP1_ARQOS; + output [3:0]M_AXI_GP1_AWCACHE; + output [3:0]M_AXI_GP1_AWLEN; + output [3:0]M_AXI_GP1_AWQOS; + output [3:0]M_AXI_GP1_WSTRB; + input M_AXI_GP1_ACLK; + input M_AXI_GP1_ARREADY; + input M_AXI_GP1_AWREADY; + input M_AXI_GP1_BVALID; + input M_AXI_GP1_RLAST; + input M_AXI_GP1_RVALID; + input M_AXI_GP1_WREADY; + input [11:0]M_AXI_GP1_BID; + input [11:0]M_AXI_GP1_RID; + input [1:0]M_AXI_GP1_BRESP; + input [1:0]M_AXI_GP1_RRESP; + input [31:0]M_AXI_GP1_RDATA; + output S_AXI_GP0_ARESETN; + output S_AXI_GP0_ARREADY; + output S_AXI_GP0_AWREADY; + output S_AXI_GP0_BVALID; + output S_AXI_GP0_RLAST; + output S_AXI_GP0_RVALID; + output S_AXI_GP0_WREADY; + output [1:0]S_AXI_GP0_BRESP; + output [1:0]S_AXI_GP0_RRESP; + output [31:0]S_AXI_GP0_RDATA; + output [5:0]S_AXI_GP0_BID; + output [5:0]S_AXI_GP0_RID; + input S_AXI_GP0_ACLK; + input S_AXI_GP0_ARVALID; + input S_AXI_GP0_AWVALID; + input S_AXI_GP0_BREADY; + input S_AXI_GP0_RREADY; + input S_AXI_GP0_WLAST; + input S_AXI_GP0_WVALID; + input [1:0]S_AXI_GP0_ARBURST; + input [1:0]S_AXI_GP0_ARLOCK; + input [2:0]S_AXI_GP0_ARSIZE; + input [1:0]S_AXI_GP0_AWBURST; + input [1:0]S_AXI_GP0_AWLOCK; + input [2:0]S_AXI_GP0_AWSIZE; + input [2:0]S_AXI_GP0_ARPROT; + input [2:0]S_AXI_GP0_AWPROT; + input [31:0]S_AXI_GP0_ARADDR; + input [31:0]S_AXI_GP0_AWADDR; + input [31:0]S_AXI_GP0_WDATA; + input [3:0]S_AXI_GP0_ARCACHE; + input [3:0]S_AXI_GP0_ARLEN; + input [3:0]S_AXI_GP0_ARQOS; + input [3:0]S_AXI_GP0_AWCACHE; + input [3:0]S_AXI_GP0_AWLEN; + input [3:0]S_AXI_GP0_AWQOS; + input [3:0]S_AXI_GP0_WSTRB; + input [5:0]S_AXI_GP0_ARID; + input [5:0]S_AXI_GP0_AWID; + input [5:0]S_AXI_GP0_WID; + output S_AXI_GP1_ARESETN; + output S_AXI_GP1_ARREADY; + output S_AXI_GP1_AWREADY; + output S_AXI_GP1_BVALID; + output S_AXI_GP1_RLAST; + output S_AXI_GP1_RVALID; + output S_AXI_GP1_WREADY; + output [1:0]S_AXI_GP1_BRESP; + output [1:0]S_AXI_GP1_RRESP; + output [31:0]S_AXI_GP1_RDATA; + output [5:0]S_AXI_GP1_BID; + output [5:0]S_AXI_GP1_RID; + input S_AXI_GP1_ACLK; + input S_AXI_GP1_ARVALID; + input S_AXI_GP1_AWVALID; + input S_AXI_GP1_BREADY; + input S_AXI_GP1_RREADY; + input S_AXI_GP1_WLAST; + input S_AXI_GP1_WVALID; + input [1:0]S_AXI_GP1_ARBURST; + input [1:0]S_AXI_GP1_ARLOCK; + input [2:0]S_AXI_GP1_ARSIZE; + input [1:0]S_AXI_GP1_AWBURST; + input [1:0]S_AXI_GP1_AWLOCK; + input [2:0]S_AXI_GP1_AWSIZE; + input [2:0]S_AXI_GP1_ARPROT; + input [2:0]S_AXI_GP1_AWPROT; + input [31:0]S_AXI_GP1_ARADDR; + input [31:0]S_AXI_GP1_AWADDR; + input [31:0]S_AXI_GP1_WDATA; + input [3:0]S_AXI_GP1_ARCACHE; + input [3:0]S_AXI_GP1_ARLEN; + input [3:0]S_AXI_GP1_ARQOS; + input [3:0]S_AXI_GP1_AWCACHE; + input [3:0]S_AXI_GP1_AWLEN; + input [3:0]S_AXI_GP1_AWQOS; + input [3:0]S_AXI_GP1_WSTRB; + input [5:0]S_AXI_GP1_ARID; + input [5:0]S_AXI_GP1_AWID; + input [5:0]S_AXI_GP1_WID; + output S_AXI_ACP_ARESETN; + output S_AXI_ACP_ARREADY; + output S_AXI_ACP_AWREADY; + output S_AXI_ACP_BVALID; + output S_AXI_ACP_RLAST; + output S_AXI_ACP_RVALID; + output S_AXI_ACP_WREADY; + output [1:0]S_AXI_ACP_BRESP; + output [1:0]S_AXI_ACP_RRESP; + output [2:0]S_AXI_ACP_BID; + output [2:0]S_AXI_ACP_RID; + output [63:0]S_AXI_ACP_RDATA; + input S_AXI_ACP_ACLK; + input S_AXI_ACP_ARVALID; + input S_AXI_ACP_AWVALID; + input S_AXI_ACP_BREADY; + input S_AXI_ACP_RREADY; + input S_AXI_ACP_WLAST; + input S_AXI_ACP_WVALID; + input [2:0]S_AXI_ACP_ARID; + input [2:0]S_AXI_ACP_ARPROT; + input [2:0]S_AXI_ACP_AWID; + input [2:0]S_AXI_ACP_AWPROT; + input [2:0]S_AXI_ACP_WID; + input [31:0]S_AXI_ACP_ARADDR; + input [31:0]S_AXI_ACP_AWADDR; + input [3:0]S_AXI_ACP_ARCACHE; + input [3:0]S_AXI_ACP_ARLEN; + input [3:0]S_AXI_ACP_ARQOS; + input [3:0]S_AXI_ACP_AWCACHE; + input [3:0]S_AXI_ACP_AWLEN; + input [3:0]S_AXI_ACP_AWQOS; + input [1:0]S_AXI_ACP_ARBURST; + input [1:0]S_AXI_ACP_ARLOCK; + input [2:0]S_AXI_ACP_ARSIZE; + input [1:0]S_AXI_ACP_AWBURST; + input [1:0]S_AXI_ACP_AWLOCK; + input [2:0]S_AXI_ACP_AWSIZE; + input [4:0]S_AXI_ACP_ARUSER; + input [4:0]S_AXI_ACP_AWUSER; + input [63:0]S_AXI_ACP_WDATA; + input [7:0]S_AXI_ACP_WSTRB; + output S_AXI_HP0_ARESETN; + output S_AXI_HP0_ARREADY; + output S_AXI_HP0_AWREADY; + output S_AXI_HP0_BVALID; + output S_AXI_HP0_RLAST; + output S_AXI_HP0_RVALID; + output S_AXI_HP0_WREADY; + output [1:0]S_AXI_HP0_BRESP; + output [1:0]S_AXI_HP0_RRESP; + output [5:0]S_AXI_HP0_BID; + output [5:0]S_AXI_HP0_RID; + output [63:0]S_AXI_HP0_RDATA; + output [7:0]S_AXI_HP0_RCOUNT; + output [7:0]S_AXI_HP0_WCOUNT; + output [2:0]S_AXI_HP0_RACOUNT; + output [5:0]S_AXI_HP0_WACOUNT; + input S_AXI_HP0_ACLK; + input S_AXI_HP0_ARVALID; + input S_AXI_HP0_AWVALID; + input S_AXI_HP0_BREADY; + input S_AXI_HP0_RDISSUECAP1_EN; + input S_AXI_HP0_RREADY; + input S_AXI_HP0_WLAST; + input S_AXI_HP0_WRISSUECAP1_EN; + input S_AXI_HP0_WVALID; + input [1:0]S_AXI_HP0_ARBURST; + input [1:0]S_AXI_HP0_ARLOCK; + input [2:0]S_AXI_HP0_ARSIZE; + input [1:0]S_AXI_HP0_AWBURST; + input [1:0]S_AXI_HP0_AWLOCK; + input [2:0]S_AXI_HP0_AWSIZE; + input [2:0]S_AXI_HP0_ARPROT; + input [2:0]S_AXI_HP0_AWPROT; + input [31:0]S_AXI_HP0_ARADDR; + input [31:0]S_AXI_HP0_AWADDR; + input [3:0]S_AXI_HP0_ARCACHE; + input [3:0]S_AXI_HP0_ARLEN; + input [3:0]S_AXI_HP0_ARQOS; + input [3:0]S_AXI_HP0_AWCACHE; + input [3:0]S_AXI_HP0_AWLEN; + input [3:0]S_AXI_HP0_AWQOS; + input [5:0]S_AXI_HP0_ARID; + input [5:0]S_AXI_HP0_AWID; + input [5:0]S_AXI_HP0_WID; + input [63:0]S_AXI_HP0_WDATA; + input [7:0]S_AXI_HP0_WSTRB; + output S_AXI_HP1_ARESETN; + output S_AXI_HP1_ARREADY; + output S_AXI_HP1_AWREADY; + output S_AXI_HP1_BVALID; + output S_AXI_HP1_RLAST; + output S_AXI_HP1_RVALID; + output S_AXI_HP1_WREADY; + output [1:0]S_AXI_HP1_BRESP; + output [1:0]S_AXI_HP1_RRESP; + output [5:0]S_AXI_HP1_BID; + output [5:0]S_AXI_HP1_RID; + output [63:0]S_AXI_HP1_RDATA; + output [7:0]S_AXI_HP1_RCOUNT; + output [7:0]S_AXI_HP1_WCOUNT; + output [2:0]S_AXI_HP1_RACOUNT; + output [5:0]S_AXI_HP1_WACOUNT; + input S_AXI_HP1_ACLK; + input S_AXI_HP1_ARVALID; + input S_AXI_HP1_AWVALID; + input S_AXI_HP1_BREADY; + input S_AXI_HP1_RDISSUECAP1_EN; + input S_AXI_HP1_RREADY; + input S_AXI_HP1_WLAST; + input S_AXI_HP1_WRISSUECAP1_EN; + input S_AXI_HP1_WVALID; + input [1:0]S_AXI_HP1_ARBURST; + input [1:0]S_AXI_HP1_ARLOCK; + input [2:0]S_AXI_HP1_ARSIZE; + input [1:0]S_AXI_HP1_AWBURST; + input [1:0]S_AXI_HP1_AWLOCK; + input [2:0]S_AXI_HP1_AWSIZE; + input [2:0]S_AXI_HP1_ARPROT; + input [2:0]S_AXI_HP1_AWPROT; + input [31:0]S_AXI_HP1_ARADDR; + input [31:0]S_AXI_HP1_AWADDR; + input [3:0]S_AXI_HP1_ARCACHE; + input [3:0]S_AXI_HP1_ARLEN; + input [3:0]S_AXI_HP1_ARQOS; + input [3:0]S_AXI_HP1_AWCACHE; + input [3:0]S_AXI_HP1_AWLEN; + input [3:0]S_AXI_HP1_AWQOS; + input [5:0]S_AXI_HP1_ARID; + input [5:0]S_AXI_HP1_AWID; + input [5:0]S_AXI_HP1_WID; + input [63:0]S_AXI_HP1_WDATA; + input [7:0]S_AXI_HP1_WSTRB; + output S_AXI_HP2_ARESETN; + output S_AXI_HP2_ARREADY; + output S_AXI_HP2_AWREADY; + output S_AXI_HP2_BVALID; + output S_AXI_HP2_RLAST; + output S_AXI_HP2_RVALID; + output S_AXI_HP2_WREADY; + output [1:0]S_AXI_HP2_BRESP; + output [1:0]S_AXI_HP2_RRESP; + output [5:0]S_AXI_HP2_BID; + output [5:0]S_AXI_HP2_RID; + output [63:0]S_AXI_HP2_RDATA; + output [7:0]S_AXI_HP2_RCOUNT; + output [7:0]S_AXI_HP2_WCOUNT; + output [2:0]S_AXI_HP2_RACOUNT; + output [5:0]S_AXI_HP2_WACOUNT; + input S_AXI_HP2_ACLK; + input S_AXI_HP2_ARVALID; + input S_AXI_HP2_AWVALID; + input S_AXI_HP2_BREADY; + input S_AXI_HP2_RDISSUECAP1_EN; + input S_AXI_HP2_RREADY; + input S_AXI_HP2_WLAST; + input S_AXI_HP2_WRISSUECAP1_EN; + input S_AXI_HP2_WVALID; + input [1:0]S_AXI_HP2_ARBURST; + input [1:0]S_AXI_HP2_ARLOCK; + input [2:0]S_AXI_HP2_ARSIZE; + input [1:0]S_AXI_HP2_AWBURST; + input [1:0]S_AXI_HP2_AWLOCK; + input [2:0]S_AXI_HP2_AWSIZE; + input [2:0]S_AXI_HP2_ARPROT; + input [2:0]S_AXI_HP2_AWPROT; + input [31:0]S_AXI_HP2_ARADDR; + input [31:0]S_AXI_HP2_AWADDR; + input [3:0]S_AXI_HP2_ARCACHE; + input [3:0]S_AXI_HP2_ARLEN; + input [3:0]S_AXI_HP2_ARQOS; + input [3:0]S_AXI_HP2_AWCACHE; + input [3:0]S_AXI_HP2_AWLEN; + input [3:0]S_AXI_HP2_AWQOS; + input [5:0]S_AXI_HP2_ARID; + input [5:0]S_AXI_HP2_AWID; + input [5:0]S_AXI_HP2_WID; + input [63:0]S_AXI_HP2_WDATA; + input [7:0]S_AXI_HP2_WSTRB; + output S_AXI_HP3_ARESETN; + output S_AXI_HP3_ARREADY; + output S_AXI_HP3_AWREADY; + output S_AXI_HP3_BVALID; + output S_AXI_HP3_RLAST; + output S_AXI_HP3_RVALID; + output S_AXI_HP3_WREADY; + output [1:0]S_AXI_HP3_BRESP; + output [1:0]S_AXI_HP3_RRESP; + output [5:0]S_AXI_HP3_BID; + output [5:0]S_AXI_HP3_RID; + output [63:0]S_AXI_HP3_RDATA; + output [7:0]S_AXI_HP3_RCOUNT; + output [7:0]S_AXI_HP3_WCOUNT; + output [2:0]S_AXI_HP3_RACOUNT; + output [5:0]S_AXI_HP3_WACOUNT; + input S_AXI_HP3_ACLK; + input S_AXI_HP3_ARVALID; + input S_AXI_HP3_AWVALID; + input S_AXI_HP3_BREADY; + input S_AXI_HP3_RDISSUECAP1_EN; + input S_AXI_HP3_RREADY; + input S_AXI_HP3_WLAST; + input S_AXI_HP3_WRISSUECAP1_EN; + input S_AXI_HP3_WVALID; + input [1:0]S_AXI_HP3_ARBURST; + input [1:0]S_AXI_HP3_ARLOCK; + input [2:0]S_AXI_HP3_ARSIZE; + input [1:0]S_AXI_HP3_AWBURST; + input [1:0]S_AXI_HP3_AWLOCK; + input [2:0]S_AXI_HP3_AWSIZE; + input [2:0]S_AXI_HP3_ARPROT; + input [2:0]S_AXI_HP3_AWPROT; + input [31:0]S_AXI_HP3_ARADDR; + input [31:0]S_AXI_HP3_AWADDR; + input [3:0]S_AXI_HP3_ARCACHE; + input [3:0]S_AXI_HP3_ARLEN; + input [3:0]S_AXI_HP3_ARQOS; + input [3:0]S_AXI_HP3_AWCACHE; + input [3:0]S_AXI_HP3_AWLEN; + input [3:0]S_AXI_HP3_AWQOS; + input [5:0]S_AXI_HP3_ARID; + input [5:0]S_AXI_HP3_AWID; + input [5:0]S_AXI_HP3_WID; + input [63:0]S_AXI_HP3_WDATA; + input [7:0]S_AXI_HP3_WSTRB; + output IRQ_P2F_DMAC_ABORT; + output IRQ_P2F_DMAC0; + output IRQ_P2F_DMAC1; + output IRQ_P2F_DMAC2; + output IRQ_P2F_DMAC3; + output IRQ_P2F_DMAC4; + output IRQ_P2F_DMAC5; + output IRQ_P2F_DMAC6; + output IRQ_P2F_DMAC7; + output IRQ_P2F_SMC; + output IRQ_P2F_QSPI; + output IRQ_P2F_CTI; + output IRQ_P2F_GPIO; + output IRQ_P2F_USB0; + output IRQ_P2F_ENET0; + output IRQ_P2F_ENET_WAKE0; + output IRQ_P2F_SDIO0; + output IRQ_P2F_I2C0; + output IRQ_P2F_SPI0; + output IRQ_P2F_UART0; + output IRQ_P2F_CAN0; + output IRQ_P2F_USB1; + output IRQ_P2F_ENET1; + output IRQ_P2F_ENET_WAKE1; + output IRQ_P2F_SDIO1; + output IRQ_P2F_I2C1; + output IRQ_P2F_SPI1; + output IRQ_P2F_UART1; + output IRQ_P2F_CAN1; + input [0:0]IRQ_F2P; + input Core0_nFIQ; + input Core0_nIRQ; + input Core1_nFIQ; + input Core1_nIRQ; + output [1:0]DMA0_DATYPE; + output DMA0_DAVALID; + output DMA0_DRREADY; + output DMA0_RSTN; + output [1:0]DMA1_DATYPE; + output DMA1_DAVALID; + output DMA1_DRREADY; + output DMA1_RSTN; + output [1:0]DMA2_DATYPE; + output DMA2_DAVALID; + output DMA2_DRREADY; + output DMA2_RSTN; + output [1:0]DMA3_DATYPE; + output DMA3_DAVALID; + output DMA3_DRREADY; + output DMA3_RSTN; + input DMA0_ACLK; + input DMA0_DAREADY; + input DMA0_DRLAST; + input DMA0_DRVALID; + input DMA1_ACLK; + input DMA1_DAREADY; + input DMA1_DRLAST; + input DMA1_DRVALID; + input DMA2_ACLK; + input DMA2_DAREADY; + input DMA2_DRLAST; + input DMA2_DRVALID; + input DMA3_ACLK; + input DMA3_DAREADY; + input DMA3_DRLAST; + input DMA3_DRVALID; + input [1:0]DMA0_DRTYPE; + input [1:0]DMA1_DRTYPE; + input [1:0]DMA2_DRTYPE; + input [1:0]DMA3_DRTYPE; + output FCLK_CLK3; + output FCLK_CLK2; + output FCLK_CLK1; + output FCLK_CLK0; + input FCLK_CLKTRIG3_N; + input FCLK_CLKTRIG2_N; + input FCLK_CLKTRIG1_N; + input FCLK_CLKTRIG0_N; + output FCLK_RESET3_N; + output FCLK_RESET2_N; + output FCLK_RESET1_N; + output FCLK_RESET0_N; + input [31:0]FTMD_TRACEIN_DATA; + input FTMD_TRACEIN_VALID; + input FTMD_TRACEIN_CLK; + input [3:0]FTMD_TRACEIN_ATID; + input FTMT_F2P_TRIG_0; + output FTMT_F2P_TRIGACK_0; + input FTMT_F2P_TRIG_1; + output FTMT_F2P_TRIGACK_1; + input FTMT_F2P_TRIG_2; + output FTMT_F2P_TRIGACK_2; + input FTMT_F2P_TRIG_3; + output FTMT_F2P_TRIGACK_3; + input [31:0]FTMT_F2P_DEBUG; + input FTMT_P2F_TRIGACK_0; + output FTMT_P2F_TRIG_0; + input FTMT_P2F_TRIGACK_1; + output FTMT_P2F_TRIG_1; + input FTMT_P2F_TRIGACK_2; + output FTMT_P2F_TRIG_2; + input FTMT_P2F_TRIGACK_3; + output FTMT_P2F_TRIG_3; + output [31:0]FTMT_P2F_DEBUG; + input FPGA_IDLE_N; + output EVENT_EVENTO; + output [1:0]EVENT_STANDBYWFE; + output [1:0]EVENT_STANDBYWFI; + input EVENT_EVENTI; + input [3:0]DDR_ARB; + inout [31:0]MIO; + inout DDR_CAS_n; + inout DDR_CKE; + inout DDR_Clk_n; + inout DDR_Clk; + inout DDR_CS_n; + inout DDR_DRSTB; + inout DDR_ODT; + inout DDR_RAS_n; + inout DDR_WEB; + inout [2:0]DDR_BankAddr; + inout [14:0]DDR_Addr; + inout DDR_VRN; + inout DDR_VRP; + inout [1:0]DDR_DM; + inout [15:0]DDR_DQ; + inout [1:0]DDR_DQS_n; + inout [1:0]DDR_DQS; + inout PS_SRSTB; + inout PS_CLK; + inout PS_PORB; + + wire \ ; + wire \ ; + wire CAN0_PHY_RX; + wire CAN0_PHY_TX; + wire CAN1_PHY_RX; + wire CAN1_PHY_TX; + wire Core0_nFIQ; + wire Core0_nIRQ; + wire Core1_nFIQ; + wire Core1_nIRQ; + wire [3:0]DDR_ARB; + wire [14:0]DDR_Addr; + wire [2:0]DDR_BankAddr; + wire DDR_CAS_n; + wire DDR_CKE; + wire DDR_CS_n; + wire DDR_Clk; + wire DDR_Clk_n; + wire [1:0]DDR_DM; + wire [15:0]DDR_DQ; + wire [1:0]DDR_DQS; + wire [1:0]DDR_DQS_n; + wire DDR_DRSTB; + wire DDR_ODT; + wire DDR_RAS_n; + wire DDR_VRN; + wire DDR_VRP; + wire DDR_WEB; + wire DMA0_ACLK; + wire DMA0_DAREADY; + wire [1:0]DMA0_DATYPE; + wire DMA0_DAVALID; + wire DMA0_DRLAST; + wire DMA0_DRREADY; + wire [1:0]DMA0_DRTYPE; + wire DMA0_DRVALID; + wire DMA0_RSTN; + wire DMA1_ACLK; + wire DMA1_DAREADY; + wire [1:0]DMA1_DATYPE; + wire DMA1_DAVALID; + wire DMA1_DRLAST; + wire DMA1_DRREADY; + wire [1:0]DMA1_DRTYPE; + wire DMA1_DRVALID; + wire DMA1_RSTN; + wire DMA2_ACLK; + wire DMA2_DAREADY; + wire [1:0]DMA2_DATYPE; + wire DMA2_DAVALID; + wire DMA2_DRLAST; + wire DMA2_DRREADY; + wire [1:0]DMA2_DRTYPE; + wire DMA2_DRVALID; + wire DMA2_RSTN; + wire DMA3_ACLK; + wire DMA3_DAREADY; + wire [1:0]DMA3_DATYPE; + wire DMA3_DAVALID; + wire DMA3_DRLAST; + wire DMA3_DRREADY; + wire [1:0]DMA3_DRTYPE; + wire DMA3_DRVALID; + wire DMA3_RSTN; + wire ENET0_EXT_INTIN; + wire ENET0_GMII_RX_CLK; + wire ENET0_GMII_TX_CLK; + wire ENET0_MDIO_I; + wire ENET0_MDIO_MDC; + wire ENET0_MDIO_O; + wire ENET0_MDIO_T; + wire ENET0_MDIO_T_n; + wire ENET0_PTP_DELAY_REQ_RX; + wire ENET0_PTP_DELAY_REQ_TX; + wire ENET0_PTP_PDELAY_REQ_RX; + wire ENET0_PTP_PDELAY_REQ_TX; + wire ENET0_PTP_PDELAY_RESP_RX; + wire ENET0_PTP_PDELAY_RESP_TX; + wire ENET0_PTP_SYNC_FRAME_RX; + wire ENET0_PTP_SYNC_FRAME_TX; + wire ENET0_SOF_RX; + wire ENET0_SOF_TX; + wire ENET1_EXT_INTIN; + wire ENET1_GMII_RX_CLK; + wire ENET1_GMII_TX_CLK; + wire ENET1_MDIO_I; + wire ENET1_MDIO_MDC; + wire ENET1_MDIO_O; + wire ENET1_MDIO_T; + wire ENET1_MDIO_T_n; + wire ENET1_PTP_DELAY_REQ_RX; + wire ENET1_PTP_DELAY_REQ_TX; + wire ENET1_PTP_PDELAY_REQ_RX; + wire ENET1_PTP_PDELAY_REQ_TX; + wire ENET1_PTP_PDELAY_RESP_RX; + wire ENET1_PTP_PDELAY_RESP_TX; + wire ENET1_PTP_SYNC_FRAME_RX; + wire ENET1_PTP_SYNC_FRAME_TX; + wire ENET1_SOF_RX; + wire ENET1_SOF_TX; + wire EVENT_EVENTI; + wire EVENT_EVENTO; + wire [1:0]EVENT_STANDBYWFE; + wire [1:0]EVENT_STANDBYWFI; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire [1:0]FCLK_CLK_unbuffered; + wire FCLK_RESET0_N; + wire FCLK_RESET1_N; + wire FCLK_RESET2_N; + wire FCLK_RESET3_N; + wire FPGA_IDLE_N; + wire FTMD_TRACEIN_CLK; + wire [31:0]FTMT_F2P_DEBUG; + wire FTMT_F2P_TRIGACK_0; + wire FTMT_F2P_TRIGACK_1; + wire FTMT_F2P_TRIGACK_2; + wire FTMT_F2P_TRIGACK_3; + wire FTMT_F2P_TRIG_0; + wire FTMT_F2P_TRIG_1; + wire FTMT_F2P_TRIG_2; + wire FTMT_F2P_TRIG_3; + wire [31:0]FTMT_P2F_DEBUG; + wire FTMT_P2F_TRIGACK_0; + wire FTMT_P2F_TRIGACK_1; + wire FTMT_P2F_TRIGACK_2; + wire FTMT_P2F_TRIGACK_3; + wire FTMT_P2F_TRIG_0; + wire FTMT_P2F_TRIG_1; + wire FTMT_P2F_TRIG_2; + wire FTMT_P2F_TRIG_3; + wire [63:0]GPIO_I; + wire [63:0]GPIO_O; + wire [63:0]GPIO_T; + wire I2C0_SCL_I; + wire I2C0_SCL_O; + wire I2C0_SCL_T; + wire I2C0_SCL_T_n; + wire I2C0_SDA_I; + wire I2C0_SDA_O; + wire I2C0_SDA_T; + wire I2C0_SDA_T_n; + wire I2C1_SCL_I; + wire I2C1_SCL_O; + wire I2C1_SCL_T; + wire I2C1_SCL_T_n; + wire I2C1_SDA_I; + wire I2C1_SDA_O; + wire I2C1_SDA_T; + wire I2C1_SDA_T_n; + wire [0:0]IRQ_F2P; + wire IRQ_P2F_CAN0; + wire IRQ_P2F_CAN1; + wire IRQ_P2F_CTI; + wire IRQ_P2F_DMAC0; + wire IRQ_P2F_DMAC1; + wire IRQ_P2F_DMAC2; + wire IRQ_P2F_DMAC3; + wire IRQ_P2F_DMAC4; + wire IRQ_P2F_DMAC5; + wire IRQ_P2F_DMAC6; + wire IRQ_P2F_DMAC7; + wire IRQ_P2F_DMAC_ABORT; + wire IRQ_P2F_ENET0; + wire IRQ_P2F_ENET1; + wire IRQ_P2F_ENET_WAKE0; + wire IRQ_P2F_ENET_WAKE1; + wire IRQ_P2F_GPIO; + wire IRQ_P2F_I2C0; + wire IRQ_P2F_I2C1; + wire IRQ_P2F_QSPI; + wire IRQ_P2F_SDIO0; + wire IRQ_P2F_SDIO1; + wire IRQ_P2F_SMC; + wire IRQ_P2F_SPI0; + wire IRQ_P2F_SPI1; + wire IRQ_P2F_UART0; + wire IRQ_P2F_UART1; + wire IRQ_P2F_USB0; + wire IRQ_P2F_USB1; + wire [31:0]MIO; + wire M_AXI_GP0_ACLK; + wire [31:0]M_AXI_GP0_ARADDR; + wire [1:0]M_AXI_GP0_ARBURST; + wire [3:0]\^M_AXI_GP0_ARCACHE ; + wire M_AXI_GP0_ARESETN; + wire [11:0]M_AXI_GP0_ARID; + wire [3:0]M_AXI_GP0_ARLEN; + wire [1:0]M_AXI_GP0_ARLOCK; + wire [2:0]M_AXI_GP0_ARPROT; + wire [3:0]M_AXI_GP0_ARQOS; + wire M_AXI_GP0_ARREADY; + wire [1:0]\^M_AXI_GP0_ARSIZE ; + wire M_AXI_GP0_ARVALID; + wire [31:0]M_AXI_GP0_AWADDR; + wire [1:0]M_AXI_GP0_AWBURST; + wire [3:0]\^M_AXI_GP0_AWCACHE ; + wire [11:0]M_AXI_GP0_AWID; + wire [3:0]M_AXI_GP0_AWLEN; + wire [1:0]M_AXI_GP0_AWLOCK; + wire [2:0]M_AXI_GP0_AWPROT; + wire [3:0]M_AXI_GP0_AWQOS; + wire M_AXI_GP0_AWREADY; + wire [1:0]\^M_AXI_GP0_AWSIZE ; + wire M_AXI_GP0_AWVALID; + wire [11:0]M_AXI_GP0_BID; + wire M_AXI_GP0_BREADY; + wire [1:0]M_AXI_GP0_BRESP; + wire M_AXI_GP0_BVALID; + wire [31:0]M_AXI_GP0_RDATA; + wire [11:0]M_AXI_GP0_RID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RREADY; + wire [1:0]M_AXI_GP0_RRESP; + wire M_AXI_GP0_RVALID; + wire [31:0]M_AXI_GP0_WDATA; + wire [11:0]M_AXI_GP0_WID; + wire M_AXI_GP0_WLAST; + wire M_AXI_GP0_WREADY; + wire [3:0]M_AXI_GP0_WSTRB; + wire M_AXI_GP0_WVALID; + wire M_AXI_GP1_ACLK; + wire [31:0]M_AXI_GP1_ARADDR; + wire [1:0]M_AXI_GP1_ARBURST; + wire [3:0]\^M_AXI_GP1_ARCACHE ; + wire M_AXI_GP1_ARESETN; + wire [11:0]M_AXI_GP1_ARID; + wire [3:0]M_AXI_GP1_ARLEN; + wire [1:0]M_AXI_GP1_ARLOCK; + wire [2:0]M_AXI_GP1_ARPROT; + wire [3:0]M_AXI_GP1_ARQOS; + wire M_AXI_GP1_ARREADY; + wire [1:0]\^M_AXI_GP1_ARSIZE ; + wire M_AXI_GP1_ARVALID; + wire [31:0]M_AXI_GP1_AWADDR; + wire [1:0]M_AXI_GP1_AWBURST; + wire [3:0]\^M_AXI_GP1_AWCACHE ; + wire [11:0]M_AXI_GP1_AWID; + wire [3:0]M_AXI_GP1_AWLEN; + wire [1:0]M_AXI_GP1_AWLOCK; + wire [2:0]M_AXI_GP1_AWPROT; + wire [3:0]M_AXI_GP1_AWQOS; + wire M_AXI_GP1_AWREADY; + wire [1:0]\^M_AXI_GP1_AWSIZE ; + wire M_AXI_GP1_AWVALID; + wire [11:0]M_AXI_GP1_BID; + wire M_AXI_GP1_BREADY; + wire [1:0]M_AXI_GP1_BRESP; + wire M_AXI_GP1_BVALID; + wire [31:0]M_AXI_GP1_RDATA; + wire [11:0]M_AXI_GP1_RID; + wire M_AXI_GP1_RLAST; + wire M_AXI_GP1_RREADY; + wire [1:0]M_AXI_GP1_RRESP; + wire M_AXI_GP1_RVALID; + wire [31:0]M_AXI_GP1_WDATA; + wire [11:0]M_AXI_GP1_WID; + wire M_AXI_GP1_WLAST; + wire M_AXI_GP1_WREADY; + wire [3:0]M_AXI_GP1_WSTRB; + wire M_AXI_GP1_WVALID; + wire PJTAG_TCK; + wire PJTAG_TDI; + wire PJTAG_TMS; + wire PS_CLK; + wire PS_PORB; + wire PS_SRSTB; + wire SDIO0_BUSPOW; + wire [2:0]SDIO0_BUSVOLT; + wire SDIO0_CDN; + wire SDIO0_CLK; + wire SDIO0_CLK_FB; + wire SDIO0_CMD_I; + wire SDIO0_CMD_O; + wire SDIO0_CMD_T; + wire SDIO0_CMD_T_n; + wire [3:0]SDIO0_DATA_I; + wire [3:0]SDIO0_DATA_O; + wire [3:0]SDIO0_DATA_T; + wire [3:0]SDIO0_DATA_T_n; + wire SDIO0_LED; + wire SDIO0_WP; + wire SDIO1_BUSPOW; + wire [2:0]SDIO1_BUSVOLT; + wire SDIO1_CDN; + wire SDIO1_CLK; + wire SDIO1_CLK_FB; + wire SDIO1_CMD_I; + wire SDIO1_CMD_O; + wire SDIO1_CMD_T; + wire SDIO1_CMD_T_n; + wire [3:0]SDIO1_DATA_I; + wire [3:0]SDIO1_DATA_O; + wire [3:0]SDIO1_DATA_T; + wire [3:0]SDIO1_DATA_T_n; + wire SDIO1_LED; + wire SDIO1_WP; + wire SPI0_MISO_I; + wire SPI0_MISO_O; + wire SPI0_MISO_T; + wire SPI0_MISO_T_n; + wire SPI0_MOSI_I; + wire SPI0_MOSI_O; + wire SPI0_MOSI_T; + wire SPI0_MOSI_T_n; + wire SPI0_SCLK_I; + wire SPI0_SCLK_O; + wire SPI0_SCLK_T; + wire SPI0_SCLK_T_n; + wire SPI0_SS1_O; + wire SPI0_SS2_O; + wire SPI0_SS_I; + wire SPI0_SS_O; + wire SPI0_SS_T; + wire SPI0_SS_T_n; + wire SPI1_MISO_I; + wire SPI1_MISO_O; + wire SPI1_MISO_T; + wire SPI1_MISO_T_n; + wire SPI1_MOSI_I; + wire SPI1_MOSI_O; + wire SPI1_MOSI_T; + wire SPI1_MOSI_T_n; + wire SPI1_SCLK_I; + wire SPI1_SCLK_O; + wire SPI1_SCLK_T; + wire SPI1_SCLK_T_n; + wire SPI1_SS1_O; + wire SPI1_SS2_O; + wire SPI1_SS_I; + wire SPI1_SS_O; + wire SPI1_SS_T; + wire SPI1_SS_T_n; + wire SRAM_INTIN; + wire S_AXI_ACP_ACLK; + wire [31:0]S_AXI_ACP_ARADDR; + wire [1:0]S_AXI_ACP_ARBURST; + wire [3:0]S_AXI_ACP_ARCACHE; + wire S_AXI_ACP_ARESETN; + wire [2:0]S_AXI_ACP_ARID; + wire [3:0]S_AXI_ACP_ARLEN; + wire [1:0]S_AXI_ACP_ARLOCK; + wire [2:0]S_AXI_ACP_ARPROT; + wire [3:0]S_AXI_ACP_ARQOS; + wire S_AXI_ACP_ARREADY; + wire [2:0]S_AXI_ACP_ARSIZE; + wire [4:0]S_AXI_ACP_ARUSER; + wire S_AXI_ACP_ARVALID; + wire [31:0]S_AXI_ACP_AWADDR; + wire [1:0]S_AXI_ACP_AWBURST; + wire [3:0]S_AXI_ACP_AWCACHE; + wire [2:0]S_AXI_ACP_AWID; + wire [3:0]S_AXI_ACP_AWLEN; + wire [1:0]S_AXI_ACP_AWLOCK; + wire [2:0]S_AXI_ACP_AWPROT; + wire [3:0]S_AXI_ACP_AWQOS; + wire S_AXI_ACP_AWREADY; + wire [2:0]S_AXI_ACP_AWSIZE; + wire [4:0]S_AXI_ACP_AWUSER; + wire S_AXI_ACP_AWVALID; + wire [2:0]S_AXI_ACP_BID; + wire S_AXI_ACP_BREADY; + wire [1:0]S_AXI_ACP_BRESP; + wire S_AXI_ACP_BVALID; + wire [63:0]S_AXI_ACP_RDATA; + wire [2:0]S_AXI_ACP_RID; + wire S_AXI_ACP_RLAST; + wire S_AXI_ACP_RREADY; + wire [1:0]S_AXI_ACP_RRESP; + wire S_AXI_ACP_RVALID; + wire [63:0]S_AXI_ACP_WDATA; + wire [2:0]S_AXI_ACP_WID; + wire S_AXI_ACP_WLAST; + wire S_AXI_ACP_WREADY; + wire [7:0]S_AXI_ACP_WSTRB; + wire S_AXI_ACP_WVALID; + wire S_AXI_GP0_ACLK; + wire [31:0]S_AXI_GP0_ARADDR; + wire [1:0]S_AXI_GP0_ARBURST; + wire [3:0]S_AXI_GP0_ARCACHE; + wire S_AXI_GP0_ARESETN; + wire [5:0]S_AXI_GP0_ARID; + wire [3:0]S_AXI_GP0_ARLEN; + wire [1:0]S_AXI_GP0_ARLOCK; + wire [2:0]S_AXI_GP0_ARPROT; + wire [3:0]S_AXI_GP0_ARQOS; + wire S_AXI_GP0_ARREADY; + wire [2:0]S_AXI_GP0_ARSIZE; + wire S_AXI_GP0_ARVALID; + wire [31:0]S_AXI_GP0_AWADDR; + wire [1:0]S_AXI_GP0_AWBURST; + wire [3:0]S_AXI_GP0_AWCACHE; + wire [5:0]S_AXI_GP0_AWID; + wire [3:0]S_AXI_GP0_AWLEN; + wire [1:0]S_AXI_GP0_AWLOCK; + wire [2:0]S_AXI_GP0_AWPROT; + wire [3:0]S_AXI_GP0_AWQOS; + wire S_AXI_GP0_AWREADY; + wire [2:0]S_AXI_GP0_AWSIZE; + wire S_AXI_GP0_AWVALID; + wire [5:0]S_AXI_GP0_BID; + wire S_AXI_GP0_BREADY; + wire [1:0]S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire [31:0]S_AXI_GP0_RDATA; + wire [5:0]S_AXI_GP0_RID; + wire S_AXI_GP0_RLAST; + wire S_AXI_GP0_RREADY; + wire [1:0]S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire [31:0]S_AXI_GP0_WDATA; + wire [5:0]S_AXI_GP0_WID; + wire S_AXI_GP0_WLAST; + wire S_AXI_GP0_WREADY; + wire [3:0]S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP1_ACLK; + wire [31:0]S_AXI_GP1_ARADDR; + wire [1:0]S_AXI_GP1_ARBURST; + wire [3:0]S_AXI_GP1_ARCACHE; + wire S_AXI_GP1_ARESETN; + wire [5:0]S_AXI_GP1_ARID; + wire [3:0]S_AXI_GP1_ARLEN; + wire [1:0]S_AXI_GP1_ARLOCK; + wire [2:0]S_AXI_GP1_ARPROT; + wire [3:0]S_AXI_GP1_ARQOS; + wire S_AXI_GP1_ARREADY; + wire [2:0]S_AXI_GP1_ARSIZE; + wire S_AXI_GP1_ARVALID; + wire [31:0]S_AXI_GP1_AWADDR; + wire [1:0]S_AXI_GP1_AWBURST; + wire [3:0]S_AXI_GP1_AWCACHE; + wire [5:0]S_AXI_GP1_AWID; + wire [3:0]S_AXI_GP1_AWLEN; + wire [1:0]S_AXI_GP1_AWLOCK; + wire [2:0]S_AXI_GP1_AWPROT; + wire [3:0]S_AXI_GP1_AWQOS; + wire S_AXI_GP1_AWREADY; + wire [2:0]S_AXI_GP1_AWSIZE; + wire S_AXI_GP1_AWVALID; + wire [5:0]S_AXI_GP1_BID; + wire S_AXI_GP1_BREADY; + wire [1:0]S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire [31:0]S_AXI_GP1_RDATA; + wire [5:0]S_AXI_GP1_RID; + wire S_AXI_GP1_RLAST; + wire S_AXI_GP1_RREADY; + wire [1:0]S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire [31:0]S_AXI_GP1_WDATA; + wire [5:0]S_AXI_GP1_WID; + wire S_AXI_GP1_WLAST; + wire S_AXI_GP1_WREADY; + wire [3:0]S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_HP0_ACLK; + wire [31:0]S_AXI_HP0_ARADDR; + wire [1:0]S_AXI_HP0_ARBURST; + wire [3:0]S_AXI_HP0_ARCACHE; + wire S_AXI_HP0_ARESETN; + wire [5:0]S_AXI_HP0_ARID; + wire [3:0]S_AXI_HP0_ARLEN; + wire [1:0]S_AXI_HP0_ARLOCK; + wire [2:0]S_AXI_HP0_ARPROT; + wire [3:0]S_AXI_HP0_ARQOS; + wire S_AXI_HP0_ARREADY; + wire [2:0]S_AXI_HP0_ARSIZE; + wire S_AXI_HP0_ARVALID; + wire [31:0]S_AXI_HP0_AWADDR; + wire [1:0]S_AXI_HP0_AWBURST; + wire [3:0]S_AXI_HP0_AWCACHE; + wire [5:0]S_AXI_HP0_AWID; + wire [3:0]S_AXI_HP0_AWLEN; + wire [1:0]S_AXI_HP0_AWLOCK; + wire [2:0]S_AXI_HP0_AWPROT; + wire [3:0]S_AXI_HP0_AWQOS; + wire S_AXI_HP0_AWREADY; + wire [2:0]S_AXI_HP0_AWSIZE; + wire S_AXI_HP0_AWVALID; + wire [5:0]S_AXI_HP0_BID; + wire S_AXI_HP0_BREADY; + wire [1:0]S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire [2:0]S_AXI_HP0_RACOUNT; + wire [7:0]S_AXI_HP0_RCOUNT; + wire [63:0]S_AXI_HP0_RDATA; + wire S_AXI_HP0_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP0_RID; + wire S_AXI_HP0_RLAST; + wire S_AXI_HP0_RREADY; + wire [1:0]S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire [5:0]S_AXI_HP0_WACOUNT; + wire [7:0]S_AXI_HP0_WCOUNT; + wire [63:0]S_AXI_HP0_WDATA; + wire [5:0]S_AXI_HP0_WID; + wire S_AXI_HP0_WLAST; + wire S_AXI_HP0_WREADY; + wire S_AXI_HP0_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP1_ACLK; + wire [31:0]S_AXI_HP1_ARADDR; + wire [1:0]S_AXI_HP1_ARBURST; + wire [3:0]S_AXI_HP1_ARCACHE; + wire S_AXI_HP1_ARESETN; + wire [5:0]S_AXI_HP1_ARID; + wire [3:0]S_AXI_HP1_ARLEN; + wire [1:0]S_AXI_HP1_ARLOCK; + wire [2:0]S_AXI_HP1_ARPROT; + wire [3:0]S_AXI_HP1_ARQOS; + wire S_AXI_HP1_ARREADY; + wire [2:0]S_AXI_HP1_ARSIZE; + wire S_AXI_HP1_ARVALID; + wire [31:0]S_AXI_HP1_AWADDR; + wire [1:0]S_AXI_HP1_AWBURST; + wire [3:0]S_AXI_HP1_AWCACHE; + wire [5:0]S_AXI_HP1_AWID; + wire [3:0]S_AXI_HP1_AWLEN; + wire [1:0]S_AXI_HP1_AWLOCK; + wire [2:0]S_AXI_HP1_AWPROT; + wire [3:0]S_AXI_HP1_AWQOS; + wire S_AXI_HP1_AWREADY; + wire [2:0]S_AXI_HP1_AWSIZE; + wire S_AXI_HP1_AWVALID; + wire [5:0]S_AXI_HP1_BID; + wire S_AXI_HP1_BREADY; + wire [1:0]S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire [2:0]S_AXI_HP1_RACOUNT; + wire [7:0]S_AXI_HP1_RCOUNT; + wire [63:0]S_AXI_HP1_RDATA; + wire S_AXI_HP1_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP1_RID; + wire S_AXI_HP1_RLAST; + wire S_AXI_HP1_RREADY; + wire [1:0]S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire [5:0]S_AXI_HP1_WACOUNT; + wire [7:0]S_AXI_HP1_WCOUNT; + wire [63:0]S_AXI_HP1_WDATA; + wire [5:0]S_AXI_HP1_WID; + wire S_AXI_HP1_WLAST; + wire S_AXI_HP1_WREADY; + wire S_AXI_HP1_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP2_ACLK; + wire [31:0]S_AXI_HP2_ARADDR; + wire [1:0]S_AXI_HP2_ARBURST; + wire [3:0]S_AXI_HP2_ARCACHE; + wire S_AXI_HP2_ARESETN; + wire [5:0]S_AXI_HP2_ARID; + wire [3:0]S_AXI_HP2_ARLEN; + wire [1:0]S_AXI_HP2_ARLOCK; + wire [2:0]S_AXI_HP2_ARPROT; + wire [3:0]S_AXI_HP2_ARQOS; + wire S_AXI_HP2_ARREADY; + wire [2:0]S_AXI_HP2_ARSIZE; + wire S_AXI_HP2_ARVALID; + wire [31:0]S_AXI_HP2_AWADDR; + wire [1:0]S_AXI_HP2_AWBURST; + wire [3:0]S_AXI_HP2_AWCACHE; + wire [5:0]S_AXI_HP2_AWID; + wire [3:0]S_AXI_HP2_AWLEN; + wire [1:0]S_AXI_HP2_AWLOCK; + wire [2:0]S_AXI_HP2_AWPROT; + wire [3:0]S_AXI_HP2_AWQOS; + wire S_AXI_HP2_AWREADY; + wire [2:0]S_AXI_HP2_AWSIZE; + wire S_AXI_HP2_AWVALID; + wire [5:0]S_AXI_HP2_BID; + wire S_AXI_HP2_BREADY; + wire [1:0]S_AXI_HP2_BRESP; + wire S_AXI_HP2_BVALID; + wire [2:0]S_AXI_HP2_RACOUNT; + wire [7:0]S_AXI_HP2_RCOUNT; + wire [63:0]S_AXI_HP2_RDATA; + wire S_AXI_HP2_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP2_RID; + wire S_AXI_HP2_RLAST; + wire S_AXI_HP2_RREADY; + wire [1:0]S_AXI_HP2_RRESP; + wire S_AXI_HP2_RVALID; + wire [5:0]S_AXI_HP2_WACOUNT; + wire [7:0]S_AXI_HP2_WCOUNT; + wire [63:0]S_AXI_HP2_WDATA; + wire [5:0]S_AXI_HP2_WID; + wire S_AXI_HP2_WLAST; + wire S_AXI_HP2_WREADY; + wire S_AXI_HP2_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP2_WSTRB; + wire S_AXI_HP2_WVALID; + wire S_AXI_HP3_ACLK; + wire [31:0]S_AXI_HP3_ARADDR; + wire [1:0]S_AXI_HP3_ARBURST; + wire [3:0]S_AXI_HP3_ARCACHE; + wire S_AXI_HP3_ARESETN; + wire [5:0]S_AXI_HP3_ARID; + wire [3:0]S_AXI_HP3_ARLEN; + wire [1:0]S_AXI_HP3_ARLOCK; + wire [2:0]S_AXI_HP3_ARPROT; + wire [3:0]S_AXI_HP3_ARQOS; + wire S_AXI_HP3_ARREADY; + wire [2:0]S_AXI_HP3_ARSIZE; + wire S_AXI_HP3_ARVALID; + wire [31:0]S_AXI_HP3_AWADDR; + wire [1:0]S_AXI_HP3_AWBURST; + wire [3:0]S_AXI_HP3_AWCACHE; + wire [5:0]S_AXI_HP3_AWID; + wire [3:0]S_AXI_HP3_AWLEN; + wire [1:0]S_AXI_HP3_AWLOCK; + wire [2:0]S_AXI_HP3_AWPROT; + wire [3:0]S_AXI_HP3_AWQOS; + wire S_AXI_HP3_AWREADY; + wire [2:0]S_AXI_HP3_AWSIZE; + wire S_AXI_HP3_AWVALID; + wire [5:0]S_AXI_HP3_BID; + wire S_AXI_HP3_BREADY; + wire [1:0]S_AXI_HP3_BRESP; + wire S_AXI_HP3_BVALID; + wire [2:0]S_AXI_HP3_RACOUNT; + wire [7:0]S_AXI_HP3_RCOUNT; + wire [63:0]S_AXI_HP3_RDATA; + wire S_AXI_HP3_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP3_RID; + wire S_AXI_HP3_RLAST; + wire S_AXI_HP3_RREADY; + wire [1:0]S_AXI_HP3_RRESP; + wire S_AXI_HP3_RVALID; + wire [5:0]S_AXI_HP3_WACOUNT; + wire [7:0]S_AXI_HP3_WCOUNT; + wire [63:0]S_AXI_HP3_WDATA; + wire [5:0]S_AXI_HP3_WID; + wire S_AXI_HP3_WLAST; + wire S_AXI_HP3_WREADY; + wire S_AXI_HP3_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP3_WSTRB; + wire S_AXI_HP3_WVALID; + wire TRACE_CLK; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ; + wire TTC0_CLK0_IN; + wire TTC0_CLK1_IN; + wire TTC0_CLK2_IN; + wire TTC0_WAVE0_OUT; + wire TTC0_WAVE1_OUT; + wire TTC0_WAVE2_OUT; + wire TTC1_CLK0_IN; + wire TTC1_CLK1_IN; + wire TTC1_CLK2_IN; + wire TTC1_WAVE0_OUT; + wire TTC1_WAVE1_OUT; + wire TTC1_WAVE2_OUT; + wire UART0_CTSN; + wire UART0_DCDN; + wire UART0_DSRN; + wire UART0_DTRN; + wire UART0_RIN; + wire UART0_RTSN; + wire UART0_RX; + wire UART0_TX; + wire UART1_CTSN; + wire UART1_DCDN; + wire UART1_DSRN; + wire UART1_DTRN; + wire UART1_RIN; + wire UART1_RTSN; + wire UART1_RX; + wire UART1_TX; + wire [1:0]USB0_PORT_INDCTL; + wire USB0_VBUS_PWRFAULT; + wire USB0_VBUS_PWRSELECT; + wire [1:0]USB1_PORT_INDCTL; + wire USB1_VBUS_PWRFAULT; + wire USB1_VBUS_PWRSELECT; + wire WDT_CLK_IN; + wire WDT_RST_OUT; + wire [14:0]buffered_DDR_Addr; + wire [2:0]buffered_DDR_BankAddr; + wire buffered_DDR_CAS_n; + wire buffered_DDR_CKE; + wire buffered_DDR_CS_n; + wire buffered_DDR_Clk; + wire buffered_DDR_Clk_n; + wire [1:0]buffered_DDR_DM; + wire [15:0]buffered_DDR_DQ; + wire [1:0]buffered_DDR_DQS; + wire [1:0]buffered_DDR_DQS_n; + wire buffered_DDR_DRSTB; + wire buffered_DDR_ODT; + wire buffered_DDR_RAS_n; + wire buffered_DDR_VRN; + wire buffered_DDR_VRP; + wire buffered_DDR_WEB; + wire [31:0]buffered_MIO; + wire buffered_PS_CLK; + wire buffered_PS_PORB; + wire buffered_PS_SRSTB; + wire [63:0]gpio_out_t_n; + wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED; + wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED; + wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED; + wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED; + wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED; + wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED; + wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED; + wire [3:2]NLW_PS7_i_DDRDM_UNCONNECTED; + wire [31:16]NLW_PS7_i_DDRDQ_UNCONNECTED; + wire [3:2]NLW_PS7_i_DDRDQSN_UNCONNECTED; + wire [3:2]NLW_PS7_i_DDRDQSP_UNCONNECTED; + wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED; + wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED; + wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED; + wire [51:16]NLW_PS7_i_MIO_UNCONNECTED; + + assign ENET0_GMII_TXD[7] = \ ; + assign ENET0_GMII_TXD[6] = \ ; + assign ENET0_GMII_TXD[5] = \ ; + assign ENET0_GMII_TXD[4] = \ ; + assign ENET0_GMII_TXD[3] = \ ; + assign ENET0_GMII_TXD[2] = \ ; + assign ENET0_GMII_TXD[1] = \ ; + assign ENET0_GMII_TXD[0] = \ ; + assign ENET0_GMII_TX_EN = \ ; + assign ENET0_GMII_TX_ER = \ ; + assign ENET1_GMII_TXD[7] = \ ; + assign ENET1_GMII_TXD[6] = \ ; + assign ENET1_GMII_TXD[5] = \ ; + assign ENET1_GMII_TXD[4] = \ ; + assign ENET1_GMII_TXD[3] = \ ; + assign ENET1_GMII_TXD[2] = \ ; + assign ENET1_GMII_TXD[1] = \ ; + assign ENET1_GMII_TXD[0] = \ ; + assign ENET1_GMII_TX_EN = \ ; + assign ENET1_GMII_TX_ER = \ ; + assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2]; + assign M_AXI_GP0_ARCACHE[1] = \ ; + assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0]; + assign M_AXI_GP0_ARSIZE[2] = \ ; + assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0]; + assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2]; + assign M_AXI_GP0_AWCACHE[1] = \ ; + assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0]; + assign M_AXI_GP0_AWSIZE[2] = \ ; + assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0]; + assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2]; + assign M_AXI_GP1_ARCACHE[1] = \ ; + assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0]; + assign M_AXI_GP1_ARSIZE[2] = \ ; + assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0]; + assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2]; + assign M_AXI_GP1_AWCACHE[1] = \ ; + assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0]; + assign M_AXI_GP1_AWSIZE[2] = \ ; + assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0]; + assign PJTAG_TDO = \ ; + assign TRACE_CLK_OUT = \ ; + assign TRACE_CTL = \TRACE_CTL_PIPE[0] ; + assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ; + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CAS_n_BIBUF + (.IO(buffered_DDR_CAS_n), + .PAD(DDR_CAS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CKE_BIBUF + (.IO(buffered_DDR_CKE), + .PAD(DDR_CKE)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CS_n_BIBUF + (.IO(buffered_DDR_CS_n), + .PAD(DDR_CS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_Clk_BIBUF + (.IO(buffered_DDR_Clk), + .PAD(DDR_Clk)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_Clk_n_BIBUF + (.IO(buffered_DDR_Clk_n), + .PAD(DDR_Clk_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_DRSTB_BIBUF + (.IO(buffered_DDR_DRSTB), + .PAD(DDR_DRSTB)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_ODT_BIBUF + (.IO(buffered_DDR_ODT), + .PAD(DDR_ODT)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_RAS_n_BIBUF + (.IO(buffered_DDR_RAS_n), + .PAD(DDR_RAS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_VRN_BIBUF + (.IO(buffered_DDR_VRN), + .PAD(DDR_VRN)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_VRP_BIBUF + (.IO(buffered_DDR_VRP), + .PAD(DDR_VRP)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_WEB_BIBUF + (.IO(buffered_DDR_WEB), + .PAD(DDR_WEB)); + LUT1 #( + .INIT(2'h1)) + ENET0_MDIO_T_INST_0 + (.I0(ENET0_MDIO_T_n), + .O(ENET0_MDIO_T)); + LUT1 #( + .INIT(2'h1)) + ENET1_MDIO_T_INST_0 + (.I0(ENET1_MDIO_T_n), + .O(ENET1_MDIO_T)); + GND GND + (.G(\ )); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[0]_INST_0 + (.I0(gpio_out_t_n[0]), + .O(GPIO_T[0])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[10]_INST_0 + (.I0(gpio_out_t_n[10]), + .O(GPIO_T[10])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[11]_INST_0 + (.I0(gpio_out_t_n[11]), + .O(GPIO_T[11])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[12]_INST_0 + (.I0(gpio_out_t_n[12]), + .O(GPIO_T[12])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[13]_INST_0 + (.I0(gpio_out_t_n[13]), + .O(GPIO_T[13])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[14]_INST_0 + (.I0(gpio_out_t_n[14]), + .O(GPIO_T[14])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[15]_INST_0 + (.I0(gpio_out_t_n[15]), + .O(GPIO_T[15])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[16]_INST_0 + (.I0(gpio_out_t_n[16]), + .O(GPIO_T[16])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[17]_INST_0 + (.I0(gpio_out_t_n[17]), + .O(GPIO_T[17])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[18]_INST_0 + (.I0(gpio_out_t_n[18]), + .O(GPIO_T[18])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[19]_INST_0 + (.I0(gpio_out_t_n[19]), + .O(GPIO_T[19])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[1]_INST_0 + (.I0(gpio_out_t_n[1]), + .O(GPIO_T[1])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[20]_INST_0 + (.I0(gpio_out_t_n[20]), + .O(GPIO_T[20])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[21]_INST_0 + (.I0(gpio_out_t_n[21]), + .O(GPIO_T[21])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[22]_INST_0 + (.I0(gpio_out_t_n[22]), + .O(GPIO_T[22])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[23]_INST_0 + (.I0(gpio_out_t_n[23]), + .O(GPIO_T[23])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[24]_INST_0 + (.I0(gpio_out_t_n[24]), + .O(GPIO_T[24])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[25]_INST_0 + (.I0(gpio_out_t_n[25]), + .O(GPIO_T[25])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[26]_INST_0 + (.I0(gpio_out_t_n[26]), + .O(GPIO_T[26])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[27]_INST_0 + (.I0(gpio_out_t_n[27]), + .O(GPIO_T[27])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[28]_INST_0 + (.I0(gpio_out_t_n[28]), + .O(GPIO_T[28])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[29]_INST_0 + (.I0(gpio_out_t_n[29]), + .O(GPIO_T[29])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[2]_INST_0 + (.I0(gpio_out_t_n[2]), + .O(GPIO_T[2])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[30]_INST_0 + (.I0(gpio_out_t_n[30]), + .O(GPIO_T[30])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[31]_INST_0 + (.I0(gpio_out_t_n[31]), + .O(GPIO_T[31])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[32]_INST_0 + (.I0(gpio_out_t_n[32]), + .O(GPIO_T[32])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[33]_INST_0 + (.I0(gpio_out_t_n[33]), + .O(GPIO_T[33])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[34]_INST_0 + (.I0(gpio_out_t_n[34]), + .O(GPIO_T[34])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[35]_INST_0 + (.I0(gpio_out_t_n[35]), + .O(GPIO_T[35])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[36]_INST_0 + (.I0(gpio_out_t_n[36]), + .O(GPIO_T[36])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[37]_INST_0 + (.I0(gpio_out_t_n[37]), + .O(GPIO_T[37])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[38]_INST_0 + (.I0(gpio_out_t_n[38]), + .O(GPIO_T[38])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[39]_INST_0 + (.I0(gpio_out_t_n[39]), + .O(GPIO_T[39])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[3]_INST_0 + (.I0(gpio_out_t_n[3]), + .O(GPIO_T[3])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[40]_INST_0 + (.I0(gpio_out_t_n[40]), + .O(GPIO_T[40])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[41]_INST_0 + (.I0(gpio_out_t_n[41]), + .O(GPIO_T[41])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[42]_INST_0 + (.I0(gpio_out_t_n[42]), + .O(GPIO_T[42])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[43]_INST_0 + (.I0(gpio_out_t_n[43]), + .O(GPIO_T[43])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[44]_INST_0 + (.I0(gpio_out_t_n[44]), + .O(GPIO_T[44])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[45]_INST_0 + (.I0(gpio_out_t_n[45]), + .O(GPIO_T[45])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[46]_INST_0 + (.I0(gpio_out_t_n[46]), + .O(GPIO_T[46])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[47]_INST_0 + (.I0(gpio_out_t_n[47]), + .O(GPIO_T[47])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[48]_INST_0 + (.I0(gpio_out_t_n[48]), + .O(GPIO_T[48])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[49]_INST_0 + (.I0(gpio_out_t_n[49]), + .O(GPIO_T[49])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[4]_INST_0 + (.I0(gpio_out_t_n[4]), + .O(GPIO_T[4])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[50]_INST_0 + (.I0(gpio_out_t_n[50]), + .O(GPIO_T[50])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[51]_INST_0 + (.I0(gpio_out_t_n[51]), + .O(GPIO_T[51])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[52]_INST_0 + (.I0(gpio_out_t_n[52]), + .O(GPIO_T[52])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[53]_INST_0 + (.I0(gpio_out_t_n[53]), + .O(GPIO_T[53])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[54]_INST_0 + (.I0(gpio_out_t_n[54]), + .O(GPIO_T[54])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[55]_INST_0 + (.I0(gpio_out_t_n[55]), + .O(GPIO_T[55])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[56]_INST_0 + (.I0(gpio_out_t_n[56]), + .O(GPIO_T[56])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[57]_INST_0 + (.I0(gpio_out_t_n[57]), + .O(GPIO_T[57])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[58]_INST_0 + (.I0(gpio_out_t_n[58]), + .O(GPIO_T[58])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[59]_INST_0 + (.I0(gpio_out_t_n[59]), + .O(GPIO_T[59])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[5]_INST_0 + (.I0(gpio_out_t_n[5]), + .O(GPIO_T[5])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[60]_INST_0 + (.I0(gpio_out_t_n[60]), + .O(GPIO_T[60])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[61]_INST_0 + (.I0(gpio_out_t_n[61]), + .O(GPIO_T[61])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[62]_INST_0 + (.I0(gpio_out_t_n[62]), + .O(GPIO_T[62])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[63]_INST_0 + (.I0(gpio_out_t_n[63]), + .O(GPIO_T[63])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[6]_INST_0 + (.I0(gpio_out_t_n[6]), + .O(GPIO_T[6])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[7]_INST_0 + (.I0(gpio_out_t_n[7]), + .O(GPIO_T[7])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[8]_INST_0 + (.I0(gpio_out_t_n[8]), + .O(GPIO_T[8])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[9]_INST_0 + (.I0(gpio_out_t_n[9]), + .O(GPIO_T[9])); + LUT1 #( + .INIT(2'h1)) + I2C0_SCL_T_INST_0 + (.I0(I2C0_SCL_T_n), + .O(I2C0_SCL_T)); + LUT1 #( + .INIT(2'h1)) + I2C0_SDA_T_INST_0 + (.I0(I2C0_SDA_T_n), + .O(I2C0_SDA_T)); + LUT1 #( + .INIT(2'h1)) + I2C1_SCL_T_INST_0 + (.I0(I2C1_SCL_T_n), + .O(I2C1_SCL_T)); + LUT1 #( + .INIT(2'h1)) + I2C1_SDA_T_INST_0 + (.I0(I2C1_SDA_T_n), + .O(I2C1_SDA_T)); + (* BOX_TYPE = "PRIMITIVE" *) + PS7 PS7_i + (.DDRA(buffered_DDR_Addr), + .DDRARB(DDR_ARB), + .DDRBA(buffered_DDR_BankAddr), + .DDRCASB(buffered_DDR_CAS_n), + .DDRCKE(buffered_DDR_CKE), + .DDRCKN(buffered_DDR_Clk_n), + .DDRCKP(buffered_DDR_Clk), + .DDRCSB(buffered_DDR_CS_n), + .DDRDM({NLW_PS7_i_DDRDM_UNCONNECTED[3:2],buffered_DDR_DM}), + .DDRDQ({NLW_PS7_i_DDRDQ_UNCONNECTED[31:16],buffered_DDR_DQ}), + .DDRDQSN({NLW_PS7_i_DDRDQSN_UNCONNECTED[3:2],buffered_DDR_DQS_n}), + .DDRDQSP({NLW_PS7_i_DDRDQSP_UNCONNECTED[3:2],buffered_DDR_DQS}), + .DDRDRSTB(buffered_DDR_DRSTB), + .DDRODT(buffered_DDR_ODT), + .DDRRASB(buffered_DDR_RAS_n), + .DDRVRN(buffered_DDR_VRN), + .DDRVRP(buffered_DDR_VRP), + .DDRWEB(buffered_DDR_WEB), + .DMA0ACLK(DMA0_ACLK), + .DMA0DAREADY(DMA0_DAREADY), + .DMA0DATYPE(DMA0_DATYPE), + .DMA0DAVALID(DMA0_DAVALID), + .DMA0DRLAST(DMA0_DRLAST), + .DMA0DRREADY(DMA0_DRREADY), + .DMA0DRTYPE(DMA0_DRTYPE), + .DMA0DRVALID(DMA0_DRVALID), + .DMA0RSTN(DMA0_RSTN), + .DMA1ACLK(DMA1_ACLK), + .DMA1DAREADY(DMA1_DAREADY), + .DMA1DATYPE(DMA1_DATYPE), + .DMA1DAVALID(DMA1_DAVALID), + .DMA1DRLAST(DMA1_DRLAST), + .DMA1DRREADY(DMA1_DRREADY), + .DMA1DRTYPE(DMA1_DRTYPE), + .DMA1DRVALID(DMA1_DRVALID), + .DMA1RSTN(DMA1_RSTN), + .DMA2ACLK(DMA2_ACLK), + .DMA2DAREADY(DMA2_DAREADY), + .DMA2DATYPE(DMA2_DATYPE), + .DMA2DAVALID(DMA2_DAVALID), + .DMA2DRLAST(DMA2_DRLAST), + .DMA2DRREADY(DMA2_DRREADY), + .DMA2DRTYPE(DMA2_DRTYPE), + .DMA2DRVALID(DMA2_DRVALID), + .DMA2RSTN(DMA2_RSTN), + .DMA3ACLK(DMA3_ACLK), + .DMA3DAREADY(DMA3_DAREADY), + .DMA3DATYPE(DMA3_DATYPE), + .DMA3DAVALID(DMA3_DAVALID), + .DMA3DRLAST(DMA3_DRLAST), + .DMA3DRREADY(DMA3_DRREADY), + .DMA3DRTYPE(DMA3_DRTYPE), + .DMA3DRVALID(DMA3_DRVALID), + .DMA3RSTN(DMA3_RSTN), + .EMIOCAN0PHYRX(CAN0_PHY_RX), + .EMIOCAN0PHYTX(CAN0_PHY_TX), + .EMIOCAN1PHYRX(CAN1_PHY_RX), + .EMIOCAN1PHYTX(CAN1_PHY_TX), + .EMIOENET0EXTINTIN(ENET0_EXT_INTIN), + .EMIOENET0GMIICOL(1'b0), + .EMIOENET0GMIICRS(1'b0), + .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK), + .EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOENET0GMIIRXDV(1'b0), + .EMIOENET0GMIIRXER(1'b0), + .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK), + .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]), + .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED), + .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED), + .EMIOENET0MDIOI(ENET0_MDIO_I), + .EMIOENET0MDIOMDC(ENET0_MDIO_MDC), + .EMIOENET0MDIOO(ENET0_MDIO_O), + .EMIOENET0MDIOTN(ENET0_MDIO_T_n), + .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX), + .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX), + .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX), + .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX), + .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), + .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), + .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX), + .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX), + .EMIOENET0SOFRX(ENET0_SOF_RX), + .EMIOENET0SOFTX(ENET0_SOF_TX), + .EMIOENET1EXTINTIN(ENET1_EXT_INTIN), + .EMIOENET1GMIICOL(1'b0), + .EMIOENET1GMIICRS(1'b0), + .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK), + .EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOENET1GMIIRXDV(1'b0), + .EMIOENET1GMIIRXER(1'b0), + .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK), + .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]), + .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED), + .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED), + .EMIOENET1MDIOI(ENET1_MDIO_I), + .EMIOENET1MDIOMDC(ENET1_MDIO_MDC), + .EMIOENET1MDIOO(ENET1_MDIO_O), + .EMIOENET1MDIOTN(ENET1_MDIO_T_n), + .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX), + .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX), + .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX), + .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX), + .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), + .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), + .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX), + .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX), + .EMIOENET1SOFRX(ENET1_SOF_RX), + .EMIOENET1SOFTX(ENET1_SOF_TX), + .EMIOGPIOI(GPIO_I), + .EMIOGPIOO(GPIO_O), + .EMIOGPIOTN(gpio_out_t_n), + .EMIOI2C0SCLI(I2C0_SCL_I), + .EMIOI2C0SCLO(I2C0_SCL_O), + .EMIOI2C0SCLTN(I2C0_SCL_T_n), + .EMIOI2C0SDAI(I2C0_SDA_I), + .EMIOI2C0SDAO(I2C0_SDA_O), + .EMIOI2C0SDATN(I2C0_SDA_T_n), + .EMIOI2C1SCLI(I2C1_SCL_I), + .EMIOI2C1SCLO(I2C1_SCL_O), + .EMIOI2C1SCLTN(I2C1_SCL_T_n), + .EMIOI2C1SDAI(I2C1_SDA_I), + .EMIOI2C1SDAO(I2C1_SDA_O), + .EMIOI2C1SDATN(I2C1_SDA_T_n), + .EMIOPJTAGTCK(PJTAG_TCK), + .EMIOPJTAGTDI(PJTAG_TDI), + .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED), + .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED), + .EMIOPJTAGTMS(PJTAG_TMS), + .EMIOSDIO0BUSPOW(SDIO0_BUSPOW), + .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT), + .EMIOSDIO0CDN(SDIO0_CDN), + .EMIOSDIO0CLK(SDIO0_CLK), + .EMIOSDIO0CLKFB(SDIO0_CLK_FB), + .EMIOSDIO0CMDI(SDIO0_CMD_I), + .EMIOSDIO0CMDO(SDIO0_CMD_O), + .EMIOSDIO0CMDTN(SDIO0_CMD_T_n), + .EMIOSDIO0DATAI(SDIO0_DATA_I), + .EMIOSDIO0DATAO(SDIO0_DATA_O), + .EMIOSDIO0DATATN(SDIO0_DATA_T_n), + .EMIOSDIO0LED(SDIO0_LED), + .EMIOSDIO0WP(SDIO0_WP), + .EMIOSDIO1BUSPOW(SDIO1_BUSPOW), + .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT), + .EMIOSDIO1CDN(SDIO1_CDN), + .EMIOSDIO1CLK(SDIO1_CLK), + .EMIOSDIO1CLKFB(SDIO1_CLK_FB), + .EMIOSDIO1CMDI(SDIO1_CMD_I), + .EMIOSDIO1CMDO(SDIO1_CMD_O), + .EMIOSDIO1CMDTN(SDIO1_CMD_T_n), + .EMIOSDIO1DATAI(SDIO1_DATA_I), + .EMIOSDIO1DATAO(SDIO1_DATA_O), + .EMIOSDIO1DATATN(SDIO1_DATA_T_n), + .EMIOSDIO1LED(SDIO1_LED), + .EMIOSDIO1WP(SDIO1_WP), + .EMIOSPI0MI(SPI0_MISO_I), + .EMIOSPI0MO(SPI0_MOSI_O), + .EMIOSPI0MOTN(SPI0_MOSI_T_n), + .EMIOSPI0SCLKI(SPI0_SCLK_I), + .EMIOSPI0SCLKO(SPI0_SCLK_O), + .EMIOSPI0SCLKTN(SPI0_SCLK_T_n), + .EMIOSPI0SI(SPI0_MOSI_I), + .EMIOSPI0SO(SPI0_MISO_O), + .EMIOSPI0SSIN(SPI0_SS_I), + .EMIOSPI0SSNTN(SPI0_SS_T_n), + .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), + .EMIOSPI0STN(SPI0_MISO_T_n), + .EMIOSPI1MI(SPI1_MISO_I), + .EMIOSPI1MO(SPI1_MOSI_O), + .EMIOSPI1MOTN(SPI1_MOSI_T_n), + .EMIOSPI1SCLKI(SPI1_SCLK_I), + .EMIOSPI1SCLKO(SPI1_SCLK_O), + .EMIOSPI1SCLKTN(SPI1_SCLK_T_n), + .EMIOSPI1SI(SPI1_MOSI_I), + .EMIOSPI1SO(SPI1_MISO_O), + .EMIOSPI1SSIN(SPI1_SS_I), + .EMIOSPI1SSNTN(SPI1_SS_T_n), + .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), + .EMIOSPI1STN(SPI1_MISO_T_n), + .EMIOSRAMINTIN(SRAM_INTIN), + .EMIOTRACECLK(TRACE_CLK), + .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED), + .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]), + .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}), + .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), + .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}), + .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), + .EMIOUART0CTSN(UART0_CTSN), + .EMIOUART0DCDN(UART0_DCDN), + .EMIOUART0DSRN(UART0_DSRN), + .EMIOUART0DTRN(UART0_DTRN), + .EMIOUART0RIN(UART0_RIN), + .EMIOUART0RTSN(UART0_RTSN), + .EMIOUART0RX(UART0_RX), + .EMIOUART0TX(UART0_TX), + .EMIOUART1CTSN(UART1_CTSN), + .EMIOUART1DCDN(UART1_DCDN), + .EMIOUART1DSRN(UART1_DSRN), + .EMIOUART1DTRN(UART1_DTRN), + .EMIOUART1RIN(UART1_RIN), + .EMIOUART1RTSN(UART1_RTSN), + .EMIOUART1RX(UART1_RX), + .EMIOUART1TX(UART1_TX), + .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL), + .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT), + .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT), + .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL), + .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT), + .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT), + .EMIOWDTCLKI(WDT_CLK_IN), + .EMIOWDTRSTO(WDT_RST_OUT), + .EVENTEVENTI(EVENT_EVENTI), + .EVENTEVENTO(EVENT_EVENTO), + .EVENTSTANDBYWFE(EVENT_STANDBYWFE), + .EVENTSTANDBYWFI(EVENT_STANDBYWFI), + .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK_unbuffered}), + .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}), + .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), + .FPGAIDLEN(FPGA_IDLE_N), + .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}), + .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK), + .FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMDTRACEINVALID(1'b0), + .FTMTF2PDEBUG(FTMT_F2P_DEBUG), + .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), + .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), + .FTMTP2FDEBUG(FTMT_P2F_DEBUG), + .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), + .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), + .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}), + .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}), + .MAXIGP0ACLK(M_AXI_GP0_ACLK), + .MAXIGP0ARADDR(M_AXI_GP0_ARADDR), + .MAXIGP0ARBURST(M_AXI_GP0_ARBURST), + .MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ), + .MAXIGP0ARESETN(M_AXI_GP0_ARESETN), + .MAXIGP0ARID(M_AXI_GP0_ARID), + .MAXIGP0ARLEN(M_AXI_GP0_ARLEN), + .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK), + .MAXIGP0ARPROT(M_AXI_GP0_ARPROT), + .MAXIGP0ARQOS(M_AXI_GP0_ARQOS), + .MAXIGP0ARREADY(M_AXI_GP0_ARREADY), + .MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ), + .MAXIGP0ARVALID(M_AXI_GP0_ARVALID), + .MAXIGP0AWADDR(M_AXI_GP0_AWADDR), + .MAXIGP0AWBURST(M_AXI_GP0_AWBURST), + .MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ), + .MAXIGP0AWID(M_AXI_GP0_AWID), + .MAXIGP0AWLEN(M_AXI_GP0_AWLEN), + .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK), + .MAXIGP0AWPROT(M_AXI_GP0_AWPROT), + .MAXIGP0AWQOS(M_AXI_GP0_AWQOS), + .MAXIGP0AWREADY(M_AXI_GP0_AWREADY), + .MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ), + .MAXIGP0AWVALID(M_AXI_GP0_AWVALID), + .MAXIGP0BID(M_AXI_GP0_BID), + .MAXIGP0BREADY(M_AXI_GP0_BREADY), + .MAXIGP0BRESP(M_AXI_GP0_BRESP), + .MAXIGP0BVALID(M_AXI_GP0_BVALID), + .MAXIGP0RDATA(M_AXI_GP0_RDATA), + .MAXIGP0RID(M_AXI_GP0_RID), + .MAXIGP0RLAST(M_AXI_GP0_RLAST), + .MAXIGP0RREADY(M_AXI_GP0_RREADY), + .MAXIGP0RRESP(M_AXI_GP0_RRESP), + .MAXIGP0RVALID(M_AXI_GP0_RVALID), + .MAXIGP0WDATA(M_AXI_GP0_WDATA), + .MAXIGP0WID(M_AXI_GP0_WID), + .MAXIGP0WLAST(M_AXI_GP0_WLAST), + .MAXIGP0WREADY(M_AXI_GP0_WREADY), + .MAXIGP0WSTRB(M_AXI_GP0_WSTRB), + .MAXIGP0WVALID(M_AXI_GP0_WVALID), + .MAXIGP1ACLK(M_AXI_GP1_ACLK), + .MAXIGP1ARADDR(M_AXI_GP1_ARADDR), + .MAXIGP1ARBURST(M_AXI_GP1_ARBURST), + .MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ), + .MAXIGP1ARESETN(M_AXI_GP1_ARESETN), + .MAXIGP1ARID(M_AXI_GP1_ARID), + .MAXIGP1ARLEN(M_AXI_GP1_ARLEN), + .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK), + .MAXIGP1ARPROT(M_AXI_GP1_ARPROT), + .MAXIGP1ARQOS(M_AXI_GP1_ARQOS), + .MAXIGP1ARREADY(M_AXI_GP1_ARREADY), + .MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ), + .MAXIGP1ARVALID(M_AXI_GP1_ARVALID), + .MAXIGP1AWADDR(M_AXI_GP1_AWADDR), + .MAXIGP1AWBURST(M_AXI_GP1_AWBURST), + .MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ), + .MAXIGP1AWID(M_AXI_GP1_AWID), + .MAXIGP1AWLEN(M_AXI_GP1_AWLEN), + .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK), + .MAXIGP1AWPROT(M_AXI_GP1_AWPROT), + .MAXIGP1AWQOS(M_AXI_GP1_AWQOS), + .MAXIGP1AWREADY(M_AXI_GP1_AWREADY), + .MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ), + .MAXIGP1AWVALID(M_AXI_GP1_AWVALID), + .MAXIGP1BID(M_AXI_GP1_BID), + .MAXIGP1BREADY(M_AXI_GP1_BREADY), + .MAXIGP1BRESP(M_AXI_GP1_BRESP), + .MAXIGP1BVALID(M_AXI_GP1_BVALID), + .MAXIGP1RDATA(M_AXI_GP1_RDATA), + .MAXIGP1RID(M_AXI_GP1_RID), + .MAXIGP1RLAST(M_AXI_GP1_RLAST), + .MAXIGP1RREADY(M_AXI_GP1_RREADY), + .MAXIGP1RRESP(M_AXI_GP1_RRESP), + .MAXIGP1RVALID(M_AXI_GP1_RVALID), + .MAXIGP1WDATA(M_AXI_GP1_WDATA), + .MAXIGP1WID(M_AXI_GP1_WID), + .MAXIGP1WLAST(M_AXI_GP1_WLAST), + .MAXIGP1WREADY(M_AXI_GP1_WREADY), + .MAXIGP1WSTRB(M_AXI_GP1_WSTRB), + .MAXIGP1WVALID(M_AXI_GP1_WVALID), + .MIO({buffered_MIO[31:30],NLW_PS7_i_MIO_UNCONNECTED[51:50],buffered_MIO[29:28],NLW_PS7_i_MIO_UNCONNECTED[47:40],buffered_MIO[27:16],NLW_PS7_i_MIO_UNCONNECTED[27:16],buffered_MIO[15:0]}), + .PSCLK(buffered_PS_CLK), + .PSPORB(buffered_PS_PORB), + .PSSRSTB(buffered_PS_SRSTB), + .SAXIACPACLK(S_AXI_ACP_ACLK), + .SAXIACPARADDR(S_AXI_ACP_ARADDR), + .SAXIACPARBURST(S_AXI_ACP_ARBURST), + .SAXIACPARCACHE(S_AXI_ACP_ARCACHE), + .SAXIACPARESETN(S_AXI_ACP_ARESETN), + .SAXIACPARID(S_AXI_ACP_ARID), + .SAXIACPARLEN(S_AXI_ACP_ARLEN), + .SAXIACPARLOCK(S_AXI_ACP_ARLOCK), + .SAXIACPARPROT(S_AXI_ACP_ARPROT), + .SAXIACPARQOS(S_AXI_ACP_ARQOS), + .SAXIACPARREADY(S_AXI_ACP_ARREADY), + .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]), + .SAXIACPARUSER(S_AXI_ACP_ARUSER), + .SAXIACPARVALID(S_AXI_ACP_ARVALID), + .SAXIACPAWADDR(S_AXI_ACP_AWADDR), + .SAXIACPAWBURST(S_AXI_ACP_AWBURST), + .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE), + .SAXIACPAWID(S_AXI_ACP_AWID), + .SAXIACPAWLEN(S_AXI_ACP_AWLEN), + .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK), + .SAXIACPAWPROT(S_AXI_ACP_AWPROT), + .SAXIACPAWQOS(S_AXI_ACP_AWQOS), + .SAXIACPAWREADY(S_AXI_ACP_AWREADY), + .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]), + .SAXIACPAWUSER(S_AXI_ACP_AWUSER), + .SAXIACPAWVALID(S_AXI_ACP_AWVALID), + .SAXIACPBID(S_AXI_ACP_BID), + .SAXIACPBREADY(S_AXI_ACP_BREADY), + .SAXIACPBRESP(S_AXI_ACP_BRESP), + .SAXIACPBVALID(S_AXI_ACP_BVALID), + .SAXIACPRDATA(S_AXI_ACP_RDATA), + .SAXIACPRID(S_AXI_ACP_RID), + .SAXIACPRLAST(S_AXI_ACP_RLAST), + .SAXIACPRREADY(S_AXI_ACP_RREADY), + .SAXIACPRRESP(S_AXI_ACP_RRESP), + .SAXIACPRVALID(S_AXI_ACP_RVALID), + .SAXIACPWDATA(S_AXI_ACP_WDATA), + .SAXIACPWID(S_AXI_ACP_WID), + .SAXIACPWLAST(S_AXI_ACP_WLAST), + .SAXIACPWREADY(S_AXI_ACP_WREADY), + .SAXIACPWSTRB(S_AXI_ACP_WSTRB), + .SAXIACPWVALID(S_AXI_ACP_WVALID), + .SAXIGP0ACLK(S_AXI_GP0_ACLK), + .SAXIGP0ARADDR(S_AXI_GP0_ARADDR), + .SAXIGP0ARBURST(S_AXI_GP0_ARBURST), + .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE), + .SAXIGP0ARESETN(S_AXI_GP0_ARESETN), + .SAXIGP0ARID(S_AXI_GP0_ARID), + .SAXIGP0ARLEN(S_AXI_GP0_ARLEN), + .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK), + .SAXIGP0ARPROT(S_AXI_GP0_ARPROT), + .SAXIGP0ARQOS(S_AXI_GP0_ARQOS), + .SAXIGP0ARREADY(S_AXI_GP0_ARREADY), + .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]), + .SAXIGP0ARVALID(S_AXI_GP0_ARVALID), + .SAXIGP0AWADDR(S_AXI_GP0_AWADDR), + .SAXIGP0AWBURST(S_AXI_GP0_AWBURST), + .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE), + .SAXIGP0AWID(S_AXI_GP0_AWID), + .SAXIGP0AWLEN(S_AXI_GP0_AWLEN), + .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK), + .SAXIGP0AWPROT(S_AXI_GP0_AWPROT), + .SAXIGP0AWQOS(S_AXI_GP0_AWQOS), + .SAXIGP0AWREADY(S_AXI_GP0_AWREADY), + .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]), + .SAXIGP0AWVALID(S_AXI_GP0_AWVALID), + .SAXIGP0BID(S_AXI_GP0_BID), + .SAXIGP0BREADY(S_AXI_GP0_BREADY), + .SAXIGP0BRESP(S_AXI_GP0_BRESP), + .SAXIGP0BVALID(S_AXI_GP0_BVALID), + .SAXIGP0RDATA(S_AXI_GP0_RDATA), + .SAXIGP0RID(S_AXI_GP0_RID), + .SAXIGP0RLAST(S_AXI_GP0_RLAST), + .SAXIGP0RREADY(S_AXI_GP0_RREADY), + .SAXIGP0RRESP(S_AXI_GP0_RRESP), + .SAXIGP0RVALID(S_AXI_GP0_RVALID), + .SAXIGP0WDATA(S_AXI_GP0_WDATA), + .SAXIGP0WID(S_AXI_GP0_WID), + .SAXIGP0WLAST(S_AXI_GP0_WLAST), + .SAXIGP0WREADY(S_AXI_GP0_WREADY), + .SAXIGP0WSTRB(S_AXI_GP0_WSTRB), + .SAXIGP0WVALID(S_AXI_GP0_WVALID), + .SAXIGP1ACLK(S_AXI_GP1_ACLK), + .SAXIGP1ARADDR(S_AXI_GP1_ARADDR), + .SAXIGP1ARBURST(S_AXI_GP1_ARBURST), + .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE), + .SAXIGP1ARESETN(S_AXI_GP1_ARESETN), + .SAXIGP1ARID(S_AXI_GP1_ARID), + .SAXIGP1ARLEN(S_AXI_GP1_ARLEN), + .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK), + .SAXIGP1ARPROT(S_AXI_GP1_ARPROT), + .SAXIGP1ARQOS(S_AXI_GP1_ARQOS), + .SAXIGP1ARREADY(S_AXI_GP1_ARREADY), + .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]), + .SAXIGP1ARVALID(S_AXI_GP1_ARVALID), + .SAXIGP1AWADDR(S_AXI_GP1_AWADDR), + .SAXIGP1AWBURST(S_AXI_GP1_AWBURST), + .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE), + .SAXIGP1AWID(S_AXI_GP1_AWID), + .SAXIGP1AWLEN(S_AXI_GP1_AWLEN), + .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK), + .SAXIGP1AWPROT(S_AXI_GP1_AWPROT), + .SAXIGP1AWQOS(S_AXI_GP1_AWQOS), + .SAXIGP1AWREADY(S_AXI_GP1_AWREADY), + .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]), + .SAXIGP1AWVALID(S_AXI_GP1_AWVALID), + .SAXIGP1BID(S_AXI_GP1_BID), + .SAXIGP1BREADY(S_AXI_GP1_BREADY), + .SAXIGP1BRESP(S_AXI_GP1_BRESP), + .SAXIGP1BVALID(S_AXI_GP1_BVALID), + .SAXIGP1RDATA(S_AXI_GP1_RDATA), + .SAXIGP1RID(S_AXI_GP1_RID), + .SAXIGP1RLAST(S_AXI_GP1_RLAST), + .SAXIGP1RREADY(S_AXI_GP1_RREADY), + .SAXIGP1RRESP(S_AXI_GP1_RRESP), + .SAXIGP1RVALID(S_AXI_GP1_RVALID), + .SAXIGP1WDATA(S_AXI_GP1_WDATA), + .SAXIGP1WID(S_AXI_GP1_WID), + .SAXIGP1WLAST(S_AXI_GP1_WLAST), + .SAXIGP1WREADY(S_AXI_GP1_WREADY), + .SAXIGP1WSTRB(S_AXI_GP1_WSTRB), + .SAXIGP1WVALID(S_AXI_GP1_WVALID), + .SAXIHP0ACLK(S_AXI_HP0_ACLK), + .SAXIHP0ARADDR(S_AXI_HP0_ARADDR), + .SAXIHP0ARBURST(S_AXI_HP0_ARBURST), + .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE), + .SAXIHP0ARESETN(S_AXI_HP0_ARESETN), + .SAXIHP0ARID(S_AXI_HP0_ARID), + .SAXIHP0ARLEN(S_AXI_HP0_ARLEN), + .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK), + .SAXIHP0ARPROT(S_AXI_HP0_ARPROT), + .SAXIHP0ARQOS(S_AXI_HP0_ARQOS), + .SAXIHP0ARREADY(S_AXI_HP0_ARREADY), + .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]), + .SAXIHP0ARVALID(S_AXI_HP0_ARVALID), + .SAXIHP0AWADDR(S_AXI_HP0_AWADDR), + .SAXIHP0AWBURST(S_AXI_HP0_AWBURST), + .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE), + .SAXIHP0AWID(S_AXI_HP0_AWID), + .SAXIHP0AWLEN(S_AXI_HP0_AWLEN), + .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK), + .SAXIHP0AWPROT(S_AXI_HP0_AWPROT), + .SAXIHP0AWQOS(S_AXI_HP0_AWQOS), + .SAXIHP0AWREADY(S_AXI_HP0_AWREADY), + .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]), + .SAXIHP0AWVALID(S_AXI_HP0_AWVALID), + .SAXIHP0BID(S_AXI_HP0_BID), + .SAXIHP0BREADY(S_AXI_HP0_BREADY), + .SAXIHP0BRESP(S_AXI_HP0_BRESP), + .SAXIHP0BVALID(S_AXI_HP0_BVALID), + .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT), + .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT), + .SAXIHP0RDATA(S_AXI_HP0_RDATA), + .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN), + .SAXIHP0RID(S_AXI_HP0_RID), + .SAXIHP0RLAST(S_AXI_HP0_RLAST), + .SAXIHP0RREADY(S_AXI_HP0_RREADY), + .SAXIHP0RRESP(S_AXI_HP0_RRESP), + .SAXIHP0RVALID(S_AXI_HP0_RVALID), + .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT), + .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT), + .SAXIHP0WDATA(S_AXI_HP0_WDATA), + .SAXIHP0WID(S_AXI_HP0_WID), + .SAXIHP0WLAST(S_AXI_HP0_WLAST), + .SAXIHP0WREADY(S_AXI_HP0_WREADY), + .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN), + .SAXIHP0WSTRB(S_AXI_HP0_WSTRB), + .SAXIHP0WVALID(S_AXI_HP0_WVALID), + .SAXIHP1ACLK(S_AXI_HP1_ACLK), + .SAXIHP1ARADDR(S_AXI_HP1_ARADDR), + .SAXIHP1ARBURST(S_AXI_HP1_ARBURST), + .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE), + .SAXIHP1ARESETN(S_AXI_HP1_ARESETN), + .SAXIHP1ARID(S_AXI_HP1_ARID), + .SAXIHP1ARLEN(S_AXI_HP1_ARLEN), + .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK), + .SAXIHP1ARPROT(S_AXI_HP1_ARPROT), + .SAXIHP1ARQOS(S_AXI_HP1_ARQOS), + .SAXIHP1ARREADY(S_AXI_HP1_ARREADY), + .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]), + .SAXIHP1ARVALID(S_AXI_HP1_ARVALID), + .SAXIHP1AWADDR(S_AXI_HP1_AWADDR), + .SAXIHP1AWBURST(S_AXI_HP1_AWBURST), + .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE), + .SAXIHP1AWID(S_AXI_HP1_AWID), + .SAXIHP1AWLEN(S_AXI_HP1_AWLEN), + .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK), + .SAXIHP1AWPROT(S_AXI_HP1_AWPROT), + .SAXIHP1AWQOS(S_AXI_HP1_AWQOS), + .SAXIHP1AWREADY(S_AXI_HP1_AWREADY), + .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]), + .SAXIHP1AWVALID(S_AXI_HP1_AWVALID), + .SAXIHP1BID(S_AXI_HP1_BID), + .SAXIHP1BREADY(S_AXI_HP1_BREADY), + .SAXIHP1BRESP(S_AXI_HP1_BRESP), + .SAXIHP1BVALID(S_AXI_HP1_BVALID), + .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT), + .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT), + .SAXIHP1RDATA(S_AXI_HP1_RDATA), + .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN), + .SAXIHP1RID(S_AXI_HP1_RID), + .SAXIHP1RLAST(S_AXI_HP1_RLAST), + .SAXIHP1RREADY(S_AXI_HP1_RREADY), + .SAXIHP1RRESP(S_AXI_HP1_RRESP), + .SAXIHP1RVALID(S_AXI_HP1_RVALID), + .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT), + .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT), + .SAXIHP1WDATA(S_AXI_HP1_WDATA), + .SAXIHP1WID(S_AXI_HP1_WID), + .SAXIHP1WLAST(S_AXI_HP1_WLAST), + .SAXIHP1WREADY(S_AXI_HP1_WREADY), + .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN), + .SAXIHP1WSTRB(S_AXI_HP1_WSTRB), + .SAXIHP1WVALID(S_AXI_HP1_WVALID), + .SAXIHP2ACLK(S_AXI_HP2_ACLK), + .SAXIHP2ARADDR(S_AXI_HP2_ARADDR), + .SAXIHP2ARBURST(S_AXI_HP2_ARBURST), + .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE), + .SAXIHP2ARESETN(S_AXI_HP2_ARESETN), + .SAXIHP2ARID(S_AXI_HP2_ARID), + .SAXIHP2ARLEN(S_AXI_HP2_ARLEN), + .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK), + .SAXIHP2ARPROT(S_AXI_HP2_ARPROT), + .SAXIHP2ARQOS(S_AXI_HP2_ARQOS), + .SAXIHP2ARREADY(S_AXI_HP2_ARREADY), + .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]), + .SAXIHP2ARVALID(S_AXI_HP2_ARVALID), + .SAXIHP2AWADDR(S_AXI_HP2_AWADDR), + .SAXIHP2AWBURST(S_AXI_HP2_AWBURST), + .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE), + .SAXIHP2AWID(S_AXI_HP2_AWID), + .SAXIHP2AWLEN(S_AXI_HP2_AWLEN), + .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK), + .SAXIHP2AWPROT(S_AXI_HP2_AWPROT), + .SAXIHP2AWQOS(S_AXI_HP2_AWQOS), + .SAXIHP2AWREADY(S_AXI_HP2_AWREADY), + .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]), + .SAXIHP2AWVALID(S_AXI_HP2_AWVALID), + .SAXIHP2BID(S_AXI_HP2_BID), + .SAXIHP2BREADY(S_AXI_HP2_BREADY), + .SAXIHP2BRESP(S_AXI_HP2_BRESP), + .SAXIHP2BVALID(S_AXI_HP2_BVALID), + .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT), + .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT), + .SAXIHP2RDATA(S_AXI_HP2_RDATA), + .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN), + .SAXIHP2RID(S_AXI_HP2_RID), + .SAXIHP2RLAST(S_AXI_HP2_RLAST), + .SAXIHP2RREADY(S_AXI_HP2_RREADY), + .SAXIHP2RRESP(S_AXI_HP2_RRESP), + .SAXIHP2RVALID(S_AXI_HP2_RVALID), + .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT), + .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT), + .SAXIHP2WDATA(S_AXI_HP2_WDATA), + .SAXIHP2WID(S_AXI_HP2_WID), + .SAXIHP2WLAST(S_AXI_HP2_WLAST), + .SAXIHP2WREADY(S_AXI_HP2_WREADY), + .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN), + .SAXIHP2WSTRB(S_AXI_HP2_WSTRB), + .SAXIHP2WVALID(S_AXI_HP2_WVALID), + .SAXIHP3ACLK(S_AXI_HP3_ACLK), + .SAXIHP3ARADDR(S_AXI_HP3_ARADDR), + .SAXIHP3ARBURST(S_AXI_HP3_ARBURST), + .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE), + .SAXIHP3ARESETN(S_AXI_HP3_ARESETN), + .SAXIHP3ARID(S_AXI_HP3_ARID), + .SAXIHP3ARLEN(S_AXI_HP3_ARLEN), + .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK), + .SAXIHP3ARPROT(S_AXI_HP3_ARPROT), + .SAXIHP3ARQOS(S_AXI_HP3_ARQOS), + .SAXIHP3ARREADY(S_AXI_HP3_ARREADY), + .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]), + .SAXIHP3ARVALID(S_AXI_HP3_ARVALID), + .SAXIHP3AWADDR(S_AXI_HP3_AWADDR), + .SAXIHP3AWBURST(S_AXI_HP3_AWBURST), + .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE), + .SAXIHP3AWID(S_AXI_HP3_AWID), + .SAXIHP3AWLEN(S_AXI_HP3_AWLEN), + .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK), + .SAXIHP3AWPROT(S_AXI_HP3_AWPROT), + .SAXIHP3AWQOS(S_AXI_HP3_AWQOS), + .SAXIHP3AWREADY(S_AXI_HP3_AWREADY), + .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]), + .SAXIHP3AWVALID(S_AXI_HP3_AWVALID), + .SAXIHP3BID(S_AXI_HP3_BID), + .SAXIHP3BREADY(S_AXI_HP3_BREADY), + .SAXIHP3BRESP(S_AXI_HP3_BRESP), + .SAXIHP3BVALID(S_AXI_HP3_BVALID), + .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT), + .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT), + .SAXIHP3RDATA(S_AXI_HP3_RDATA), + .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN), + .SAXIHP3RID(S_AXI_HP3_RID), + .SAXIHP3RLAST(S_AXI_HP3_RLAST), + .SAXIHP3RREADY(S_AXI_HP3_RREADY), + .SAXIHP3RRESP(S_AXI_HP3_RRESP), + .SAXIHP3RVALID(S_AXI_HP3_RVALID), + .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT), + .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT), + .SAXIHP3WDATA(S_AXI_HP3_WDATA), + .SAXIHP3WID(S_AXI_HP3_WID), + .SAXIHP3WLAST(S_AXI_HP3_WLAST), + .SAXIHP3WREADY(S_AXI_HP3_WREADY), + .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN), + .SAXIHP3WSTRB(S_AXI_HP3_WSTRB), + .SAXIHP3WVALID(S_AXI_HP3_WVALID)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_CLK_BIBUF + (.IO(buffered_PS_CLK), + .PAD(PS_CLK)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_PORB_BIBUF + (.IO(buffered_PS_PORB), + .PAD(PS_PORB)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_SRSTB_BIBUF + (.IO(buffered_PS_SRSTB), + .PAD(PS_SRSTB)); + LUT1 #( + .INIT(2'h1)) + SDIO0_CMD_T_INST_0 + (.I0(SDIO0_CMD_T_n), + .O(SDIO0_CMD_T)); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[0]_INST_0 + (.I0(SDIO0_DATA_T_n[0]), + .O(SDIO0_DATA_T[0])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[1]_INST_0 + (.I0(SDIO0_DATA_T_n[1]), + .O(SDIO0_DATA_T[1])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[2]_INST_0 + (.I0(SDIO0_DATA_T_n[2]), + .O(SDIO0_DATA_T[2])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[3]_INST_0 + (.I0(SDIO0_DATA_T_n[3]), + .O(SDIO0_DATA_T[3])); + LUT1 #( + .INIT(2'h1)) + SDIO1_CMD_T_INST_0 + (.I0(SDIO1_CMD_T_n), + .O(SDIO1_CMD_T)); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[0]_INST_0 + (.I0(SDIO1_DATA_T_n[0]), + .O(SDIO1_DATA_T[0])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[1]_INST_0 + (.I0(SDIO1_DATA_T_n[1]), + .O(SDIO1_DATA_T[1])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[2]_INST_0 + (.I0(SDIO1_DATA_T_n[2]), + .O(SDIO1_DATA_T[2])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[3]_INST_0 + (.I0(SDIO1_DATA_T_n[3]), + .O(SDIO1_DATA_T[3])); + LUT1 #( + .INIT(2'h1)) + SPI0_MISO_T_INST_0 + (.I0(SPI0_MISO_T_n), + .O(SPI0_MISO_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_MOSI_T_INST_0 + (.I0(SPI0_MOSI_T_n), + .O(SPI0_MOSI_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_SCLK_T_INST_0 + (.I0(SPI0_SCLK_T_n), + .O(SPI0_SCLK_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_SS_T_INST_0 + (.I0(SPI0_SS_T_n), + .O(SPI0_SS_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_MISO_T_INST_0 + (.I0(SPI1_MISO_T_n), + .O(SPI1_MISO_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_MOSI_T_INST_0 + (.I0(SPI1_MOSI_T_n), + .O(SPI1_MOSI_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_SCLK_T_INST_0 + (.I0(SPI1_SCLK_T_n), + .O(SPI1_SCLK_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_SS_T_INST_0 + (.I0(SPI1_SS_T_n), + .O(SPI1_SS_T)); + VCC VCC + (.P(\ )); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG + (.I(FCLK_CLK_unbuffered[0]), + .O(FCLK_CLK0)); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_1.FCLK_CLK_1_BUFG + (.I(FCLK_CLK_unbuffered[1]), + .O(FCLK_CLK1)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[0].MIO_BIBUF + (.IO(buffered_MIO[0]), + .PAD(MIO[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[10].MIO_BIBUF + (.IO(buffered_MIO[10]), + .PAD(MIO[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[11].MIO_BIBUF + (.IO(buffered_MIO[11]), + .PAD(MIO[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[12].MIO_BIBUF + (.IO(buffered_MIO[12]), + .PAD(MIO[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[13].MIO_BIBUF + (.IO(buffered_MIO[13]), + .PAD(MIO[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[14].MIO_BIBUF + (.IO(buffered_MIO[14]), + .PAD(MIO[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[15].MIO_BIBUF + (.IO(buffered_MIO[15]), + .PAD(MIO[15])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[16].MIO_BIBUF + (.IO(buffered_MIO[16]), + .PAD(MIO[16])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[17].MIO_BIBUF + (.IO(buffered_MIO[17]), + .PAD(MIO[17])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[18].MIO_BIBUF + (.IO(buffered_MIO[18]), + .PAD(MIO[18])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[19].MIO_BIBUF + (.IO(buffered_MIO[19]), + .PAD(MIO[19])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[1].MIO_BIBUF + (.IO(buffered_MIO[1]), + .PAD(MIO[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[20].MIO_BIBUF + (.IO(buffered_MIO[20]), + .PAD(MIO[20])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[21].MIO_BIBUF + (.IO(buffered_MIO[21]), + .PAD(MIO[21])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[22].MIO_BIBUF + (.IO(buffered_MIO[22]), + .PAD(MIO[22])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[23].MIO_BIBUF + (.IO(buffered_MIO[23]), + .PAD(MIO[23])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[24].MIO_BIBUF + (.IO(buffered_MIO[24]), + .PAD(MIO[24])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[25].MIO_BIBUF + (.IO(buffered_MIO[25]), + .PAD(MIO[25])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[26].MIO_BIBUF + (.IO(buffered_MIO[26]), + .PAD(MIO[26])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[27].MIO_BIBUF + (.IO(buffered_MIO[27]), + .PAD(MIO[27])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[28].MIO_BIBUF + (.IO(buffered_MIO[28]), + .PAD(MIO[28])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[29].MIO_BIBUF + (.IO(buffered_MIO[29]), + .PAD(MIO[29])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[2].MIO_BIBUF + (.IO(buffered_MIO[2]), + .PAD(MIO[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[30].MIO_BIBUF + (.IO(buffered_MIO[30]), + .PAD(MIO[30])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[31].MIO_BIBUF + (.IO(buffered_MIO[31]), + .PAD(MIO[31])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[3].MIO_BIBUF + (.IO(buffered_MIO[3]), + .PAD(MIO[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[4].MIO_BIBUF + (.IO(buffered_MIO[4]), + .PAD(MIO[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[5].MIO_BIBUF + (.IO(buffered_MIO[5]), + .PAD(MIO[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[6].MIO_BIBUF + (.IO(buffered_MIO[6]), + .PAD(MIO[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[7].MIO_BIBUF + (.IO(buffered_MIO[7]), + .PAD(MIO[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[8].MIO_BIBUF + (.IO(buffered_MIO[8]), + .PAD(MIO[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[9].MIO_BIBUF + (.IO(buffered_MIO[9]), + .PAD(MIO[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[0].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[0]), + .PAD(DDR_BankAddr[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[1].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[1]), + .PAD(DDR_BankAddr[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[2].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[2]), + .PAD(DDR_BankAddr[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[0].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[0]), + .PAD(DDR_Addr[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[10].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[10]), + .PAD(DDR_Addr[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[11].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[11]), + .PAD(DDR_Addr[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[12].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[12]), + .PAD(DDR_Addr[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[13].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[13]), + .PAD(DDR_Addr[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[14].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[14]), + .PAD(DDR_Addr[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[1].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[1]), + .PAD(DDR_Addr[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[2].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[2]), + .PAD(DDR_Addr[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[3].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[3]), + .PAD(DDR_Addr[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[4].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[4]), + .PAD(DDR_Addr[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[5].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[5]), + .PAD(DDR_Addr[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[6].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[6]), + .PAD(DDR_Addr[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[7].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[7]), + .PAD(DDR_Addr[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[8].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[8]), + .PAD(DDR_Addr[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[9].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[9]), + .PAD(DDR_Addr[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[0].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[0]), + .PAD(DDR_DM[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[1].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[1]), + .PAD(DDR_DM[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[0].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[0]), + .PAD(DDR_DQ[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[10].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[10]), + .PAD(DDR_DQ[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[11].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[11]), + .PAD(DDR_DQ[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[12].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[12]), + .PAD(DDR_DQ[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[13].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[13]), + .PAD(DDR_DQ[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[14].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[14]), + .PAD(DDR_DQ[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[15].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[15]), + .PAD(DDR_DQ[15])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[1].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[1]), + .PAD(DDR_DQ[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[2].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[2]), + .PAD(DDR_DQ[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[3].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[3]), + .PAD(DDR_DQ[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[4].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[4]), + .PAD(DDR_DQ[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[5].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[5]), + .PAD(DDR_DQ[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[6].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[6]), + .PAD(DDR_DQ[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[7].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[7]), + .PAD(DDR_DQ[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[8].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[8]), + .PAD(DDR_DQ[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[9].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[9]), + .PAD(DDR_DQ[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[0].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[0]), + .PAD(DDR_DQS_n[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[1].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[1]), + .PAD(DDR_DQS_n[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[0].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[0]), + .PAD(DDR_DQS[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[1].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[1]), + .PAD(DDR_DQS[1])); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[0] )); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[0] [1])); + LUT1 #( + .INIT(2'h2)) + i_10 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[7] [1])); + LUT1 #( + .INIT(2'h2)) + i_11 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[7] [0])); + LUT1 #( + .INIT(2'h2)) + i_12 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[6] [1])); + LUT1 #( + .INIT(2'h2)) + i_13 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[6] [0])); + LUT1 #( + .INIT(2'h2)) + i_14 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[5] [1])); + LUT1 #( + .INIT(2'h2)) + i_15 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[5] [0])); + LUT1 #( + .INIT(2'h2)) + i_16 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[4] [1])); + LUT1 #( + .INIT(2'h2)) + i_17 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[4] [0])); + LUT1 #( + .INIT(2'h2)) + i_18 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[3] [1])); + LUT1 #( + .INIT(2'h2)) + i_19 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[3] [0])); + LUT1 #( + .INIT(2'h2)) + i_2 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[0] [0])); + LUT1 #( + .INIT(2'h2)) + i_20 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[2] [1])); + LUT1 #( + .INIT(2'h2)) + i_21 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[2] [0])); + LUT1 #( + .INIT(2'h2)) + i_22 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[1] [1])); + LUT1 #( + .INIT(2'h2)) + i_23 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[1] [0])); + LUT1 #( + .INIT(2'h2)) + i_3 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[7] )); + LUT1 #( + .INIT(2'h2)) + i_4 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[6] )); + LUT1 #( + .INIT(2'h2)) + i_5 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[5] )); + LUT1 #( + .INIT(2'h2)) + i_6 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[4] )); + LUT1 #( + .INIT(2'h2)) + i_7 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[3] )); + LUT1 #( + .INIT(2'h2)) + i_8 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[2] )); + LUT1 #( + .INIT(2'h2)) + i_9 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[1] )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v new file mode 100644 index 0000000..146bc3f --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v @@ -0,0 +1,164 @@ +// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +// Date : Fri Aug 17 17:36:46 2018 +// Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub +// c:/Users/qwpmb/Documents/summercamp2018/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v +// Design : design_1_processing_system7_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg225-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *) +module design_1_processing_system7_0_0(GPIO_I, GPIO_O, GPIO_T, I2C0_SDA_I, I2C0_SDA_O, + I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, SDIO0_CLK, SDIO0_CLK_FB, SDIO0_CMD_O, + SDIO0_CMD_I, SDIO0_CMD_T, SDIO0_DATA_I, SDIO0_DATA_O, SDIO0_DATA_T, SDIO0_LED, SDIO0_CDN, + SDIO0_WP, SDIO0_BUSPOW, SDIO0_BUSVOLT, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, + SPI0_MOSI_O, SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, + SPI0_SS1_O, SPI0_SS2_O, SPI0_SS_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, + SPI1_MOSI_O, SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, + SPI1_SS1_O, SPI1_SS2_O, SPI1_SS_T, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, TTC1_WAVE0_OUT, TTC1_WAVE1_OUT, TTC1_WAVE2_OUT, USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, + M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, + M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_CLK1, + FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, + DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, + PS_SRSTB, PS_CLK, PS_PORB) +/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_CLK,SDIO0_CLK_FB,SDIO0_CMD_O,SDIO0_CMD_I,SDIO0_CMD_T,SDIO0_DATA_I[3:0],SDIO0_DATA_O[3:0],SDIO0_DATA_T[3:0],SDIO0_LED,SDIO0_CDN,SDIO0_WP,SDIO0_BUSPOW,SDIO0_BUSVOLT[2:0],SPI0_SCLK_I,SPI0_SCLK_O,SPI0_SCLK_T,SPI0_MOSI_I,SPI0_MOSI_O,SPI0_MOSI_T,SPI0_MISO_I,SPI0_MISO_O,SPI0_MISO_T,SPI0_SS_I,SPI0_SS_O,SPI0_SS1_O,SPI0_SS2_O,SPI0_SS_T,SPI1_SCLK_I,SPI1_SCLK_O,SPI1_SCLK_T,SPI1_MOSI_I,SPI1_MOSI_O,SPI1_MOSI_T,SPI1_MISO_I,SPI1_MISO_O,SPI1_MISO_T,SPI1_SS_I,SPI1_SS_O,SPI1_SS1_O,SPI1_SS2_O,SPI1_SS_T,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,TTC1_WAVE0_OUT,TTC1_WAVE1_OUT,TTC1_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[31:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[1:0],DDR_DQ[15:0],DDR_DQS_n[1:0],DDR_DQS[1:0],PS_SRSTB,PS_CLK,PS_PORB" */; + input [63:0]GPIO_I; + output [63:0]GPIO_O; + output [63:0]GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0]SDIO0_DATA_I; + output [3:0]SDIO0_DATA_O; + output [3:0]SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0]SDIO0_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_TX; + input UART0_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + output [1:0]USB0_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [11:0]M_AXI_GP0_ARID; + output [11:0]M_AXI_GP0_AWID; + output [11:0]M_AXI_GP0_WID; + output [1:0]M_AXI_GP0_ARBURST; + output [1:0]M_AXI_GP0_ARLOCK; + output [2:0]M_AXI_GP0_ARSIZE; + output [1:0]M_AXI_GP0_AWBURST; + output [1:0]M_AXI_GP0_AWLOCK; + output [2:0]M_AXI_GP0_AWSIZE; + output [2:0]M_AXI_GP0_ARPROT; + output [2:0]M_AXI_GP0_AWPROT; + output [31:0]M_AXI_GP0_ARADDR; + output [31:0]M_AXI_GP0_AWADDR; + output [31:0]M_AXI_GP0_WDATA; + output [3:0]M_AXI_GP0_ARCACHE; + output [3:0]M_AXI_GP0_ARLEN; + output [3:0]M_AXI_GP0_ARQOS; + output [3:0]M_AXI_GP0_AWCACHE; + output [3:0]M_AXI_GP0_AWLEN; + output [3:0]M_AXI_GP0_AWQOS; + output [3:0]M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [11:0]M_AXI_GP0_BID; + input [11:0]M_AXI_GP0_RID; + input [1:0]M_AXI_GP0_BRESP; + input [1:0]M_AXI_GP0_RRESP; + input [31:0]M_AXI_GP0_RDATA; + input [0:0]IRQ_F2P; + output FCLK_CLK0; + output FCLK_CLK1; + output FCLK_RESET0_N; + inout [31:0]MIO; + inout DDR_CAS_n; + inout DDR_CKE; + inout DDR_Clk_n; + inout DDR_Clk; + inout DDR_CS_n; + inout DDR_DRSTB; + inout DDR_ODT; + inout DDR_RAS_n; + inout DDR_WEB; + inout [2:0]DDR_BankAddr; + inout [14:0]DDR_Addr; + inout DDR_VRN; + inout DDR_VRP; + inout [1:0]DDR_DM; + inout [15:0]DDR_DQ; + inout [1:0]DDR_DQS_n; + inout [1:0]DDR_DQS; + inout PS_SRSTB; + inout PS_CLK; + inout PS_PORB; +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v new file mode 100644 index 0000000..3f7b3e7 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v @@ -0,0 +1,3935 @@ + +//----------------------------------------------------------------------------- +// processing_system7 +// processor sub system wrapper +//----------------------------------------------------------------------------- +// +// ************************************************************************ +// ** DISCLAIMER OF LIABILITY ** +// ** ** +// ** This file contains proprietary and confidential information of ** +// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** +// ** from Xilinx, and may be used, copied and/or diSCLosed only ** +// ** pursuant to the terms of a valid license agreement with Xilinx. ** +// ** ** +// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** +// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** +// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** +// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** +// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** +// ** does not warrant that functions included in the Materials will ** +// ** meet the requirements of Licensee, or that the operation of the ** +// ** Materials will be uninterrupted or error-free, or that defects ** +// ** in the Materials will be corrected. Furthermore, Xilinx does ** +// ** not warrant or make any representations regarding use, or the ** +// ** results of the use, of the Materials in terms of correctness, ** +// ** accuracy, reliability or otherwise. ** +// ** ** +// ** Xilinx products are not designed or intended to be fail-safe, ** +// ** or for use in any application requiring fail-safe performance, ** +// ** such as life-support or safety devices or systems, Class III ** +// ** medical devices, nuclear facilities, applications related to ** +// ** the deployment of airbags, or any other applications that could ** +// ** lead to death, personal injury or severe property or ** +// ** environmental damage (individually and collectively, "critical ** +// ** applications"). Customer assumes the sole risk and liability ** +// ** of any use of Xilinx products in critical applications, ** +// ** subject only to applicable laws and regulations governing ** +// ** limitations on product liability. ** +// ** ** +// ** Copyright 2010 Xilinx, Inc. ** +// ** All rights reserved. ** +// ** ** +// ** This disclaimer and copyright notice must be retained as part ** +// ** of this file at all times. ** +// ************************************************************************ +// +//----------------------------------------------------------------------------- +// Filename: processing_system7_v5_5_processing_system7.v +// Version: v1.00.a +// Description: This is the wrapper file for PSS. +//----------------------------------------------------------------------------- +// Structure: This section shows the hierarchical structure of +// pss_wrapper. +// +// --processing_system7_v5_5_processing_system7.v +// --PS7.v - Unisim component +//----------------------------------------------------------------------------- +// Author: SD +// +// History: +// +// SD 09/20/11 -- First version +// ~~~~~~ +// Created the first version v2.00.a +// ^^^^^^ +//------------------------------------------------------------------------------ +// ^^^^^^ +// SR 11/25/11 -- v3.00.a version +// ~~~~~~~ +// Key changes are +// 1. Changed all clock, reset and clktrig ports to be individual +// signals instead of vectors. This is required for modeling of tools. +// 2. Interrupts are now defined as individual signals as well. +// 3. Added Clk buffer logic for FCLK_CLK +// 4. Includes the ACP related changes done +// +// TODO: +// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the +// number of interrupt ports connected for IRQ_F2P. +// +//------------------------------------------------------------------------------ +// ^^^^^^ +// KP 12/07/11 -- v3.00.a version +// ~~~~~~~ +// Key changes are +// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 12/09/11 -- v3.00.a version +// ~~~~~~~ +// Key changes are +// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated +// to STRING and fix for CR 640523 +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 12/13/11 -- v3.00.a version +// ~~~~~~~ +// Key changes are +// Updated IRQ_F2P logic to address CR 641523. +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 02/01/12 -- v3.01.a version +// ~~~~~~~ +// Key changes are +// Updated SDIO logic to address CR 636210. +// | +// Added C_PS7_SI_REV parameter to track SI Rev +// Removed compress/decompress logic to address CR 642527. +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 02/27/12 -- v3.01.a version +// ~~~~~~~ +// Key changes are +// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual +// ports as fix for CR 646379 +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 03/05/12 -- v3.01.a version +// ~~~~~~~ +// Key changes are +// Added/updated compress/decompress logic to address 648393 +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 03/14/12 -- v4.00.a version +// ~~~~~~~ +// Unused parameters deleted CR 651120 +// Addressed CR 651751 +//------------------------------------------------------------------------------ +// ^^^^^^ +// NR 04/17/12 -- v4.01.a version +// ~~~~~~~ +// Added FTM trace buffer functionality +// Added support for ACP AxUSER ports local update +//------------------------------------------------------------------------------ +// ^^^^^^ +// VR 05/18/12 -- v4.01.a version +// ~~~~~~~ +// Fixed CR#659157 +//------------------------------------------------------------------------------ +// ^^^^^^ +// VR 07/25/12 -- v4.01.a version +// ~~~~~~~ +// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model +// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model +//------------------------------------------------------------------------------ +// ^^^^^^ +// VR 11/06/12 -- v5.00 version +// ~~~~~~~ +// CR #682573 +// Added BIBUF to fixed IO ports and IBUF to fixed input ports +//------------------------------------------------------------------------------ +(*POWER= "/>" *) +(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.91, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.0, PCW_UIPARAM_DDR_BOARD_DELAY0=0.25, PCW_UIPARAM_DDR_BOARD_DELAY1=0.25, PCW_UIPARAM_DDR_BOARD_DELAY2=0.25, PCW_UIPARAM_DDR_BOARD_DELAY3=0.25, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=81.244, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=57.044, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=520, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=700, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=77.166, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=53.995, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=550, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=780, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=86.1835, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=86.1835, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=86.1835, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=86.1835, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\ +, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666666, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=100, PCW_UART_PERIPHERAL_FREQMHZ=100, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=50, PCW_FPGA1_PERIPHERAL_FREQMHZ=100, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=50\ +, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=10, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 3.3V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3 (Low Voltage), PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=16 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0\ +, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=0, PCW_ENET0_GRP_MDIO_ENABLE=0, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=EMIO, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=EMIO, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=1, PCW_SD1_SD1_IO=MIO 10 .. 15, PCW_SD1_GRP_CD_ENABLE=1, PCW_SD1_GRP_CD_IO=MIO 0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=1, PCW_UART0_UART0_IO=EMIO, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 8 .. 9, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=EMIO, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=EMIO, PCW_SPI0_GRP_SS1_ENABLE=1, PCW_SPI0_GRP_SS1_IO=EMIO, PCW_SPI0_GRP_SS2_ENABLE=1, PCW_SPI0_GRP_SS2_IO=EMIO, PCW_SPI1_PERIPHERAL_ENABLE=1, PCW_SPI1_SPI1_IO=EMIO, PCW_SPI1_GRP_SS0_ENABLE=1, PCW_SPI1_GRP_SS0_IO=EMIO, PCW_SPI1_GRP_SS1_ENABLE=1, PCW_SPI1_GRP_SS1_IO=EMIO, PCW_SPI1_GRP_SS2_ENABLE=1\ +, PCW_SPI1_GRP_SS2_IO=EMIO, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=1, PCW_TTC1_TTC1_IO=EMIO, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 7, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=1, PCW_I2C1_I2C1_IO=MIO 48 .. 49, PCW_I2C1_GRP_INT_ENABLE=1, PCW_I2C1_GRP_INT_IO=EMIO, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=1, PCW_GPIO_EMIO_GPIO_IO=64, PCW_APU_CLK_RATIO_ENABLE=0.251400462962963, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL\ +, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=External, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11\ +, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *) +(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) + +module processing_system7_v5_5_processing_system7 + +#( + parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1, + parameter integer C_S_AXI_ACP_ARUSER_VAL = 31, + parameter integer C_S_AXI_ACP_AWUSER_VAL = 31, + parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12, + parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12, + parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1, + parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1, + parameter integer C_M_AXI_GP0_ID_WIDTH = 12, + parameter integer C_M_AXI_GP1_ID_WIDTH = 12, + parameter integer C_S_AXI_GP0_ID_WIDTH = 6, + parameter integer C_S_AXI_GP1_ID_WIDTH = 6, + parameter integer C_S_AXI_HP0_ID_WIDTH = 6, + parameter integer C_S_AXI_HP1_ID_WIDTH = 6, + parameter integer C_S_AXI_HP2_ID_WIDTH = 6, + parameter integer C_S_AXI_HP3_ID_WIDTH = 6, + parameter integer C_S_AXI_ACP_ID_WIDTH = 3, + parameter integer C_S_AXI_HP0_DATA_WIDTH = 64, + parameter integer C_S_AXI_HP1_DATA_WIDTH = 64, + parameter integer C_S_AXI_HP2_DATA_WIDTH = 64, + parameter integer C_S_AXI_HP3_DATA_WIDTH = 64, + parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0, + parameter integer C_NUM_F2P_INTR_INPUTS = 1, + parameter C_FCLK_CLK0_BUF = "TRUE", + parameter C_FCLK_CLK1_BUF = "TRUE", + parameter C_FCLK_CLK2_BUF = "TRUE", + parameter C_FCLK_CLK3_BUF = "TRUE", + parameter integer C_EMIO_GPIO_WIDTH = 64, + parameter integer C_INCLUDE_TRACE_BUFFER = 0, + parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128, + parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12, + parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0, + parameter integer C_TRACE_PIPELINE_WIDTH = 8, + parameter C_PS7_SI_REV = "PRODUCTION", + parameter integer C_EN_EMIO_ENET0 = 0, + parameter integer C_EN_EMIO_ENET1 = 0, + parameter integer C_EN_EMIO_TRACE = 0, + parameter integer C_DQ_WIDTH = 32, + parameter integer C_DQS_WIDTH = 4, + parameter integer C_DM_WIDTH = 4, + parameter integer C_MIO_PRIMITIVE = 54, + parameter C_PACKAGE_NAME = "clg484", + parameter C_IRQ_F2P_MODE = "DIRECT", + parameter C_TRACE_INTERNAL_WIDTH = 32, + parameter integer C_EN_EMIO_PJTAG = 0, + + // Enable and disable AFI Secure transaction + parameter C_USE_AXI_NONSECURE = 0, + + //parameters for HP enable ports + parameter C_USE_S_AXI_HP0 = 0, + parameter C_USE_S_AXI_HP1 = 0, + parameter C_USE_S_AXI_HP2 = 0, + parameter C_USE_S_AXI_HP3 = 0, + + //parameters for GP and ACP enable ports */ + parameter C_USE_M_AXI_GP0 = 0, + parameter C_USE_M_AXI_GP1 = 0, + parameter C_USE_S_AXI_GP0 = 0, + parameter C_USE_S_AXI_GP1 = 0, + parameter C_USE_S_AXI_ACP = 0, + parameter C_GP0_EN_MODIFIABLE_TXN=0, + parameter C_GP1_EN_MODIFIABLE_TXN=0 + +) +( + //FMIO ========================================= + + //FMIO CAN0 + output CAN0_PHY_TX, + input CAN0_PHY_RX, + + //FMIO CAN1 + output CAN1_PHY_TX, + input CAN1_PHY_RX, + + //FMIO ENET0 + output reg ENET0_GMII_TX_EN = 'b0, + output reg ENET0_GMII_TX_ER = 'b0, + output ENET0_MDIO_MDC, + output ENET0_MDIO_O, + output ENET0_MDIO_T, + output ENET0_PTP_DELAY_REQ_RX, + output ENET0_PTP_DELAY_REQ_TX, + output ENET0_PTP_PDELAY_REQ_RX, + output ENET0_PTP_PDELAY_REQ_TX, + output ENET0_PTP_PDELAY_RESP_RX, + output ENET0_PTP_PDELAY_RESP_TX, + output ENET0_PTP_SYNC_FRAME_RX, + output ENET0_PTP_SYNC_FRAME_TX, + output ENET0_SOF_RX, + output ENET0_SOF_TX, + + + output reg [7:0] ENET0_GMII_TXD, + + + input ENET0_GMII_COL, + input ENET0_GMII_CRS, + input ENET0_GMII_RX_CLK, + input ENET0_GMII_RX_DV, + input ENET0_GMII_RX_ER, + input ENET0_GMII_TX_CLK, + input ENET0_MDIO_I, + input ENET0_EXT_INTIN, + input [7:0] ENET0_GMII_RXD, + + //FMIO ENET1 + output reg ENET1_GMII_TX_EN = 'b0, + output reg ENET1_GMII_TX_ER = 'b0, + output ENET1_MDIO_MDC, + output ENET1_MDIO_O, + output ENET1_MDIO_T, + output ENET1_PTP_DELAY_REQ_RX, + output ENET1_PTP_DELAY_REQ_TX, + output ENET1_PTP_PDELAY_REQ_RX, + output ENET1_PTP_PDELAY_REQ_TX, + output ENET1_PTP_PDELAY_RESP_RX, + output ENET1_PTP_PDELAY_RESP_TX, + output ENET1_PTP_SYNC_FRAME_RX, + output ENET1_PTP_SYNC_FRAME_TX, + output ENET1_SOF_RX, + output ENET1_SOF_TX, + output reg [7:0] ENET1_GMII_TXD, + + input ENET1_GMII_COL, + input ENET1_GMII_CRS, + input ENET1_GMII_RX_CLK, + input ENET1_GMII_RX_DV, + input ENET1_GMII_RX_ER, + input ENET1_GMII_TX_CLK, + input ENET1_MDIO_I, + input ENET1_EXT_INTIN, + input [7:0] ENET1_GMII_RXD, + + //FMIO GPIO + input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I, + output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O, + output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T, + + //FMIO I2C0 + input I2C0_SDA_I, + output I2C0_SDA_O, + output I2C0_SDA_T, + input I2C0_SCL_I, + output I2C0_SCL_O, + output I2C0_SCL_T, + + //FMIO I2C1 + input I2C1_SDA_I, + output I2C1_SDA_O, + output I2C1_SDA_T, + input I2C1_SCL_I, + output I2C1_SCL_O, + output I2C1_SCL_T, + + //FMIO PJTAG + input PJTAG_TCK, + input PJTAG_TMS, + input PJTAG_TDI, + output PJTAG_TDO, + + + //FMIO SDIO0 + output SDIO0_CLK, + input SDIO0_CLK_FB, + output SDIO0_CMD_O, + input SDIO0_CMD_I, + output SDIO0_CMD_T, + input [3:0] SDIO0_DATA_I, + output [3:0] SDIO0_DATA_O, + output [3:0] SDIO0_DATA_T, + output SDIO0_LED, + input SDIO0_CDN, + input SDIO0_WP, + output SDIO0_BUSPOW, + output [2:0] SDIO0_BUSVOLT, + + //FMIO SDIO1 + output SDIO1_CLK, + input SDIO1_CLK_FB, + output SDIO1_CMD_O, + input SDIO1_CMD_I, + output SDIO1_CMD_T, + input [3:0] SDIO1_DATA_I, + output [3:0] SDIO1_DATA_O, + output [3:0] SDIO1_DATA_T, + output SDIO1_LED, + input SDIO1_CDN, + input SDIO1_WP, + output SDIO1_BUSPOW, + output [2:0] SDIO1_BUSVOLT, + + //FMIO SPI0 + input SPI0_SCLK_I, + output SPI0_SCLK_O, + output SPI0_SCLK_T, + input SPI0_MOSI_I, + output SPI0_MOSI_O, + output SPI0_MOSI_T, + input SPI0_MISO_I, + output SPI0_MISO_O, + output SPI0_MISO_T, + input SPI0_SS_I, + output SPI0_SS_O, + output SPI0_SS1_O, + output SPI0_SS2_O, + output SPI0_SS_T, + + //FMIO SPI1 + input SPI1_SCLK_I, + output SPI1_SCLK_O, + output SPI1_SCLK_T, + input SPI1_MOSI_I, + output SPI1_MOSI_O, + output SPI1_MOSI_T, + input SPI1_MISO_I, + output SPI1_MISO_O, + output SPI1_MISO_T, + input SPI1_SS_I, + output SPI1_SS_O, + output SPI1_SS1_O, + output SPI1_SS2_O, + output SPI1_SS_T, + + //FMIO UART0 + output UART0_DTRN, + output UART0_RTSN, + output UART0_TX, + input UART0_CTSN, + input UART0_DCDN, + input UART0_DSRN, + input UART0_RIN, + input UART0_RX, + + //FMIO UART1 + output UART1_DTRN, + output UART1_RTSN, + output UART1_TX, + input UART1_CTSN, + input UART1_DCDN, + input UART1_DSRN, + input UART1_RIN, + input UART1_RX, + + //FMIO TTC0 + output TTC0_WAVE0_OUT, + output TTC0_WAVE1_OUT, + output TTC0_WAVE2_OUT, + input TTC0_CLK0_IN, + input TTC0_CLK1_IN, + input TTC0_CLK2_IN, + + //FMIO TTC1 + output TTC1_WAVE0_OUT, + output TTC1_WAVE1_OUT, + output TTC1_WAVE2_OUT, + input TTC1_CLK0_IN, + input TTC1_CLK1_IN, + input TTC1_CLK2_IN, + + //WDT + input WDT_CLK_IN, + output WDT_RST_OUT, + + //FTPORT + input TRACE_CLK, + output TRACE_CTL, + output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA, + output reg TRACE_CLK_OUT, + + // USB + output [1:0] USB0_PORT_INDCTL, + output USB0_VBUS_PWRSELECT, + input USB0_VBUS_PWRFAULT, + + output [1:0] USB1_PORT_INDCTL, + output USB1_VBUS_PWRSELECT, + input USB1_VBUS_PWRFAULT, + + input SRAM_INTIN, + + //AIO =================================================== + + //M_AXI_GP0 + + // -- Output + + output M_AXI_GP0_ARESETN, + output M_AXI_GP0_ARVALID, + output M_AXI_GP0_AWVALID, + output M_AXI_GP0_BREADY, + output M_AXI_GP0_RREADY, + output M_AXI_GP0_WLAST, + output M_AXI_GP0_WVALID, + output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID, + output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID, + output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID, + output [1:0] M_AXI_GP0_ARBURST, + output [1:0] M_AXI_GP0_ARLOCK, + output [2:0] M_AXI_GP0_ARSIZE, + output [1:0] M_AXI_GP0_AWBURST, + output [1:0] M_AXI_GP0_AWLOCK, + output [2:0] M_AXI_GP0_AWSIZE, + output [2:0] M_AXI_GP0_ARPROT, + output [2:0] M_AXI_GP0_AWPROT, + output [31:0] M_AXI_GP0_ARADDR, + output [31:0] M_AXI_GP0_AWADDR, + output [31:0] M_AXI_GP0_WDATA, + output [3:0] M_AXI_GP0_ARCACHE, + output [3:0] M_AXI_GP0_ARLEN, + output [3:0] M_AXI_GP0_ARQOS, + output [3:0] M_AXI_GP0_AWCACHE, + output [3:0] M_AXI_GP0_AWLEN, + output [3:0] M_AXI_GP0_AWQOS, + output [3:0] M_AXI_GP0_WSTRB, + + // -- Input + + input M_AXI_GP0_ACLK, + input M_AXI_GP0_ARREADY, + input M_AXI_GP0_AWREADY, + input M_AXI_GP0_BVALID, + input M_AXI_GP0_RLAST, + input M_AXI_GP0_RVALID, + input M_AXI_GP0_WREADY, + input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID, + input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID, + input [1:0] M_AXI_GP0_BRESP, + input [1:0] M_AXI_GP0_RRESP, + input [31:0] M_AXI_GP0_RDATA, + + + //M_AXI_GP1 + + // -- Output + + output M_AXI_GP1_ARESETN, + output M_AXI_GP1_ARVALID, + output M_AXI_GP1_AWVALID, + output M_AXI_GP1_BREADY, + output M_AXI_GP1_RREADY, + output M_AXI_GP1_WLAST, + output M_AXI_GP1_WVALID, + output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID, + output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID, + output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID, + output [1:0] M_AXI_GP1_ARBURST, + output [1:0] M_AXI_GP1_ARLOCK, + output [2:0] M_AXI_GP1_ARSIZE, + output [1:0] M_AXI_GP1_AWBURST, + output [1:0] M_AXI_GP1_AWLOCK, + output [2:0] M_AXI_GP1_AWSIZE, + output [2:0] M_AXI_GP1_ARPROT, + output [2:0] M_AXI_GP1_AWPROT, + output [31:0] M_AXI_GP1_ARADDR, + output [31:0] M_AXI_GP1_AWADDR, + output [31:0] M_AXI_GP1_WDATA, + output [3:0] M_AXI_GP1_ARCACHE, + output [3:0] M_AXI_GP1_ARLEN, + output [3:0] M_AXI_GP1_ARQOS, + output [3:0] M_AXI_GP1_AWCACHE, + output [3:0] M_AXI_GP1_AWLEN, + output [3:0] M_AXI_GP1_AWQOS, + output [3:0] M_AXI_GP1_WSTRB, + + // -- Input + + input M_AXI_GP1_ACLK, + input M_AXI_GP1_ARREADY, + input M_AXI_GP1_AWREADY, + input M_AXI_GP1_BVALID, + input M_AXI_GP1_RLAST, + input M_AXI_GP1_RVALID, + input M_AXI_GP1_WREADY, + input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID, + input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID, + input [1:0] M_AXI_GP1_BRESP, + input [1:0] M_AXI_GP1_RRESP, + input [31:0] M_AXI_GP1_RDATA, + + + // S_AXI_GP0 + + // -- Output + + output S_AXI_GP0_ARESETN, + output S_AXI_GP0_ARREADY, + output S_AXI_GP0_AWREADY, + output S_AXI_GP0_BVALID, + output S_AXI_GP0_RLAST, + output S_AXI_GP0_RVALID, + output S_AXI_GP0_WREADY, + output [1:0] S_AXI_GP0_BRESP, + output [1:0] S_AXI_GP0_RRESP, + output [31:0] S_AXI_GP0_RDATA, + output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID, + output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID, + + // -- Input + input S_AXI_GP0_ACLK, + input S_AXI_GP0_ARVALID, + input S_AXI_GP0_AWVALID, + input S_AXI_GP0_BREADY, + input S_AXI_GP0_RREADY, + input S_AXI_GP0_WLAST, + input S_AXI_GP0_WVALID, + input [1:0] S_AXI_GP0_ARBURST, + input [1:0] S_AXI_GP0_ARLOCK, + input [2:0] S_AXI_GP0_ARSIZE, + input [1:0] S_AXI_GP0_AWBURST, + input [1:0] S_AXI_GP0_AWLOCK, + input [2:0] S_AXI_GP0_AWSIZE, + input [2:0] S_AXI_GP0_ARPROT, + input [2:0] S_AXI_GP0_AWPROT, + input [31:0] S_AXI_GP0_ARADDR, + input [31:0] S_AXI_GP0_AWADDR, + input [31:0] S_AXI_GP0_WDATA, + input [3:0] S_AXI_GP0_ARCACHE, + input [3:0] S_AXI_GP0_ARLEN, + input [3:0] S_AXI_GP0_ARQOS, + input [3:0] S_AXI_GP0_AWCACHE, + input [3:0] S_AXI_GP0_AWLEN, + input [3:0] S_AXI_GP0_AWQOS, + input [3:0] S_AXI_GP0_WSTRB, + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID, + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID, + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID, + + // S_AXI_GP1 + + // -- Output + output S_AXI_GP1_ARESETN, + output S_AXI_GP1_ARREADY, + output S_AXI_GP1_AWREADY, + output S_AXI_GP1_BVALID, + output S_AXI_GP1_RLAST, + output S_AXI_GP1_RVALID, + output S_AXI_GP1_WREADY, + output [1:0] S_AXI_GP1_BRESP, + output [1:0] S_AXI_GP1_RRESP, + output [31:0] S_AXI_GP1_RDATA, + output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID, + output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID, + + // -- Input + input S_AXI_GP1_ACLK, + input S_AXI_GP1_ARVALID, + input S_AXI_GP1_AWVALID, + input S_AXI_GP1_BREADY, + input S_AXI_GP1_RREADY, + input S_AXI_GP1_WLAST, + input S_AXI_GP1_WVALID, + input [1:0] S_AXI_GP1_ARBURST, + input [1:0] S_AXI_GP1_ARLOCK, + input [2:0] S_AXI_GP1_ARSIZE, + input [1:0] S_AXI_GP1_AWBURST, + input [1:0] S_AXI_GP1_AWLOCK, + input [2:0] S_AXI_GP1_AWSIZE, + input [2:0] S_AXI_GP1_ARPROT, + input [2:0] S_AXI_GP1_AWPROT, + input [31:0] S_AXI_GP1_ARADDR, + input [31:0] S_AXI_GP1_AWADDR, + input [31:0] S_AXI_GP1_WDATA, + input [3:0] S_AXI_GP1_ARCACHE, + input [3:0] S_AXI_GP1_ARLEN, + input [3:0] S_AXI_GP1_ARQOS, + input [3:0] S_AXI_GP1_AWCACHE, + input [3:0] S_AXI_GP1_AWLEN, + input [3:0] S_AXI_GP1_AWQOS, + input [3:0] S_AXI_GP1_WSTRB, + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID, + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID, + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID, + + //S_AXI_ACP + + // -- Output + + output S_AXI_ACP_ARESETN, + output S_AXI_ACP_ARREADY, + output S_AXI_ACP_AWREADY, + output S_AXI_ACP_BVALID, + output S_AXI_ACP_RLAST, + output S_AXI_ACP_RVALID, + output S_AXI_ACP_WREADY, + output [1:0] S_AXI_ACP_BRESP, + output [1:0] S_AXI_ACP_RRESP, + output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID, + output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID, + output [63:0] S_AXI_ACP_RDATA, + + // -- Input + + input S_AXI_ACP_ACLK, + input S_AXI_ACP_ARVALID, + input S_AXI_ACP_AWVALID, + input S_AXI_ACP_BREADY, + input S_AXI_ACP_RREADY, + input S_AXI_ACP_WLAST, + input S_AXI_ACP_WVALID, + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID, + input [2:0] S_AXI_ACP_ARPROT, + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID, + input [2:0] S_AXI_ACP_AWPROT, + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID, + input [31:0] S_AXI_ACP_ARADDR, + input [31:0] S_AXI_ACP_AWADDR, + input [3:0] S_AXI_ACP_ARCACHE, + input [3:0] S_AXI_ACP_ARLEN, + input [3:0] S_AXI_ACP_ARQOS, + input [3:0] S_AXI_ACP_AWCACHE, + input [3:0] S_AXI_ACP_AWLEN, + input [3:0] S_AXI_ACP_AWQOS, + input [1:0] S_AXI_ACP_ARBURST, + input [1:0] S_AXI_ACP_ARLOCK, + input [2:0] S_AXI_ACP_ARSIZE, + input [1:0] S_AXI_ACP_AWBURST, + input [1:0] S_AXI_ACP_AWLOCK, + input [2:0] S_AXI_ACP_AWSIZE, + input [4:0] S_AXI_ACP_ARUSER, + input [4:0] S_AXI_ACP_AWUSER, + input [63:0] S_AXI_ACP_WDATA, + input [7:0] S_AXI_ACP_WSTRB, + + // S_AXI_HP_0 + + // -- Output + output S_AXI_HP0_ARESETN, + output S_AXI_HP0_ARREADY, + output S_AXI_HP0_AWREADY, + output S_AXI_HP0_BVALID, + output S_AXI_HP0_RLAST, + output S_AXI_HP0_RVALID, + output S_AXI_HP0_WREADY, + output [1:0] S_AXI_HP0_BRESP, + output [1:0] S_AXI_HP0_RRESP, + output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID, + output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID, + output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA, + output [7:0] S_AXI_HP0_RCOUNT, + output [7:0] S_AXI_HP0_WCOUNT, + output [2:0] S_AXI_HP0_RACOUNT, + output [5:0] S_AXI_HP0_WACOUNT, + + // -- Input + input S_AXI_HP0_ACLK, + input S_AXI_HP0_ARVALID, + input S_AXI_HP0_AWVALID, + input S_AXI_HP0_BREADY, + input S_AXI_HP0_RDISSUECAP1_EN, + input S_AXI_HP0_RREADY, + input S_AXI_HP0_WLAST, + input S_AXI_HP0_WRISSUECAP1_EN, + input S_AXI_HP0_WVALID, + input [1:0] S_AXI_HP0_ARBURST, + input [1:0] S_AXI_HP0_ARLOCK, + input [2:0] S_AXI_HP0_ARSIZE, + input [1:0] S_AXI_HP0_AWBURST, + input [1:0] S_AXI_HP0_AWLOCK, + input [2:0] S_AXI_HP0_AWSIZE, + input [2:0] S_AXI_HP0_ARPROT, + input [2:0] S_AXI_HP0_AWPROT, + input [31:0] S_AXI_HP0_ARADDR, + input [31:0] S_AXI_HP0_AWADDR, + input [3:0] S_AXI_HP0_ARCACHE, + input [3:0] S_AXI_HP0_ARLEN, + input [3:0] S_AXI_HP0_ARQOS, + input [3:0] S_AXI_HP0_AWCACHE, + input [3:0] S_AXI_HP0_AWLEN, + input [3:0] S_AXI_HP0_AWQOS, + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID, + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID, + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID, + input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA, + input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB, + + // S_AXI_HP1 + // -- Output + output S_AXI_HP1_ARESETN, + output S_AXI_HP1_ARREADY, + output S_AXI_HP1_AWREADY, + output S_AXI_HP1_BVALID, + output S_AXI_HP1_RLAST, + output S_AXI_HP1_RVALID, + output S_AXI_HP1_WREADY, + output [1:0] S_AXI_HP1_BRESP, + output [1:0] S_AXI_HP1_RRESP, + output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID, + output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID, + output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA, + output [7:0] S_AXI_HP1_RCOUNT, + output [7:0] S_AXI_HP1_WCOUNT, + output [2:0] S_AXI_HP1_RACOUNT, + output [5:0] S_AXI_HP1_WACOUNT, + + + // -- Input + input S_AXI_HP1_ACLK, + input S_AXI_HP1_ARVALID, + input S_AXI_HP1_AWVALID, + input S_AXI_HP1_BREADY, + input S_AXI_HP1_RDISSUECAP1_EN, + input S_AXI_HP1_RREADY, + input S_AXI_HP1_WLAST, + input S_AXI_HP1_WRISSUECAP1_EN, + input S_AXI_HP1_WVALID, + input [1:0] S_AXI_HP1_ARBURST, + input [1:0] S_AXI_HP1_ARLOCK, + input [2:0] S_AXI_HP1_ARSIZE, + input [1:0] S_AXI_HP1_AWBURST, + input [1:0] S_AXI_HP1_AWLOCK, + input [2:0] S_AXI_HP1_AWSIZE, + input [2:0] S_AXI_HP1_ARPROT, + input [2:0] S_AXI_HP1_AWPROT, + input [31:0] S_AXI_HP1_ARADDR, + input [31:0] S_AXI_HP1_AWADDR, + input [3:0] S_AXI_HP1_ARCACHE, + input [3:0] S_AXI_HP1_ARLEN, + input [3:0] S_AXI_HP1_ARQOS, + input [3:0] S_AXI_HP1_AWCACHE, + input [3:0] S_AXI_HP1_AWLEN, + input [3:0] S_AXI_HP1_AWQOS, + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID, + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID, + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID, + input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA, + input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB, + + // S_AXI_HP2 + // -- Output + output S_AXI_HP2_ARESETN, + output S_AXI_HP2_ARREADY, + output S_AXI_HP2_AWREADY, + output S_AXI_HP2_BVALID, + output S_AXI_HP2_RLAST, + output S_AXI_HP2_RVALID, + output S_AXI_HP2_WREADY, + output [1:0] S_AXI_HP2_BRESP, + output [1:0] S_AXI_HP2_RRESP, + output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID, + output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID, + output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA, + output [7:0] S_AXI_HP2_RCOUNT, + output [7:0] S_AXI_HP2_WCOUNT, + output [2:0] S_AXI_HP2_RACOUNT, + output [5:0] S_AXI_HP2_WACOUNT, + + + // -- Input + input S_AXI_HP2_ACLK, + input S_AXI_HP2_ARVALID, + input S_AXI_HP2_AWVALID, + input S_AXI_HP2_BREADY, + input S_AXI_HP2_RDISSUECAP1_EN, + input S_AXI_HP2_RREADY, + input S_AXI_HP2_WLAST, + input S_AXI_HP2_WRISSUECAP1_EN, + input S_AXI_HP2_WVALID, + input [1:0] S_AXI_HP2_ARBURST, + input [1:0] S_AXI_HP2_ARLOCK, + input [2:0] S_AXI_HP2_ARSIZE, + input [1:0] S_AXI_HP2_AWBURST, + input [1:0] S_AXI_HP2_AWLOCK, + input [2:0] S_AXI_HP2_AWSIZE, + input [2:0] S_AXI_HP2_ARPROT, + input [2:0] S_AXI_HP2_AWPROT, + input [31:0] S_AXI_HP2_ARADDR, + input [31:0] S_AXI_HP2_AWADDR, + input [3:0] S_AXI_HP2_ARCACHE, + input [3:0] S_AXI_HP2_ARLEN, + input [3:0] S_AXI_HP2_ARQOS, + input [3:0] S_AXI_HP2_AWCACHE, + input [3:0] S_AXI_HP2_AWLEN, + input [3:0] S_AXI_HP2_AWQOS, + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID, + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID, + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID, + input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA, + input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB, + + // S_AXI_HP_3 + + // -- Output + output S_AXI_HP3_ARESETN, + output S_AXI_HP3_ARREADY, + output S_AXI_HP3_AWREADY, + output S_AXI_HP3_BVALID, + output S_AXI_HP3_RLAST, + output S_AXI_HP3_RVALID, + output S_AXI_HP3_WREADY, + output [1:0] S_AXI_HP3_BRESP, + output [1:0] S_AXI_HP3_RRESP, + output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID, + output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID, + output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA, + output [7:0] S_AXI_HP3_RCOUNT, + output [7:0] S_AXI_HP3_WCOUNT, + output [2:0] S_AXI_HP3_RACOUNT, + output [5:0] S_AXI_HP3_WACOUNT, + + + // -- Input + input S_AXI_HP3_ACLK, + input S_AXI_HP3_ARVALID, + input S_AXI_HP3_AWVALID, + input S_AXI_HP3_BREADY, + input S_AXI_HP3_RDISSUECAP1_EN, + input S_AXI_HP3_RREADY, + input S_AXI_HP3_WLAST, + input S_AXI_HP3_WRISSUECAP1_EN, + input S_AXI_HP3_WVALID, + input [1:0] S_AXI_HP3_ARBURST, + input [1:0] S_AXI_HP3_ARLOCK, + input [2:0] S_AXI_HP3_ARSIZE, + input [1:0] S_AXI_HP3_AWBURST, + input [1:0] S_AXI_HP3_AWLOCK, + input [2:0] S_AXI_HP3_AWSIZE, + input [2:0] S_AXI_HP3_ARPROT, + input [2:0] S_AXI_HP3_AWPROT, + input [31:0] S_AXI_HP3_ARADDR, + input [31:0] S_AXI_HP3_AWADDR, + input [3:0] S_AXI_HP3_ARCACHE, + input [3:0] S_AXI_HP3_ARLEN, + input [3:0] S_AXI_HP3_ARQOS, + input [3:0] S_AXI_HP3_AWCACHE, + input [3:0] S_AXI_HP3_AWLEN, + input [3:0] S_AXI_HP3_AWQOS, + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID, + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID, + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID, + input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA, + input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB, + + //FIO ======================================== + + //IRQ + //output [28:0] IRQ_P2F, + output IRQ_P2F_DMAC_ABORT , + output IRQ_P2F_DMAC0, + output IRQ_P2F_DMAC1, + output IRQ_P2F_DMAC2, + output IRQ_P2F_DMAC3, + output IRQ_P2F_DMAC4, + output IRQ_P2F_DMAC5, + output IRQ_P2F_DMAC6, + output IRQ_P2F_DMAC7, + output IRQ_P2F_SMC, + output IRQ_P2F_QSPI, + output IRQ_P2F_CTI, + output IRQ_P2F_GPIO, + output IRQ_P2F_USB0, + output IRQ_P2F_ENET0, + output IRQ_P2F_ENET_WAKE0, + output IRQ_P2F_SDIO0, + output IRQ_P2F_I2C0, + output IRQ_P2F_SPI0, + output IRQ_P2F_UART0, + output IRQ_P2F_CAN0, + output IRQ_P2F_USB1, + output IRQ_P2F_ENET1, + output IRQ_P2F_ENET_WAKE1, + output IRQ_P2F_SDIO1, + output IRQ_P2F_I2C1, + output IRQ_P2F_SPI1, + output IRQ_P2F_UART1, + output IRQ_P2F_CAN1, + input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P, + input Core0_nFIQ, + input Core0_nIRQ, + input Core1_nFIQ, + input Core1_nIRQ, + + //DMA + + output [1:0] DMA0_DATYPE, + output DMA0_DAVALID, + output DMA0_DRREADY, + output DMA0_RSTN, + output [1:0] DMA1_DATYPE, + output DMA1_DAVALID, + output DMA1_DRREADY, + output DMA1_RSTN, + output [1:0] DMA2_DATYPE, + output DMA2_DAVALID, + output DMA2_DRREADY, + output DMA2_RSTN, + output [1:0] DMA3_DATYPE, + output DMA3_DAVALID, + output DMA3_DRREADY, + output DMA3_RSTN, + input DMA0_ACLK, + input DMA0_DAREADY, + input DMA0_DRLAST, + input DMA0_DRVALID, + input DMA1_ACLK, + input DMA1_DAREADY, + input DMA1_DRLAST, + input DMA1_DRVALID, + input DMA2_ACLK, + input DMA2_DAREADY, + input DMA2_DRLAST, + input DMA2_DRVALID, + input DMA3_ACLK, + input DMA3_DAREADY, + input DMA3_DRLAST, + input DMA3_DRVALID, + input [1:0] DMA0_DRTYPE, + input [1:0] DMA1_DRTYPE, + input [1:0] DMA2_DRTYPE, + input [1:0] DMA3_DRTYPE, + + //FCLK + output FCLK_CLK3, + output FCLK_CLK2, + output FCLK_CLK1, + output FCLK_CLK0, + + input FCLK_CLKTRIG3_N, + input FCLK_CLKTRIG2_N, + input FCLK_CLKTRIG1_N, + input FCLK_CLKTRIG0_N, + + output FCLK_RESET3_N, + output FCLK_RESET2_N, + output FCLK_RESET1_N, + output FCLK_RESET0_N, + + //FTMD + input [31:0] FTMD_TRACEIN_DATA, + input FTMD_TRACEIN_VALID, + input FTMD_TRACEIN_CLK, + input [3:0] FTMD_TRACEIN_ATID, + + //FTMT + input FTMT_F2P_TRIG_0, + output FTMT_F2P_TRIGACK_0, + input FTMT_F2P_TRIG_1, + output FTMT_F2P_TRIGACK_1, + input FTMT_F2P_TRIG_2, + output FTMT_F2P_TRIGACK_2, + input FTMT_F2P_TRIG_3, + output FTMT_F2P_TRIGACK_3, + input [31:0] FTMT_F2P_DEBUG, + input FTMT_P2F_TRIGACK_0, + output FTMT_P2F_TRIG_0, + input FTMT_P2F_TRIGACK_1, + output FTMT_P2F_TRIG_1, + input FTMT_P2F_TRIGACK_2, + output FTMT_P2F_TRIG_2, + input FTMT_P2F_TRIGACK_3, + output FTMT_P2F_TRIG_3, + output [31:0] FTMT_P2F_DEBUG, + + //FIDLE + input FPGA_IDLE_N, + + //EVENT + + output EVENT_EVENTO, + output [1:0] EVENT_STANDBYWFE, + output [1:0] EVENT_STANDBYWFI, + input EVENT_EVENTI, + + + //DARB + input [3:0] DDR_ARB, + inout [C_MIO_PRIMITIVE - 1:0] MIO, + + //DDR + inout DDR_CAS_n, // CASB + inout DDR_CKE, // CKE + inout DDR_Clk_n, // CKN + inout DDR_Clk, // CKP + inout DDR_CS_n, // CSB + inout DDR_DRSTB, // DDR_DRSTB + inout DDR_ODT, // ODT + inout DDR_RAS_n, // RASB + inout DDR_WEB, + inout [2:0] DDR_BankAddr, // BA + inout [14:0] DDR_Addr, // A + + inout DDR_VRN, + inout DDR_VRP, + inout [C_DM_WIDTH - 1:0] DDR_DM, // DM + inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ + inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN + inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP + + inout PS_SRSTB, // SRSTB + inout PS_CLK, // CLK + inout PS_PORB // PORB + + +); + +wire [11:0] M_AXI_GP0_AWID_FULL; +wire [11:0] M_AXI_GP0_WID_FULL; +wire [11:0] M_AXI_GP0_ARID_FULL; + +wire [11:0] M_AXI_GP0_BID_FULL; +wire [11:0] M_AXI_GP0_RID_FULL; + +wire [11:0] M_AXI_GP1_AWID_FULL; +wire [11:0] M_AXI_GP1_WID_FULL; +wire [11:0] M_AXI_GP1_ARID_FULL; + +wire [11:0] M_AXI_GP1_BID_FULL; +wire [11:0] M_AXI_GP1_RID_FULL; + +wire [3:0] M_AXI_GP0_ARCACHE_t; +wire [3:0] M_AXI_GP1_ARCACHE_t; +wire [3:0] M_AXI_GP0_AWCACHE_t; +wire [3:0] M_AXI_GP1_AWCACHE_t; + + +// Wires for connecting to the PS7 +wire ENET0_GMII_TX_EN_i; +wire ENET0_GMII_TX_ER_i; +reg ENET0_GMII_COL_i; +reg ENET0_GMII_CRS_i; +reg ENET0_GMII_RX_DV_i; +reg ENET0_GMII_RX_ER_i; +reg [7:0] ENET0_GMII_RXD_i; +wire [7:0] ENET0_GMII_TXD_i; + +wire ENET1_GMII_TX_EN_i; +wire ENET1_GMII_TX_ER_i; +reg ENET1_GMII_COL_i; +reg ENET1_GMII_CRS_i; +reg ENET1_GMII_RX_DV_i; +reg ENET1_GMII_RX_ER_i; +reg [7:0] ENET1_GMII_RXD_i; +wire [7:0] ENET1_GMII_TXD_i; + +reg [31:0] FTMD_TRACEIN_DATA_notracebuf; +reg FTMD_TRACEIN_VALID_notracebuf; +reg [3:0] FTMD_TRACEIN_ATID_notracebuf; + +wire [31:0] FTMD_TRACEIN_DATA_i; +wire FTMD_TRACEIN_VALID_i; +wire [3:0] FTMD_TRACEIN_ATID_i; + +wire [31:0] FTMD_TRACEIN_DATA_tracebuf; +wire FTMD_TRACEIN_VALID_tracebuf; +wire [3:0] FTMD_TRACEIN_ATID_tracebuf; + +wire [5:0] S_AXI_GP0_BID_out; +wire [5:0] S_AXI_GP0_RID_out; +wire [5:0] S_AXI_GP0_ARID_in; +wire [5:0] S_AXI_GP0_AWID_in; +wire [5:0] S_AXI_GP0_WID_in; + +wire [5:0] S_AXI_GP1_BID_out; +wire [5:0] S_AXI_GP1_RID_out; +wire [5:0] S_AXI_GP1_ARID_in; +wire [5:0] S_AXI_GP1_AWID_in; +wire [5:0] S_AXI_GP1_WID_in; + +wire [5:0] S_AXI_HP0_BID_out; +wire [5:0] S_AXI_HP0_RID_out; +wire [5:0] S_AXI_HP0_ARID_in; +wire [5:0] S_AXI_HP0_AWID_in; +wire [5:0] S_AXI_HP0_WID_in; + +wire [5:0] S_AXI_HP1_BID_out; +wire [5:0] S_AXI_HP1_RID_out; +wire [5:0] S_AXI_HP1_ARID_in; +wire [5:0] S_AXI_HP1_AWID_in; +wire [5:0] S_AXI_HP1_WID_in; + +wire [5:0] S_AXI_HP2_BID_out; +wire [5:0] S_AXI_HP2_RID_out; +wire [5:0] S_AXI_HP2_ARID_in; +wire [5:0] S_AXI_HP2_AWID_in; +wire [5:0] S_AXI_HP2_WID_in; + +wire [5:0] S_AXI_HP3_BID_out; +wire [5:0] S_AXI_HP3_RID_out; +wire [5:0] S_AXI_HP3_ARID_in; +wire [5:0] S_AXI_HP3_AWID_in; +wire [5:0] S_AXI_HP3_WID_in; + +wire [2:0] S_AXI_ACP_BID_out; +wire [2:0] S_AXI_ACP_RID_out; +wire [2:0] S_AXI_ACP_ARID_in; +wire [2:0] S_AXI_ACP_AWID_in; +wire [2:0] S_AXI_ACP_WID_in; + +wire [63:0] S_AXI_HP0_WDATA_in; +wire [7:0] S_AXI_HP0_WSTRB_in; +wire [63:0] S_AXI_HP0_RDATA_out; + +wire [63:0] S_AXI_HP1_WDATA_in; +wire [7:0] S_AXI_HP1_WSTRB_in; +wire [63:0] S_AXI_HP1_RDATA_out; + +wire [63:0] S_AXI_HP2_WDATA_in; +wire [7:0] S_AXI_HP2_WSTRB_in; +wire [63:0] S_AXI_HP2_RDATA_out; + +wire [63:0] S_AXI_HP3_WDATA_in; +wire [7:0] S_AXI_HP3_WSTRB_in; +wire [63:0] S_AXI_HP3_RDATA_out; + +wire [1:0] M_AXI_GP0_ARSIZE_i; +wire [1:0] M_AXI_GP0_AWSIZE_i; + +wire [1:0] M_AXI_GP1_ARSIZE_i; +wire [1:0] M_AXI_GP1_AWSIZE_i; + +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W; + + +wire SAXIACPARREADY_W; +wire SAXIACPAWREADY_W; +wire SAXIACPBVALID_W; +wire SAXIACPRLAST_W; +wire SAXIACPRVALID_W; +wire SAXIACPWREADY_W; +wire [1:0] SAXIACPBRESP_W; +wire [1:0] SAXIACPRRESP_W; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID; +wire [63:0] SAXIACPRDATA_W; + +wire S_AXI_ATC_ARVALID; +wire S_AXI_ATC_AWVALID; +wire S_AXI_ATC_BREADY; +wire S_AXI_ATC_RREADY; +wire S_AXI_ATC_WLAST; +wire S_AXI_ATC_WVALID; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID; +wire [2:0] S_AXI_ATC_ARPROT; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID; +wire [2:0] S_AXI_ATC_AWPROT; +wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID; +wire [31:0] S_AXI_ATC_ARADDR; +wire [31:0] S_AXI_ATC_AWADDR; +wire [3:0] S_AXI_ATC_ARCACHE; +wire [3:0] S_AXI_ATC_ARLEN; +wire [3:0] S_AXI_ATC_ARQOS; +wire [3:0] S_AXI_ATC_AWCACHE; +wire [3:0] S_AXI_ATC_AWLEN; +wire [3:0] S_AXI_ATC_AWQOS; +wire [1:0] S_AXI_ATC_ARBURST; +wire [1:0] S_AXI_ATC_ARLOCK; +wire [2:0] S_AXI_ATC_ARSIZE; +wire [1:0] S_AXI_ATC_AWBURST; +wire [1:0] S_AXI_ATC_AWLOCK; +wire [2:0] S_AXI_ATC_AWSIZE; +wire [4:0] S_AXI_ATC_ARUSER; +wire [4:0] S_AXI_ATC_AWUSER; +wire [63:0] S_AXI_ATC_WDATA; +wire [7:0] S_AXI_ATC_WSTRB; + + +wire SAXIACPARVALID_W; +wire SAXIACPAWVALID_W; +wire SAXIACPBREADY_W; +wire SAXIACPRREADY_W; +wire SAXIACPWLAST_W; +wire SAXIACPWVALID_W; +wire [2:0] SAXIACPARPROT_W; +wire [2:0] SAXIACPAWPROT_W; +wire [31:0] SAXIACPARADDR_W; +wire [31:0] SAXIACPAWADDR_W; +wire [3:0] SAXIACPARCACHE_W; +wire [3:0] SAXIACPARLEN_W; +wire [3:0] SAXIACPARQOS_W; +wire [3:0] SAXIACPAWCACHE_W; +wire [3:0] SAXIACPAWLEN_W; +wire [3:0] SAXIACPAWQOS_W; +wire [1:0] SAXIACPARBURST_W; +wire [1:0] SAXIACPARLOCK_W; +wire [2:0] SAXIACPARSIZE_W; +wire [1:0] SAXIACPAWBURST_W; +wire [1:0] SAXIACPAWLOCK_W; +wire [2:0] SAXIACPAWSIZE_W; +wire [4:0] SAXIACPARUSER_W; +wire [4:0] SAXIACPAWUSER_W; +wire [63:0] SAXIACPWDATA_W; +wire [7:0] SAXIACPWSTRB_W; + +// AxUSER signal update +wire [4:0] param_aruser; +wire [4:0] param_awuser; + +// Added to address CR 651751 +wire [3:0] fclk_clktrig_gnd = 4'h0; + + +wire [19:0] irq_f2p_i; +wire [15:0] irq_f2p_null = 16'h0000; + +// EMIO I2C0 +wire I2C0_SDA_T_n; +wire I2C0_SCL_T_n; +// EMIO I2C1 +wire I2C1_SDA_T_n; +wire I2C1_SCL_T_n; +// EMIO SPI0 +wire SPI0_SCLK_T_n; +wire SPI0_MOSI_T_n; +wire SPI0_MISO_T_n; +wire SPI0_SS_T_n; +// EMIO SPI1 +wire SPI1_SCLK_T_n; +wire SPI1_MOSI_T_n; +wire SPI1_MISO_T_n; +wire SPI1_SS_T_n; + +// EMIO GEM0 +wire ENET0_MDIO_T_n; + +// EMIO GEM1 +wire ENET1_MDIO_T_n; + +// EMIO GPIO +wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n; + +wire [63:0] gpio_out_t_n; +wire [63:0] gpio_out; +wire [63:0] gpio_in63_0; + +//For Clock buffering +wire [3:0] FCLK_CLK_unbuffered; +wire [3:0] FCLK_CLK_buffered; +wire FCLK_CLK0_temp; + +// EMIO PJTAG +wire PJTAG_TDO_O; +wire PJTAG_TDO_T; +wire PJTAG_TDO_T_n; + +// EMIO SDIO0 +wire SDIO0_CMD_T_n; +wire [3:0] SDIO0_DATA_T_n; + +// EMIO SDIO1 +wire SDIO1_CMD_T_n; +wire [3:0] SDIO1_DATA_T_n; + +// buffered IO +wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO; +wire buffered_DDR_WEB; +wire buffered_DDR_CAS_n; +wire buffered_DDR_CKE; +wire buffered_DDR_Clk_n; +wire buffered_DDR_Clk; +wire buffered_DDR_CS_n; +wire buffered_DDR_DRSTB; +wire buffered_DDR_ODT; +wire buffered_DDR_RAS_n; +wire [2:0] buffered_DDR_BankAddr; +wire [14:0] buffered_DDR_Addr; + +wire buffered_DDR_VRN; +wire buffered_DDR_VRP; +wire [C_DM_WIDTH - 1:0] buffered_DDR_DM; +wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ; +wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n; +wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS; + +wire buffered_PS_SRSTB; +wire buffered_PS_CLK; +wire buffered_PS_PORB; + +wire S_AXI_HP0_ACLK_temp; +wire S_AXI_HP1_ACLK_temp; +wire S_AXI_HP2_ACLK_temp; +wire S_AXI_HP3_ACLK_temp; +wire M_AXI_GP0_ACLK_temp; +wire M_AXI_GP1_ACLK_temp; +wire S_AXI_GP0_ACLK_temp; +wire S_AXI_GP1_ACLK_temp; +wire S_AXI_ACP_ACLK_temp; + +wire [31:0] TRACE_DATA_i; +wire TRACE_CTL_i; +(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0]; +(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0]; + +// fixed CR #665394 +integer j; +generate + if (C_EN_EMIO_TRACE == 1) begin + always @(posedge TRACE_CLK) + begin + TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i; + TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0]; + for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin + TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j]; + TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j]; + end + TRACE_CLK_OUT <= ~TRACE_CLK_OUT; + end + end +else +begin +always @* +begin +TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0; + TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0; + for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin + TRACE_CTL_PIPE[j-1] <= 1'b0; + TRACE_DATA_PIPE[j-1] <= 1'b0; + end + TRACE_CLK_OUT <= 1'b0; + end +end +endgenerate + +assign TRACE_CTL = TRACE_CTL_PIPE[0]; + +assign TRACE_DATA = TRACE_DATA_PIPE[0]; + +//irq_p2f + +// Updated IRQ_F2P logic to address CR 641523 +generate + if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null + assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]}; + end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all + assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]}; + end else begin : irq_f2p_select + if (C_IRQ_F2P_MODE == "DIRECT") begin + assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, + irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0], + IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]}; + end else begin + assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ, + IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0], + irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]}; + end + end +endgenerate + +assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]}; +assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]}; +assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]}; +assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]}; + + + +// Compress Function + + +// Modified as per CR 631955 +//function [11:0] uncompress_id; +// input [5:0] id; +// begin +// case (id[5:0]) +// // dmac0 +// 6'd1 : uncompress_id = 12'b010000_1000_00 ; +// 6'd2 : uncompress_id = 12'b010000_0000_00 ; +// 6'd3 : uncompress_id = 12'b010000_0001_00 ; +// 6'd4 : uncompress_id = 12'b010000_0010_00 ; +// 6'd5 : uncompress_id = 12'b010000_0011_00 ; +// 6'd6 : uncompress_id = 12'b010000_0100_00 ; +// 6'd7 : uncompress_id = 12'b010000_0101_00 ; +// 6'd8 : uncompress_id = 12'b010000_0110_00 ; +// 6'd9 : uncompress_id = 12'b010000_0111_00 ; +// // ioum +// 6'd10 : uncompress_id = 12'b0100000_000_01 ; +// 6'd11 : uncompress_id = 12'b0100000_001_01 ; +// 6'd12 : uncompress_id = 12'b0100000_010_01 ; +// 6'd13 : uncompress_id = 12'b0100000_011_01 ; +// 6'd14 : uncompress_id = 12'b0100000_100_01 ; +// 6'd15 : uncompress_id = 12'b0100000_101_01 ; +// // devci +// 6'd16 : uncompress_id = 12'b1000_0000_0000 ; +// // dap +// 6'd17 : uncompress_id = 12'b1000_0000_0001 ; +// // l2m1 (CPU000) +// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ; +// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ; +// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ; +// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ; +// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ; +// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ; +// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ; +// // l2m1 (CPU001) +// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ; +// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ; +// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ; +// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ; +// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ; +// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ; +// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ; +// // l2m1 (L2CC) +// 6'd32 : uncompress_id = 12'b11_000_00101_00 ; +// 6'd33 : uncompress_id = 12'b11_000_01001_00 ; +// 6'd34 : uncompress_id = 12'b11_000_01101_00 ; +// 6'd35 : uncompress_id = 12'b11_000_10011_00 ; +// 6'd36 : uncompress_id = 12'b11_000_10111_00 ; +// 6'd37 : uncompress_id = 12'b11_000_11011_00 ; +// 6'd38 : uncompress_id = 12'b11_000_11111_00 ; +// 6'd39 : uncompress_id = 12'b11_000_00011_00 ; +// 6'd40 : uncompress_id = 12'b11_000_00111_00 ; +// 6'd41 : uncompress_id = 12'b11_000_01011_00 ; +// 6'd42 : uncompress_id = 12'b11_000_01111_00 ; +// 6'd43 : uncompress_id = 12'b11_000_00001_00 ; +// // l2m1 (ACP) +// 6'd44 : uncompress_id = 12'b11_000_10000_00 ; +// 6'd45 : uncompress_id = 12'b11_001_10000_00 ; +// 6'd46 : uncompress_id = 12'b11_010_10000_00 ; +// 6'd47 : uncompress_id = 12'b11_011_10000_00 ; +// 6'd48 : uncompress_id = 12'b11_100_10000_00 ; +// 6'd49 : uncompress_id = 12'b11_101_10000_00 ; +// 6'd50 : uncompress_id = 12'b11_110_10000_00 ; +// 6'd51 : uncompress_id = 12'b11_111_10000_00 ; +// default : uncompress_id = ~0; +// endcase +// end +//endfunction +// +//function [5:0] compress_id; +// input [11:0] id; +// begin +// case (id[11:0]) +// // dmac0 +// 12'b010000_1000_00 : compress_id = 'd1 ; +// 12'b010000_0000_00 : compress_id = 'd2 ; +// 12'b010000_0001_00 : compress_id = 'd3 ; +// 12'b010000_0010_00 : compress_id = 'd4 ; +// 12'b010000_0011_00 : compress_id = 'd5 ; +// 12'b010000_0100_00 : compress_id = 'd6 ; +// 12'b010000_0101_00 : compress_id = 'd7 ; +// 12'b010000_0110_00 : compress_id = 'd8 ; +// 12'b010000_0111_00 : compress_id = 'd9 ; +// // ioum +// 12'b0100000_000_01 : compress_id = 'd10 ; +// 12'b0100000_001_01 : compress_id = 'd11 ; +// 12'b0100000_010_01 : compress_id = 'd12 ; +// 12'b0100000_011_01 : compress_id = 'd13 ; +// 12'b0100000_100_01 : compress_id = 'd14 ; +// 12'b0100000_101_01 : compress_id = 'd15 ; +// // devci +// 12'b1000_0000_0000 : compress_id = 'd16 ; +// // dap +// 12'b1000_0000_0001 : compress_id = 'd17 ; +// // l2m1 (CPU000) +// 12'b11_000_000_00_00 : compress_id = 'd18 ; +// 12'b11_010_000_00_00 : compress_id = 'd19 ; +// 12'b11_011_000_00_00 : compress_id = 'd20 ; +// 12'b11_100_000_00_00 : compress_id = 'd21 ; +// 12'b11_101_000_00_00 : compress_id = 'd22 ; +// 12'b11_110_000_00_00 : compress_id = 'd23 ; +// 12'b11_111_000_00_00 : compress_id = 'd24 ; +// // l2m1 (CPU001) +// 12'b11_000_001_00_00 : compress_id = 'd25 ; +// 12'b11_010_001_00_00 : compress_id = 'd26 ; +// 12'b11_011_001_00_00 : compress_id = 'd27 ; +// 12'b11_100_001_00_00 : compress_id = 'd28 ; +// 12'b11_101_001_00_00 : compress_id = 'd29 ; +// 12'b11_110_001_00_00 : compress_id = 'd30 ; +// 12'b11_111_001_00_00 : compress_id = 'd31 ; +// // l2m1 (L2CC) +// 12'b11_000_00101_00 : compress_id = 'd32 ; +// 12'b11_000_01001_00 : compress_id = 'd33 ; +// 12'b11_000_01101_00 : compress_id = 'd34 ; +// 12'b11_000_10011_00 : compress_id = 'd35 ; +// 12'b11_000_10111_00 : compress_id = 'd36 ; +// 12'b11_000_11011_00 : compress_id = 'd37 ; +// 12'b11_000_11111_00 : compress_id = 'd38 ; +// 12'b11_000_00011_00 : compress_id = 'd39 ; +// 12'b11_000_00111_00 : compress_id = 'd40 ; +// 12'b11_000_01011_00 : compress_id = 'd41 ; +// 12'b11_000_01111_00 : compress_id = 'd42 ; +// 12'b11_000_00001_00 : compress_id = 'd43 ; +// // l2m1 (ACP) +// 12'b11_000_10000_00 : compress_id = 'd44 ; +// 12'b11_001_10000_00 : compress_id = 'd45 ; +// 12'b11_010_10000_00 : compress_id = 'd46 ; +// 12'b11_011_10000_00 : compress_id = 'd47 ; +// 12'b11_100_10000_00 : compress_id = 'd48 ; +// 12'b11_101_10000_00 : compress_id = 'd49 ; +// 12'b11_110_10000_00 : compress_id = 'd50 ; +// 12'b11_111_10000_00 : compress_id = 'd51 ; +// default: compress_id = ~0; +// endcase +// end +//endfunction + +// Modified as per CR 648393 + + function [5:0] compress_id; + input [11:0] id; + begin + compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]); + compress_id[1] = id[8] | id[5] | (~id[11] & id[3]); + compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]); + compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]); + compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]); + compress_id[5] = id[11] & id[10] & ~id[3]; + end + endfunction + + function [11:0] uncompress_id; + input [5:0] id; + begin + case (id[5:0]) + // dmac0 + 6'b000_010 : uncompress_id = 12'b010000_1000_00 ; + 6'b001_000 : uncompress_id = 12'b010000_0000_00 ; + 6'b001_001 : uncompress_id = 12'b010000_0001_00 ; + 6'b001_010 : uncompress_id = 12'b010000_0010_00 ; + 6'b001_011 : uncompress_id = 12'b010000_0011_00 ; + 6'b001_100 : uncompress_id = 12'b010000_0100_00 ; + 6'b001_101 : uncompress_id = 12'b010000_0101_00 ; + 6'b001_110 : uncompress_id = 12'b010000_0110_00 ; + 6'b001_111 : uncompress_id = 12'b010000_0111_00 ; + // ioum + 6'b010_000 : uncompress_id = 12'b0100000_000_01 ; + 6'b010_001 : uncompress_id = 12'b0100000_001_01 ; + 6'b010_010 : uncompress_id = 12'b0100000_010_01 ; + 6'b010_011 : uncompress_id = 12'b0100000_011_01 ; + 6'b010_100 : uncompress_id = 12'b0100000_100_01 ; + 6'b010_101 : uncompress_id = 12'b0100000_101_01 ; + // devci + 6'b000_000 : uncompress_id = 12'b1000_0000_0000 ; + // dap + 6'b000_001 : uncompress_id = 12'b1000_0000_0001 ; + // l2m1 (CPU000) + 6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ; + 6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ; + 6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ; + 6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ; + 6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ; + 6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ; + 6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ; + // l2m1 (CPU001) + 6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ; + 6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ; + 6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ; + 6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ; + 6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ; + 6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ; + 6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ; + // l2m1 (L2CC) + 6'b101_001 : uncompress_id = 12'b11_000_00101_00 ; + 6'b101_010 : uncompress_id = 12'b11_000_01001_00 ; + 6'b101_011 : uncompress_id = 12'b11_000_01101_00 ; + 6'b011_100 : uncompress_id = 12'b11_000_10011_00 ; + 6'b011_101 : uncompress_id = 12'b11_000_10111_00 ; + 6'b011_110 : uncompress_id = 12'b11_000_11011_00 ; + 6'b011_111 : uncompress_id = 12'b11_000_11111_00 ; + 6'b011_000 : uncompress_id = 12'b11_000_00011_00 ; + 6'b011_001 : uncompress_id = 12'b11_000_00111_00 ; + 6'b011_010 : uncompress_id = 12'b11_000_01011_00 ; + 6'b011_011 : uncompress_id = 12'b11_000_01111_00 ; + 6'b101_000 : uncompress_id = 12'b11_000_00001_00 ; + // l2m1 (ACP) + 6'b100_000 : uncompress_id = 12'b11_000_10000_00 ; + 6'b100_001 : uncompress_id = 12'b11_001_10000_00 ; + 6'b100_010 : uncompress_id = 12'b11_010_10000_00 ; + 6'b100_011 : uncompress_id = 12'b11_011_10000_00 ; + 6'b100_100 : uncompress_id = 12'b11_100_10000_00 ; + 6'b100_101 : uncompress_id = 12'b11_101_10000_00 ; + 6'b100_110 : uncompress_id = 12'b11_110_10000_00 ; + 6'b100_111 : uncompress_id = 12'b11_111_10000_00 ; + default : uncompress_id = 12'hx ; + endcase + end + endfunction + + +// Static Remap logic Enablement and Disablement for C_M_AXI0 port + + assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL; + assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL; + assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL; + assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID; + assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID; + + // Static Remap logic Enablement and Disablement for C_M_AXI1 port + + assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL; + assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL; + assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL; + assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID; + assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID; + + +//// Compress_id and uncompress_id has been removed to address CR 642527 +//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression. +// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL; +// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL; +// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL; +// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID; +// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID; +// +// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL; +// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL; +// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL; +// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID; +// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID; + + +// Pipeline Stage for ENET0 + +generate + if (C_EN_EMIO_ENET0 == 1) begin + always @(posedge ENET0_GMII_TX_CLK) + begin + ENET0_GMII_TXD <= ENET0_GMII_TXD_i; + ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; + ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; + ENET0_GMII_COL_i <= ENET0_GMII_COL; + ENET0_GMII_CRS_i <= ENET0_GMII_CRS; + end + end + else + always@* + begin + ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i; + ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; + ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; + ENET0_GMII_COL_i <= 'b0; + ENET0_GMII_CRS_i <= 'b0; + end +endgenerate + +generate + if (C_EN_EMIO_ENET0 == 1) begin + always @(posedge ENET0_GMII_RX_CLK) + begin + ENET0_GMII_RXD_i <= ENET0_GMII_RXD; + ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV; + ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER; + end + end + else + begin + always @* + begin + ENET0_GMII_RXD_i <= 0; + ENET0_GMII_RX_DV_i <= 0; + ENET0_GMII_RX_ER_i <= 0; + end + end +endgenerate + +// Pipeline Stage for ENET1 + +generate + if (C_EN_EMIO_ENET1 == 1) begin + always @(posedge ENET1_GMII_TX_CLK) + begin + ENET1_GMII_TXD <= ENET1_GMII_TXD_i; + ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i; + ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i; + ENET1_GMII_COL_i <= ENET1_GMII_COL; + ENET1_GMII_CRS_i <= ENET1_GMII_CRS; + end + end + else + begin + always@* + begin + ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i; + ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i; + ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i; + ENET1_GMII_COL_i <= 0; + ENET1_GMII_CRS_i <= 0; + end + end +endgenerate + +generate + if (C_EN_EMIO_ENET1 == 1) begin + always @(posedge ENET1_GMII_RX_CLK) + begin + ENET1_GMII_RXD_i <= ENET1_GMII_RXD; + ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV; + ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER; + end + end +else + begin + always @* + begin + ENET1_GMII_RXD_i <= 'b0; + ENET1_GMII_RX_DV_i <= 'b0; + ENET1_GMII_RX_ER_i <= 'b0; + end + end +endgenerate + +// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1. + +generate + if (C_EN_EMIO_TRACE == 1) begin + if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer + + // Pipeline Stage for Traceport ATID + always @(posedge FTMD_TRACEIN_CLK) + begin + FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA; + FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID; + FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID; + end + + assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf; + assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf; + assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf; + + end else begin : gen_trace_buffer + + processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE), + .USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR), + .C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY) + ) + trace_buffer_i ( + .TRACE_CLK(FTMD_TRACEIN_CLK), + .RST(~FCLK_RESET0_N), + .TRACE_VALID_IN(FTMD_TRACEIN_VALID), + .TRACE_DATA_IN(FTMD_TRACEIN_DATA), + .TRACE_ATID_IN(FTMD_TRACEIN_ATID), + .TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf), + .TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf), + .TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf) + ); + + assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf; + assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf; + assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf; + + end + end + else + begin + assign FTMD_TRACEIN_DATA_i = 1'b0; + assign FTMD_TRACEIN_VALID_i = 1'b0; + assign FTMD_TRACEIN_ATID_i = 1'b0; + end +endgenerate + + + // ID Width Control on AXI Slave ports + // S_AXI_GP0 + + function [5:0] id_in_gp0; + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in; + begin + case (C_S_AXI_GP0_ID_WIDTH) + 1: id_in_gp0 = {5'b0, axi_id_gp0_in}; + 2: id_in_gp0 = {4'b0, axi_id_gp0_in}; + 3: id_in_gp0 = {3'b0, axi_id_gp0_in}; + 4: id_in_gp0 = {2'b0, axi_id_gp0_in}; + 5: id_in_gp0 = {1'b0, axi_id_gp0_in}; + 6: id_in_gp0 = axi_id_gp0_in; + default : id_in_gp0 = axi_id_gp0_in; + endcase + end + endfunction + + assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID); + assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID); + assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID); + + function [5:0] id_out_gp0; + input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out; + begin + case (C_S_AXI_GP0_ID_WIDTH) + 1: id_out_gp0 = axi_id_gp0_out[0]; + 2: id_out_gp0 = axi_id_gp0_out[1:0]; + 3: id_out_gp0 = axi_id_gp0_out[2:0]; + 4: id_out_gp0 = axi_id_gp0_out[3:0]; + 5: id_out_gp0 = axi_id_gp0_out[4:0]; + 6: id_out_gp0 = axi_id_gp0_out; + default : id_out_gp0 = axi_id_gp0_out; + endcase + end + endfunction + + assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out); + assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out); + + // S_AXI_GP1 + + function [5:0] id_in_gp1; + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in; + begin + case (C_S_AXI_GP1_ID_WIDTH) + 1: id_in_gp1 = {5'b0, axi_id_gp1_in}; + 2: id_in_gp1 = {4'b0, axi_id_gp1_in}; + 3: id_in_gp1 = {3'b0, axi_id_gp1_in}; + 4: id_in_gp1 = {2'b0, axi_id_gp1_in}; + 5: id_in_gp1 = {1'b0, axi_id_gp1_in}; + 6: id_in_gp1 = axi_id_gp1_in; + default : id_in_gp1 = axi_id_gp1_in; + endcase + end + endfunction + + assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID); + assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID); + assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID); + + function [5:0] id_out_gp1; + input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out; + begin + case (C_S_AXI_GP1_ID_WIDTH) + 1: id_out_gp1 = axi_id_gp1_out[0]; + 2: id_out_gp1 = axi_id_gp1_out[1:0]; + 3: id_out_gp1 = axi_id_gp1_out[2:0]; + 4: id_out_gp1 = axi_id_gp1_out[3:0]; + 5: id_out_gp1 = axi_id_gp1_out[4:0]; + 6: id_out_gp1 = axi_id_gp1_out; + default : id_out_gp1 = axi_id_gp1_out; + endcase + end + endfunction + + assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out); + assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out); + +// S_AXI_HP0 + + function [5:0] id_in_hp0; + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in; + begin + case (C_S_AXI_HP0_ID_WIDTH) + 1: id_in_hp0 = {5'b0, axi_id_hp0_in}; + 2: id_in_hp0 = {4'b0, axi_id_hp0_in}; + 3: id_in_hp0 = {3'b0, axi_id_hp0_in}; + 4: id_in_hp0 = {2'b0, axi_id_hp0_in}; + 5: id_in_hp0 = {1'b0, axi_id_hp0_in}; + 6: id_in_hp0 = axi_id_hp0_in; + default : id_in_hp0 = axi_id_hp0_in; + endcase + end + endfunction + + assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID); + assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID); + assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID); + + function [5:0] id_out_hp0; + input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out; + begin + case (C_S_AXI_HP0_ID_WIDTH) + 1: id_out_hp0 = axi_id_hp0_out[0]; + 2: id_out_hp0 = axi_id_hp0_out[1:0]; + 3: id_out_hp0 = axi_id_hp0_out[2:0]; + 4: id_out_hp0 = axi_id_hp0_out[3:0]; + 5: id_out_hp0 = axi_id_hp0_out[4:0]; + 6: id_out_hp0 = axi_id_hp0_out; + default : id_out_hp0 = axi_id_hp0_out; + endcase + end + endfunction + + assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out); + assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out); + + assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA}; + assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB}; + assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0]; + +// S_AXI_HP1 + + function [5:0] id_in_hp1; + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in; + begin + case (C_S_AXI_HP1_ID_WIDTH) + 1: id_in_hp1 = {5'b0, axi_id_hp1_in}; + 2: id_in_hp1 = {4'b0, axi_id_hp1_in}; + 3: id_in_hp1 = {3'b0, axi_id_hp1_in}; + 4: id_in_hp1 = {2'b0, axi_id_hp1_in}; + 5: id_in_hp1 = {1'b0, axi_id_hp1_in}; + 6: id_in_hp1 = axi_id_hp1_in; + default : id_in_hp1 = axi_id_hp1_in; + endcase + end + endfunction + + + + assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID); + assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID); + assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID); + + function [5:0] id_out_hp1; + input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out; + begin + case (C_S_AXI_HP1_ID_WIDTH) + 1: id_out_hp1 = axi_id_hp1_out[0]; + 2: id_out_hp1 = axi_id_hp1_out[1:0]; + 3: id_out_hp1 = axi_id_hp1_out[2:0]; + 4: id_out_hp1 = axi_id_hp1_out[3:0]; + 5: id_out_hp1 = axi_id_hp1_out[4:0]; + 6: id_out_hp1 = axi_id_hp1_out; + default : id_out_hp1 = axi_id_hp1_out; + endcase + end + endfunction + + assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out); + assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out); + + assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA}; + assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB}; + assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0]; + + +// S_AXI_HP2 + + function [5:0] id_in_hp2; + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in; + begin + case (C_S_AXI_HP2_ID_WIDTH) + 1: id_in_hp2 = {5'b0, axi_id_hp2_in}; + 2: id_in_hp2 = {4'b0, axi_id_hp2_in}; + 3: id_in_hp2 = {3'b0, axi_id_hp2_in}; + 4: id_in_hp2 = {2'b0, axi_id_hp2_in}; + 5: id_in_hp2 = {1'b0, axi_id_hp2_in}; + 6: id_in_hp2 = axi_id_hp2_in; + default : id_in_hp2 = axi_id_hp2_in; + endcase + end + endfunction + + assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID); + assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID); + assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID); + + + function [5:0] id_out_hp2; + input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out; + begin + case (C_S_AXI_HP2_ID_WIDTH) + 1: id_out_hp2 = axi_id_hp2_out[0]; + 2: id_out_hp2 = axi_id_hp2_out[1:0]; + 3: id_out_hp2 = axi_id_hp2_out[2:0]; + 4: id_out_hp2 = axi_id_hp2_out[3:0]; + 5: id_out_hp2 = axi_id_hp2_out[4:0]; + 6: id_out_hp2 = axi_id_hp2_out; + default : id_out_hp2 = axi_id_hp2_out; + endcase + end + endfunction + + assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out); + assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out); + + assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA}; + assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB}; + assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0]; + + +// S_AXI_HP3 + + function [5:0] id_in_hp3; + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in; + begin + case (C_S_AXI_HP3_ID_WIDTH) + 1: id_in_hp3 = {5'b0, axi_id_hp3_in}; + 2: id_in_hp3 = {4'b0, axi_id_hp3_in}; + 3: id_in_hp3 = {3'b0, axi_id_hp3_in}; + 4: id_in_hp3 = {2'b0, axi_id_hp3_in}; + 5: id_in_hp3 = {1'b0, axi_id_hp3_in}; + 6: id_in_hp3 = axi_id_hp3_in; + default : id_in_hp3 = axi_id_hp3_in; + endcase + end + endfunction + + assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID); + assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID); + assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID); + + + + function [5:0] id_out_hp3; + input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out; + begin + case (C_S_AXI_HP3_ID_WIDTH) + 1: id_out_hp3 = axi_id_hp3_out[0]; + 2: id_out_hp3 = axi_id_hp3_out[1:0]; + 3: id_out_hp3 = axi_id_hp3_out[2:0]; + 4: id_out_hp3 = axi_id_hp3_out[3:0]; + 5: id_out_hp3 = axi_id_hp3_out[4:0]; + 6: id_out_hp3 = axi_id_hp3_out; + default : id_out_hp3 = axi_id_hp3_out; + endcase + end + endfunction + + assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out); + assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out); + + assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA}; + assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB}; + assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0]; + + +// S_AXI_ACP + + function [2:0] id_in_acp; + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in; + begin + case (C_S_AXI_ACP_ID_WIDTH) + 1: id_in_acp = {2'b0, axi_id_acp_in}; + 2: id_in_acp = {1'b0, axi_id_acp_in}; + 3: id_in_acp = axi_id_acp_in; + default : id_in_acp = axi_id_acp_in; + endcase + end + endfunction + + assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W); + assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W); + assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W); + + function [2:0] id_out_acp; + input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out; + begin + case (C_S_AXI_ACP_ID_WIDTH) + 1: id_out_acp = axi_id_acp_out[0]; + 2: id_out_acp = axi_id_acp_out[1:0]; + 3: id_out_acp = axi_id_acp_out; + default : id_out_acp = axi_id_acp_out; + endcase + end + endfunction + + assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out); + assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out); + +// FMIO Tristate Inversion logic + +//FMIO I2C0 +assign I2C0_SDA_T = ~ I2C0_SDA_T_n; +assign I2C0_SCL_T = ~ I2C0_SCL_T_n; +//FMIO I2C1 +assign I2C1_SDA_T = ~ I2C1_SDA_T_n; +assign I2C1_SCL_T = ~ I2C1_SCL_T_n; +//FMIO SPI0 +assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n; +assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n; +assign SPI0_MISO_T = ~ SPI0_MISO_T_n; +assign SPI0_SS_T = ~ SPI0_SS_T_n; +//FMIO SPI1 +assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n; +assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n; +assign SPI1_MISO_T = ~ SPI1_MISO_T_n; +assign SPI1_SS_T = ~ SPI1_SS_T_n; + + + +// EMIO GEM0 MDIO +assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n; + +// EMIO GEM1 MDIO +assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n; + +// EMIO GPIO +assign GPIO_T = ~ GPIO_T_n; + +// EMIO GPIO Width Control + + function [63:0] gpio_width_adjust_in; + input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in; + begin + case (C_EMIO_GPIO_WIDTH) + 1: gpio_width_adjust_in = {63'b0, gpio_in}; + 2: gpio_width_adjust_in = {62'b0, gpio_in}; + 3: gpio_width_adjust_in = {61'b0, gpio_in}; + 4: gpio_width_adjust_in = {60'b0, gpio_in}; + 5: gpio_width_adjust_in = {59'b0, gpio_in}; + 6: gpio_width_adjust_in = {58'b0, gpio_in}; + 7: gpio_width_adjust_in = {57'b0, gpio_in}; + 8: gpio_width_adjust_in = {56'b0, gpio_in}; + 9: gpio_width_adjust_in = {55'b0, gpio_in}; + 10: gpio_width_adjust_in = {54'b0, gpio_in}; + 11: gpio_width_adjust_in = {53'b0, gpio_in}; + 12: gpio_width_adjust_in = {52'b0, gpio_in}; + 13: gpio_width_adjust_in = {51'b0, gpio_in}; + 14: gpio_width_adjust_in = {50'b0, gpio_in}; + 15: gpio_width_adjust_in = {49'b0, gpio_in}; + 16: gpio_width_adjust_in = {48'b0, gpio_in}; + 17: gpio_width_adjust_in = {47'b0, gpio_in}; + 18: gpio_width_adjust_in = {46'b0, gpio_in}; + 19: gpio_width_adjust_in = {45'b0, gpio_in}; + 20: gpio_width_adjust_in = {44'b0, gpio_in}; + 21: gpio_width_adjust_in = {43'b0, gpio_in}; + 22: gpio_width_adjust_in = {42'b0, gpio_in}; + 23: gpio_width_adjust_in = {41'b0, gpio_in}; + 24: gpio_width_adjust_in = {40'b0, gpio_in}; + 25: gpio_width_adjust_in = {39'b0, gpio_in}; + 26: gpio_width_adjust_in = {38'b0, gpio_in}; + 27: gpio_width_adjust_in = {37'b0, gpio_in}; + 28: gpio_width_adjust_in = {36'b0, gpio_in}; + 29: gpio_width_adjust_in = {35'b0, gpio_in}; + 30: gpio_width_adjust_in = {34'b0, gpio_in}; + 31: gpio_width_adjust_in = {33'b0, gpio_in}; + 32: gpio_width_adjust_in = {32'b0, gpio_in}; + 33: gpio_width_adjust_in = {31'b0, gpio_in}; + 34: gpio_width_adjust_in = {30'b0, gpio_in}; + 35: gpio_width_adjust_in = {29'b0, gpio_in}; + 36: gpio_width_adjust_in = {28'b0, gpio_in}; + 37: gpio_width_adjust_in = {27'b0, gpio_in}; + 38: gpio_width_adjust_in = {26'b0, gpio_in}; + 39: gpio_width_adjust_in = {25'b0, gpio_in}; + 40: gpio_width_adjust_in = {24'b0, gpio_in}; + 41: gpio_width_adjust_in = {23'b0, gpio_in}; + 42: gpio_width_adjust_in = {22'b0, gpio_in}; + 43: gpio_width_adjust_in = {21'b0, gpio_in}; + 44: gpio_width_adjust_in = {20'b0, gpio_in}; + 45: gpio_width_adjust_in = {19'b0, gpio_in}; + 46: gpio_width_adjust_in = {18'b0, gpio_in}; + 47: gpio_width_adjust_in = {17'b0, gpio_in}; + 48: gpio_width_adjust_in = {16'b0, gpio_in}; + 49: gpio_width_adjust_in = {15'b0, gpio_in}; + 50: gpio_width_adjust_in = {14'b0, gpio_in}; + 51: gpio_width_adjust_in = {13'b0, gpio_in}; + 52: gpio_width_adjust_in = {12'b0, gpio_in}; + 53: gpio_width_adjust_in = {11'b0, gpio_in}; + 54: gpio_width_adjust_in = {10'b0, gpio_in}; + 55: gpio_width_adjust_in = {9'b0, gpio_in}; + 56: gpio_width_adjust_in = {8'b0, gpio_in}; + 57: gpio_width_adjust_in = {7'b0, gpio_in}; + 58: gpio_width_adjust_in = {6'b0, gpio_in}; + 59: gpio_width_adjust_in = {5'b0, gpio_in}; + 60: gpio_width_adjust_in = {4'b0, gpio_in}; + 61: gpio_width_adjust_in = {3'b0, gpio_in}; + 62: gpio_width_adjust_in = {2'b0, gpio_in}; + 63: gpio_width_adjust_in = {1'b0, gpio_in}; + 64: gpio_width_adjust_in = gpio_in; + default : gpio_width_adjust_in = gpio_in; + endcase + end + endfunction + + assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I); + + + function [63:0] gpio_width_adjust_out; + input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o; + begin + case (C_EMIO_GPIO_WIDTH) + 1: gpio_width_adjust_out = gpio_o[0]; + 2: gpio_width_adjust_out = gpio_o[1:0]; + 3: gpio_width_adjust_out = gpio_o[2:0]; + 4: gpio_width_adjust_out = gpio_o[3:0]; + 5: gpio_width_adjust_out = gpio_o[4:0]; + 6: gpio_width_adjust_out = gpio_o[5:0]; + 7: gpio_width_adjust_out = gpio_o[6:0]; + 8: gpio_width_adjust_out = gpio_o[7:0]; + 9: gpio_width_adjust_out = gpio_o[8:0]; + 10: gpio_width_adjust_out = gpio_o[9:0]; + 11: gpio_width_adjust_out = gpio_o[10:0]; + 12: gpio_width_adjust_out = gpio_o[11:0]; + 13: gpio_width_adjust_out = gpio_o[12:0]; + 14: gpio_width_adjust_out = gpio_o[13:0]; + 15: gpio_width_adjust_out = gpio_o[14:0]; + 16: gpio_width_adjust_out = gpio_o[15:0]; + 17: gpio_width_adjust_out = gpio_o[16:0]; + 18: gpio_width_adjust_out = gpio_o[17:0]; + 19: gpio_width_adjust_out = gpio_o[18:0]; + 20: gpio_width_adjust_out = gpio_o[19:0]; + 21: gpio_width_adjust_out = gpio_o[20:0]; + 22: gpio_width_adjust_out = gpio_o[21:0]; + 23: gpio_width_adjust_out = gpio_o[22:0]; + 24: gpio_width_adjust_out = gpio_o[23:0]; + 25: gpio_width_adjust_out = gpio_o[24:0]; + 26: gpio_width_adjust_out = gpio_o[25:0]; + 27: gpio_width_adjust_out = gpio_o[26:0]; + 28: gpio_width_adjust_out = gpio_o[27:0]; + 29: gpio_width_adjust_out = gpio_o[28:0]; + 30: gpio_width_adjust_out = gpio_o[29:0]; + 31: gpio_width_adjust_out = gpio_o[30:0]; + 32: gpio_width_adjust_out = gpio_o[31:0]; + 33: gpio_width_adjust_out = gpio_o[32:0]; + 34: gpio_width_adjust_out = gpio_o[33:0]; + 35: gpio_width_adjust_out = gpio_o[34:0]; + 36: gpio_width_adjust_out = gpio_o[35:0]; + 37: gpio_width_adjust_out = gpio_o[36:0]; + 38: gpio_width_adjust_out = gpio_o[37:0]; + 39: gpio_width_adjust_out = gpio_o[38:0]; + 40: gpio_width_adjust_out = gpio_o[39:0]; + 41: gpio_width_adjust_out = gpio_o[40:0]; + 42: gpio_width_adjust_out = gpio_o[41:0]; + 43: gpio_width_adjust_out = gpio_o[42:0]; + 44: gpio_width_adjust_out = gpio_o[43:0]; + 45: gpio_width_adjust_out = gpio_o[44:0]; + 46: gpio_width_adjust_out = gpio_o[45:0]; + 47: gpio_width_adjust_out = gpio_o[46:0]; + 48: gpio_width_adjust_out = gpio_o[47:0]; + 49: gpio_width_adjust_out = gpio_o[48:0]; + 50: gpio_width_adjust_out = gpio_o[49:0]; + 51: gpio_width_adjust_out = gpio_o[50:0]; + 52: gpio_width_adjust_out = gpio_o[51:0]; + 53: gpio_width_adjust_out = gpio_o[52:0]; + 54: gpio_width_adjust_out = gpio_o[53:0]; + 55: gpio_width_adjust_out = gpio_o[54:0]; + 56: gpio_width_adjust_out = gpio_o[55:0]; + 57: gpio_width_adjust_out = gpio_o[56:0]; + 58: gpio_width_adjust_out = gpio_o[57:0]; + 59: gpio_width_adjust_out = gpio_o[58:0]; + 60: gpio_width_adjust_out = gpio_o[59:0]; + 61: gpio_width_adjust_out = gpio_o[60:0]; + 62: gpio_width_adjust_out = gpio_o[61:0]; + 63: gpio_width_adjust_out = gpio_o[62:0]; + 64: gpio_width_adjust_out = gpio_o; + default : gpio_width_adjust_out = gpio_o; + endcase + end + endfunction + + assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out); + assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n); + +// Adding OBUFT to JTAG out port +generate + if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE + OBUFT jtag_obuft_inst ( + .O(PJTAG_TDO), + .I(PJTAG_TDO_O), + .T(PJTAG_TDO_T) + ); + end + else + begin + assign PJTAG_TDO = 1'b0; + end +endgenerate +// ------- +// EMIO PJTAG +assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n; + +// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon, +// FOR Other SI REV, inversion is required + +assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n); +assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]); + +// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon, +// FOR Other SI REV, inversion is required +assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n); +assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]); + +// FCLK_CLK optional clock buffers + +generate + if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0 + BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0])); + end + if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1 + BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1])); + end + if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2 + BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2])); + end + if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3 + BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3])); + end +endgenerate + +assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0]; +assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1]; +assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2]; +assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3]; + +assign FCLK_CLK0 = FCLK_CLK0_temp; + +// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports + +BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n)); +BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE)); +BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n)); +BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk)); +BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n)); +BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB)); +BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT)); +BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n)); +BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB)); +BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN)); +BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP)); +BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB)); +BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK)); +BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB)); + +genvar i; +generate + for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin + BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i])); + end +endgenerate + +generate + for (i=0; i < 3; i=i+1) begin + BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i])); + end +endgenerate + +generate + for (i=0; i < 15; i=i+1) begin + BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i])); + end +endgenerate + +generate + for (i=0; i < C_DM_WIDTH; i=i+1) begin + BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i])); + end +endgenerate + +generate + for (i=0; i < C_DQ_WIDTH; i=i+1) begin + BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i])); + end +endgenerate + +generate + for (i=0; i < C_DQS_WIDTH; i=i+1) begin + BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i])); + end +endgenerate + +generate + for (i=0; i < C_DQS_WIDTH; i=i+1) begin + BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i])); + end +endgenerate + +// Connect FCLK in case of disable the AXI port for non Secure Transaction +//Start + + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin + assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin + assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin + assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin + assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK; + end +endgenerate + +//Start + + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin + assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin + assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin + assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin + assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK; + end +endgenerate + +generate + if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin + assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp; + end + else begin + assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK; + end +endgenerate + +assign M_AXI_GP0_ARCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP0_ARCACHE_t[0]}}:M_AXI_GP0_ARCACHE_t ; +assign M_AXI_GP1_ARCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_ARCACHE_t[3:2]},{1'b1},{M_AXI_GP1_ARCACHE_t[0]}}:M_AXI_GP1_ARCACHE_t ; +assign M_AXI_GP0_AWCACHE=(C_GP0_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP0_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP0_AWCACHE_t[0]}}:M_AXI_GP0_AWCACHE_t ; +assign M_AXI_GP1_AWCACHE=(C_GP1_EN_MODIFIABLE_TXN==1)?{{M_AXI_GP1_AWCACHE_t[3:2]},{1'b1},{M_AXI_GP1_AWCACHE_t[0]}}:M_AXI_GP1_AWCACHE_t ; + + +//END +//==================== +//PSS TOP +//==================== +generate +if (C_PACKAGE_NAME == "clg225" ) begin + wire [21:0] dummy; + PS7 PS7_i ( + .DMA0DATYPE (DMA0_DATYPE ), + .DMA0DAVALID (DMA0_DAVALID), + .DMA0DRREADY (DMA0_DRREADY), + .DMA0RSTN (DMA0_RSTN ), + .DMA1DATYPE (DMA1_DATYPE ), + .DMA1DAVALID (DMA1_DAVALID), + .DMA1DRREADY (DMA1_DRREADY), + .DMA1RSTN (DMA1_RSTN ), + .DMA2DATYPE (DMA2_DATYPE ), + .DMA2DAVALID (DMA2_DAVALID), + .DMA2DRREADY (DMA2_DRREADY), + .DMA2RSTN (DMA2_RSTN ), + .DMA3DATYPE (DMA3_DATYPE ), + .DMA3DAVALID (DMA3_DAVALID), + .DMA3DRREADY (DMA3_DRREADY), + .DMA3RSTN (DMA3_RSTN ), + .EMIOCAN0PHYTX (CAN0_PHY_TX ), + .EMIOCAN1PHYTX (CAN1_PHY_TX ), + .EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ), + .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i), + .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i), + .EMIOENET0MDIOMDC (ENET0_MDIO_MDC), + .EMIOENET0MDIOO (ENET0_MDIO_O ), + .EMIOENET0MDIOTN (ENET0_MDIO_T_n ), + .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX), + .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX), + .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX), + .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX), + .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), + .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), + .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX), + .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX), + .EMIOENET0SOFRX (ENET0_SOF_RX), + .EMIOENET0SOFTX (ENET0_SOF_TX), + .EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i), + .EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i), + .EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i), + .EMIOENET1MDIOMDC (ENET1_MDIO_MDC), + .EMIOENET1MDIOO (ENET1_MDIO_O), + .EMIOENET1MDIOTN (ENET1_MDIO_T_n), + .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX), + .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX), + .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX), + .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX), + .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), + .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), + .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX), + .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX), + .EMIOENET1SOFRX (ENET1_SOF_RX), + .EMIOENET1SOFTX (ENET1_SOF_TX), + .EMIOGPIOO (gpio_out), + .EMIOGPIOTN (gpio_out_t_n), + .EMIOI2C0SCLO (I2C0_SCL_O), + .EMIOI2C0SCLTN (I2C0_SCL_T_n), + .EMIOI2C0SDAO (I2C0_SDA_O), + .EMIOI2C0SDATN (I2C0_SDA_T_n), + .EMIOI2C1SCLO (I2C1_SCL_O), + .EMIOI2C1SCLTN (I2C1_SCL_T_n), + .EMIOI2C1SDAO (I2C1_SDA_O), + .EMIOI2C1SDATN (I2C1_SDA_T_n), + .EMIOPJTAGTDO (PJTAG_TDO_O), + .EMIOPJTAGTDTN (PJTAG_TDO_T_n), + .EMIOSDIO0BUSPOW (SDIO0_BUSPOW), + .EMIOSDIO0CLK (SDIO0_CLK ), + .EMIOSDIO0CMDO (SDIO0_CMD_O ), + .EMIOSDIO0CMDTN (SDIO0_CMD_T_n ), + .EMIOSDIO0DATAO (SDIO0_DATA_O), + .EMIOSDIO0DATATN (SDIO0_DATA_T_n), + .EMIOSDIO0LED (SDIO0_LED), + .EMIOSDIO1BUSPOW (SDIO1_BUSPOW), + .EMIOSDIO1CLK (SDIO1_CLK ), + .EMIOSDIO1CMDO (SDIO1_CMD_O ), + .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ), + .EMIOSDIO1DATAO (SDIO1_DATA_O), + .EMIOSDIO1DATATN (SDIO1_DATA_T_n), + .EMIOSDIO1LED (SDIO1_LED), + .EMIOSPI0MO (SPI0_MOSI_O), + .EMIOSPI0MOTN (SPI0_MOSI_T_n), + .EMIOSPI0SCLKO (SPI0_SCLK_O), + .EMIOSPI0SCLKTN (SPI0_SCLK_T_n), + .EMIOSPI0SO (SPI0_MISO_O), + .EMIOSPI0STN (SPI0_MISO_T_n), + .EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), + .EMIOSPI0SSNTN (SPI0_SS_T_n), + .EMIOSPI1MO (SPI1_MOSI_O), + .EMIOSPI1MOTN (SPI1_MOSI_T_n), + .EMIOSPI1SCLKO (SPI1_SCLK_O), + .EMIOSPI1SCLKTN (SPI1_SCLK_T_n), + .EMIOSPI1SO (SPI1_MISO_O), + .EMIOSPI1STN (SPI1_MISO_T_n), + .EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), + .EMIOSPI1SSNTN (SPI1_SS_T_n), + .EMIOTRACECTL (TRACE_CTL_i), + .EMIOTRACEDATA (TRACE_DATA_i), + .EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), + .EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), + .EMIOUART0DTRN (UART0_DTRN), + .EMIOUART0RTSN (UART0_RTSN), + .EMIOUART0TX (UART0_TX ), + .EMIOUART1DTRN (UART1_DTRN), + .EMIOUART1RTSN (UART1_RTSN), + .EMIOUART1TX (UART1_TX ), + .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL), + .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT), + .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL), + .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT), + .EMIOWDTRSTO (WDT_RST_OUT), + .EVENTEVENTO (EVENT_EVENTO), + .EVENTSTANDBYWFE (EVENT_STANDBYWFE), + .EVENTSTANDBYWFI (EVENT_STANDBYWFI), + .FCLKCLK (FCLK_CLK_unbuffered), + .FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), + .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT), + .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT), + .FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), + .FTMTP2FDEBUG (FTMT_P2F_DEBUG ), + .FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), + .IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}), + .MAXIGP0ARADDR (M_AXI_GP0_ARADDR), + .MAXIGP0ARBURST (M_AXI_GP0_ARBURST), + .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t), + .MAXIGP0ARESETN (M_AXI_GP0_ARESETN), + .MAXIGP0ARID (M_AXI_GP0_ARID_FULL ), + .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ), + .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ), + .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ), + .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ), + .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ), + .MAXIGP0ARVALID (M_AXI_GP0_ARVALID), + .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ), + .MAXIGP0AWBURST (M_AXI_GP0_AWBURST), + .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t), + .MAXIGP0AWID (M_AXI_GP0_AWID_FULL ), + .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ), + .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ), + .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ), + .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ), + .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ), + .MAXIGP0AWVALID (M_AXI_GP0_AWVALID), + .MAXIGP0BREADY (M_AXI_GP0_BREADY ), + .MAXIGP0RREADY (M_AXI_GP0_RREADY ), + .MAXIGP0WDATA (M_AXI_GP0_WDATA ), + .MAXIGP0WID (M_AXI_GP0_WID_FULL ), + .MAXIGP0WLAST (M_AXI_GP0_WLAST ), + .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ), + .MAXIGP0WVALID (M_AXI_GP0_WVALID ), + .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ), + .MAXIGP1ARBURST (M_AXI_GP1_ARBURST), + .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t), + .MAXIGP1ARESETN (M_AXI_GP1_ARESETN), + .MAXIGP1ARID (M_AXI_GP1_ARID_FULL ), + .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ), + .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ), + .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ), + .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ), + .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ), + .MAXIGP1ARVALID (M_AXI_GP1_ARVALID), + .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ), + .MAXIGP1AWBURST (M_AXI_GP1_AWBURST), + .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t), + .MAXIGP1AWID (M_AXI_GP1_AWID_FULL ), + .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ), + .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ), + .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ), + .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ), + .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ), + .MAXIGP1AWVALID (M_AXI_GP1_AWVALID), + .MAXIGP1BREADY (M_AXI_GP1_BREADY ), + .MAXIGP1RREADY (M_AXI_GP1_RREADY ), + .MAXIGP1WDATA (M_AXI_GP1_WDATA ), + .MAXIGP1WID (M_AXI_GP1_WID_FULL ), + .MAXIGP1WLAST (M_AXI_GP1_WLAST ), + .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ), + .MAXIGP1WVALID (M_AXI_GP1_WVALID ), + .SAXIACPARESETN (S_AXI_ACP_ARESETN), + .SAXIACPARREADY (SAXIACPARREADY_W), + .SAXIACPAWREADY (SAXIACPAWREADY_W), + .SAXIACPBID (S_AXI_ACP_BID_out ), + .SAXIACPBRESP (SAXIACPBRESP_W ), + .SAXIACPBVALID (SAXIACPBVALID_W ), + .SAXIACPRDATA (SAXIACPRDATA_W ), + .SAXIACPRID (S_AXI_ACP_RID_out), + .SAXIACPRLAST (SAXIACPRLAST_W ), + .SAXIACPRRESP (SAXIACPRRESP_W ), + .SAXIACPRVALID (SAXIACPRVALID_W ), + .SAXIACPWREADY (SAXIACPWREADY_W ), + .SAXIGP0ARESETN (S_AXI_GP0_ARESETN), + .SAXIGP0ARREADY (S_AXI_GP0_ARREADY), + .SAXIGP0AWREADY (S_AXI_GP0_AWREADY), + .SAXIGP0BID (S_AXI_GP0_BID_out), + .SAXIGP0BRESP (S_AXI_GP0_BRESP ), + .SAXIGP0BVALID (S_AXI_GP0_BVALID ), + .SAXIGP0RDATA (S_AXI_GP0_RDATA ), + .SAXIGP0RID (S_AXI_GP0_RID_out ), + .SAXIGP0RLAST (S_AXI_GP0_RLAST ), + .SAXIGP0RRESP (S_AXI_GP0_RRESP ), + .SAXIGP0RVALID (S_AXI_GP0_RVALID ), + .SAXIGP0WREADY (S_AXI_GP0_WREADY ), + .SAXIGP1ARESETN (S_AXI_GP1_ARESETN), + .SAXIGP1ARREADY (S_AXI_GP1_ARREADY), + .SAXIGP1AWREADY (S_AXI_GP1_AWREADY), + .SAXIGP1BID (S_AXI_GP1_BID_out ), + .SAXIGP1BRESP (S_AXI_GP1_BRESP ), + .SAXIGP1BVALID (S_AXI_GP1_BVALID ), + .SAXIGP1RDATA (S_AXI_GP1_RDATA ), + .SAXIGP1RID (S_AXI_GP1_RID_out ), + .SAXIGP1RLAST (S_AXI_GP1_RLAST ), + .SAXIGP1RRESP (S_AXI_GP1_RRESP ), + .SAXIGP1RVALID (S_AXI_GP1_RVALID ), + .SAXIGP1WREADY (S_AXI_GP1_WREADY ), + .SAXIHP0ARESETN (S_AXI_HP0_ARESETN), + .SAXIHP0ARREADY (S_AXI_HP0_ARREADY), + .SAXIHP0AWREADY (S_AXI_HP0_AWREADY), + .SAXIHP0BID (S_AXI_HP0_BID_out ), + .SAXIHP0BRESP (S_AXI_HP0_BRESP ), + .SAXIHP0BVALID (S_AXI_HP0_BVALID ), + .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT), + .SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT), + .SAXIHP0RDATA (S_AXI_HP0_RDATA_out), + .SAXIHP0RID (S_AXI_HP0_RID_out ), + .SAXIHP0RLAST (S_AXI_HP0_RLAST), + .SAXIHP0RRESP (S_AXI_HP0_RRESP), + .SAXIHP0RVALID (S_AXI_HP0_RVALID), + .SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT), + .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT), + .SAXIHP0WREADY (S_AXI_HP0_WREADY), + .SAXIHP1ARESETN (S_AXI_HP1_ARESETN), + .SAXIHP1ARREADY (S_AXI_HP1_ARREADY), + .SAXIHP1AWREADY (S_AXI_HP1_AWREADY), + .SAXIHP1BID (S_AXI_HP1_BID_out ), + .SAXIHP1BRESP (S_AXI_HP1_BRESP ), + .SAXIHP1BVALID (S_AXI_HP1_BVALID ), + .SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ), + .SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ), + .SAXIHP1RDATA (S_AXI_HP1_RDATA_out), + .SAXIHP1RID (S_AXI_HP1_RID_out ), + .SAXIHP1RLAST (S_AXI_HP1_RLAST ), + .SAXIHP1RRESP (S_AXI_HP1_RRESP ), + .SAXIHP1RVALID (S_AXI_HP1_RVALID), + .SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT), + .SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT), + .SAXIHP1WREADY (S_AXI_HP1_WREADY), + .SAXIHP2ARESETN (S_AXI_HP2_ARESETN), + .SAXIHP2ARREADY (S_AXI_HP2_ARREADY), + .SAXIHP2AWREADY (S_AXI_HP2_AWREADY), + .SAXIHP2BID (S_AXI_HP2_BID_out ), + .SAXIHP2BRESP (S_AXI_HP2_BRESP), + .SAXIHP2BVALID (S_AXI_HP2_BVALID), + .SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT), + .SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT), + .SAXIHP2RDATA (S_AXI_HP2_RDATA_out), + .SAXIHP2RID (S_AXI_HP2_RID_out ), + .SAXIHP2RLAST (S_AXI_HP2_RLAST), + .SAXIHP2RRESP (S_AXI_HP2_RRESP), + .SAXIHP2RVALID (S_AXI_HP2_RVALID), + .SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT), + .SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT), + .SAXIHP2WREADY (S_AXI_HP2_WREADY), + .SAXIHP3ARESETN (S_AXI_HP3_ARESETN), + .SAXIHP3ARREADY (S_AXI_HP3_ARREADY), + .SAXIHP3AWREADY (S_AXI_HP3_AWREADY), + .SAXIHP3BID (S_AXI_HP3_BID_out), + .SAXIHP3BRESP (S_AXI_HP3_BRESP), + .SAXIHP3BVALID (S_AXI_HP3_BVALID), + .SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT), + .SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT), + .SAXIHP3RDATA (S_AXI_HP3_RDATA_out), + .SAXIHP3RID (S_AXI_HP3_RID_out), + .SAXIHP3RLAST (S_AXI_HP3_RLAST), + .SAXIHP3RRESP (S_AXI_HP3_RRESP), + .SAXIHP3RVALID (S_AXI_HP3_RVALID), + .SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT), + .SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT), + .SAXIHP3WREADY (S_AXI_HP3_WREADY), + .DDRARB (DDR_ARB), + .DMA0ACLK (DMA0_ACLK ), + .DMA0DAREADY (DMA0_DAREADY), + .DMA0DRLAST (DMA0_DRLAST ), + .DMA0DRTYPE (DMA0_DRTYPE), + .DMA0DRVALID (DMA0_DRVALID), + .DMA1ACLK (DMA1_ACLK ), + .DMA1DAREADY (DMA1_DAREADY), + .DMA1DRLAST (DMA1_DRLAST ), + .DMA1DRTYPE (DMA1_DRTYPE), + .DMA1DRVALID (DMA1_DRVALID), + .DMA2ACLK (DMA2_ACLK ), + .DMA2DAREADY (DMA2_DAREADY), + .DMA2DRLAST (DMA2_DRLAST ), + .DMA2DRTYPE (DMA2_DRTYPE), + .DMA2DRVALID (DMA2_DRVALID), + .DMA3ACLK (DMA3_ACLK ), + .DMA3DAREADY (DMA3_DAREADY), + .DMA3DRLAST (DMA3_DRLAST ), + .DMA3DRTYPE (DMA3_DRTYPE), + .DMA3DRVALID (DMA3_DRVALID), + .EMIOCAN0PHYRX (CAN0_PHY_RX), + .EMIOCAN1PHYRX (CAN1_PHY_RX), + .EMIOENET0EXTINTIN (ENET0_EXT_INTIN), + .EMIOENET0GMIICOL (ENET0_GMII_COL_i), + .EMIOENET0GMIICRS (ENET0_GMII_CRS_i), + .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK), + .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i), + .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i), + .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i), + .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK), + .EMIOENET0MDIOI (ENET0_MDIO_I), + .EMIOENET1EXTINTIN (ENET1_EXT_INTIN), + .EMIOENET1GMIICOL (ENET1_GMII_COL_i), + .EMIOENET1GMIICRS (ENET1_GMII_CRS_i), + .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK), + .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i), + .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i), + .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i), + .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK), + .EMIOENET1MDIOI (ENET1_MDIO_I), + .EMIOGPIOI (gpio_in63_0 ), + .EMIOI2C0SCLI (I2C0_SCL_I), + .EMIOI2C0SDAI (I2C0_SDA_I), + .EMIOI2C1SCLI (I2C1_SCL_I), + .EMIOI2C1SDAI (I2C1_SDA_I), + .EMIOPJTAGTCK (PJTAG_TCK), + .EMIOPJTAGTDI (PJTAG_TDI), + .EMIOPJTAGTMS (PJTAG_TMS), + .EMIOSDIO0CDN (SDIO0_CDN), + .EMIOSDIO0CLKFB (SDIO0_CLK_FB ), + .EMIOSDIO0CMDI (SDIO0_CMD_I ), + .EMIOSDIO0DATAI (SDIO0_DATA_I ), + .EMIOSDIO0WP (SDIO0_WP), + .EMIOSDIO1CDN (SDIO1_CDN), + .EMIOSDIO1CLKFB (SDIO1_CLK_FB ), + .EMIOSDIO1CMDI (SDIO1_CMD_I ), + .EMIOSDIO1DATAI (SDIO1_DATA_I ), + .EMIOSDIO1WP (SDIO1_WP), + .EMIOSPI0MI (SPI0_MISO_I), + .EMIOSPI0SCLKI (SPI0_SCLK_I), + .EMIOSPI0SI (SPI0_MOSI_I), + .EMIOSPI0SSIN (SPI0_SS_I), + .EMIOSPI1MI (SPI1_MISO_I), + .EMIOSPI1SCLKI (SPI1_SCLK_I), + .EMIOSPI1SI (SPI1_MOSI_I), + .EMIOSPI1SSIN (SPI1_SS_I), + .EMIOSRAMINTIN (SRAM_INTIN), + .EMIOTRACECLK (TRACE_CLK), + .EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}), + .EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}), + .EMIOUART0CTSN (UART0_CTSN), + .EMIOUART0DCDN (UART0_DCDN), + .EMIOUART0DSRN (UART0_DSRN), + .EMIOUART0RIN (UART0_RIN ), + .EMIOUART0RX (UART0_RX ), + .EMIOUART1CTSN (UART1_CTSN), + .EMIOUART1DCDN (UART1_DCDN), + .EMIOUART1DSRN (UART1_DSRN), + .EMIOUART1RIN (UART1_RIN ), + .EMIOUART1RX (UART1_RX ), + .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT), + .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT), + .EMIOWDTCLKI (WDT_CLK_IN), + .EVENTEVENTI (EVENT_EVENTI), + .FCLKCLKTRIGN (fclk_clktrig_gnd), + .FPGAIDLEN (FPGA_IDLE_N), + .FTMDTRACEINATID (FTMD_TRACEIN_ATID_i), + .FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK), + .FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i), + .FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i), + .FTMTF2PDEBUG (FTMT_F2P_DEBUG ), + .FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), + .FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), + .IRQF2P (irq_f2p_i), + .MAXIGP0ACLK (M_AXI_GP0_ACLK_temp), + .MAXIGP0ARREADY (M_AXI_GP0_ARREADY), + .MAXIGP0AWREADY (M_AXI_GP0_AWREADY), + .MAXIGP0BID (M_AXI_GP0_BID_FULL ), + .MAXIGP0BRESP (M_AXI_GP0_BRESP ), + .MAXIGP0BVALID (M_AXI_GP0_BVALID ), + .MAXIGP0RDATA (M_AXI_GP0_RDATA ), + .MAXIGP0RID (M_AXI_GP0_RID_FULL ), + .MAXIGP0RLAST (M_AXI_GP0_RLAST ), + .MAXIGP0RRESP (M_AXI_GP0_RRESP ), + .MAXIGP0RVALID (M_AXI_GP0_RVALID ), + .MAXIGP0WREADY (M_AXI_GP0_WREADY ), + .MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ), + .MAXIGP1ARREADY (M_AXI_GP1_ARREADY), + .MAXIGP1AWREADY (M_AXI_GP1_AWREADY), + .MAXIGP1BID (M_AXI_GP1_BID_FULL ), + .MAXIGP1BRESP (M_AXI_GP1_BRESP ), + .MAXIGP1BVALID (M_AXI_GP1_BVALID ), + .MAXIGP1RDATA (M_AXI_GP1_RDATA ), + .MAXIGP1RID (M_AXI_GP1_RID_FULL ), + .MAXIGP1RLAST (M_AXI_GP1_RLAST ), + .MAXIGP1RRESP (M_AXI_GP1_RRESP ), + .MAXIGP1RVALID (M_AXI_GP1_RVALID ), + .MAXIGP1WREADY (M_AXI_GP1_WREADY ), + .SAXIACPACLK (S_AXI_ACP_ACLK_temp ), + .SAXIACPARADDR (SAXIACPARADDR_W ), + .SAXIACPARBURST (SAXIACPARBURST_W), + .SAXIACPARCACHE (SAXIACPARCACHE_W), + .SAXIACPARID (S_AXI_ACP_ARID_in ), + .SAXIACPARLEN (SAXIACPARLEN_W ), + .SAXIACPARLOCK (SAXIACPARLOCK_W ), + .SAXIACPARPROT (SAXIACPARPROT_W ), + .SAXIACPARQOS (S_AXI_ACP_ARQOS ), + .SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ), + .SAXIACPARUSER (SAXIACPARUSER_W ), + .SAXIACPARVALID (SAXIACPARVALID_W), + .SAXIACPAWADDR (SAXIACPAWADDR_W ), + .SAXIACPAWBURST (SAXIACPAWBURST_W), + .SAXIACPAWCACHE (SAXIACPAWCACHE_W), + .SAXIACPAWID (S_AXI_ACP_AWID_in ), + .SAXIACPAWLEN (SAXIACPAWLEN_W ), + .SAXIACPAWLOCK (SAXIACPAWLOCK_W ), + .SAXIACPAWPROT (SAXIACPAWPROT_W ), + .SAXIACPAWQOS (S_AXI_ACP_AWQOS ), + .SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ), + .SAXIACPAWUSER (SAXIACPAWUSER_W ), + .SAXIACPAWVALID (SAXIACPAWVALID_W), + .SAXIACPBREADY (SAXIACPBREADY_W ), + .SAXIACPRREADY (SAXIACPRREADY_W ), + .SAXIACPWDATA (SAXIACPWDATA_W ), + .SAXIACPWID (S_AXI_ACP_WID_in ), + .SAXIACPWLAST (SAXIACPWLAST_W ), + .SAXIACPWSTRB (SAXIACPWSTRB_W ), + .SAXIACPWVALID (SAXIACPWVALID_W ), + .SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ), + .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ), + .SAXIGP0ARBURST (S_AXI_GP0_ARBURST), + .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE), + .SAXIGP0ARID (S_AXI_GP0_ARID_in ), + .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ), + .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ), + .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ), + .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ), + .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ), + .SAXIGP0ARVALID (S_AXI_GP0_ARVALID), + .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ), + .SAXIGP0AWBURST (S_AXI_GP0_AWBURST), + .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE), + .SAXIGP0AWID (S_AXI_GP0_AWID_in ), + .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ), + .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ), + .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ), + .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ), + .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ), + .SAXIGP0AWVALID (S_AXI_GP0_AWVALID), + .SAXIGP0BREADY (S_AXI_GP0_BREADY ), + .SAXIGP0RREADY (S_AXI_GP0_RREADY ), + .SAXIGP0WDATA (S_AXI_GP0_WDATA ), + .SAXIGP0WID (S_AXI_GP0_WID_in ), + .SAXIGP0WLAST (S_AXI_GP0_WLAST ), + .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ), + .SAXIGP0WVALID (S_AXI_GP0_WVALID ), + .SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ), + .SAXIGP1ARADDR (S_AXI_GP1_ARADDR ), + .SAXIGP1ARBURST (S_AXI_GP1_ARBURST), + .SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE), + .SAXIGP1ARID (S_AXI_GP1_ARID_in ), + .SAXIGP1ARLEN (S_AXI_GP1_ARLEN ), + .SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ), + .SAXIGP1ARPROT (S_AXI_GP1_ARPROT ), + .SAXIGP1ARQOS (S_AXI_GP1_ARQOS ), + .SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ), + .SAXIGP1ARVALID (S_AXI_GP1_ARVALID), + .SAXIGP1AWADDR (S_AXI_GP1_AWADDR ), + .SAXIGP1AWBURST (S_AXI_GP1_AWBURST), + .SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE), + .SAXIGP1AWID (S_AXI_GP1_AWID_in ), + .SAXIGP1AWLEN (S_AXI_GP1_AWLEN ), + .SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ), + .SAXIGP1AWPROT (S_AXI_GP1_AWPROT ), + .SAXIGP1AWQOS (S_AXI_GP1_AWQOS ), + .SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ), + .SAXIGP1AWVALID (S_AXI_GP1_AWVALID), + .SAXIGP1BREADY (S_AXI_GP1_BREADY ), + .SAXIGP1RREADY (S_AXI_GP1_RREADY ), + .SAXIGP1WDATA (S_AXI_GP1_WDATA ), + .SAXIGP1WID (S_AXI_GP1_WID_in ), + .SAXIGP1WLAST (S_AXI_GP1_WLAST ), + .SAXIGP1WSTRB (S_AXI_GP1_WSTRB ), + .SAXIGP1WVALID (S_AXI_GP1_WVALID ), + .SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ), + .SAXIHP0ARADDR (S_AXI_HP0_ARADDR), + .SAXIHP0ARBURST (S_AXI_HP0_ARBURST), + .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE), + .SAXIHP0ARID (S_AXI_HP0_ARID_in), + .SAXIHP0ARLEN (S_AXI_HP0_ARLEN), + .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK), + .SAXIHP0ARPROT (S_AXI_HP0_ARPROT), + .SAXIHP0ARQOS (S_AXI_HP0_ARQOS), + .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]), + .SAXIHP0ARVALID (S_AXI_HP0_ARVALID), + .SAXIHP0AWADDR (S_AXI_HP0_AWADDR), + .SAXIHP0AWBURST (S_AXI_HP0_AWBURST), + .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE), + .SAXIHP0AWID (S_AXI_HP0_AWID_in), + .SAXIHP0AWLEN (S_AXI_HP0_AWLEN), + .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK), + .SAXIHP0AWPROT (S_AXI_HP0_AWPROT), + .SAXIHP0AWQOS (S_AXI_HP0_AWQOS), + .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]), + .SAXIHP0AWVALID (S_AXI_HP0_AWVALID), + .SAXIHP0BREADY (S_AXI_HP0_BREADY), + .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN), + .SAXIHP0RREADY (S_AXI_HP0_RREADY), + .SAXIHP0WDATA (S_AXI_HP0_WDATA_in), + .SAXIHP0WID (S_AXI_HP0_WID_in), + .SAXIHP0WLAST (S_AXI_HP0_WLAST), + .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN), + .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in), + .SAXIHP0WVALID (S_AXI_HP0_WVALID), + .SAXIHP1ACLK (S_AXI_HP1_ACLK_temp), + .SAXIHP1ARADDR (S_AXI_HP1_ARADDR), + .SAXIHP1ARBURST (S_AXI_HP1_ARBURST), + .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE), + .SAXIHP1ARID (S_AXI_HP1_ARID_in), + .SAXIHP1ARLEN (S_AXI_HP1_ARLEN), + .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK), + .SAXIHP1ARPROT (S_AXI_HP1_ARPROT), + .SAXIHP1ARQOS (S_AXI_HP1_ARQOS), + .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]), + .SAXIHP1ARVALID (S_AXI_HP1_ARVALID), + .SAXIHP1AWADDR (S_AXI_HP1_AWADDR), + .SAXIHP1AWBURST (S_AXI_HP1_AWBURST), + .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE), + .SAXIHP1AWID (S_AXI_HP1_AWID_in), + .SAXIHP1AWLEN (S_AXI_HP1_AWLEN), + .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK), + .SAXIHP1AWPROT (S_AXI_HP1_AWPROT), + .SAXIHP1AWQOS (S_AXI_HP1_AWQOS), + .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]), + .SAXIHP1AWVALID (S_AXI_HP1_AWVALID), + .SAXIHP1BREADY (S_AXI_HP1_BREADY), + .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN), + .SAXIHP1RREADY (S_AXI_HP1_RREADY), + .SAXIHP1WDATA (S_AXI_HP1_WDATA_in), + .SAXIHP1WID (S_AXI_HP1_WID_in), + .SAXIHP1WLAST (S_AXI_HP1_WLAST), + .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN), + .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in), + .SAXIHP1WVALID (S_AXI_HP1_WVALID), + .SAXIHP2ACLK (S_AXI_HP2_ACLK_temp), + .SAXIHP2ARADDR (S_AXI_HP2_ARADDR), + .SAXIHP2ARBURST (S_AXI_HP2_ARBURST), + .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE), + .SAXIHP2ARID (S_AXI_HP2_ARID_in), + .SAXIHP2ARLEN (S_AXI_HP2_ARLEN), + .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK), + .SAXIHP2ARPROT (S_AXI_HP2_ARPROT), + .SAXIHP2ARQOS (S_AXI_HP2_ARQOS), + .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]), + .SAXIHP2ARVALID (S_AXI_HP2_ARVALID), + .SAXIHP2AWADDR (S_AXI_HP2_AWADDR), + .SAXIHP2AWBURST (S_AXI_HP2_AWBURST), + .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE), + .SAXIHP2AWID (S_AXI_HP2_AWID_in), + .SAXIHP2AWLEN (S_AXI_HP2_AWLEN), + .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK), + .SAXIHP2AWPROT (S_AXI_HP2_AWPROT), + .SAXIHP2AWQOS (S_AXI_HP2_AWQOS), + .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]), + .SAXIHP2AWVALID (S_AXI_HP2_AWVALID), + .SAXIHP2BREADY (S_AXI_HP2_BREADY), + .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN), + .SAXIHP2RREADY (S_AXI_HP2_RREADY), + .SAXIHP2WDATA (S_AXI_HP2_WDATA_in), + .SAXIHP2WID (S_AXI_HP2_WID_in), + .SAXIHP2WLAST (S_AXI_HP2_WLAST), + .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN), + .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in), + .SAXIHP2WVALID (S_AXI_HP2_WVALID), + .SAXIHP3ACLK (S_AXI_HP3_ACLK_temp), + .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ), + .SAXIHP3ARBURST (S_AXI_HP3_ARBURST), + .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE), + .SAXIHP3ARID (S_AXI_HP3_ARID_in ), + .SAXIHP3ARLEN (S_AXI_HP3_ARLEN), + .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK), + .SAXIHP3ARPROT (S_AXI_HP3_ARPROT), + .SAXIHP3ARQOS (S_AXI_HP3_ARQOS), + .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]), + .SAXIHP3ARVALID (S_AXI_HP3_ARVALID), + .SAXIHP3AWADDR (S_AXI_HP3_AWADDR), + .SAXIHP3AWBURST (S_AXI_HP3_AWBURST), + .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE), + .SAXIHP3AWID (S_AXI_HP3_AWID_in), + .SAXIHP3AWLEN (S_AXI_HP3_AWLEN), + .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK), + .SAXIHP3AWPROT (S_AXI_HP3_AWPROT), + .SAXIHP3AWQOS (S_AXI_HP3_AWQOS), + .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]), + .SAXIHP3AWVALID (S_AXI_HP3_AWVALID), + .SAXIHP3BREADY (S_AXI_HP3_BREADY), + .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN), + .SAXIHP3RREADY (S_AXI_HP3_RREADY), + .SAXIHP3WDATA (S_AXI_HP3_WDATA_in), + .SAXIHP3WID (S_AXI_HP3_WID_in), + .SAXIHP3WLAST (S_AXI_HP3_WLAST), + .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN), + .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in), + .SAXIHP3WVALID (S_AXI_HP3_WVALID), + .DDRA (buffered_DDR_Addr), + .DDRBA (buffered_DDR_BankAddr), + .DDRCASB (buffered_DDR_CAS_n), + .DDRCKE (buffered_DDR_CKE), + .DDRCKN (buffered_DDR_Clk_n), + .DDRCKP (buffered_DDR_Clk), + .DDRCSB (buffered_DDR_CS_n), + .DDRDM (buffered_DDR_DM), + .DDRDQ (buffered_DDR_DQ), + .DDRDQSN (buffered_DDR_DQS_n), + .DDRDQSP (buffered_DDR_DQS), + .DDRDRSTB (buffered_DDR_DRSTB), + .DDRODT (buffered_DDR_ODT), + .DDRRASB (buffered_DDR_RAS_n), + .DDRVRN (buffered_DDR_VRN), + .DDRVRP (buffered_DDR_VRP), + .DDRWEB (buffered_DDR_WEB), + .MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}), + .PSCLK (buffered_PS_CLK), + .PSPORB (buffered_PS_PORB), + .PSSRSTB (buffered_PS_SRSTB) + + +); + end + else begin + PS7 PS7_i ( + .DMA0DATYPE (DMA0_DATYPE ), + .DMA0DAVALID (DMA0_DAVALID), + .DMA0DRREADY (DMA0_DRREADY), + .DMA0RSTN (DMA0_RSTN ), + .DMA1DATYPE (DMA1_DATYPE ), + .DMA1DAVALID (DMA1_DAVALID), + .DMA1DRREADY (DMA1_DRREADY), + .DMA1RSTN (DMA1_RSTN ), + .DMA2DATYPE (DMA2_DATYPE ), + .DMA2DAVALID (DMA2_DAVALID), + .DMA2DRREADY (DMA2_DRREADY), + .DMA2RSTN (DMA2_RSTN ), + .DMA3DATYPE (DMA3_DATYPE ), + .DMA3DAVALID (DMA3_DAVALID), + .DMA3DRREADY (DMA3_DRREADY), + .DMA3RSTN (DMA3_RSTN ), + .EMIOCAN0PHYTX (CAN0_PHY_TX ), + .EMIOCAN1PHYTX (CAN1_PHY_TX ), + .EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ), + .EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i), + .EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i), + .EMIOENET0MDIOMDC (ENET0_MDIO_MDC), + .EMIOENET0MDIOO (ENET0_MDIO_O ), + .EMIOENET0MDIOTN (ENET0_MDIO_T_n ), + .EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX), + .EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX), + .EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX), + .EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX), + .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), + .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), + .EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX), + .EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX), + .EMIOENET0SOFRX (ENET0_SOF_RX), + .EMIOENET0SOFTX (ENET0_SOF_TX), + .EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i), + .EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i), + .EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i), + .EMIOENET1MDIOMDC (ENET1_MDIO_MDC), + .EMIOENET1MDIOO (ENET1_MDIO_O ), + .EMIOENET1MDIOTN (ENET1_MDIO_T_n), + .EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX), + .EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX), + .EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX), + .EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX), + .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), + .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), + .EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX), + .EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX), + .EMIOENET1SOFRX (ENET1_SOF_RX), + .EMIOENET1SOFTX (ENET1_SOF_TX), + .EMIOGPIOO (gpio_out), + .EMIOGPIOTN (gpio_out_t_n), + .EMIOI2C0SCLO (I2C0_SCL_O), + .EMIOI2C0SCLTN (I2C0_SCL_T_n), + .EMIOI2C0SDAO (I2C0_SDA_O), + .EMIOI2C0SDATN (I2C0_SDA_T_n), + .EMIOI2C1SCLO (I2C1_SCL_O), + .EMIOI2C1SCLTN (I2C1_SCL_T_n), + .EMIOI2C1SDAO (I2C1_SDA_O), + .EMIOI2C1SDATN (I2C1_SDA_T_n), + .EMIOPJTAGTDO (PJTAG_TDO_O), + .EMIOPJTAGTDTN (PJTAG_TDO_T_n), + .EMIOSDIO0BUSPOW (SDIO0_BUSPOW), + .EMIOSDIO0CLK (SDIO0_CLK ), + .EMIOSDIO0CMDO (SDIO0_CMD_O ), + .EMIOSDIO0CMDTN (SDIO0_CMD_T_n ), + .EMIOSDIO0DATAO (SDIO0_DATA_O), + .EMIOSDIO0DATATN (SDIO0_DATA_T_n), + .EMIOSDIO0LED (SDIO0_LED), + .EMIOSDIO1BUSPOW (SDIO1_BUSPOW), + .EMIOSDIO1CLK (SDIO1_CLK ), + .EMIOSDIO1CMDO (SDIO1_CMD_O ), + .EMIOSDIO1CMDTN (SDIO1_CMD_T_n ), + .EMIOSDIO1DATAO (SDIO1_DATA_O), + .EMIOSDIO1DATATN (SDIO1_DATA_T_n), + .EMIOSDIO1LED (SDIO1_LED), + .EMIOSPI0MO (SPI0_MOSI_O), + .EMIOSPI0MOTN (SPI0_MOSI_T_n), + .EMIOSPI0SCLKO (SPI0_SCLK_O), + .EMIOSPI0SCLKTN (SPI0_SCLK_T_n), + .EMIOSPI0SO (SPI0_MISO_O), + .EMIOSPI0STN (SPI0_MISO_T_n), + .EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), + .EMIOSPI0SSNTN (SPI0_SS_T_n), + .EMIOSPI1MO (SPI1_MOSI_O), + .EMIOSPI1MOTN (SPI1_MOSI_T_n), + .EMIOSPI1SCLKO (SPI1_SCLK_O), + .EMIOSPI1SCLKTN (SPI1_SCLK_T_n), + .EMIOSPI1SO (SPI1_MISO_O), + .EMIOSPI1STN (SPI1_MISO_T_n), + .EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), + .EMIOSPI1SSNTN (SPI1_SS_T_n), + .EMIOTRACECTL (TRACE_CTL_i), + .EMIOTRACEDATA (TRACE_DATA_i), + .EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), + .EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), + .EMIOUART0DTRN (UART0_DTRN), + .EMIOUART0RTSN (UART0_RTSN), + .EMIOUART0TX (UART0_TX ), + .EMIOUART1DTRN (UART1_DTRN), + .EMIOUART1RTSN (UART1_RTSN), + .EMIOUART1TX (UART1_TX ), + .EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL), + .EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT), + .EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL), + .EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT), + .EMIOWDTRSTO (WDT_RST_OUT), + .EVENTEVENTO (EVENT_EVENTO), + .EVENTSTANDBYWFE (EVENT_STANDBYWFE), + .EVENTSTANDBYWFI (EVENT_STANDBYWFI), + .FCLKCLK (FCLK_CLK_unbuffered), + .FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), + .EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT), + .EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT), + .FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), + .FTMTP2FDEBUG (FTMT_P2F_DEBUG ), + .FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), + .IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}), + .MAXIGP0ARADDR (M_AXI_GP0_ARADDR), + .MAXIGP0ARBURST (M_AXI_GP0_ARBURST), + .MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE_t), + .MAXIGP0ARESETN (M_AXI_GP0_ARESETN), + .MAXIGP0ARID (M_AXI_GP0_ARID_FULL ), + .MAXIGP0ARLEN (M_AXI_GP0_ARLEN ), + .MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ), + .MAXIGP0ARPROT (M_AXI_GP0_ARPROT ), + .MAXIGP0ARQOS (M_AXI_GP0_ARQOS ), + .MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ), + .MAXIGP0ARVALID (M_AXI_GP0_ARVALID), + .MAXIGP0AWADDR (M_AXI_GP0_AWADDR ), + .MAXIGP0AWBURST (M_AXI_GP0_AWBURST), + .MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE_t), + .MAXIGP0AWID (M_AXI_GP0_AWID_FULL ), + .MAXIGP0AWLEN (M_AXI_GP0_AWLEN ), + .MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ), + .MAXIGP0AWPROT (M_AXI_GP0_AWPROT ), + .MAXIGP0AWQOS (M_AXI_GP0_AWQOS ), + .MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ), + .MAXIGP0AWVALID (M_AXI_GP0_AWVALID), + .MAXIGP0BREADY (M_AXI_GP0_BREADY ), + .MAXIGP0RREADY (M_AXI_GP0_RREADY ), + .MAXIGP0WDATA (M_AXI_GP0_WDATA ), + .MAXIGP0WID (M_AXI_GP0_WID_FULL ), + .MAXIGP0WLAST (M_AXI_GP0_WLAST ), + .MAXIGP0WSTRB (M_AXI_GP0_WSTRB ), + .MAXIGP0WVALID (M_AXI_GP0_WVALID ), + .MAXIGP1ARADDR (M_AXI_GP1_ARADDR ), + .MAXIGP1ARBURST (M_AXI_GP1_ARBURST), + .MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE_t), + .MAXIGP1ARESETN (M_AXI_GP1_ARESETN), + .MAXIGP1ARID (M_AXI_GP1_ARID_FULL ), + .MAXIGP1ARLEN (M_AXI_GP1_ARLEN ), + .MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ), + .MAXIGP1ARPROT (M_AXI_GP1_ARPROT ), + .MAXIGP1ARQOS (M_AXI_GP1_ARQOS ), + .MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ), + .MAXIGP1ARVALID (M_AXI_GP1_ARVALID), + .MAXIGP1AWADDR (M_AXI_GP1_AWADDR ), + .MAXIGP1AWBURST (M_AXI_GP1_AWBURST), + .MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE_t), + .MAXIGP1AWID (M_AXI_GP1_AWID_FULL ), + .MAXIGP1AWLEN (M_AXI_GP1_AWLEN ), + .MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ), + .MAXIGP1AWPROT (M_AXI_GP1_AWPROT ), + .MAXIGP1AWQOS (M_AXI_GP1_AWQOS ), + .MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ), + .MAXIGP1AWVALID (M_AXI_GP1_AWVALID), + .MAXIGP1BREADY (M_AXI_GP1_BREADY ), + .MAXIGP1RREADY (M_AXI_GP1_RREADY ), + .MAXIGP1WDATA (M_AXI_GP1_WDATA ), + .MAXIGP1WID (M_AXI_GP1_WID_FULL ), + .MAXIGP1WLAST (M_AXI_GP1_WLAST ), + .MAXIGP1WSTRB (M_AXI_GP1_WSTRB ), + .MAXIGP1WVALID (M_AXI_GP1_WVALID ), + .SAXIACPARESETN (S_AXI_ACP_ARESETN), + .SAXIACPARREADY (SAXIACPARREADY_W), + .SAXIACPAWREADY (SAXIACPAWREADY_W), + .SAXIACPBID (S_AXI_ACP_BID_out ), + .SAXIACPBRESP (SAXIACPBRESP_W ), + .SAXIACPBVALID (SAXIACPBVALID_W ), + .SAXIACPRDATA (SAXIACPRDATA_W ), + .SAXIACPRID (S_AXI_ACP_RID_out), + .SAXIACPRLAST (SAXIACPRLAST_W ), + .SAXIACPRRESP (SAXIACPRRESP_W ), + .SAXIACPRVALID (SAXIACPRVALID_W ), + .SAXIACPWREADY (SAXIACPWREADY_W ), + .SAXIGP0ARESETN (S_AXI_GP0_ARESETN), + .SAXIGP0ARREADY (S_AXI_GP0_ARREADY), + .SAXIGP0AWREADY (S_AXI_GP0_AWREADY), + .SAXIGP0BID (S_AXI_GP0_BID_out), + .SAXIGP0BRESP (S_AXI_GP0_BRESP ), + .SAXIGP0BVALID (S_AXI_GP0_BVALID ), + .SAXIGP0RDATA (S_AXI_GP0_RDATA ), + .SAXIGP0RID (S_AXI_GP0_RID_out ), + .SAXIGP0RLAST (S_AXI_GP0_RLAST ), + .SAXIGP0RRESP (S_AXI_GP0_RRESP ), + .SAXIGP0RVALID (S_AXI_GP0_RVALID ), + .SAXIGP0WREADY (S_AXI_GP0_WREADY ), + .SAXIGP1ARESETN (S_AXI_GP1_ARESETN), + .SAXIGP1ARREADY (S_AXI_GP1_ARREADY), + .SAXIGP1AWREADY (S_AXI_GP1_AWREADY), + .SAXIGP1BID (S_AXI_GP1_BID_out ), + .SAXIGP1BRESP (S_AXI_GP1_BRESP ), + .SAXIGP1BVALID (S_AXI_GP1_BVALID ), + .SAXIGP1RDATA (S_AXI_GP1_RDATA ), + .SAXIGP1RID (S_AXI_GP1_RID_out ), + .SAXIGP1RLAST (S_AXI_GP1_RLAST ), + .SAXIGP1RRESP (S_AXI_GP1_RRESP ), + .SAXIGP1RVALID (S_AXI_GP1_RVALID ), + .SAXIGP1WREADY (S_AXI_GP1_WREADY ), + .SAXIHP0ARESETN (S_AXI_HP0_ARESETN), + .SAXIHP0ARREADY (S_AXI_HP0_ARREADY), + .SAXIHP0AWREADY (S_AXI_HP0_AWREADY), + .SAXIHP0BID (S_AXI_HP0_BID_out ), + .SAXIHP0BRESP (S_AXI_HP0_BRESP ), + .SAXIHP0BVALID (S_AXI_HP0_BVALID ), + .SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT), + .SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT), + .SAXIHP0RDATA (S_AXI_HP0_RDATA_out), + .SAXIHP0RID (S_AXI_HP0_RID_out ), + .SAXIHP0RLAST (S_AXI_HP0_RLAST), + .SAXIHP0RRESP (S_AXI_HP0_RRESP), + .SAXIHP0RVALID (S_AXI_HP0_RVALID), + .SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT), + .SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT), + .SAXIHP0WREADY (S_AXI_HP0_WREADY), + .SAXIHP1ARESETN (S_AXI_HP1_ARESETN), + .SAXIHP1ARREADY (S_AXI_HP1_ARREADY), + .SAXIHP1AWREADY (S_AXI_HP1_AWREADY), + .SAXIHP1BID (S_AXI_HP1_BID_out ), + .SAXIHP1BRESP (S_AXI_HP1_BRESP ), + .SAXIHP1BVALID (S_AXI_HP1_BVALID ), + .SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ), + .SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ), + .SAXIHP1RDATA (S_AXI_HP1_RDATA_out), + .SAXIHP1RID (S_AXI_HP1_RID_out ), + .SAXIHP1RLAST (S_AXI_HP1_RLAST ), + .SAXIHP1RRESP (S_AXI_HP1_RRESP ), + .SAXIHP1RVALID (S_AXI_HP1_RVALID), + .SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT), + .SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT), + .SAXIHP1WREADY (S_AXI_HP1_WREADY), + .SAXIHP2ARESETN (S_AXI_HP2_ARESETN), + .SAXIHP2ARREADY (S_AXI_HP2_ARREADY), + .SAXIHP2AWREADY (S_AXI_HP2_AWREADY), + .SAXIHP2BID (S_AXI_HP2_BID_out ), + .SAXIHP2BRESP (S_AXI_HP2_BRESP), + .SAXIHP2BVALID (S_AXI_HP2_BVALID), + .SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT), + .SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT), + .SAXIHP2RDATA (S_AXI_HP2_RDATA_out), + .SAXIHP2RID (S_AXI_HP2_RID_out ), + .SAXIHP2RLAST (S_AXI_HP2_RLAST), + .SAXIHP2RRESP (S_AXI_HP2_RRESP), + .SAXIHP2RVALID (S_AXI_HP2_RVALID), + .SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT), + .SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT), + .SAXIHP2WREADY (S_AXI_HP2_WREADY), + .SAXIHP3ARESETN (S_AXI_HP3_ARESETN), + .SAXIHP3ARREADY (S_AXI_HP3_ARREADY), + .SAXIHP3AWREADY (S_AXI_HP3_AWREADY), + .SAXIHP3BID (S_AXI_HP3_BID_out), + .SAXIHP3BRESP (S_AXI_HP3_BRESP), + .SAXIHP3BVALID (S_AXI_HP3_BVALID), + .SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT), + .SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT), + .SAXIHP3RDATA (S_AXI_HP3_RDATA_out), + .SAXIHP3RID (S_AXI_HP3_RID_out), + .SAXIHP3RLAST (S_AXI_HP3_RLAST), + .SAXIHP3RRESP (S_AXI_HP3_RRESP), + .SAXIHP3RVALID (S_AXI_HP3_RVALID), + .SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT), + .SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT), + .SAXIHP3WREADY (S_AXI_HP3_WREADY), + .DDRARB (DDR_ARB), + .DMA0ACLK (DMA0_ACLK ), + .DMA0DAREADY (DMA0_DAREADY), + .DMA0DRLAST (DMA0_DRLAST ), + .DMA0DRTYPE (DMA0_DRTYPE), + .DMA0DRVALID (DMA0_DRVALID), + .DMA1ACLK (DMA1_ACLK ), + .DMA1DAREADY (DMA1_DAREADY), + .DMA1DRLAST (DMA1_DRLAST ), + .DMA1DRTYPE (DMA1_DRTYPE), + .DMA1DRVALID (DMA1_DRVALID), + .DMA2ACLK (DMA2_ACLK ), + .DMA2DAREADY (DMA2_DAREADY), + .DMA2DRLAST (DMA2_DRLAST ), + .DMA2DRTYPE (DMA2_DRTYPE), + .DMA2DRVALID (DMA2_DRVALID), + .DMA3ACLK (DMA3_ACLK ), + .DMA3DAREADY (DMA3_DAREADY), + .DMA3DRLAST (DMA3_DRLAST ), + .DMA3DRTYPE (DMA3_DRTYPE), + .DMA3DRVALID (DMA3_DRVALID), + .EMIOCAN0PHYRX (CAN0_PHY_RX), + .EMIOCAN1PHYRX (CAN1_PHY_RX), + .EMIOENET0EXTINTIN (ENET0_EXT_INTIN), + .EMIOENET0GMIICOL (ENET0_GMII_COL_i), + .EMIOENET0GMIICRS (ENET0_GMII_CRS_i), + .EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK), + .EMIOENET0GMIIRXD (ENET0_GMII_RXD_i), + .EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i), + .EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i), + .EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK), + .EMIOENET0MDIOI (ENET0_MDIO_I), + .EMIOENET1EXTINTIN (ENET1_EXT_INTIN), + .EMIOENET1GMIICOL (ENET1_GMII_COL_i), + .EMIOENET1GMIICRS (ENET1_GMII_CRS_i), + .EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK), + .EMIOENET1GMIIRXD (ENET1_GMII_RXD_i), + .EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i), + .EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i), + .EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK), + .EMIOENET1MDIOI (ENET1_MDIO_I), + .EMIOGPIOI (gpio_in63_0 ), + .EMIOI2C0SCLI (I2C0_SCL_I), + .EMIOI2C0SDAI (I2C0_SDA_I), + .EMIOI2C1SCLI (I2C1_SCL_I), + .EMIOI2C1SDAI (I2C1_SDA_I), + .EMIOPJTAGTCK (PJTAG_TCK), + .EMIOPJTAGTDI (PJTAG_TDI), + .EMIOPJTAGTMS (PJTAG_TMS), + .EMIOSDIO0CDN (SDIO0_CDN), + .EMIOSDIO0CLKFB (SDIO0_CLK_FB ), + .EMIOSDIO0CMDI (SDIO0_CMD_I ), + .EMIOSDIO0DATAI (SDIO0_DATA_I ), + .EMIOSDIO0WP (SDIO0_WP), + .EMIOSDIO1CDN (SDIO1_CDN), + .EMIOSDIO1CLKFB (SDIO1_CLK_FB ), + .EMIOSDIO1CMDI (SDIO1_CMD_I ), + .EMIOSDIO1DATAI (SDIO1_DATA_I ), + .EMIOSDIO1WP (SDIO1_WP), + .EMIOSPI0MI (SPI0_MISO_I), + .EMIOSPI0SCLKI (SPI0_SCLK_I), + .EMIOSPI0SI (SPI0_MOSI_I), + .EMIOSPI0SSIN (SPI0_SS_I), + .EMIOSPI1MI (SPI1_MISO_I), + .EMIOSPI1SCLKI (SPI1_SCLK_I), + .EMIOSPI1SI (SPI1_MOSI_I), + .EMIOSPI1SSIN (SPI1_SS_I), + .EMIOSRAMINTIN (SRAM_INTIN), + .EMIOTRACECLK (TRACE_CLK), + .EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}), + .EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}), + .EMIOUART0CTSN (UART0_CTSN), + .EMIOUART0DCDN (UART0_DCDN), + .EMIOUART0DSRN (UART0_DSRN), + .EMIOUART0RIN (UART0_RIN ), + .EMIOUART0RX (UART0_RX ), + .EMIOUART1CTSN (UART1_CTSN), + .EMIOUART1DCDN (UART1_DCDN), + .EMIOUART1DSRN (UART1_DSRN), + .EMIOUART1RIN (UART1_RIN ), + .EMIOUART1RX (UART1_RX ), + .EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT), + .EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT), + .EMIOWDTCLKI (WDT_CLK_IN), + .EVENTEVENTI (EVENT_EVENTI), + .FCLKCLKTRIGN (fclk_clktrig_gnd), + .FPGAIDLEN (FPGA_IDLE_N), + .FTMDTRACEINATID (FTMD_TRACEIN_ATID_i), + .FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK), + .FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i), + .FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i), + .FTMTF2PDEBUG (FTMT_F2P_DEBUG ), + .FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), + .FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), + .IRQF2P (irq_f2p_i), + .MAXIGP0ACLK (M_AXI_GP0_ACLK_temp), + .MAXIGP0ARREADY (M_AXI_GP0_ARREADY), + .MAXIGP0AWREADY (M_AXI_GP0_AWREADY), + .MAXIGP0BID (M_AXI_GP0_BID_FULL ), + .MAXIGP0BRESP (M_AXI_GP0_BRESP ), + .MAXIGP0BVALID (M_AXI_GP0_BVALID ), + .MAXIGP0RDATA (M_AXI_GP0_RDATA ), + .MAXIGP0RID (M_AXI_GP0_RID_FULL ), + .MAXIGP0RLAST (M_AXI_GP0_RLAST ), + .MAXIGP0RRESP (M_AXI_GP0_RRESP ), + .MAXIGP0RVALID (M_AXI_GP0_RVALID ), + .MAXIGP0WREADY (M_AXI_GP0_WREADY ), + .MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ), + .MAXIGP1ARREADY (M_AXI_GP1_ARREADY), + .MAXIGP1AWREADY (M_AXI_GP1_AWREADY), + .MAXIGP1BID (M_AXI_GP1_BID_FULL ), + .MAXIGP1BRESP (M_AXI_GP1_BRESP ), + .MAXIGP1BVALID (M_AXI_GP1_BVALID ), + .MAXIGP1RDATA (M_AXI_GP1_RDATA ), + .MAXIGP1RID (M_AXI_GP1_RID_FULL ), + .MAXIGP1RLAST (M_AXI_GP1_RLAST ), + .MAXIGP1RRESP (M_AXI_GP1_RRESP ), + .MAXIGP1RVALID (M_AXI_GP1_RVALID ), + .MAXIGP1WREADY (M_AXI_GP1_WREADY ), + .SAXIACPACLK (S_AXI_ACP_ACLK_temp), + .SAXIACPARADDR (SAXIACPARADDR_W ), + .SAXIACPARBURST (SAXIACPARBURST_W), + .SAXIACPARCACHE (SAXIACPARCACHE_W), + .SAXIACPARID (S_AXI_ACP_ARID_in ), + .SAXIACPARLEN (SAXIACPARLEN_W ), + .SAXIACPARLOCK (SAXIACPARLOCK_W ), + .SAXIACPARPROT (SAXIACPARPROT_W ), + .SAXIACPARQOS (S_AXI_ACP_ARQOS ), + .SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ), + .SAXIACPARUSER (SAXIACPARUSER_W ), + .SAXIACPARVALID (SAXIACPARVALID_W), + .SAXIACPAWADDR (SAXIACPAWADDR_W ), + .SAXIACPAWBURST (SAXIACPAWBURST_W), + .SAXIACPAWCACHE (SAXIACPAWCACHE_W), + .SAXIACPAWID (S_AXI_ACP_AWID_in ), + .SAXIACPAWLEN (SAXIACPAWLEN_W ), + .SAXIACPAWLOCK (SAXIACPAWLOCK_W ), + .SAXIACPAWPROT (SAXIACPAWPROT_W ), + .SAXIACPAWQOS (S_AXI_ACP_AWQOS ), + .SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ), + .SAXIACPAWUSER (SAXIACPAWUSER_W ), + .SAXIACPAWVALID (SAXIACPAWVALID_W), + .SAXIACPBREADY (SAXIACPBREADY_W ), + .SAXIACPRREADY (SAXIACPRREADY_W ), + .SAXIACPWDATA (SAXIACPWDATA_W ), + .SAXIACPWID (S_AXI_ACP_WID_in ), + .SAXIACPWLAST (SAXIACPWLAST_W ), + .SAXIACPWSTRB (SAXIACPWSTRB_W ), + .SAXIACPWVALID (SAXIACPWVALID_W ), + .SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ), + .SAXIGP0ARADDR (S_AXI_GP0_ARADDR ), + .SAXIGP0ARBURST (S_AXI_GP0_ARBURST), + .SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE), + .SAXIGP0ARID (S_AXI_GP0_ARID_in ), + .SAXIGP0ARLEN (S_AXI_GP0_ARLEN ), + .SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ), + .SAXIGP0ARPROT (S_AXI_GP0_ARPROT ), + .SAXIGP0ARQOS (S_AXI_GP0_ARQOS ), + .SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ), + .SAXIGP0ARVALID (S_AXI_GP0_ARVALID), + .SAXIGP0AWADDR (S_AXI_GP0_AWADDR ), + .SAXIGP0AWBURST (S_AXI_GP0_AWBURST), + .SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE), + .SAXIGP0AWID (S_AXI_GP0_AWID_in ), + .SAXIGP0AWLEN (S_AXI_GP0_AWLEN ), + .SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ), + .SAXIGP0AWPROT (S_AXI_GP0_AWPROT ), + .SAXIGP0AWQOS (S_AXI_GP0_AWQOS ), + .SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ), + .SAXIGP0AWVALID (S_AXI_GP0_AWVALID), + .SAXIGP0BREADY (S_AXI_GP0_BREADY ), + .SAXIGP0RREADY (S_AXI_GP0_RREADY ), + .SAXIGP0WDATA (S_AXI_GP0_WDATA ), + .SAXIGP0WID (S_AXI_GP0_WID_in ), + .SAXIGP0WLAST (S_AXI_GP0_WLAST ), + .SAXIGP0WSTRB (S_AXI_GP0_WSTRB ), + .SAXIGP0WVALID (S_AXI_GP0_WVALID ), + .SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ), + .SAXIGP1ARADDR (S_AXI_GP1_ARADDR ), + .SAXIGP1ARBURST (S_AXI_GP1_ARBURST), + .SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE), + .SAXIGP1ARID (S_AXI_GP1_ARID_in ), + .SAXIGP1ARLEN (S_AXI_GP1_ARLEN ), + .SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ), + .SAXIGP1ARPROT (S_AXI_GP1_ARPROT ), + .SAXIGP1ARQOS (S_AXI_GP1_ARQOS ), + .SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ), + .SAXIGP1ARVALID (S_AXI_GP1_ARVALID), + .SAXIGP1AWADDR (S_AXI_GP1_AWADDR ), + .SAXIGP1AWBURST (S_AXI_GP1_AWBURST), + .SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE), + .SAXIGP1AWID (S_AXI_GP1_AWID_in ), + .SAXIGP1AWLEN (S_AXI_GP1_AWLEN ), + .SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ), + .SAXIGP1AWPROT (S_AXI_GP1_AWPROT ), + .SAXIGP1AWQOS (S_AXI_GP1_AWQOS ), + .SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ), + .SAXIGP1AWVALID (S_AXI_GP1_AWVALID), + .SAXIGP1BREADY (S_AXI_GP1_BREADY ), + .SAXIGP1RREADY (S_AXI_GP1_RREADY ), + .SAXIGP1WDATA (S_AXI_GP1_WDATA ), + .SAXIGP1WID (S_AXI_GP1_WID_in ), + .SAXIGP1WLAST (S_AXI_GP1_WLAST ), + .SAXIGP1WSTRB (S_AXI_GP1_WSTRB ), + .SAXIGP1WVALID (S_AXI_GP1_WVALID ), + .SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ), + .SAXIHP0ARADDR (S_AXI_HP0_ARADDR), + .SAXIHP0ARBURST (S_AXI_HP0_ARBURST), + .SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE), + .SAXIHP0ARID (S_AXI_HP0_ARID_in), + .SAXIHP0ARLEN (S_AXI_HP0_ARLEN), + .SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK), + .SAXIHP0ARPROT (S_AXI_HP0_ARPROT), + .SAXIHP0ARQOS (S_AXI_HP0_ARQOS), + .SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]), + .SAXIHP0ARVALID (S_AXI_HP0_ARVALID), + .SAXIHP0AWADDR (S_AXI_HP0_AWADDR), + .SAXIHP0AWBURST (S_AXI_HP0_AWBURST), + .SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE), + .SAXIHP0AWID (S_AXI_HP0_AWID_in), + .SAXIHP0AWLEN (S_AXI_HP0_AWLEN), + .SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK), + .SAXIHP0AWPROT (S_AXI_HP0_AWPROT), + .SAXIHP0AWQOS (S_AXI_HP0_AWQOS), + .SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]), + .SAXIHP0AWVALID (S_AXI_HP0_AWVALID), + .SAXIHP0BREADY (S_AXI_HP0_BREADY), + .SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN), + .SAXIHP0RREADY (S_AXI_HP0_RREADY), + .SAXIHP0WDATA (S_AXI_HP0_WDATA_in), + .SAXIHP0WID (S_AXI_HP0_WID_in), + .SAXIHP0WLAST (S_AXI_HP0_WLAST), + .SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN), + .SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in), + .SAXIHP0WVALID (S_AXI_HP0_WVALID), + .SAXIHP1ACLK (S_AXI_HP1_ACLK_temp), + .SAXIHP1ARADDR (S_AXI_HP1_ARADDR), + .SAXIHP1ARBURST (S_AXI_HP1_ARBURST), + .SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE), + .SAXIHP1ARID (S_AXI_HP1_ARID_in), + .SAXIHP1ARLEN (S_AXI_HP1_ARLEN), + .SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK), + .SAXIHP1ARPROT (S_AXI_HP1_ARPROT), + .SAXIHP1ARQOS (S_AXI_HP1_ARQOS), + .SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]), + .SAXIHP1ARVALID (S_AXI_HP1_ARVALID), + .SAXIHP1AWADDR (S_AXI_HP1_AWADDR), + .SAXIHP1AWBURST (S_AXI_HP1_AWBURST), + .SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE), + .SAXIHP1AWID (S_AXI_HP1_AWID_in), + .SAXIHP1AWLEN (S_AXI_HP1_AWLEN), + .SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK), + .SAXIHP1AWPROT (S_AXI_HP1_AWPROT), + .SAXIHP1AWQOS (S_AXI_HP1_AWQOS), + .SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]), + .SAXIHP1AWVALID (S_AXI_HP1_AWVALID), + .SAXIHP1BREADY (S_AXI_HP1_BREADY), + .SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN), + .SAXIHP1RREADY (S_AXI_HP1_RREADY), + .SAXIHP1WDATA (S_AXI_HP1_WDATA_in), + .SAXIHP1WID (S_AXI_HP1_WID_in), + .SAXIHP1WLAST (S_AXI_HP1_WLAST), + .SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN), + .SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in), + .SAXIHP1WVALID (S_AXI_HP1_WVALID), + .SAXIHP2ACLK (S_AXI_HP2_ACLK_temp), + .SAXIHP2ARADDR (S_AXI_HP2_ARADDR), + .SAXIHP2ARBURST (S_AXI_HP2_ARBURST), + .SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE), + .SAXIHP2ARID (S_AXI_HP2_ARID_in), + .SAXIHP2ARLEN (S_AXI_HP2_ARLEN), + .SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK), + .SAXIHP2ARPROT (S_AXI_HP2_ARPROT), + .SAXIHP2ARQOS (S_AXI_HP2_ARQOS), + .SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]), + .SAXIHP2ARVALID (S_AXI_HP2_ARVALID), + .SAXIHP2AWADDR (S_AXI_HP2_AWADDR), + .SAXIHP2AWBURST (S_AXI_HP2_AWBURST), + .SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE), + .SAXIHP2AWID (S_AXI_HP2_AWID_in), + .SAXIHP2AWLEN (S_AXI_HP2_AWLEN), + .SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK), + .SAXIHP2AWPROT (S_AXI_HP2_AWPROT), + .SAXIHP2AWQOS (S_AXI_HP2_AWQOS), + .SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]), + .SAXIHP2AWVALID (S_AXI_HP2_AWVALID), + .SAXIHP2BREADY (S_AXI_HP2_BREADY), + .SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN), + .SAXIHP2RREADY (S_AXI_HP2_RREADY), + .SAXIHP2WDATA (S_AXI_HP2_WDATA_in), + .SAXIHP2WID (S_AXI_HP2_WID_in), + .SAXIHP2WLAST (S_AXI_HP2_WLAST), + .SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN), + .SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in), + .SAXIHP2WVALID (S_AXI_HP2_WVALID), + .SAXIHP3ACLK (S_AXI_HP3_ACLK_temp), + .SAXIHP3ARADDR (S_AXI_HP3_ARADDR ), + .SAXIHP3ARBURST (S_AXI_HP3_ARBURST), + .SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE), + .SAXIHP3ARID (S_AXI_HP3_ARID_in ), + .SAXIHP3ARLEN (S_AXI_HP3_ARLEN), + .SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK), + .SAXIHP3ARPROT (S_AXI_HP3_ARPROT), + .SAXIHP3ARQOS (S_AXI_HP3_ARQOS), + .SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]), + .SAXIHP3ARVALID (S_AXI_HP3_ARVALID), + .SAXIHP3AWADDR (S_AXI_HP3_AWADDR), + .SAXIHP3AWBURST (S_AXI_HP3_AWBURST), + .SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE), + .SAXIHP3AWID (S_AXI_HP3_AWID_in), + .SAXIHP3AWLEN (S_AXI_HP3_AWLEN), + .SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK), + .SAXIHP3AWPROT (S_AXI_HP3_AWPROT), + .SAXIHP3AWQOS (S_AXI_HP3_AWQOS), + .SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]), + .SAXIHP3AWVALID (S_AXI_HP3_AWVALID), + .SAXIHP3BREADY (S_AXI_HP3_BREADY), + .SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN), + .SAXIHP3RREADY (S_AXI_HP3_RREADY), + .SAXIHP3WDATA (S_AXI_HP3_WDATA_in), + .SAXIHP3WID (S_AXI_HP3_WID_in), + .SAXIHP3WLAST (S_AXI_HP3_WLAST), + .SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN), + .SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in), + .SAXIHP3WVALID (S_AXI_HP3_WVALID), + .DDRA (buffered_DDR_Addr), + .DDRBA (buffered_DDR_BankAddr), + .DDRCASB (buffered_DDR_CAS_n), + .DDRCKE (buffered_DDR_CKE), + .DDRCKN (buffered_DDR_Clk_n), + .DDRCKP (buffered_DDR_Clk), + .DDRCSB (buffered_DDR_CS_n), + .DDRDM (buffered_DDR_DM), + .DDRDQ (buffered_DDR_DQ), + .DDRDQSN (buffered_DDR_DQS_n), + .DDRDQSP (buffered_DDR_DQS), + .DDRDRSTB (buffered_DDR_DRSTB), + .DDRODT (buffered_DDR_ODT), + .DDRRASB (buffered_DDR_RAS_n), + .DDRVRN (buffered_DDR_VRN), + .DDRVRP (buffered_DDR_VRP), + .DDRWEB (buffered_DDR_WEB), + .MIO (buffered_MIO), + .PSCLK (buffered_PS_CLK), + .PSPORB (buffered_PS_PORB), + .PSSRSTB (buffered_PS_SRSTB) + + + ); + + end + endgenerate + + +// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled. +// Otherwise a master connected to the ACP port will drive the AxUSER Ports +assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER; +assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER; + + assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR; + assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST; + assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE; + assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN; + assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK; + assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT; + assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE; + //assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER; + assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser; + + assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ; + assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR; + assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST; + + + assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE; + assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN; + assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK; + assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT; + assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE; + //assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER; + assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser; + assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID; + assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY; + assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY; + assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA; + assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST; + assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB; + assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID; + + assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID; + assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID; + assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID; + + + generate + if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc + + assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W; + assign S_AXI_ACP_WREADY = SAXIACPWREADY_W; + assign S_AXI_ACP_BID = SAXIACPBID_W; + assign S_AXI_ACP_BRESP = SAXIACPBRESP_W; + assign S_AXI_ACP_BVALID = SAXIACPBVALID_W; + assign S_AXI_ACP_RDATA = SAXIACPRDATA_W; + assign S_AXI_ACP_RID = SAXIACPRID_W; + assign S_AXI_ACP_RLAST = SAXIACPRLAST_W; + assign S_AXI_ACP_RRESP = SAXIACPRRESP_W; + assign S_AXI_ACP_RVALID = SAXIACPRVALID_W; + assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W; + + + end else begin : gen_atc + + processing_system7_v5_5_atc #( + .C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH), + .C_AXI_AWUSER_WIDTH (5), + .C_AXI_ARUSER_WIDTH (5) + ) + + atc_i ( + + // Global Signals + .ACLK (S_AXI_ACP_ACLK_temp), + .ARESETN (S_AXI_ACP_ARESETN), + + // Slave Interface Write Address Ports + .S_AXI_AWID (S_AXI_ACP_AWID), + .S_AXI_AWADDR (S_AXI_ACP_AWADDR), + .S_AXI_AWLEN (S_AXI_ACP_AWLEN), + .S_AXI_AWSIZE (S_AXI_ACP_AWSIZE), + .S_AXI_AWBURST (S_AXI_ACP_AWBURST), + .S_AXI_AWLOCK (S_AXI_ACP_AWLOCK), + .S_AXI_AWCACHE (S_AXI_ACP_AWCACHE), + .S_AXI_AWPROT (S_AXI_ACP_AWPROT), + //.S_AXI_AWUSER (S_AXI_ACP_AWUSER), + .S_AXI_AWUSER (param_awuser), + .S_AXI_AWVALID (S_AXI_ACP_AWVALID), + .S_AXI_AWREADY (S_AXI_ACP_AWREADY), + // Slave Interface Write Data Ports + .S_AXI_WID (S_AXI_ACP_WID), + .S_AXI_WDATA (S_AXI_ACP_WDATA), + .S_AXI_WSTRB (S_AXI_ACP_WSTRB), + .S_AXI_WLAST (S_AXI_ACP_WLAST), + .S_AXI_WUSER (), + .S_AXI_WVALID (S_AXI_ACP_WVALID), + .S_AXI_WREADY (S_AXI_ACP_WREADY), + // Slave Interface Write Response Ports + .S_AXI_BID (S_AXI_ACP_BID), + .S_AXI_BRESP (S_AXI_ACP_BRESP), + .S_AXI_BUSER (), + .S_AXI_BVALID (S_AXI_ACP_BVALID), + .S_AXI_BREADY (S_AXI_ACP_BREADY), + // Slave Interface Read Address Ports + .S_AXI_ARID (S_AXI_ACP_ARID), + .S_AXI_ARADDR (S_AXI_ACP_ARADDR), + .S_AXI_ARLEN (S_AXI_ACP_ARLEN), + .S_AXI_ARSIZE (S_AXI_ACP_ARSIZE), + .S_AXI_ARBURST (S_AXI_ACP_ARBURST), + .S_AXI_ARLOCK (S_AXI_ACP_ARLOCK), + .S_AXI_ARCACHE (S_AXI_ACP_ARCACHE), + .S_AXI_ARPROT (S_AXI_ACP_ARPROT), + //.S_AXI_ARUSER (S_AXI_ACP_ARUSER), + .S_AXI_ARUSER (param_aruser), + .S_AXI_ARVALID (S_AXI_ACP_ARVALID), + .S_AXI_ARREADY (S_AXI_ACP_ARREADY), + // Slave Interface Read Data Ports + .S_AXI_RID (S_AXI_ACP_RID), + .S_AXI_RDATA (S_AXI_ACP_RDATA), + .S_AXI_RRESP (S_AXI_ACP_RRESP), + .S_AXI_RLAST (S_AXI_ACP_RLAST), + .S_AXI_RUSER (), + .S_AXI_RVALID (S_AXI_ACP_RVALID), + .S_AXI_RREADY (S_AXI_ACP_RREADY), + + // Slave Interface Write Address Ports + .M_AXI_AWID (S_AXI_ATC_AWID), + .M_AXI_AWADDR (S_AXI_ATC_AWADDR), + .M_AXI_AWLEN (S_AXI_ATC_AWLEN), + .M_AXI_AWSIZE (S_AXI_ATC_AWSIZE), + .M_AXI_AWBURST (S_AXI_ATC_AWBURST), + .M_AXI_AWLOCK (S_AXI_ATC_AWLOCK), + .M_AXI_AWCACHE (S_AXI_ATC_AWCACHE), + .M_AXI_AWPROT (S_AXI_ATC_AWPROT), + .M_AXI_AWUSER (S_AXI_ATC_AWUSER), + .M_AXI_AWVALID (S_AXI_ATC_AWVALID), + .M_AXI_AWREADY (SAXIACPAWREADY_W), + // Slave Interface Write Data Ports + .M_AXI_WID (S_AXI_ATC_WID), + .M_AXI_WDATA (S_AXI_ATC_WDATA), + .M_AXI_WSTRB (S_AXI_ATC_WSTRB), + .M_AXI_WLAST (S_AXI_ATC_WLAST), + .M_AXI_WUSER (), + .M_AXI_WVALID (S_AXI_ATC_WVALID), + .M_AXI_WREADY (SAXIACPWREADY_W), + // Slave Interface Write Response Ports + .M_AXI_BID (SAXIACPBID_W), + .M_AXI_BRESP (SAXIACPBRESP_W), + .M_AXI_BUSER (), + .M_AXI_BVALID (SAXIACPBVALID_W), + .M_AXI_BREADY (S_AXI_ATC_BREADY), + // Slave Interface Read Address Ports + .M_AXI_ARID (S_AXI_ATC_ARID), + .M_AXI_ARADDR (S_AXI_ATC_ARADDR), + .M_AXI_ARLEN (S_AXI_ATC_ARLEN), + .M_AXI_ARSIZE (S_AXI_ATC_ARSIZE), + .M_AXI_ARBURST (S_AXI_ATC_ARBURST), + .M_AXI_ARLOCK (S_AXI_ATC_ARLOCK), + .M_AXI_ARCACHE (S_AXI_ATC_ARCACHE), + .M_AXI_ARPROT (S_AXI_ATC_ARPROT), + .M_AXI_ARUSER (S_AXI_ATC_ARUSER), + .M_AXI_ARVALID (S_AXI_ATC_ARVALID), + .M_AXI_ARREADY (SAXIACPARREADY_W), + // Slave Interface Read Data Ports + .M_AXI_RID (SAXIACPRID_W), + .M_AXI_RDATA (SAXIACPRDATA_W), + .M_AXI_RRESP (SAXIACPRRESP_W), + .M_AXI_RLAST (SAXIACPRLAST_W), + .M_AXI_RUSER (), + .M_AXI_RVALID (SAXIACPRVALID_W), + .M_AXI_RREADY (S_AXI_ATC_RREADY), + + + .ERROR_TRIGGER(), + .ERROR_TRANSACTION_ID() + ); + + + + end + endgenerate + + + + +endmodule + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.c b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.c new file mode 100644 index 0000000..3bcce86 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.c @@ -0,0 +1,10638 @@ +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h new file mode 100644 index 0000000..bb95e06 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 166666672 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 100000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl new file mode 100644 index 0000000..d0f4463 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init.tcl @@ -0,0 +1,781 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000158 0x00003F33 0x00000603 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000180 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FCCC0D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000000 + mask_write 0XF8006124 0x7FFFFFCF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x00007FFF 0x00000220 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x000006E0 + mask_write 0XF8000724 0x00003FFF 0x000016E1 + mask_write 0XF8000728 0x00003FFF 0x00000680 + mask_write 0XF800072C 0x00003FFF 0x00000680 + mask_write 0XF8000730 0x00003FFF 0x00000680 + mask_write 0XF8000734 0x00003FFF 0x00000680 + mask_write 0XF8000738 0x00003FFF 0x00000680 + mask_write 0XF800073C 0x00003FFF 0x00000680 + mask_write 0XF8000770 0x00003FFF 0x00001604 + mask_write 0XF8000774 0x00003FFF 0x00001605 + mask_write 0XF8000778 0x00003FFF 0x00001604 + mask_write 0XF800077C 0x00003FFF 0x00001605 + mask_write 0XF8000780 0x00003FFF 0x00001604 + mask_write 0XF8000784 0x00003FFF 0x00001604 + mask_write 0XF8000788 0x00003FFF 0x00001604 + mask_write 0XF800078C 0x00003FFF 0x00001604 + mask_write 0XF8000790 0x00003FFF 0x00001605 + mask_write 0XF8000794 0x00003FFF 0x00001604 + mask_write 0XF8000798 0x00003FFF 0x00001604 + mask_write 0XF800079C 0x00003FFF 0x00001604 + mask_write 0XF80007C0 0x00003FFF 0x00001640 + mask_write 0XF80007C4 0x00003FFF 0x00001640 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 + mask_write 0XF8000830 0x003F003F 0x00380037 + mask_write 0XF8000834 0x003F003F 0x00000039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000158 0x00003F33 0x00000603 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000180 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FCCC0D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000000 + mask_write 0XF8006124 0x7FFFFFFF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x00007FFF 0x00000220 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x000006E0 + mask_write 0XF8000724 0x00003FFF 0x000016E1 + mask_write 0XF8000728 0x00003FFF 0x00000680 + mask_write 0XF800072C 0x00003FFF 0x00000680 + mask_write 0XF8000730 0x00003FFF 0x00000680 + mask_write 0XF8000734 0x00003FFF 0x00000680 + mask_write 0XF8000738 0x00003FFF 0x00000680 + mask_write 0XF800073C 0x00003FFF 0x00000680 + mask_write 0XF8000770 0x00003FFF 0x00001604 + mask_write 0XF8000774 0x00003FFF 0x00001605 + mask_write 0XF8000778 0x00003FFF 0x00001604 + mask_write 0XF800077C 0x00003FFF 0x00001605 + mask_write 0XF8000780 0x00003FFF 0x00001604 + mask_write 0XF8000784 0x00003FFF 0x00001604 + mask_write 0XF8000788 0x00003FFF 0x00001604 + mask_write 0XF800078C 0x00003FFF 0x00001604 + mask_write 0XF8000790 0x00003FFF 0x00001605 + mask_write 0XF8000794 0x00003FFF 0x00001604 + mask_write 0XF8000798 0x00003FFF 0x00001604 + mask_write 0XF800079C 0x00003FFF 0x00001604 + mask_write 0XF80007C0 0x00003FFF 0x00001640 + mask_write 0XF80007C4 0x00003FFF 0x00001640 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 + mask_write 0XF8000830 0x003F003F 0x00380037 + mask_write 0XF8000834 0x003F003F 0x00000039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00000A03 + mask_write 0XF8000154 0x00003F33 0x00000A03 + mask_write 0XF8000158 0x00003F33 0x00000603 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00400500 + mask_write 0XF8000180 0x03F03F30 0x00200500 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01FCCC0D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004281B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000000 + mask_write 0XF8006124 0x7FFFFFFF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C068 + mask_write 0XF8000B60 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B64 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B68 0xFFFFFFFF 0x00F98068 + mask_write 0XF8000B6C 0x000073FF 0x00000220 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001601 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mask_write 0XF800071C 0x00003FFF 0x00000600 + mask_write 0XF8000720 0x00003FFF 0x000006E0 + mask_write 0XF8000724 0x00003FFF 0x000016E1 + mask_write 0XF8000728 0x00003FFF 0x00000680 + mask_write 0XF800072C 0x00003FFF 0x00000680 + mask_write 0XF8000730 0x00003FFF 0x00000680 + mask_write 0XF8000734 0x00003FFF 0x00000680 + mask_write 0XF8000738 0x00003FFF 0x00000680 + mask_write 0XF800073C 0x00003FFF 0x00000680 + mask_write 0XF8000770 0x00003FFF 0x00001604 + mask_write 0XF8000774 0x00003FFF 0x00001605 + mask_write 0XF8000778 0x00003FFF 0x00001604 + mask_write 0XF800077C 0x00003FFF 0x00001605 + mask_write 0XF8000780 0x00003FFF 0x00001604 + mask_write 0XF8000784 0x00003FFF 0x00001604 + mask_write 0XF8000788 0x00003FFF 0x00001604 + mask_write 0XF800078C 0x00003FFF 0x00001604 + mask_write 0XF8000790 0x00003FFF 0x00001605 + mask_write 0XF8000794 0x00003FFF 0x00001604 + mask_write 0XF8000798 0x00003FFF 0x00001604 + mask_write 0XF800079C 0x00003FFF 0x00001604 + mask_write 0XF80007C0 0x00003FFF 0x00001640 + mask_write 0XF80007C4 0x00003FFF 0x00001640 + mask_write 0XF80007D0 0x00003FFF 0x00001600 + mask_write 0XF80007D4 0x00003FFF 0x00001600 + mask_write 0XF8000830 0x003F003F 0x00380037 + mask_write 0XF8000834 0x003F003F 0x00000039 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000007C + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE0000034 0x000000FF 0x00000006 + mask_write 0XE0000018 0x0000FFFF 0x0000007C + mask_write 0XE0000000 0x000001FF 0x00000017 + mask_write 0XE0000004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00000080 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.c b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.c new file mode 100644 index 0000000..52d7d38 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.c @@ -0,0 +1,10629 @@ +/****************************************************************************** +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License along +* with this program; if not, see +* +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init_gpl.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init_gpl.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x270872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F03FU ,0x0003C008U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. reserved_DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. reserved_DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. .. START: AFI2 SECURE REGISTER + // .. .. FINISH: AFI2 SECURE REGISTER + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x0 + // .. ==> 0XF8000B6C[11:10] = 0x00000000U + // .. ==> MASK : 0x00000C00U VAL : 0x00000000U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0xf + // .. ==> 0XF8000128[13:8] = 0x0000000FU + // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U + // .. DIVISOR1 = 0x7 + // .. ==> 0XF8000128[25:20] = 0x00000007U + // .. ==> MASK : 0x03F00000U VAL : 0x00700000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000150[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000150[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000154[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0xa + // .. ==> 0XF8000154[13:8] = 0x0000000AU + // .. ==> MASK : 0x00003F00U VAL : 0x00000A00U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00000A03U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000158[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000158[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x6 + // .. ==> 0XF8000158[13:8] = 0x00000006U + // .. ==> MASK : 0x00003F00U VAL : 0x00000600U + // .. + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000603U), + // .. .. START: TRACE CLOCK + // .. .. FINISH: TRACE CLOCK + // .. .. CLKACT = 0x1 + // .. .. ==> 0XF8000168[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000168[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR = 0x5 + // .. .. ==> 0XF8000168[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000170[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000170[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x4 + // .. .. ==> 0XF8000170[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), + // .. .. SRCSEL = 0x0 + // .. .. ==> 0XF8000180[5:4] = 0x00000000U + // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. DIVISOR0 = 0x5 + // .. .. ==> 0XF8000180[13:8] = 0x00000005U + // .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. .. DIVISOR1 = 0x2 + // .. .. ==> 0XF8000180[25:20] = 0x00000002U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00200500U), + // .. .. CLK_621_TRUE = 0x1 + // .. .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. .. DMA_CPU_2XCLKACT = 0x1 + // .. .. ==> 0XF800012C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. USB0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[2:2] = 0x00000001U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. USB1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. GEM0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. GEM1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. SDI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[10:10] = 0x00000001U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. .. SDI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[11:11] = 0x00000001U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. .. SPI0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. CAN0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. CAN1_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. I2C0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[18:18] = 0x00000001U + // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. .. I2C1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. UART0_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[20:20] = 0x00000001U + // .. .. ==> MASK : 0x00100000U VAL : 0x00100000U + // .. .. UART1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. GPIO_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[22:22] = 0x00000001U + // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. .. LQSPI_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[23:23] = 0x00000001U + // .. .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. .. SMC_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[24:24] = 0x00000001U + // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01FCCC0DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000084U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0xa0 + // .. .. ==> 0XF8006014[13:6] = 0x000000A0U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00002800U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004281BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x16 + // .. .. ==> 0XF8006018[15:10] = 0x00000016U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00005800U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x13 + // .. .. ==> 0XF8006018[26:22] = 0x00000013U + // .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x44E458D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x6 + // .. .. ==> 0XF8006020[7:5] = 0x00000006U + // .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x272872D0U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x16d + // .. .. ==> 0XF8006034[13:4] = 0x0000016DU + // .. .. ==> MASK : 0x00003FF0U VAL : 0x000016D0U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x000116D4U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x6 + // .. .. ==> 0XF800603C[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x6 + // .. .. ==> 0XF800603C[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x6 + // .. .. ==> 0XF800603C[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000666U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0xf + // .. .. ==> 0XF8006040[19:16] = 0x0000000FU + // .. .. ==> MASK : 0x000F0000U VAL : 0x000F0000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFFF0000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x5 + // .. .. ==> 0XF8006044[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_addrmap_row_b1 = 0x5 + // .. .. ==> 0XF8006044[7:4] = 0x00000005U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000050U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x5 + // .. .. ==> 0XF8006044[11:8] = 0x00000005U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000500U + // .. .. reg_ddrc_addrmap_row_b12 = 0x5 + // .. .. ==> 0XF8006044[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x5 + // .. .. ==> 0XF8006044[19:16] = 0x00000005U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00050000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x5 + // .. .. ==> 0XF8006044[23:20] = 0x00000005U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00500000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F555555U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006120[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_data_slice_in_use = 0x0 + // .. .. ==> 0XF8006124[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF800612C[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF800612C[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006130[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006130[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006134[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006134[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_wrlvl_init_ratio = 0x0 + // .. .. ==> 0XF8006138[9:0] = 0x00000000U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U + // .. .. reg_phy_gatelvl_init_ratio = 0xa4 + // .. .. ==> 0XF8006138[19:10] = 0x000000A4U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00029000U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x00029000U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006154[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006158[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF800615C[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x80 + // .. .. ==> 0XF8006160[9:0] = 0x00000080U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000080U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x00000080U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006168[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF800616C[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006170[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_fifo_we_slave_ratio = 0xf9 + // .. .. ==> 0XF8006174[10:0] = 0x000000F9U + // .. .. ==> MASK : 0x000007FFU VAL : 0x000000F9U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x000000F9U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF800617C[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006180[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006184[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_wr_data_slave_ratio = 0xc0 + // .. .. ==> 0XF8006188[9:0] = 0x000000C0U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000C0U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000C0U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x1 + // .. .. ==> 0XF8006000[3:2] = 0x00000001U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000004U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000085U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B4C[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B4C[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B4C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B4C[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B4C[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B54[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B54[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B54[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x0 + // .. ==> 0XF8000B54[10:9] = 0x00000000U + // .. ==> MASK : 0x00000600U VAL : 0x00000000U + // .. PULLUP_EN = 0x1 + // .. ==> 0XF8000B54[11:11] = 0x00000001U + // .. ==> MASK : 0x00000800U VAL : 0x00000800U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000800U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B5C[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B5C[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B60[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B60[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B64[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B64[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F98068U), + // .. DRIVE_P = 0x68 + // .. ==> 0XF8000B68[6:0] = 0x00000068U + // .. ==> MASK : 0x0000007FU VAL : 0x00000068U + // .. DRIVE_N = 0x0 + // .. ==> 0XF8000B68[13:7] = 0x00000000U + // .. ==> MASK : 0x00003F80U VAL : 0x00000000U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F98068U), + // .. VREF_INT_EN = 0x0 + // .. ==> 0XF8000B6C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B6C[4:1] = 0x00000000U + // .. ==> MASK : 0x0000001EU VAL : 0x00000000U + // .. VREF_EXT_EN = 0x1 + // .. ==> 0XF8000B6C[6:5] = 0x00000001U + // .. ==> MASK : 0x00000060U VAL : 0x00000020U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000220U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000700[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001601U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000704[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000708[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800070C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000710[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000714[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000718[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000602U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800071C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000720[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000720[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000720[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x000006E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000724[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF8000724[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000724[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x000016E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000728[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000728[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000728[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800072C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800072C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800072C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000730[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000730[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000730[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000734[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000734[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000734[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF8000738[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000738[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF8000738[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800073C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800073C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800073C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800073C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF800073C[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800073C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 0 + // .. ==> 0XF800073C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003FFFU ,0x00000680U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000770[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000770[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000774[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000774[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000778[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000778[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800077C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800077C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000780[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000780[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000784[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000784[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000788[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000788[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800078C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800078C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000790[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000790[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00001605U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000794[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000794[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF8000798[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF8000798[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF800079C[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF800079C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00001604U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C0[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C4[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007C4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007C4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x00001640U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D0[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D0[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D0[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00001600U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF80007D4[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 3 + // .. ==> 0XF80007D4[11:9] = 0x00000003U + // .. ==> MASK : 0x00000E00U VAL : 0x00000600U + // .. PULLUP = 1 + // .. ==> 0XF80007D4[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00001600U), + // .. SDIO0_WP_SEL = 55 + // .. ==> 0XF8000830[5:0] = 0x00000037U + // .. ==> MASK : 0x0000003FU VAL : 0x00000037U + // .. SDIO0_CD_SEL = 56 + // .. ==> 0XF8000830[21:16] = 0x00000038U + // .. ==> MASK : 0x003F0000U VAL : 0x00380000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), + // .. SDIO1_WP_SEL = 57 + // .. ==> 0XF8000834[5:0] = 0x00000039U + // .. ==> MASK : 0x0000003FU VAL : 0x00000039U + // .. SDIO1_CD_SEL = 0 + // .. ==> 0XF8000834[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000834, 0x003F003FU ,0x00000039U), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000000U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000000U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0001018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. BDIV = 0x6 + // .. ==> 0XE0000034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0000034, 0x000000FFU ,0x00000006U), + // .. CD = 0x7c + // .. ==> 0XE0000018[15:0] = 0x0000007CU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU + // .. + EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU ,0x0000007CU), + // .. STPBRK = 0x0 + // .. ==> 0XE0000000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0000000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0000000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0000000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0000000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0000000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0000000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0000000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0000000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0000000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0000004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0000004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0000004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0000004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0000004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0000004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0000004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0000004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: USB0 RESET + // .. .. .. .. START: DIR MODE BANK 0 + // .. .. .. .. DIRECTION_0 = 0x80 + // .. .. .. .. ==> 0XE000A204[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. .. START: DIR MODE BANK 1 + // .. .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. .. OP_ENABLE_0 = 0x80 + // .. .. .. .. ==> 0XE000A208[31:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00000080U), + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x0 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. .. START: ADD 1 MS DELAY + // .. .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. .. DATA_0_LSW = 0x80 + // .. .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: USB0 RESET + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. FINISH: I2C RESET + // .. .. START: NOR CHIP SELECT + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. FINISH: NOR CHIP SELECT + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_WRITE(0XF8000008, 0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_WRITE(0XF8000004, 0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h new file mode 100644 index 0000000..bb95e06 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_init_gpl.h @@ -0,0 +1,137 @@ + +/****************************************************************************** +* +* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy of this +* software and associated documentation files (the "Software"), to deal in the Software +* without restriction, including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, and to permit +* persons to whom the Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in all copies or +* substantial portions of the Software. +* +* Use of the Software is limited solely to applications: (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING +* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +* NONINFRINGEMENT. IN NO EVENT SHALL THE X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used in advertising or +* otherwise to promote the sale, use or other dealings in this Software without prior written +* authorization from Xilinx. +* +*******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158730 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 125000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 100000000 +#define UART_FREQ 100000000 +#define SPI_FREQ 166666672 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 10000000 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 100000000 +#define FPGA2_FREQ 10000000 +#define FPGA3_FREQ 10000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml new file mode 100644 index 0000000..d2f7bcd --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/ps7_parameters.xml @@ -0,0 +1,643 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v new file mode 100644 index 0000000..65b0825 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/sim/design_1_processing_system7_0_0.v @@ -0,0 +1,704 @@ + + + +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0 +// IP Revision: 1 + +`timescale 1ns/1ps + +module design_1_processing_system7_0_0 ( +GPIO_I, +GPIO_O, +GPIO_T, +I2C0_SDA_I, +I2C0_SDA_O, +I2C0_SDA_T, +I2C0_SCL_I, +I2C0_SCL_O, +I2C0_SCL_T, +SDIO0_CLK, +SDIO0_CLK_FB, +SDIO0_CMD_O, +SDIO0_CMD_I, +SDIO0_CMD_T, +SDIO0_DATA_I, +SDIO0_DATA_O, +SDIO0_DATA_T, +SDIO0_LED, +SDIO0_CDN, +SDIO0_WP, +SDIO0_BUSPOW, +SDIO0_BUSVOLT, +SPI0_SCLK_I, +SPI0_SCLK_O, +SPI0_SCLK_T, +SPI0_MOSI_I, +SPI0_MOSI_O, +SPI0_MOSI_T, +SPI0_MISO_I, +SPI0_MISO_O, +SPI0_MISO_T, +SPI0_SS_I, +SPI0_SS_O, +SPI0_SS1_O, +SPI0_SS2_O, +SPI0_SS_T, +SPI1_SCLK_I, +SPI1_SCLK_O, +SPI1_SCLK_T, +SPI1_MOSI_I, +SPI1_MOSI_O, +SPI1_MOSI_T, +SPI1_MISO_I, +SPI1_MISO_O, +SPI1_MISO_T, +SPI1_SS_I, +SPI1_SS_O, +SPI1_SS1_O, +SPI1_SS2_O, +SPI1_SS_T, +UART0_TX, +UART0_RX, +TTC0_WAVE0_OUT, +TTC0_WAVE1_OUT, +TTC0_WAVE2_OUT, +TTC1_WAVE0_OUT, +TTC1_WAVE1_OUT, +TTC1_WAVE2_OUT, +USB0_PORT_INDCTL, +USB0_VBUS_PWRSELECT, +USB0_VBUS_PWRFAULT, +M_AXI_GP0_ARVALID, +M_AXI_GP0_AWVALID, +M_AXI_GP0_BREADY, +M_AXI_GP0_RREADY, +M_AXI_GP0_WLAST, +M_AXI_GP0_WVALID, +M_AXI_GP0_ARID, +M_AXI_GP0_AWID, +M_AXI_GP0_WID, +M_AXI_GP0_ARBURST, +M_AXI_GP0_ARLOCK, +M_AXI_GP0_ARSIZE, +M_AXI_GP0_AWBURST, +M_AXI_GP0_AWLOCK, +M_AXI_GP0_AWSIZE, +M_AXI_GP0_ARPROT, +M_AXI_GP0_AWPROT, +M_AXI_GP0_ARADDR, +M_AXI_GP0_AWADDR, +M_AXI_GP0_WDATA, +M_AXI_GP0_ARCACHE, +M_AXI_GP0_ARLEN, +M_AXI_GP0_ARQOS, +M_AXI_GP0_AWCACHE, +M_AXI_GP0_AWLEN, +M_AXI_GP0_AWQOS, +M_AXI_GP0_WSTRB, +M_AXI_GP0_ACLK, +M_AXI_GP0_ARREADY, +M_AXI_GP0_AWREADY, +M_AXI_GP0_BVALID, +M_AXI_GP0_RLAST, +M_AXI_GP0_RVALID, +M_AXI_GP0_WREADY, +M_AXI_GP0_BID, +M_AXI_GP0_RID, +M_AXI_GP0_BRESP, +M_AXI_GP0_RRESP, +M_AXI_GP0_RDATA, +IRQ_F2P, +FCLK_CLK0, +FCLK_CLK1, +FCLK_RESET0_N, +MIO, +DDR_CAS_n, +DDR_CKE, +DDR_Clk_n, +DDR_Clk, +DDR_CS_n, +DDR_DRSTB, +DDR_ODT, +DDR_RAS_n, +DDR_WEB, +DDR_BankAddr, +DDR_Addr, +DDR_VRN, +DDR_VRP, +DDR_DM, +DDR_DQ, +DDR_DQS_n, +DDR_DQS, +PS_SRSTB, +PS_CLK, +PS_PORB +); +input [63 : 0] GPIO_I; +output [63 : 0] GPIO_O; +output [63 : 0] GPIO_T; +input I2C0_SDA_I; +output I2C0_SDA_O; +output I2C0_SDA_T; +input I2C0_SCL_I; +output I2C0_SCL_O; +output I2C0_SCL_T; +output SDIO0_CLK; +input SDIO0_CLK_FB; +output SDIO0_CMD_O; +input SDIO0_CMD_I; +output SDIO0_CMD_T; +input [3 : 0] SDIO0_DATA_I; +output [3 : 0] SDIO0_DATA_O; +output [3 : 0] SDIO0_DATA_T; +output SDIO0_LED; +input SDIO0_CDN; +input SDIO0_WP; +output SDIO0_BUSPOW; +output [2 : 0] SDIO0_BUSVOLT; +input SPI0_SCLK_I; +output SPI0_SCLK_O; +output SPI0_SCLK_T; +input SPI0_MOSI_I; +output SPI0_MOSI_O; +output SPI0_MOSI_T; +input SPI0_MISO_I; +output SPI0_MISO_O; +output SPI0_MISO_T; +input SPI0_SS_I; +output SPI0_SS_O; +output SPI0_SS1_O; +output SPI0_SS2_O; +output SPI0_SS_T; +input SPI1_SCLK_I; +output SPI1_SCLK_O; +output SPI1_SCLK_T; +input SPI1_MOSI_I; +output SPI1_MOSI_O; +output SPI1_MOSI_T; +input SPI1_MISO_I; +output SPI1_MISO_O; +output SPI1_MISO_T; +input SPI1_SS_I; +output SPI1_SS_O; +output SPI1_SS1_O; +output SPI1_SS2_O; +output SPI1_SS_T; +output UART0_TX; +input UART0_RX; +output TTC0_WAVE0_OUT; +output TTC0_WAVE1_OUT; +output TTC0_WAVE2_OUT; +output TTC1_WAVE0_OUT; +output TTC1_WAVE1_OUT; +output TTC1_WAVE2_OUT; +output [1 : 0] USB0_PORT_INDCTL; +output USB0_VBUS_PWRSELECT; +input USB0_VBUS_PWRFAULT; +output M_AXI_GP0_ARVALID; +output M_AXI_GP0_AWVALID; +output M_AXI_GP0_BREADY; +output M_AXI_GP0_RREADY; +output M_AXI_GP0_WLAST; +output M_AXI_GP0_WVALID; +output [11 : 0] M_AXI_GP0_ARID; +output [11 : 0] M_AXI_GP0_AWID; +output [11 : 0] M_AXI_GP0_WID; +output [1 : 0] M_AXI_GP0_ARBURST; +output [1 : 0] M_AXI_GP0_ARLOCK; +output [2 : 0] M_AXI_GP0_ARSIZE; +output [1 : 0] M_AXI_GP0_AWBURST; +output [1 : 0] M_AXI_GP0_AWLOCK; +output [2 : 0] M_AXI_GP0_AWSIZE; +output [2 : 0] M_AXI_GP0_ARPROT; +output [2 : 0] M_AXI_GP0_AWPROT; +output [31 : 0] M_AXI_GP0_ARADDR; +output [31 : 0] M_AXI_GP0_AWADDR; +output [31 : 0] M_AXI_GP0_WDATA; +output [3 : 0] M_AXI_GP0_ARCACHE; +output [3 : 0] M_AXI_GP0_ARLEN; +output [3 : 0] M_AXI_GP0_ARQOS; +output [3 : 0] M_AXI_GP0_AWCACHE; +output [3 : 0] M_AXI_GP0_AWLEN; +output [3 : 0] M_AXI_GP0_AWQOS; +output [3 : 0] M_AXI_GP0_WSTRB; +input M_AXI_GP0_ACLK; +input M_AXI_GP0_ARREADY; +input M_AXI_GP0_AWREADY; +input M_AXI_GP0_BVALID; +input M_AXI_GP0_RLAST; +input M_AXI_GP0_RVALID; +input M_AXI_GP0_WREADY; +input [11 : 0] M_AXI_GP0_BID; +input [11 : 0] M_AXI_GP0_RID; +input [1 : 0] M_AXI_GP0_BRESP; +input [1 : 0] M_AXI_GP0_RRESP; +input [31 : 0] M_AXI_GP0_RDATA; +input [0 : 0] IRQ_F2P; +output FCLK_CLK0; +output FCLK_CLK1; +output FCLK_RESET0_N; +input [31 : 0] MIO; +input DDR_CAS_n; +input DDR_CKE; +input DDR_Clk_n; +input DDR_Clk; +input DDR_CS_n; +input DDR_DRSTB; +input DDR_ODT; +input DDR_RAS_n; +input DDR_WEB; +input [2 : 0] DDR_BankAddr; +input [14 : 0] DDR_Addr; +input DDR_VRN; +input DDR_VRP; +input [1 : 0] DDR_DM; +input [15 : 0] DDR_DQ; +input [1 : 0] DDR_DQS_n; +input [1 : 0] DDR_DQS; +input PS_SRSTB; +input PS_CLK; +input PS_PORB; + + processing_system7_vip_v1_0_5 #( + .C_USE_M_AXI_GP0(1), + .C_USE_M_AXI_GP1(0), + .C_USE_S_AXI_ACP(0), + .C_USE_S_AXI_GP0(0), + .C_USE_S_AXI_GP1(0), + .C_USE_S_AXI_HP0(0), + .C_USE_S_AXI_HP1(0), + .C_USE_S_AXI_HP2(0), + .C_USE_S_AXI_HP3(0), + .C_S_AXI_HP0_DATA_WIDTH(64), + .C_S_AXI_HP1_DATA_WIDTH(64), + .C_S_AXI_HP2_DATA_WIDTH(64), + .C_S_AXI_HP3_DATA_WIDTH(64), + .C_HIGH_OCM_EN(0), + .C_FCLK_CLK0_FREQ(50.0), + .C_FCLK_CLK1_FREQ(100.0), + .C_FCLK_CLK2_FREQ(10.0), + .C_FCLK_CLK3_FREQ(10.0), + .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP0_THREAD_ID_WIDTH (12), + .C_M_AXI_GP1_THREAD_ID_WIDTH (12) + ) inst ( + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP1_ARVALID(), + .M_AXI_GP1_AWVALID(), + .M_AXI_GP1_BREADY(), + .M_AXI_GP1_RREADY(), + .M_AXI_GP1_WLAST(), + .M_AXI_GP1_WVALID(), + .M_AXI_GP1_ARID(), + .M_AXI_GP1_AWID(), + .M_AXI_GP1_WID(), + .M_AXI_GP1_ARBURST(), + .M_AXI_GP1_ARLOCK(), + .M_AXI_GP1_ARSIZE(), + .M_AXI_GP1_AWBURST(), + .M_AXI_GP1_AWLOCK(), + .M_AXI_GP1_AWSIZE(), + .M_AXI_GP1_ARPROT(), + .M_AXI_GP1_AWPROT(), + .M_AXI_GP1_ARADDR(), + .M_AXI_GP1_AWADDR(), + .M_AXI_GP1_WDATA(), + .M_AXI_GP1_ARCACHE(), + .M_AXI_GP1_ARLEN(), + .M_AXI_GP1_ARQOS(), + .M_AXI_GP1_AWCACHE(), + .M_AXI_GP1_AWLEN(), + .M_AXI_GP1_AWQOS(), + .M_AXI_GP1_WSTRB(), + .M_AXI_GP1_ACLK(1'B0), + .M_AXI_GP1_ARREADY(1'B0), + .M_AXI_GP1_AWREADY(1'B0), + .M_AXI_GP1_BVALID(1'B0), + .M_AXI_GP1_RLAST(1'B0), + .M_AXI_GP1_RVALID(1'B0), + .M_AXI_GP1_WREADY(1'B0), + .M_AXI_GP1_BID(12'B0), + .M_AXI_GP1_RID(12'B0), + .M_AXI_GP1_BRESP(2'B0), + .M_AXI_GP1_RRESP(2'B0), + .M_AXI_GP1_RDATA(32'B0), + .S_AXI_GP0_ARREADY(), + .S_AXI_GP0_AWREADY(), + .S_AXI_GP0_BVALID(), + .S_AXI_GP0_RLAST(), + .S_AXI_GP0_RVALID(), + .S_AXI_GP0_WREADY(), + .S_AXI_GP0_BRESP(), + .S_AXI_GP0_RRESP(), + .S_AXI_GP0_RDATA(), + .S_AXI_GP0_BID(), + .S_AXI_GP0_RID(), + .S_AXI_GP0_ACLK(1'B0), + .S_AXI_GP0_ARVALID(1'B0), + .S_AXI_GP0_AWVALID(1'B0), + .S_AXI_GP0_BREADY(1'B0), + .S_AXI_GP0_RREADY(1'B0), + .S_AXI_GP0_WLAST(1'B0), + .S_AXI_GP0_WVALID(1'B0), + .S_AXI_GP0_ARBURST(2'B0), + .S_AXI_GP0_ARLOCK(2'B0), + .S_AXI_GP0_ARSIZE(3'B0), + .S_AXI_GP0_AWBURST(2'B0), + .S_AXI_GP0_AWLOCK(2'B0), + .S_AXI_GP0_AWSIZE(3'B0), + .S_AXI_GP0_ARPROT(3'B0), + .S_AXI_GP0_AWPROT(3'B0), + .S_AXI_GP0_ARADDR(32'B0), + .S_AXI_GP0_AWADDR(32'B0), + .S_AXI_GP0_WDATA(32'B0), + .S_AXI_GP0_ARCACHE(4'B0), + .S_AXI_GP0_ARLEN(4'B0), + .S_AXI_GP0_ARQOS(4'B0), + .S_AXI_GP0_AWCACHE(4'B0), + .S_AXI_GP0_AWLEN(4'B0), + .S_AXI_GP0_AWQOS(4'B0), + .S_AXI_GP0_WSTRB(4'B0), + .S_AXI_GP0_ARID(6'B0), + .S_AXI_GP0_AWID(6'B0), + .S_AXI_GP0_WID(6'B0), + .S_AXI_GP1_ARREADY(), + .S_AXI_GP1_AWREADY(), + .S_AXI_GP1_BVALID(), + .S_AXI_GP1_RLAST(), + .S_AXI_GP1_RVALID(), + .S_AXI_GP1_WREADY(), + .S_AXI_GP1_BRESP(), + .S_AXI_GP1_RRESP(), + .S_AXI_GP1_RDATA(), + .S_AXI_GP1_BID(), + .S_AXI_GP1_RID(), + .S_AXI_GP1_ACLK(1'B0), + .S_AXI_GP1_ARVALID(1'B0), + .S_AXI_GP1_AWVALID(1'B0), + .S_AXI_GP1_BREADY(1'B0), + .S_AXI_GP1_RREADY(1'B0), + .S_AXI_GP1_WLAST(1'B0), + .S_AXI_GP1_WVALID(1'B0), + .S_AXI_GP1_ARBURST(2'B0), + .S_AXI_GP1_ARLOCK(2'B0), + .S_AXI_GP1_ARSIZE(3'B0), + .S_AXI_GP1_AWBURST(2'B0), + .S_AXI_GP1_AWLOCK(2'B0), + .S_AXI_GP1_AWSIZE(3'B0), + .S_AXI_GP1_ARPROT(3'B0), + .S_AXI_GP1_AWPROT(3'B0), + .S_AXI_GP1_ARADDR(32'B0), + .S_AXI_GP1_AWADDR(32'B0), + .S_AXI_GP1_WDATA(32'B0), + .S_AXI_GP1_ARCACHE(4'B0), + .S_AXI_GP1_ARLEN(4'B0), + .S_AXI_GP1_ARQOS(4'B0), + .S_AXI_GP1_AWCACHE(4'B0), + .S_AXI_GP1_AWLEN(4'B0), + .S_AXI_GP1_AWQOS(4'B0), + .S_AXI_GP1_WSTRB(4'B0), + .S_AXI_GP1_ARID(6'B0), + .S_AXI_GP1_AWID(6'B0), + .S_AXI_GP1_WID(6'B0), + .S_AXI_ACP_ARREADY(), + .S_AXI_ACP_AWREADY(), + .S_AXI_ACP_BVALID(), + .S_AXI_ACP_RLAST(), + .S_AXI_ACP_RVALID(), + .S_AXI_ACP_WREADY(), + .S_AXI_ACP_BRESP(), + .S_AXI_ACP_RRESP(), + .S_AXI_ACP_BID(), + .S_AXI_ACP_RID(), + .S_AXI_ACP_RDATA(), + .S_AXI_ACP_ACLK(1'B0), + .S_AXI_ACP_ARVALID(1'B0), + .S_AXI_ACP_AWVALID(1'B0), + .S_AXI_ACP_BREADY(1'B0), + .S_AXI_ACP_RREADY(1'B0), + .S_AXI_ACP_WLAST(1'B0), + .S_AXI_ACP_WVALID(1'B0), + .S_AXI_ACP_ARID(3'B0), + .S_AXI_ACP_ARPROT(3'B0), + .S_AXI_ACP_AWID(3'B0), + .S_AXI_ACP_AWPROT(3'B0), + .S_AXI_ACP_WID(3'B0), + .S_AXI_ACP_ARADDR(32'B0), + .S_AXI_ACP_AWADDR(32'B0), + .S_AXI_ACP_ARCACHE(4'B0), + .S_AXI_ACP_ARLEN(4'B0), + .S_AXI_ACP_ARQOS(4'B0), + .S_AXI_ACP_AWCACHE(4'B0), + .S_AXI_ACP_AWLEN(4'B0), + .S_AXI_ACP_AWQOS(4'B0), + .S_AXI_ACP_ARBURST(2'B0), + .S_AXI_ACP_ARLOCK(2'B0), + .S_AXI_ACP_ARSIZE(3'B0), + .S_AXI_ACP_AWBURST(2'B0), + .S_AXI_ACP_AWLOCK(2'B0), + .S_AXI_ACP_AWSIZE(3'B0), + .S_AXI_ACP_ARUSER(5'B0), + .S_AXI_ACP_AWUSER(5'B0), + .S_AXI_ACP_WDATA(64'B0), + .S_AXI_ACP_WSTRB(8'B0), + .S_AXI_HP0_ARREADY(), + .S_AXI_HP0_AWREADY(), + .S_AXI_HP0_BVALID(), + .S_AXI_HP0_RLAST(), + .S_AXI_HP0_RVALID(), + .S_AXI_HP0_WREADY(), + .S_AXI_HP0_BRESP(), + .S_AXI_HP0_RRESP(), + .S_AXI_HP0_BID(), + .S_AXI_HP0_RID(), + .S_AXI_HP0_RDATA(), + .S_AXI_HP0_ACLK(1'B0), + .S_AXI_HP0_ARVALID(1'B0), + .S_AXI_HP0_AWVALID(1'B0), + .S_AXI_HP0_BREADY(1'B0), + .S_AXI_HP0_RREADY(1'B0), + .S_AXI_HP0_WLAST(1'B0), + .S_AXI_HP0_WVALID(1'B0), + .S_AXI_HP0_ARBURST(2'B0), + .S_AXI_HP0_ARLOCK(2'B0), + .S_AXI_HP0_ARSIZE(3'B0), + .S_AXI_HP0_AWBURST(2'B0), + .S_AXI_HP0_AWLOCK(2'B0), + .S_AXI_HP0_AWSIZE(3'B0), + .S_AXI_HP0_ARPROT(3'B0), + .S_AXI_HP0_AWPROT(3'B0), + .S_AXI_HP0_ARADDR(32'B0), + .S_AXI_HP0_AWADDR(32'B0), + .S_AXI_HP0_ARCACHE(4'B0), + .S_AXI_HP0_ARLEN(4'B0), + .S_AXI_HP0_ARQOS(4'B0), + .S_AXI_HP0_AWCACHE(4'B0), + .S_AXI_HP0_AWLEN(4'B0), + .S_AXI_HP0_AWQOS(4'B0), + .S_AXI_HP0_ARID(6'B0), + .S_AXI_HP0_AWID(6'B0), + .S_AXI_HP0_WID(6'B0), + .S_AXI_HP0_WDATA(64'B0), + .S_AXI_HP0_WSTRB(8'B0), + .S_AXI_HP1_ARREADY(), + .S_AXI_HP1_AWREADY(), + .S_AXI_HP1_BVALID(), + .S_AXI_HP1_RLAST(), + .S_AXI_HP1_RVALID(), + .S_AXI_HP1_WREADY(), + .S_AXI_HP1_BRESP(), + .S_AXI_HP1_RRESP(), + .S_AXI_HP1_BID(), + .S_AXI_HP1_RID(), + .S_AXI_HP1_RDATA(), + .S_AXI_HP1_ACLK(1'B0), + .S_AXI_HP1_ARVALID(1'B0), + .S_AXI_HP1_AWVALID(1'B0), + .S_AXI_HP1_BREADY(1'B0), + .S_AXI_HP1_RREADY(1'B0), + .S_AXI_HP1_WLAST(1'B0), + .S_AXI_HP1_WVALID(1'B0), + .S_AXI_HP1_ARBURST(2'B0), + .S_AXI_HP1_ARLOCK(2'B0), + .S_AXI_HP1_ARSIZE(3'B0), + .S_AXI_HP1_AWBURST(2'B0), + .S_AXI_HP1_AWLOCK(2'B0), + .S_AXI_HP1_AWSIZE(3'B0), + .S_AXI_HP1_ARPROT(3'B0), + .S_AXI_HP1_AWPROT(3'B0), + .S_AXI_HP1_ARADDR(32'B0), + .S_AXI_HP1_AWADDR(32'B0), + .S_AXI_HP1_ARCACHE(4'B0), + .S_AXI_HP1_ARLEN(4'B0), + .S_AXI_HP1_ARQOS(4'B0), + .S_AXI_HP1_AWCACHE(4'B0), + .S_AXI_HP1_AWLEN(4'B0), + .S_AXI_HP1_AWQOS(4'B0), + .S_AXI_HP1_ARID(6'B0), + .S_AXI_HP1_AWID(6'B0), + .S_AXI_HP1_WID(6'B0), + .S_AXI_HP1_WDATA(64'B0), + .S_AXI_HP1_WSTRB(8'B0), + .S_AXI_HP2_ARREADY(), + .S_AXI_HP2_AWREADY(), + .S_AXI_HP2_BVALID(), + .S_AXI_HP2_RLAST(), + .S_AXI_HP2_RVALID(), + .S_AXI_HP2_WREADY(), + .S_AXI_HP2_BRESP(), + .S_AXI_HP2_RRESP(), + .S_AXI_HP2_BID(), + .S_AXI_HP2_RID(), + .S_AXI_HP2_RDATA(), + .S_AXI_HP2_ACLK(1'B0), + .S_AXI_HP2_ARVALID(1'B0), + .S_AXI_HP2_AWVALID(1'B0), + .S_AXI_HP2_BREADY(1'B0), + .S_AXI_HP2_RREADY(1'B0), + .S_AXI_HP2_WLAST(1'B0), + .S_AXI_HP2_WVALID(1'B0), + .S_AXI_HP2_ARBURST(2'B0), + .S_AXI_HP2_ARLOCK(2'B0), + .S_AXI_HP2_ARSIZE(3'B0), + .S_AXI_HP2_AWBURST(2'B0), + .S_AXI_HP2_AWLOCK(2'B0), + .S_AXI_HP2_AWSIZE(3'B0), + .S_AXI_HP2_ARPROT(3'B0), + .S_AXI_HP2_AWPROT(3'B0), + .S_AXI_HP2_ARADDR(32'B0), + .S_AXI_HP2_AWADDR(32'B0), + .S_AXI_HP2_ARCACHE(4'B0), + .S_AXI_HP2_ARLEN(4'B0), + .S_AXI_HP2_ARQOS(4'B0), + .S_AXI_HP2_AWCACHE(4'B0), + .S_AXI_HP2_AWLEN(4'B0), + .S_AXI_HP2_AWQOS(4'B0), + .S_AXI_HP2_ARID(6'B0), + .S_AXI_HP2_AWID(6'B0), + .S_AXI_HP2_WID(6'B0), + .S_AXI_HP2_WDATA(64'B0), + .S_AXI_HP2_WSTRB(8'B0), + .S_AXI_HP3_ARREADY(), + .S_AXI_HP3_AWREADY(), + .S_AXI_HP3_BVALID(), + .S_AXI_HP3_RLAST(), + .S_AXI_HP3_RVALID(), + .S_AXI_HP3_WREADY(), + .S_AXI_HP3_BRESP(), + .S_AXI_HP3_RRESP(), + .S_AXI_HP3_BID(), + .S_AXI_HP3_RID(), + .S_AXI_HP3_RDATA(), + .S_AXI_HP3_ACLK(1'B0), + .S_AXI_HP3_ARVALID(1'B0), + .S_AXI_HP3_AWVALID(1'B0), + .S_AXI_HP3_BREADY(1'B0), + .S_AXI_HP3_RREADY(1'B0), + .S_AXI_HP3_WLAST(1'B0), + .S_AXI_HP3_WVALID(1'B0), + .S_AXI_HP3_ARBURST(2'B0), + .S_AXI_HP3_ARLOCK(2'B0), + .S_AXI_HP3_ARSIZE(3'B0), + .S_AXI_HP3_AWBURST(2'B0), + .S_AXI_HP3_AWLOCK(2'B0), + .S_AXI_HP3_AWSIZE(3'B0), + .S_AXI_HP3_ARPROT(3'B0), + .S_AXI_HP3_AWPROT(3'B0), + .S_AXI_HP3_ARADDR(32'B0), + .S_AXI_HP3_AWADDR(32'B0), + .S_AXI_HP3_ARCACHE(4'B0), + .S_AXI_HP3_ARLEN(4'B0), + .S_AXI_HP3_ARQOS(4'B0), + .S_AXI_HP3_AWCACHE(4'B0), + .S_AXI_HP3_AWLEN(4'B0), + .S_AXI_HP3_AWQOS(4'B0), + .S_AXI_HP3_ARID(6'B0), + .S_AXI_HP3_AWID(6'B0), + .S_AXI_HP3_WID(6'B0), + .S_AXI_HP3_WDATA(64'B0), + .S_AXI_HP3_WSTRB(8'B0), + .FCLK_CLK0(FCLK_CLK0), + + .FCLK_CLK1(FCLK_CLK1), + + .FCLK_CLK2(), + + .FCLK_CLK3(), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(), + .FCLK_RESET2_N(), + .FCLK_RESET3_N(), + .IRQ_F2P(IRQ_F2P), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v new file mode 100644 index 0000000..5813335 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/synth/design_1_processing_system7_0_0.v @@ -0,0 +1,1173 @@ +// (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:processing_system7:5.5 +// IP Revision: 6 + +(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *) +(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) +(* CORE_GENERATION_INFO = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CH\ +ECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C\ +_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=16,C_DQS_WIDTH=2,C_DM_WIDTH=2,C_MIO_PRIMITIVE=32,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=TRUE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg225,C_GP0_EN_MODIFIABLE_TXN\ +=1,C_GP1_EN_MODIFIABLE_TXN=1}" *) +(* DowngradeIPIdentifiedWarnings = "yes" *) +module design_1_processing_system7_0_0 ( + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_TX, + UART0_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + IRQ_F2P, + FCLK_CLK0, + FCLK_CLK1, + FCLK_RESET0_N, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB +); + +(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *) +input wire [63 : 0] GPIO_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *) +output wire [63 : 0] GPIO_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *) +output wire [63 : 0] GPIO_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) +input wire I2C0_SDA_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) +output wire I2C0_SDA_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) +output wire I2C0_SDA_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) +input wire I2C0_SCL_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) +output wire I2C0_SCL_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) +output wire I2C0_SCL_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CLK" *) +output wire SDIO0_CLK; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CLK_FB" *) +input wire SDIO0_CLK_FB; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_O" *) +output wire SDIO0_CMD_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_I" *) +input wire SDIO0_CMD_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CMD_T" *) +output wire SDIO0_CMD_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_I" *) +input wire [3 : 0] SDIO0_DATA_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_O" *) +output wire [3 : 0] SDIO0_DATA_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 DATA_T" *) +output wire [3 : 0] SDIO0_DATA_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 LED" *) +output wire SDIO0_LED; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 CDN" *) +input wire SDIO0_CDN; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 WP" *) +input wire SDIO0_WP; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 BUSPOW" *) +output wire SDIO0_BUSPOW; +(* X_INTERFACE_INFO = "xilinx.com:interface:sdio:1.0 SDIO_0 BUSVOLT" *) +output wire [2 : 0] SDIO0_BUSVOLT; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_I" *) +input wire SPI0_SCLK_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_O" *) +output wire SPI0_SCLK_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_T" *) +output wire SPI0_SCLK_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_I" *) +input wire SPI0_MOSI_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_O" *) +output wire SPI0_MOSI_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_T" *) +output wire SPI0_MOSI_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_I" *) +input wire SPI0_MISO_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_O" *) +output wire SPI0_MISO_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_T" *) +output wire SPI0_MISO_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_I" *) +input wire SPI0_SS_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_O" *) +output wire SPI0_SS_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS1_O" *) +output wire SPI0_SS1_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS2_O" *) +output wire SPI0_SS2_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_T" *) +output wire SPI0_SS_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *) +input wire SPI1_SCLK_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *) +output wire SPI1_SCLK_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *) +output wire SPI1_SCLK_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *) +input wire SPI1_MOSI_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *) +output wire SPI1_MOSI_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *) +output wire SPI1_MOSI_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *) +input wire SPI1_MISO_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *) +output wire SPI1_MISO_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *) +output wire SPI1_MISO_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *) +input wire SPI1_SS_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *) +output wire SPI1_SS_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *) +output wire SPI1_SS1_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *) +output wire SPI1_SS2_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *) +output wire SPI1_SS_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 UART_0 TxD" *) +output wire UART0_TX; +(* X_INTERFACE_INFO = "xilinx.com:interface:uart:1.0 UART_0 RxD" *) +input wire UART0_RX; +output wire TTC0_WAVE0_OUT; +output wire TTC0_WAVE1_OUT; +output wire TTC0_WAVE2_OUT; +output wire TTC1_WAVE0_OUT; +output wire TTC1_WAVE1_OUT; +output wire TTC1_WAVE2_OUT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) +output wire [1 : 0] USB0_PORT_INDCTL; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) +output wire USB0_VBUS_PWRSELECT; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) +input wire USB0_VBUS_PWRFAULT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) +output wire M_AXI_GP0_ARVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) +output wire M_AXI_GP0_AWVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) +output wire M_AXI_GP0_BREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) +output wire M_AXI_GP0_RREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) +output wire M_AXI_GP0_WLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) +output wire M_AXI_GP0_WVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) +output wire [11 : 0] M_AXI_GP0_ARID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) +output wire [11 : 0] M_AXI_GP0_AWID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) +output wire [11 : 0] M_AXI_GP0_WID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) +output wire [1 : 0] M_AXI_GP0_ARBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) +output wire [1 : 0] M_AXI_GP0_ARLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) +output wire [2 : 0] M_AXI_GP0_ARSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) +output wire [1 : 0] M_AXI_GP0_AWBURST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) +output wire [1 : 0] M_AXI_GP0_AWLOCK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) +output wire [2 : 0] M_AXI_GP0_AWSIZE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) +output wire [2 : 0] M_AXI_GP0_ARPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) +output wire [2 : 0] M_AXI_GP0_AWPROT; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) +output wire [31 : 0] M_AXI_GP0_ARADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) +output wire [31 : 0] M_AXI_GP0_AWADDR; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) +output wire [31 : 0] M_AXI_GP0_WDATA; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) +output wire [3 : 0] M_AXI_GP0_ARCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) +output wire [3 : 0] M_AXI_GP0_ARLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) +output wire [3 : 0] M_AXI_GP0_ARQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) +output wire [3 : 0] M_AXI_GP0_AWCACHE; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) +output wire [3 : 0] M_AXI_GP0_AWLEN; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) +output wire [3 : 0] M_AXI_GP0_AWQOS; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) +output wire [3 : 0] M_AXI_GP0_WSTRB; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) +input wire M_AXI_GP0_ACLK; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) +input wire M_AXI_GP0_ARREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) +input wire M_AXI_GP0_AWREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) +input wire M_AXI_GP0_BVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) +input wire M_AXI_GP0_RLAST; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) +input wire M_AXI_GP0_RVALID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) +input wire M_AXI_GP0_WREADY; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) +input wire [11 : 0] M_AXI_GP0_BID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) +input wire [11 : 0] M_AXI_GP0_RID; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) +input wire [1 : 0] M_AXI_GP0_BRESP; +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) +input wire [1 : 0] M_AXI_GP0_RRESP; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREA\ +DS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) +input wire [31 : 0] M_AXI_GP0_RDATA; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) +input wire [0 : 0] IRQ_F2P; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) +output wire FCLK_CLK0; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK1" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *) +output wire FCLK_CLK1; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) +(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) +output wire FCLK_RESET0_N; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) +inout wire [31 : 0] MIO; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) +inout wire DDR_CAS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) +inout wire DDR_CKE; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) +inout wire DDR_Clk_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) +inout wire DDR_Clk; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) +inout wire DDR_CS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) +inout wire DDR_DRSTB; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) +inout wire DDR_ODT; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) +inout wire DDR_RAS_n; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) +inout wire DDR_WEB; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) +inout wire [2 : 0] DDR_BankAddr; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) +inout wire [14 : 0] DDR_Addr; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) +inout wire DDR_VRN; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) +inout wire DDR_VRP; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) +inout wire [1 : 0] DDR_DM; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) +inout wire [15 : 0] DDR_DQ; +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) +inout wire [1 : 0] DDR_DQS_n; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) +inout wire [1 : 0] DDR_DQS; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) +inout wire PS_SRSTB; +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) +inout wire PS_CLK; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) +(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) +inout wire PS_PORB; + + processing_system7_v5_5_processing_system7 #( + .C_EN_EMIO_PJTAG(0), + .C_EN_EMIO_ENET0(0), + .C_EN_EMIO_ENET1(0), + .C_EN_EMIO_TRACE(0), + .C_INCLUDE_TRACE_BUFFER(0), + .C_TRACE_BUFFER_FIFO_SIZE(128), + .USE_TRACE_DATA_EDGE_DETECTOR(0), + .C_TRACE_PIPELINE_WIDTH(8), + .C_TRACE_BUFFER_CLOCK_DELAY(12), + .C_EMIO_GPIO_WIDTH(64), + .C_INCLUDE_ACP_TRANS_CHECK(0), + .C_USE_DEFAULT_ACP_USER_VAL(0), + .C_S_AXI_ACP_ARUSER_VAL(31), + .C_S_AXI_ACP_AWUSER_VAL(31), + .C_M_AXI_GP0_ID_WIDTH(12), + .C_M_AXI_GP0_ENABLE_STATIC_REMAP(0), + .C_M_AXI_GP1_ID_WIDTH(12), + .C_M_AXI_GP1_ENABLE_STATIC_REMAP(0), + .C_S_AXI_GP0_ID_WIDTH(6), + .C_S_AXI_GP1_ID_WIDTH(6), + .C_S_AXI_ACP_ID_WIDTH(3), + .C_S_AXI_HP0_ID_WIDTH(6), + .C_S_AXI_HP0_DATA_WIDTH(64), + .C_S_AXI_HP1_ID_WIDTH(6), + .C_S_AXI_HP1_DATA_WIDTH(64), + .C_S_AXI_HP2_ID_WIDTH(6), + .C_S_AXI_HP2_DATA_WIDTH(64), + .C_S_AXI_HP3_ID_WIDTH(6), + .C_S_AXI_HP3_DATA_WIDTH(64), + .C_M_AXI_GP0_THREAD_ID_WIDTH(12), + .C_M_AXI_GP1_THREAD_ID_WIDTH(12), + .C_NUM_F2P_INTR_INPUTS(1), + .C_IRQ_F2P_MODE("DIRECT"), + .C_DQ_WIDTH(16), + .C_DQS_WIDTH(2), + .C_DM_WIDTH(2), + .C_MIO_PRIMITIVE(32), + .C_TRACE_INTERNAL_WIDTH(2), + .C_USE_AXI_NONSECURE(0), + .C_USE_M_AXI_GP0(1), + .C_USE_M_AXI_GP1(0), + .C_USE_S_AXI_GP0(0), + .C_USE_S_AXI_GP1(0), + .C_USE_S_AXI_HP0(0), + .C_USE_S_AXI_HP1(0), + .C_USE_S_AXI_HP2(0), + .C_USE_S_AXI_HP3(0), + .C_USE_S_AXI_ACP(0), + .C_PS7_SI_REV("PRODUCTION"), + .C_FCLK_CLK0_BUF("TRUE"), + .C_FCLK_CLK1_BUF("TRUE"), + .C_FCLK_CLK2_BUF("FALSE"), + .C_FCLK_CLK3_BUF("FALSE"), + .C_PACKAGE_NAME("clg225"), + .C_GP0_EN_MODIFIABLE_TXN(1), + .C_GP1_EN_MODIFIABLE_TXN(1) + ) inst ( + .CAN0_PHY_TX(), + .CAN0_PHY_RX(1'B0), + .CAN1_PHY_TX(), + .CAN1_PHY_RX(1'B0), + .ENET0_GMII_TX_EN(), + .ENET0_GMII_TX_ER(), + .ENET0_MDIO_MDC(), + .ENET0_MDIO_O(), + .ENET0_MDIO_T(), + .ENET0_PTP_DELAY_REQ_RX(), + .ENET0_PTP_DELAY_REQ_TX(), + .ENET0_PTP_PDELAY_REQ_RX(), + .ENET0_PTP_PDELAY_REQ_TX(), + .ENET0_PTP_PDELAY_RESP_RX(), + .ENET0_PTP_PDELAY_RESP_TX(), + .ENET0_PTP_SYNC_FRAME_RX(), + .ENET0_PTP_SYNC_FRAME_TX(), + .ENET0_SOF_RX(), + .ENET0_SOF_TX(), + .ENET0_GMII_TXD(), + .ENET0_GMII_COL(1'B0), + .ENET0_GMII_CRS(1'B0), + .ENET0_GMII_RX_CLK(1'B0), + .ENET0_GMII_RX_DV(1'B0), + .ENET0_GMII_RX_ER(1'B0), + .ENET0_GMII_TX_CLK(1'B0), + .ENET0_MDIO_I(1'B0), + .ENET0_EXT_INTIN(1'B0), + .ENET0_GMII_RXD(8'B0), + .ENET1_GMII_TX_EN(), + .ENET1_GMII_TX_ER(), + .ENET1_MDIO_MDC(), + .ENET1_MDIO_O(), + .ENET1_MDIO_T(), + .ENET1_PTP_DELAY_REQ_RX(), + .ENET1_PTP_DELAY_REQ_TX(), + .ENET1_PTP_PDELAY_REQ_RX(), + .ENET1_PTP_PDELAY_REQ_TX(), + .ENET1_PTP_PDELAY_RESP_RX(), + .ENET1_PTP_PDELAY_RESP_TX(), + .ENET1_PTP_SYNC_FRAME_RX(), + .ENET1_PTP_SYNC_FRAME_TX(), + .ENET1_SOF_RX(), + .ENET1_SOF_TX(), + .ENET1_GMII_TXD(), + .ENET1_GMII_COL(1'B0), + .ENET1_GMII_CRS(1'B0), + .ENET1_GMII_RX_CLK(1'B0), + .ENET1_GMII_RX_DV(1'B0), + .ENET1_GMII_RX_ER(1'B0), + .ENET1_GMII_TX_CLK(1'B0), + .ENET1_MDIO_I(1'B0), + .ENET1_EXT_INTIN(1'B0), + .ENET1_GMII_RXD(8'B0), + .GPIO_I(GPIO_I), + .GPIO_O(GPIO_O), + .GPIO_T(GPIO_T), + .I2C0_SDA_I(I2C0_SDA_I), + .I2C0_SDA_O(I2C0_SDA_O), + .I2C0_SDA_T(I2C0_SDA_T), + .I2C0_SCL_I(I2C0_SCL_I), + .I2C0_SCL_O(I2C0_SCL_O), + .I2C0_SCL_T(I2C0_SCL_T), + .I2C1_SDA_I(1'B0), + .I2C1_SDA_O(), + .I2C1_SDA_T(), + .I2C1_SCL_I(1'B0), + .I2C1_SCL_O(), + .I2C1_SCL_T(), + .PJTAG_TCK(1'B0), + .PJTAG_TMS(1'B0), + .PJTAG_TDI(1'B0), + .PJTAG_TDO(), + .SDIO0_CLK(SDIO0_CLK), + .SDIO0_CLK_FB(SDIO0_CLK_FB), + .SDIO0_CMD_O(SDIO0_CMD_O), + .SDIO0_CMD_I(SDIO0_CMD_I), + .SDIO0_CMD_T(SDIO0_CMD_T), + .SDIO0_DATA_I(SDIO0_DATA_I), + .SDIO0_DATA_O(SDIO0_DATA_O), + .SDIO0_DATA_T(SDIO0_DATA_T), + .SDIO0_LED(SDIO0_LED), + .SDIO0_CDN(SDIO0_CDN), + .SDIO0_WP(SDIO0_WP), + .SDIO0_BUSPOW(SDIO0_BUSPOW), + .SDIO0_BUSVOLT(SDIO0_BUSVOLT), + .SDIO1_CLK(), + .SDIO1_CLK_FB(1'B0), + .SDIO1_CMD_O(), + .SDIO1_CMD_I(1'B0), + .SDIO1_CMD_T(), + .SDIO1_DATA_I(4'B0), + .SDIO1_DATA_O(), + .SDIO1_DATA_T(), + .SDIO1_LED(), + .SDIO1_CDN(1'B0), + .SDIO1_WP(1'B0), + .SDIO1_BUSPOW(), + .SDIO1_BUSVOLT(), + .SPI0_SCLK_I(SPI0_SCLK_I), + .SPI0_SCLK_O(SPI0_SCLK_O), + .SPI0_SCLK_T(SPI0_SCLK_T), + .SPI0_MOSI_I(SPI0_MOSI_I), + .SPI0_MOSI_O(SPI0_MOSI_O), + .SPI0_MOSI_T(SPI0_MOSI_T), + .SPI0_MISO_I(SPI0_MISO_I), + .SPI0_MISO_O(SPI0_MISO_O), + .SPI0_MISO_T(SPI0_MISO_T), + .SPI0_SS_I(SPI0_SS_I), + .SPI0_SS_O(SPI0_SS_O), + .SPI0_SS1_O(SPI0_SS1_O), + .SPI0_SS2_O(SPI0_SS2_O), + .SPI0_SS_T(SPI0_SS_T), + .SPI1_SCLK_I(SPI1_SCLK_I), + .SPI1_SCLK_O(SPI1_SCLK_O), + .SPI1_SCLK_T(SPI1_SCLK_T), + .SPI1_MOSI_I(SPI1_MOSI_I), + .SPI1_MOSI_O(SPI1_MOSI_O), + .SPI1_MOSI_T(SPI1_MOSI_T), + .SPI1_MISO_I(SPI1_MISO_I), + .SPI1_MISO_O(SPI1_MISO_O), + .SPI1_MISO_T(SPI1_MISO_T), + .SPI1_SS_I(SPI1_SS_I), + .SPI1_SS_O(SPI1_SS_O), + .SPI1_SS1_O(SPI1_SS1_O), + .SPI1_SS2_O(SPI1_SS2_O), + .SPI1_SS_T(SPI1_SS_T), + .UART0_DTRN(), + .UART0_RTSN(), + .UART0_TX(UART0_TX), + .UART0_CTSN(1'B0), + .UART0_DCDN(1'B0), + .UART0_DSRN(1'B0), + .UART0_RIN(1'B0), + .UART0_RX(UART0_RX), + .UART1_DTRN(), + .UART1_RTSN(), + .UART1_TX(), + .UART1_CTSN(1'B0), + .UART1_DCDN(1'B0), + .UART1_DSRN(1'B0), + .UART1_RIN(1'B0), + .UART1_RX(1'B1), + .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT), + .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT), + .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT), + .TTC0_CLK0_IN(1'B0), + .TTC0_CLK1_IN(1'B0), + .TTC0_CLK2_IN(1'B0), + .TTC1_WAVE0_OUT(TTC1_WAVE0_OUT), + .TTC1_WAVE1_OUT(TTC1_WAVE1_OUT), + .TTC1_WAVE2_OUT(TTC1_WAVE2_OUT), + .TTC1_CLK0_IN(1'B0), + .TTC1_CLK1_IN(1'B0), + .TTC1_CLK2_IN(1'B0), + .WDT_CLK_IN(1'B0), + .WDT_RST_OUT(), + .TRACE_CLK(1'B0), + .TRACE_CLK_OUT(), + .TRACE_CTL(), + .TRACE_DATA(), + .USB0_PORT_INDCTL(USB0_PORT_INDCTL), + .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), + .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), + .USB1_PORT_INDCTL(), + .USB1_VBUS_PWRSELECT(), + .USB1_VBUS_PWRFAULT(1'B0), + .SRAM_INTIN(1'B0), + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP1_ARVALID(), + .M_AXI_GP1_AWVALID(), + .M_AXI_GP1_BREADY(), + .M_AXI_GP1_RREADY(), + .M_AXI_GP1_WLAST(), + .M_AXI_GP1_WVALID(), + .M_AXI_GP1_ARID(), + .M_AXI_GP1_AWID(), + .M_AXI_GP1_WID(), + .M_AXI_GP1_ARBURST(), + .M_AXI_GP1_ARLOCK(), + .M_AXI_GP1_ARSIZE(), + .M_AXI_GP1_AWBURST(), + .M_AXI_GP1_AWLOCK(), + .M_AXI_GP1_AWSIZE(), + .M_AXI_GP1_ARPROT(), + .M_AXI_GP1_AWPROT(), + .M_AXI_GP1_ARADDR(), + .M_AXI_GP1_AWADDR(), + .M_AXI_GP1_WDATA(), + .M_AXI_GP1_ARCACHE(), + .M_AXI_GP1_ARLEN(), + .M_AXI_GP1_ARQOS(), + .M_AXI_GP1_AWCACHE(), + .M_AXI_GP1_AWLEN(), + .M_AXI_GP1_AWQOS(), + .M_AXI_GP1_WSTRB(), + .M_AXI_GP1_ACLK(1'B0), + .M_AXI_GP1_ARREADY(1'B0), + .M_AXI_GP1_AWREADY(1'B0), + .M_AXI_GP1_BVALID(1'B0), + .M_AXI_GP1_RLAST(1'B0), + .M_AXI_GP1_RVALID(1'B0), + .M_AXI_GP1_WREADY(1'B0), + .M_AXI_GP1_BID(12'B0), + .M_AXI_GP1_RID(12'B0), + .M_AXI_GP1_BRESP(2'B0), + .M_AXI_GP1_RRESP(2'B0), + .M_AXI_GP1_RDATA(32'B0), + .S_AXI_GP0_ARREADY(), + .S_AXI_GP0_AWREADY(), + .S_AXI_GP0_BVALID(), + .S_AXI_GP0_RLAST(), + .S_AXI_GP0_RVALID(), + .S_AXI_GP0_WREADY(), + .S_AXI_GP0_BRESP(), + .S_AXI_GP0_RRESP(), + .S_AXI_GP0_RDATA(), + .S_AXI_GP0_BID(), + .S_AXI_GP0_RID(), + .S_AXI_GP0_ACLK(1'B0), + .S_AXI_GP0_ARVALID(1'B0), + .S_AXI_GP0_AWVALID(1'B0), + .S_AXI_GP0_BREADY(1'B0), + .S_AXI_GP0_RREADY(1'B0), + .S_AXI_GP0_WLAST(1'B0), + .S_AXI_GP0_WVALID(1'B0), + .S_AXI_GP0_ARBURST(2'B0), + .S_AXI_GP0_ARLOCK(2'B0), + .S_AXI_GP0_ARSIZE(3'B0), + .S_AXI_GP0_AWBURST(2'B0), + .S_AXI_GP0_AWLOCK(2'B0), + .S_AXI_GP0_AWSIZE(3'B0), + .S_AXI_GP0_ARPROT(3'B0), + .S_AXI_GP0_AWPROT(3'B0), + .S_AXI_GP0_ARADDR(32'B0), + .S_AXI_GP0_AWADDR(32'B0), + .S_AXI_GP0_WDATA(32'B0), + .S_AXI_GP0_ARCACHE(4'B0), + .S_AXI_GP0_ARLEN(4'B0), + .S_AXI_GP0_ARQOS(4'B0), + .S_AXI_GP0_AWCACHE(4'B0), + .S_AXI_GP0_AWLEN(4'B0), + .S_AXI_GP0_AWQOS(4'B0), + .S_AXI_GP0_WSTRB(4'B0), + .S_AXI_GP0_ARID(6'B0), + .S_AXI_GP0_AWID(6'B0), + .S_AXI_GP0_WID(6'B0), + .S_AXI_GP1_ARREADY(), + .S_AXI_GP1_AWREADY(), + .S_AXI_GP1_BVALID(), + .S_AXI_GP1_RLAST(), + .S_AXI_GP1_RVALID(), + .S_AXI_GP1_WREADY(), + .S_AXI_GP1_BRESP(), + .S_AXI_GP1_RRESP(), + .S_AXI_GP1_RDATA(), + .S_AXI_GP1_BID(), + .S_AXI_GP1_RID(), + .S_AXI_GP1_ACLK(1'B0), + .S_AXI_GP1_ARVALID(1'B0), + .S_AXI_GP1_AWVALID(1'B0), + .S_AXI_GP1_BREADY(1'B0), + .S_AXI_GP1_RREADY(1'B0), + .S_AXI_GP1_WLAST(1'B0), + .S_AXI_GP1_WVALID(1'B0), + .S_AXI_GP1_ARBURST(2'B0), + .S_AXI_GP1_ARLOCK(2'B0), + .S_AXI_GP1_ARSIZE(3'B0), + .S_AXI_GP1_AWBURST(2'B0), + .S_AXI_GP1_AWLOCK(2'B0), + .S_AXI_GP1_AWSIZE(3'B0), + .S_AXI_GP1_ARPROT(3'B0), + .S_AXI_GP1_AWPROT(3'B0), + .S_AXI_GP1_ARADDR(32'B0), + .S_AXI_GP1_AWADDR(32'B0), + .S_AXI_GP1_WDATA(32'B0), + .S_AXI_GP1_ARCACHE(4'B0), + .S_AXI_GP1_ARLEN(4'B0), + .S_AXI_GP1_ARQOS(4'B0), + .S_AXI_GP1_AWCACHE(4'B0), + .S_AXI_GP1_AWLEN(4'B0), + .S_AXI_GP1_AWQOS(4'B0), + .S_AXI_GP1_WSTRB(4'B0), + .S_AXI_GP1_ARID(6'B0), + .S_AXI_GP1_AWID(6'B0), + .S_AXI_GP1_WID(6'B0), + .S_AXI_ACP_ARREADY(), + .S_AXI_ACP_AWREADY(), + .S_AXI_ACP_BVALID(), + .S_AXI_ACP_RLAST(), + .S_AXI_ACP_RVALID(), + .S_AXI_ACP_WREADY(), + .S_AXI_ACP_BRESP(), + .S_AXI_ACP_RRESP(), + .S_AXI_ACP_BID(), + .S_AXI_ACP_RID(), + .S_AXI_ACP_RDATA(), + .S_AXI_ACP_ACLK(1'B0), + .S_AXI_ACP_ARVALID(1'B0), + .S_AXI_ACP_AWVALID(1'B0), + .S_AXI_ACP_BREADY(1'B0), + .S_AXI_ACP_RREADY(1'B0), + .S_AXI_ACP_WLAST(1'B0), + .S_AXI_ACP_WVALID(1'B0), + .S_AXI_ACP_ARID(3'B0), + .S_AXI_ACP_ARPROT(3'B0), + .S_AXI_ACP_AWID(3'B0), + .S_AXI_ACP_AWPROT(3'B0), + .S_AXI_ACP_WID(3'B0), + .S_AXI_ACP_ARADDR(32'B0), + .S_AXI_ACP_AWADDR(32'B0), + .S_AXI_ACP_ARCACHE(4'B0), + .S_AXI_ACP_ARLEN(4'B0), + .S_AXI_ACP_ARQOS(4'B0), + .S_AXI_ACP_AWCACHE(4'B0), + .S_AXI_ACP_AWLEN(4'B0), + .S_AXI_ACP_AWQOS(4'B0), + .S_AXI_ACP_ARBURST(2'B0), + .S_AXI_ACP_ARLOCK(2'B0), + .S_AXI_ACP_ARSIZE(3'B0), + .S_AXI_ACP_AWBURST(2'B0), + .S_AXI_ACP_AWLOCK(2'B0), + .S_AXI_ACP_AWSIZE(3'B0), + .S_AXI_ACP_ARUSER(5'B0), + .S_AXI_ACP_AWUSER(5'B0), + .S_AXI_ACP_WDATA(64'B0), + .S_AXI_ACP_WSTRB(8'B0), + .S_AXI_HP0_ARREADY(), + .S_AXI_HP0_AWREADY(), + .S_AXI_HP0_BVALID(), + .S_AXI_HP0_RLAST(), + .S_AXI_HP0_RVALID(), + .S_AXI_HP0_WREADY(), + .S_AXI_HP0_BRESP(), + .S_AXI_HP0_RRESP(), + .S_AXI_HP0_BID(), + .S_AXI_HP0_RID(), + .S_AXI_HP0_RDATA(), + .S_AXI_HP0_RCOUNT(), + .S_AXI_HP0_WCOUNT(), + .S_AXI_HP0_RACOUNT(), + .S_AXI_HP0_WACOUNT(), + .S_AXI_HP0_ACLK(1'B0), + .S_AXI_HP0_ARVALID(1'B0), + .S_AXI_HP0_AWVALID(1'B0), + .S_AXI_HP0_BREADY(1'B0), + .S_AXI_HP0_RDISSUECAP1_EN(1'B0), + .S_AXI_HP0_RREADY(1'B0), + .S_AXI_HP0_WLAST(1'B0), + .S_AXI_HP0_WRISSUECAP1_EN(1'B0), + .S_AXI_HP0_WVALID(1'B0), + .S_AXI_HP0_ARBURST(2'B0), + .S_AXI_HP0_ARLOCK(2'B0), + .S_AXI_HP0_ARSIZE(3'B0), + .S_AXI_HP0_AWBURST(2'B0), + .S_AXI_HP0_AWLOCK(2'B0), + .S_AXI_HP0_AWSIZE(3'B0), + .S_AXI_HP0_ARPROT(3'B0), + .S_AXI_HP0_AWPROT(3'B0), + .S_AXI_HP0_ARADDR(32'B0), + .S_AXI_HP0_AWADDR(32'B0), + .S_AXI_HP0_ARCACHE(4'B0), + .S_AXI_HP0_ARLEN(4'B0), + .S_AXI_HP0_ARQOS(4'B0), + .S_AXI_HP0_AWCACHE(4'B0), + .S_AXI_HP0_AWLEN(4'B0), + .S_AXI_HP0_AWQOS(4'B0), + .S_AXI_HP0_ARID(6'B0), + .S_AXI_HP0_AWID(6'B0), + .S_AXI_HP0_WID(6'B0), + .S_AXI_HP0_WDATA(64'B0), + .S_AXI_HP0_WSTRB(8'B0), + .S_AXI_HP1_ARREADY(), + .S_AXI_HP1_AWREADY(), + .S_AXI_HP1_BVALID(), + .S_AXI_HP1_RLAST(), + .S_AXI_HP1_RVALID(), + .S_AXI_HP1_WREADY(), + .S_AXI_HP1_BRESP(), + .S_AXI_HP1_RRESP(), + .S_AXI_HP1_BID(), + .S_AXI_HP1_RID(), + .S_AXI_HP1_RDATA(), + .S_AXI_HP1_RCOUNT(), + .S_AXI_HP1_WCOUNT(), + .S_AXI_HP1_RACOUNT(), + .S_AXI_HP1_WACOUNT(), + .S_AXI_HP1_ACLK(1'B0), + .S_AXI_HP1_ARVALID(1'B0), + .S_AXI_HP1_AWVALID(1'B0), + .S_AXI_HP1_BREADY(1'B0), + .S_AXI_HP1_RDISSUECAP1_EN(1'B0), + .S_AXI_HP1_RREADY(1'B0), + .S_AXI_HP1_WLAST(1'B0), + .S_AXI_HP1_WRISSUECAP1_EN(1'B0), + .S_AXI_HP1_WVALID(1'B0), + .S_AXI_HP1_ARBURST(2'B0), + .S_AXI_HP1_ARLOCK(2'B0), + .S_AXI_HP1_ARSIZE(3'B0), + .S_AXI_HP1_AWBURST(2'B0), + .S_AXI_HP1_AWLOCK(2'B0), + .S_AXI_HP1_AWSIZE(3'B0), + .S_AXI_HP1_ARPROT(3'B0), + .S_AXI_HP1_AWPROT(3'B0), + .S_AXI_HP1_ARADDR(32'B0), + .S_AXI_HP1_AWADDR(32'B0), + .S_AXI_HP1_ARCACHE(4'B0), + .S_AXI_HP1_ARLEN(4'B0), + .S_AXI_HP1_ARQOS(4'B0), + .S_AXI_HP1_AWCACHE(4'B0), + .S_AXI_HP1_AWLEN(4'B0), + .S_AXI_HP1_AWQOS(4'B0), + .S_AXI_HP1_ARID(6'B0), + .S_AXI_HP1_AWID(6'B0), + .S_AXI_HP1_WID(6'B0), + .S_AXI_HP1_WDATA(64'B0), + .S_AXI_HP1_WSTRB(8'B0), + .S_AXI_HP2_ARREADY(), + .S_AXI_HP2_AWREADY(), + .S_AXI_HP2_BVALID(), + .S_AXI_HP2_RLAST(), + .S_AXI_HP2_RVALID(), + .S_AXI_HP2_WREADY(), + .S_AXI_HP2_BRESP(), + .S_AXI_HP2_RRESP(), + .S_AXI_HP2_BID(), + .S_AXI_HP2_RID(), + .S_AXI_HP2_RDATA(), + .S_AXI_HP2_RCOUNT(), + .S_AXI_HP2_WCOUNT(), + .S_AXI_HP2_RACOUNT(), + .S_AXI_HP2_WACOUNT(), + .S_AXI_HP2_ACLK(1'B0), + .S_AXI_HP2_ARVALID(1'B0), + .S_AXI_HP2_AWVALID(1'B0), + .S_AXI_HP2_BREADY(1'B0), + .S_AXI_HP2_RDISSUECAP1_EN(1'B0), + .S_AXI_HP2_RREADY(1'B0), + .S_AXI_HP2_WLAST(1'B0), + .S_AXI_HP2_WRISSUECAP1_EN(1'B0), + .S_AXI_HP2_WVALID(1'B0), + .S_AXI_HP2_ARBURST(2'B0), + .S_AXI_HP2_ARLOCK(2'B0), + .S_AXI_HP2_ARSIZE(3'B0), + .S_AXI_HP2_AWBURST(2'B0), + .S_AXI_HP2_AWLOCK(2'B0), + .S_AXI_HP2_AWSIZE(3'B0), + .S_AXI_HP2_ARPROT(3'B0), + .S_AXI_HP2_AWPROT(3'B0), + .S_AXI_HP2_ARADDR(32'B0), + .S_AXI_HP2_AWADDR(32'B0), + .S_AXI_HP2_ARCACHE(4'B0), + .S_AXI_HP2_ARLEN(4'B0), + .S_AXI_HP2_ARQOS(4'B0), + .S_AXI_HP2_AWCACHE(4'B0), + .S_AXI_HP2_AWLEN(4'B0), + .S_AXI_HP2_AWQOS(4'B0), + .S_AXI_HP2_ARID(6'B0), + .S_AXI_HP2_AWID(6'B0), + .S_AXI_HP2_WID(6'B0), + .S_AXI_HP2_WDATA(64'B0), + .S_AXI_HP2_WSTRB(8'B0), + .S_AXI_HP3_ARREADY(), + .S_AXI_HP3_AWREADY(), + .S_AXI_HP3_BVALID(), + .S_AXI_HP3_RLAST(), + .S_AXI_HP3_RVALID(), + .S_AXI_HP3_WREADY(), + .S_AXI_HP3_BRESP(), + .S_AXI_HP3_RRESP(), + .S_AXI_HP3_BID(), + .S_AXI_HP3_RID(), + .S_AXI_HP3_RDATA(), + .S_AXI_HP3_RCOUNT(), + .S_AXI_HP3_WCOUNT(), + .S_AXI_HP3_RACOUNT(), + .S_AXI_HP3_WACOUNT(), + .S_AXI_HP3_ACLK(1'B0), + .S_AXI_HP3_ARVALID(1'B0), + .S_AXI_HP3_AWVALID(1'B0), + .S_AXI_HP3_BREADY(1'B0), + .S_AXI_HP3_RDISSUECAP1_EN(1'B0), + .S_AXI_HP3_RREADY(1'B0), + .S_AXI_HP3_WLAST(1'B0), + .S_AXI_HP3_WRISSUECAP1_EN(1'B0), + .S_AXI_HP3_WVALID(1'B0), + .S_AXI_HP3_ARBURST(2'B0), + .S_AXI_HP3_ARLOCK(2'B0), + .S_AXI_HP3_ARSIZE(3'B0), + .S_AXI_HP3_AWBURST(2'B0), + .S_AXI_HP3_AWLOCK(2'B0), + .S_AXI_HP3_AWSIZE(3'B0), + .S_AXI_HP3_ARPROT(3'B0), + .S_AXI_HP3_AWPROT(3'B0), + .S_AXI_HP3_ARADDR(32'B0), + .S_AXI_HP3_AWADDR(32'B0), + .S_AXI_HP3_ARCACHE(4'B0), + .S_AXI_HP3_ARLEN(4'B0), + .S_AXI_HP3_ARQOS(4'B0), + .S_AXI_HP3_AWCACHE(4'B0), + .S_AXI_HP3_AWLEN(4'B0), + .S_AXI_HP3_AWQOS(4'B0), + .S_AXI_HP3_ARID(6'B0), + .S_AXI_HP3_AWID(6'B0), + .S_AXI_HP3_WID(6'B0), + .S_AXI_HP3_WDATA(64'B0), + .S_AXI_HP3_WSTRB(8'B0), + .IRQ_P2F_DMAC_ABORT(), + .IRQ_P2F_DMAC0(), + .IRQ_P2F_DMAC1(), + .IRQ_P2F_DMAC2(), + .IRQ_P2F_DMAC3(), + .IRQ_P2F_DMAC4(), + .IRQ_P2F_DMAC5(), + .IRQ_P2F_DMAC6(), + .IRQ_P2F_DMAC7(), + .IRQ_P2F_SMC(), + .IRQ_P2F_QSPI(), + .IRQ_P2F_CTI(), + .IRQ_P2F_GPIO(), + .IRQ_P2F_USB0(), + .IRQ_P2F_ENET0(), + .IRQ_P2F_ENET_WAKE0(), + .IRQ_P2F_SDIO0(), + .IRQ_P2F_I2C0(), + .IRQ_P2F_SPI0(), + .IRQ_P2F_UART0(), + .IRQ_P2F_CAN0(), + .IRQ_P2F_USB1(), + .IRQ_P2F_ENET1(), + .IRQ_P2F_ENET_WAKE1(), + .IRQ_P2F_SDIO1(), + .IRQ_P2F_I2C1(), + .IRQ_P2F_SPI1(), + .IRQ_P2F_UART1(), + .IRQ_P2F_CAN1(), + .IRQ_F2P(IRQ_F2P), + .Core0_nFIQ(1'B0), + .Core0_nIRQ(1'B0), + .Core1_nFIQ(1'B0), + .Core1_nIRQ(1'B0), + .DMA0_DATYPE(), + .DMA0_DAVALID(), + .DMA0_DRREADY(), + .DMA1_DATYPE(), + .DMA1_DAVALID(), + .DMA1_DRREADY(), + .DMA2_DATYPE(), + .DMA2_DAVALID(), + .DMA2_DRREADY(), + .DMA3_DATYPE(), + .DMA3_DAVALID(), + .DMA3_DRREADY(), + .DMA0_ACLK(1'B0), + .DMA0_DAREADY(1'B0), + .DMA0_DRLAST(1'B0), + .DMA0_DRVALID(1'B0), + .DMA1_ACLK(1'B0), + .DMA1_DAREADY(1'B0), + .DMA1_DRLAST(1'B0), + .DMA1_DRVALID(1'B0), + .DMA2_ACLK(1'B0), + .DMA2_DAREADY(1'B0), + .DMA2_DRLAST(1'B0), + .DMA2_DRVALID(1'B0), + .DMA3_ACLK(1'B0), + .DMA3_DAREADY(1'B0), + .DMA3_DRLAST(1'B0), + .DMA3_DRVALID(1'B0), + .DMA0_DRTYPE(2'B0), + .DMA1_DRTYPE(2'B0), + .DMA2_DRTYPE(2'B0), + .DMA3_DRTYPE(2'B0), + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(FCLK_CLK1), + .FCLK_CLK2(), + .FCLK_CLK3(), + .FCLK_CLKTRIG0_N(1'B0), + .FCLK_CLKTRIG1_N(1'B0), + .FCLK_CLKTRIG2_N(1'B0), + .FCLK_CLKTRIG3_N(1'B0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(), + .FCLK_RESET2_N(), + .FCLK_RESET3_N(), + .FTMD_TRACEIN_DATA(32'B0), + .FTMD_TRACEIN_VALID(1'B0), + .FTMD_TRACEIN_CLK(1'B0), + .FTMD_TRACEIN_ATID(4'B0), + .FTMT_F2P_TRIG_0(1'B0), + .FTMT_F2P_TRIGACK_0(), + .FTMT_F2P_TRIG_1(1'B0), + .FTMT_F2P_TRIGACK_1(), + .FTMT_F2P_TRIG_2(1'B0), + .FTMT_F2P_TRIGACK_2(), + .FTMT_F2P_TRIG_3(1'B0), + .FTMT_F2P_TRIGACK_3(), + .FTMT_F2P_DEBUG(32'B0), + .FTMT_P2F_TRIGACK_0(1'B0), + .FTMT_P2F_TRIG_0(), + .FTMT_P2F_TRIGACK_1(1'B0), + .FTMT_P2F_TRIG_1(), + .FTMT_P2F_TRIGACK_2(1'B0), + .FTMT_P2F_TRIG_2(), + .FTMT_P2F_TRIGACK_3(1'B0), + .FTMT_P2F_TRIG_3(), + .FTMT_P2F_DEBUG(), + .FPGA_IDLE_N(1'B0), + .EVENT_EVENTO(), + .EVENT_STANDBYWFE(), + .EVENT_STANDBYWFI(), + .EVENT_EVENTI(1'B0), + .DDR_ARB(4'B0), + .MIO(MIO), + .DDR_CAS_n(DDR_CAS_n), + .DDR_CKE(DDR_CKE), + .DDR_Clk_n(DDR_Clk_n), + .DDR_Clk(DDR_Clk), + .DDR_CS_n(DDR_CS_n), + .DDR_DRSTB(DDR_DRSTB), + .DDR_ODT(DDR_ODT), + .DDR_RAS_n(DDR_RAS_n), + .DDR_WEB(DDR_WEB), + .DDR_BankAddr(DDR_BankAddr), + .DDR_Addr(DDR_Addr), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_DM(DDR_DM), + .DDR_DQ(DDR_DQ), + .DDR_DQS_n(DDR_DQS_n), + .DDR_DQS(DDR_DQS), + .PS_SRSTB(PS_SRSTB), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB) + ); +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_apis.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_apis.v new file mode 100644 index 0000000..db24752 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_apis.v @@ -0,0 +1,842 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_5_apis.v + * + * Date : 2012-11 + * + * Description : Set of Zynq VIP APIs that are used for writing tests. + * + *****************************************************************************/ + + /* API for setting the STOP_ON_ERROR*/ + task automatic set_stop_on_error; + input LEVEL; + begin + $display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL); + STOP_ON_ERROR = LEVEL; +// M_AXI_GP0.master.set_stop_on_error(LEVEL); +// M_AXI_GP1.master.set_stop_on_error(LEVEL); +// S_AXI_GP0.slave.set_stop_on_error(LEVEL); +// S_AXI_GP1.slave.set_stop_on_error(LEVEL); +// S_AXI_HP0.slave.set_stop_on_error(LEVEL); +// S_AXI_HP1.slave.set_stop_on_error(LEVEL); +// S_AXI_HP2.slave.set_stop_on_error(LEVEL); +// S_AXI_HP3.slave.set_stop_on_error(LEVEL); +// S_AXI_ACP.slave.set_stop_on_error(LEVEL); + M_AXI_GP0.STOP_ON_ERROR = LEVEL; + M_AXI_GP1.STOP_ON_ERROR = LEVEL; + S_AXI_GP0.STOP_ON_ERROR = LEVEL; + S_AXI_GP1.STOP_ON_ERROR = LEVEL; + S_AXI_HP0.STOP_ON_ERROR = LEVEL; + S_AXI_HP1.STOP_ON_ERROR = LEVEL; + S_AXI_HP2.STOP_ON_ERROR = LEVEL; + S_AXI_HP3.STOP_ON_ERROR = LEVEL; + S_AXI_ACP.STOP_ON_ERROR = LEVEL; + + end + endtask + + /* API for setting the verbosity for channel level info*/ + task automatic set_channel_level_info; + input [1023:0] name; + input LEVEL; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL); + case(name) +// "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL); +// "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL); +// "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL); +// "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL); +// "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL); +// "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL); +// "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL); +// "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL); +// "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL); + "ALL" : begin +// M_AXI_GP0.master.set_channel_level_info(LEVEL); +// M_AXI_GP1.master.set_channel_level_info(LEVEL); +// S_AXI_GP0.slave.set_channel_level_info(LEVEL); +// S_AXI_GP1.slave.set_channel_level_info(LEVEL); +// S_AXI_HP0.slave.set_channel_level_info(LEVEL); +// S_AXI_HP1.slave.set_channel_level_info(LEVEL); +// S_AXI_HP2.slave.set_channel_level_info(LEVEL); +// S_AXI_HP3.slave.set_channel_level_info(LEVEL); +// S_AXI_ACP.slave.set_channel_level_info(LEVEL); + end + default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting the verbosity for function level info*/ + task automatic set_function_level_info; + input [1023:0] name; + input LEVEL; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL); + case(name) +// "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL); +// "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL); +// "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL); +// "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL); +// "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL); +// "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL); +// "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL); +// "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL); +// "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL); + "ALL" : begin +// M_AXI_GP0.master.set_function_level_info(LEVEL); +// M_AXI_GP1.master.set_function_level_info(LEVEL); +// S_AXI_GP0.slave.set_function_level_info(LEVEL); +// S_AXI_GP1.slave.set_function_level_info(LEVEL); +// S_AXI_HP0.slave.set_function_level_info(LEVEL); +// S_AXI_HP1.slave.set_function_level_info(LEVEL); +// S_AXI_HP2.slave.set_function_level_info(LEVEL); +// S_AXI_HP3.slave.set_function_level_info(LEVEL); +// S_AXI_ACP.slave.set_function_level_info(LEVEL); + end + default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting the Message verbosity */ + task automatic set_debug_level_info; + input LEVEL; + begin + $display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL); + DEBUG_INFO = LEVEL; + M_AXI_GP0.DEBUG_INFO = LEVEL; + M_AXI_GP1.DEBUG_INFO = LEVEL; + S_AXI_GP0.DEBUG_INFO = LEVEL; + S_AXI_GP1.DEBUG_INFO = LEVEL; + S_AXI_HP0.DEBUG_INFO = LEVEL; + S_AXI_HP1.DEBUG_INFO = LEVEL; + S_AXI_HP2.DEBUG_INFO = LEVEL; + S_AXI_HP3.DEBUG_INFO = LEVEL; + S_AXI_ACP.DEBUG_INFO = LEVEL; + end + endtask + + /* API for setting ARQos Values */ + task automatic set_arqos; + input [1023:0] name; + input [axi_qos_width-1:0] value; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_arqos(value); + "S_AXI_GP1" : S_AXI_GP1.set_arqos(value); + "S_AXI_HP0" : S_AXI_HP0.set_arqos(value); + "S_AXI_HP1" : S_AXI_HP1.set_arqos(value); + "S_AXI_HP2" : S_AXI_HP2.set_arqos(value); + "S_AXI_HP3" : S_AXI_HP3.set_arqos(value); + "S_AXI_ACP" : S_AXI_ACP.set_arqos(value); + default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for setting AWQos Values */ + task automatic set_awqos; + input [1023:0] name; + input [axi_qos_width-1:0] value; + begin + $display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_awqos(value); + "S_AXI_GP1" : S_AXI_GP1.set_awqos(value); + "S_AXI_HP0" : S_AXI_HP0.set_awqos(value); + "S_AXI_HP1" : S_AXI_HP1.set_awqos(value); + "S_AXI_HP2" : S_AXI_HP2.set_awqos(value); + "S_AXI_HP3" : S_AXI_HP3.set_awqos(value); + "S_AXI_ACP" : S_AXI_ACP.set_awqos(value); + default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name); + endcase + end + endtask + + /* API for soft reset control */ + task automatic fpga_soft_reset; + input[data_width-1:0] reset_ctrl; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl); + gen_rst.fpga_soft_reset(reset_ctrl); + end + endtask + + /* API for por and strb reset control */ +// task automatic por_srstb_reset; +// input por_reset_ctrl; +// begin +// if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO, por_reset_ctrl); +// // gen_rst.por_srstb_reset(por_reset_ctrl); +// gen_rst.por_srstb_reset(por_reset_ctrl); +// +// end +// endtask + + /* API for pre-loading memories from (DDR/OCM model) */ + task automatic pre_load_mem_from_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + succ = $fopen(file_name,"r"); + if(succ == 0) begin + $display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name); + if(STOP_ON_ERROR) $stop; + end + else if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); + else + ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + DDR_MEM : begin + ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API for pre-loading memories (DDR/OCM) */ + task automatic pre_load_mem; + input [1:0] data_type; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes); + else + ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + endtask + + /* API for backdoor write to memories (DDR/OCM) */ + task automatic write_mem; + input [max_burst_bits-1 :0] data; + input [addr_width-1:0] start_addr; + input [max_burst_bytes_width:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid); + else + ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* read_memory */ + task automatic read_mem; + input [addr_width-1:0] start_addr; + input [max_burst_bytes_width :0] no_of_bytes; + output[max_burst_bits-1 :0] data; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.read_mem(data,start_addr,no_of_bytes); + else + ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes); + end + DDR_MEM : begin + ddrc.ddr.read_mem(data,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API for backdoor read to memories (DDR/OCM) */ + task automatic peek_mem_to_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] no_of_bytes; + reg [1:0] mem_type; + integer succ; + begin + mem_type = decode_address(start_addr); + if(check_addr_aligned(start_addr)) begin + case(mem_type) + OCM_MEM : begin + if (!C_HIGH_OCM_EN) + ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes); + else + ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + DDR_MEM : begin + ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes); + if(DEBUG_INFO) + $display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name); + end + default : begin + $display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) + $stop; + end + end + endtask + + /* API to read interrupt status */ + task automatic read_interrupt; + output[irq_width-1:0] irq_status; + begin + irq_status = IRQ_F2P; + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status); + end + endtask + + /* API to wait on interrup */ + task automatic wait_interrupt; + input [3:0] irq; + output[irq_width-1:0] irq_status; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq); + + case(irq) + 0 : wait(IRQ_F2P[0] === 1'b1); + 1 : wait(IRQ_F2P[1] === 1'b1); + 2 : wait(IRQ_F2P[2] === 1'b1); + 3 : wait(IRQ_F2P[3] === 1'b1); + 4 : wait(IRQ_F2P[4] === 1'b1); + 5 : wait(IRQ_F2P[5] === 1'b1); + 6 : wait(IRQ_F2P[6] === 1'b1); + 7 : wait(IRQ_F2P[7] === 1'b1); + 8 : wait(IRQ_F2P[8] === 1'b1); + 8 : wait(IRQ_F2P[9] === 1'b1); + 10: wait(IRQ_F2P[10] === 1'b1); + 11: wait(IRQ_F2P[11] === 1'b1); + 12: wait(IRQ_F2P[12] === 1'b1); + 13: wait(IRQ_F2P[13] === 1'b1); + 14: wait(IRQ_F2P[14] === 1'b1); + 15: wait(IRQ_F2P[15] === 1'b1); + default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR); + endcase + if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq); + irq_status = IRQ_F2P; + end + endtask + + /* API to wait for a certain match pattern*/ + task automatic wait_mem_update; + input[addr_width-1:0] address; + input[data_width-1:0] data_in; + output[data_width-1:0] data_out; + reg[data_width-1:0] datao; + begin + if(mem_update_key) begin + mem_update_key = 0; + if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in); + if(check_addr_aligned(address)) begin + ddrc.ddr.wait_mem_update(address, datao); + if(datao != data_in)begin + $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao); + $stop; + end else + $display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in); + data_out = datao; + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address); + if(STOP_ON_ERROR) $stop; + end + mem_update_key = 1; + end else + $display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end + endtask + + + /* API to initiate a WRITE transaction on one of the AXI-Master ports*/ + task automatic write_from_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] wr_size; + output [axi_rsp_width-1:0] response; + integer succ; + begin + succ = $fopen(file_name,"r"); + if(succ == 0) begin + $display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name); + if(STOP_ON_ERROR) $stop; + end + else if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(check_addr_aligned(start_addr)) begin + $fclose(succ); + // case(start_addr[31:30]) + if (start_addr[31:30] === 2'b01) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name); + M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end else if(start_addr[31:30] === 2'b10) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name); + M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end else begin + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + end + // endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + endtask + + /* API to initiate a READ transaction on one of the AXI-Master ports*/ + task automatic read_to_file; + input [(max_chars*8)-1:0] file_name; + input [addr_width-1:0] start_addr; + input [int_width-1:0] rd_size; + output [axi_rsp_width-1:0] response; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr); + if(STOP_ON_ERROR) $stop; + end else if(check_addr_aligned(start_addr)) begin + // case(start_addr[31:30]) + if (start_addr[31:30] === 2'b01) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name); + M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + end else if(start_addr[31:30] === 2'b10) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name); + M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr); + // end + // default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + // endcase + end else begin + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end + end + end + endtask + + /* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/ + task automatic write_data; + input [addr_width-1:0] start_addr; + input [max_transfer_bytes_width:0] wr_size; + input [(max_transfer_bytes*8)-1:0] w_data; + output [axi_rsp_width-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(wr_size > max_transfer_bytes) begin + $display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size); + M_AXI_GP0.write_data(start_addr,wr_size,w_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size); + M_AXI_GP1.write_data(start_addr,wr_size,w_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr); + end + endtask + + /* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/ + task automatic read_data; + input [addr_width-1:0] start_addr; + input [max_transfer_bytes_width:0] rd_size; + output[(max_transfer_bytes*8)-1:0] rd_data; + output [axi_rsp_width-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(rd_size > max_transfer_bytes) begin + $display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size); + M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size); + M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr); + end + endtask + +/* Hooks to call to VIP APIs */ + task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === 2'b01) begin + // end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === 2'b10) begin + // end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response); + reg[511:0] rsp; /// string for response + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === 2'b01) begin + // end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === 2'b10) begin + // end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize); + M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic read_burst; + input [addr_width-1:0] start_addr; + input [axi_len_width-1:0] len; + input [axi_size_width-1:0] siz; + input [axi_brst_type_width-1:0] burst; + input [axi_lock_width-1:0] lck; + input [axi_cache_width-1:0] cache; + input [axi_prot_width-1:0] prot; + output [(axi_mgp_data_width*axi_burst_len)-1:0] data; + output [(axi_rsp_width*axi_burst_len)-1:0] response; + reg[511:0] rsp; + begin + if(!check_master_address(start_addr)) begin + $display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr); + if(STOP_ON_ERROR) $stop; + end else if(start_addr[31:30] === 2'b01) begin + // end else if(start_addr[31:30] === GP_M0) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr); + M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else if(start_addr[31:30] === 2'b10) begin + // end else if(start_addr[31:30] === GP_M1) begin + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr); + M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response); + rsp = get_resp(response); + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr); + end + endtask + + task automatic wait_reg_update; + input [addr_width-1:0] addr; + input [data_width-1:0] data_i; + input [data_width-1:0] mask_i; + input [int_width-1:0] time_interval; + input [int_width-1:0] time_out; + output [data_width-1:0] data_o; + + reg upd_done0; + reg upd_done1; + begin + if(!check_master_address(addr)) begin + $display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr); + if(STOP_ON_ERROR) $stop; + end else if(addr[31:30] === 2'b01) begin + // end else if(addr[31:30] === GP_M0) begin + if(reg_update_key_0) begin + reg_update_key_0 = 0; + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); + M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0); + if(DEBUG_INFO && upd_done0) + $display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); + reg_update_key_0 = 1; + end else + $display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end else if(addr[31:30] === 2'b10) begin + // end else if(addr[31:30] === GP_M1) begin + if(reg_update_key_1) begin + reg_update_key_1 = 0; + if(DEBUG_INFO) + $display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i); + M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1); + if(DEBUG_INFO && upd_done1) + $display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr); + reg_update_key_1 = 1; + end else + $display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN); + end else + $display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr); + end + endtask + +/* API to read register map */ + task read_register_map; + input [addr_width-1:0] start_addr; + input [max_regs_width:0] no_of_registers; + output[max_burst_bits-1 :0] data; + reg [max_regs_width:0] no_of_regs; + begin + no_of_regs = no_of_registers; + if(no_of_registers > 32) begin + $display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr); + no_of_regs = 32; + end + if(check_addr_aligned(start_addr)) begin + if(decode_address(start_addr) == REG_MEM) begin + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs ); + regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes + if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data ); + end else begin + $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr); + end + end else begin + data = 0; + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr); + end + end + endtask + +/* API to read single register */ + task read_register; + input [addr_width-1:0] addr; + output[data_width-1:0] data; + begin + if(check_addr_aligned(addr)) begin + if(decode_address(addr) == REG_MEM) begin + if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr ); + regc.regm.get_data(addr >> 2, data); + if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data ); + end else begin + $display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr); + end + end else begin + data = 0; + $display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr); + end + + end + endtask + + /* API to set the AXI-Slave profile*/ + task automatic set_slave_profile; + input[1023:0] name; + input[1:0] latency ; + begin + if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name); + case(name) + "S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency); + "S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency); + "S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency); + "S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency); + "S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency); + "S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency); + "S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency); + "ALL" : begin + S_AXI_GP0.set_latency_type(latency); + S_AXI_GP1.set_latency_type(latency); + S_AXI_HP0.set_latency_type(latency); + S_AXI_HP1.set_latency_type(latency); + S_AXI_HP2.set_latency_type(latency); + S_AXI_HP3.set_latency_type(latency); + S_AXI_ACP.set_latency_type(latency); + end + endcase + end + endtask + + +/*------------------------------ LOCAL APIs ------------------------------------------------ */ + + /* local API for address decoding*/ + function automatic [1:0] decode_address; + input [addr_width-1:0] address; + begin + if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr )) + decode_address = OCM_MEM; /// OCM + else if(address >= ddr_start_addr && address <= ddr_end_addr) + decode_address = DDR_MEM; /// DDR + else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr) + decode_address = OCM_MEM; /// OCM + else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr) + decode_address = REG_MEM; /// Register Map + else + decode_address = INVALID_MEM_TYPE; /// ERROR in Address + end + endfunction + + /* local API for checking address is 32-bit (4-byte) aligned */ + function automatic check_addr_aligned; + input [addr_width-1:0] address; + begin + if((address%4) !=0 ) begin // + check_addr_aligned = 0; ///not_aligned + end else + check_addr_aligned = 1; + end + endfunction + + /* local API to check address for GP Masters */ + function check_master_address; + input [addr_width-1:0] address; + begin + if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr) + check_master_address = 1'b1; + else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr) + check_master_address = 1'b1; + else + check_master_address = 1'b0; /// ERROR in Address + end + endfunction + + /* Response decode */ + function automatic [511:0] get_resp; + input[axi_rsp_width-1:0] response; + begin + case(response) + 2'b00 : get_resp = "OKAY"; + 2'b01 : get_resp = "EXOKAY"; + 2'b10 : get_resp = "SLVERR"; + 2'b11 : get_resp = "DECERR"; + endcase + end + endfunction diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_acp.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_acp.v new file mode 100644 index 0000000..3a11bbe --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_acp.v @@ -0,0 +1,94 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_5_axi_acp.v + * + * Date : 2012-11 + * + * Description : Connections for ACP port + * + *****************************************************************************/ + +/* AXI Slave ACP */ + processing_system7_vip_v1_0_5_axi_slave #( C_USE_S_AXI_ACP, // enable + axi_acp_name, // name + axi_acp_data_width, // data width + addr_width, /// address width + axi_acp_id_width, // ID width + C_S_AXI_ACP_BASEADDR, // slave base address + C_S_AXI_ACP_HIGHADDR,// slave size + axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes + axi_slv_excl_support, // Exclusive access support + axi_acp_wr_outstanding, + axi_acp_rd_outstanding) + S_AXI_ACP(.S_RESETN (net_axi_acp_rstn), + .S_ACLK (S_AXI_ACP_ACLK), + // Write Address Channel + .S_AWID (S_AXI_ACP_AWID), + .S_AWADDR (S_AXI_ACP_AWADDR), + .S_AWLEN (S_AXI_ACP_AWLEN), + .S_AWSIZE (S_AXI_ACP_AWSIZE), + .S_AWBURST (S_AXI_ACP_AWBURST), + .S_AWLOCK (S_AXI_ACP_AWLOCK), + .S_AWCACHE (S_AXI_ACP_AWCACHE), + .S_AWPROT (S_AXI_ACP_AWPROT), + .S_AWVALID (S_AXI_ACP_AWVALID), + .S_AWREADY (S_AXI_ACP_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_ACP_WID), + .S_WDATA (S_AXI_ACP_WDATA), + .S_WSTRB (S_AXI_ACP_WSTRB), + .S_WLAST (S_AXI_ACP_WLAST), + .S_WVALID (S_AXI_ACP_WVALID), + .S_WREADY (S_AXI_ACP_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_ACP_BID), + .S_BRESP (S_AXI_ACP_BRESP), + .S_BVALID (S_AXI_ACP_BVALID), + .S_BREADY (S_AXI_ACP_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_ACP_ARID), + .S_ARADDR (S_AXI_ACP_ARADDR), + .S_ARLEN (S_AXI_ACP_ARLEN), + .S_ARSIZE (S_AXI_ACP_ARSIZE), + .S_ARBURST (S_AXI_ACP_ARBURST), + .S_ARLOCK (S_AXI_ACP_ARLOCK), + .S_ARCACHE (S_AXI_ACP_ARCACHE), + .S_ARPROT (S_AXI_ACP_ARPROT), + .S_ARVALID (S_AXI_ACP_ARVALID), + .S_ARREADY (S_AXI_ACP_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_ACP_RID), + .S_RDATA (S_AXI_ACP_RDATA), + .S_RRESP (S_AXI_ACP_RRESP), + .S_RLAST (S_AXI_ACP_RLAST), + .S_RVALID (S_AXI_ACP_RVALID), + .S_RREADY (S_AXI_ACP_RREADY), + // Side band signals + .S_AWQOS (S_AXI_ACP_AWQOS), + .S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals + + .SW_CLK (net_sw_clk), +/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/ + .WR_DATA_ACK_DDR (ddr_wr_ack_port0), + .WR_DATA_ACK_OCM (ocm_wr_ack_port0), + .WR_DATA (net_wr_data_acp), + .WR_DATA_STRB (net_wr_strb_acp), + .WR_ADDR (net_wr_addr_acp), + .WR_BYTES (net_wr_bytes_acp), + .WR_DATA_VALID_DDR (ddr_wr_dv_port0), + .WR_DATA_VALID_OCM (ocm_wr_dv_port0), + .WR_QOS (net_wr_qos_acp), + + .RD_REQ_DDR (ddr_rd_req_port0), + .RD_REQ_OCM (ocm_rd_req_port0), + .RD_REQ_REG (reg_rd_req_port0), + .RD_ADDR (net_rd_addr_acp), + .RD_DATA_DDR (ddr_rd_data_port0), + .RD_DATA_OCM (ocm_rd_data_port0), + .RD_DATA_REG (reg_rd_data_port0), + .RD_BYTES (net_rd_bytes_acp), + .RD_DATA_VALID_DDR (ddr_rd_dv_port0), + .RD_DATA_VALID_OCM (ocm_rd_dv_port0), + .RD_DATA_VALID_REG (reg_rd_dv_port0), + .RD_QOS (net_rd_qos_acp) + +); diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_gp.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_gp.v new file mode 100644 index 0000000..e32105d --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_gp.v @@ -0,0 +1,311 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_5_axi_gp.v + * + * Date : 2012-11 + * + * Description : Connections for AXI GP ports + * + *****************************************************************************/ + + /* IDs for Masters + // l2m1 (CPU000) + 12'b11_000_000_00_00 + 12'b11_010_000_00_00 + 12'b11_011_000_00_00 + 12'b11_100_000_00_00 + 12'b11_101_000_00_00 + 12'b11_110_000_00_00 + 12'b11_111_000_00_00 + // l2m1 (CPU001) + 12'b11_000_001_00_00 + 12'b11_010_001_00_00 + 12'b11_011_001_00_00 + 12'b11_100_001_00_00 + 12'b11_101_001_00_00 + 12'b11_110_001_00_00 + 12'b11_111_001_00_00 + */ + +/* AXI -Master GP0 */ + processing_system7_vip_v1_0_5_axi_master #(C_USE_M_AXI_GP0, // enable + axi_mgp0_name,// name + axi_mgp_data_width, /// Data Width + addr_width, /// Address width + axi_mgp_id_width, //// ID Width + axi_mgp_outstanding, //// Outstanding transactions + axi_mst_excl_support, // EXCL Access Support + axi_mgp_wr_id, //WR_ID + axi_mgp_rd_id) //RD_ID + M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn), + .M_ACLK (M_AXI_GP0_ACLK), + // Write Address Channel + .M_AWID (M_AXI_GP0_AWID_FULL), + .M_AWADDR (M_AXI_GP0_AWADDR), + .M_AWLEN (M_AXI_GP0_AWLEN), + .M_AWSIZE (M_AXI_GP0_AWSIZE), + .M_AWBURST (M_AXI_GP0_AWBURST), + .M_AWLOCK (M_AXI_GP0_AWLOCK), + .M_AWCACHE (M_AXI_GP0_AWCACHE), + .M_AWPROT (M_AXI_GP0_AWPROT), + .M_AWVALID (M_AXI_GP0_AWVALID), + .M_AWREADY (M_AXI_GP0_AWREADY), + // Write Data Channel Signals. + .M_WID (M_AXI_GP0_WID_FULL), + .M_WDATA (M_AXI_GP0_WDATA), + .M_WSTRB (M_AXI_GP0_WSTRB), + .M_WLAST (M_AXI_GP0_WLAST), + .M_WVALID (M_AXI_GP0_WVALID), + .M_WREADY (M_AXI_GP0_WREADY), + // Write Response Channel Signals. + .M_BID (M_AXI_GP0_BID_FULL), + .M_BRESP (M_AXI_GP0_BRESP), + .M_BVALID (M_AXI_GP0_BVALID), + .M_BREADY (M_AXI_GP0_BREADY), + // Read Address Channel Signals. + .M_ARID (M_AXI_GP0_ARID_FULL), + .M_ARADDR (M_AXI_GP0_ARADDR), + .M_ARLEN (M_AXI_GP0_ARLEN), + .M_ARSIZE (M_AXI_GP0_ARSIZE), + .M_ARBURST (M_AXI_GP0_ARBURST), + .M_ARLOCK (M_AXI_GP0_ARLOCK), + .M_ARCACHE (M_AXI_GP0_ARCACHE), + .M_ARPROT (M_AXI_GP0_ARPROT), + .M_ARVALID (M_AXI_GP0_ARVALID), + .M_ARREADY (M_AXI_GP0_ARREADY), + // Read Data Channel Signals. + .M_RID (M_AXI_GP0_RID_FULL), + .M_RDATA (M_AXI_GP0_RDATA), + .M_RRESP (M_AXI_GP0_RRESP), + .M_RLAST (M_AXI_GP0_RLAST), + .M_RVALID (M_AXI_GP0_RVALID), + .M_RREADY (M_AXI_GP0_RREADY), + // Side band signals + .M_AWQOS (M_AXI_GP0_AWQOS), + .M_ARQOS (M_AXI_GP0_ARQOS) + ); + + /* AXI Master GP1 */ + processing_system7_vip_v1_0_5_axi_master #(C_USE_M_AXI_GP1, // enable + axi_mgp1_name,// name + axi_mgp_data_width, /// Data Width + addr_width, /// Address width + axi_mgp_id_width, //// ID Width + axi_mgp_outstanding, //// Outstanding transactions + axi_mst_excl_support, // EXCL Access Support + axi_mgp_wr_id, //WR_ID + axi_mgp_rd_id) //RD_ID + M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn), + .M_ACLK (M_AXI_GP1_ACLK), + // Write Address Channel + .M_AWID (M_AXI_GP1_AWID_FULL), + .M_AWADDR (M_AXI_GP1_AWADDR), + .M_AWLEN (M_AXI_GP1_AWLEN), + .M_AWSIZE (M_AXI_GP1_AWSIZE), + .M_AWBURST (M_AXI_GP1_AWBURST), + .M_AWLOCK (M_AXI_GP1_AWLOCK), + .M_AWCACHE (M_AXI_GP1_AWCACHE), + .M_AWPROT (M_AXI_GP1_AWPROT), + .M_AWVALID (M_AXI_GP1_AWVALID), + .M_AWREADY (M_AXI_GP1_AWREADY), + // Write Data Channel Signals. + .M_WID (M_AXI_GP1_WID_FULL), + .M_WDATA (M_AXI_GP1_WDATA), + .M_WSTRB (M_AXI_GP1_WSTRB), + .M_WLAST (M_AXI_GP1_WLAST), + .M_WVALID (M_AXI_GP1_WVALID), + .M_WREADY (M_AXI_GP1_WREADY), + // Write Response Channel Signals. + .M_BID (M_AXI_GP1_BID_FULL), + .M_BRESP (M_AXI_GP1_BRESP), + .M_BVALID (M_AXI_GP1_BVALID), + .M_BREADY (M_AXI_GP1_BREADY), + // Read Address Channel Signals. + .M_ARID (M_AXI_GP1_ARID_FULL), + .M_ARADDR (M_AXI_GP1_ARADDR), + .M_ARLEN (M_AXI_GP1_ARLEN), + .M_ARSIZE (M_AXI_GP1_ARSIZE), + .M_ARBURST (M_AXI_GP1_ARBURST), + .M_ARLOCK (M_AXI_GP1_ARLOCK), + .M_ARCACHE (M_AXI_GP1_ARCACHE), + .M_ARPROT (M_AXI_GP1_ARPROT), + .M_ARVALID (M_AXI_GP1_ARVALID), + .M_ARREADY (M_AXI_GP1_ARREADY), + // Read Data Channel Signals. + .M_RID (M_AXI_GP1_RID_FULL), + .M_RDATA (M_AXI_GP1_RDATA), + .M_RRESP (M_AXI_GP1_RRESP), + .M_RLAST (M_AXI_GP1_RLAST), + .M_RVALID (M_AXI_GP1_RVALID), + .M_RREADY (M_AXI_GP1_RREADY), + // Side band signals + .M_AWQOS (M_AXI_GP1_AWQOS), + .M_ARQOS (M_AXI_GP1_ARQOS) + ); + +/* AXI Slave GP0 */ + processing_system7_vip_v1_0_5_axi_slave #(C_USE_S_AXI_GP0, /// enable + axi_sgp0_name, //name + axi_sgp_data_width, /// data width + addr_width, /// address width + axi_sgp_id_width, /// ID width + C_S_AXI_GP0_BASEADDR,//// base address + C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr) + axi_sgp_outstanding, // outstanding transactions + axi_slv_excl_support, // exclusive access not supported + axi_sgp_wr_outstanding, + axi_sgp_rd_outstanding) + S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn), + .S_ACLK (S_AXI_GP0_ACLK), + // Write Address Channel + .S_AWID (S_AXI_GP0_AWID), + .S_AWADDR (S_AXI_GP0_AWADDR), + .S_AWLEN (S_AXI_GP0_AWLEN), + .S_AWSIZE (S_AXI_GP0_AWSIZE), + .S_AWBURST (S_AXI_GP0_AWBURST), + .S_AWLOCK (S_AXI_GP0_AWLOCK), + .S_AWCACHE (S_AXI_GP0_AWCACHE), + .S_AWPROT (S_AXI_GP0_AWPROT), + .S_AWVALID (S_AXI_GP0_AWVALID), + .S_AWREADY (S_AXI_GP0_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_GP0_WID), + .S_WDATA (S_AXI_GP0_WDATA), + .S_WSTRB (S_AXI_GP0_WSTRB), + .S_WLAST (S_AXI_GP0_WLAST), + .S_WVALID (S_AXI_GP0_WVALID), + .S_WREADY (S_AXI_GP0_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_GP0_BID), + .S_BRESP (S_AXI_GP0_BRESP), + .S_BVALID (S_AXI_GP0_BVALID), + .S_BREADY (S_AXI_GP0_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_GP0_ARID), + .S_ARADDR (S_AXI_GP0_ARADDR), + .S_ARLEN (S_AXI_GP0_ARLEN), + .S_ARSIZE (S_AXI_GP0_ARSIZE), + .S_ARBURST (S_AXI_GP0_ARBURST), + .S_ARLOCK (S_AXI_GP0_ARLOCK), + .S_ARCACHE (S_AXI_GP0_ARCACHE), + .S_ARPROT (S_AXI_GP0_ARPROT), + .S_ARVALID (S_AXI_GP0_ARVALID), + .S_ARREADY (S_AXI_GP0_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_GP0_RID), + .S_RDATA (S_AXI_GP0_RDATA), + .S_RRESP (S_AXI_GP0_RRESP), + .S_RLAST (S_AXI_GP0_RLAST), + .S_RVALID (S_AXI_GP0_RVALID), + .S_RREADY (S_AXI_GP0_RREADY), + // Side band signals + .S_AWQOS (S_AXI_GP0_AWQOS), + .S_ARQOS (S_AXI_GP0_ARQOS), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0), + .WR_DATA (net_wr_data_gp0), + .WR_DATA_STRB (net_wr_strb_gp0), + .WR_ADDR (net_wr_addr_gp0), + .WR_BYTES (net_wr_bytes_gp0), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0), + .WR_QOS (net_wr_qos_gp0), + .RD_REQ_DDR (net_rd_req_ddr_gp0), + .RD_REQ_OCM (net_rd_req_ocm_gp0), + .RD_REQ_REG (net_rd_req_reg_gp0), + .RD_ADDR (net_rd_addr_gp0), + .RD_DATA_DDR (net_rd_data_ddr_gp0), + .RD_DATA_OCM (net_rd_data_ocm_gp0), + .RD_DATA_REG (net_rd_data_reg_gp0), + .RD_BYTES (net_rd_bytes_gp0), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0), + .RD_DATA_VALID_REG (net_rd_dv_reg_gp0), + .RD_QOS (net_rd_qos_gp0) + +); + +/* AXI Slave GP1 */ + processing_system7_vip_v1_0_5_axi_slave #(C_USE_S_AXI_GP1, /// enable + axi_sgp1_name, //name + axi_sgp_data_width, /// data width + addr_width, /// address width + axi_sgp_id_width, /// ID width + C_S_AXI_GP1_BASEADDR,//// base address + C_S_AXI_GP1_HIGHADDR,/// HIGh_addr + axi_sgp_outstanding, // outstanding transactions + axi_slv_excl_support, // exclusive access + axi_sgp_wr_outstanding, + axi_sgp_rd_outstanding) + S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn), + .S_ACLK (S_AXI_GP1_ACLK), + // Write Address Channel + .S_AWID (S_AXI_GP1_AWID), + .S_AWADDR (S_AXI_GP1_AWADDR), + .S_AWLEN (S_AXI_GP1_AWLEN), + .S_AWSIZE (S_AXI_GP1_AWSIZE), + .S_AWBURST (S_AXI_GP1_AWBURST), + .S_AWLOCK (S_AXI_GP1_AWLOCK), + .S_AWCACHE (S_AXI_GP1_AWCACHE), + .S_AWPROT (S_AXI_GP1_AWPROT), + .S_AWVALID (S_AXI_GP1_AWVALID), + .S_AWREADY (S_AXI_GP1_AWREADY), + // Write Data Channel Signals. + .S_WID (S_AXI_GP1_WID), + .S_WDATA (S_AXI_GP1_WDATA), + .S_WSTRB (S_AXI_GP1_WSTRB), + .S_WLAST (S_AXI_GP1_WLAST), + .S_WVALID (S_AXI_GP1_WVALID), + .S_WREADY (S_AXI_GP1_WREADY), + // Write Response Channel Signals. + .S_BID (S_AXI_GP1_BID), + .S_BRESP (S_AXI_GP1_BRESP), + .S_BVALID (S_AXI_GP1_BVALID), + .S_BREADY (S_AXI_GP1_BREADY), + // Read Address Channel Signals. + .S_ARID (S_AXI_GP1_ARID), + .S_ARADDR (S_AXI_GP1_ARADDR), + .S_ARLEN (S_AXI_GP1_ARLEN), + .S_ARSIZE (S_AXI_GP1_ARSIZE), + .S_ARBURST (S_AXI_GP1_ARBURST), + .S_ARLOCK (S_AXI_GP1_ARLOCK), + .S_ARCACHE (S_AXI_GP1_ARCACHE), + .S_ARPROT (S_AXI_GP1_ARPROT), + .S_ARVALID (S_AXI_GP1_ARVALID), + .S_ARREADY (S_AXI_GP1_ARREADY), + // Read Data Channel Signals. + .S_RID (S_AXI_GP1_RID), + .S_RDATA (S_AXI_GP1_RDATA), + .S_RRESP (S_AXI_GP1_RRESP), + .S_RLAST (S_AXI_GP1_RLAST), + .S_RVALID (S_AXI_GP1_RVALID), + .S_RREADY (S_AXI_GP1_RREADY), + // Side band signals + .S_AWQOS (S_AXI_GP1_AWQOS), + .S_ARQOS (S_AXI_GP1_ARQOS), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1), + .WR_DATA (net_wr_data_gp1), + .WR_DATA_STRB (net_wr_strb_gp1), + .WR_ADDR (net_wr_addr_gp1), + .WR_BYTES (net_wr_bytes_gp1), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1), + .WR_QOS (net_wr_qos_gp1), + .RD_REQ_OCM (net_rd_req_ocm_gp1), + .RD_REQ_DDR (net_rd_req_ddr_gp1), + .RD_REQ_REG (net_rd_req_reg_gp1), + .RD_ADDR (net_rd_addr_gp1), + .RD_DATA_DDR (net_rd_data_ddr_gp1), + .RD_DATA_OCM (net_rd_data_ocm_gp1), + .RD_DATA_REG (net_rd_data_reg_gp1), + .RD_BYTES (net_rd_bytes_gp1), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1), + .RD_DATA_VALID_REG (net_rd_dv_reg_gp1), + .RD_QOS (net_rd_qos_gp1) + +); diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_hp.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_hp.v new file mode 100644 index 0000000..34d7151 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_axi_hp.v @@ -0,0 +1,350 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_5_axi_hp.v + * + * Date : 2012-11 + * + * Description : Connections for AXI HP ports + * + *****************************************************************************/ + +/* AXI Slave HP0 */ + processing_system7_vip_v1_0_5_afi_slave #( C_USE_S_AXI_HP0, // enable + axi_hp0_name, // name + C_S_AXI_HP0_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP0_BASEADDR, // slave base address + C_S_AXI_HP0_HIGHADDR, // slave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn), + .S_ACLK (S_AXI_HP0_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP0_AWID), + .S_AWADDR (S_AXI_HP0_AWADDR), + .S_AWLEN (S_AXI_HP0_AWLEN), + .S_AWSIZE (S_AXI_HP0_AWSIZE), + .S_AWBURST (S_AXI_HP0_AWBURST), + .S_AWLOCK (S_AXI_HP0_AWLOCK), + .S_AWCACHE (S_AXI_HP0_AWCACHE), + .S_AWPROT (S_AXI_HP0_AWPROT), + .S_AWVALID (S_AXI_HP0_AWVALID), + .S_AWREADY (S_AXI_HP0_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP0_WID), + .S_WDATA (S_AXI_HP0_WDATA), + .S_WSTRB (S_AXI_HP0_WSTRB), + .S_WLAST (S_AXI_HP0_WLAST), + .S_WVALID (S_AXI_HP0_WVALID), + .S_WREADY (S_AXI_HP0_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP0_BID), + .S_BRESP (S_AXI_HP0_BRESP), + .S_BVALID (S_AXI_HP0_BVALID), + .S_BREADY (S_AXI_HP0_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP0_ARID), + .S_ARADDR (S_AXI_HP0_ARADDR), + .S_ARLEN (S_AXI_HP0_ARLEN), + .S_ARSIZE (S_AXI_HP0_ARSIZE), + .S_ARBURST (S_AXI_HP0_ARBURST), + .S_ARLOCK (S_AXI_HP0_ARLOCK), + .S_ARCACHE (S_AXI_HP0_ARCACHE), + .S_ARPROT (S_AXI_HP0_ARPROT), + .S_ARVALID (S_AXI_HP0_ARVALID), + .S_ARREADY (S_AXI_HP0_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP0_RID), + .S_RDATA (S_AXI_HP0_RDATA), + .S_RRESP (S_AXI_HP0_RRESP), + .S_RLAST (S_AXI_HP0_RLAST), + .S_RVALID (S_AXI_HP0_RVALID), + .S_RREADY (S_AXI_HP0_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP0_AWQOS), + .S_ARQOS (S_AXI_HP0_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP0_RCOUNT), + .S_WCOUNT (S_AXI_HP0_WCOUNT), + .S_RACOUNT (S_AXI_HP0_RACOUNT), + .S_WACOUNT (S_AXI_HP0_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0), + .WR_DATA (net_wr_data_hp0), + .WR_DATA_STRB (net_wr_strb_hp0), + .WR_ADDR (net_wr_addr_hp0), + .WR_BYTES (net_wr_bytes_hp0), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0), + .WR_QOS (net_wr_qos_hp0), + .RD_REQ_DDR (net_rd_req_ddr_hp0), + .RD_REQ_OCM (net_rd_req_ocm_hp0), + .RD_ADDR (net_rd_addr_hp0), + .RD_DATA_DDR (net_rd_data_ddr_hp0), + .RD_DATA_OCM (net_rd_data_ocm_hp0), + .RD_BYTES (net_rd_bytes_hp0), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0), + .RD_QOS (net_rd_qos_hp0) + ); + +/* AXI Slave HP1 */ + processing_system7_vip_v1_0_5_afi_slave #( C_USE_S_AXI_HP1, // enable + axi_hp1_name, // name + C_S_AXI_HP1_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP1_BASEADDR, // slave base address + C_S_AXI_HP1_HIGHADDR, // Slave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn), + .S_ACLK (S_AXI_HP1_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP1_AWID), + .S_AWADDR (S_AXI_HP1_AWADDR), + .S_AWLEN (S_AXI_HP1_AWLEN), + .S_AWSIZE (S_AXI_HP1_AWSIZE), + .S_AWBURST (S_AXI_HP1_AWBURST), + .S_AWLOCK (S_AXI_HP1_AWLOCK), + .S_AWCACHE (S_AXI_HP1_AWCACHE), + .S_AWPROT (S_AXI_HP1_AWPROT), + .S_AWVALID (S_AXI_HP1_AWVALID), + .S_AWREADY (S_AXI_HP1_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP1_WID), + .S_WDATA (S_AXI_HP1_WDATA), + .S_WSTRB (S_AXI_HP1_WSTRB), + .S_WLAST (S_AXI_HP1_WLAST), + .S_WVALID (S_AXI_HP1_WVALID), + .S_WREADY (S_AXI_HP1_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP1_BID), + .S_BRESP (S_AXI_HP1_BRESP), + .S_BVALID (S_AXI_HP1_BVALID), + .S_BREADY (S_AXI_HP1_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP1_ARID), + .S_ARADDR (S_AXI_HP1_ARADDR), + .S_ARLEN (S_AXI_HP1_ARLEN), + .S_ARSIZE (S_AXI_HP1_ARSIZE), + .S_ARBURST (S_AXI_HP1_ARBURST), + .S_ARLOCK (S_AXI_HP1_ARLOCK), + .S_ARCACHE (S_AXI_HP1_ARCACHE), + .S_ARPROT (S_AXI_HP1_ARPROT), + .S_ARVALID (S_AXI_HP1_ARVALID), + .S_ARREADY (S_AXI_HP1_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP1_RID), + .S_RDATA (S_AXI_HP1_RDATA), + .S_RRESP (S_AXI_HP1_RRESP), + .S_RLAST (S_AXI_HP1_RLAST), + .S_RVALID (S_AXI_HP1_RVALID), + .S_RREADY (S_AXI_HP1_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP1_AWQOS), + .S_ARQOS (S_AXI_HP1_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP1_RCOUNT), + .S_WCOUNT (S_AXI_HP1_WCOUNT), + .S_RACOUNT (S_AXI_HP1_RACOUNT), + .S_WACOUNT (S_AXI_HP1_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1), + .WR_DATA (net_wr_data_hp1), + .WR_DATA_STRB (net_wr_strb_hp1), + .WR_ADDR (net_wr_addr_hp1), + .WR_BYTES (net_wr_bytes_hp1), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1), + .WR_QOS (net_wr_qos_hp1), + .RD_REQ_DDR (net_rd_req_ddr_hp1), + .RD_REQ_OCM (net_rd_req_ocm_hp1), + .RD_ADDR (net_rd_addr_hp1), + .RD_DATA_DDR (net_rd_data_ddr_hp1), + .RD_DATA_OCM (net_rd_data_ocm_hp1), + .RD_BYTES (net_rd_bytes_hp1), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1), + .RD_QOS (net_rd_qos_hp1) + + ); + +/* AXI Slave HP2 */ + processing_system7_vip_v1_0_5_afi_slave #( C_USE_S_AXI_HP2, // enable + axi_hp2_name, // name + C_S_AXI_HP2_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP2_BASEADDR, // slave base address + C_S_AXI_HP2_HIGHADDR, // SLave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn), + .S_ACLK (S_AXI_HP2_ACLK), + // Write Address channel + .S_AWID (S_AXI_HP2_AWID), + .S_AWADDR (S_AXI_HP2_AWADDR), + .S_AWLEN (S_AXI_HP2_AWLEN), + .S_AWSIZE (S_AXI_HP2_AWSIZE), + .S_AWBURST (S_AXI_HP2_AWBURST), + .S_AWLOCK (S_AXI_HP2_AWLOCK), + .S_AWCACHE (S_AXI_HP2_AWCACHE), + .S_AWPROT (S_AXI_HP2_AWPROT), + .S_AWVALID (S_AXI_HP2_AWVALID), + .S_AWREADY (S_AXI_HP2_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP2_WID), + .S_WDATA (S_AXI_HP2_WDATA), + .S_WSTRB (S_AXI_HP2_WSTRB), + .S_WLAST (S_AXI_HP2_WLAST), + .S_WVALID (S_AXI_HP2_WVALID), + .S_WREADY (S_AXI_HP2_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP2_BID), + .S_BRESP (S_AXI_HP2_BRESP), + .S_BVALID (S_AXI_HP2_BVALID), + .S_BREADY (S_AXI_HP2_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP2_ARID), + .S_ARADDR (S_AXI_HP2_ARADDR), + .S_ARLEN (S_AXI_HP2_ARLEN), + .S_ARSIZE (S_AXI_HP2_ARSIZE), + .S_ARBURST (S_AXI_HP2_ARBURST), + .S_ARLOCK (S_AXI_HP2_ARLOCK), + .S_ARCACHE (S_AXI_HP2_ARCACHE), + .S_ARPROT (S_AXI_HP2_ARPROT), + .S_ARVALID (S_AXI_HP2_ARVALID), + .S_ARREADY (S_AXI_HP2_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP2_RID), + .S_RDATA (S_AXI_HP2_RDATA), + .S_RRESP (S_AXI_HP2_RRESP), + .S_RLAST (S_AXI_HP2_RLAST), + .S_RVALID (S_AXI_HP2_RVALID), + .S_RREADY (S_AXI_HP2_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP2_AWQOS), + .S_ARQOS (S_AXI_HP2_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP2_RCOUNT), + .S_WCOUNT (S_AXI_HP2_WCOUNT), + .S_RACOUNT (S_AXI_HP2_RACOUNT), + .S_WACOUNT (S_AXI_HP2_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2), + .WR_DATA (net_wr_data_hp2), + .WR_DATA_STRB (net_wr_strb_hp2), + .WR_ADDR (net_wr_addr_hp2), + .WR_BYTES (net_wr_bytes_hp2), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2), + .WR_QOS (net_wr_qos_hp2), + .RD_REQ_DDR (net_rd_req_ddr_hp2), + .RD_REQ_OCM (net_rd_req_ocm_hp2), + .RD_ADDR (net_rd_addr_hp2), + .RD_DATA_DDR (net_rd_data_ddr_hp2), + .RD_DATA_OCM (net_rd_data_ocm_hp2), + .RD_BYTES (net_rd_bytes_hp2), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2), + .RD_QOS (net_rd_qos_hp2) + + ); + +/* AXI Slave HP3 */ + processing_system7_vip_v1_0_5_afi_slave #( C_USE_S_AXI_HP3, // enable + axi_hp3_name, // name + C_S_AXI_HP3_DATA_WIDTH, // data width + addr_width, /// address width + axi_hp_id_width, // ID width + C_S_AXI_HP3_BASEADDR, // slave base address + C_S_AXI_HP3_HIGHADDR, // SLave size + axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports + axi_slv_excl_support) // Exclusive access support + S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn), + .S_ACLK (S_AXI_HP3_ACLK), + // Write ADDRESS CHANNEL + .S_AWID (S_AXI_HP3_AWID), + .S_AWADDR (S_AXI_HP3_AWADDR), + .S_AWLEN (S_AXI_HP3_AWLEN), + .S_AWSIZE (S_AXI_HP3_AWSIZE), + .S_AWBURST (S_AXI_HP3_AWBURST), + .S_AWLOCK (S_AXI_HP3_AWLOCK), + .S_AWCACHE (S_AXI_HP3_AWCACHE), + .S_AWPROT (S_AXI_HP3_AWPROT), + .S_AWVALID (S_AXI_HP3_AWVALID), + .S_AWREADY (S_AXI_HP3_AWREADY), + // Write Data channel signals. + .S_WID (S_AXI_HP3_WID), + .S_WDATA (S_AXI_HP3_WDATA), + .S_WSTRB (S_AXI_HP3_WSTRB), + .S_WLAST (S_AXI_HP3_WLAST), + .S_WVALID (S_AXI_HP3_WVALID), + .S_WREADY (S_AXI_HP3_WREADY), + // Write Response channel signals. + .S_BID (S_AXI_HP3_BID), + .S_BRESP (S_AXI_HP3_BRESP), + .S_BVALID (S_AXI_HP3_BVALID), + .S_BREADY (S_AXI_HP3_BREADY), + // Read Address channel signals. + .S_ARID (S_AXI_HP3_ARID), + .S_ARADDR (S_AXI_HP3_ARADDR), + .S_ARLEN (S_AXI_HP3_ARLEN), + .S_ARSIZE (S_AXI_HP3_ARSIZE), + .S_ARBURST (S_AXI_HP3_ARBURST), + .S_ARLOCK (S_AXI_HP3_ARLOCK), + .S_ARCACHE (S_AXI_HP3_ARCACHE), + .S_ARPROT (S_AXI_HP3_ARPROT), + .S_ARVALID (S_AXI_HP3_ARVALID), + .S_ARREADY (S_AXI_HP3_ARREADY), + // Read Data channel signals. + .S_RID (S_AXI_HP3_RID), + .S_RDATA (S_AXI_HP3_RDATA), + .S_RRESP (S_AXI_HP3_RRESP), + .S_RLAST (S_AXI_HP3_RLAST), + .S_RVALID (S_AXI_HP3_RVALID), + .S_RREADY (S_AXI_HP3_RREADY), + // Side band signals + .S_AWQOS (S_AXI_HP3_AWQOS), + .S_ARQOS (S_AXI_HP3_ARQOS), + // these are needed only for HP ports + .S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN), + .S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN), + .S_RCOUNT (S_AXI_HP3_RCOUNT), + .S_WCOUNT (S_AXI_HP3_WCOUNT), + .S_RACOUNT (S_AXI_HP3_RACOUNT), + .S_WACOUNT (S_AXI_HP3_WACOUNT), + + .SW_CLK (net_sw_clk), + .WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3), + .WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3), + .WR_DATA (net_wr_data_hp3), + .WR_DATA_STRB (net_wr_strb_hp3), + .WR_ADDR (net_wr_addr_hp3), + .WR_BYTES (net_wr_bytes_hp3), + .WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3), + .WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3), + .WR_QOS (net_wr_qos_hp3), + .RD_REQ_DDR (net_rd_req_ddr_hp3), + .RD_REQ_OCM (net_rd_req_ocm_hp3), + .RD_ADDR (net_rd_addr_hp3), + .RD_DATA_DDR (net_rd_data_ddr_hp3), + .RD_DATA_OCM (net_rd_data_ocm_hp3), + .RD_BYTES (net_rd_bytes_hp3), + .RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3), + .RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3), + .RD_QOS (net_rd_qos_hp3) + ); diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_local_params.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_local_params.v new file mode 100644 index 0000000..d30fd2a --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_local_params.v @@ -0,0 +1,244 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_5_local_params.v + * + * Date : 2012-11 + * + * Description : Parameters used in Zynq VIP + * + *****************************************************************************/ + + +/* local */ +parameter m_axi_gp0_baseaddr = 32'h4000_0000; +parameter m_axi_gp1_baseaddr = 32'h8000_0000; +parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF; +parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF; + +parameter addr_width = 32; // maximum address width +parameter data_width = 32; // maximum data width. +parameter max_chars = 128; // max characters for file name +parameter mem_width = data_width/8; /// memory width in bytes +parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted +parameter int_width = 32; //integre width + +/* for internal read/write APIs used for data transfers */ +parameter max_burst_len = 16; /// maximum brst length on axi +parameter max_data_width = 64; // maximum data width for internal AXI bursts +parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts +parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer +parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts + +parameter max_registers = 32; +parameter max_regs_width = clogb2(max_registers); + +parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11; + +/* Interrupt bits supported */ +parameter irq_width = 16; + +/* GP Master0 & Master1 address decode */ +parameter GP_M0 = 2'b01; +parameter GP_M1 = 2'b10; + +parameter ALL_RANDOM= 2'b00; +parameter ALL_ZEROS = 2'b01; +parameter ALL_ONES = 2'b10; + +parameter ddr_start_addr = 32'h0008_0000; +parameter ddr_end_addr = 32'h3FFF_FFFF; + +parameter ocm_start_addr = 32'h0000_0000; +parameter ocm_end_addr = 32'h0003_FFFF; +parameter high_ocm_start_addr = 32'hFFFC_0000; +parameter high_ocm_end_addr = 32'hFFFF_FFFF; +parameter ocm_low_addr = 32'hFFFF_0000; + +parameter reg_start_addr = 32'hE000_0000; +parameter reg_end_addr = 32'hF8F0_2F80; + + +/* for Master port APIs and AXI protocol related signal widths*/ +parameter axi_burst_len = 16; +parameter axi_len_width = clogb2(axi_burst_len); +parameter axi_size_width = 3; +parameter axi_brst_type_width = 2; +parameter axi_lock_width = 2; +parameter axi_cache_width = 4; +parameter axi_prot_width = 3; +parameter axi_rsp_width = 2; +parameter axi_mgp_data_width = 32; +parameter axi_mgp_id_width = 12; +parameter axi_mgp_outstanding = 8; +parameter axi_mgp_wr_id = 12'hC00; +parameter axi_mgp_rd_id = 12'hC0C; +parameter axi_mgp0_name = "M_AXI_GP0"; +parameter axi_mgp1_name = "M_AXI_GP1"; +parameter axi_qos_width = 4; +parameter max_transfer_bytes = 256; // For Master APIs. +parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs. + + +/* for GP slave ports*/ +parameter axi_sgp_data_width = 32; +parameter axi_sgp_id_width = 6; +parameter axi_sgp_rd_outstanding = 8; +parameter axi_sgp_wr_outstanding = 8; +parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding; +parameter axi_sgp0_name = "S_AXI_GP0"; +parameter axi_sgp1_name = "S_AXI_GP1"; + +/* for ACP slave ports*/ +parameter axi_acp_data_width = 64; +parameter axi_acp_id_width = 3; +parameter axi_acp_rd_outstanding = 7; +parameter axi_acp_wr_outstanding = 3; +parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding; +parameter axi_acp_name = "S_AXI_ACP"; + +/* for HP slave ports*/ +parameter axi_hp_id_width = 6; +parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT .. +parameter axi_hp0_name = "S_AXI_HP0"; +parameter axi_hp1_name = "S_AXI_HP1"; +parameter axi_hp2_name = "S_AXI_HP2"; +parameter axi_hp3_name = "S_AXI_HP3"; + + +parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported +parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported + +/* AXI transfer types */ +parameter AXI_FIXED = 2'b00; +parameter AXI_INCR = 2'b01; +parameter AXI_WRAP = 2'b10; + +/* Exclusive Access */ +parameter AXI_NRML = 2'b00; +parameter AXI_EXCL = 2'b01; +parameter AXI_LOCK = 2'b10; + +/* AXI Response types */ +parameter AXI_OK = 2'b00; +parameter AXI_EXCL_OK = 2'b01; +parameter AXI_SLV_ERR = 2'b10; +parameter AXI_DEC_ERR = 2'b11; + +function automatic integer clogb2; + input [31:0] value; + begin + value = value - 1; + for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin + value = value >> 1; + end + end +endfunction + +/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */ + /* WR FIFO data */ + // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1); + // parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1); + // parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1); + parameter wr_bytes_lsb = 0; + parameter wr_bytes_msb = max_burst_bytes_width; + parameter wr_addr_lsb = wr_bytes_msb + 1; + parameter wr_addr_msb = wr_addr_lsb + addr_width-1; + parameter wr_data_lsb = wr_addr_msb + 1; + // parameter wr_data_msb = wr_data_lsb + max_burst_bits-1; + // parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1; + // parameter wr_qos_lsb = wr_data_msb + 1; + // `parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1; + + /* WR AFI FIFO data */ + /* ID - 1071:1066 + Resp - 1065:1064 + data - 1063:40 + address - 39:8 + valid_bytes - 7:0 + */ + // parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1); + // parameter wr_afi_bytes_lsb = 0; + // parameter wr_afi_bytes_msb = max_burst_bytes_width; + // parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1; + // parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1; + // parameter wr_afi_data_lsb = wr_afi_addr_msb + 1; + // parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1; + // parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1; + // parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1; + // parameter wr_afi_ln_lsb = wr_afi_id_msb + 1; + // parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1; + // parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1; + // parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1; + + + parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes + parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes) + parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location + +/* for interconnect fifo models */ + parameter intr_max_outstanding = 8; + parameter intr_cnt_width = clogb2(intr_max_outstanding)+1; + parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1); + parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ; + + //Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes + parameter rd_afi_bytes_lsb = 0; + parameter rd_afi_bytes_msb = max_burst_bytes_width; + parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1; + parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1; + parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1; + parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1; + parameter rd_afi_ln_lsb = rd_afi_id_msb + 1; + parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1; + parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1; + parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1; + parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1; + parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1; + parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1; + parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1; + parameter rd_afi_data_lsb = rd_afi_addr_msb + 1; + parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1; + + +/* Latency types */ + parameter BEST_CASE = 0; + parameter AVG_CASE = 1; + parameter WORST_CASE = 2; + parameter RANDOM_CASE = 3; + +/* Latency Parameters ACP */ + parameter acp_wr_min = 21; + parameter acp_wr_avg = 16; + parameter acp_wr_max = 27; + parameter acp_rd_min = 34; + parameter acp_rd_avg = 125; + parameter acp_rd_max = 130; + +/* Latency Parameters GP */ + parameter gp_wr_min = 21; + parameter gp_wr_avg = 16; + parameter gp_wr_max = 46; + parameter gp_rd_min = 38; + parameter gp_rd_avg = 125; + parameter gp_rd_max = 130; + +/* Latency Parameters HP */ + parameter afi_wr_min = 37; + parameter afi_wr_avg = 41; + parameter afi_wr_max = 42; + parameter afi_rd_min = 41; + parameter afi_rd_avg = 221; + parameter afi_rd_max = 229; + +/* ID VALID and INVALID */ + parameter secure_access_enabled = 0; + parameter id_invalid = 0; + parameter id_valid = 1; + +/* Display */ + parameter DISP_INFO = "*ZYNQ_VIP_INFO"; + parameter DISP_WARN = "*ZYNQ_VIP_WARNING"; + parameter DISP_ERR = "*ZYNQ_VIP_ERROR"; + parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO"; + + parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_reg_init.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_reg_init.v new file mode 100644 index 0000000..83ed258 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_reg_init.v @@ -0,0 +1,2924 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_5_reg_init.v + * + * Date : 2012-11 + * + * Description : Initialize register default values. + * + *****************************************************************************/ + +// Register default value info for chip pele_ps +// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 +// 54 modules, 2532 registers. + + +// ************************************************************ +// Module afi0 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi0__AFI_RDCHAN_CTRL, val_afi0__AFI_RDCHAN_CTRL); +set_reset_data( afi0__AFI_RDCHAN_ISSUINGCAP, val_afi0__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi0__AFI_RDQOS, val_afi0__AFI_RDQOS); +set_reset_data( afi0__AFI_RDDATAFIFO_LEVEL, val_afi0__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi0__AFI_RDDEBUG, val_afi0__AFI_RDDEBUG); +set_reset_data( afi0__AFI_WRCHAN_CTRL, val_afi0__AFI_WRCHAN_CTRL); +set_reset_data( afi0__AFI_WRCHAN_ISSUINGCAP, val_afi0__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi0__AFI_WRQOS, val_afi0__AFI_WRQOS); +set_reset_data( afi0__AFI_WRDATAFIFO_LEVEL, val_afi0__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi0__AFI_WRDEBUG, val_afi0__AFI_WRDEBUG); + +// ************************************************************ +// Module afi1 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi1__AFI_RDCHAN_CTRL, val_afi1__AFI_RDCHAN_CTRL); +set_reset_data( afi1__AFI_RDCHAN_ISSUINGCAP, val_afi1__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi1__AFI_RDQOS, val_afi1__AFI_RDQOS); +set_reset_data( afi1__AFI_RDDATAFIFO_LEVEL, val_afi1__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi1__AFI_RDDEBUG, val_afi1__AFI_RDDEBUG); +set_reset_data( afi1__AFI_WRCHAN_CTRL, val_afi1__AFI_WRCHAN_CTRL); +set_reset_data( afi1__AFI_WRCHAN_ISSUINGCAP, val_afi1__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi1__AFI_WRQOS, val_afi1__AFI_WRQOS); +set_reset_data( afi1__AFI_WRDATAFIFO_LEVEL, val_afi1__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi1__AFI_WRDEBUG, val_afi1__AFI_WRDEBUG); + +// ************************************************************ +// Module afi2 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi2__AFI_RDCHAN_CTRL, val_afi2__AFI_RDCHAN_CTRL); +set_reset_data( afi2__AFI_RDCHAN_ISSUINGCAP, val_afi2__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi2__AFI_RDQOS, val_afi2__AFI_RDQOS); +set_reset_data( afi2__AFI_RDDATAFIFO_LEVEL, val_afi2__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi2__AFI_RDDEBUG, val_afi2__AFI_RDDEBUG); +set_reset_data( afi2__AFI_WRCHAN_CTRL, val_afi2__AFI_WRCHAN_CTRL); +set_reset_data( afi2__AFI_WRCHAN_ISSUINGCAP, val_afi2__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi2__AFI_WRQOS, val_afi2__AFI_WRQOS); +set_reset_data( afi2__AFI_WRDATAFIFO_LEVEL, val_afi2__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi2__AFI_WRDEBUG, val_afi2__AFI_WRDEBUG); + +// ************************************************************ +// Module afi3 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( afi3__AFI_RDCHAN_CTRL, val_afi3__AFI_RDCHAN_CTRL); +set_reset_data( afi3__AFI_RDCHAN_ISSUINGCAP, val_afi3__AFI_RDCHAN_ISSUINGCAP); +set_reset_data( afi3__AFI_RDQOS, val_afi3__AFI_RDQOS); +set_reset_data( afi3__AFI_RDDATAFIFO_LEVEL, val_afi3__AFI_RDDATAFIFO_LEVEL); +set_reset_data( afi3__AFI_RDDEBUG, val_afi3__AFI_RDDEBUG); +set_reset_data( afi3__AFI_WRCHAN_CTRL, val_afi3__AFI_WRCHAN_CTRL); +set_reset_data( afi3__AFI_WRCHAN_ISSUINGCAP, val_afi3__AFI_WRCHAN_ISSUINGCAP); +set_reset_data( afi3__AFI_WRQOS, val_afi3__AFI_WRQOS); +set_reset_data( afi3__AFI_WRDATAFIFO_LEVEL, val_afi3__AFI_WRDATAFIFO_LEVEL); +set_reset_data( afi3__AFI_WRDEBUG, val_afi3__AFI_WRDEBUG); + +// ************************************************************ +// Module can0 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( can0__SRR, val_can0__SRR); +set_reset_data( can0__MSR, val_can0__MSR); +set_reset_data( can0__BRPR, val_can0__BRPR); +set_reset_data( can0__BTR, val_can0__BTR); +set_reset_data( can0__ECR, val_can0__ECR); +set_reset_data( can0__ESR, val_can0__ESR); +set_reset_data( can0__SR, val_can0__SR); +set_reset_data( can0__ISR, val_can0__ISR); +set_reset_data( can0__IER, val_can0__IER); +set_reset_data( can0__ICR, val_can0__ICR); +set_reset_data( can0__TCR, val_can0__TCR); +set_reset_data( can0__WIR, val_can0__WIR); +set_reset_data( can0__TXFIFO_ID, val_can0__TXFIFO_ID); +set_reset_data( can0__TXFIFO_DLC, val_can0__TXFIFO_DLC); +set_reset_data( can0__TXFIFO_DATA1, val_can0__TXFIFO_DATA1); +set_reset_data( can0__TXFIFO_DATA2, val_can0__TXFIFO_DATA2); +set_reset_data( can0__TXHPB_ID, val_can0__TXHPB_ID); +set_reset_data( can0__TXHPB_DLC, val_can0__TXHPB_DLC); +set_reset_data( can0__TXHPB_DATA1, val_can0__TXHPB_DATA1); +set_reset_data( can0__TXHPB_DATA2, val_can0__TXHPB_DATA2); +set_reset_data( can0__RXFIFO_ID, val_can0__RXFIFO_ID); +set_reset_data( can0__RXFIFO_DLC, val_can0__RXFIFO_DLC); +set_reset_data( can0__RXFIFO_DATA1, val_can0__RXFIFO_DATA1); +set_reset_data( can0__RXFIFO_DATA2, val_can0__RXFIFO_DATA2); +set_reset_data( can0__AFR, val_can0__AFR); +set_reset_data( can0__AFMR1, val_can0__AFMR1); +set_reset_data( can0__AFIR1, val_can0__AFIR1); +set_reset_data( can0__AFMR2, val_can0__AFMR2); +set_reset_data( can0__AFIR2, val_can0__AFIR2); +set_reset_data( can0__AFMR3, val_can0__AFMR3); +set_reset_data( can0__AFIR3, val_can0__AFIR3); +set_reset_data( can0__AFMR4, val_can0__AFMR4); +set_reset_data( can0__AFIR4, val_can0__AFIR4); + +// ************************************************************ +// Module can1 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( can1__SRR, val_can1__SRR); +set_reset_data( can1__MSR, val_can1__MSR); +set_reset_data( can1__BRPR, val_can1__BRPR); +set_reset_data( can1__BTR, val_can1__BTR); +set_reset_data( can1__ECR, val_can1__ECR); +set_reset_data( can1__ESR, val_can1__ESR); +set_reset_data( can1__SR, val_can1__SR); +set_reset_data( can1__ISR, val_can1__ISR); +set_reset_data( can1__IER, val_can1__IER); +set_reset_data( can1__ICR, val_can1__ICR); +set_reset_data( can1__TCR, val_can1__TCR); +set_reset_data( can1__WIR, val_can1__WIR); +set_reset_data( can1__TXFIFO_ID, val_can1__TXFIFO_ID); +set_reset_data( can1__TXFIFO_DLC, val_can1__TXFIFO_DLC); +set_reset_data( can1__TXFIFO_DATA1, val_can1__TXFIFO_DATA1); +set_reset_data( can1__TXFIFO_DATA2, val_can1__TXFIFO_DATA2); +set_reset_data( can1__TXHPB_ID, val_can1__TXHPB_ID); +set_reset_data( can1__TXHPB_DLC, val_can1__TXHPB_DLC); +set_reset_data( can1__TXHPB_DATA1, val_can1__TXHPB_DATA1); +set_reset_data( can1__TXHPB_DATA2, val_can1__TXHPB_DATA2); +set_reset_data( can1__RXFIFO_ID, val_can1__RXFIFO_ID); +set_reset_data( can1__RXFIFO_DLC, val_can1__RXFIFO_DLC); +set_reset_data( can1__RXFIFO_DATA1, val_can1__RXFIFO_DATA1); +set_reset_data( can1__RXFIFO_DATA2, val_can1__RXFIFO_DATA2); +set_reset_data( can1__AFR, val_can1__AFR); +set_reset_data( can1__AFMR1, val_can1__AFMR1); +set_reset_data( can1__AFIR1, val_can1__AFIR1); +set_reset_data( can1__AFMR2, val_can1__AFMR2); +set_reset_data( can1__AFIR2, val_can1__AFIR2); +set_reset_data( can1__AFMR3, val_can1__AFMR3); +set_reset_data( can1__AFIR3, val_can1__AFIR3); +set_reset_data( can1__AFMR4, val_can1__AFMR4); +set_reset_data( can1__AFIR4, val_can1__AFIR4); + +// ************************************************************ +// Module ddrc ddrc +// doc version: 1.25 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ddrc__ddrc_ctrl, val_ddrc__ddrc_ctrl); +set_reset_data( ddrc__Two_rank_cfg, val_ddrc__Two_rank_cfg); +set_reset_data( ddrc__HPR_reg, val_ddrc__HPR_reg); +set_reset_data( ddrc__LPR_reg, val_ddrc__LPR_reg); +set_reset_data( ddrc__WR_reg, val_ddrc__WR_reg); +set_reset_data( ddrc__DRAM_param_reg0, val_ddrc__DRAM_param_reg0); +set_reset_data( ddrc__DRAM_param_reg1, val_ddrc__DRAM_param_reg1); +set_reset_data( ddrc__DRAM_param_reg2, val_ddrc__DRAM_param_reg2); +set_reset_data( ddrc__DRAM_param_reg3, val_ddrc__DRAM_param_reg3); +set_reset_data( ddrc__DRAM_param_reg4, val_ddrc__DRAM_param_reg4); +set_reset_data( ddrc__DRAM_init_param, val_ddrc__DRAM_init_param); +set_reset_data( ddrc__DRAM_EMR_reg, val_ddrc__DRAM_EMR_reg); +set_reset_data( ddrc__DRAM_EMR_MR_reg, val_ddrc__DRAM_EMR_MR_reg); +set_reset_data( ddrc__DRAM_burst8_rdwr, val_ddrc__DRAM_burst8_rdwr); +set_reset_data( ddrc__DRAM_disable_DQ, val_ddrc__DRAM_disable_DQ); +set_reset_data( ddrc__DRAM_addr_map_bank, val_ddrc__DRAM_addr_map_bank); +set_reset_data( ddrc__DRAM_addr_map_col, val_ddrc__DRAM_addr_map_col); +set_reset_data( ddrc__DRAM_addr_map_row, val_ddrc__DRAM_addr_map_row); +set_reset_data( ddrc__DRAM_ODT_reg, val_ddrc__DRAM_ODT_reg); +set_reset_data( ddrc__phy_dbg_reg, val_ddrc__phy_dbg_reg); +set_reset_data( ddrc__phy_cmd_timeout_rddata_cpt, val_ddrc__phy_cmd_timeout_rddata_cpt); +set_reset_data( ddrc__mode_sts_reg, val_ddrc__mode_sts_reg); +set_reset_data( ddrc__DLL_calib, val_ddrc__DLL_calib); +set_reset_data( ddrc__ODT_delay_hold, val_ddrc__ODT_delay_hold); +set_reset_data( ddrc__ctrl_reg1, val_ddrc__ctrl_reg1); +set_reset_data( ddrc__ctrl_reg2, val_ddrc__ctrl_reg2); +set_reset_data( ddrc__ctrl_reg3, val_ddrc__ctrl_reg3); +set_reset_data( ddrc__ctrl_reg4, val_ddrc__ctrl_reg4); +set_reset_data( ddrc__ctrl_reg5, val_ddrc__ctrl_reg5); +set_reset_data( ddrc__ctrl_reg6, val_ddrc__ctrl_reg6); +set_reset_data( ddrc__CHE_REFRESH_TIMER01, val_ddrc__CHE_REFRESH_TIMER01); +set_reset_data( ddrc__CHE_T_ZQ, val_ddrc__CHE_T_ZQ); +set_reset_data( ddrc__CHE_T_ZQ_Short_Interval_Reg, val_ddrc__CHE_T_ZQ_Short_Interval_Reg); +set_reset_data( ddrc__deep_pwrdwn_reg, val_ddrc__deep_pwrdwn_reg); +set_reset_data( ddrc__reg_2c, val_ddrc__reg_2c); +set_reset_data( ddrc__reg_2d, val_ddrc__reg_2d); +set_reset_data( ddrc__dfi_timing, val_ddrc__dfi_timing); +set_reset_data( ddrc__refresh_timer_2, val_ddrc__refresh_timer_2); +set_reset_data( ddrc__nc_timing, val_ddrc__nc_timing); +set_reset_data( ddrc__CHE_ECC_CONTROL_REG_OFFSET, val_ddrc__CHE_ECC_CONTROL_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET); +set_reset_data( ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET); +set_reset_data( ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET); +set_reset_data( ddrc__CHE_ECC_STATS_REG_OFFSET, val_ddrc__CHE_ECC_STATS_REG_OFFSET); +set_reset_data( ddrc__ECC_scrub, val_ddrc__ECC_scrub); +set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET); +set_reset_data( ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET); +set_reset_data( ddrc__phy_rcvr_enable, val_ddrc__phy_rcvr_enable); +set_reset_data( ddrc__PHY_Config0, val_ddrc__PHY_Config0); +set_reset_data( ddrc__PHY_Config1, val_ddrc__PHY_Config1); +set_reset_data( ddrc__PHY_Config2, val_ddrc__PHY_Config2); +set_reset_data( ddrc__PHY_Config3, val_ddrc__PHY_Config3); +set_reset_data( ddrc__phy_init_ratio0, val_ddrc__phy_init_ratio0); +set_reset_data( ddrc__phy_init_ratio1, val_ddrc__phy_init_ratio1); +set_reset_data( ddrc__phy_init_ratio2, val_ddrc__phy_init_ratio2); +set_reset_data( ddrc__phy_init_ratio3, val_ddrc__phy_init_ratio3); +set_reset_data( ddrc__phy_rd_dqs_cfg0, val_ddrc__phy_rd_dqs_cfg0); +set_reset_data( ddrc__phy_rd_dqs_cfg1, val_ddrc__phy_rd_dqs_cfg1); +set_reset_data( ddrc__phy_rd_dqs_cfg2, val_ddrc__phy_rd_dqs_cfg2); +set_reset_data( ddrc__phy_rd_dqs_cfg3, val_ddrc__phy_rd_dqs_cfg3); +set_reset_data( ddrc__phy_wr_dqs_cfg0, val_ddrc__phy_wr_dqs_cfg0); +set_reset_data( ddrc__phy_wr_dqs_cfg1, val_ddrc__phy_wr_dqs_cfg1); +set_reset_data( ddrc__phy_wr_dqs_cfg2, val_ddrc__phy_wr_dqs_cfg2); +set_reset_data( ddrc__phy_wr_dqs_cfg3, val_ddrc__phy_wr_dqs_cfg3); +set_reset_data( ddrc__phy_we_cfg0, val_ddrc__phy_we_cfg0); +set_reset_data( ddrc__phy_we_cfg1, val_ddrc__phy_we_cfg1); +set_reset_data( ddrc__phy_we_cfg2, val_ddrc__phy_we_cfg2); +set_reset_data( ddrc__phy_we_cfg3, val_ddrc__phy_we_cfg3); +set_reset_data( ddrc__wr_data_slv0, val_ddrc__wr_data_slv0); +set_reset_data( ddrc__wr_data_slv1, val_ddrc__wr_data_slv1); +set_reset_data( ddrc__wr_data_slv2, val_ddrc__wr_data_slv2); +set_reset_data( ddrc__wr_data_slv3, val_ddrc__wr_data_slv3); +set_reset_data( ddrc__reg_64, val_ddrc__reg_64); +set_reset_data( ddrc__reg_65, val_ddrc__reg_65); +set_reset_data( ddrc__reg69_6a0, val_ddrc__reg69_6a0); +set_reset_data( ddrc__reg69_6a1, val_ddrc__reg69_6a1); +set_reset_data( ddrc__reg6c_6d2, val_ddrc__reg6c_6d2); +set_reset_data( ddrc__reg6c_6d3, val_ddrc__reg6c_6d3); +set_reset_data( ddrc__reg6e_710, val_ddrc__reg6e_710); +set_reset_data( ddrc__reg6e_711, val_ddrc__reg6e_711); +set_reset_data( ddrc__reg6e_712, val_ddrc__reg6e_712); +set_reset_data( ddrc__reg6e_713, val_ddrc__reg6e_713); +set_reset_data( ddrc__phy_dll_sts0, val_ddrc__phy_dll_sts0); +set_reset_data( ddrc__phy_dll_sts1, val_ddrc__phy_dll_sts1); +set_reset_data( ddrc__phy_dll_sts2, val_ddrc__phy_dll_sts2); +set_reset_data( ddrc__phy_dll_sts3, val_ddrc__phy_dll_sts3); +set_reset_data( ddrc__dll_lock_sts, val_ddrc__dll_lock_sts); +set_reset_data( ddrc__phy_ctrl_sts, val_ddrc__phy_ctrl_sts); +set_reset_data( ddrc__phy_ctrl_sts_reg2, val_ddrc__phy_ctrl_sts_reg2); +set_reset_data( ddrc__axi_id, val_ddrc__axi_id); +set_reset_data( ddrc__page_mask, val_ddrc__page_mask); +set_reset_data( ddrc__axi_priority_wr_port0, val_ddrc__axi_priority_wr_port0); +set_reset_data( ddrc__axi_priority_wr_port1, val_ddrc__axi_priority_wr_port1); +set_reset_data( ddrc__axi_priority_wr_port2, val_ddrc__axi_priority_wr_port2); +set_reset_data( ddrc__axi_priority_wr_port3, val_ddrc__axi_priority_wr_port3); +set_reset_data( ddrc__axi_priority_rd_port0, val_ddrc__axi_priority_rd_port0); +set_reset_data( ddrc__axi_priority_rd_port1, val_ddrc__axi_priority_rd_port1); +set_reset_data( ddrc__axi_priority_rd_port2, val_ddrc__axi_priority_rd_port2); +set_reset_data( ddrc__axi_priority_rd_port3, val_ddrc__axi_priority_rd_port3); +set_reset_data( ddrc__AHB_priority_cfg0, val_ddrc__AHB_priority_cfg0); +set_reset_data( ddrc__AHB_priority_cfg1, val_ddrc__AHB_priority_cfg1); +set_reset_data( ddrc__AHB_priority_cfg2, val_ddrc__AHB_priority_cfg2); +set_reset_data( ddrc__AHB_priority_cfg3, val_ddrc__AHB_priority_cfg3); +set_reset_data( ddrc__perf_mon0, val_ddrc__perf_mon0); +set_reset_data( ddrc__perf_mon1, val_ddrc__perf_mon1); +set_reset_data( ddrc__perf_mon2, val_ddrc__perf_mon2); +set_reset_data( ddrc__perf_mon3, val_ddrc__perf_mon3); +set_reset_data( ddrc__perf_mon20, val_ddrc__perf_mon20); +set_reset_data( ddrc__perf_mon21, val_ddrc__perf_mon21); +set_reset_data( ddrc__perf_mon22, val_ddrc__perf_mon22); +set_reset_data( ddrc__perf_mon23, val_ddrc__perf_mon23); +set_reset_data( ddrc__perf_mon30, val_ddrc__perf_mon30); +set_reset_data( ddrc__perf_mon31, val_ddrc__perf_mon31); +set_reset_data( ddrc__perf_mon32, val_ddrc__perf_mon32); +set_reset_data( ddrc__perf_mon33, val_ddrc__perf_mon33); +set_reset_data( ddrc__trusted_mem_cfg, val_ddrc__trusted_mem_cfg); +set_reset_data( ddrc__excl_access_cfg0, val_ddrc__excl_access_cfg0); +set_reset_data( ddrc__excl_access_cfg1, val_ddrc__excl_access_cfg1); +set_reset_data( ddrc__excl_access_cfg2, val_ddrc__excl_access_cfg2); +set_reset_data( ddrc__excl_access_cfg3, val_ddrc__excl_access_cfg3); +set_reset_data( ddrc__mode_reg_read, val_ddrc__mode_reg_read); +set_reset_data( ddrc__lpddr_ctrl0, val_ddrc__lpddr_ctrl0); +set_reset_data( ddrc__lpddr_ctrl1, val_ddrc__lpddr_ctrl1); +set_reset_data( ddrc__lpddr_ctrl2, val_ddrc__lpddr_ctrl2); +set_reset_data( ddrc__lpddr_ctrl3, val_ddrc__lpddr_ctrl3); +set_reset_data( ddrc__phy_wr_lvl_fsm, val_ddrc__phy_wr_lvl_fsm); +set_reset_data( ddrc__phy_rd_lvl_fsm, val_ddrc__phy_rd_lvl_fsm); +set_reset_data( ddrc__phy_gate_lvl_fsm, val_ddrc__phy_gate_lvl_fsm); + +// ************************************************************ +// Module debug_axim axim +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_axim__GLOBAL_CTRL, val_debug_axim__GLOBAL_CTRL); +set_reset_data( debug_axim__GLOBAL_STATUS, val_debug_axim__GLOBAL_STATUS); +set_reset_data( debug_axim__FILTER_CTRL, val_debug_axim__FILTER_CTRL); +set_reset_data( debug_axim__TRIGGER_CTRL, val_debug_axim__TRIGGER_CTRL); +set_reset_data( debug_axim__TRIGGER_STATUS, val_debug_axim__TRIGGER_STATUS); +set_reset_data( debug_axim__PACKET_CTRL, val_debug_axim__PACKET_CTRL); +set_reset_data( debug_axim__TOUT_CTRL, val_debug_axim__TOUT_CTRL); +set_reset_data( debug_axim__TOUT_THRESH, val_debug_axim__TOUT_THRESH); +set_reset_data( debug_axim__FIFO_CURRENT, val_debug_axim__FIFO_CURRENT); +set_reset_data( debug_axim__FIFO_HYSTER, val_debug_axim__FIFO_HYSTER); +set_reset_data( debug_axim__SYNC_CURRENT, val_debug_axim__SYNC_CURRENT); +set_reset_data( debug_axim__SYNC_RELOAD, val_debug_axim__SYNC_RELOAD); +set_reset_data( debug_axim__TSTMP_CURRENT, val_debug_axim__TSTMP_CURRENT); +set_reset_data( debug_axim__ADDR0_MASK, val_debug_axim__ADDR0_MASK); +set_reset_data( debug_axim__ADDR0_LOWER, val_debug_axim__ADDR0_LOWER); +set_reset_data( debug_axim__ADDR0_UPPER, val_debug_axim__ADDR0_UPPER); +set_reset_data( debug_axim__ADDR0_MISC, val_debug_axim__ADDR0_MISC); +set_reset_data( debug_axim__ADDR1_MASK, val_debug_axim__ADDR1_MASK); +set_reset_data( debug_axim__ADDR1_LOWER, val_debug_axim__ADDR1_LOWER); +set_reset_data( debug_axim__ADDR1_UPPER, val_debug_axim__ADDR1_UPPER); +set_reset_data( debug_axim__ADDR1_MISC, val_debug_axim__ADDR1_MISC); +set_reset_data( debug_axim__ADDR2_MASK, val_debug_axim__ADDR2_MASK); +set_reset_data( debug_axim__ADDR2_LOWER, val_debug_axim__ADDR2_LOWER); +set_reset_data( debug_axim__ADDR2_UPPER, val_debug_axim__ADDR2_UPPER); +set_reset_data( debug_axim__ADDR2_MISC, val_debug_axim__ADDR2_MISC); +set_reset_data( debug_axim__ADDR3_MASK, val_debug_axim__ADDR3_MASK); +set_reset_data( debug_axim__ADDR3_LOWER, val_debug_axim__ADDR3_LOWER); +set_reset_data( debug_axim__ADDR3_UPPER, val_debug_axim__ADDR3_UPPER); +set_reset_data( debug_axim__ADDR3_MISC, val_debug_axim__ADDR3_MISC); +set_reset_data( debug_axim__ID0_MASK, val_debug_axim__ID0_MASK); +set_reset_data( debug_axim__ID0_LOWER, val_debug_axim__ID0_LOWER); +set_reset_data( debug_axim__ID0_UPPER, val_debug_axim__ID0_UPPER); +set_reset_data( debug_axim__ID0_MISC, val_debug_axim__ID0_MISC); +set_reset_data( debug_axim__ID1_MASK, val_debug_axim__ID1_MASK); +set_reset_data( debug_axim__ID1_LOWER, val_debug_axim__ID1_LOWER); +set_reset_data( debug_axim__ID1_UPPER, val_debug_axim__ID1_UPPER); +set_reset_data( debug_axim__ID1_MISC, val_debug_axim__ID1_MISC); +set_reset_data( debug_axim__ID2_MASK, val_debug_axim__ID2_MASK); +set_reset_data( debug_axim__ID2_LOWER, val_debug_axim__ID2_LOWER); +set_reset_data( debug_axim__ID2_UPPER, val_debug_axim__ID2_UPPER); +set_reset_data( debug_axim__ID2_MISC, val_debug_axim__ID2_MISC); +set_reset_data( debug_axim__ID3_MASK, val_debug_axim__ID3_MASK); +set_reset_data( debug_axim__ID3_LOWER, val_debug_axim__ID3_LOWER); +set_reset_data( debug_axim__ID3_UPPER, val_debug_axim__ID3_UPPER); +set_reset_data( debug_axim__ID3_MISC, val_debug_axim__ID3_MISC); +set_reset_data( debug_axim__AXI_SEL, val_debug_axim__AXI_SEL); +set_reset_data( debug_axim__IT_TRIGOUT, val_debug_axim__IT_TRIGOUT); +set_reset_data( debug_axim__IT_TRIGOUTACK, val_debug_axim__IT_TRIGOUTACK); +set_reset_data( debug_axim__IT_TRIGIN, val_debug_axim__IT_TRIGIN); +set_reset_data( debug_axim__IT_TRIGINACK, val_debug_axim__IT_TRIGINACK); +set_reset_data( debug_axim__IT_ATBDATA, val_debug_axim__IT_ATBDATA); +set_reset_data( debug_axim__IT_ATBSTATUS, val_debug_axim__IT_ATBSTATUS); +set_reset_data( debug_axim__IT_ATBCTRL1, val_debug_axim__IT_ATBCTRL1); +set_reset_data( debug_axim__IT_ATBCTRL0, val_debug_axim__IT_ATBCTRL0); +set_reset_data( debug_axim__IT_CTRL, val_debug_axim__IT_CTRL); +set_reset_data( debug_axim__CLAIM_SET, val_debug_axim__CLAIM_SET); +set_reset_data( debug_axim__CLAIM_CLEAR, val_debug_axim__CLAIM_CLEAR); +set_reset_data( debug_axim__LOCK_ACCESS, val_debug_axim__LOCK_ACCESS); +set_reset_data( debug_axim__LOCK_STATUS, val_debug_axim__LOCK_STATUS); +set_reset_data( debug_axim__AUTH_STATUS, val_debug_axim__AUTH_STATUS); +set_reset_data( debug_axim__DEV_ID, val_debug_axim__DEV_ID); +set_reset_data( debug_axim__DEV_TYPE, val_debug_axim__DEV_TYPE); +set_reset_data( debug_axim__PERIPHID4, val_debug_axim__PERIPHID4); +set_reset_data( debug_axim__PERIPHID5, val_debug_axim__PERIPHID5); +set_reset_data( debug_axim__PERIPHID6, val_debug_axim__PERIPHID6); +set_reset_data( debug_axim__PERIPHID7, val_debug_axim__PERIPHID7); +set_reset_data( debug_axim__PERIPHID0, val_debug_axim__PERIPHID0); +set_reset_data( debug_axim__PERIPHID1, val_debug_axim__PERIPHID1); +set_reset_data( debug_axim__PERIPHID2, val_debug_axim__PERIPHID2); +set_reset_data( debug_axim__PERIPHID3, val_debug_axim__PERIPHID3); +set_reset_data( debug_axim__COMPID0, val_debug_axim__COMPID0); +set_reset_data( debug_axim__COMPID1, val_debug_axim__COMPID1); +set_reset_data( debug_axim__COMPID2, val_debug_axim__COMPID2); +set_reset_data( debug_axim__COMPID3, val_debug_axim__COMPID3); + +// ************************************************************ +// Module debug_cpu_cti0 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_cti0__CTICONTROL, val_debug_cpu_cti0__CTICONTROL); +set_reset_data( debug_cpu_cti0__CTIINTACK, val_debug_cpu_cti0__CTIINTACK); +set_reset_data( debug_cpu_cti0__CTIAPPSET, val_debug_cpu_cti0__CTIAPPSET); +set_reset_data( debug_cpu_cti0__CTIAPPCLEAR, val_debug_cpu_cti0__CTIAPPCLEAR); +set_reset_data( debug_cpu_cti0__CTIAPPPULSE, val_debug_cpu_cti0__CTIAPPPULSE); +set_reset_data( debug_cpu_cti0__CTIINEN0, val_debug_cpu_cti0__CTIINEN0); +set_reset_data( debug_cpu_cti0__CTIINEN1, val_debug_cpu_cti0__CTIINEN1); +set_reset_data( debug_cpu_cti0__CTIINEN2, val_debug_cpu_cti0__CTIINEN2); +set_reset_data( debug_cpu_cti0__CTIINEN3, val_debug_cpu_cti0__CTIINEN3); +set_reset_data( debug_cpu_cti0__CTIINEN4, val_debug_cpu_cti0__CTIINEN4); +set_reset_data( debug_cpu_cti0__CTIINEN5, val_debug_cpu_cti0__CTIINEN5); +set_reset_data( debug_cpu_cti0__CTIINEN6, val_debug_cpu_cti0__CTIINEN6); +set_reset_data( debug_cpu_cti0__CTIINEN7, val_debug_cpu_cti0__CTIINEN7); +set_reset_data( debug_cpu_cti0__CTIOUTEN0, val_debug_cpu_cti0__CTIOUTEN0); +set_reset_data( debug_cpu_cti0__CTIOUTEN1, val_debug_cpu_cti0__CTIOUTEN1); +set_reset_data( debug_cpu_cti0__CTIOUTEN2, val_debug_cpu_cti0__CTIOUTEN2); +set_reset_data( debug_cpu_cti0__CTIOUTEN3, val_debug_cpu_cti0__CTIOUTEN3); +set_reset_data( debug_cpu_cti0__CTIOUTEN4, val_debug_cpu_cti0__CTIOUTEN4); +set_reset_data( debug_cpu_cti0__CTIOUTEN5, val_debug_cpu_cti0__CTIOUTEN5); +set_reset_data( debug_cpu_cti0__CTIOUTEN6, val_debug_cpu_cti0__CTIOUTEN6); +set_reset_data( debug_cpu_cti0__CTIOUTEN7, val_debug_cpu_cti0__CTIOUTEN7); +set_reset_data( debug_cpu_cti0__CTITRIGINSTATUS, val_debug_cpu_cti0__CTITRIGINSTATUS); +set_reset_data( debug_cpu_cti0__CTITRIGOUTSTATUS, val_debug_cpu_cti0__CTITRIGOUTSTATUS); +set_reset_data( debug_cpu_cti0__CTICHINSTATUS, val_debug_cpu_cti0__CTICHINSTATUS); +set_reset_data( debug_cpu_cti0__CTICHOUTSTATUS, val_debug_cpu_cti0__CTICHOUTSTATUS); +set_reset_data( debug_cpu_cti0__CTIGATE, val_debug_cpu_cti0__CTIGATE); +set_reset_data( debug_cpu_cti0__ASICCTL, val_debug_cpu_cti0__ASICCTL); +set_reset_data( debug_cpu_cti0__ITCHINACK, val_debug_cpu_cti0__ITCHINACK); +set_reset_data( debug_cpu_cti0__ITTRIGINACK, val_debug_cpu_cti0__ITTRIGINACK); +set_reset_data( debug_cpu_cti0__ITCHOUT, val_debug_cpu_cti0__ITCHOUT); +set_reset_data( debug_cpu_cti0__ITTRIGOUT, val_debug_cpu_cti0__ITTRIGOUT); +set_reset_data( debug_cpu_cti0__ITCHOUTACK, val_debug_cpu_cti0__ITCHOUTACK); +set_reset_data( debug_cpu_cti0__ITTRIGOUTACK, val_debug_cpu_cti0__ITTRIGOUTACK); +set_reset_data( debug_cpu_cti0__ITCHIN, val_debug_cpu_cti0__ITCHIN); +set_reset_data( debug_cpu_cti0__ITTRIGIN, val_debug_cpu_cti0__ITTRIGIN); +set_reset_data( debug_cpu_cti0__ITCTRL, val_debug_cpu_cti0__ITCTRL); +set_reset_data( debug_cpu_cti0__CTSR, val_debug_cpu_cti0__CTSR); +set_reset_data( debug_cpu_cti0__CTCR, val_debug_cpu_cti0__CTCR); +set_reset_data( debug_cpu_cti0__LAR, val_debug_cpu_cti0__LAR); +set_reset_data( debug_cpu_cti0__LSR, val_debug_cpu_cti0__LSR); +set_reset_data( debug_cpu_cti0__ASR, val_debug_cpu_cti0__ASR); +set_reset_data( debug_cpu_cti0__DEVID, val_debug_cpu_cti0__DEVID); +set_reset_data( debug_cpu_cti0__DTIR, val_debug_cpu_cti0__DTIR); +set_reset_data( debug_cpu_cti0__PERIPHID4, val_debug_cpu_cti0__PERIPHID4); +set_reset_data( debug_cpu_cti0__PERIPHID5, val_debug_cpu_cti0__PERIPHID5); +set_reset_data( debug_cpu_cti0__PERIPHID6, val_debug_cpu_cti0__PERIPHID6); +set_reset_data( debug_cpu_cti0__PERIPHID7, val_debug_cpu_cti0__PERIPHID7); +set_reset_data( debug_cpu_cti0__PERIPHID0, val_debug_cpu_cti0__PERIPHID0); +set_reset_data( debug_cpu_cti0__PERIPHID1, val_debug_cpu_cti0__PERIPHID1); +set_reset_data( debug_cpu_cti0__PERIPHID2, val_debug_cpu_cti0__PERIPHID2); +set_reset_data( debug_cpu_cti0__PERIPHID3, val_debug_cpu_cti0__PERIPHID3); +set_reset_data( debug_cpu_cti0__COMPID0, val_debug_cpu_cti0__COMPID0); +set_reset_data( debug_cpu_cti0__COMPID1, val_debug_cpu_cti0__COMPID1); +set_reset_data( debug_cpu_cti0__COMPID2, val_debug_cpu_cti0__COMPID2); +set_reset_data( debug_cpu_cti0__COMPID3, val_debug_cpu_cti0__COMPID3); + +// ************************************************************ +// Module debug_cpu_cti1 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_cti1__CTICONTROL, val_debug_cpu_cti1__CTICONTROL); +set_reset_data( debug_cpu_cti1__CTIINTACK, val_debug_cpu_cti1__CTIINTACK); +set_reset_data( debug_cpu_cti1__CTIAPPSET, val_debug_cpu_cti1__CTIAPPSET); +set_reset_data( debug_cpu_cti1__CTIAPPCLEAR, val_debug_cpu_cti1__CTIAPPCLEAR); +set_reset_data( debug_cpu_cti1__CTIAPPPULSE, val_debug_cpu_cti1__CTIAPPPULSE); +set_reset_data( debug_cpu_cti1__CTIINEN0, val_debug_cpu_cti1__CTIINEN0); +set_reset_data( debug_cpu_cti1__CTIINEN1, val_debug_cpu_cti1__CTIINEN1); +set_reset_data( debug_cpu_cti1__CTIINEN2, val_debug_cpu_cti1__CTIINEN2); +set_reset_data( debug_cpu_cti1__CTIINEN3, val_debug_cpu_cti1__CTIINEN3); +set_reset_data( debug_cpu_cti1__CTIINEN4, val_debug_cpu_cti1__CTIINEN4); +set_reset_data( debug_cpu_cti1__CTIINEN5, val_debug_cpu_cti1__CTIINEN5); +set_reset_data( debug_cpu_cti1__CTIINEN6, val_debug_cpu_cti1__CTIINEN6); +set_reset_data( debug_cpu_cti1__CTIINEN7, val_debug_cpu_cti1__CTIINEN7); +set_reset_data( debug_cpu_cti1__CTIOUTEN0, val_debug_cpu_cti1__CTIOUTEN0); +set_reset_data( debug_cpu_cti1__CTIOUTEN1, val_debug_cpu_cti1__CTIOUTEN1); +set_reset_data( debug_cpu_cti1__CTIOUTEN2, val_debug_cpu_cti1__CTIOUTEN2); +set_reset_data( debug_cpu_cti1__CTIOUTEN3, val_debug_cpu_cti1__CTIOUTEN3); +set_reset_data( debug_cpu_cti1__CTIOUTEN4, val_debug_cpu_cti1__CTIOUTEN4); +set_reset_data( debug_cpu_cti1__CTIOUTEN5, val_debug_cpu_cti1__CTIOUTEN5); +set_reset_data( debug_cpu_cti1__CTIOUTEN6, val_debug_cpu_cti1__CTIOUTEN6); +set_reset_data( debug_cpu_cti1__CTIOUTEN7, val_debug_cpu_cti1__CTIOUTEN7); +set_reset_data( debug_cpu_cti1__CTITRIGINSTATUS, val_debug_cpu_cti1__CTITRIGINSTATUS); +set_reset_data( debug_cpu_cti1__CTITRIGOUTSTATUS, val_debug_cpu_cti1__CTITRIGOUTSTATUS); +set_reset_data( debug_cpu_cti1__CTICHINSTATUS, val_debug_cpu_cti1__CTICHINSTATUS); +set_reset_data( debug_cpu_cti1__CTICHOUTSTATUS, val_debug_cpu_cti1__CTICHOUTSTATUS); +set_reset_data( debug_cpu_cti1__CTIGATE, val_debug_cpu_cti1__CTIGATE); +set_reset_data( debug_cpu_cti1__ASICCTL, val_debug_cpu_cti1__ASICCTL); +set_reset_data( debug_cpu_cti1__ITCHINACK, val_debug_cpu_cti1__ITCHINACK); +set_reset_data( debug_cpu_cti1__ITTRIGINACK, val_debug_cpu_cti1__ITTRIGINACK); +set_reset_data( debug_cpu_cti1__ITCHOUT, val_debug_cpu_cti1__ITCHOUT); +set_reset_data( debug_cpu_cti1__ITTRIGOUT, val_debug_cpu_cti1__ITTRIGOUT); +set_reset_data( debug_cpu_cti1__ITCHOUTACK, val_debug_cpu_cti1__ITCHOUTACK); +set_reset_data( debug_cpu_cti1__ITTRIGOUTACK, val_debug_cpu_cti1__ITTRIGOUTACK); +set_reset_data( debug_cpu_cti1__ITCHIN, val_debug_cpu_cti1__ITCHIN); +set_reset_data( debug_cpu_cti1__ITTRIGIN, val_debug_cpu_cti1__ITTRIGIN); +set_reset_data( debug_cpu_cti1__ITCTRL, val_debug_cpu_cti1__ITCTRL); +set_reset_data( debug_cpu_cti1__CTSR, val_debug_cpu_cti1__CTSR); +set_reset_data( debug_cpu_cti1__CTCR, val_debug_cpu_cti1__CTCR); +set_reset_data( debug_cpu_cti1__LAR, val_debug_cpu_cti1__LAR); +set_reset_data( debug_cpu_cti1__LSR, val_debug_cpu_cti1__LSR); +set_reset_data( debug_cpu_cti1__ASR, val_debug_cpu_cti1__ASR); +set_reset_data( debug_cpu_cti1__DEVID, val_debug_cpu_cti1__DEVID); +set_reset_data( debug_cpu_cti1__DTIR, val_debug_cpu_cti1__DTIR); +set_reset_data( debug_cpu_cti1__PERIPHID4, val_debug_cpu_cti1__PERIPHID4); +set_reset_data( debug_cpu_cti1__PERIPHID5, val_debug_cpu_cti1__PERIPHID5); +set_reset_data( debug_cpu_cti1__PERIPHID6, val_debug_cpu_cti1__PERIPHID6); +set_reset_data( debug_cpu_cti1__PERIPHID7, val_debug_cpu_cti1__PERIPHID7); +set_reset_data( debug_cpu_cti1__PERIPHID0, val_debug_cpu_cti1__PERIPHID0); +set_reset_data( debug_cpu_cti1__PERIPHID1, val_debug_cpu_cti1__PERIPHID1); +set_reset_data( debug_cpu_cti1__PERIPHID2, val_debug_cpu_cti1__PERIPHID2); +set_reset_data( debug_cpu_cti1__PERIPHID3, val_debug_cpu_cti1__PERIPHID3); +set_reset_data( debug_cpu_cti1__COMPID0, val_debug_cpu_cti1__COMPID0); +set_reset_data( debug_cpu_cti1__COMPID1, val_debug_cpu_cti1__COMPID1); +set_reset_data( debug_cpu_cti1__COMPID2, val_debug_cpu_cti1__COMPID2); +set_reset_data( debug_cpu_cti1__COMPID3, val_debug_cpu_cti1__COMPID3); + +// ************************************************************ +// Module debug_cpu_pmu0 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_pmu0__PMXEVCNTR0, val_debug_cpu_pmu0__PMXEVCNTR0); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR1, val_debug_cpu_pmu0__PMXEVCNTR1); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR2, val_debug_cpu_pmu0__PMXEVCNTR2); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR3, val_debug_cpu_pmu0__PMXEVCNTR3); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR4, val_debug_cpu_pmu0__PMXEVCNTR4); +set_reset_data( debug_cpu_pmu0__PMXEVCNTR5, val_debug_cpu_pmu0__PMXEVCNTR5); +set_reset_data( debug_cpu_pmu0__PMCCNTR, val_debug_cpu_pmu0__PMCCNTR); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER0, val_debug_cpu_pmu0__PMXEVTYPER0); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER1, val_debug_cpu_pmu0__PMXEVTYPER1); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER2, val_debug_cpu_pmu0__PMXEVTYPER2); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER3, val_debug_cpu_pmu0__PMXEVTYPER3); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER4, val_debug_cpu_pmu0__PMXEVTYPER4); +set_reset_data( debug_cpu_pmu0__PMXEVTYPER5, val_debug_cpu_pmu0__PMXEVTYPER5); +set_reset_data( debug_cpu_pmu0__PMCNTENSET, val_debug_cpu_pmu0__PMCNTENSET); +set_reset_data( debug_cpu_pmu0__PMCNTENCLR, val_debug_cpu_pmu0__PMCNTENCLR); +set_reset_data( debug_cpu_pmu0__PMINTENSET, val_debug_cpu_pmu0__PMINTENSET); +set_reset_data( debug_cpu_pmu0__PMINTENCLR, val_debug_cpu_pmu0__PMINTENCLR); +set_reset_data( debug_cpu_pmu0__PMOVSR, val_debug_cpu_pmu0__PMOVSR); +set_reset_data( debug_cpu_pmu0__PMSWINC, val_debug_cpu_pmu0__PMSWINC); +set_reset_data( debug_cpu_pmu0__PMCR, val_debug_cpu_pmu0__PMCR); +set_reset_data( debug_cpu_pmu0__PMUSERENR, val_debug_cpu_pmu0__PMUSERENR); + +// ************************************************************ +// Module debug_cpu_pmu1 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_pmu1__PMXEVCNTR0, val_debug_cpu_pmu1__PMXEVCNTR0); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR1, val_debug_cpu_pmu1__PMXEVCNTR1); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR2, val_debug_cpu_pmu1__PMXEVCNTR2); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR3, val_debug_cpu_pmu1__PMXEVCNTR3); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR4, val_debug_cpu_pmu1__PMXEVCNTR4); +set_reset_data( debug_cpu_pmu1__PMXEVCNTR5, val_debug_cpu_pmu1__PMXEVCNTR5); +set_reset_data( debug_cpu_pmu1__PMCCNTR, val_debug_cpu_pmu1__PMCCNTR); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER0, val_debug_cpu_pmu1__PMXEVTYPER0); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER1, val_debug_cpu_pmu1__PMXEVTYPER1); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER2, val_debug_cpu_pmu1__PMXEVTYPER2); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER3, val_debug_cpu_pmu1__PMXEVTYPER3); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER4, val_debug_cpu_pmu1__PMXEVTYPER4); +set_reset_data( debug_cpu_pmu1__PMXEVTYPER5, val_debug_cpu_pmu1__PMXEVTYPER5); +set_reset_data( debug_cpu_pmu1__PMCNTENSET, val_debug_cpu_pmu1__PMCNTENSET); +set_reset_data( debug_cpu_pmu1__PMCNTENCLR, val_debug_cpu_pmu1__PMCNTENCLR); +set_reset_data( debug_cpu_pmu1__PMINTENSET, val_debug_cpu_pmu1__PMINTENSET); +set_reset_data( debug_cpu_pmu1__PMINTENCLR, val_debug_cpu_pmu1__PMINTENCLR); +set_reset_data( debug_cpu_pmu1__PMOVSR, val_debug_cpu_pmu1__PMOVSR); +set_reset_data( debug_cpu_pmu1__PMSWINC, val_debug_cpu_pmu1__PMSWINC); +set_reset_data( debug_cpu_pmu1__PMCR, val_debug_cpu_pmu1__PMCR); +set_reset_data( debug_cpu_pmu1__PMUSERENR, val_debug_cpu_pmu1__PMUSERENR); + +// ************************************************************ +// Module debug_cpu_ptm0 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_ptm0__ETMCR, val_debug_cpu_ptm0__ETMCR); +set_reset_data( debug_cpu_ptm0__ETMCCR, val_debug_cpu_ptm0__ETMCCR); +set_reset_data( debug_cpu_ptm0__ETMTRIGGER, val_debug_cpu_ptm0__ETMTRIGGER); +set_reset_data( debug_cpu_ptm0__ETMSR, val_debug_cpu_ptm0__ETMSR); +set_reset_data( debug_cpu_ptm0__ETMSCR, val_debug_cpu_ptm0__ETMSCR); +set_reset_data( debug_cpu_ptm0__ETMTSSCR, val_debug_cpu_ptm0__ETMTSSCR); +set_reset_data( debug_cpu_ptm0__ETMTECR1, val_debug_cpu_ptm0__ETMTECR1); +set_reset_data( debug_cpu_ptm0__ETMACVR1, val_debug_cpu_ptm0__ETMACVR1); +set_reset_data( debug_cpu_ptm0__ETMACVR2, val_debug_cpu_ptm0__ETMACVR2); +set_reset_data( debug_cpu_ptm0__ETMACVR3, val_debug_cpu_ptm0__ETMACVR3); +set_reset_data( debug_cpu_ptm0__ETMACVR4, val_debug_cpu_ptm0__ETMACVR4); +set_reset_data( debug_cpu_ptm0__ETMACVR5, val_debug_cpu_ptm0__ETMACVR5); +set_reset_data( debug_cpu_ptm0__ETMACVR6, val_debug_cpu_ptm0__ETMACVR6); +set_reset_data( debug_cpu_ptm0__ETMACVR7, val_debug_cpu_ptm0__ETMACVR7); +set_reset_data( debug_cpu_ptm0__ETMACVR8, val_debug_cpu_ptm0__ETMACVR8); +set_reset_data( debug_cpu_ptm0__ETMACTR1, val_debug_cpu_ptm0__ETMACTR1); +set_reset_data( debug_cpu_ptm0__ETMACTR2, val_debug_cpu_ptm0__ETMACTR2); +set_reset_data( debug_cpu_ptm0__ETMACTR3, val_debug_cpu_ptm0__ETMACTR3); +set_reset_data( debug_cpu_ptm0__ETMACTR4, val_debug_cpu_ptm0__ETMACTR4); +set_reset_data( debug_cpu_ptm0__ETMACTR5, val_debug_cpu_ptm0__ETMACTR5); +set_reset_data( debug_cpu_ptm0__ETMACTR6, val_debug_cpu_ptm0__ETMACTR6); +set_reset_data( debug_cpu_ptm0__ETMACTR7, val_debug_cpu_ptm0__ETMACTR7); +set_reset_data( debug_cpu_ptm0__ETMACTR8, val_debug_cpu_ptm0__ETMACTR8); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR1, val_debug_cpu_ptm0__ETMCNTRLDVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDVR2, val_debug_cpu_ptm0__ETMCNTRLDVR2); +set_reset_data( debug_cpu_ptm0__ETMCNTENR1, val_debug_cpu_ptm0__ETMCNTENR1); +set_reset_data( debug_cpu_ptm0__ETMCNTENR2, val_debug_cpu_ptm0__ETMCNTENR2); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR1, val_debug_cpu_ptm0__ETMCNTRLDEVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTRLDEVR2, val_debug_cpu_ptm0__ETMCNTRLDEVR2); +set_reset_data( debug_cpu_ptm0__ETMCNTVR1, val_debug_cpu_ptm0__ETMCNTVR1); +set_reset_data( debug_cpu_ptm0__ETMCNTVR2, val_debug_cpu_ptm0__ETMCNTVR2); +set_reset_data( debug_cpu_ptm0__ETMSQ12EVR, val_debug_cpu_ptm0__ETMSQ12EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ21EVR, val_debug_cpu_ptm0__ETMSQ21EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ23EVR, val_debug_cpu_ptm0__ETMSQ23EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ31EVR, val_debug_cpu_ptm0__ETMSQ31EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ32EVR, val_debug_cpu_ptm0__ETMSQ32EVR); +set_reset_data( debug_cpu_ptm0__ETMSQ13EVR, val_debug_cpu_ptm0__ETMSQ13EVR); +set_reset_data( debug_cpu_ptm0__ETMSQR, val_debug_cpu_ptm0__ETMSQR); +set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR1, val_debug_cpu_ptm0__ETMEXTOUTEVR1); +set_reset_data( debug_cpu_ptm0__ETMEXTOUTEVR2, val_debug_cpu_ptm0__ETMEXTOUTEVR2); +set_reset_data( debug_cpu_ptm0__ETMCIDCVR1, val_debug_cpu_ptm0__ETMCIDCVR1); +set_reset_data( debug_cpu_ptm0__ETMCIDCMR, val_debug_cpu_ptm0__ETMCIDCMR); +set_reset_data( debug_cpu_ptm0__ETMSYNCFR, val_debug_cpu_ptm0__ETMSYNCFR); +set_reset_data( debug_cpu_ptm0__ETMIDR, val_debug_cpu_ptm0__ETMIDR); +set_reset_data( debug_cpu_ptm0__ETMCCER, val_debug_cpu_ptm0__ETMCCER); +set_reset_data( debug_cpu_ptm0__ETMEXTINSELR, val_debug_cpu_ptm0__ETMEXTINSELR); +set_reset_data( debug_cpu_ptm0__ETMAUXCR, val_debug_cpu_ptm0__ETMAUXCR); +set_reset_data( debug_cpu_ptm0__ETMTRACEIDR, val_debug_cpu_ptm0__ETMTRACEIDR); +set_reset_data( debug_cpu_ptm0__OSLSR, val_debug_cpu_ptm0__OSLSR); +set_reset_data( debug_cpu_ptm0__ETMPDSR, val_debug_cpu_ptm0__ETMPDSR); +set_reset_data( debug_cpu_ptm0__ITMISCOUT, val_debug_cpu_ptm0__ITMISCOUT); +set_reset_data( debug_cpu_ptm0__ITMISCIN, val_debug_cpu_ptm0__ITMISCIN); +set_reset_data( debug_cpu_ptm0__ITTRIGGER, val_debug_cpu_ptm0__ITTRIGGER); +set_reset_data( debug_cpu_ptm0__ITATBDATA0, val_debug_cpu_ptm0__ITATBDATA0); +set_reset_data( debug_cpu_ptm0__ITATBCTR2, val_debug_cpu_ptm0__ITATBCTR2); +set_reset_data( debug_cpu_ptm0__ITATBID, val_debug_cpu_ptm0__ITATBID); +set_reset_data( debug_cpu_ptm0__ITATBCTR0, val_debug_cpu_ptm0__ITATBCTR0); +set_reset_data( debug_cpu_ptm0__ETMITCTRL, val_debug_cpu_ptm0__ETMITCTRL); +set_reset_data( debug_cpu_ptm0__CTSR, val_debug_cpu_ptm0__CTSR); +set_reset_data( debug_cpu_ptm0__CTCR, val_debug_cpu_ptm0__CTCR); +set_reset_data( debug_cpu_ptm0__LAR, val_debug_cpu_ptm0__LAR); +set_reset_data( debug_cpu_ptm0__LSR, val_debug_cpu_ptm0__LSR); +set_reset_data( debug_cpu_ptm0__ASR, val_debug_cpu_ptm0__ASR); +set_reset_data( debug_cpu_ptm0__DEVID, val_debug_cpu_ptm0__DEVID); +set_reset_data( debug_cpu_ptm0__DTIR, val_debug_cpu_ptm0__DTIR); +set_reset_data( debug_cpu_ptm0__PERIPHID4, val_debug_cpu_ptm0__PERIPHID4); +set_reset_data( debug_cpu_ptm0__PERIPHID5, val_debug_cpu_ptm0__PERIPHID5); +set_reset_data( debug_cpu_ptm0__PERIPHID6, val_debug_cpu_ptm0__PERIPHID6); +set_reset_data( debug_cpu_ptm0__PERIPHID7, val_debug_cpu_ptm0__PERIPHID7); +set_reset_data( debug_cpu_ptm0__PERIPHID0, val_debug_cpu_ptm0__PERIPHID0); +set_reset_data( debug_cpu_ptm0__PERIPHID1, val_debug_cpu_ptm0__PERIPHID1); +set_reset_data( debug_cpu_ptm0__PERIPHID2, val_debug_cpu_ptm0__PERIPHID2); +set_reset_data( debug_cpu_ptm0__PERIPHID3, val_debug_cpu_ptm0__PERIPHID3); +set_reset_data( debug_cpu_ptm0__COMPID0, val_debug_cpu_ptm0__COMPID0); +set_reset_data( debug_cpu_ptm0__COMPID1, val_debug_cpu_ptm0__COMPID1); +set_reset_data( debug_cpu_ptm0__COMPID2, val_debug_cpu_ptm0__COMPID2); +set_reset_data( debug_cpu_ptm0__COMPID3, val_debug_cpu_ptm0__COMPID3); + +// ************************************************************ +// Module debug_cpu_ptm1 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cpu_ptm1__ETMCR, val_debug_cpu_ptm1__ETMCR); +set_reset_data( debug_cpu_ptm1__ETMCCR, val_debug_cpu_ptm1__ETMCCR); +set_reset_data( debug_cpu_ptm1__ETMTRIGGER, val_debug_cpu_ptm1__ETMTRIGGER); +set_reset_data( debug_cpu_ptm1__ETMSR, val_debug_cpu_ptm1__ETMSR); +set_reset_data( debug_cpu_ptm1__ETMSCR, val_debug_cpu_ptm1__ETMSCR); +set_reset_data( debug_cpu_ptm1__ETMTSSCR, val_debug_cpu_ptm1__ETMTSSCR); +set_reset_data( debug_cpu_ptm1__ETMTECR1, val_debug_cpu_ptm1__ETMTECR1); +set_reset_data( debug_cpu_ptm1__ETMACVR1, val_debug_cpu_ptm1__ETMACVR1); +set_reset_data( debug_cpu_ptm1__ETMACVR2, val_debug_cpu_ptm1__ETMACVR2); +set_reset_data( debug_cpu_ptm1__ETMACVR3, val_debug_cpu_ptm1__ETMACVR3); +set_reset_data( debug_cpu_ptm1__ETMACVR4, val_debug_cpu_ptm1__ETMACVR4); +set_reset_data( debug_cpu_ptm1__ETMACVR5, val_debug_cpu_ptm1__ETMACVR5); +set_reset_data( debug_cpu_ptm1__ETMACVR6, val_debug_cpu_ptm1__ETMACVR6); +set_reset_data( debug_cpu_ptm1__ETMACVR7, val_debug_cpu_ptm1__ETMACVR7); +set_reset_data( debug_cpu_ptm1__ETMACVR8, val_debug_cpu_ptm1__ETMACVR8); +set_reset_data( debug_cpu_ptm1__ETMACTR1, val_debug_cpu_ptm1__ETMACTR1); +set_reset_data( debug_cpu_ptm1__ETMACTR2, val_debug_cpu_ptm1__ETMACTR2); +set_reset_data( debug_cpu_ptm1__ETMACTR3, val_debug_cpu_ptm1__ETMACTR3); +set_reset_data( debug_cpu_ptm1__ETMACTR4, val_debug_cpu_ptm1__ETMACTR4); +set_reset_data( debug_cpu_ptm1__ETMACTR5, val_debug_cpu_ptm1__ETMACTR5); +set_reset_data( debug_cpu_ptm1__ETMACTR6, val_debug_cpu_ptm1__ETMACTR6); +set_reset_data( debug_cpu_ptm1__ETMACTR7, val_debug_cpu_ptm1__ETMACTR7); +set_reset_data( debug_cpu_ptm1__ETMACTR8, val_debug_cpu_ptm1__ETMACTR8); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR1, val_debug_cpu_ptm1__ETMCNTRLDVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDVR2, val_debug_cpu_ptm1__ETMCNTRLDVR2); +set_reset_data( debug_cpu_ptm1__ETMCNTENR1, val_debug_cpu_ptm1__ETMCNTENR1); +set_reset_data( debug_cpu_ptm1__ETMCNTENR2, val_debug_cpu_ptm1__ETMCNTENR2); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR1, val_debug_cpu_ptm1__ETMCNTRLDEVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTRLDEVR2, val_debug_cpu_ptm1__ETMCNTRLDEVR2); +set_reset_data( debug_cpu_ptm1__ETMCNTVR1, val_debug_cpu_ptm1__ETMCNTVR1); +set_reset_data( debug_cpu_ptm1__ETMCNTVR2, val_debug_cpu_ptm1__ETMCNTVR2); +set_reset_data( debug_cpu_ptm1__ETMSQ12EVR, val_debug_cpu_ptm1__ETMSQ12EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ21EVR, val_debug_cpu_ptm1__ETMSQ21EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ23EVR, val_debug_cpu_ptm1__ETMSQ23EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ31EVR, val_debug_cpu_ptm1__ETMSQ31EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ32EVR, val_debug_cpu_ptm1__ETMSQ32EVR); +set_reset_data( debug_cpu_ptm1__ETMSQ13EVR, val_debug_cpu_ptm1__ETMSQ13EVR); +set_reset_data( debug_cpu_ptm1__ETMSQR, val_debug_cpu_ptm1__ETMSQR); +set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR1, val_debug_cpu_ptm1__ETMEXTOUTEVR1); +set_reset_data( debug_cpu_ptm1__ETMEXTOUTEVR2, val_debug_cpu_ptm1__ETMEXTOUTEVR2); +set_reset_data( debug_cpu_ptm1__ETMCIDCVR1, val_debug_cpu_ptm1__ETMCIDCVR1); +set_reset_data( debug_cpu_ptm1__ETMCIDCMR, val_debug_cpu_ptm1__ETMCIDCMR); +set_reset_data( debug_cpu_ptm1__ETMSYNCFR, val_debug_cpu_ptm1__ETMSYNCFR); +set_reset_data( debug_cpu_ptm1__ETMIDR, val_debug_cpu_ptm1__ETMIDR); +set_reset_data( debug_cpu_ptm1__ETMCCER, val_debug_cpu_ptm1__ETMCCER); +set_reset_data( debug_cpu_ptm1__ETMEXTINSELR, val_debug_cpu_ptm1__ETMEXTINSELR); +set_reset_data( debug_cpu_ptm1__ETMAUXCR, val_debug_cpu_ptm1__ETMAUXCR); +set_reset_data( debug_cpu_ptm1__ETMTRACEIDR, val_debug_cpu_ptm1__ETMTRACEIDR); +set_reset_data( debug_cpu_ptm1__OSLSR, val_debug_cpu_ptm1__OSLSR); +set_reset_data( debug_cpu_ptm1__ETMPDSR, val_debug_cpu_ptm1__ETMPDSR); +set_reset_data( debug_cpu_ptm1__ITMISCOUT, val_debug_cpu_ptm1__ITMISCOUT); +set_reset_data( debug_cpu_ptm1__ITMISCIN, val_debug_cpu_ptm1__ITMISCIN); +set_reset_data( debug_cpu_ptm1__ITTRIGGER, val_debug_cpu_ptm1__ITTRIGGER); +set_reset_data( debug_cpu_ptm1__ITATBDATA0, val_debug_cpu_ptm1__ITATBDATA0); +set_reset_data( debug_cpu_ptm1__ITATBCTR2, val_debug_cpu_ptm1__ITATBCTR2); +set_reset_data( debug_cpu_ptm1__ITATBID, val_debug_cpu_ptm1__ITATBID); +set_reset_data( debug_cpu_ptm1__ITATBCTR0, val_debug_cpu_ptm1__ITATBCTR0); +set_reset_data( debug_cpu_ptm1__ETMITCTRL, val_debug_cpu_ptm1__ETMITCTRL); +set_reset_data( debug_cpu_ptm1__CTSR, val_debug_cpu_ptm1__CTSR); +set_reset_data( debug_cpu_ptm1__CTCR, val_debug_cpu_ptm1__CTCR); +set_reset_data( debug_cpu_ptm1__LAR, val_debug_cpu_ptm1__LAR); +set_reset_data( debug_cpu_ptm1__LSR, val_debug_cpu_ptm1__LSR); +set_reset_data( debug_cpu_ptm1__ASR, val_debug_cpu_ptm1__ASR); +set_reset_data( debug_cpu_ptm1__DEVID, val_debug_cpu_ptm1__DEVID); +set_reset_data( debug_cpu_ptm1__DTIR, val_debug_cpu_ptm1__DTIR); +set_reset_data( debug_cpu_ptm1__PERIPHID4, val_debug_cpu_ptm1__PERIPHID4); +set_reset_data( debug_cpu_ptm1__PERIPHID5, val_debug_cpu_ptm1__PERIPHID5); +set_reset_data( debug_cpu_ptm1__PERIPHID6, val_debug_cpu_ptm1__PERIPHID6); +set_reset_data( debug_cpu_ptm1__PERIPHID7, val_debug_cpu_ptm1__PERIPHID7); +set_reset_data( debug_cpu_ptm1__PERIPHID0, val_debug_cpu_ptm1__PERIPHID0); +set_reset_data( debug_cpu_ptm1__PERIPHID1, val_debug_cpu_ptm1__PERIPHID1); +set_reset_data( debug_cpu_ptm1__PERIPHID2, val_debug_cpu_ptm1__PERIPHID2); +set_reset_data( debug_cpu_ptm1__PERIPHID3, val_debug_cpu_ptm1__PERIPHID3); +set_reset_data( debug_cpu_ptm1__COMPID0, val_debug_cpu_ptm1__COMPID0); +set_reset_data( debug_cpu_ptm1__COMPID1, val_debug_cpu_ptm1__COMPID1); +set_reset_data( debug_cpu_ptm1__COMPID2, val_debug_cpu_ptm1__COMPID2); +set_reset_data( debug_cpu_ptm1__COMPID3, val_debug_cpu_ptm1__COMPID3); + +// ************************************************************ +// Module debug_cti_axim cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_axim__CTICONTROL, val_debug_cti_axim__CTICONTROL); +set_reset_data( debug_cti_axim__CTIINTACK, val_debug_cti_axim__CTIINTACK); +set_reset_data( debug_cti_axim__CTIAPPSET, val_debug_cti_axim__CTIAPPSET); +set_reset_data( debug_cti_axim__CTIAPPCLEAR, val_debug_cti_axim__CTIAPPCLEAR); +set_reset_data( debug_cti_axim__CTIAPPPULSE, val_debug_cti_axim__CTIAPPPULSE); +set_reset_data( debug_cti_axim__CTIINEN0, val_debug_cti_axim__CTIINEN0); +set_reset_data( debug_cti_axim__CTIINEN1, val_debug_cti_axim__CTIINEN1); +set_reset_data( debug_cti_axim__CTIINEN2, val_debug_cti_axim__CTIINEN2); +set_reset_data( debug_cti_axim__CTIINEN3, val_debug_cti_axim__CTIINEN3); +set_reset_data( debug_cti_axim__CTIINEN4, val_debug_cti_axim__CTIINEN4); +set_reset_data( debug_cti_axim__CTIINEN5, val_debug_cti_axim__CTIINEN5); +set_reset_data( debug_cti_axim__CTIINEN6, val_debug_cti_axim__CTIINEN6); +set_reset_data( debug_cti_axim__CTIINEN7, val_debug_cti_axim__CTIINEN7); +set_reset_data( debug_cti_axim__CTIOUTEN0, val_debug_cti_axim__CTIOUTEN0); +set_reset_data( debug_cti_axim__CTIOUTEN1, val_debug_cti_axim__CTIOUTEN1); +set_reset_data( debug_cti_axim__CTIOUTEN2, val_debug_cti_axim__CTIOUTEN2); +set_reset_data( debug_cti_axim__CTIOUTEN3, val_debug_cti_axim__CTIOUTEN3); +set_reset_data( debug_cti_axim__CTIOUTEN4, val_debug_cti_axim__CTIOUTEN4); +set_reset_data( debug_cti_axim__CTIOUTEN5, val_debug_cti_axim__CTIOUTEN5); +set_reset_data( debug_cti_axim__CTIOUTEN6, val_debug_cti_axim__CTIOUTEN6); +set_reset_data( debug_cti_axim__CTIOUTEN7, val_debug_cti_axim__CTIOUTEN7); +set_reset_data( debug_cti_axim__CTITRIGINSTATUS, val_debug_cti_axim__CTITRIGINSTATUS); +set_reset_data( debug_cti_axim__CTITRIGOUTSTATUS, val_debug_cti_axim__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_axim__CTICHINSTATUS, val_debug_cti_axim__CTICHINSTATUS); +set_reset_data( debug_cti_axim__CTICHOUTSTATUS, val_debug_cti_axim__CTICHOUTSTATUS); +set_reset_data( debug_cti_axim__CTIGATE, val_debug_cti_axim__CTIGATE); +set_reset_data( debug_cti_axim__ASICCTL, val_debug_cti_axim__ASICCTL); +set_reset_data( debug_cti_axim__ITCHINACK, val_debug_cti_axim__ITCHINACK); +set_reset_data( debug_cti_axim__ITTRIGINACK, val_debug_cti_axim__ITTRIGINACK); +set_reset_data( debug_cti_axim__ITCHOUT, val_debug_cti_axim__ITCHOUT); +set_reset_data( debug_cti_axim__ITTRIGOUT, val_debug_cti_axim__ITTRIGOUT); +set_reset_data( debug_cti_axim__ITCHOUTACK, val_debug_cti_axim__ITCHOUTACK); +set_reset_data( debug_cti_axim__ITTRIGOUTACK, val_debug_cti_axim__ITTRIGOUTACK); +set_reset_data( debug_cti_axim__ITCHIN, val_debug_cti_axim__ITCHIN); +set_reset_data( debug_cti_axim__ITTRIGIN, val_debug_cti_axim__ITTRIGIN); +set_reset_data( debug_cti_axim__ITCTRL, val_debug_cti_axim__ITCTRL); +set_reset_data( debug_cti_axim__CTSR, val_debug_cti_axim__CTSR); +set_reset_data( debug_cti_axim__CTCR, val_debug_cti_axim__CTCR); +set_reset_data( debug_cti_axim__LAR, val_debug_cti_axim__LAR); +set_reset_data( debug_cti_axim__LSR, val_debug_cti_axim__LSR); +set_reset_data( debug_cti_axim__ASR, val_debug_cti_axim__ASR); +set_reset_data( debug_cti_axim__DEVID, val_debug_cti_axim__DEVID); +set_reset_data( debug_cti_axim__DTIR, val_debug_cti_axim__DTIR); +set_reset_data( debug_cti_axim__PERIPHID4, val_debug_cti_axim__PERIPHID4); +set_reset_data( debug_cti_axim__PERIPHID5, val_debug_cti_axim__PERIPHID5); +set_reset_data( debug_cti_axim__PERIPHID6, val_debug_cti_axim__PERIPHID6); +set_reset_data( debug_cti_axim__PERIPHID7, val_debug_cti_axim__PERIPHID7); +set_reset_data( debug_cti_axim__PERIPHID0, val_debug_cti_axim__PERIPHID0); +set_reset_data( debug_cti_axim__PERIPHID1, val_debug_cti_axim__PERIPHID1); +set_reset_data( debug_cti_axim__PERIPHID2, val_debug_cti_axim__PERIPHID2); +set_reset_data( debug_cti_axim__PERIPHID3, val_debug_cti_axim__PERIPHID3); +set_reset_data( debug_cti_axim__COMPID0, val_debug_cti_axim__COMPID0); +set_reset_data( debug_cti_axim__COMPID1, val_debug_cti_axim__COMPID1); +set_reset_data( debug_cti_axim__COMPID2, val_debug_cti_axim__COMPID2); +set_reset_data( debug_cti_axim__COMPID3, val_debug_cti_axim__COMPID3); + +// ************************************************************ +// Module debug_cti_etb_tpiu cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_etb_tpiu__CTICONTROL, val_debug_cti_etb_tpiu__CTICONTROL); +set_reset_data( debug_cti_etb_tpiu__CTIINTACK, val_debug_cti_etb_tpiu__CTIINTACK); +set_reset_data( debug_cti_etb_tpiu__CTIAPPSET, val_debug_cti_etb_tpiu__CTIAPPSET); +set_reset_data( debug_cti_etb_tpiu__CTIAPPCLEAR, val_debug_cti_etb_tpiu__CTIAPPCLEAR); +set_reset_data( debug_cti_etb_tpiu__CTIAPPPULSE, val_debug_cti_etb_tpiu__CTIAPPPULSE); +set_reset_data( debug_cti_etb_tpiu__CTIINEN0, val_debug_cti_etb_tpiu__CTIINEN0); +set_reset_data( debug_cti_etb_tpiu__CTIINEN1, val_debug_cti_etb_tpiu__CTIINEN1); +set_reset_data( debug_cti_etb_tpiu__CTIINEN2, val_debug_cti_etb_tpiu__CTIINEN2); +set_reset_data( debug_cti_etb_tpiu__CTIINEN3, val_debug_cti_etb_tpiu__CTIINEN3); +set_reset_data( debug_cti_etb_tpiu__CTIINEN4, val_debug_cti_etb_tpiu__CTIINEN4); +set_reset_data( debug_cti_etb_tpiu__CTIINEN5, val_debug_cti_etb_tpiu__CTIINEN5); +set_reset_data( debug_cti_etb_tpiu__CTIINEN6, val_debug_cti_etb_tpiu__CTIINEN6); +set_reset_data( debug_cti_etb_tpiu__CTIINEN7, val_debug_cti_etb_tpiu__CTIINEN7); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN0, val_debug_cti_etb_tpiu__CTIOUTEN0); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN1, val_debug_cti_etb_tpiu__CTIOUTEN1); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN2, val_debug_cti_etb_tpiu__CTIOUTEN2); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN3, val_debug_cti_etb_tpiu__CTIOUTEN3); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN4, val_debug_cti_etb_tpiu__CTIOUTEN4); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN5, val_debug_cti_etb_tpiu__CTIOUTEN5); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN6, val_debug_cti_etb_tpiu__CTIOUTEN6); +set_reset_data( debug_cti_etb_tpiu__CTIOUTEN7, val_debug_cti_etb_tpiu__CTIOUTEN7); +set_reset_data( debug_cti_etb_tpiu__CTITRIGINSTATUS, val_debug_cti_etb_tpiu__CTITRIGINSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTITRIGOUTSTATUS, val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTICHINSTATUS, val_debug_cti_etb_tpiu__CTICHINSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTICHOUTSTATUS, val_debug_cti_etb_tpiu__CTICHOUTSTATUS); +set_reset_data( debug_cti_etb_tpiu__CTIGATE, val_debug_cti_etb_tpiu__CTIGATE); +set_reset_data( debug_cti_etb_tpiu__ASICCTL, val_debug_cti_etb_tpiu__ASICCTL); +set_reset_data( debug_cti_etb_tpiu__ITCHINACK, val_debug_cti_etb_tpiu__ITCHINACK); +set_reset_data( debug_cti_etb_tpiu__ITTRIGINACK, val_debug_cti_etb_tpiu__ITTRIGINACK); +set_reset_data( debug_cti_etb_tpiu__ITCHOUT, val_debug_cti_etb_tpiu__ITCHOUT); +set_reset_data( debug_cti_etb_tpiu__ITTRIGOUT, val_debug_cti_etb_tpiu__ITTRIGOUT); +set_reset_data( debug_cti_etb_tpiu__ITCHOUTACK, val_debug_cti_etb_tpiu__ITCHOUTACK); +set_reset_data( debug_cti_etb_tpiu__ITTRIGOUTACK, val_debug_cti_etb_tpiu__ITTRIGOUTACK); +set_reset_data( debug_cti_etb_tpiu__ITCHIN, val_debug_cti_etb_tpiu__ITCHIN); +set_reset_data( debug_cti_etb_tpiu__ITTRIGIN, val_debug_cti_etb_tpiu__ITTRIGIN); +set_reset_data( debug_cti_etb_tpiu__ITCTRL, val_debug_cti_etb_tpiu__ITCTRL); +set_reset_data( debug_cti_etb_tpiu__CTSR, val_debug_cti_etb_tpiu__CTSR); +set_reset_data( debug_cti_etb_tpiu__CTCR, val_debug_cti_etb_tpiu__CTCR); +set_reset_data( debug_cti_etb_tpiu__LAR, val_debug_cti_etb_tpiu__LAR); +set_reset_data( debug_cti_etb_tpiu__LSR, val_debug_cti_etb_tpiu__LSR); +set_reset_data( debug_cti_etb_tpiu__ASR, val_debug_cti_etb_tpiu__ASR); +set_reset_data( debug_cti_etb_tpiu__DEVID, val_debug_cti_etb_tpiu__DEVID); +set_reset_data( debug_cti_etb_tpiu__DTIR, val_debug_cti_etb_tpiu__DTIR); +set_reset_data( debug_cti_etb_tpiu__PERIPHID4, val_debug_cti_etb_tpiu__PERIPHID4); +set_reset_data( debug_cti_etb_tpiu__PERIPHID5, val_debug_cti_etb_tpiu__PERIPHID5); +set_reset_data( debug_cti_etb_tpiu__PERIPHID6, val_debug_cti_etb_tpiu__PERIPHID6); +set_reset_data( debug_cti_etb_tpiu__PERIPHID7, val_debug_cti_etb_tpiu__PERIPHID7); +set_reset_data( debug_cti_etb_tpiu__PERIPHID0, val_debug_cti_etb_tpiu__PERIPHID0); +set_reset_data( debug_cti_etb_tpiu__PERIPHID1, val_debug_cti_etb_tpiu__PERIPHID1); +set_reset_data( debug_cti_etb_tpiu__PERIPHID2, val_debug_cti_etb_tpiu__PERIPHID2); +set_reset_data( debug_cti_etb_tpiu__PERIPHID3, val_debug_cti_etb_tpiu__PERIPHID3); +set_reset_data( debug_cti_etb_tpiu__COMPID0, val_debug_cti_etb_tpiu__COMPID0); +set_reset_data( debug_cti_etb_tpiu__COMPID1, val_debug_cti_etb_tpiu__COMPID1); +set_reset_data( debug_cti_etb_tpiu__COMPID2, val_debug_cti_etb_tpiu__COMPID2); +set_reset_data( debug_cti_etb_tpiu__COMPID3, val_debug_cti_etb_tpiu__COMPID3); + +// ************************************************************ +// Module debug_cti_ftm cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_cti_ftm__CTICONTROL, val_debug_cti_ftm__CTICONTROL); +set_reset_data( debug_cti_ftm__CTIINTACK, val_debug_cti_ftm__CTIINTACK); +set_reset_data( debug_cti_ftm__CTIAPPSET, val_debug_cti_ftm__CTIAPPSET); +set_reset_data( debug_cti_ftm__CTIAPPCLEAR, val_debug_cti_ftm__CTIAPPCLEAR); +set_reset_data( debug_cti_ftm__CTIAPPPULSE, val_debug_cti_ftm__CTIAPPPULSE); +set_reset_data( debug_cti_ftm__CTIINEN0, val_debug_cti_ftm__CTIINEN0); +set_reset_data( debug_cti_ftm__CTIINEN1, val_debug_cti_ftm__CTIINEN1); +set_reset_data( debug_cti_ftm__CTIINEN2, val_debug_cti_ftm__CTIINEN2); +set_reset_data( debug_cti_ftm__CTIINEN3, val_debug_cti_ftm__CTIINEN3); +set_reset_data( debug_cti_ftm__CTIINEN4, val_debug_cti_ftm__CTIINEN4); +set_reset_data( debug_cti_ftm__CTIINEN5, val_debug_cti_ftm__CTIINEN5); +set_reset_data( debug_cti_ftm__CTIINEN6, val_debug_cti_ftm__CTIINEN6); +set_reset_data( debug_cti_ftm__CTIINEN7, val_debug_cti_ftm__CTIINEN7); +set_reset_data( debug_cti_ftm__CTIOUTEN0, val_debug_cti_ftm__CTIOUTEN0); +set_reset_data( debug_cti_ftm__CTIOUTEN1, val_debug_cti_ftm__CTIOUTEN1); +set_reset_data( debug_cti_ftm__CTIOUTEN2, val_debug_cti_ftm__CTIOUTEN2); +set_reset_data( debug_cti_ftm__CTIOUTEN3, val_debug_cti_ftm__CTIOUTEN3); +set_reset_data( debug_cti_ftm__CTIOUTEN4, val_debug_cti_ftm__CTIOUTEN4); +set_reset_data( debug_cti_ftm__CTIOUTEN5, val_debug_cti_ftm__CTIOUTEN5); +set_reset_data( debug_cti_ftm__CTIOUTEN6, val_debug_cti_ftm__CTIOUTEN6); +set_reset_data( debug_cti_ftm__CTIOUTEN7, val_debug_cti_ftm__CTIOUTEN7); +set_reset_data( debug_cti_ftm__CTITRIGINSTATUS, val_debug_cti_ftm__CTITRIGINSTATUS); +set_reset_data( debug_cti_ftm__CTITRIGOUTSTATUS, val_debug_cti_ftm__CTITRIGOUTSTATUS); +set_reset_data( debug_cti_ftm__CTICHINSTATUS, val_debug_cti_ftm__CTICHINSTATUS); +set_reset_data( debug_cti_ftm__CTICHOUTSTATUS, val_debug_cti_ftm__CTICHOUTSTATUS); +set_reset_data( debug_cti_ftm__CTIGATE, val_debug_cti_ftm__CTIGATE); +set_reset_data( debug_cti_ftm__ASICCTL, val_debug_cti_ftm__ASICCTL); +set_reset_data( debug_cti_ftm__ITCHINACK, val_debug_cti_ftm__ITCHINACK); +set_reset_data( debug_cti_ftm__ITTRIGINACK, val_debug_cti_ftm__ITTRIGINACK); +set_reset_data( debug_cti_ftm__ITCHOUT, val_debug_cti_ftm__ITCHOUT); +set_reset_data( debug_cti_ftm__ITTRIGOUT, val_debug_cti_ftm__ITTRIGOUT); +set_reset_data( debug_cti_ftm__ITCHOUTACK, val_debug_cti_ftm__ITCHOUTACK); +set_reset_data( debug_cti_ftm__ITTRIGOUTACK, val_debug_cti_ftm__ITTRIGOUTACK); +set_reset_data( debug_cti_ftm__ITCHIN, val_debug_cti_ftm__ITCHIN); +set_reset_data( debug_cti_ftm__ITTRIGIN, val_debug_cti_ftm__ITTRIGIN); +set_reset_data( debug_cti_ftm__ITCTRL, val_debug_cti_ftm__ITCTRL); +set_reset_data( debug_cti_ftm__CTSR, val_debug_cti_ftm__CTSR); +set_reset_data( debug_cti_ftm__CTCR, val_debug_cti_ftm__CTCR); +set_reset_data( debug_cti_ftm__LAR, val_debug_cti_ftm__LAR); +set_reset_data( debug_cti_ftm__LSR, val_debug_cti_ftm__LSR); +set_reset_data( debug_cti_ftm__ASR, val_debug_cti_ftm__ASR); +set_reset_data( debug_cti_ftm__DEVID, val_debug_cti_ftm__DEVID); +set_reset_data( debug_cti_ftm__DTIR, val_debug_cti_ftm__DTIR); +set_reset_data( debug_cti_ftm__PERIPHID4, val_debug_cti_ftm__PERIPHID4); +set_reset_data( debug_cti_ftm__PERIPHID5, val_debug_cti_ftm__PERIPHID5); +set_reset_data( debug_cti_ftm__PERIPHID6, val_debug_cti_ftm__PERIPHID6); +set_reset_data( debug_cti_ftm__PERIPHID7, val_debug_cti_ftm__PERIPHID7); +set_reset_data( debug_cti_ftm__PERIPHID0, val_debug_cti_ftm__PERIPHID0); +set_reset_data( debug_cti_ftm__PERIPHID1, val_debug_cti_ftm__PERIPHID1); +set_reset_data( debug_cti_ftm__PERIPHID2, val_debug_cti_ftm__PERIPHID2); +set_reset_data( debug_cti_ftm__PERIPHID3, val_debug_cti_ftm__PERIPHID3); +set_reset_data( debug_cti_ftm__COMPID0, val_debug_cti_ftm__COMPID0); +set_reset_data( debug_cti_ftm__COMPID1, val_debug_cti_ftm__COMPID1); +set_reset_data( debug_cti_ftm__COMPID2, val_debug_cti_ftm__COMPID2); +set_reset_data( debug_cti_ftm__COMPID3, val_debug_cti_ftm__COMPID3); + +// ************************************************************ +// Module debug_dap_rom dap +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_dap_rom__ROMENTRY00, val_debug_dap_rom__ROMENTRY00); +set_reset_data( debug_dap_rom__ROMENTRY01, val_debug_dap_rom__ROMENTRY01); +set_reset_data( debug_dap_rom__ROMENTRY02, val_debug_dap_rom__ROMENTRY02); +set_reset_data( debug_dap_rom__ROMENTRY03, val_debug_dap_rom__ROMENTRY03); +set_reset_data( debug_dap_rom__ROMENTRY04, val_debug_dap_rom__ROMENTRY04); +set_reset_data( debug_dap_rom__ROMENTRY05, val_debug_dap_rom__ROMENTRY05); +set_reset_data( debug_dap_rom__ROMENTRY06, val_debug_dap_rom__ROMENTRY06); +set_reset_data( debug_dap_rom__ROMENTRY07, val_debug_dap_rom__ROMENTRY07); +set_reset_data( debug_dap_rom__ROMENTRY08, val_debug_dap_rom__ROMENTRY08); +set_reset_data( debug_dap_rom__ROMENTRY09, val_debug_dap_rom__ROMENTRY09); +set_reset_data( debug_dap_rom__ROMENTRY10, val_debug_dap_rom__ROMENTRY10); +set_reset_data( debug_dap_rom__ROMENTRY11, val_debug_dap_rom__ROMENTRY11); +set_reset_data( debug_dap_rom__ROMENTRY12, val_debug_dap_rom__ROMENTRY12); +set_reset_data( debug_dap_rom__ROMENTRY13, val_debug_dap_rom__ROMENTRY13); +set_reset_data( debug_dap_rom__ROMENTRY14, val_debug_dap_rom__ROMENTRY14); +set_reset_data( debug_dap_rom__ROMENTRY15, val_debug_dap_rom__ROMENTRY15); +set_reset_data( debug_dap_rom__PERIPHID4, val_debug_dap_rom__PERIPHID4); +set_reset_data( debug_dap_rom__PERIPHID5, val_debug_dap_rom__PERIPHID5); +set_reset_data( debug_dap_rom__PERIPHID6, val_debug_dap_rom__PERIPHID6); +set_reset_data( debug_dap_rom__PERIPHID7, val_debug_dap_rom__PERIPHID7); +set_reset_data( debug_dap_rom__PERIPHID0, val_debug_dap_rom__PERIPHID0); +set_reset_data( debug_dap_rom__PERIPHID1, val_debug_dap_rom__PERIPHID1); +set_reset_data( debug_dap_rom__PERIPHID2, val_debug_dap_rom__PERIPHID2); +set_reset_data( debug_dap_rom__PERIPHID3, val_debug_dap_rom__PERIPHID3); +set_reset_data( debug_dap_rom__COMPID0, val_debug_dap_rom__COMPID0); +set_reset_data( debug_dap_rom__COMPID1, val_debug_dap_rom__COMPID1); +set_reset_data( debug_dap_rom__COMPID2, val_debug_dap_rom__COMPID2); +set_reset_data( debug_dap_rom__COMPID3, val_debug_dap_rom__COMPID3); + +// ************************************************************ +// Module debug_etb etb +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_etb__RDP, val_debug_etb__RDP); +set_reset_data( debug_etb__STS, val_debug_etb__STS); +set_reset_data( debug_etb__RRD, val_debug_etb__RRD); +set_reset_data( debug_etb__RRP, val_debug_etb__RRP); +set_reset_data( debug_etb__RWP, val_debug_etb__RWP); +set_reset_data( debug_etb__TRG, val_debug_etb__TRG); +set_reset_data( debug_etb__CTL, val_debug_etb__CTL); +set_reset_data( debug_etb__RWD, val_debug_etb__RWD); +set_reset_data( debug_etb__FFSR, val_debug_etb__FFSR); +set_reset_data( debug_etb__FFCR, val_debug_etb__FFCR); +set_reset_data( debug_etb__ITMISCOP0, val_debug_etb__ITMISCOP0); +set_reset_data( debug_etb__ITTRFLINACK, val_debug_etb__ITTRFLINACK); +set_reset_data( debug_etb__ITTRFLIN, val_debug_etb__ITTRFLIN); +set_reset_data( debug_etb__ITATBDATA0, val_debug_etb__ITATBDATA0); +set_reset_data( debug_etb__ITATBCTR2, val_debug_etb__ITATBCTR2); +set_reset_data( debug_etb__ITATBCTR1, val_debug_etb__ITATBCTR1); +set_reset_data( debug_etb__ITATBCTR0, val_debug_etb__ITATBCTR0); +set_reset_data( debug_etb__IMCR, val_debug_etb__IMCR); +set_reset_data( debug_etb__CTSR, val_debug_etb__CTSR); +set_reset_data( debug_etb__CTCR, val_debug_etb__CTCR); +set_reset_data( debug_etb__LAR, val_debug_etb__LAR); +set_reset_data( debug_etb__LSR, val_debug_etb__LSR); +set_reset_data( debug_etb__ASR, val_debug_etb__ASR); +set_reset_data( debug_etb__DEVID, val_debug_etb__DEVID); +set_reset_data( debug_etb__DTIR, val_debug_etb__DTIR); +set_reset_data( debug_etb__PERIPHID4, val_debug_etb__PERIPHID4); +set_reset_data( debug_etb__PERIPHID5, val_debug_etb__PERIPHID5); +set_reset_data( debug_etb__PERIPHID6, val_debug_etb__PERIPHID6); +set_reset_data( debug_etb__PERIPHID7, val_debug_etb__PERIPHID7); +set_reset_data( debug_etb__PERIPHID0, val_debug_etb__PERIPHID0); +set_reset_data( debug_etb__PERIPHID1, val_debug_etb__PERIPHID1); +set_reset_data( debug_etb__PERIPHID2, val_debug_etb__PERIPHID2); +set_reset_data( debug_etb__PERIPHID3, val_debug_etb__PERIPHID3); +set_reset_data( debug_etb__COMPID0, val_debug_etb__COMPID0); +set_reset_data( debug_etb__COMPID1, val_debug_etb__COMPID1); +set_reset_data( debug_etb__COMPID2, val_debug_etb__COMPID2); +set_reset_data( debug_etb__COMPID3, val_debug_etb__COMPID3); + +// ************************************************************ +// Module debug_ftm ftm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_ftm__FTMGLBCTRL, val_debug_ftm__FTMGLBCTRL); +set_reset_data( debug_ftm__FTMSTATUS, val_debug_ftm__FTMSTATUS); +set_reset_data( debug_ftm__FTMCONTROL, val_debug_ftm__FTMCONTROL); +set_reset_data( debug_ftm__FTMP2FDBG0, val_debug_ftm__FTMP2FDBG0); +set_reset_data( debug_ftm__FTMP2FDBG1, val_debug_ftm__FTMP2FDBG1); +set_reset_data( debug_ftm__FTMP2FDBG2, val_debug_ftm__FTMP2FDBG2); +set_reset_data( debug_ftm__FTMP2FDBG3, val_debug_ftm__FTMP2FDBG3); +set_reset_data( debug_ftm__FTMF2PDBG0, val_debug_ftm__FTMF2PDBG0); +set_reset_data( debug_ftm__FTMF2PDBG1, val_debug_ftm__FTMF2PDBG1); +set_reset_data( debug_ftm__FTMF2PDBG2, val_debug_ftm__FTMF2PDBG2); +set_reset_data( debug_ftm__FTMF2PDBG3, val_debug_ftm__FTMF2PDBG3); +set_reset_data( debug_ftm__CYCOUNTPRE, val_debug_ftm__CYCOUNTPRE); +set_reset_data( debug_ftm__FTMSYNCRELOAD, val_debug_ftm__FTMSYNCRELOAD); +set_reset_data( debug_ftm__FTMSYNCCOUT, val_debug_ftm__FTMSYNCCOUT); +set_reset_data( debug_ftm__FTMATID, val_debug_ftm__FTMATID); +set_reset_data( debug_ftm__FTMITTRIGOUTACK, val_debug_ftm__FTMITTRIGOUTACK); +set_reset_data( debug_ftm__FTMITTRIGGER, val_debug_ftm__FTMITTRIGGER); +set_reset_data( debug_ftm__FTMITTRACEDIS, val_debug_ftm__FTMITTRACEDIS); +set_reset_data( debug_ftm__FTMITCYCCOUNT, val_debug_ftm__FTMITCYCCOUNT); +set_reset_data( debug_ftm__FTMITATBDATA0, val_debug_ftm__FTMITATBDATA0); +set_reset_data( debug_ftm__FTMITATBCTR2, val_debug_ftm__FTMITATBCTR2); +set_reset_data( debug_ftm__FTMITATBCTR1, val_debug_ftm__FTMITATBCTR1); +set_reset_data( debug_ftm__FTMITATBCTR0, val_debug_ftm__FTMITATBCTR0); +set_reset_data( debug_ftm__FTMITCR, val_debug_ftm__FTMITCR); +set_reset_data( debug_ftm__CLAIMTAGSET, val_debug_ftm__CLAIMTAGSET); +set_reset_data( debug_ftm__CLAIMTAGCLR, val_debug_ftm__CLAIMTAGCLR); +set_reset_data( debug_ftm__LOCK_ACCESS, val_debug_ftm__LOCK_ACCESS); +set_reset_data( debug_ftm__LOCK_STATUS, val_debug_ftm__LOCK_STATUS); +set_reset_data( debug_ftm__FTMAUTHSTATUS, val_debug_ftm__FTMAUTHSTATUS); +set_reset_data( debug_ftm__FTMDEVID, val_debug_ftm__FTMDEVID); +set_reset_data( debug_ftm__FTMDEV_TYPE, val_debug_ftm__FTMDEV_TYPE); +set_reset_data( debug_ftm__FTMPERIPHID4, val_debug_ftm__FTMPERIPHID4); +set_reset_data( debug_ftm__FTMPERIPHID5, val_debug_ftm__FTMPERIPHID5); +set_reset_data( debug_ftm__FTMPERIPHID6, val_debug_ftm__FTMPERIPHID6); +set_reset_data( debug_ftm__FTMPERIPHID7, val_debug_ftm__FTMPERIPHID7); +set_reset_data( debug_ftm__FTMPERIPHID0, val_debug_ftm__FTMPERIPHID0); +set_reset_data( debug_ftm__FTMPERIPHID1, val_debug_ftm__FTMPERIPHID1); +set_reset_data( debug_ftm__FTMPERIPHID2, val_debug_ftm__FTMPERIPHID2); +set_reset_data( debug_ftm__FTMPERIPHID3, val_debug_ftm__FTMPERIPHID3); +set_reset_data( debug_ftm__FTMCOMPONID0, val_debug_ftm__FTMCOMPONID0); +set_reset_data( debug_ftm__FTMCOMPONID1, val_debug_ftm__FTMCOMPONID1); +set_reset_data( debug_ftm__FTMCOMPONID2, val_debug_ftm__FTMCOMPONID2); +set_reset_data( debug_ftm__FTMCOMPONID3, val_debug_ftm__FTMCOMPONID3); + +// ************************************************************ +// Module debug_funnel funnel +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_funnel__Control, val_debug_funnel__Control); +set_reset_data( debug_funnel__PriControl, val_debug_funnel__PriControl); +set_reset_data( debug_funnel__ITATBDATA0, val_debug_funnel__ITATBDATA0); +set_reset_data( debug_funnel__ITATBCTR2, val_debug_funnel__ITATBCTR2); +set_reset_data( debug_funnel__ITATBCTR1, val_debug_funnel__ITATBCTR1); +set_reset_data( debug_funnel__ITATBCTR0, val_debug_funnel__ITATBCTR0); +set_reset_data( debug_funnel__IMCR, val_debug_funnel__IMCR); +set_reset_data( debug_funnel__CTSR, val_debug_funnel__CTSR); +set_reset_data( debug_funnel__CTCR, val_debug_funnel__CTCR); +set_reset_data( debug_funnel__LAR, val_debug_funnel__LAR); +set_reset_data( debug_funnel__LSR, val_debug_funnel__LSR); +set_reset_data( debug_funnel__ASR, val_debug_funnel__ASR); +set_reset_data( debug_funnel__DEVID, val_debug_funnel__DEVID); +set_reset_data( debug_funnel__DTIR, val_debug_funnel__DTIR); +set_reset_data( debug_funnel__PERIPHID4, val_debug_funnel__PERIPHID4); +set_reset_data( debug_funnel__PERIPHID5, val_debug_funnel__PERIPHID5); +set_reset_data( debug_funnel__PERIPHID6, val_debug_funnel__PERIPHID6); +set_reset_data( debug_funnel__PERIPHID7, val_debug_funnel__PERIPHID7); +set_reset_data( debug_funnel__PERIPHID0, val_debug_funnel__PERIPHID0); +set_reset_data( debug_funnel__PERIPHID1, val_debug_funnel__PERIPHID1); +set_reset_data( debug_funnel__PERIPHID2, val_debug_funnel__PERIPHID2); +set_reset_data( debug_funnel__PERIPHID3, val_debug_funnel__PERIPHID3); +set_reset_data( debug_funnel__COMPID0, val_debug_funnel__COMPID0); +set_reset_data( debug_funnel__COMPID1, val_debug_funnel__COMPID1); +set_reset_data( debug_funnel__COMPID2, val_debug_funnel__COMPID2); +set_reset_data( debug_funnel__COMPID3, val_debug_funnel__COMPID3); + +// ************************************************************ +// Module debug_itm itm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_itm__StimPort00, val_debug_itm__StimPort00); +set_reset_data( debug_itm__StimPort01, val_debug_itm__StimPort01); +set_reset_data( debug_itm__StimPort02, val_debug_itm__StimPort02); +set_reset_data( debug_itm__StimPort03, val_debug_itm__StimPort03); +set_reset_data( debug_itm__StimPort04, val_debug_itm__StimPort04); +set_reset_data( debug_itm__StimPort05, val_debug_itm__StimPort05); +set_reset_data( debug_itm__StimPort06, val_debug_itm__StimPort06); +set_reset_data( debug_itm__StimPort07, val_debug_itm__StimPort07); +set_reset_data( debug_itm__StimPort08, val_debug_itm__StimPort08); +set_reset_data( debug_itm__StimPort09, val_debug_itm__StimPort09); +set_reset_data( debug_itm__StimPort10, val_debug_itm__StimPort10); +set_reset_data( debug_itm__StimPort11, val_debug_itm__StimPort11); +set_reset_data( debug_itm__StimPort12, val_debug_itm__StimPort12); +set_reset_data( debug_itm__StimPort13, val_debug_itm__StimPort13); +set_reset_data( debug_itm__StimPort14, val_debug_itm__StimPort14); +set_reset_data( debug_itm__StimPort15, val_debug_itm__StimPort15); +set_reset_data( debug_itm__StimPort16, val_debug_itm__StimPort16); +set_reset_data( debug_itm__StimPort17, val_debug_itm__StimPort17); +set_reset_data( debug_itm__StimPort18, val_debug_itm__StimPort18); +set_reset_data( debug_itm__StimPort19, val_debug_itm__StimPort19); +set_reset_data( debug_itm__StimPort20, val_debug_itm__StimPort20); +set_reset_data( debug_itm__StimPort21, val_debug_itm__StimPort21); +set_reset_data( debug_itm__StimPort22, val_debug_itm__StimPort22); +set_reset_data( debug_itm__StimPort23, val_debug_itm__StimPort23); +set_reset_data( debug_itm__StimPort24, val_debug_itm__StimPort24); +set_reset_data( debug_itm__StimPort25, val_debug_itm__StimPort25); +set_reset_data( debug_itm__StimPort26, val_debug_itm__StimPort26); +set_reset_data( debug_itm__StimPort27, val_debug_itm__StimPort27); +set_reset_data( debug_itm__StimPort28, val_debug_itm__StimPort28); +set_reset_data( debug_itm__StimPort29, val_debug_itm__StimPort29); +set_reset_data( debug_itm__StimPort30, val_debug_itm__StimPort30); +set_reset_data( debug_itm__StimPort31, val_debug_itm__StimPort31); +set_reset_data( debug_itm__TER, val_debug_itm__TER); +set_reset_data( debug_itm__TTR, val_debug_itm__TTR); +set_reset_data( debug_itm__CR, val_debug_itm__CR); +set_reset_data( debug_itm__SCR, val_debug_itm__SCR); +set_reset_data( debug_itm__ITTRIGOUTACK, val_debug_itm__ITTRIGOUTACK); +set_reset_data( debug_itm__ITTRIGOUT, val_debug_itm__ITTRIGOUT); +set_reset_data( debug_itm__ITATBDATA0, val_debug_itm__ITATBDATA0); +set_reset_data( debug_itm__ITATBCTR2, val_debug_itm__ITATBCTR2); +set_reset_data( debug_itm__ITATABCTR1, val_debug_itm__ITATABCTR1); +set_reset_data( debug_itm__ITATBCTR0, val_debug_itm__ITATBCTR0); +set_reset_data( debug_itm__IMCR, val_debug_itm__IMCR); +set_reset_data( debug_itm__CTSR, val_debug_itm__CTSR); +set_reset_data( debug_itm__CTCR, val_debug_itm__CTCR); +set_reset_data( debug_itm__LAR, val_debug_itm__LAR); +set_reset_data( debug_itm__LSR, val_debug_itm__LSR); +set_reset_data( debug_itm__ASR, val_debug_itm__ASR); +set_reset_data( debug_itm__DEVID, val_debug_itm__DEVID); +set_reset_data( debug_itm__DTIR, val_debug_itm__DTIR); +set_reset_data( debug_itm__PERIPHID4, val_debug_itm__PERIPHID4); +set_reset_data( debug_itm__PERIPHID5, val_debug_itm__PERIPHID5); +set_reset_data( debug_itm__PERIPHID6, val_debug_itm__PERIPHID6); +set_reset_data( debug_itm__PERIPHID7, val_debug_itm__PERIPHID7); +set_reset_data( debug_itm__PERIPHID0, val_debug_itm__PERIPHID0); +set_reset_data( debug_itm__PERIPHID1, val_debug_itm__PERIPHID1); +set_reset_data( debug_itm__PERIPHID2, val_debug_itm__PERIPHID2); +set_reset_data( debug_itm__PERIPHID3, val_debug_itm__PERIPHID3); +set_reset_data( debug_itm__COMPID0, val_debug_itm__COMPID0); +set_reset_data( debug_itm__COMPID1, val_debug_itm__COMPID1); +set_reset_data( debug_itm__COMPID2, val_debug_itm__COMPID2); +set_reset_data( debug_itm__COMPID3, val_debug_itm__COMPID3); + +// ************************************************************ +// Module debug_tpiu tpiu +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( debug_tpiu__SuppSize, val_debug_tpiu__SuppSize); +set_reset_data( debug_tpiu__CurrentSize, val_debug_tpiu__CurrentSize); +set_reset_data( debug_tpiu__SuppTrigMode, val_debug_tpiu__SuppTrigMode); +set_reset_data( debug_tpiu__TrigCount, val_debug_tpiu__TrigCount); +set_reset_data( debug_tpiu__TrigMult, val_debug_tpiu__TrigMult); +set_reset_data( debug_tpiu__SuppTest, val_debug_tpiu__SuppTest); +set_reset_data( debug_tpiu__CurrentTest, val_debug_tpiu__CurrentTest); +set_reset_data( debug_tpiu__TestRepeatCount, val_debug_tpiu__TestRepeatCount); +set_reset_data( debug_tpiu__FFSR, val_debug_tpiu__FFSR); +set_reset_data( debug_tpiu__FFCR, val_debug_tpiu__FFCR); +set_reset_data( debug_tpiu__FormatSyncCount, val_debug_tpiu__FormatSyncCount); +set_reset_data( debug_tpiu__EXTCTLIn, val_debug_tpiu__EXTCTLIn); +set_reset_data( debug_tpiu__EXTCTLOut, val_debug_tpiu__EXTCTLOut); +set_reset_data( debug_tpiu__ITTRFLINACK, val_debug_tpiu__ITTRFLINACK); +set_reset_data( debug_tpiu__ITTRFLIN, val_debug_tpiu__ITTRFLIN); +set_reset_data( debug_tpiu__ITATBDATA0, val_debug_tpiu__ITATBDATA0); +set_reset_data( debug_tpiu__ITATBCTR2, val_debug_tpiu__ITATBCTR2); +set_reset_data( debug_tpiu__ITATBCTR1, val_debug_tpiu__ITATBCTR1); +set_reset_data( debug_tpiu__ITATBCTR0, val_debug_tpiu__ITATBCTR0); +set_reset_data( debug_tpiu__IMCR, val_debug_tpiu__IMCR); +set_reset_data( debug_tpiu__CTSR, val_debug_tpiu__CTSR); +set_reset_data( debug_tpiu__CTCR, val_debug_tpiu__CTCR); +set_reset_data( debug_tpiu__LAR, val_debug_tpiu__LAR); +set_reset_data( debug_tpiu__LSR, val_debug_tpiu__LSR); +set_reset_data( debug_tpiu__ASR, val_debug_tpiu__ASR); +set_reset_data( debug_tpiu__DEVID, val_debug_tpiu__DEVID); +set_reset_data( debug_tpiu__DTIR, val_debug_tpiu__DTIR); +set_reset_data( debug_tpiu__PERIPHID4, val_debug_tpiu__PERIPHID4); +set_reset_data( debug_tpiu__PERIPHID5, val_debug_tpiu__PERIPHID5); +set_reset_data( debug_tpiu__PERIPHID6, val_debug_tpiu__PERIPHID6); +set_reset_data( debug_tpiu__PERIPHID7, val_debug_tpiu__PERIPHID7); +set_reset_data( debug_tpiu__PERIPHID0, val_debug_tpiu__PERIPHID0); +set_reset_data( debug_tpiu__PERIPHID1, val_debug_tpiu__PERIPHID1); +set_reset_data( debug_tpiu__PERIPHID2, val_debug_tpiu__PERIPHID2); +set_reset_data( debug_tpiu__PERIPHID3, val_debug_tpiu__PERIPHID3); +set_reset_data( debug_tpiu__COMPID0, val_debug_tpiu__COMPID0); +set_reset_data( debug_tpiu__COMPID1, val_debug_tpiu__COMPID1); +set_reset_data( debug_tpiu__COMPID2, val_debug_tpiu__COMPID2); +set_reset_data( debug_tpiu__COMPID3, val_debug_tpiu__COMPID3); + +// ************************************************************ +// Module devcfg devcfg +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( devcfg__CTRL, val_devcfg__CTRL); +set_reset_data( devcfg__LOCK, val_devcfg__LOCK); +set_reset_data( devcfg__CFG, val_devcfg__CFG); +set_reset_data( devcfg__INT_STS, val_devcfg__INT_STS); +set_reset_data( devcfg__INT_MASK, val_devcfg__INT_MASK); +set_reset_data( devcfg__STATUS, val_devcfg__STATUS); +set_reset_data( devcfg__DMA_SRC_ADDR, val_devcfg__DMA_SRC_ADDR); +set_reset_data( devcfg__DMA_DST_ADDR, val_devcfg__DMA_DST_ADDR); +set_reset_data( devcfg__DMA_SRC_LEN, val_devcfg__DMA_SRC_LEN); +set_reset_data( devcfg__DMA_DEST_LEN, val_devcfg__DMA_DEST_LEN); +set_reset_data( devcfg__ROM_SHADOW, val_devcfg__ROM_SHADOW); +set_reset_data( devcfg__MULTIBOOT_ADDR, val_devcfg__MULTIBOOT_ADDR); +set_reset_data( devcfg__SW_ID, val_devcfg__SW_ID); +set_reset_data( devcfg__UNLOCK, val_devcfg__UNLOCK); +set_reset_data( devcfg__MCTRL, val_devcfg__MCTRL); +set_reset_data( devcfg__XADCIF_CFG, val_devcfg__XADCIF_CFG); +set_reset_data( devcfg__XADCIF_INT_STS, val_devcfg__XADCIF_INT_STS); +set_reset_data( devcfg__XADCIF_INT_MASK, val_devcfg__XADCIF_INT_MASK); +set_reset_data( devcfg__XADCIF_MSTS, val_devcfg__XADCIF_MSTS); +set_reset_data( devcfg__XADCIF_CMDFIFO, val_devcfg__XADCIF_CMDFIFO); +set_reset_data( devcfg__XADCIF_RDFIFO, val_devcfg__XADCIF_RDFIFO); +set_reset_data( devcfg__XADCIF_MCTL, val_devcfg__XADCIF_MCTL); + +// ************************************************************ +// Module dmac0_ns dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( dmac0_ns__DSR, val_dmac0_ns__DSR); +set_reset_data( dmac0_ns__DPC, val_dmac0_ns__DPC); +set_reset_data( dmac0_ns__INTEN, val_dmac0_ns__INTEN); +set_reset_data( dmac0_ns__INT_EVENT_RIS, val_dmac0_ns__INT_EVENT_RIS); +set_reset_data( dmac0_ns__INTMIS, val_dmac0_ns__INTMIS); +set_reset_data( dmac0_ns__INTCLR, val_dmac0_ns__INTCLR); +set_reset_data( dmac0_ns__FSRD, val_dmac0_ns__FSRD); +set_reset_data( dmac0_ns__FSRC, val_dmac0_ns__FSRC); +set_reset_data( dmac0_ns__FTRD, val_dmac0_ns__FTRD); +set_reset_data( dmac0_ns__FTR0, val_dmac0_ns__FTR0); +set_reset_data( dmac0_ns__FTR1, val_dmac0_ns__FTR1); +set_reset_data( dmac0_ns__FTR2, val_dmac0_ns__FTR2); +set_reset_data( dmac0_ns__FTR3, val_dmac0_ns__FTR3); +set_reset_data( dmac0_ns__FTR4, val_dmac0_ns__FTR4); +set_reset_data( dmac0_ns__FTR5, val_dmac0_ns__FTR5); +set_reset_data( dmac0_ns__FTR6, val_dmac0_ns__FTR6); +set_reset_data( dmac0_ns__FTR7, val_dmac0_ns__FTR7); +set_reset_data( dmac0_ns__CSR0, val_dmac0_ns__CSR0); +set_reset_data( dmac0_ns__CPC0, val_dmac0_ns__CPC0); +set_reset_data( dmac0_ns__CSR1, val_dmac0_ns__CSR1); +set_reset_data( dmac0_ns__CPC1, val_dmac0_ns__CPC1); +set_reset_data( dmac0_ns__CSR2, val_dmac0_ns__CSR2); +set_reset_data( dmac0_ns__CPC2, val_dmac0_ns__CPC2); +set_reset_data( dmac0_ns__CSR3, val_dmac0_ns__CSR3); +set_reset_data( dmac0_ns__CPC3, val_dmac0_ns__CPC3); +set_reset_data( dmac0_ns__CSR4, val_dmac0_ns__CSR4); +set_reset_data( dmac0_ns__CPC4, val_dmac0_ns__CPC4); +set_reset_data( dmac0_ns__CSR5, val_dmac0_ns__CSR5); +set_reset_data( dmac0_ns__CPC5, val_dmac0_ns__CPC5); +set_reset_data( dmac0_ns__CSR6, val_dmac0_ns__CSR6); +set_reset_data( dmac0_ns__CPC6, val_dmac0_ns__CPC6); +set_reset_data( dmac0_ns__CSR7, val_dmac0_ns__CSR7); +set_reset_data( dmac0_ns__CPC7, val_dmac0_ns__CPC7); +set_reset_data( dmac0_ns__SAR0, val_dmac0_ns__SAR0); +set_reset_data( dmac0_ns__DAR0, val_dmac0_ns__DAR0); +set_reset_data( dmac0_ns__CCR0, val_dmac0_ns__CCR0); +set_reset_data( dmac0_ns__LC0_0, val_dmac0_ns__LC0_0); +set_reset_data( dmac0_ns__LC1_0, val_dmac0_ns__LC1_0); +set_reset_data( dmac0_ns__SAR1, val_dmac0_ns__SAR1); +set_reset_data( dmac0_ns__DAR1, val_dmac0_ns__DAR1); +set_reset_data( dmac0_ns__CCR1, val_dmac0_ns__CCR1); +set_reset_data( dmac0_ns__LC0_1, val_dmac0_ns__LC0_1); +set_reset_data( dmac0_ns__LC1_1, val_dmac0_ns__LC1_1); +set_reset_data( dmac0_ns__SAR2, val_dmac0_ns__SAR2); +set_reset_data( dmac0_ns__DAR2, val_dmac0_ns__DAR2); +set_reset_data( dmac0_ns__CCR2, val_dmac0_ns__CCR2); +set_reset_data( dmac0_ns__LC0_2, val_dmac0_ns__LC0_2); +set_reset_data( dmac0_ns__LC1_2, val_dmac0_ns__LC1_2); +set_reset_data( dmac0_ns__SAR3, val_dmac0_ns__SAR3); +set_reset_data( dmac0_ns__DAR3, val_dmac0_ns__DAR3); +set_reset_data( dmac0_ns__CCR3, val_dmac0_ns__CCR3); +set_reset_data( dmac0_ns__LC0_3, val_dmac0_ns__LC0_3); +set_reset_data( dmac0_ns__LC1_3, val_dmac0_ns__LC1_3); +set_reset_data( dmac0_ns__SAR4, val_dmac0_ns__SAR4); +set_reset_data( dmac0_ns__DAR4, val_dmac0_ns__DAR4); +set_reset_data( dmac0_ns__CCR4, val_dmac0_ns__CCR4); +set_reset_data( dmac0_ns__LC0_4, val_dmac0_ns__LC0_4); +set_reset_data( dmac0_ns__LC1_4, val_dmac0_ns__LC1_4); +set_reset_data( dmac0_ns__SAR5, val_dmac0_ns__SAR5); +set_reset_data( dmac0_ns__DAR5, val_dmac0_ns__DAR5); +set_reset_data( dmac0_ns__CCR5, val_dmac0_ns__CCR5); +set_reset_data( dmac0_ns__LC0_5, val_dmac0_ns__LC0_5); +set_reset_data( dmac0_ns__LC1_5, val_dmac0_ns__LC1_5); +set_reset_data( dmac0_ns__SAR6, val_dmac0_ns__SAR6); +set_reset_data( dmac0_ns__DAR6, val_dmac0_ns__DAR6); +set_reset_data( dmac0_ns__CCR6, val_dmac0_ns__CCR6); +set_reset_data( dmac0_ns__LC0_6, val_dmac0_ns__LC0_6); +set_reset_data( dmac0_ns__LC1_6, val_dmac0_ns__LC1_6); +set_reset_data( dmac0_ns__SAR7, val_dmac0_ns__SAR7); +set_reset_data( dmac0_ns__DAR7, val_dmac0_ns__DAR7); +set_reset_data( dmac0_ns__CCR7, val_dmac0_ns__CCR7); +set_reset_data( dmac0_ns__LC0_7, val_dmac0_ns__LC0_7); +set_reset_data( dmac0_ns__LC1_7, val_dmac0_ns__LC1_7); +set_reset_data( dmac0_ns__DBGSTATUS, val_dmac0_ns__DBGSTATUS); +set_reset_data( dmac0_ns__DBGCMD, val_dmac0_ns__DBGCMD); +set_reset_data( dmac0_ns__DBGINST0, val_dmac0_ns__DBGINST0); +set_reset_data( dmac0_ns__DBGINST1, val_dmac0_ns__DBGINST1); +set_reset_data( dmac0_ns__CR0, val_dmac0_ns__CR0); +set_reset_data( dmac0_ns__CR1, val_dmac0_ns__CR1); +set_reset_data( dmac0_ns__CR2, val_dmac0_ns__CR2); +set_reset_data( dmac0_ns__CR3, val_dmac0_ns__CR3); +set_reset_data( dmac0_ns__CR4, val_dmac0_ns__CR4); +set_reset_data( dmac0_ns__CRD, val_dmac0_ns__CRD); +set_reset_data( dmac0_ns__WD, val_dmac0_ns__WD); +set_reset_data( dmac0_ns__periph_id_0, val_dmac0_ns__periph_id_0); +set_reset_data( dmac0_ns__periph_id_1, val_dmac0_ns__periph_id_1); +set_reset_data( dmac0_ns__periph_id_2, val_dmac0_ns__periph_id_2); +set_reset_data( dmac0_ns__periph_id_3, val_dmac0_ns__periph_id_3); +set_reset_data( dmac0_ns__pcell_id_0, val_dmac0_ns__pcell_id_0); +set_reset_data( dmac0_ns__pcell_id_1, val_dmac0_ns__pcell_id_1); +set_reset_data( dmac0_ns__pcell_id_2, val_dmac0_ns__pcell_id_2); +set_reset_data( dmac0_ns__pcell_id_3, val_dmac0_ns__pcell_id_3); + +// ************************************************************ +// Module dmac0_s dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( dmac0_s__DSR, val_dmac0_s__DSR); +set_reset_data( dmac0_s__DPC, val_dmac0_s__DPC); +set_reset_data( dmac0_s__INTEN, val_dmac0_s__INTEN); +set_reset_data( dmac0_s__INT_EVENT_RIS, val_dmac0_s__INT_EVENT_RIS); +set_reset_data( dmac0_s__INTMIS, val_dmac0_s__INTMIS); +set_reset_data( dmac0_s__INTCLR, val_dmac0_s__INTCLR); +set_reset_data( dmac0_s__FSRD, val_dmac0_s__FSRD); +set_reset_data( dmac0_s__FSRC, val_dmac0_s__FSRC); +set_reset_data( dmac0_s__FTRD, val_dmac0_s__FTRD); +set_reset_data( dmac0_s__FTR0, val_dmac0_s__FTR0); +set_reset_data( dmac0_s__FTR1, val_dmac0_s__FTR1); +set_reset_data( dmac0_s__FTR2, val_dmac0_s__FTR2); +set_reset_data( dmac0_s__FTR3, val_dmac0_s__FTR3); +set_reset_data( dmac0_s__FTR4, val_dmac0_s__FTR4); +set_reset_data( dmac0_s__FTR5, val_dmac0_s__FTR5); +set_reset_data( dmac0_s__FTR6, val_dmac0_s__FTR6); +set_reset_data( dmac0_s__FTR7, val_dmac0_s__FTR7); +set_reset_data( dmac0_s__CSR0, val_dmac0_s__CSR0); +set_reset_data( dmac0_s__CPC0, val_dmac0_s__CPC0); +set_reset_data( dmac0_s__CSR1, val_dmac0_s__CSR1); +set_reset_data( dmac0_s__CPC1, val_dmac0_s__CPC1); +set_reset_data( dmac0_s__CSR2, val_dmac0_s__CSR2); +set_reset_data( dmac0_s__CPC2, val_dmac0_s__CPC2); +set_reset_data( dmac0_s__CSR3, val_dmac0_s__CSR3); +set_reset_data( dmac0_s__CPC3, val_dmac0_s__CPC3); +set_reset_data( dmac0_s__CSR4, val_dmac0_s__CSR4); +set_reset_data( dmac0_s__CPC4, val_dmac0_s__CPC4); +set_reset_data( dmac0_s__CSR5, val_dmac0_s__CSR5); +set_reset_data( dmac0_s__CPC5, val_dmac0_s__CPC5); +set_reset_data( dmac0_s__CSR6, val_dmac0_s__CSR6); +set_reset_data( dmac0_s__CPC6, val_dmac0_s__CPC6); +set_reset_data( dmac0_s__CSR7, val_dmac0_s__CSR7); +set_reset_data( dmac0_s__CPC7, val_dmac0_s__CPC7); +set_reset_data( dmac0_s__SAR0, val_dmac0_s__SAR0); +set_reset_data( dmac0_s__DAR0, val_dmac0_s__DAR0); +set_reset_data( dmac0_s__CCR0, val_dmac0_s__CCR0); +set_reset_data( dmac0_s__LC0_0, val_dmac0_s__LC0_0); +set_reset_data( dmac0_s__LC1_0, val_dmac0_s__LC1_0); +set_reset_data( dmac0_s__SAR1, val_dmac0_s__SAR1); +set_reset_data( dmac0_s__DAR1, val_dmac0_s__DAR1); +set_reset_data( dmac0_s__CCR1, val_dmac0_s__CCR1); +set_reset_data( dmac0_s__LC0_1, val_dmac0_s__LC0_1); +set_reset_data( dmac0_s__LC1_1, val_dmac0_s__LC1_1); +set_reset_data( dmac0_s__SAR2, val_dmac0_s__SAR2); +set_reset_data( dmac0_s__DAR2, val_dmac0_s__DAR2); +set_reset_data( dmac0_s__CCR2, val_dmac0_s__CCR2); +set_reset_data( dmac0_s__LC0_2, val_dmac0_s__LC0_2); +set_reset_data( dmac0_s__LC1_2, val_dmac0_s__LC1_2); +set_reset_data( dmac0_s__SAR3, val_dmac0_s__SAR3); +set_reset_data( dmac0_s__DAR3, val_dmac0_s__DAR3); +set_reset_data( dmac0_s__CCR3, val_dmac0_s__CCR3); +set_reset_data( dmac0_s__LC0_3, val_dmac0_s__LC0_3); +set_reset_data( dmac0_s__LC1_3, val_dmac0_s__LC1_3); +set_reset_data( dmac0_s__SAR4, val_dmac0_s__SAR4); +set_reset_data( dmac0_s__DAR4, val_dmac0_s__DAR4); +set_reset_data( dmac0_s__CCR4, val_dmac0_s__CCR4); +set_reset_data( dmac0_s__LC0_4, val_dmac0_s__LC0_4); +set_reset_data( dmac0_s__LC1_4, val_dmac0_s__LC1_4); +set_reset_data( dmac0_s__SAR5, val_dmac0_s__SAR5); +set_reset_data( dmac0_s__DAR5, val_dmac0_s__DAR5); +set_reset_data( dmac0_s__CCR5, val_dmac0_s__CCR5); +set_reset_data( dmac0_s__LC0_5, val_dmac0_s__LC0_5); +set_reset_data( dmac0_s__LC1_5, val_dmac0_s__LC1_5); +set_reset_data( dmac0_s__SAR6, val_dmac0_s__SAR6); +set_reset_data( dmac0_s__DAR6, val_dmac0_s__DAR6); +set_reset_data( dmac0_s__CCR6, val_dmac0_s__CCR6); +set_reset_data( dmac0_s__LC0_6, val_dmac0_s__LC0_6); +set_reset_data( dmac0_s__LC1_6, val_dmac0_s__LC1_6); +set_reset_data( dmac0_s__SAR7, val_dmac0_s__SAR7); +set_reset_data( dmac0_s__DAR7, val_dmac0_s__DAR7); +set_reset_data( dmac0_s__CCR7, val_dmac0_s__CCR7); +set_reset_data( dmac0_s__LC0_7, val_dmac0_s__LC0_7); +set_reset_data( dmac0_s__LC1_7, val_dmac0_s__LC1_7); +set_reset_data( dmac0_s__DBGSTATUS, val_dmac0_s__DBGSTATUS); +set_reset_data( dmac0_s__DBGCMD, val_dmac0_s__DBGCMD); +set_reset_data( dmac0_s__DBGINST0, val_dmac0_s__DBGINST0); +set_reset_data( dmac0_s__DBGINST1, val_dmac0_s__DBGINST1); +set_reset_data( dmac0_s__CR0, val_dmac0_s__CR0); +set_reset_data( dmac0_s__CR1, val_dmac0_s__CR1); +set_reset_data( dmac0_s__CR2, val_dmac0_s__CR2); +set_reset_data( dmac0_s__CR3, val_dmac0_s__CR3); +set_reset_data( dmac0_s__CR4, val_dmac0_s__CR4); +set_reset_data( dmac0_s__CRD, val_dmac0_s__CRD); +set_reset_data( dmac0_s__WD, val_dmac0_s__WD); +set_reset_data( dmac0_s__periph_id_0, val_dmac0_s__periph_id_0); +set_reset_data( dmac0_s__periph_id_1, val_dmac0_s__periph_id_1); +set_reset_data( dmac0_s__periph_id_2, val_dmac0_s__periph_id_2); +set_reset_data( dmac0_s__periph_id_3, val_dmac0_s__periph_id_3); +set_reset_data( dmac0_s__pcell_id_0, val_dmac0_s__pcell_id_0); +set_reset_data( dmac0_s__pcell_id_1, val_dmac0_s__pcell_id_1); +set_reset_data( dmac0_s__pcell_id_2, val_dmac0_s__pcell_id_2); +set_reset_data( dmac0_s__pcell_id_3, val_dmac0_s__pcell_id_3); + +// ************************************************************ +// Module efuse_ctrl efuse_ctrl +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( efuse_ctrl__WR_LOCK, val_efuse_ctrl__WR_LOCK); +set_reset_data( efuse_ctrl__WR_UNLOCK, val_efuse_ctrl__WR_UNLOCK); +set_reset_data( efuse_ctrl__WR_LOCKSTA, val_efuse_ctrl__WR_LOCKSTA); +set_reset_data( efuse_ctrl__CFG, val_efuse_ctrl__CFG); +set_reset_data( efuse_ctrl__STATUS, val_efuse_ctrl__STATUS); +set_reset_data( efuse_ctrl__CONTROL, val_efuse_ctrl__CONTROL); +set_reset_data( efuse_ctrl__PGM_STBW, val_efuse_ctrl__PGM_STBW); +set_reset_data( efuse_ctrl__RD_STBW, val_efuse_ctrl__RD_STBW); + +// ************************************************************ +// Module gem0 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gem0__net_ctrl, val_gem0__net_ctrl); +set_reset_data( gem0__net_cfg, val_gem0__net_cfg); +set_reset_data( gem0__net_status, val_gem0__net_status); +set_reset_data( gem0__user_io, val_gem0__user_io); +set_reset_data( gem0__dma_cfg, val_gem0__dma_cfg); +set_reset_data( gem0__tx_status, val_gem0__tx_status); +set_reset_data( gem0__rx_qbar, val_gem0__rx_qbar); +set_reset_data( gem0__tx_qbar, val_gem0__tx_qbar); +set_reset_data( gem0__rx_status, val_gem0__rx_status); +set_reset_data( gem0__intr_status, val_gem0__intr_status); +set_reset_data( gem0__intr_en, val_gem0__intr_en); +set_reset_data( gem0__intr_dis, val_gem0__intr_dis); +set_reset_data( gem0__intr_mask, val_gem0__intr_mask); +set_reset_data( gem0__phy_maint, val_gem0__phy_maint); +set_reset_data( gem0__rx_pauseq, val_gem0__rx_pauseq); +set_reset_data( gem0__tx_pauseq, val_gem0__tx_pauseq); +set_reset_data( gem0__tx_partial_st_fwd, val_gem0__tx_partial_st_fwd); +set_reset_data( gem0__rx_partial_st_fwd, val_gem0__rx_partial_st_fwd); +set_reset_data( gem0__hash_bot, val_gem0__hash_bot); +set_reset_data( gem0__hash_top, val_gem0__hash_top); +set_reset_data( gem0__spec_addr1_bot, val_gem0__spec_addr1_bot); +set_reset_data( gem0__spec_addr1_top, val_gem0__spec_addr1_top); +set_reset_data( gem0__spec_addr2_bot, val_gem0__spec_addr2_bot); +set_reset_data( gem0__spec_addr2_top, val_gem0__spec_addr2_top); +set_reset_data( gem0__spec_addr3_bot, val_gem0__spec_addr3_bot); +set_reset_data( gem0__spec_addr3_top, val_gem0__spec_addr3_top); +set_reset_data( gem0__spec_addr4_bot, val_gem0__spec_addr4_bot); +set_reset_data( gem0__spec_addr4_top, val_gem0__spec_addr4_top); +set_reset_data( gem0__type_id_match1, val_gem0__type_id_match1); +set_reset_data( gem0__type_id_match2, val_gem0__type_id_match2); +set_reset_data( gem0__type_id_match3, val_gem0__type_id_match3); +set_reset_data( gem0__type_id_match4, val_gem0__type_id_match4); +set_reset_data( gem0__wake_on_lan, val_gem0__wake_on_lan); +set_reset_data( gem0__ipg_stretch, val_gem0__ipg_stretch); +set_reset_data( gem0__stacked_vlan, val_gem0__stacked_vlan); +set_reset_data( gem0__tx_pfc_pause, val_gem0__tx_pfc_pause); +set_reset_data( gem0__spec_addr1_mask_bot, val_gem0__spec_addr1_mask_bot); +set_reset_data( gem0__spec_addr1_mask_top, val_gem0__spec_addr1_mask_top); +set_reset_data( gem0__module_id, val_gem0__module_id); +set_reset_data( gem0__octets_tx_bot, val_gem0__octets_tx_bot); +set_reset_data( gem0__octets_tx_top, val_gem0__octets_tx_top); +set_reset_data( gem0__frames_tx, val_gem0__frames_tx); +set_reset_data( gem0__broadcast_frames_tx, val_gem0__broadcast_frames_tx); +set_reset_data( gem0__multi_frames_tx, val_gem0__multi_frames_tx); +set_reset_data( gem0__pause_frames_tx, val_gem0__pause_frames_tx); +set_reset_data( gem0__frames_64b_tx, val_gem0__frames_64b_tx); +set_reset_data( gem0__frames_65to127b_tx, val_gem0__frames_65to127b_tx); +set_reset_data( gem0__frames_128to255b_tx, val_gem0__frames_128to255b_tx); +set_reset_data( gem0__frames_256to511b_tx, val_gem0__frames_256to511b_tx); +set_reset_data( gem0__frames_512to1023b_tx, val_gem0__frames_512to1023b_tx); +set_reset_data( gem0__frames_1024to1518b_tx, val_gem0__frames_1024to1518b_tx); +set_reset_data( gem0__frames_gt1518b_tx, val_gem0__frames_gt1518b_tx); +set_reset_data( gem0__tx_under_runs, val_gem0__tx_under_runs); +set_reset_data( gem0__single_collisn_frames, val_gem0__single_collisn_frames); +set_reset_data( gem0__multi_collisn_frames, val_gem0__multi_collisn_frames); +set_reset_data( gem0__excessive_collisns, val_gem0__excessive_collisns); +set_reset_data( gem0__late_collisns, val_gem0__late_collisns); +set_reset_data( gem0__deferred_tx_frames, val_gem0__deferred_tx_frames); +set_reset_data( gem0__carrier_sense_errs, val_gem0__carrier_sense_errs); +set_reset_data( gem0__octets_rx_bot, val_gem0__octets_rx_bot); +set_reset_data( gem0__octets_rx_top, val_gem0__octets_rx_top); +set_reset_data( gem0__frames_rx, val_gem0__frames_rx); +set_reset_data( gem0__bdcast_fames_rx, val_gem0__bdcast_fames_rx); +set_reset_data( gem0__multi_frames_rx, val_gem0__multi_frames_rx); +set_reset_data( gem0__pause_rx, val_gem0__pause_rx); +set_reset_data( gem0__frames_64b_rx, val_gem0__frames_64b_rx); +set_reset_data( gem0__frames_65to127b_rx, val_gem0__frames_65to127b_rx); +set_reset_data( gem0__frames_128to255b_rx, val_gem0__frames_128to255b_rx); +set_reset_data( gem0__frames_256to511b_rx, val_gem0__frames_256to511b_rx); +set_reset_data( gem0__frames_512to1023b_rx, val_gem0__frames_512to1023b_rx); +set_reset_data( gem0__frames_1024to1518b_rx, val_gem0__frames_1024to1518b_rx); +set_reset_data( gem0__frames_gt1518b_rx, val_gem0__frames_gt1518b_rx); +set_reset_data( gem0__undersz_rx, val_gem0__undersz_rx); +set_reset_data( gem0__oversz_rx, val_gem0__oversz_rx); +set_reset_data( gem0__jab_rx, val_gem0__jab_rx); +set_reset_data( gem0__fcs_errors, val_gem0__fcs_errors); +set_reset_data( gem0__length_field_errors, val_gem0__length_field_errors); +set_reset_data( gem0__rx_symbol_errors, val_gem0__rx_symbol_errors); +set_reset_data( gem0__align_errors, val_gem0__align_errors); +set_reset_data( gem0__rx_resource_errors, val_gem0__rx_resource_errors); +set_reset_data( gem0__rx_overrun_errors, val_gem0__rx_overrun_errors); +set_reset_data( gem0__ip_hdr_csum_errors, val_gem0__ip_hdr_csum_errors); +set_reset_data( gem0__tcp_csum_errors, val_gem0__tcp_csum_errors); +set_reset_data( gem0__udp_csum_errors, val_gem0__udp_csum_errors); +set_reset_data( gem0__timer_strobe_s, val_gem0__timer_strobe_s); +set_reset_data( gem0__timer_strobe_ns, val_gem0__timer_strobe_ns); +set_reset_data( gem0__timer_s, val_gem0__timer_s); +set_reset_data( gem0__timer_ns, val_gem0__timer_ns); +set_reset_data( gem0__timer_adjust, val_gem0__timer_adjust); +set_reset_data( gem0__timer_incr, val_gem0__timer_incr); +set_reset_data( gem0__ptp_tx_s, val_gem0__ptp_tx_s); +set_reset_data( gem0__ptp_tx_ns, val_gem0__ptp_tx_ns); +set_reset_data( gem0__ptp_rx_s, val_gem0__ptp_rx_s); +set_reset_data( gem0__ptp_rx_ns, val_gem0__ptp_rx_ns); +set_reset_data( gem0__ptp_peer_tx_s, val_gem0__ptp_peer_tx_s); +set_reset_data( gem0__ptp_peer_tx_ns, val_gem0__ptp_peer_tx_ns); +set_reset_data( gem0__ptp_peer_rx_s, val_gem0__ptp_peer_rx_s); +set_reset_data( gem0__ptp_peer_rx_ns, val_gem0__ptp_peer_rx_ns); +set_reset_data( gem0__pcs_ctrl, val_gem0__pcs_ctrl); +set_reset_data( gem0__pcs_status, val_gem0__pcs_status); +set_reset_data( gem0__pcs_upper_phy_id, val_gem0__pcs_upper_phy_id); +set_reset_data( gem0__pcs_lower_phy_id, val_gem0__pcs_lower_phy_id); +set_reset_data( gem0__pcs_autoneg_ad, val_gem0__pcs_autoneg_ad); +set_reset_data( gem0__pcs_autoneg_ability, val_gem0__pcs_autoneg_ability); +set_reset_data( gem0__pcs_autonec_exp, val_gem0__pcs_autonec_exp); +set_reset_data( gem0__pcs_autoneg_next_pg, val_gem0__pcs_autoneg_next_pg); +set_reset_data( gem0__pcs_autoneg_pnext_pg, val_gem0__pcs_autoneg_pnext_pg); +set_reset_data( gem0__pcs_extended_status, val_gem0__pcs_extended_status); +set_reset_data( gem0__design_cfg1, val_gem0__design_cfg1); +set_reset_data( gem0__design_cfg2, val_gem0__design_cfg2); +set_reset_data( gem0__design_cfg3, val_gem0__design_cfg3); +set_reset_data( gem0__design_cfg4, val_gem0__design_cfg4); +set_reset_data( gem0__design_cfg5, val_gem0__design_cfg5); +set_reset_data( gem0__design_cfg6, val_gem0__design_cfg6); +set_reset_data( gem0__design_cfg7, val_gem0__design_cfg7); +set_reset_data( gem0__isr_pq1, val_gem0__isr_pq1); +set_reset_data( gem0__isr_pq2, val_gem0__isr_pq2); +set_reset_data( gem0__isr_pq3, val_gem0__isr_pq3); +set_reset_data( gem0__isr_pq4, val_gem0__isr_pq4); +set_reset_data( gem0__isr_pq5, val_gem0__isr_pq5); +set_reset_data( gem0__isr_pq6, val_gem0__isr_pq6); +set_reset_data( gem0__isr_pq7, val_gem0__isr_pq7); +set_reset_data( gem0__tx_qbar_q1, val_gem0__tx_qbar_q1); +set_reset_data( gem0__tx_qbar_q2, val_gem0__tx_qbar_q2); +set_reset_data( gem0__tx_qbar_q3, val_gem0__tx_qbar_q3); +set_reset_data( gem0__tx_qbar_q4, val_gem0__tx_qbar_q4); +set_reset_data( gem0__tx_qbar_q5, val_gem0__tx_qbar_q5); +set_reset_data( gem0__tx_qbar_q6, val_gem0__tx_qbar_q6); +set_reset_data( gem0__tx_qbar_q7, val_gem0__tx_qbar_q7); +set_reset_data( gem0__rx_qbar_q1, val_gem0__rx_qbar_q1); +set_reset_data( gem0__rx_qbar_q2, val_gem0__rx_qbar_q2); +set_reset_data( gem0__rx_qbar_q3, val_gem0__rx_qbar_q3); +set_reset_data( gem0__rx_qbar_q4, val_gem0__rx_qbar_q4); +set_reset_data( gem0__rx_qbar_q5, val_gem0__rx_qbar_q5); +set_reset_data( gem0__rx_qbar_q6, val_gem0__rx_qbar_q6); +set_reset_data( gem0__rx_qbar_q7, val_gem0__rx_qbar_q7); +set_reset_data( gem0__rx_bufsz_q1, val_gem0__rx_bufsz_q1); +set_reset_data( gem0__rx_bufsz_q2, val_gem0__rx_bufsz_q2); +set_reset_data( gem0__rx_bufsz_q3, val_gem0__rx_bufsz_q3); +set_reset_data( gem0__rx_bufsz_q4, val_gem0__rx_bufsz_q4); +set_reset_data( gem0__rx_bufsz_q5, val_gem0__rx_bufsz_q5); +set_reset_data( gem0__rx_bufsz_q6, val_gem0__rx_bufsz_q6); +set_reset_data( gem0__rx_bufsz_q7, val_gem0__rx_bufsz_q7); +set_reset_data( gem0__screen_t1_r0, val_gem0__screen_t1_r0); +set_reset_data( gem0__screen_t1_r1, val_gem0__screen_t1_r1); +set_reset_data( gem0__screen_t1_r2, val_gem0__screen_t1_r2); +set_reset_data( gem0__screen_t1_r3, val_gem0__screen_t1_r3); +set_reset_data( gem0__screen_t1_r4, val_gem0__screen_t1_r4); +set_reset_data( gem0__screen_t1_r5, val_gem0__screen_t1_r5); +set_reset_data( gem0__screen_t1_r6, val_gem0__screen_t1_r6); +set_reset_data( gem0__screen_t1_r7, val_gem0__screen_t1_r7); +set_reset_data( gem0__screen_t1_r8, val_gem0__screen_t1_r8); +set_reset_data( gem0__screen_t1_r9, val_gem0__screen_t1_r9); +set_reset_data( gem0__screen_t1_r10, val_gem0__screen_t1_r10); +set_reset_data( gem0__screen_t1_r11, val_gem0__screen_t1_r11); +set_reset_data( gem0__screen_t1_r12, val_gem0__screen_t1_r12); +set_reset_data( gem0__screen_t1_r13, val_gem0__screen_t1_r13); +set_reset_data( gem0__screen_t1_r14, val_gem0__screen_t1_r14); +set_reset_data( gem0__screen_t1_r15, val_gem0__screen_t1_r15); +set_reset_data( gem0__screen_t2_r0, val_gem0__screen_t2_r0); +set_reset_data( gem0__screen_t2_r1, val_gem0__screen_t2_r1); +set_reset_data( gem0__screen_t2_r2, val_gem0__screen_t2_r2); +set_reset_data( gem0__screen_t2_r3, val_gem0__screen_t2_r3); +set_reset_data( gem0__screen_t2_r4, val_gem0__screen_t2_r4); +set_reset_data( gem0__screen_t2_r5, val_gem0__screen_t2_r5); +set_reset_data( gem0__screen_t2_r6, val_gem0__screen_t2_r6); +set_reset_data( gem0__screen_t2_r7, val_gem0__screen_t2_r7); +set_reset_data( gem0__screen_t2_r8, val_gem0__screen_t2_r8); +set_reset_data( gem0__screen_t2_r9, val_gem0__screen_t2_r9); +set_reset_data( gem0__screen_t2_r10, val_gem0__screen_t2_r10); +set_reset_data( gem0__screen_t2_r11, val_gem0__screen_t2_r11); +set_reset_data( gem0__screen_t2_r12, val_gem0__screen_t2_r12); +set_reset_data( gem0__screen_t2_r13, val_gem0__screen_t2_r13); +set_reset_data( gem0__screen_t2_r14, val_gem0__screen_t2_r14); +set_reset_data( gem0__screen_t2_r15, val_gem0__screen_t2_r15); +set_reset_data( gem0__intr_en_pq1, val_gem0__intr_en_pq1); +set_reset_data( gem0__intr_en_pq2, val_gem0__intr_en_pq2); +set_reset_data( gem0__intr_en_pq3, val_gem0__intr_en_pq3); +set_reset_data( gem0__intr_en_pq4, val_gem0__intr_en_pq4); +set_reset_data( gem0__intr_en_pq5, val_gem0__intr_en_pq5); +set_reset_data( gem0__intr_en_pq6, val_gem0__intr_en_pq6); +set_reset_data( gem0__intr_en_pq7, val_gem0__intr_en_pq7); +set_reset_data( gem0__intr_dis_pq1, val_gem0__intr_dis_pq1); +set_reset_data( gem0__intr_dis_pq2, val_gem0__intr_dis_pq2); +set_reset_data( gem0__intr_dis_pq3, val_gem0__intr_dis_pq3); +set_reset_data( gem0__intr_dis_pq4, val_gem0__intr_dis_pq4); +set_reset_data( gem0__intr_dis_pq5, val_gem0__intr_dis_pq5); +set_reset_data( gem0__intr_dis_pq6, val_gem0__intr_dis_pq6); +set_reset_data( gem0__intr_dis_pq7, val_gem0__intr_dis_pq7); +set_reset_data( gem0__intr_mask_pq1, val_gem0__intr_mask_pq1); +set_reset_data( gem0__intr_mask_pq2, val_gem0__intr_mask_pq2); +set_reset_data( gem0__intr_mask_pq3, val_gem0__intr_mask_pq3); +set_reset_data( gem0__intr_mask_pq4, val_gem0__intr_mask_pq4); +set_reset_data( gem0__intr_mask_pq5, val_gem0__intr_mask_pq5); +set_reset_data( gem0__intr_mask_pq6, val_gem0__intr_mask_pq6); +set_reset_data( gem0__intr_mask_pq7, val_gem0__intr_mask_pq7); + +// ************************************************************ +// Module gem1 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gem1__net_ctrl, val_gem1__net_ctrl); +set_reset_data( gem1__net_cfg, val_gem1__net_cfg); +set_reset_data( gem1__net_status, val_gem1__net_status); +set_reset_data( gem1__user_io, val_gem1__user_io); +set_reset_data( gem1__dma_cfg, val_gem1__dma_cfg); +set_reset_data( gem1__tx_status, val_gem1__tx_status); +set_reset_data( gem1__rx_qbar, val_gem1__rx_qbar); +set_reset_data( gem1__tx_qbar, val_gem1__tx_qbar); +set_reset_data( gem1__rx_status, val_gem1__rx_status); +set_reset_data( gem1__intr_status, val_gem1__intr_status); +set_reset_data( gem1__intr_en, val_gem1__intr_en); +set_reset_data( gem1__intr_dis, val_gem1__intr_dis); +set_reset_data( gem1__intr_mask, val_gem1__intr_mask); +set_reset_data( gem1__phy_maint, val_gem1__phy_maint); +set_reset_data( gem1__rx_pauseq, val_gem1__rx_pauseq); +set_reset_data( gem1__tx_pauseq, val_gem1__tx_pauseq); +set_reset_data( gem1__tx_partial_st_fwd, val_gem1__tx_partial_st_fwd); +set_reset_data( gem1__rx_partial_st_fwd, val_gem1__rx_partial_st_fwd); +set_reset_data( gem1__hash_bot, val_gem1__hash_bot); +set_reset_data( gem1__hash_top, val_gem1__hash_top); +set_reset_data( gem1__spec_addr1_bot, val_gem1__spec_addr1_bot); +set_reset_data( gem1__spec_addr1_top, val_gem1__spec_addr1_top); +set_reset_data( gem1__spec_addr2_bot, val_gem1__spec_addr2_bot); +set_reset_data( gem1__spec_addr2_top, val_gem1__spec_addr2_top); +set_reset_data( gem1__spec_addr3_bot, val_gem1__spec_addr3_bot); +set_reset_data( gem1__spec_addr3_top, val_gem1__spec_addr3_top); +set_reset_data( gem1__spec_addr4_bot, val_gem1__spec_addr4_bot); +set_reset_data( gem1__spec_addr4_top, val_gem1__spec_addr4_top); +set_reset_data( gem1__type_id_match1, val_gem1__type_id_match1); +set_reset_data( gem1__type_id_match2, val_gem1__type_id_match2); +set_reset_data( gem1__type_id_match3, val_gem1__type_id_match3); +set_reset_data( gem1__type_id_match4, val_gem1__type_id_match4); +set_reset_data( gem1__wake_on_lan, val_gem1__wake_on_lan); +set_reset_data( gem1__ipg_stretch, val_gem1__ipg_stretch); +set_reset_data( gem1__stacked_vlan, val_gem1__stacked_vlan); +set_reset_data( gem1__tx_pfc_pause, val_gem1__tx_pfc_pause); +set_reset_data( gem1__spec_addr1_mask_bot, val_gem1__spec_addr1_mask_bot); +set_reset_data( gem1__spec_addr1_mask_top, val_gem1__spec_addr1_mask_top); +set_reset_data( gem1__module_id, val_gem1__module_id); +set_reset_data( gem1__octets_tx_bot, val_gem1__octets_tx_bot); +set_reset_data( gem1__octets_tx_top, val_gem1__octets_tx_top); +set_reset_data( gem1__frames_tx, val_gem1__frames_tx); +set_reset_data( gem1__broadcast_frames_tx, val_gem1__broadcast_frames_tx); +set_reset_data( gem1__multi_frames_tx, val_gem1__multi_frames_tx); +set_reset_data( gem1__pause_frames_tx, val_gem1__pause_frames_tx); +set_reset_data( gem1__frames_64b_tx, val_gem1__frames_64b_tx); +set_reset_data( gem1__frames_65to127b_tx, val_gem1__frames_65to127b_tx); +set_reset_data( gem1__frames_128to255b_tx, val_gem1__frames_128to255b_tx); +set_reset_data( gem1__frames_256to511b_tx, val_gem1__frames_256to511b_tx); +set_reset_data( gem1__frames_512to1023b_tx, val_gem1__frames_512to1023b_tx); +set_reset_data( gem1__frames_1024to1518b_tx, val_gem1__frames_1024to1518b_tx); +set_reset_data( gem1__frames_gt1518b_tx, val_gem1__frames_gt1518b_tx); +set_reset_data( gem1__tx_under_runs, val_gem1__tx_under_runs); +set_reset_data( gem1__single_collisn_frames, val_gem1__single_collisn_frames); +set_reset_data( gem1__multi_collisn_frames, val_gem1__multi_collisn_frames); +set_reset_data( gem1__excessive_collisns, val_gem1__excessive_collisns); +set_reset_data( gem1__late_collisns, val_gem1__late_collisns); +set_reset_data( gem1__deferred_tx_frames, val_gem1__deferred_tx_frames); +set_reset_data( gem1__carrier_sense_errs, val_gem1__carrier_sense_errs); +set_reset_data( gem1__octets_rx_bot, val_gem1__octets_rx_bot); +set_reset_data( gem1__octets_rx_top, val_gem1__octets_rx_top); +set_reset_data( gem1__frames_rx, val_gem1__frames_rx); +set_reset_data( gem1__bdcast_fames_rx, val_gem1__bdcast_fames_rx); +set_reset_data( gem1__multi_frames_rx, val_gem1__multi_frames_rx); +set_reset_data( gem1__pause_rx, val_gem1__pause_rx); +set_reset_data( gem1__frames_64b_rx, val_gem1__frames_64b_rx); +set_reset_data( gem1__frames_65to127b_rx, val_gem1__frames_65to127b_rx); +set_reset_data( gem1__frames_128to255b_rx, val_gem1__frames_128to255b_rx); +set_reset_data( gem1__frames_256to511b_rx, val_gem1__frames_256to511b_rx); +set_reset_data( gem1__frames_512to1023b_rx, val_gem1__frames_512to1023b_rx); +set_reset_data( gem1__frames_1024to1518b_rx, val_gem1__frames_1024to1518b_rx); +set_reset_data( gem1__frames_gt1518b_rx, val_gem1__frames_gt1518b_rx); +set_reset_data( gem1__undersz_rx, val_gem1__undersz_rx); +set_reset_data( gem1__oversz_rx, val_gem1__oversz_rx); +set_reset_data( gem1__jab_rx, val_gem1__jab_rx); +set_reset_data( gem1__fcs_errors, val_gem1__fcs_errors); +set_reset_data( gem1__length_field_errors, val_gem1__length_field_errors); +set_reset_data( gem1__rx_symbol_errors, val_gem1__rx_symbol_errors); +set_reset_data( gem1__align_errors, val_gem1__align_errors); +set_reset_data( gem1__rx_resource_errors, val_gem1__rx_resource_errors); +set_reset_data( gem1__rx_overrun_errors, val_gem1__rx_overrun_errors); +set_reset_data( gem1__ip_hdr_csum_errors, val_gem1__ip_hdr_csum_errors); +set_reset_data( gem1__tcp_csum_errors, val_gem1__tcp_csum_errors); +set_reset_data( gem1__udp_csum_errors, val_gem1__udp_csum_errors); +set_reset_data( gem1__timer_strobe_s, val_gem1__timer_strobe_s); +set_reset_data( gem1__timer_strobe_ns, val_gem1__timer_strobe_ns); +set_reset_data( gem1__timer_s, val_gem1__timer_s); +set_reset_data( gem1__timer_ns, val_gem1__timer_ns); +set_reset_data( gem1__timer_adjust, val_gem1__timer_adjust); +set_reset_data( gem1__timer_incr, val_gem1__timer_incr); +set_reset_data( gem1__ptp_tx_s, val_gem1__ptp_tx_s); +set_reset_data( gem1__ptp_tx_ns, val_gem1__ptp_tx_ns); +set_reset_data( gem1__ptp_rx_s, val_gem1__ptp_rx_s); +set_reset_data( gem1__ptp_rx_ns, val_gem1__ptp_rx_ns); +set_reset_data( gem1__ptp_peer_tx_s, val_gem1__ptp_peer_tx_s); +set_reset_data( gem1__ptp_peer_tx_ns, val_gem1__ptp_peer_tx_ns); +set_reset_data( gem1__ptp_peer_rx_s, val_gem1__ptp_peer_rx_s); +set_reset_data( gem1__ptp_peer_rx_ns, val_gem1__ptp_peer_rx_ns); +set_reset_data( gem1__pcs_ctrl, val_gem1__pcs_ctrl); +set_reset_data( gem1__pcs_status, val_gem1__pcs_status); +set_reset_data( gem1__pcs_upper_phy_id, val_gem1__pcs_upper_phy_id); +set_reset_data( gem1__pcs_lower_phy_id, val_gem1__pcs_lower_phy_id); +set_reset_data( gem1__pcs_autoneg_ad, val_gem1__pcs_autoneg_ad); +set_reset_data( gem1__pcs_autoneg_ability, val_gem1__pcs_autoneg_ability); +set_reset_data( gem1__pcs_autonec_exp, val_gem1__pcs_autonec_exp); +set_reset_data( gem1__pcs_autoneg_next_pg, val_gem1__pcs_autoneg_next_pg); +set_reset_data( gem1__pcs_autoneg_pnext_pg, val_gem1__pcs_autoneg_pnext_pg); +set_reset_data( gem1__pcs_extended_status, val_gem1__pcs_extended_status); +set_reset_data( gem1__design_cfg1, val_gem1__design_cfg1); +set_reset_data( gem1__design_cfg2, val_gem1__design_cfg2); +set_reset_data( gem1__design_cfg3, val_gem1__design_cfg3); +set_reset_data( gem1__design_cfg4, val_gem1__design_cfg4); +set_reset_data( gem1__design_cfg5, val_gem1__design_cfg5); +set_reset_data( gem1__design_cfg6, val_gem1__design_cfg6); +set_reset_data( gem1__design_cfg7, val_gem1__design_cfg7); +set_reset_data( gem1__isr_pq1, val_gem1__isr_pq1); +set_reset_data( gem1__isr_pq2, val_gem1__isr_pq2); +set_reset_data( gem1__isr_pq3, val_gem1__isr_pq3); +set_reset_data( gem1__isr_pq4, val_gem1__isr_pq4); +set_reset_data( gem1__isr_pq5, val_gem1__isr_pq5); +set_reset_data( gem1__isr_pq6, val_gem1__isr_pq6); +set_reset_data( gem1__isr_pq7, val_gem1__isr_pq7); +set_reset_data( gem1__tx_qbar_q1, val_gem1__tx_qbar_q1); +set_reset_data( gem1__tx_qbar_q2, val_gem1__tx_qbar_q2); +set_reset_data( gem1__tx_qbar_q3, val_gem1__tx_qbar_q3); +set_reset_data( gem1__tx_qbar_q4, val_gem1__tx_qbar_q4); +set_reset_data( gem1__tx_qbar_q5, val_gem1__tx_qbar_q5); +set_reset_data( gem1__tx_qbar_q6, val_gem1__tx_qbar_q6); +set_reset_data( gem1__tx_qbar_q7, val_gem1__tx_qbar_q7); +set_reset_data( gem1__rx_qbar_q1, val_gem1__rx_qbar_q1); +set_reset_data( gem1__rx_qbar_q2, val_gem1__rx_qbar_q2); +set_reset_data( gem1__rx_qbar_q3, val_gem1__rx_qbar_q3); +set_reset_data( gem1__rx_qbar_q4, val_gem1__rx_qbar_q4); +set_reset_data( gem1__rx_qbar_q5, val_gem1__rx_qbar_q5); +set_reset_data( gem1__rx_qbar_q6, val_gem1__rx_qbar_q6); +set_reset_data( gem1__rx_qbar_q7, val_gem1__rx_qbar_q7); +set_reset_data( gem1__rx_bufsz_q1, val_gem1__rx_bufsz_q1); +set_reset_data( gem1__rx_bufsz_q2, val_gem1__rx_bufsz_q2); +set_reset_data( gem1__rx_bufsz_q3, val_gem1__rx_bufsz_q3); +set_reset_data( gem1__rx_bufsz_q4, val_gem1__rx_bufsz_q4); +set_reset_data( gem1__rx_bufsz_q5, val_gem1__rx_bufsz_q5); +set_reset_data( gem1__rx_bufsz_q6, val_gem1__rx_bufsz_q6); +set_reset_data( gem1__rx_bufsz_q7, val_gem1__rx_bufsz_q7); +set_reset_data( gem1__screen_t1_r0, val_gem1__screen_t1_r0); +set_reset_data( gem1__screen_t1_r1, val_gem1__screen_t1_r1); +set_reset_data( gem1__screen_t1_r2, val_gem1__screen_t1_r2); +set_reset_data( gem1__screen_t1_r3, val_gem1__screen_t1_r3); +set_reset_data( gem1__screen_t1_r4, val_gem1__screen_t1_r4); +set_reset_data( gem1__screen_t1_r5, val_gem1__screen_t1_r5); +set_reset_data( gem1__screen_t1_r6, val_gem1__screen_t1_r6); +set_reset_data( gem1__screen_t1_r7, val_gem1__screen_t1_r7); +set_reset_data( gem1__screen_t1_r8, val_gem1__screen_t1_r8); +set_reset_data( gem1__screen_t1_r9, val_gem1__screen_t1_r9); +set_reset_data( gem1__screen_t1_r10, val_gem1__screen_t1_r10); +set_reset_data( gem1__screen_t1_r11, val_gem1__screen_t1_r11); +set_reset_data( gem1__screen_t1_r12, val_gem1__screen_t1_r12); +set_reset_data( gem1__screen_t1_r13, val_gem1__screen_t1_r13); +set_reset_data( gem1__screen_t1_r14, val_gem1__screen_t1_r14); +set_reset_data( gem1__screen_t1_r15, val_gem1__screen_t1_r15); +set_reset_data( gem1__screen_t2_r0, val_gem1__screen_t2_r0); +set_reset_data( gem1__screen_t2_r1, val_gem1__screen_t2_r1); +set_reset_data( gem1__screen_t2_r2, val_gem1__screen_t2_r2); +set_reset_data( gem1__screen_t2_r3, val_gem1__screen_t2_r3); +set_reset_data( gem1__screen_t2_r4, val_gem1__screen_t2_r4); +set_reset_data( gem1__screen_t2_r5, val_gem1__screen_t2_r5); +set_reset_data( gem1__screen_t2_r6, val_gem1__screen_t2_r6); +set_reset_data( gem1__screen_t2_r7, val_gem1__screen_t2_r7); +set_reset_data( gem1__screen_t2_r8, val_gem1__screen_t2_r8); +set_reset_data( gem1__screen_t2_r9, val_gem1__screen_t2_r9); +set_reset_data( gem1__screen_t2_r10, val_gem1__screen_t2_r10); +set_reset_data( gem1__screen_t2_r11, val_gem1__screen_t2_r11); +set_reset_data( gem1__screen_t2_r12, val_gem1__screen_t2_r12); +set_reset_data( gem1__screen_t2_r13, val_gem1__screen_t2_r13); +set_reset_data( gem1__screen_t2_r14, val_gem1__screen_t2_r14); +set_reset_data( gem1__screen_t2_r15, val_gem1__screen_t2_r15); +set_reset_data( gem1__intr_en_pq1, val_gem1__intr_en_pq1); +set_reset_data( gem1__intr_en_pq2, val_gem1__intr_en_pq2); +set_reset_data( gem1__intr_en_pq3, val_gem1__intr_en_pq3); +set_reset_data( gem1__intr_en_pq4, val_gem1__intr_en_pq4); +set_reset_data( gem1__intr_en_pq5, val_gem1__intr_en_pq5); +set_reset_data( gem1__intr_en_pq6, val_gem1__intr_en_pq6); +set_reset_data( gem1__intr_en_pq7, val_gem1__intr_en_pq7); +set_reset_data( gem1__intr_dis_pq1, val_gem1__intr_dis_pq1); +set_reset_data( gem1__intr_dis_pq2, val_gem1__intr_dis_pq2); +set_reset_data( gem1__intr_dis_pq3, val_gem1__intr_dis_pq3); +set_reset_data( gem1__intr_dis_pq4, val_gem1__intr_dis_pq4); +set_reset_data( gem1__intr_dis_pq5, val_gem1__intr_dis_pq5); +set_reset_data( gem1__intr_dis_pq6, val_gem1__intr_dis_pq6); +set_reset_data( gem1__intr_dis_pq7, val_gem1__intr_dis_pq7); +set_reset_data( gem1__intr_mask_pq1, val_gem1__intr_mask_pq1); +set_reset_data( gem1__intr_mask_pq2, val_gem1__intr_mask_pq2); +set_reset_data( gem1__intr_mask_pq3, val_gem1__intr_mask_pq3); +set_reset_data( gem1__intr_mask_pq4, val_gem1__intr_mask_pq4); +set_reset_data( gem1__intr_mask_pq5, val_gem1__intr_mask_pq5); +set_reset_data( gem1__intr_mask_pq6, val_gem1__intr_mask_pq6); +set_reset_data( gem1__intr_mask_pq7, val_gem1__intr_mask_pq7); + +// ************************************************************ +// Module gpio gpio +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpio__MASK_DATA_0_LSW, val_gpio__MASK_DATA_0_LSW); +set_reset_data( gpio__MASK_DATA_0_MSW, val_gpio__MASK_DATA_0_MSW); +set_reset_data( gpio__MASK_DATA_1_LSW, val_gpio__MASK_DATA_1_LSW); +set_reset_data( gpio__MASK_DATA_1_MSW, val_gpio__MASK_DATA_1_MSW); +set_reset_data( gpio__MASK_DATA_2_LSW, val_gpio__MASK_DATA_2_LSW); +set_reset_data( gpio__MASK_DATA_2_MSW, val_gpio__MASK_DATA_2_MSW); +set_reset_data( gpio__MASK_DATA_3_LSW, val_gpio__MASK_DATA_3_LSW); +set_reset_data( gpio__MASK_DATA_3_MSW, val_gpio__MASK_DATA_3_MSW); +set_reset_data( gpio__DATA_0, val_gpio__DATA_0); +set_reset_data( gpio__DATA_1, val_gpio__DATA_1); +set_reset_data( gpio__DATA_2, val_gpio__DATA_2); +set_reset_data( gpio__DATA_3, val_gpio__DATA_3); +set_reset_data( gpio__DATA_0_RO, val_gpio__DATA_0_RO); +set_reset_data( gpio__DATA_1_RO, val_gpio__DATA_1_RO); +set_reset_data( gpio__DATA_2_RO, val_gpio__DATA_2_RO); +set_reset_data( gpio__DATA_3_RO, val_gpio__DATA_3_RO); +set_reset_data( gpio__BYPM_0, val_gpio__BYPM_0); +set_reset_data( gpio__DIRM_0, val_gpio__DIRM_0); +set_reset_data( gpio__OEN_0, val_gpio__OEN_0); +set_reset_data( gpio__INT_MASK_0, val_gpio__INT_MASK_0); +set_reset_data( gpio__INT_EN_0, val_gpio__INT_EN_0); +set_reset_data( gpio__INT_DIS_0, val_gpio__INT_DIS_0); +set_reset_data( gpio__INT_STAT_0, val_gpio__INT_STAT_0); +set_reset_data( gpio__INT_TYPE_0, val_gpio__INT_TYPE_0); +set_reset_data( gpio__INT_POLARITY_0, val_gpio__INT_POLARITY_0); +set_reset_data( gpio__INT_ANY_0, val_gpio__INT_ANY_0); +set_reset_data( gpio__BYPM_1, val_gpio__BYPM_1); +set_reset_data( gpio__DIRM_1, val_gpio__DIRM_1); +set_reset_data( gpio__OEN_1, val_gpio__OEN_1); +set_reset_data( gpio__INT_MASK_1, val_gpio__INT_MASK_1); +set_reset_data( gpio__INT_EN_1, val_gpio__INT_EN_1); +set_reset_data( gpio__INT_DIS_1, val_gpio__INT_DIS_1); +set_reset_data( gpio__INT_STAT_1, val_gpio__INT_STAT_1); +set_reset_data( gpio__INT_TYPE_1, val_gpio__INT_TYPE_1); +set_reset_data( gpio__INT_POLARITY_1, val_gpio__INT_POLARITY_1); +set_reset_data( gpio__INT_ANY_1, val_gpio__INT_ANY_1); +set_reset_data( gpio__BYPM_2, val_gpio__BYPM_2); +set_reset_data( gpio__DIRM_2, val_gpio__DIRM_2); +set_reset_data( gpio__OEN_2, val_gpio__OEN_2); +set_reset_data( gpio__INT_MASK_2, val_gpio__INT_MASK_2); +set_reset_data( gpio__INT_EN_2, val_gpio__INT_EN_2); +set_reset_data( gpio__INT_DIS_2, val_gpio__INT_DIS_2); +set_reset_data( gpio__INT_STAT_2, val_gpio__INT_STAT_2); +set_reset_data( gpio__INT_TYPE_2, val_gpio__INT_TYPE_2); +set_reset_data( gpio__INT_POLARITY_2, val_gpio__INT_POLARITY_2); +set_reset_data( gpio__INT_ANY_2, val_gpio__INT_ANY_2); +set_reset_data( gpio__BYPM_3, val_gpio__BYPM_3); +set_reset_data( gpio__DIRM_3, val_gpio__DIRM_3); +set_reset_data( gpio__OEN_3, val_gpio__OEN_3); +set_reset_data( gpio__INT_MASK_3, val_gpio__INT_MASK_3); +set_reset_data( gpio__INT_EN_3, val_gpio__INT_EN_3); +set_reset_data( gpio__INT_DIS_3, val_gpio__INT_DIS_3); +set_reset_data( gpio__INT_STAT_3, val_gpio__INT_STAT_3); +set_reset_data( gpio__INT_TYPE_3, val_gpio__INT_TYPE_3); +set_reset_data( gpio__INT_POLARITY_3, val_gpio__INT_POLARITY_3); +set_reset_data( gpio__INT_ANY_3, val_gpio__INT_ANY_3); + +// ************************************************************ +// Module gpv_iou_switch gpv_iou_switch +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_iou_switch__Remap, val_gpv_iou_switch__Remap); +set_reset_data( gpv_iou_switch__security2_sdio0, val_gpv_iou_switch__security2_sdio0); +set_reset_data( gpv_iou_switch__security3_sdio1, val_gpv_iou_switch__security3_sdio1); +set_reset_data( gpv_iou_switch__security4_qspi, val_gpv_iou_switch__security4_qspi); +set_reset_data( gpv_iou_switch__security5_miou, val_gpv_iou_switch__security5_miou); +set_reset_data( gpv_iou_switch__security6_apb_slaves, val_gpv_iou_switch__security6_apb_slaves); +set_reset_data( gpv_iou_switch__security7_smc, val_gpv_iou_switch__security7_smc); +set_reset_data( gpv_iou_switch__peripheral_id4, val_gpv_iou_switch__peripheral_id4); +set_reset_data( gpv_iou_switch__peripheral_id5, val_gpv_iou_switch__peripheral_id5); +set_reset_data( gpv_iou_switch__peripheral_id6, val_gpv_iou_switch__peripheral_id6); +set_reset_data( gpv_iou_switch__peripheral_id7, val_gpv_iou_switch__peripheral_id7); +set_reset_data( gpv_iou_switch__peripheral_id0, val_gpv_iou_switch__peripheral_id0); +set_reset_data( gpv_iou_switch__peripheral_id1, val_gpv_iou_switch__peripheral_id1); +set_reset_data( gpv_iou_switch__peripheral_id2, val_gpv_iou_switch__peripheral_id2); +set_reset_data( gpv_iou_switch__peripheral_id3, val_gpv_iou_switch__peripheral_id3); +set_reset_data( gpv_iou_switch__component_id0, val_gpv_iou_switch__component_id0); +set_reset_data( gpv_iou_switch__component_id1, val_gpv_iou_switch__component_id1); +set_reset_data( gpv_iou_switch__component_id2, val_gpv_iou_switch__component_id2); +set_reset_data( gpv_iou_switch__component_id3, val_gpv_iou_switch__component_id3); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio0, val_gpv_iou_switch__fn_mod_bm_iss_sdio0); +set_reset_data( gpv_iou_switch__ahb_cntl_sdio0, val_gpv_iou_switch__ahb_cntl_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_sdio1, val_gpv_iou_switch__fn_mod_bm_iss_sdio1); +set_reset_data( gpv_iou_switch__ahb_cntl_sdio1, val_gpv_iou_switch__ahb_cntl_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_qspi, val_gpv_iou_switch__fn_mod_bm_iss_qspi); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_miou, val_gpv_iou_switch__fn_mod_bm_iss_miou); +set_reset_data( gpv_iou_switch__fn_mod_bm_iss_smc, val_gpv_iou_switch__fn_mod_bm_iss_smc); +set_reset_data( gpv_iou_switch__fn_mod_ahb_gem0, val_gpv_iou_switch__fn_mod_ahb_gem0); +set_reset_data( gpv_iou_switch__read_qos_gem0, val_gpv_iou_switch__read_qos_gem0); +set_reset_data( gpv_iou_switch__write_qos_gem0, val_gpv_iou_switch__write_qos_gem0); +set_reset_data( gpv_iou_switch__fn_mod_iss_gem0, val_gpv_iou_switch__fn_mod_iss_gem0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_gem1, val_gpv_iou_switch__fn_mod_ahb_gem1); +set_reset_data( gpv_iou_switch__read_qos_gem1, val_gpv_iou_switch__read_qos_gem1); +set_reset_data( gpv_iou_switch__write_qos_gem1, val_gpv_iou_switch__write_qos_gem1); +set_reset_data( gpv_iou_switch__fn_mod_iss_gem1, val_gpv_iou_switch__fn_mod_iss_gem1); +set_reset_data( gpv_iou_switch__fn_mod_ahb_usb0, val_gpv_iou_switch__fn_mod_ahb_usb0); +set_reset_data( gpv_iou_switch__read_qos_usb0, val_gpv_iou_switch__read_qos_usb0); +set_reset_data( gpv_iou_switch__write_qos_usb0, val_gpv_iou_switch__write_qos_usb0); +set_reset_data( gpv_iou_switch__fn_mod_iss_usb0, val_gpv_iou_switch__fn_mod_iss_usb0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_usb1, val_gpv_iou_switch__fn_mod_ahb_usb1); +set_reset_data( gpv_iou_switch__read_qos_usb1, val_gpv_iou_switch__read_qos_usb1); +set_reset_data( gpv_iou_switch__write_qos_usb1, val_gpv_iou_switch__write_qos_usb1); +set_reset_data( gpv_iou_switch__fn_mod_iss_usb1, val_gpv_iou_switch__fn_mod_iss_usb1); +set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio0, val_gpv_iou_switch__fn_mod_ahb_sdio0); +set_reset_data( gpv_iou_switch__read_qos_sdio0, val_gpv_iou_switch__read_qos_sdio0); +set_reset_data( gpv_iou_switch__write_qos_sdio0, val_gpv_iou_switch__write_qos_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_iss_sdio0, val_gpv_iou_switch__fn_mod_iss_sdio0); +set_reset_data( gpv_iou_switch__fn_mod_ahb_sdio1, val_gpv_iou_switch__fn_mod_ahb_sdio1); +set_reset_data( gpv_iou_switch__read_qos_sdio1, val_gpv_iou_switch__read_qos_sdio1); +set_reset_data( gpv_iou_switch__write_qos_sdio1, val_gpv_iou_switch__write_qos_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_iss_sdio1, val_gpv_iou_switch__fn_mod_iss_sdio1); +set_reset_data( gpv_iou_switch__fn_mod_iss_siou, val_gpv_iou_switch__fn_mod_iss_siou); + +// ************************************************************ +// Module gpv_qos301_cpu qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_cpu__qos_cntl, val_gpv_qos301_cpu__qos_cntl); +set_reset_data( gpv_qos301_cpu__max_ot, val_gpv_qos301_cpu__max_ot); +set_reset_data( gpv_qos301_cpu__max_comb_ot, val_gpv_qos301_cpu__max_comb_ot); +set_reset_data( gpv_qos301_cpu__aw_p, val_gpv_qos301_cpu__aw_p); +set_reset_data( gpv_qos301_cpu__aw_b, val_gpv_qos301_cpu__aw_b); +set_reset_data( gpv_qos301_cpu__aw_r, val_gpv_qos301_cpu__aw_r); +set_reset_data( gpv_qos301_cpu__ar_p, val_gpv_qos301_cpu__ar_p); +set_reset_data( gpv_qos301_cpu__ar_b, val_gpv_qos301_cpu__ar_b); +set_reset_data( gpv_qos301_cpu__ar_r, val_gpv_qos301_cpu__ar_r); + +// ************************************************************ +// Module gpv_qos301_dmac qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_dmac__qos_cntl, val_gpv_qos301_dmac__qos_cntl); +set_reset_data( gpv_qos301_dmac__max_ot, val_gpv_qos301_dmac__max_ot); +set_reset_data( gpv_qos301_dmac__max_comb_ot, val_gpv_qos301_dmac__max_comb_ot); +set_reset_data( gpv_qos301_dmac__aw_p, val_gpv_qos301_dmac__aw_p); +set_reset_data( gpv_qos301_dmac__aw_b, val_gpv_qos301_dmac__aw_b); +set_reset_data( gpv_qos301_dmac__aw_r, val_gpv_qos301_dmac__aw_r); +set_reset_data( gpv_qos301_dmac__ar_p, val_gpv_qos301_dmac__ar_p); +set_reset_data( gpv_qos301_dmac__ar_b, val_gpv_qos301_dmac__ar_b); +set_reset_data( gpv_qos301_dmac__ar_r, val_gpv_qos301_dmac__ar_r); + +// ************************************************************ +// Module gpv_qos301_iou qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_qos301_iou__qos_cntl, val_gpv_qos301_iou__qos_cntl); +set_reset_data( gpv_qos301_iou__max_ot, val_gpv_qos301_iou__max_ot); +set_reset_data( gpv_qos301_iou__max_comb_ot, val_gpv_qos301_iou__max_comb_ot); +set_reset_data( gpv_qos301_iou__aw_p, val_gpv_qos301_iou__aw_p); +set_reset_data( gpv_qos301_iou__aw_b, val_gpv_qos301_iou__aw_b); +set_reset_data( gpv_qos301_iou__aw_r, val_gpv_qos301_iou__aw_r); +set_reset_data( gpv_qos301_iou__ar_p, val_gpv_qos301_iou__ar_p); +set_reset_data( gpv_qos301_iou__ar_b, val_gpv_qos301_iou__ar_b); +set_reset_data( gpv_qos301_iou__ar_r, val_gpv_qos301_iou__ar_r); + +// ************************************************************ +// Module gpv_trustzone nic301_addr_region_ctrl_registers +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( gpv_trustzone__Remap, val_gpv_trustzone__Remap); +set_reset_data( gpv_trustzone__security_fssw_s0, val_gpv_trustzone__security_fssw_s0); +set_reset_data( gpv_trustzone__security_fssw_s1, val_gpv_trustzone__security_fssw_s1); +set_reset_data( gpv_trustzone__security_apb, val_gpv_trustzone__security_apb); + +// ************************************************************ +// Module i2c0 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( i2c0__Control_reg0, val_i2c0__Control_reg0); +set_reset_data( i2c0__Status_reg0, val_i2c0__Status_reg0); +set_reset_data( i2c0__I2C_address_reg0, val_i2c0__I2C_address_reg0); +set_reset_data( i2c0__I2C_data_reg0, val_i2c0__I2C_data_reg0); +set_reset_data( i2c0__Interrupt_status_reg0, val_i2c0__Interrupt_status_reg0); +set_reset_data( i2c0__Transfer_size_reg0, val_i2c0__Transfer_size_reg0); +set_reset_data( i2c0__Slave_mon_pause_reg0, val_i2c0__Slave_mon_pause_reg0); +set_reset_data( i2c0__Time_out_reg0, val_i2c0__Time_out_reg0); +set_reset_data( i2c0__Intrpt_mask_reg0, val_i2c0__Intrpt_mask_reg0); +set_reset_data( i2c0__Intrpt_enable_reg0, val_i2c0__Intrpt_enable_reg0); +set_reset_data( i2c0__Intrpt_disable_reg0, val_i2c0__Intrpt_disable_reg0); + +// ************************************************************ +// Module i2c1 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( i2c1__Control_reg0, val_i2c1__Control_reg0); +set_reset_data( i2c1__Status_reg0, val_i2c1__Status_reg0); +set_reset_data( i2c1__I2C_address_reg0, val_i2c1__I2C_address_reg0); +set_reset_data( i2c1__I2C_data_reg0, val_i2c1__I2C_data_reg0); +set_reset_data( i2c1__Interrupt_status_reg0, val_i2c1__Interrupt_status_reg0); +set_reset_data( i2c1__Transfer_size_reg0, val_i2c1__Transfer_size_reg0); +set_reset_data( i2c1__Slave_mon_pause_reg0, val_i2c1__Slave_mon_pause_reg0); +set_reset_data( i2c1__Time_out_reg0, val_i2c1__Time_out_reg0); +set_reset_data( i2c1__Intrpt_mask_reg0, val_i2c1__Intrpt_mask_reg0); +set_reset_data( i2c1__Intrpt_enable_reg0, val_i2c1__Intrpt_enable_reg0); +set_reset_data( i2c1__Intrpt_disable_reg0, val_i2c1__Intrpt_disable_reg0); + +// ************************************************************ +// Module l2cache L2Cpl310 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( l2cache__reg0_cache_id, val_l2cache__reg0_cache_id); +set_reset_data( l2cache__reg0_cache_type, val_l2cache__reg0_cache_type); +set_reset_data( l2cache__reg1_control, val_l2cache__reg1_control); +set_reset_data( l2cache__reg1_aux_control, val_l2cache__reg1_aux_control); +set_reset_data( l2cache__reg1_tag_ram_control, val_l2cache__reg1_tag_ram_control); +set_reset_data( l2cache__reg1_data_ram_control, val_l2cache__reg1_data_ram_control); +set_reset_data( l2cache__reg2_ev_counter_ctrl, val_l2cache__reg2_ev_counter_ctrl); +set_reset_data( l2cache__reg2_ev_counter1_cfg, val_l2cache__reg2_ev_counter1_cfg); +set_reset_data( l2cache__reg2_ev_counter0_cfg, val_l2cache__reg2_ev_counter0_cfg); +set_reset_data( l2cache__reg2_ev_counter1, val_l2cache__reg2_ev_counter1); +set_reset_data( l2cache__reg2_ev_counter0, val_l2cache__reg2_ev_counter0); +set_reset_data( l2cache__reg2_int_mask, val_l2cache__reg2_int_mask); +set_reset_data( l2cache__reg2_int_mask_status, val_l2cache__reg2_int_mask_status); +set_reset_data( l2cache__reg2_int_raw_status, val_l2cache__reg2_int_raw_status); +set_reset_data( l2cache__reg2_int_clear, val_l2cache__reg2_int_clear); +set_reset_data( l2cache__reg7_cache_sync, val_l2cache__reg7_cache_sync); +set_reset_data( l2cache__reg7_inv_pa, val_l2cache__reg7_inv_pa); +set_reset_data( l2cache__reg7_inv_way, val_l2cache__reg7_inv_way); +set_reset_data( l2cache__reg7_clean_pa, val_l2cache__reg7_clean_pa); +set_reset_data( l2cache__reg7_clean_index, val_l2cache__reg7_clean_index); +set_reset_data( l2cache__reg7_clean_way, val_l2cache__reg7_clean_way); +set_reset_data( l2cache__reg7_clean_inv_pa, val_l2cache__reg7_clean_inv_pa); +set_reset_data( l2cache__reg7_clean_inv_index, val_l2cache__reg7_clean_inv_index); +set_reset_data( l2cache__reg7_clean_inv_way, val_l2cache__reg7_clean_inv_way); +set_reset_data( l2cache__reg9_d_lockdown0, val_l2cache__reg9_d_lockdown0); +set_reset_data( l2cache__reg9_i_lockdown0, val_l2cache__reg9_i_lockdown0); +set_reset_data( l2cache__reg9_d_lockdown1, val_l2cache__reg9_d_lockdown1); +set_reset_data( l2cache__reg9_i_lockdown1, val_l2cache__reg9_i_lockdown1); +set_reset_data( l2cache__reg9_d_lockdown2, val_l2cache__reg9_d_lockdown2); +set_reset_data( l2cache__reg9_i_lockdown2, val_l2cache__reg9_i_lockdown2); +set_reset_data( l2cache__reg9_d_lockdown3, val_l2cache__reg9_d_lockdown3); +set_reset_data( l2cache__reg9_i_lockdown3, val_l2cache__reg9_i_lockdown3); +set_reset_data( l2cache__reg9_d_lockdown4, val_l2cache__reg9_d_lockdown4); +set_reset_data( l2cache__reg9_i_lockdown4, val_l2cache__reg9_i_lockdown4); +set_reset_data( l2cache__reg9_d_lockdown5, val_l2cache__reg9_d_lockdown5); +set_reset_data( l2cache__reg9_i_lockdown5, val_l2cache__reg9_i_lockdown5); +set_reset_data( l2cache__reg9_d_lockdown6, val_l2cache__reg9_d_lockdown6); +set_reset_data( l2cache__reg9_i_lockdown6, val_l2cache__reg9_i_lockdown6); +set_reset_data( l2cache__reg9_d_lockdown7, val_l2cache__reg9_d_lockdown7); +set_reset_data( l2cache__reg9_i_lockdown7, val_l2cache__reg9_i_lockdown7); +set_reset_data( l2cache__reg9_lock_line_en, val_l2cache__reg9_lock_line_en); +set_reset_data( l2cache__reg9_unlock_way, val_l2cache__reg9_unlock_way); +set_reset_data( l2cache__reg12_addr_filtering_start, val_l2cache__reg12_addr_filtering_start); +set_reset_data( l2cache__reg12_addr_filtering_end, val_l2cache__reg12_addr_filtering_end); +set_reset_data( l2cache__reg15_debug_ctrl, val_l2cache__reg15_debug_ctrl); +set_reset_data( l2cache__reg15_prefetch_ctrl, val_l2cache__reg15_prefetch_ctrl); +set_reset_data( l2cache__reg15_power_ctrl, val_l2cache__reg15_power_ctrl); + +// ************************************************************ +// Module mpcore mpcore +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( mpcore__SCU_CONTROL_REGISTER, val_mpcore__SCU_CONTROL_REGISTER); +set_reset_data( mpcore__SCU_CONFIGURATION_REGISTER, val_mpcore__SCU_CONFIGURATION_REGISTER); +set_reset_data( mpcore__SCU_CPU_Power_Status_Register, val_mpcore__SCU_CPU_Power_Status_Register); +set_reset_data( mpcore__SCU_Invalidate_All_Registers_in_Secure_State, val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State); +set_reset_data( mpcore__Filtering_Start_Address_Register, val_mpcore__Filtering_Start_Address_Register); +set_reset_data( mpcore__Filtering_End_Address_Register, val_mpcore__Filtering_End_Address_Register); +set_reset_data( mpcore__SCU_Access_Control_Register_SAC, val_mpcore__SCU_Access_Control_Register_SAC); +set_reset_data( mpcore__SCU_Non_secure_Access_Control_Register, val_mpcore__SCU_Non_secure_Access_Control_Register); +set_reset_data( mpcore__ICCICR, val_mpcore__ICCICR); +set_reset_data( mpcore__ICCPMR, val_mpcore__ICCPMR); +set_reset_data( mpcore__ICCBPR, val_mpcore__ICCBPR); +set_reset_data( mpcore__ICCIAR, val_mpcore__ICCIAR); +set_reset_data( mpcore__ICCEOIR, val_mpcore__ICCEOIR); +set_reset_data( mpcore__ICCRPR, val_mpcore__ICCRPR); +set_reset_data( mpcore__ICCHPIR, val_mpcore__ICCHPIR); +set_reset_data( mpcore__ICCABPR, val_mpcore__ICCABPR); +set_reset_data( mpcore__ICCIDR, val_mpcore__ICCIDR); +set_reset_data( mpcore__Global_Timer_Counter_Register0, val_mpcore__Global_Timer_Counter_Register0); +set_reset_data( mpcore__Global_Timer_Counter_Register1, val_mpcore__Global_Timer_Counter_Register1); +set_reset_data( mpcore__Global_Timer_Control_Register, val_mpcore__Global_Timer_Control_Register); +set_reset_data( mpcore__Global_Timer_Interrupt_Status_Register, val_mpcore__Global_Timer_Interrupt_Status_Register); +set_reset_data( mpcore__Comparator_Value_Register0, val_mpcore__Comparator_Value_Register0); +set_reset_data( mpcore__Comparator_Value_Register1, val_mpcore__Comparator_Value_Register1); +set_reset_data( mpcore__Auto_increment_Register, val_mpcore__Auto_increment_Register); +set_reset_data( mpcore__Private_Timer_Load_Register, val_mpcore__Private_Timer_Load_Register); +set_reset_data( mpcore__Private_Timer_Counter_Register, val_mpcore__Private_Timer_Counter_Register); +set_reset_data( mpcore__Private_Timer_Control_Register, val_mpcore__Private_Timer_Control_Register); +set_reset_data( mpcore__Private_Timer_Interrupt_Status_Register, val_mpcore__Private_Timer_Interrupt_Status_Register); +set_reset_data( mpcore__Watchdog_Load_Register, val_mpcore__Watchdog_Load_Register); +set_reset_data( mpcore__Watchdog_Counter_Register, val_mpcore__Watchdog_Counter_Register); +set_reset_data( mpcore__Watchdog_Control_Register, val_mpcore__Watchdog_Control_Register); +set_reset_data( mpcore__Watchdog_Interrupt_Status_Register, val_mpcore__Watchdog_Interrupt_Status_Register); +set_reset_data( mpcore__Watchdog_Reset_Status_Register, val_mpcore__Watchdog_Reset_Status_Register); +set_reset_data( mpcore__Watchdog_Disable_Register, val_mpcore__Watchdog_Disable_Register); +set_reset_data( mpcore__ICDDCR, val_mpcore__ICDDCR); +set_reset_data( mpcore__ICDICTR, val_mpcore__ICDICTR); +set_reset_data( mpcore__ICDIIDR, val_mpcore__ICDIIDR); +set_reset_data( mpcore__ICDISR0, val_mpcore__ICDISR0); +set_reset_data( mpcore__ICDISR1, val_mpcore__ICDISR1); +set_reset_data( mpcore__ICDISR2, val_mpcore__ICDISR2); +set_reset_data( mpcore__ICDISER0, val_mpcore__ICDISER0); +set_reset_data( mpcore__ICDISER1, val_mpcore__ICDISER1); +set_reset_data( mpcore__ICDISER2, val_mpcore__ICDISER2); +set_reset_data( mpcore__ICDICER0, val_mpcore__ICDICER0); +set_reset_data( mpcore__ICDICER1, val_mpcore__ICDICER1); +set_reset_data( mpcore__ICDICER2, val_mpcore__ICDICER2); +set_reset_data( mpcore__ICDISPR0, val_mpcore__ICDISPR0); +set_reset_data( mpcore__ICDISPR1, val_mpcore__ICDISPR1); +set_reset_data( mpcore__ICDISPR2, val_mpcore__ICDISPR2); +set_reset_data( mpcore__ICDICPR0, val_mpcore__ICDICPR0); +set_reset_data( mpcore__ICDICPR1, val_mpcore__ICDICPR1); +set_reset_data( mpcore__ICDICPR2, val_mpcore__ICDICPR2); +set_reset_data( mpcore__ICDABR0, val_mpcore__ICDABR0); +set_reset_data( mpcore__ICDABR1, val_mpcore__ICDABR1); +set_reset_data( mpcore__ICDABR2, val_mpcore__ICDABR2); +set_reset_data( mpcore__ICDIPR0, val_mpcore__ICDIPR0); +set_reset_data( mpcore__ICDIPR1, val_mpcore__ICDIPR1); +set_reset_data( mpcore__ICDIPR2, val_mpcore__ICDIPR2); +set_reset_data( mpcore__ICDIPR3, val_mpcore__ICDIPR3); +set_reset_data( mpcore__ICDIPR4, val_mpcore__ICDIPR4); +set_reset_data( mpcore__ICDIPR5, val_mpcore__ICDIPR5); +set_reset_data( mpcore__ICDIPR6, val_mpcore__ICDIPR6); +set_reset_data( mpcore__ICDIPR7, val_mpcore__ICDIPR7); +set_reset_data( mpcore__ICDIPR8, val_mpcore__ICDIPR8); +set_reset_data( mpcore__ICDIPR9, val_mpcore__ICDIPR9); +set_reset_data( mpcore__ICDIPR10, val_mpcore__ICDIPR10); +set_reset_data( mpcore__ICDIPR11, val_mpcore__ICDIPR11); +set_reset_data( mpcore__ICDIPR12, val_mpcore__ICDIPR12); +set_reset_data( mpcore__ICDIPR13, val_mpcore__ICDIPR13); +set_reset_data( mpcore__ICDIPR14, val_mpcore__ICDIPR14); +set_reset_data( mpcore__ICDIPR15, val_mpcore__ICDIPR15); +set_reset_data( mpcore__ICDIPR16, val_mpcore__ICDIPR16); +set_reset_data( mpcore__ICDIPR17, val_mpcore__ICDIPR17); +set_reset_data( mpcore__ICDIPR18, val_mpcore__ICDIPR18); +set_reset_data( mpcore__ICDIPR19, val_mpcore__ICDIPR19); +set_reset_data( mpcore__ICDIPR20, val_mpcore__ICDIPR20); +set_reset_data( mpcore__ICDIPR21, val_mpcore__ICDIPR21); +set_reset_data( mpcore__ICDIPR22, val_mpcore__ICDIPR22); +set_reset_data( mpcore__ICDIPR23, val_mpcore__ICDIPR23); +set_reset_data( mpcore__ICDIPTR0, val_mpcore__ICDIPTR0); +set_reset_data( mpcore__ICDIPTR1, val_mpcore__ICDIPTR1); +set_reset_data( mpcore__ICDIPTR2, val_mpcore__ICDIPTR2); +set_reset_data( mpcore__ICDIPTR3, val_mpcore__ICDIPTR3); +set_reset_data( mpcore__ICDIPTR4, val_mpcore__ICDIPTR4); +set_reset_data( mpcore__ICDIPTR5, val_mpcore__ICDIPTR5); +set_reset_data( mpcore__ICDIPTR6, val_mpcore__ICDIPTR6); +set_reset_data( mpcore__ICDIPTR7, val_mpcore__ICDIPTR7); +set_reset_data( mpcore__ICDIPTR8, val_mpcore__ICDIPTR8); +set_reset_data( mpcore__ICDIPTR9, val_mpcore__ICDIPTR9); +set_reset_data( mpcore__ICDIPTR10, val_mpcore__ICDIPTR10); +set_reset_data( mpcore__ICDIPTR11, val_mpcore__ICDIPTR11); +set_reset_data( mpcore__ICDIPTR12, val_mpcore__ICDIPTR12); +set_reset_data( mpcore__ICDIPTR13, val_mpcore__ICDIPTR13); +set_reset_data( mpcore__ICDIPTR14, val_mpcore__ICDIPTR14); +set_reset_data( mpcore__ICDIPTR15, val_mpcore__ICDIPTR15); +set_reset_data( mpcore__ICDIPTR16, val_mpcore__ICDIPTR16); +set_reset_data( mpcore__ICDIPTR17, val_mpcore__ICDIPTR17); +set_reset_data( mpcore__ICDIPTR18, val_mpcore__ICDIPTR18); +set_reset_data( mpcore__ICDIPTR19, val_mpcore__ICDIPTR19); +set_reset_data( mpcore__ICDIPTR20, val_mpcore__ICDIPTR20); +set_reset_data( mpcore__ICDIPTR21, val_mpcore__ICDIPTR21); +set_reset_data( mpcore__ICDIPTR22, val_mpcore__ICDIPTR22); +set_reset_data( mpcore__ICDIPTR23, val_mpcore__ICDIPTR23); +set_reset_data( mpcore__ICDICFR0, val_mpcore__ICDICFR0); +set_reset_data( mpcore__ICDICFR1, val_mpcore__ICDICFR1); +set_reset_data( mpcore__ICDICFR2, val_mpcore__ICDICFR2); +set_reset_data( mpcore__ICDICFR3, val_mpcore__ICDICFR3); +set_reset_data( mpcore__ICDICFR4, val_mpcore__ICDICFR4); +set_reset_data( mpcore__ICDICFR5, val_mpcore__ICDICFR5); +set_reset_data( mpcore__ppi_status, val_mpcore__ppi_status); +set_reset_data( mpcore__spi_status_0, val_mpcore__spi_status_0); +set_reset_data( mpcore__spi_status_1, val_mpcore__spi_status_1); +set_reset_data( mpcore__ICDSGIR, val_mpcore__ICDSGIR); +set_reset_data( mpcore__ICPIDR4, val_mpcore__ICPIDR4); +set_reset_data( mpcore__ICPIDR5, val_mpcore__ICPIDR5); +set_reset_data( mpcore__ICPIDR6, val_mpcore__ICPIDR6); +set_reset_data( mpcore__ICPIDR7, val_mpcore__ICPIDR7); +set_reset_data( mpcore__ICPIDR0, val_mpcore__ICPIDR0); +set_reset_data( mpcore__ICPIDR1, val_mpcore__ICPIDR1); +set_reset_data( mpcore__ICPIDR2, val_mpcore__ICPIDR2); +set_reset_data( mpcore__ICPIDR3, val_mpcore__ICPIDR3); +set_reset_data( mpcore__ICCIDR0, val_mpcore__ICCIDR0); +set_reset_data( mpcore__ICCIDR1, val_mpcore__ICCIDR1); +set_reset_data( mpcore__ICCIDR2, val_mpcore__ICCIDR2); +set_reset_data( mpcore__ICCIDR3, val_mpcore__ICCIDR3); + +// ************************************************************ +// Module ocm ocm +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ocm__OCM_PARITY_CTRL, val_ocm__OCM_PARITY_CTRL); +set_reset_data( ocm__OCM_PARITY_ERRADDRESS, val_ocm__OCM_PARITY_ERRADDRESS); +set_reset_data( ocm__OCM_IRQ_STS, val_ocm__OCM_IRQ_STS); +set_reset_data( ocm__OCM_CONTROL, val_ocm__OCM_CONTROL); + +// ************************************************************ +// Module qspi qspi +// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller +/// Design Specification document +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( qspi__Config_reg, val_qspi__Config_reg); +set_reset_data( qspi__Intr_status_REG, val_qspi__Intr_status_REG); +set_reset_data( qspi__Intrpt_en_REG, val_qspi__Intrpt_en_REG); +set_reset_data( qspi__Intrpt_dis_REG, val_qspi__Intrpt_dis_REG); +set_reset_data( qspi__Intrpt_mask_REG, val_qspi__Intrpt_mask_REG); +set_reset_data( qspi__En_REG, val_qspi__En_REG); +set_reset_data( qspi__Delay_REG, val_qspi__Delay_REG); +set_reset_data( qspi__TXD0, val_qspi__TXD0); +set_reset_data( qspi__Rx_data_REG, val_qspi__Rx_data_REG); +set_reset_data( qspi__Slave_Idle_count_REG, val_qspi__Slave_Idle_count_REG); +set_reset_data( qspi__TX_thres_REG, val_qspi__TX_thres_REG); +set_reset_data( qspi__RX_thres_REG, val_qspi__RX_thres_REG); +set_reset_data( qspi__GPIO, val_qspi__GPIO); +set_reset_data( qspi__LPBK_DLY_ADJ, val_qspi__LPBK_DLY_ADJ); +set_reset_data( qspi__TXD1, val_qspi__TXD1); +set_reset_data( qspi__TXD2, val_qspi__TXD2); +set_reset_data( qspi__TXD3, val_qspi__TXD3); +set_reset_data( qspi__LQSPI_CFG, val_qspi__LQSPI_CFG); +set_reset_data( qspi__LQSPI_STS, val_qspi__LQSPI_STS); +set_reset_data( qspi__MOD_ID, val_qspi__MOD_ID); + +// ************************************************************ +// Module sd0 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( sd0__SDMA_system_address_register, val_sd0__SDMA_system_address_register); +set_reset_data( sd0__Block_Size_Block_Count, val_sd0__Block_Size_Block_Count); +set_reset_data( sd0__Argument, val_sd0__Argument); +set_reset_data( sd0__Transfer_Mode_Command, val_sd0__Transfer_Mode_Command); +set_reset_data( sd0__Response0, val_sd0__Response0); +set_reset_data( sd0__Response1, val_sd0__Response1); +set_reset_data( sd0__Response2, val_sd0__Response2); +set_reset_data( sd0__Response3, val_sd0__Response3); +set_reset_data( sd0__Buffer_Data_Port, val_sd0__Buffer_Data_Port); +set_reset_data( sd0__Present_State, val_sd0__Present_State); +set_reset_data( sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control); +set_reset_data( sd0__Clock_Control_Timeout_control_Software_reset, val_sd0__Clock_Control_Timeout_control_Software_reset); +set_reset_data( sd0__Normal_interrupt_status_Error_interrupt_status, val_sd0__Normal_interrupt_status_Error_interrupt_status); +set_reset_data( sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable); +set_reset_data( sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); +set_reset_data( sd0__Auto_CMD12_error_status, val_sd0__Auto_CMD12_error_status); +set_reset_data( sd0__Capabilities, val_sd0__Capabilities); +set_reset_data( sd0__Maximum_current_capabilities, val_sd0__Maximum_current_capabilities); +set_reset_data( sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); +set_reset_data( sd0__ADMA_error_status, val_sd0__ADMA_error_status); +set_reset_data( sd0__ADMA_system_address, val_sd0__ADMA_system_address); +set_reset_data( sd0__Boot_Timeout_control, val_sd0__Boot_Timeout_control); +set_reset_data( sd0__Debug_Selection, val_sd0__Debug_Selection); +set_reset_data( sd0__SPI_interrupt_support, val_sd0__SPI_interrupt_support); +set_reset_data( sd0__Slot_interrupt_status_Host_controller_version, val_sd0__Slot_interrupt_status_Host_controller_version); + +// ************************************************************ +// Module sd1 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( sd1__SDMA_system_address_register, val_sd1__SDMA_system_address_register); +set_reset_data( sd1__Block_Size_Block_Count, val_sd1__Block_Size_Block_Count); +set_reset_data( sd1__Argument, val_sd1__Argument); +set_reset_data( sd1__Transfer_Mode_Command, val_sd1__Transfer_Mode_Command); +set_reset_data( sd1__Response0, val_sd1__Response0); +set_reset_data( sd1__Response1, val_sd1__Response1); +set_reset_data( sd1__Response2, val_sd1__Response2); +set_reset_data( sd1__Response3, val_sd1__Response3); +set_reset_data( sd1__Buffer_Data_Port, val_sd1__Buffer_Data_Port); +set_reset_data( sd1__Present_State, val_sd1__Present_State); +set_reset_data( sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control, val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control); +set_reset_data( sd1__Clock_Control_Timeout_control_Software_reset, val_sd1__Clock_Control_Timeout_control_Software_reset); +set_reset_data( sd1__Normal_interrupt_status_Error_interrupt_status, val_sd1__Normal_interrupt_status_Error_interrupt_status); +set_reset_data( sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable, val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable); +set_reset_data( sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable, val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable); +set_reset_data( sd1__Auto_CMD12_error_status, val_sd1__Auto_CMD12_error_status); +set_reset_data( sd1__Capabilities, val_sd1__Capabilities); +set_reset_data( sd1__Maximum_current_capabilities, val_sd1__Maximum_current_capabilities); +set_reset_data( sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status, val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status); +set_reset_data( sd1__ADMA_error_status, val_sd1__ADMA_error_status); +set_reset_data( sd1__ADMA_system_address, val_sd1__ADMA_system_address); +set_reset_data( sd1__Boot_Timeout_control, val_sd1__Boot_Timeout_control); +set_reset_data( sd1__Debug_Selection, val_sd1__Debug_Selection); +set_reset_data( sd1__SPI_interrupt_support, val_sd1__SPI_interrupt_support); +set_reset_data( sd1__Slot_interrupt_status_Host_controller_version, val_sd1__Slot_interrupt_status_Host_controller_version); + +// ************************************************************ +// Module slcr slcr +// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( slcr__SCL, val_slcr__SCL); +set_reset_data( slcr__SLCR_LOCK, val_slcr__SLCR_LOCK); +set_reset_data( slcr__SLCR_UNLOCK, val_slcr__SLCR_UNLOCK); +set_reset_data( slcr__SLCR_LOCKSTA, val_slcr__SLCR_LOCKSTA); +set_reset_data( slcr__ARM_PLL_CTRL, val_slcr__ARM_PLL_CTRL); +set_reset_data( slcr__DDR_PLL_CTRL, val_slcr__DDR_PLL_CTRL); +set_reset_data( slcr__IO_PLL_CTRL, val_slcr__IO_PLL_CTRL); +set_reset_data( slcr__PLL_STATUS, val_slcr__PLL_STATUS); +set_reset_data( slcr__ARM_PLL_CFG, val_slcr__ARM_PLL_CFG); +set_reset_data( slcr__DDR_PLL_CFG, val_slcr__DDR_PLL_CFG); +set_reset_data( slcr__IO_PLL_CFG, val_slcr__IO_PLL_CFG); +set_reset_data( slcr__PLL_BG_CTRL, val_slcr__PLL_BG_CTRL); +set_reset_data( slcr__ARM_CLK_CTRL, val_slcr__ARM_CLK_CTRL); +set_reset_data( slcr__DDR_CLK_CTRL, val_slcr__DDR_CLK_CTRL); +set_reset_data( slcr__DCI_CLK_CTRL, val_slcr__DCI_CLK_CTRL); +set_reset_data( slcr__APER_CLK_CTRL, val_slcr__APER_CLK_CTRL); +set_reset_data( slcr__USB0_CLK_CTRL, val_slcr__USB0_CLK_CTRL); +set_reset_data( slcr__USB1_CLK_CTRL, val_slcr__USB1_CLK_CTRL); +set_reset_data( slcr__GEM0_RCLK_CTRL, val_slcr__GEM0_RCLK_CTRL); +set_reset_data( slcr__GEM1_RCLK_CTRL, val_slcr__GEM1_RCLK_CTRL); +set_reset_data( slcr__GEM0_CLK_CTRL, val_slcr__GEM0_CLK_CTRL); +set_reset_data( slcr__GEM1_CLK_CTRL, val_slcr__GEM1_CLK_CTRL); +set_reset_data( slcr__SMC_CLK_CTRL, val_slcr__SMC_CLK_CTRL); +set_reset_data( slcr__LQSPI_CLK_CTRL, val_slcr__LQSPI_CLK_CTRL); +set_reset_data( slcr__SDIO_CLK_CTRL, val_slcr__SDIO_CLK_CTRL); +set_reset_data( slcr__UART_CLK_CTRL, val_slcr__UART_CLK_CTRL); +set_reset_data( slcr__SPI_CLK_CTRL, val_slcr__SPI_CLK_CTRL); +set_reset_data( slcr__CAN_CLK_CTRL, val_slcr__CAN_CLK_CTRL); +set_reset_data( slcr__CAN_MIOCLK_CTRL, val_slcr__CAN_MIOCLK_CTRL); +set_reset_data( slcr__DBG_CLK_CTRL, val_slcr__DBG_CLK_CTRL); +set_reset_data( slcr__PCAP_CLK_CTRL, val_slcr__PCAP_CLK_CTRL); +set_reset_data( slcr__TOPSW_CLK_CTRL, val_slcr__TOPSW_CLK_CTRL); +set_reset_data( slcr__FPGA0_CLK_CTRL, val_slcr__FPGA0_CLK_CTRL); +set_reset_data( slcr__FPGA0_THR_CTRL, val_slcr__FPGA0_THR_CTRL); +set_reset_data( slcr__FPGA0_THR_CNT, val_slcr__FPGA0_THR_CNT); +set_reset_data( slcr__FPGA0_THR_STA, val_slcr__FPGA0_THR_STA); +set_reset_data( slcr__FPGA1_CLK_CTRL, val_slcr__FPGA1_CLK_CTRL); +set_reset_data( slcr__FPGA1_THR_CTRL, val_slcr__FPGA1_THR_CTRL); +set_reset_data( slcr__FPGA1_THR_CNT, val_slcr__FPGA1_THR_CNT); +set_reset_data( slcr__FPGA1_THR_STA, val_slcr__FPGA1_THR_STA); +set_reset_data( slcr__FPGA2_CLK_CTRL, val_slcr__FPGA2_CLK_CTRL); +set_reset_data( slcr__FPGA2_THR_CTRL, val_slcr__FPGA2_THR_CTRL); +set_reset_data( slcr__FPGA2_THR_CNT, val_slcr__FPGA2_THR_CNT); +set_reset_data( slcr__FPGA2_THR_STA, val_slcr__FPGA2_THR_STA); +set_reset_data( slcr__FPGA3_CLK_CTRL, val_slcr__FPGA3_CLK_CTRL); +set_reset_data( slcr__FPGA3_THR_CTRL, val_slcr__FPGA3_THR_CTRL); +set_reset_data( slcr__FPGA3_THR_CNT, val_slcr__FPGA3_THR_CNT); +set_reset_data( slcr__FPGA3_THR_STA, val_slcr__FPGA3_THR_STA); +set_reset_data( slcr__SRST_UART_CTRL, val_slcr__SRST_UART_CTRL); +set_reset_data( slcr__BANDGAP_TRIM, val_slcr__BANDGAP_TRIM); +set_reset_data( slcr__CC_TEST, val_slcr__CC_TEST); +set_reset_data( slcr__PLL_PREDIVISOR, val_slcr__PLL_PREDIVISOR); +set_reset_data( slcr__CLK_621_TRUE, val_slcr__CLK_621_TRUE); +set_reset_data( slcr__PICTURE_DBG, val_slcr__PICTURE_DBG); +set_reset_data( slcr__PICTURE_DBG_UCNT, val_slcr__PICTURE_DBG_UCNT); +set_reset_data( slcr__PICTURE_DBG_LCNT, val_slcr__PICTURE_DBG_LCNT); +set_reset_data( slcr__PSS_RST_CTRL, val_slcr__PSS_RST_CTRL); +set_reset_data( slcr__DDR_RST_CTRL, val_slcr__DDR_RST_CTRL); +set_reset_data( slcr__TOPSW_RST_CTRL, val_slcr__TOPSW_RST_CTRL); +set_reset_data( slcr__DMAC_RST_CTRL, val_slcr__DMAC_RST_CTRL); +set_reset_data( slcr__USB_RST_CTRL, val_slcr__USB_RST_CTRL); +set_reset_data( slcr__GEM_RST_CTRL, val_slcr__GEM_RST_CTRL); +set_reset_data( slcr__SDIO_RST_CTRL, val_slcr__SDIO_RST_CTRL); +set_reset_data( slcr__SPI_RST_CTRL, val_slcr__SPI_RST_CTRL); +set_reset_data( slcr__CAN_RST_CTRL, val_slcr__CAN_RST_CTRL); +set_reset_data( slcr__I2C_RST_CTRL, val_slcr__I2C_RST_CTRL); +set_reset_data( slcr__UART_RST_CTRL, val_slcr__UART_RST_CTRL); +set_reset_data( slcr__GPIO_RST_CTRL, val_slcr__GPIO_RST_CTRL); +set_reset_data( slcr__LQSPI_RST_CTRL, val_slcr__LQSPI_RST_CTRL); +set_reset_data( slcr__SMC_RST_CTRL, val_slcr__SMC_RST_CTRL); +set_reset_data( slcr__OCM_RST_CTRL, val_slcr__OCM_RST_CTRL); +set_reset_data( slcr__DEVCI_RST_CTRL, val_slcr__DEVCI_RST_CTRL); +set_reset_data( slcr__FPGA_RST_CTRL, val_slcr__FPGA_RST_CTRL); +set_reset_data( slcr__A9_CPU_RST_CTRL, val_slcr__A9_CPU_RST_CTRL); +set_reset_data( slcr__RS_AWDT_CTRL, val_slcr__RS_AWDT_CTRL); +set_reset_data( slcr__RST_REASON, val_slcr__RST_REASON); +set_reset_data( slcr__RST_REASON_CLR, val_slcr__RST_REASON_CLR); +set_reset_data( slcr__REBOOT_STATUS, val_slcr__REBOOT_STATUS); +set_reset_data( slcr__BOOT_MODE, val_slcr__BOOT_MODE); +set_reset_data( slcr__APU_CTRL, val_slcr__APU_CTRL); +set_reset_data( slcr__WDT_CLK_SEL, val_slcr__WDT_CLK_SEL); +set_reset_data( slcr__TZ_OCM_RAM0, val_slcr__TZ_OCM_RAM0); +set_reset_data( slcr__TZ_OCM_RAM1, val_slcr__TZ_OCM_RAM1); +set_reset_data( slcr__TZ_OCM_ROM, val_slcr__TZ_OCM_ROM); +set_reset_data( slcr__TZ_DDR_RAM, val_slcr__TZ_DDR_RAM); +set_reset_data( slcr__TZ_DMA_NS, val_slcr__TZ_DMA_NS); +set_reset_data( slcr__TZ_DMA_IRQ_NS, val_slcr__TZ_DMA_IRQ_NS); +set_reset_data( slcr__TZ_DMA_PERIPH_NS, val_slcr__TZ_DMA_PERIPH_NS); +set_reset_data( slcr__TZ_GEM, val_slcr__TZ_GEM); +set_reset_data( slcr__TZ_SDIO, val_slcr__TZ_SDIO); +set_reset_data( slcr__TZ_USB, val_slcr__TZ_USB); +set_reset_data( slcr__TZ_FPGA_M, val_slcr__TZ_FPGA_M); +set_reset_data( slcr__TZ_FPGA_AFI, val_slcr__TZ_FPGA_AFI); +set_reset_data( slcr__DBG_CTRL, val_slcr__DBG_CTRL); +set_reset_data( slcr__PSS_IDCODE, val_slcr__PSS_IDCODE); +set_reset_data( slcr__DDR_URGENT, val_slcr__DDR_URGENT); +set_reset_data( slcr__DDR_CAL_START, val_slcr__DDR_CAL_START); +set_reset_data( slcr__DDR_REF_START, val_slcr__DDR_REF_START); +set_reset_data( slcr__DDR_CMD_STA, val_slcr__DDR_CMD_STA); +set_reset_data( slcr__DDR_URGENT_SEL, val_slcr__DDR_URGENT_SEL); +set_reset_data( slcr__DDR_DFI_STATUS, val_slcr__DDR_DFI_STATUS); +set_reset_data( slcr__MIO_PIN_00, val_slcr__MIO_PIN_00); +set_reset_data( slcr__MIO_PIN_01, val_slcr__MIO_PIN_01); +set_reset_data( slcr__MIO_PIN_02, val_slcr__MIO_PIN_02); +set_reset_data( slcr__MIO_PIN_03, val_slcr__MIO_PIN_03); +set_reset_data( slcr__MIO_PIN_04, val_slcr__MIO_PIN_04); +set_reset_data( slcr__MIO_PIN_05, val_slcr__MIO_PIN_05); +set_reset_data( slcr__MIO_PIN_06, val_slcr__MIO_PIN_06); +set_reset_data( slcr__MIO_PIN_07, val_slcr__MIO_PIN_07); +set_reset_data( slcr__MIO_PIN_08, val_slcr__MIO_PIN_08); +set_reset_data( slcr__MIO_PIN_09, val_slcr__MIO_PIN_09); +set_reset_data( slcr__MIO_PIN_10, val_slcr__MIO_PIN_10); +set_reset_data( slcr__MIO_PIN_11, val_slcr__MIO_PIN_11); +set_reset_data( slcr__MIO_PIN_12, val_slcr__MIO_PIN_12); +set_reset_data( slcr__MIO_PIN_13, val_slcr__MIO_PIN_13); +set_reset_data( slcr__MIO_PIN_14, val_slcr__MIO_PIN_14); +set_reset_data( slcr__MIO_PIN_15, val_slcr__MIO_PIN_15); +set_reset_data( slcr__MIO_PIN_16, val_slcr__MIO_PIN_16); +set_reset_data( slcr__MIO_PIN_17, val_slcr__MIO_PIN_17); +set_reset_data( slcr__MIO_PIN_18, val_slcr__MIO_PIN_18); +set_reset_data( slcr__MIO_PIN_19, val_slcr__MIO_PIN_19); +set_reset_data( slcr__MIO_PIN_20, val_slcr__MIO_PIN_20); +set_reset_data( slcr__MIO_PIN_21, val_slcr__MIO_PIN_21); +set_reset_data( slcr__MIO_PIN_22, val_slcr__MIO_PIN_22); +set_reset_data( slcr__MIO_PIN_23, val_slcr__MIO_PIN_23); +set_reset_data( slcr__MIO_PIN_24, val_slcr__MIO_PIN_24); +set_reset_data( slcr__MIO_PIN_25, val_slcr__MIO_PIN_25); +set_reset_data( slcr__MIO_PIN_26, val_slcr__MIO_PIN_26); +set_reset_data( slcr__MIO_PIN_27, val_slcr__MIO_PIN_27); +set_reset_data( slcr__MIO_PIN_28, val_slcr__MIO_PIN_28); +set_reset_data( slcr__MIO_PIN_29, val_slcr__MIO_PIN_29); +set_reset_data( slcr__MIO_PIN_30, val_slcr__MIO_PIN_30); +set_reset_data( slcr__MIO_PIN_31, val_slcr__MIO_PIN_31); +set_reset_data( slcr__MIO_PIN_32, val_slcr__MIO_PIN_32); +set_reset_data( slcr__MIO_PIN_33, val_slcr__MIO_PIN_33); +set_reset_data( slcr__MIO_PIN_34, val_slcr__MIO_PIN_34); +set_reset_data( slcr__MIO_PIN_35, val_slcr__MIO_PIN_35); +set_reset_data( slcr__MIO_PIN_36, val_slcr__MIO_PIN_36); +set_reset_data( slcr__MIO_PIN_37, val_slcr__MIO_PIN_37); +set_reset_data( slcr__MIO_PIN_38, val_slcr__MIO_PIN_38); +set_reset_data( slcr__MIO_PIN_39, val_slcr__MIO_PIN_39); +set_reset_data( slcr__MIO_PIN_40, val_slcr__MIO_PIN_40); +set_reset_data( slcr__MIO_PIN_41, val_slcr__MIO_PIN_41); +set_reset_data( slcr__MIO_PIN_42, val_slcr__MIO_PIN_42); +set_reset_data( slcr__MIO_PIN_43, val_slcr__MIO_PIN_43); +set_reset_data( slcr__MIO_PIN_44, val_slcr__MIO_PIN_44); +set_reset_data( slcr__MIO_PIN_45, val_slcr__MIO_PIN_45); +set_reset_data( slcr__MIO_PIN_46, val_slcr__MIO_PIN_46); +set_reset_data( slcr__MIO_PIN_47, val_slcr__MIO_PIN_47); +set_reset_data( slcr__MIO_PIN_48, val_slcr__MIO_PIN_48); +set_reset_data( slcr__MIO_PIN_49, val_slcr__MIO_PIN_49); +set_reset_data( slcr__MIO_PIN_50, val_slcr__MIO_PIN_50); +set_reset_data( slcr__MIO_PIN_51, val_slcr__MIO_PIN_51); +set_reset_data( slcr__MIO_PIN_52, val_slcr__MIO_PIN_52); +set_reset_data( slcr__MIO_PIN_53, val_slcr__MIO_PIN_53); +set_reset_data( slcr__MIO_FMIO_GEM_SEL, val_slcr__MIO_FMIO_GEM_SEL); +set_reset_data( slcr__MIO_LOOPBACK, val_slcr__MIO_LOOPBACK); +set_reset_data( slcr__MIO_MST_TRI0, val_slcr__MIO_MST_TRI0); +set_reset_data( slcr__MIO_MST_TRI1, val_slcr__MIO_MST_TRI1); +set_reset_data( slcr__SD0_WP_CD_SEL, val_slcr__SD0_WP_CD_SEL); +set_reset_data( slcr__SD1_WP_CD_SEL, val_slcr__SD1_WP_CD_SEL); +set_reset_data( slcr__LVL_SHFTR_EN, val_slcr__LVL_SHFTR_EN); +set_reset_data( slcr__OCM_CFG, val_slcr__OCM_CFG); +set_reset_data( slcr__CPU0_RAM0, val_slcr__CPU0_RAM0); +set_reset_data( slcr__CPU0_RAM1, val_slcr__CPU0_RAM1); +set_reset_data( slcr__CPU0_RAM2, val_slcr__CPU0_RAM2); +set_reset_data( slcr__CPU1_RAM0, val_slcr__CPU1_RAM0); +set_reset_data( slcr__CPU1_RAM1, val_slcr__CPU1_RAM1); +set_reset_data( slcr__CPU1_RAM2, val_slcr__CPU1_RAM2); +set_reset_data( slcr__SCU_RAM, val_slcr__SCU_RAM); +set_reset_data( slcr__L2C_RAM, val_slcr__L2C_RAM); +set_reset_data( slcr__IOU_RAM_GEM01, val_slcr__IOU_RAM_GEM01); +set_reset_data( slcr__IOU_RAM_USB01, val_slcr__IOU_RAM_USB01); +set_reset_data( slcr__IOU_RAM_SDIO0, val_slcr__IOU_RAM_SDIO0); +set_reset_data( slcr__IOU_RAM_SDIO1, val_slcr__IOU_RAM_SDIO1); +set_reset_data( slcr__IOU_RAM_CAN0, val_slcr__IOU_RAM_CAN0); +set_reset_data( slcr__IOU_RAM_CAN1, val_slcr__IOU_RAM_CAN1); +set_reset_data( slcr__IOU_RAM_LQSPI, val_slcr__IOU_RAM_LQSPI); +set_reset_data( slcr__DMAC_RAM, val_slcr__DMAC_RAM); +set_reset_data( slcr__AFI0_RAM0, val_slcr__AFI0_RAM0); +set_reset_data( slcr__AFI0_RAM1, val_slcr__AFI0_RAM1); +set_reset_data( slcr__AFI0_RAM2, val_slcr__AFI0_RAM2); +set_reset_data( slcr__AFI1_RAM0, val_slcr__AFI1_RAM0); +set_reset_data( slcr__AFI1_RAM1, val_slcr__AFI1_RAM1); +set_reset_data( slcr__AFI1_RAM2, val_slcr__AFI1_RAM2); +set_reset_data( slcr__AFI2_RAM0, val_slcr__AFI2_RAM0); +set_reset_data( slcr__AFI2_RAM1, val_slcr__AFI2_RAM1); +set_reset_data( slcr__AFI2_RAM2, val_slcr__AFI2_RAM2); +set_reset_data( slcr__AFI3_RAM0, val_slcr__AFI3_RAM0); +set_reset_data( slcr__AFI3_RAM1, val_slcr__AFI3_RAM1); +set_reset_data( slcr__AFI3_RAM2, val_slcr__AFI3_RAM2); +set_reset_data( slcr__OCM_RAM, val_slcr__OCM_RAM); +set_reset_data( slcr__OCM_ROM0, val_slcr__OCM_ROM0); +set_reset_data( slcr__OCM_ROM1, val_slcr__OCM_ROM1); +set_reset_data( slcr__DEVCI_RAM, val_slcr__DEVCI_RAM); +set_reset_data( slcr__CSG_RAM, val_slcr__CSG_RAM); +set_reset_data( slcr__GPIOB_CTRL, val_slcr__GPIOB_CTRL); +set_reset_data( slcr__GPIOB_CFG_CMOS18, val_slcr__GPIOB_CFG_CMOS18); +set_reset_data( slcr__GPIOB_CFG_CMOS25, val_slcr__GPIOB_CFG_CMOS25); +set_reset_data( slcr__GPIOB_CFG_CMOS33, val_slcr__GPIOB_CFG_CMOS33); +set_reset_data( slcr__GPIOB_CFG_LVTTL, val_slcr__GPIOB_CFG_LVTTL); +set_reset_data( slcr__GPIOB_CFG_HSTL, val_slcr__GPIOB_CFG_HSTL); +set_reset_data( slcr__GPIOB_DRVR_BIAS_CTRL, val_slcr__GPIOB_DRVR_BIAS_CTRL); +set_reset_data( slcr__DDRIOB_ADDR0, val_slcr__DDRIOB_ADDR0); +set_reset_data( slcr__DDRIOB_ADDR1, val_slcr__DDRIOB_ADDR1); +set_reset_data( slcr__DDRIOB_DATA0, val_slcr__DDRIOB_DATA0); +set_reset_data( slcr__DDRIOB_DATA1, val_slcr__DDRIOB_DATA1); +set_reset_data( slcr__DDRIOB_DIFF0, val_slcr__DDRIOB_DIFF0); +set_reset_data( slcr__DDRIOB_DIFF1, val_slcr__DDRIOB_DIFF1); +set_reset_data( slcr__DDRIOB_CLOCK, val_slcr__DDRIOB_CLOCK); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_ADDR, val_slcr__DDRIOB_DRIVE_SLEW_ADDR); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DATA, val_slcr__DDRIOB_DRIVE_SLEW_DATA); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_DIFF, val_slcr__DDRIOB_DRIVE_SLEW_DIFF); +set_reset_data( slcr__DDRIOB_DRIVE_SLEW_CLOCK, val_slcr__DDRIOB_DRIVE_SLEW_CLOCK); +set_reset_data( slcr__DDRIOB_DDR_CTRL, val_slcr__DDRIOB_DDR_CTRL); +set_reset_data( slcr__DDRIOB_DCI_CTRL, val_slcr__DDRIOB_DCI_CTRL); +set_reset_data( slcr__DDRIOB_DCI_STATUS, val_slcr__DDRIOB_DCI_STATUS); + +// ************************************************************ +// Module smcc pl353 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( smcc__memc_status, val_smcc__memc_status); +set_reset_data( smcc__memif_cfg, val_smcc__memif_cfg); +set_reset_data( smcc__memc_cfg_set, val_smcc__memc_cfg_set); +set_reset_data( smcc__memc_cfg_clr, val_smcc__memc_cfg_clr); +set_reset_data( smcc__direct_cmd, val_smcc__direct_cmd); +set_reset_data( smcc__set_cycles, val_smcc__set_cycles); +set_reset_data( smcc__set_opmode, val_smcc__set_opmode); +set_reset_data( smcc__refresh_period_0, val_smcc__refresh_period_0); +set_reset_data( smcc__refresh_period_1, val_smcc__refresh_period_1); +set_reset_data( smcc__sram_cycles0_0, val_smcc__sram_cycles0_0); +set_reset_data( smcc__opmode0_0, val_smcc__opmode0_0); +set_reset_data( smcc__sram_cycles0_1, val_smcc__sram_cycles0_1); +set_reset_data( smcc__opmode0_1, val_smcc__opmode0_1); +set_reset_data( smcc__nand_cycles1_0, val_smcc__nand_cycles1_0); +set_reset_data( smcc__opmode1_0, val_smcc__opmode1_0); +set_reset_data( smcc__user_status, val_smcc__user_status); +set_reset_data( smcc__user_config, val_smcc__user_config); +set_reset_data( smcc__ecc_status_0, val_smcc__ecc_status_0); +set_reset_data( smcc__ecc_memcfg_0, val_smcc__ecc_memcfg_0); +set_reset_data( smcc__ecc_memcommand1_0, val_smcc__ecc_memcommand1_0); +set_reset_data( smcc__ecc_memcommand2_0, val_smcc__ecc_memcommand2_0); +set_reset_data( smcc__ecc_addr0_0, val_smcc__ecc_addr0_0); +set_reset_data( smcc__ecc_addr1_0, val_smcc__ecc_addr1_0); +set_reset_data( smcc__ecc_value0_0, val_smcc__ecc_value0_0); +set_reset_data( smcc__ecc_value1_0, val_smcc__ecc_value1_0); +set_reset_data( smcc__ecc_value2_0, val_smcc__ecc_value2_0); +set_reset_data( smcc__ecc_value3_0, val_smcc__ecc_value3_0); +set_reset_data( smcc__ecc_status_1, val_smcc__ecc_status_1); +set_reset_data( smcc__ecc_memcfg_1, val_smcc__ecc_memcfg_1); +set_reset_data( smcc__ecc_memcommand1_1, val_smcc__ecc_memcommand1_1); +set_reset_data( smcc__ecc_memcommand2_1, val_smcc__ecc_memcommand2_1); +set_reset_data( smcc__ecc_addr0_1, val_smcc__ecc_addr0_1); +set_reset_data( smcc__ecc_addr1_1, val_smcc__ecc_addr1_1); +set_reset_data( smcc__ecc_value0_1, val_smcc__ecc_value0_1); +set_reset_data( smcc__ecc_value1_1, val_smcc__ecc_value1_1); +set_reset_data( smcc__ecc_value2_1, val_smcc__ecc_value2_1); +set_reset_data( smcc__ecc_value3_1, val_smcc__ecc_value3_1); +set_reset_data( smcc__integration_test, val_smcc__integration_test); +set_reset_data( smcc__periph_id_0, val_smcc__periph_id_0); +set_reset_data( smcc__periph_id_1, val_smcc__periph_id_1); +set_reset_data( smcc__periph_id_2, val_smcc__periph_id_2); +set_reset_data( smcc__periph_id_3, val_smcc__periph_id_3); +set_reset_data( smcc__pcell_id_0, val_smcc__pcell_id_0); +set_reset_data( smcc__pcell_id_1, val_smcc__pcell_id_1); +set_reset_data( smcc__pcell_id_2, val_smcc__pcell_id_2); +set_reset_data( smcc__pcell_id_3, val_smcc__pcell_id_3); + +// ************************************************************ +// Module spi0 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( spi0__Config_reg0, val_spi0__Config_reg0); +set_reset_data( spi0__Intr_status_reg0, val_spi0__Intr_status_reg0); +set_reset_data( spi0__Intrpt_en_reg0, val_spi0__Intrpt_en_reg0); +set_reset_data( spi0__Intrpt_dis_reg0, val_spi0__Intrpt_dis_reg0); +set_reset_data( spi0__Intrpt_mask_reg0, val_spi0__Intrpt_mask_reg0); +set_reset_data( spi0__En_reg0, val_spi0__En_reg0); +set_reset_data( spi0__Delay_reg0, val_spi0__Delay_reg0); +set_reset_data( spi0__Tx_data_reg0, val_spi0__Tx_data_reg0); +set_reset_data( spi0__Rx_data_reg0, val_spi0__Rx_data_reg0); +set_reset_data( spi0__Slave_Idle_count_reg0, val_spi0__Slave_Idle_count_reg0); +set_reset_data( spi0__TX_thres_reg0, val_spi0__TX_thres_reg0); +set_reset_data( spi0__RX_thres_reg0, val_spi0__RX_thres_reg0); +set_reset_data( spi0__Mod_id_reg0, val_spi0__Mod_id_reg0); + +// ************************************************************ +// Module spi1 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( spi1__Config_reg0, val_spi1__Config_reg0); +set_reset_data( spi1__Intr_status_reg0, val_spi1__Intr_status_reg0); +set_reset_data( spi1__Intrpt_en_reg0, val_spi1__Intrpt_en_reg0); +set_reset_data( spi1__Intrpt_dis_reg0, val_spi1__Intrpt_dis_reg0); +set_reset_data( spi1__Intrpt_mask_reg0, val_spi1__Intrpt_mask_reg0); +set_reset_data( spi1__En_reg0, val_spi1__En_reg0); +set_reset_data( spi1__Delay_reg0, val_spi1__Delay_reg0); +set_reset_data( spi1__Tx_data_reg0, val_spi1__Tx_data_reg0); +set_reset_data( spi1__Rx_data_reg0, val_spi1__Rx_data_reg0); +set_reset_data( spi1__Slave_Idle_count_reg0, val_spi1__Slave_Idle_count_reg0); +set_reset_data( spi1__TX_thres_reg0, val_spi1__TX_thres_reg0); +set_reset_data( spi1__RX_thres_reg0, val_spi1__RX_thres_reg0); +set_reset_data( spi1__Mod_id_reg0, val_spi1__Mod_id_reg0); + +// ************************************************************ +// Module swdt swdt +// doc version: 2.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( swdt__MODE, val_swdt__MODE); +set_reset_data( swdt__CONTROL, val_swdt__CONTROL); +set_reset_data( swdt__RESTART, val_swdt__RESTART); +set_reset_data( swdt__STATUS, val_swdt__STATUS); + +// ************************************************************ +// Module ttc0 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ttc0__Clock_Control_1, val_ttc0__Clock_Control_1); +set_reset_data( ttc0__Clock_Control_2, val_ttc0__Clock_Control_2); +set_reset_data( ttc0__Clock_Control_3, val_ttc0__Clock_Control_3); +set_reset_data( ttc0__Counter_Control_1, val_ttc0__Counter_Control_1); +set_reset_data( ttc0__Counter_Control_2, val_ttc0__Counter_Control_2); +set_reset_data( ttc0__Counter_Control_3, val_ttc0__Counter_Control_3); +set_reset_data( ttc0__Counter_Value_1, val_ttc0__Counter_Value_1); +set_reset_data( ttc0__Counter_Value_2, val_ttc0__Counter_Value_2); +set_reset_data( ttc0__Counter_Value_3, val_ttc0__Counter_Value_3); +set_reset_data( ttc0__Interval_Counter_1, val_ttc0__Interval_Counter_1); +set_reset_data( ttc0__Interval_Counter_2, val_ttc0__Interval_Counter_2); +set_reset_data( ttc0__Interval_Counter_3, val_ttc0__Interval_Counter_3); +set_reset_data( ttc0__Match_1_Counter_1, val_ttc0__Match_1_Counter_1); +set_reset_data( ttc0__Match_1_Counter_2, val_ttc0__Match_1_Counter_2); +set_reset_data( ttc0__Match_1_Counter_3, val_ttc0__Match_1_Counter_3); +set_reset_data( ttc0__Match_2_Counter_1, val_ttc0__Match_2_Counter_1); +set_reset_data( ttc0__Match_2_Counter_2, val_ttc0__Match_2_Counter_2); +set_reset_data( ttc0__Match_2_Counter_3, val_ttc0__Match_2_Counter_3); +set_reset_data( ttc0__Match_3_Counter_1, val_ttc0__Match_3_Counter_1); +set_reset_data( ttc0__Match_3_Counter_2, val_ttc0__Match_3_Counter_2); +set_reset_data( ttc0__Match_3_Counter_3, val_ttc0__Match_3_Counter_3); +set_reset_data( ttc0__Interrupt_Register_1, val_ttc0__Interrupt_Register_1); +set_reset_data( ttc0__Interrupt_Register_2, val_ttc0__Interrupt_Register_2); +set_reset_data( ttc0__Interrupt_Register_3, val_ttc0__Interrupt_Register_3); +set_reset_data( ttc0__Interrupt_Enable_1, val_ttc0__Interrupt_Enable_1); +set_reset_data( ttc0__Interrupt_Enable_2, val_ttc0__Interrupt_Enable_2); +set_reset_data( ttc0__Interrupt_Enable_3, val_ttc0__Interrupt_Enable_3); +set_reset_data( ttc0__Event_Control_Timer_1, val_ttc0__Event_Control_Timer_1); +set_reset_data( ttc0__Event_Control_Timer_2, val_ttc0__Event_Control_Timer_2); +set_reset_data( ttc0__Event_Control_Timer_3, val_ttc0__Event_Control_Timer_3); +set_reset_data( ttc0__Event_Register_1, val_ttc0__Event_Register_1); +set_reset_data( ttc0__Event_Register_2, val_ttc0__Event_Register_2); +set_reset_data( ttc0__Event_Register_3, val_ttc0__Event_Register_3); + +// ************************************************************ +// Module ttc1 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( ttc1__Clock_Control_1, val_ttc1__Clock_Control_1); +set_reset_data( ttc1__Clock_Control_2, val_ttc1__Clock_Control_2); +set_reset_data( ttc1__Clock_Control_3, val_ttc1__Clock_Control_3); +set_reset_data( ttc1__Counter_Control_1, val_ttc1__Counter_Control_1); +set_reset_data( ttc1__Counter_Control_2, val_ttc1__Counter_Control_2); +set_reset_data( ttc1__Counter_Control_3, val_ttc1__Counter_Control_3); +set_reset_data( ttc1__Counter_Value_1, val_ttc1__Counter_Value_1); +set_reset_data( ttc1__Counter_Value_2, val_ttc1__Counter_Value_2); +set_reset_data( ttc1__Counter_Value_3, val_ttc1__Counter_Value_3); +set_reset_data( ttc1__Interval_Counter_1, val_ttc1__Interval_Counter_1); +set_reset_data( ttc1__Interval_Counter_2, val_ttc1__Interval_Counter_2); +set_reset_data( ttc1__Interval_Counter_3, val_ttc1__Interval_Counter_3); +set_reset_data( ttc1__Match_1_Counter_1, val_ttc1__Match_1_Counter_1); +set_reset_data( ttc1__Match_1_Counter_2, val_ttc1__Match_1_Counter_2); +set_reset_data( ttc1__Match_1_Counter_3, val_ttc1__Match_1_Counter_3); +set_reset_data( ttc1__Match_2_Counter_1, val_ttc1__Match_2_Counter_1); +set_reset_data( ttc1__Match_2_Counter_2, val_ttc1__Match_2_Counter_2); +set_reset_data( ttc1__Match_2_Counter_3, val_ttc1__Match_2_Counter_3); +set_reset_data( ttc1__Match_3_Counter_1, val_ttc1__Match_3_Counter_1); +set_reset_data( ttc1__Match_3_Counter_2, val_ttc1__Match_3_Counter_2); +set_reset_data( ttc1__Match_3_Counter_3, val_ttc1__Match_3_Counter_3); +set_reset_data( ttc1__Interrupt_Register_1, val_ttc1__Interrupt_Register_1); +set_reset_data( ttc1__Interrupt_Register_2, val_ttc1__Interrupt_Register_2); +set_reset_data( ttc1__Interrupt_Register_3, val_ttc1__Interrupt_Register_3); +set_reset_data( ttc1__Interrupt_Enable_1, val_ttc1__Interrupt_Enable_1); +set_reset_data( ttc1__Interrupt_Enable_2, val_ttc1__Interrupt_Enable_2); +set_reset_data( ttc1__Interrupt_Enable_3, val_ttc1__Interrupt_Enable_3); +set_reset_data( ttc1__Event_Control_Timer_1, val_ttc1__Event_Control_Timer_1); +set_reset_data( ttc1__Event_Control_Timer_2, val_ttc1__Event_Control_Timer_2); +set_reset_data( ttc1__Event_Control_Timer_3, val_ttc1__Event_Control_Timer_3); +set_reset_data( ttc1__Event_Register_1, val_ttc1__Event_Register_1); +set_reset_data( ttc1__Event_Register_2, val_ttc1__Event_Register_2); +set_reset_data( ttc1__Event_Register_3, val_ttc1__Event_Register_3); + +// ************************************************************ +// Module uart0 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( uart0__Control_reg0, val_uart0__Control_reg0); +set_reset_data( uart0__mode_reg0, val_uart0__mode_reg0); +set_reset_data( uart0__Intrpt_en_reg0, val_uart0__Intrpt_en_reg0); +set_reset_data( uart0__Intrpt_dis_reg0, val_uart0__Intrpt_dis_reg0); +set_reset_data( uart0__Intrpt_mask_reg0, val_uart0__Intrpt_mask_reg0); +set_reset_data( uart0__Chnl_int_sts_reg0, val_uart0__Chnl_int_sts_reg0); +set_reset_data( uart0__Baud_rate_gen_reg0, val_uart0__Baud_rate_gen_reg0); +set_reset_data( uart0__Rcvr_timeout_reg0, val_uart0__Rcvr_timeout_reg0); +set_reset_data( uart0__Rcvr_FIFO_trigger_level0, val_uart0__Rcvr_FIFO_trigger_level0); +set_reset_data( uart0__Modem_ctrl_reg0, val_uart0__Modem_ctrl_reg0); +set_reset_data( uart0__Modem_sts_reg0, val_uart0__Modem_sts_reg0); +set_reset_data( uart0__Channel_sts_reg0, val_uart0__Channel_sts_reg0); +set_reset_data( uart0__TX_RX_FIFO0, val_uart0__TX_RX_FIFO0); +set_reset_data( uart0__Baud_rate_divider_reg0, val_uart0__Baud_rate_divider_reg0); +set_reset_data( uart0__Flow_delay_reg0, val_uart0__Flow_delay_reg0); +set_reset_data( uart0__IR_min_rcv_pulse_wdth0, val_uart0__IR_min_rcv_pulse_wdth0); +set_reset_data( uart0__IR_transmitted_pulse_wdth0, val_uart0__IR_transmitted_pulse_wdth0); +set_reset_data( uart0__Tx_FIFO_trigger_level0, val_uart0__Tx_FIFO_trigger_level0); + +// ************************************************************ +// Module uart1 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( uart1__Control_reg0, val_uart1__Control_reg0); +set_reset_data( uart1__mode_reg0, val_uart1__mode_reg0); +set_reset_data( uart1__Intrpt_en_reg0, val_uart1__Intrpt_en_reg0); +set_reset_data( uart1__Intrpt_dis_reg0, val_uart1__Intrpt_dis_reg0); +set_reset_data( uart1__Intrpt_mask_reg0, val_uart1__Intrpt_mask_reg0); +set_reset_data( uart1__Chnl_int_sts_reg0, val_uart1__Chnl_int_sts_reg0); +set_reset_data( uart1__Baud_rate_gen_reg0, val_uart1__Baud_rate_gen_reg0); +set_reset_data( uart1__Rcvr_timeout_reg0, val_uart1__Rcvr_timeout_reg0); +set_reset_data( uart1__Rcvr_FIFO_trigger_level0, val_uart1__Rcvr_FIFO_trigger_level0); +set_reset_data( uart1__Modem_ctrl_reg0, val_uart1__Modem_ctrl_reg0); +set_reset_data( uart1__Modem_sts_reg0, val_uart1__Modem_sts_reg0); +set_reset_data( uart1__Channel_sts_reg0, val_uart1__Channel_sts_reg0); +set_reset_data( uart1__TX_RX_FIFO0, val_uart1__TX_RX_FIFO0); +set_reset_data( uart1__Baud_rate_divider_reg0, val_uart1__Baud_rate_divider_reg0); +set_reset_data( uart1__Flow_delay_reg0, val_uart1__Flow_delay_reg0); +set_reset_data( uart1__IR_min_rcv_pulse_wdth0, val_uart1__IR_min_rcv_pulse_wdth0); +set_reset_data( uart1__IR_transmitted_pulse_wdth0, val_uart1__IR_transmitted_pulse_wdth0); +set_reset_data( uart1__Tx_FIFO_trigger_level0, val_uart1__Tx_FIFO_trigger_level0); + +// ************************************************************ +// Module usb0 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( usb0__ID, val_usb0__ID); +set_reset_data( usb0__HWGENERAL, val_usb0__HWGENERAL); +set_reset_data( usb0__HWHOST, val_usb0__HWHOST); +set_reset_data( usb0__HWDEVICE, val_usb0__HWDEVICE); +set_reset_data( usb0__HWTXBUF, val_usb0__HWTXBUF); +set_reset_data( usb0__HWRXBUF, val_usb0__HWRXBUF); +set_reset_data( usb0__GPTIMER0LD, val_usb0__GPTIMER0LD); +set_reset_data( usb0__GPTIMER0CTRL, val_usb0__GPTIMER0CTRL); +set_reset_data( usb0__GPTIMER1LD, val_usb0__GPTIMER1LD); +set_reset_data( usb0__GPTIMER1CTRL, val_usb0__GPTIMER1CTRL); +set_reset_data( usb0__SBUSCFG, val_usb0__SBUSCFG); +set_reset_data( usb0__CAPLENGTH_HCIVERSION, val_usb0__CAPLENGTH_HCIVERSION); +set_reset_data( usb0__HCSPARAMS, val_usb0__HCSPARAMS); +set_reset_data( usb0__HCCPARAMS, val_usb0__HCCPARAMS); +set_reset_data( usb0__DCIVERSION, val_usb0__DCIVERSION); +set_reset_data( usb0__DCCPARAMS, val_usb0__DCCPARAMS); +set_reset_data( usb0__USBCMD, val_usb0__USBCMD); +set_reset_data( usb0__USBSTS, val_usb0__USBSTS); +set_reset_data( usb0__USBINTR, val_usb0__USBINTR); +set_reset_data( usb0__FRINDEX, val_usb0__FRINDEX); +set_reset_data( usb0__PERIODICLISTBASE_DEVICEADDR, val_usb0__PERIODICLISTBASE_DEVICEADDR); +set_reset_data( usb0__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR); +set_reset_data( usb0__TTCTRL, val_usb0__TTCTRL); +set_reset_data( usb0__BURSTSIZE, val_usb0__BURSTSIZE); +set_reset_data( usb0__TXFILLTUNING, val_usb0__TXFILLTUNING); +set_reset_data( usb0__TXTTFILLTUNING, val_usb0__TXTTFILLTUNING); +set_reset_data( usb0__IC_USB, val_usb0__IC_USB); +set_reset_data( usb0__ULPI_VIEWPORT, val_usb0__ULPI_VIEWPORT); +set_reset_data( usb0__ENDPTNAK, val_usb0__ENDPTNAK); +set_reset_data( usb0__ENDPTNAKEN, val_usb0__ENDPTNAKEN); +set_reset_data( usb0__CONFIGFLAG, val_usb0__CONFIGFLAG); +set_reset_data( usb0__PORTSC1, val_usb0__PORTSC1); +set_reset_data( usb0__OTGSC, val_usb0__OTGSC); +set_reset_data( usb0__USBMODE, val_usb0__USBMODE); +set_reset_data( usb0__ENDPTSETUPSTAT, val_usb0__ENDPTSETUPSTAT); +set_reset_data( usb0__ENDPTPRIME, val_usb0__ENDPTPRIME); +set_reset_data( usb0__ENDPTFLUSH, val_usb0__ENDPTFLUSH); +set_reset_data( usb0__ENDPTSTAT, val_usb0__ENDPTSTAT); +set_reset_data( usb0__ENDPTCOMPLETE, val_usb0__ENDPTCOMPLETE); +set_reset_data( usb0__ENDPTCTRL0, val_usb0__ENDPTCTRL0); +set_reset_data( usb0__ENDPTCTRL1, val_usb0__ENDPTCTRL1); +set_reset_data( usb0__ENDPTCTRL2, val_usb0__ENDPTCTRL2); +set_reset_data( usb0__ENDPTCTRL3, val_usb0__ENDPTCTRL3); +set_reset_data( usb0__ENDPTCTRL4, val_usb0__ENDPTCTRL4); +set_reset_data( usb0__ENDPTCTRL5, val_usb0__ENDPTCTRL5); +set_reset_data( usb0__ENDPTCTRL6, val_usb0__ENDPTCTRL6); +set_reset_data( usb0__ENDPTCTRL7, val_usb0__ENDPTCTRL7); +set_reset_data( usb0__ENDPTCTRL8, val_usb0__ENDPTCTRL8); +set_reset_data( usb0__ENDPTCTRL9, val_usb0__ENDPTCTRL9); +set_reset_data( usb0__ENDPTCTRL10, val_usb0__ENDPTCTRL10); +set_reset_data( usb0__ENDPTCTRL11, val_usb0__ENDPTCTRL11); +set_reset_data( usb0__ENDPTCTRL12, val_usb0__ENDPTCTRL12); + +// ************************************************************ +// Module usb1 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +set_reset_data( usb1__ID, val_usb1__ID); +set_reset_data( usb1__HWGENERAL, val_usb1__HWGENERAL); +set_reset_data( usb1__HWHOST, val_usb1__HWHOST); +set_reset_data( usb1__HWDEVICE, val_usb1__HWDEVICE); +set_reset_data( usb1__HWTXBUF, val_usb1__HWTXBUF); +set_reset_data( usb1__HWRXBUF, val_usb1__HWRXBUF); +set_reset_data( usb1__GPTIMER0LD, val_usb1__GPTIMER0LD); +set_reset_data( usb1__GPTIMER0CTRL, val_usb1__GPTIMER0CTRL); +set_reset_data( usb1__GPTIMER1LD, val_usb1__GPTIMER1LD); +set_reset_data( usb1__GPTIMER1CTRL, val_usb1__GPTIMER1CTRL); +set_reset_data( usb1__SBUSCFG, val_usb1__SBUSCFG); +set_reset_data( usb1__CAPLENGTH_HCIVERSION, val_usb1__CAPLENGTH_HCIVERSION); +set_reset_data( usb1__HCSPARAMS, val_usb1__HCSPARAMS); +set_reset_data( usb1__HCCPARAMS, val_usb1__HCCPARAMS); +set_reset_data( usb1__DCIVERSION, val_usb1__DCIVERSION); +set_reset_data( usb1__DCCPARAMS, val_usb1__DCCPARAMS); +set_reset_data( usb1__USBCMD, val_usb1__USBCMD); +set_reset_data( usb1__USBSTS, val_usb1__USBSTS); +set_reset_data( usb1__USBINTR, val_usb1__USBINTR); +set_reset_data( usb1__FRINDEX, val_usb1__FRINDEX); +set_reset_data( usb1__PERIODICLISTBASE_DEVICEADDR, val_usb1__PERIODICLISTBASE_DEVICEADDR); +set_reset_data( usb1__ASYNCLISTADDR_ENDPOINTLISTADDR, val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR); +set_reset_data( usb1__TTCTRL, val_usb1__TTCTRL); +set_reset_data( usb1__BURSTSIZE, val_usb1__BURSTSIZE); +set_reset_data( usb1__TXFILLTUNING, val_usb1__TXFILLTUNING); +set_reset_data( usb1__TXTTFILLTUNING, val_usb1__TXTTFILLTUNING); +set_reset_data( usb1__IC_USB, val_usb1__IC_USB); +set_reset_data( usb1__ULPI_VIEWPORT, val_usb1__ULPI_VIEWPORT); +set_reset_data( usb1__ENDPTNAK, val_usb1__ENDPTNAK); +set_reset_data( usb1__ENDPTNAKEN, val_usb1__ENDPTNAKEN); +set_reset_data( usb1__CONFIGFLAG, val_usb1__CONFIGFLAG); +set_reset_data( usb1__PORTSC1, val_usb1__PORTSC1); +set_reset_data( usb1__OTGSC, val_usb1__OTGSC); +set_reset_data( usb1__USBMODE, val_usb1__USBMODE); +set_reset_data( usb1__ENDPTSETUPSTAT, val_usb1__ENDPTSETUPSTAT); +set_reset_data( usb1__ENDPTPRIME, val_usb1__ENDPTPRIME); +set_reset_data( usb1__ENDPTFLUSH, val_usb1__ENDPTFLUSH); +set_reset_data( usb1__ENDPTSTAT, val_usb1__ENDPTSTAT); +set_reset_data( usb1__ENDPTCOMPLETE, val_usb1__ENDPTCOMPLETE); +set_reset_data( usb1__ENDPTCTRL0, val_usb1__ENDPTCTRL0); +set_reset_data( usb1__ENDPTCTRL1, val_usb1__ENDPTCTRL1); +set_reset_data( usb1__ENDPTCTRL2, val_usb1__ENDPTCTRL2); +set_reset_data( usb1__ENDPTCTRL3, val_usb1__ENDPTCTRL3); +set_reset_data( usb1__ENDPTCTRL4, val_usb1__ENDPTCTRL4); +set_reset_data( usb1__ENDPTCTRL5, val_usb1__ENDPTCTRL5); +set_reset_data( usb1__ENDPTCTRL6, val_usb1__ENDPTCTRL6); +set_reset_data( usb1__ENDPTCTRL7, val_usb1__ENDPTCTRL7); +set_reset_data( usb1__ENDPTCTRL8, val_usb1__ENDPTCTRL8); +set_reset_data( usb1__ENDPTCTRL9, val_usb1__ENDPTCTRL9); +set_reset_data( usb1__ENDPTCTRL10, val_usb1__ENDPTCTRL10); +set_reset_data( usb1__ENDPTCTRL11, val_usb1__ENDPTCTRL11); +set_reset_data( usb1__ENDPTCTRL12, val_usb1__ENDPTCTRL12); diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_reg_params.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_reg_params.v new file mode 100644 index 0000000..41b0b56 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_reg_params.v @@ -0,0 +1,10519 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_5_reg_params.v + * + * Date : 2012-11 + * + * Description : Parameters for Register Address and Default values. + * + *****************************************************************************/ + +// Register default value info for chip pele_ps +// This code was auto-generated by xregdb.py ver. 0.68, Thu Jul 12 10:32:25 2012 +// 54 modules, 2532 registers. + + +// ************************************************************ +// Module afi0 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi0__AFI_RDCHAN_CTRL = 32'hF8008000; +parameter val_afi0__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi0__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi0__AFI_RDCHAN_ISSUINGCAP = 32'hF8008004; +parameter val_afi0__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi0__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi0__AFI_RDQOS = 32'hF8008008; +parameter val_afi0__AFI_RDQOS = 32'h00000000; +parameter mask_afi0__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi0__AFI_RDDATAFIFO_LEVEL = 32'hF800800C; +parameter val_afi0__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi0__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi0__AFI_RDDEBUG = 32'hF8008010; +parameter val_afi0__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi0__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi0__AFI_WRCHAN_CTRL = 32'hF8008014; +parameter val_afi0__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi0__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi0__AFI_WRCHAN_ISSUINGCAP = 32'hF8008018; +parameter val_afi0__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi0__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi0__AFI_WRQOS = 32'hF800801C; +parameter val_afi0__AFI_WRQOS = 32'h00000000; +parameter mask_afi0__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi0__AFI_WRDATAFIFO_LEVEL = 32'hF8008020; +parameter val_afi0__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi0__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi0__AFI_WRDEBUG = 32'hF8008024; +parameter val_afi0__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi0__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi1 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi1__AFI_RDCHAN_CTRL = 32'hF8009000; +parameter val_afi1__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi1__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi1__AFI_RDCHAN_ISSUINGCAP = 32'hF8009004; +parameter val_afi1__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi1__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi1__AFI_RDQOS = 32'hF8009008; +parameter val_afi1__AFI_RDQOS = 32'h00000000; +parameter mask_afi1__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi1__AFI_RDDATAFIFO_LEVEL = 32'hF800900C; +parameter val_afi1__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi1__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi1__AFI_RDDEBUG = 32'hF8009010; +parameter val_afi1__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi1__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi1__AFI_WRCHAN_CTRL = 32'hF8009014; +parameter val_afi1__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi1__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi1__AFI_WRCHAN_ISSUINGCAP = 32'hF8009018; +parameter val_afi1__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi1__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi1__AFI_WRQOS = 32'hF800901C; +parameter val_afi1__AFI_WRQOS = 32'h00000000; +parameter mask_afi1__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi1__AFI_WRDATAFIFO_LEVEL = 32'hF8009020; +parameter val_afi1__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi1__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi1__AFI_WRDEBUG = 32'hF8009024; +parameter val_afi1__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi1__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi2 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi2__AFI_RDCHAN_CTRL = 32'hF800A000; +parameter val_afi2__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi2__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi2__AFI_RDCHAN_ISSUINGCAP = 32'hF800A004; +parameter val_afi2__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi2__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi2__AFI_RDQOS = 32'hF800A008; +parameter val_afi2__AFI_RDQOS = 32'h00000000; +parameter mask_afi2__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi2__AFI_RDDATAFIFO_LEVEL = 32'hF800A00C; +parameter val_afi2__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi2__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi2__AFI_RDDEBUG = 32'hF800A010; +parameter val_afi2__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi2__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi2__AFI_WRCHAN_CTRL = 32'hF800A014; +parameter val_afi2__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi2__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi2__AFI_WRCHAN_ISSUINGCAP = 32'hF800A018; +parameter val_afi2__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi2__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi2__AFI_WRQOS = 32'hF800A01C; +parameter val_afi2__AFI_WRQOS = 32'h00000000; +parameter mask_afi2__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi2__AFI_WRDATAFIFO_LEVEL = 32'hF800A020; +parameter val_afi2__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi2__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi2__AFI_WRDEBUG = 32'hF800A024; +parameter val_afi2__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi2__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module afi3 AFI +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter afi3__AFI_RDCHAN_CTRL = 32'hF800B000; +parameter val_afi3__AFI_RDCHAN_CTRL = 32'h00000000; +parameter mask_afi3__AFI_RDCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi3__AFI_RDCHAN_ISSUINGCAP = 32'hF800B004; +parameter val_afi3__AFI_RDCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi3__AFI_RDCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi3__AFI_RDQOS = 32'hF800B008; +parameter val_afi3__AFI_RDQOS = 32'h00000000; +parameter mask_afi3__AFI_RDQOS = 32'hFFFFFFFF; + +parameter afi3__AFI_RDDATAFIFO_LEVEL = 32'hF800B00C; +parameter val_afi3__AFI_RDDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi3__AFI_RDDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi3__AFI_RDDEBUG = 32'hF800B010; +parameter val_afi3__AFI_RDDEBUG = 32'h00000000; +parameter mask_afi3__AFI_RDDEBUG = 32'hFFFFFFFF; + +parameter afi3__AFI_WRCHAN_CTRL = 32'hF800B014; +parameter val_afi3__AFI_WRCHAN_CTRL = 32'h00000F00; +parameter mask_afi3__AFI_WRCHAN_CTRL = 32'hFFFFFFFF; + +parameter afi3__AFI_WRCHAN_ISSUINGCAP = 32'hF800B018; +parameter val_afi3__AFI_WRCHAN_ISSUINGCAP = 32'h00000007; +parameter mask_afi3__AFI_WRCHAN_ISSUINGCAP = 32'hFFFFFFFF; + +parameter afi3__AFI_WRQOS = 32'hF800B01C; +parameter val_afi3__AFI_WRQOS = 32'h00000000; +parameter mask_afi3__AFI_WRQOS = 32'hFFFFFFFF; + +parameter afi3__AFI_WRDATAFIFO_LEVEL = 32'hF800B020; +parameter val_afi3__AFI_WRDATAFIFO_LEVEL = 32'h00000000; +parameter mask_afi3__AFI_WRDATAFIFO_LEVEL = 32'hFFFFFFFF; + +parameter afi3__AFI_WRDEBUG = 32'hF800B024; +parameter val_afi3__AFI_WRDEBUG = 32'h00000000; +parameter mask_afi3__AFI_WRDEBUG = 32'hFFFFFFFF; + + +// ************************************************************ +// Module can0 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter can0__SRR = 32'hE0008000; +parameter val_can0__SRR = 32'h00000000; +parameter mask_can0__SRR = 32'hFFFFFFFF; + +parameter can0__MSR = 32'hE0008004; +parameter val_can0__MSR = 32'h00000000; +parameter mask_can0__MSR = 32'hFFFFFFFF; + +parameter can0__BRPR = 32'hE0008008; +parameter val_can0__BRPR = 32'h00000000; +parameter mask_can0__BRPR = 32'hFFFFFFFF; + +parameter can0__BTR = 32'hE000800C; +parameter val_can0__BTR = 32'h00000000; +parameter mask_can0__BTR = 32'hFFFFFFFF; + +parameter can0__ECR = 32'hE0008010; +parameter val_can0__ECR = 32'h00000000; +parameter mask_can0__ECR = 32'hFFFFFFFF; + +parameter can0__ESR = 32'hE0008014; +parameter val_can0__ESR = 32'h00000000; +parameter mask_can0__ESR = 32'hFFFFFFFF; + +parameter can0__SR = 32'hE0008018; +parameter val_can0__SR = 32'h00000001; +parameter mask_can0__SR = 32'hFFFFFFFF; + +parameter can0__ISR = 32'hE000801C; +parameter val_can0__ISR = 32'h00006000; +parameter mask_can0__ISR = 32'hFFFFFFFF; + +parameter can0__IER = 32'hE0008020; +parameter val_can0__IER = 32'h00000000; +parameter mask_can0__IER = 32'hFFFFFFFF; + +parameter can0__ICR = 32'hE0008024; +parameter val_can0__ICR = 32'h00000000; +parameter mask_can0__ICR = 32'hFFFFFFFF; + +parameter can0__TCR = 32'hE0008028; +parameter val_can0__TCR = 32'h00000000; +parameter mask_can0__TCR = 32'hFFFFFFFF; + +parameter can0__WIR = 32'hE000802C; +parameter val_can0__WIR = 32'h00003F3F; +parameter mask_can0__WIR = 32'hFFFFFFFF; + +parameter can0__TXFIFO_ID = 32'hE0008030; +parameter val_can0__TXFIFO_ID = 32'h00000000; +parameter mask_can0__TXFIFO_ID = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DLC = 32'hE0008034; +parameter val_can0__TXFIFO_DLC = 32'h00000000; +parameter mask_can0__TXFIFO_DLC = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DATA1 = 32'hE0008038; +parameter val_can0__TXFIFO_DATA1 = 32'h00000000; +parameter mask_can0__TXFIFO_DATA1 = 32'hFFFFFFFF; + +parameter can0__TXFIFO_DATA2 = 32'hE000803C; +parameter val_can0__TXFIFO_DATA2 = 32'h00000000; +parameter mask_can0__TXFIFO_DATA2 = 32'hFFFFFFFF; + +parameter can0__TXHPB_ID = 32'hE0008040; +parameter val_can0__TXHPB_ID = 32'h00000000; +parameter mask_can0__TXHPB_ID = 32'hFFFFFFFF; + +parameter can0__TXHPB_DLC = 32'hE0008044; +parameter val_can0__TXHPB_DLC = 32'h00000000; +parameter mask_can0__TXHPB_DLC = 32'hFFFFFFFF; + +parameter can0__TXHPB_DATA1 = 32'hE0008048; +parameter val_can0__TXHPB_DATA1 = 32'h00000000; +parameter mask_can0__TXHPB_DATA1 = 32'hFFFFFFFF; + +parameter can0__TXHPB_DATA2 = 32'hE000804C; +parameter val_can0__TXHPB_DATA2 = 32'h00000000; +parameter mask_can0__TXHPB_DATA2 = 32'hFFFFFFFF; + +parameter can0__RXFIFO_ID = 32'hE0008050; +parameter val_can0__RXFIFO_ID = 32'h00000000; +parameter mask_can0__RXFIFO_ID = 32'h00000000; + +parameter can0__RXFIFO_DLC = 32'hE0008054; +parameter val_can0__RXFIFO_DLC = 32'h00000000; +parameter mask_can0__RXFIFO_DLC = 32'h00000000; + +parameter can0__RXFIFO_DATA1 = 32'hE0008058; +parameter val_can0__RXFIFO_DATA1 = 32'h00000000; +parameter mask_can0__RXFIFO_DATA1 = 32'h00000000; + +parameter can0__RXFIFO_DATA2 = 32'hE000805C; +parameter val_can0__RXFIFO_DATA2 = 32'h00000000; +parameter mask_can0__RXFIFO_DATA2 = 32'h00000000; + +parameter can0__AFR = 32'hE0008060; +parameter val_can0__AFR = 32'h00000000; +parameter mask_can0__AFR = 32'hFFFFFFFF; + +parameter can0__AFMR1 = 32'hE0008064; +parameter val_can0__AFMR1 = 32'h00000000; +parameter mask_can0__AFMR1 = 32'h00000000; + +parameter can0__AFIR1 = 32'hE0008068; +parameter val_can0__AFIR1 = 32'h00000000; +parameter mask_can0__AFIR1 = 32'h00000000; + +parameter can0__AFMR2 = 32'hE000806C; +parameter val_can0__AFMR2 = 32'h00000000; +parameter mask_can0__AFMR2 = 32'h00000000; + +parameter can0__AFIR2 = 32'hE0008070; +parameter val_can0__AFIR2 = 32'h00000000; +parameter mask_can0__AFIR2 = 32'h00000000; + +parameter can0__AFMR3 = 32'hE0008074; +parameter val_can0__AFMR3 = 32'h00000000; +parameter mask_can0__AFMR3 = 32'h00000000; + +parameter can0__AFIR3 = 32'hE0008078; +parameter val_can0__AFIR3 = 32'h00000000; +parameter mask_can0__AFIR3 = 32'h00000000; + +parameter can0__AFMR4 = 32'hE000807C; +parameter val_can0__AFMR4 = 32'h00000000; +parameter mask_can0__AFMR4 = 32'h00000000; + +parameter can0__AFIR4 = 32'hE0008080; +parameter val_can0__AFIR4 = 32'h00000000; +parameter mask_can0__AFIR4 = 32'h00000000; + + +// ************************************************************ +// Module can1 can +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter can1__SRR = 32'hE0009000; +parameter val_can1__SRR = 32'h00000000; +parameter mask_can1__SRR = 32'hFFFFFFFF; + +parameter can1__MSR = 32'hE0009004; +parameter val_can1__MSR = 32'h00000000; +parameter mask_can1__MSR = 32'hFFFFFFFF; + +parameter can1__BRPR = 32'hE0009008; +parameter val_can1__BRPR = 32'h00000000; +parameter mask_can1__BRPR = 32'hFFFFFFFF; + +parameter can1__BTR = 32'hE000900C; +parameter val_can1__BTR = 32'h00000000; +parameter mask_can1__BTR = 32'hFFFFFFFF; + +parameter can1__ECR = 32'hE0009010; +parameter val_can1__ECR = 32'h00000000; +parameter mask_can1__ECR = 32'hFFFFFFFF; + +parameter can1__ESR = 32'hE0009014; +parameter val_can1__ESR = 32'h00000000; +parameter mask_can1__ESR = 32'hFFFFFFFF; + +parameter can1__SR = 32'hE0009018; +parameter val_can1__SR = 32'h00000001; +parameter mask_can1__SR = 32'hFFFFFFFF; + +parameter can1__ISR = 32'hE000901C; +parameter val_can1__ISR = 32'h00006000; +parameter mask_can1__ISR = 32'hFFFFFFFF; + +parameter can1__IER = 32'hE0009020; +parameter val_can1__IER = 32'h00000000; +parameter mask_can1__IER = 32'hFFFFFFFF; + +parameter can1__ICR = 32'hE0009024; +parameter val_can1__ICR = 32'h00000000; +parameter mask_can1__ICR = 32'hFFFFFFFF; + +parameter can1__TCR = 32'hE0009028; +parameter val_can1__TCR = 32'h00000000; +parameter mask_can1__TCR = 32'hFFFFFFFF; + +parameter can1__WIR = 32'hE000902C; +parameter val_can1__WIR = 32'h00003F3F; +parameter mask_can1__WIR = 32'hFFFFFFFF; + +parameter can1__TXFIFO_ID = 32'hE0009030; +parameter val_can1__TXFIFO_ID = 32'h00000000; +parameter mask_can1__TXFIFO_ID = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DLC = 32'hE0009034; +parameter val_can1__TXFIFO_DLC = 32'h00000000; +parameter mask_can1__TXFIFO_DLC = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DATA1 = 32'hE0009038; +parameter val_can1__TXFIFO_DATA1 = 32'h00000000; +parameter mask_can1__TXFIFO_DATA1 = 32'hFFFFFFFF; + +parameter can1__TXFIFO_DATA2 = 32'hE000903C; +parameter val_can1__TXFIFO_DATA2 = 32'h00000000; +parameter mask_can1__TXFIFO_DATA2 = 32'hFFFFFFFF; + +parameter can1__TXHPB_ID = 32'hE0009040; +parameter val_can1__TXHPB_ID = 32'h00000000; +parameter mask_can1__TXHPB_ID = 32'hFFFFFFFF; + +parameter can1__TXHPB_DLC = 32'hE0009044; +parameter val_can1__TXHPB_DLC = 32'h00000000; +parameter mask_can1__TXHPB_DLC = 32'hFFFFFFFF; + +parameter can1__TXHPB_DATA1 = 32'hE0009048; +parameter val_can1__TXHPB_DATA1 = 32'h00000000; +parameter mask_can1__TXHPB_DATA1 = 32'hFFFFFFFF; + +parameter can1__TXHPB_DATA2 = 32'hE000904C; +parameter val_can1__TXHPB_DATA2 = 32'h00000000; +parameter mask_can1__TXHPB_DATA2 = 32'hFFFFFFFF; + +parameter can1__RXFIFO_ID = 32'hE0009050; +parameter val_can1__RXFIFO_ID = 32'h00000000; +parameter mask_can1__RXFIFO_ID = 32'h00000000; + +parameter can1__RXFIFO_DLC = 32'hE0009054; +parameter val_can1__RXFIFO_DLC = 32'h00000000; +parameter mask_can1__RXFIFO_DLC = 32'h00000000; + +parameter can1__RXFIFO_DATA1 = 32'hE0009058; +parameter val_can1__RXFIFO_DATA1 = 32'h00000000; +parameter mask_can1__RXFIFO_DATA1 = 32'h00000000; + +parameter can1__RXFIFO_DATA2 = 32'hE000905C; +parameter val_can1__RXFIFO_DATA2 = 32'h00000000; +parameter mask_can1__RXFIFO_DATA2 = 32'h00000000; + +parameter can1__AFR = 32'hE0009060; +parameter val_can1__AFR = 32'h00000000; +parameter mask_can1__AFR = 32'hFFFFFFFF; + +parameter can1__AFMR1 = 32'hE0009064; +parameter val_can1__AFMR1 = 32'h00000000; +parameter mask_can1__AFMR1 = 32'h00000000; + +parameter can1__AFIR1 = 32'hE0009068; +parameter val_can1__AFIR1 = 32'h00000000; +parameter mask_can1__AFIR1 = 32'h00000000; + +parameter can1__AFMR2 = 32'hE000906C; +parameter val_can1__AFMR2 = 32'h00000000; +parameter mask_can1__AFMR2 = 32'h00000000; + +parameter can1__AFIR2 = 32'hE0009070; +parameter val_can1__AFIR2 = 32'h00000000; +parameter mask_can1__AFIR2 = 32'h00000000; + +parameter can1__AFMR3 = 32'hE0009074; +parameter val_can1__AFMR3 = 32'h00000000; +parameter mask_can1__AFMR3 = 32'h00000000; + +parameter can1__AFIR3 = 32'hE0009078; +parameter val_can1__AFIR3 = 32'h00000000; +parameter mask_can1__AFIR3 = 32'h00000000; + +parameter can1__AFMR4 = 32'hE000907C; +parameter val_can1__AFMR4 = 32'h00000000; +parameter mask_can1__AFMR4 = 32'h00000000; + +parameter can1__AFIR4 = 32'hE0009080; +parameter val_can1__AFIR4 = 32'h00000000; +parameter mask_can1__AFIR4 = 32'h00000000; + + +// ************************************************************ +// Module ddrc ddrc +// doc version: 1.25 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ddrc__ddrc_ctrl = 32'hF8006000; +parameter val_ddrc__ddrc_ctrl = 32'h00000200; +parameter mask_ddrc__ddrc_ctrl = 32'hFFFFFFFF; + +parameter ddrc__Two_rank_cfg = 32'hF8006004; +parameter val_ddrc__Two_rank_cfg = 32'h000C1076; +parameter mask_ddrc__Two_rank_cfg = 32'h1FFFFFFF; + +parameter ddrc__HPR_reg = 32'hF8006008; +parameter val_ddrc__HPR_reg = 32'h03C0780F; +parameter mask_ddrc__HPR_reg = 32'h03FFFFFF; + +parameter ddrc__LPR_reg = 32'hF800600C; +parameter val_ddrc__LPR_reg = 32'h03C0780F; +parameter mask_ddrc__LPR_reg = 32'h03FFFFFF; + +parameter ddrc__WR_reg = 32'hF8006010; +parameter val_ddrc__WR_reg = 32'h0007F80F; +parameter mask_ddrc__WR_reg = 32'h03FFFFFF; + +parameter ddrc__DRAM_param_reg0 = 32'hF8006014; +parameter val_ddrc__DRAM_param_reg0 = 32'h00041016; +parameter mask_ddrc__DRAM_param_reg0 = 32'h001FFFFF; + +parameter ddrc__DRAM_param_reg1 = 32'hF8006018; +parameter val_ddrc__DRAM_param_reg1 = 32'h351B48D9; +parameter mask_ddrc__DRAM_param_reg1 = 32'hF7FFFFFF; + +parameter ddrc__DRAM_param_reg2 = 32'hF800601C; +parameter val_ddrc__DRAM_param_reg2 = 32'h83015904; +parameter mask_ddrc__DRAM_param_reg2 = 32'hFFFFFFFF; + +parameter ddrc__DRAM_param_reg3 = 32'hF8006020; +parameter val_ddrc__DRAM_param_reg3 = 32'h250882D0; +parameter mask_ddrc__DRAM_param_reg3 = 32'hFFFFFFFF; + +parameter ddrc__DRAM_param_reg4 = 32'hF8006024; +parameter val_ddrc__DRAM_param_reg4 = 32'h0000003C; +parameter mask_ddrc__DRAM_param_reg4 = 32'h0FFFFFFF; + +parameter ddrc__DRAM_init_param = 32'hF8006028; +parameter val_ddrc__DRAM_init_param = 32'h00002007; +parameter mask_ddrc__DRAM_init_param = 32'h00003FFF; + +parameter ddrc__DRAM_EMR_reg = 32'hF800602C; +parameter val_ddrc__DRAM_EMR_reg = 32'h00000008; +parameter mask_ddrc__DRAM_EMR_reg = 32'hFFFFFFFF; + +parameter ddrc__DRAM_EMR_MR_reg = 32'hF8006030; +parameter val_ddrc__DRAM_EMR_MR_reg = 32'h00000940; +parameter mask_ddrc__DRAM_EMR_MR_reg = 32'hFFFFFFFF; + +parameter ddrc__DRAM_burst8_rdwr = 32'hF8006034; +parameter val_ddrc__DRAM_burst8_rdwr = 32'h00020034; +parameter mask_ddrc__DRAM_burst8_rdwr = 32'h1FFFFFFF; + +parameter ddrc__DRAM_disable_DQ = 32'hF8006038; +parameter val_ddrc__DRAM_disable_DQ = 32'h00000000; +parameter mask_ddrc__DRAM_disable_DQ = 32'h00001FFF; + +parameter ddrc__DRAM_addr_map_bank = 32'hF800603C; +parameter val_ddrc__DRAM_addr_map_bank = 32'h00000F77; +parameter mask_ddrc__DRAM_addr_map_bank = 32'h000FFFFF; + +parameter ddrc__DRAM_addr_map_col = 32'hF8006040; +parameter val_ddrc__DRAM_addr_map_col = 32'hFFF00000; +parameter mask_ddrc__DRAM_addr_map_col = 32'hFFFFFFFF; + +parameter ddrc__DRAM_addr_map_row = 32'hF8006044; +parameter val_ddrc__DRAM_addr_map_row = 32'h0FF55555; +parameter mask_ddrc__DRAM_addr_map_row = 32'h0FFFFFFF; + +parameter ddrc__DRAM_ODT_reg = 32'hF8006048; +parameter val_ddrc__DRAM_ODT_reg = 32'h00000249; +parameter mask_ddrc__DRAM_ODT_reg = 32'h3FFFFFFF; + +parameter ddrc__phy_dbg_reg = 32'hF800604C; +parameter val_ddrc__phy_dbg_reg = 32'h00000000; +parameter mask_ddrc__phy_dbg_reg = 32'h000FFFFF; + +parameter ddrc__phy_cmd_timeout_rddata_cpt = 32'hF8006050; +parameter val_ddrc__phy_cmd_timeout_rddata_cpt = 32'h00010200; +parameter mask_ddrc__phy_cmd_timeout_rddata_cpt = 32'hFFFFFFFF; + +parameter ddrc__mode_sts_reg = 32'hF8006054; +parameter val_ddrc__mode_sts_reg = 32'h00000000; +parameter mask_ddrc__mode_sts_reg = 32'h001FFFFF; + +parameter ddrc__DLL_calib = 32'hF8006058; +parameter val_ddrc__DLL_calib = 32'h00000101; +parameter mask_ddrc__DLL_calib = 32'h0001FFFF; + +parameter ddrc__ODT_delay_hold = 32'hF800605C; +parameter val_ddrc__ODT_delay_hold = 32'h00000023; +parameter mask_ddrc__ODT_delay_hold = 32'h0000FFFF; + +parameter ddrc__ctrl_reg1 = 32'hF8006060; +parameter val_ddrc__ctrl_reg1 = 32'h0000003E; +parameter mask_ddrc__ctrl_reg1 = 32'h00001FFF; + +parameter ddrc__ctrl_reg2 = 32'hF8006064; +parameter val_ddrc__ctrl_reg2 = 32'h00020000; +parameter mask_ddrc__ctrl_reg2 = 32'h0003FFFF; + +parameter ddrc__ctrl_reg3 = 32'hF8006068; +parameter val_ddrc__ctrl_reg3 = 32'h00284027; +parameter mask_ddrc__ctrl_reg3 = 32'h03FFFFFF; + +parameter ddrc__ctrl_reg4 = 32'hF800606C; +parameter val_ddrc__ctrl_reg4 = 32'h00001610; +parameter mask_ddrc__ctrl_reg4 = 32'h0000FFFF; + +parameter ddrc__ctrl_reg5 = 32'hF8006078; +parameter val_ddrc__ctrl_reg5 = 32'h00455111; +parameter mask_ddrc__ctrl_reg5 = 32'hFFFFFFFF; + +parameter ddrc__ctrl_reg6 = 32'hF800607C; +parameter val_ddrc__ctrl_reg6 = 32'h00032222; +parameter mask_ddrc__ctrl_reg6 = 32'hFFFFFFFF; + +parameter ddrc__CHE_REFRESH_TIMER01 = 32'hF80060A0; +parameter val_ddrc__CHE_REFRESH_TIMER01 = 32'h00008000; +parameter mask_ddrc__CHE_REFRESH_TIMER01 = 32'h00FFFFFF; + +parameter ddrc__CHE_T_ZQ = 32'hF80060A4; +parameter val_ddrc__CHE_T_ZQ = 32'h10300802; +parameter mask_ddrc__CHE_T_ZQ = 32'hFFFFFFFF; + +parameter ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'hF80060A8; +parameter val_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0020003A; +parameter mask_ddrc__CHE_T_ZQ_Short_Interval_Reg = 32'h0FFFFFFF; + +parameter ddrc__deep_pwrdwn_reg = 32'hF80060AC; +parameter val_ddrc__deep_pwrdwn_reg = 32'h00000000; +parameter mask_ddrc__deep_pwrdwn_reg = 32'h000001FF; + +parameter ddrc__reg_2c = 32'hF80060B0; +parameter val_ddrc__reg_2c = 32'h00000000; +parameter mask_ddrc__reg_2c = 32'h1FFFFFFF; + +parameter ddrc__reg_2d = 32'hF80060B4; +parameter val_ddrc__reg_2d = 32'h00000200; +parameter mask_ddrc__reg_2d = 32'h000007FF; + +parameter ddrc__dfi_timing = 32'hF80060B8; +parameter val_ddrc__dfi_timing = 32'h00200067; +parameter mask_ddrc__dfi_timing = 32'h01FFFFFF; + +parameter ddrc__refresh_timer_2 = 32'hF80060BC; +parameter val_ddrc__refresh_timer_2 = 32'h00000000; +parameter mask_ddrc__refresh_timer_2 = 32'h00FFFFFF; + +parameter ddrc__nc_timing = 32'hF80060C0; +parameter val_ddrc__nc_timing = 32'h00000000; +parameter mask_ddrc__nc_timing = 32'h003FFFFF; + +parameter ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'hF80060C4; +parameter val_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CONTROL_REG_OFFSET = 32'h00000003; + +parameter ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'hF80060C8; +parameter val_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_LOG_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'hF80060CC; +parameter val_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060D0; +parameter val_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060D4; +parameter val_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060D8; +parameter val_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_CORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'hF80060DC; +parameter val_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_LOG_REG_OFFSET = 32'h00000001; + +parameter ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'hF80060E0; +parameter val_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_ADDR_REG_OFFSET = 32'h7FFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hF80060E4; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hF80060E8; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'hF80060EC; +parameter val_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET = 32'h000000FF; + +parameter ddrc__CHE_ECC_STATS_REG_OFFSET = 32'hF80060F0; +parameter val_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_STATS_REG_OFFSET = 32'h0000FFFF; + +parameter ddrc__ECC_scrub = 32'hF80060F4; +parameter val_ddrc__ECC_scrub = 32'h00000008; +parameter mask_ddrc__ECC_scrub = 32'h0000000F; + +parameter ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hF80060F8; +parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hF80060FC; +parameter val_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'h00000000; +parameter mask_ddrc__CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET = 32'hFFFFFFFF; + +parameter ddrc__phy_rcvr_enable = 32'hF8006114; +parameter val_ddrc__phy_rcvr_enable = 32'h00000000; +parameter mask_ddrc__phy_rcvr_enable = 32'h000000FF; + +parameter ddrc__PHY_Config0 = 32'hF8006118; +parameter val_ddrc__PHY_Config0 = 32'h40000001; +parameter mask_ddrc__PHY_Config0 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config1 = 32'hF800611C; +parameter val_ddrc__PHY_Config1 = 32'h40000001; +parameter mask_ddrc__PHY_Config1 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config2 = 32'hF8006120; +parameter val_ddrc__PHY_Config2 = 32'h40000001; +parameter mask_ddrc__PHY_Config2 = 32'h7FFFFFFF; + +parameter ddrc__PHY_Config3 = 32'hF8006124; +parameter val_ddrc__PHY_Config3 = 32'h40000001; +parameter mask_ddrc__PHY_Config3 = 32'h7FFFFFFF; + +parameter ddrc__phy_init_ratio0 = 32'hF800612C; +parameter val_ddrc__phy_init_ratio0 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio0 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio1 = 32'hF8006130; +parameter val_ddrc__phy_init_ratio1 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio1 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio2 = 32'hF8006134; +parameter val_ddrc__phy_init_ratio2 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio2 = 32'h000FFFFF; + +parameter ddrc__phy_init_ratio3 = 32'hF8006138; +parameter val_ddrc__phy_init_ratio3 = 32'h00000000; +parameter mask_ddrc__phy_init_ratio3 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg0 = 32'hF8006140; +parameter val_ddrc__phy_rd_dqs_cfg0 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg0 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg1 = 32'hF8006144; +parameter val_ddrc__phy_rd_dqs_cfg1 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg1 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg2 = 32'hF8006148; +parameter val_ddrc__phy_rd_dqs_cfg2 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg2 = 32'h000FFFFF; + +parameter ddrc__phy_rd_dqs_cfg3 = 32'hF800614C; +parameter val_ddrc__phy_rd_dqs_cfg3 = 32'h00000040; +parameter mask_ddrc__phy_rd_dqs_cfg3 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg0 = 32'hF8006154; +parameter val_ddrc__phy_wr_dqs_cfg0 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg0 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg1 = 32'hF8006158; +parameter val_ddrc__phy_wr_dqs_cfg1 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg1 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg2 = 32'hF800615C; +parameter val_ddrc__phy_wr_dqs_cfg2 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg2 = 32'h000FFFFF; + +parameter ddrc__phy_wr_dqs_cfg3 = 32'hF8006160; +parameter val_ddrc__phy_wr_dqs_cfg3 = 32'h00000000; +parameter mask_ddrc__phy_wr_dqs_cfg3 = 32'h000FFFFF; + +parameter ddrc__phy_we_cfg0 = 32'hF8006168; +parameter val_ddrc__phy_we_cfg0 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg0 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg1 = 32'hF800616C; +parameter val_ddrc__phy_we_cfg1 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg1 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg2 = 32'hF8006170; +parameter val_ddrc__phy_we_cfg2 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg2 = 32'h001FFFFF; + +parameter ddrc__phy_we_cfg3 = 32'hF8006174; +parameter val_ddrc__phy_we_cfg3 = 32'h00000040; +parameter mask_ddrc__phy_we_cfg3 = 32'h001FFFFF; + +parameter ddrc__wr_data_slv0 = 32'hF800617C; +parameter val_ddrc__wr_data_slv0 = 32'h00000080; +parameter mask_ddrc__wr_data_slv0 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv1 = 32'hF8006180; +parameter val_ddrc__wr_data_slv1 = 32'h00000080; +parameter mask_ddrc__wr_data_slv1 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv2 = 32'hF8006184; +parameter val_ddrc__wr_data_slv2 = 32'h00000080; +parameter mask_ddrc__wr_data_slv2 = 32'h000FFFFF; + +parameter ddrc__wr_data_slv3 = 32'hF8006188; +parameter val_ddrc__wr_data_slv3 = 32'h00000080; +parameter mask_ddrc__wr_data_slv3 = 32'h000FFFFF; + +parameter ddrc__reg_64 = 32'hF8006190; +parameter val_ddrc__reg_64 = 32'h10020000; +parameter mask_ddrc__reg_64 = 32'hFFFFFFFF; + +parameter ddrc__reg_65 = 32'hF8006194; +parameter val_ddrc__reg_65 = 32'h00000000; +parameter mask_ddrc__reg_65 = 32'h000FFFFF; + +parameter ddrc__reg69_6a0 = 32'hF80061A4; +parameter val_ddrc__reg69_6a0 = 32'h000F0000; +parameter mask_ddrc__reg69_6a0 = 32'h1FFFFFFF; + +parameter ddrc__reg69_6a1 = 32'hF80061A8; +parameter val_ddrc__reg69_6a1 = 32'h000F0000; +parameter mask_ddrc__reg69_6a1 = 32'h1FFFFFFF; + +parameter ddrc__reg6c_6d2 = 32'hF80061B0; +parameter val_ddrc__reg6c_6d2 = 32'h000F0000; +parameter mask_ddrc__reg6c_6d2 = 32'h1FFFFFFF; + +parameter ddrc__reg6c_6d3 = 32'hF80061B4; +parameter val_ddrc__reg6c_6d3 = 32'h000F0000; +parameter mask_ddrc__reg6c_6d3 = 32'h1FFFFFFF; + +parameter ddrc__reg6e_710 = 32'hF80061B8; +parameter val_ddrc__reg6e_710 = 32'h00000000; +parameter mask_ddrc__reg6e_710 = 32'h00000000; + +parameter ddrc__reg6e_711 = 32'hF80061BC; +parameter val_ddrc__reg6e_711 = 32'h00000000; +parameter mask_ddrc__reg6e_711 = 32'h00000000; + +parameter ddrc__reg6e_712 = 32'hF80061C0; +parameter val_ddrc__reg6e_712 = 32'h00000000; +parameter mask_ddrc__reg6e_712 = 32'h00000000; + +parameter ddrc__reg6e_713 = 32'hF80061C4; +parameter val_ddrc__reg6e_713 = 32'h00000000; +parameter mask_ddrc__reg6e_713 = 32'h00000000; + +parameter ddrc__phy_dll_sts0 = 32'hF80061CC; +parameter val_ddrc__phy_dll_sts0 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts0 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts1 = 32'hF80061D0; +parameter val_ddrc__phy_dll_sts1 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts1 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts2 = 32'hF80061D4; +parameter val_ddrc__phy_dll_sts2 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts2 = 32'h07FFFFFF; + +parameter ddrc__phy_dll_sts3 = 32'hF80061D8; +parameter val_ddrc__phy_dll_sts3 = 32'h00000000; +parameter mask_ddrc__phy_dll_sts3 = 32'h07FFFFFF; + +parameter ddrc__dll_lock_sts = 32'hF80061E0; +parameter val_ddrc__dll_lock_sts = 32'h00000000; +parameter mask_ddrc__dll_lock_sts = 32'h00FFFFFF; + +parameter ddrc__phy_ctrl_sts = 32'hF80061E4; +parameter val_ddrc__phy_ctrl_sts = 32'h00000000; +parameter mask_ddrc__phy_ctrl_sts = 32'h3FF80000; + +parameter ddrc__phy_ctrl_sts_reg2 = 32'hF80061E8; +parameter val_ddrc__phy_ctrl_sts_reg2 = 32'h00000000; +parameter mask_ddrc__phy_ctrl_sts_reg2 = 32'h07FFFFFF; + +parameter ddrc__axi_id = 32'hF8006200; +parameter val_ddrc__axi_id = 32'h00153042; +parameter mask_ddrc__axi_id = 32'h03FFFFFF; + +parameter ddrc__page_mask = 32'hF8006204; +parameter val_ddrc__page_mask = 32'h00000000; +parameter mask_ddrc__page_mask = 32'hFFFFFFFF; + +parameter ddrc__axi_priority_wr_port0 = 32'hF8006208; +parameter val_ddrc__axi_priority_wr_port0 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port0 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port1 = 32'hF800620C; +parameter val_ddrc__axi_priority_wr_port1 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port1 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port2 = 32'hF8006210; +parameter val_ddrc__axi_priority_wr_port2 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port2 = 32'h000FFFFF; + +parameter ddrc__axi_priority_wr_port3 = 32'hF8006214; +parameter val_ddrc__axi_priority_wr_port3 = 32'h000803FF; +parameter mask_ddrc__axi_priority_wr_port3 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port0 = 32'hF8006218; +parameter val_ddrc__axi_priority_rd_port0 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port0 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port1 = 32'hF800621C; +parameter val_ddrc__axi_priority_rd_port1 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port1 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port2 = 32'hF8006220; +parameter val_ddrc__axi_priority_rd_port2 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port2 = 32'h000FFFFF; + +parameter ddrc__axi_priority_rd_port3 = 32'hF8006224; +parameter val_ddrc__axi_priority_rd_port3 = 32'h000003FF; +parameter mask_ddrc__axi_priority_rd_port3 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg0 = 32'hF8006248; +parameter val_ddrc__AHB_priority_cfg0 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg0 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg1 = 32'hF800624C; +parameter val_ddrc__AHB_priority_cfg1 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg1 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg2 = 32'hF8006250; +parameter val_ddrc__AHB_priority_cfg2 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg2 = 32'h000FFFFF; + +parameter ddrc__AHB_priority_cfg3 = 32'hF8006254; +parameter val_ddrc__AHB_priority_cfg3 = 32'h000003FF; +parameter mask_ddrc__AHB_priority_cfg3 = 32'h000FFFFF; + +parameter ddrc__perf_mon0 = 32'hF8006260; +parameter val_ddrc__perf_mon0 = 32'h00000000; +parameter mask_ddrc__perf_mon0 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon1 = 32'hF8006264; +parameter val_ddrc__perf_mon1 = 32'h00000000; +parameter mask_ddrc__perf_mon1 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon2 = 32'hF8006268; +parameter val_ddrc__perf_mon2 = 32'h00000000; +parameter mask_ddrc__perf_mon2 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon3 = 32'hF800626C; +parameter val_ddrc__perf_mon3 = 32'h00000000; +parameter mask_ddrc__perf_mon3 = 32'h7FFFFFFF; + +parameter ddrc__perf_mon20 = 32'hF8006270; +parameter val_ddrc__perf_mon20 = 32'h00000000; +parameter mask_ddrc__perf_mon20 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon21 = 32'hF8006274; +parameter val_ddrc__perf_mon21 = 32'h00000000; +parameter mask_ddrc__perf_mon21 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon22 = 32'hF8006278; +parameter val_ddrc__perf_mon22 = 32'h00000000; +parameter mask_ddrc__perf_mon22 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon23 = 32'hF800627C; +parameter val_ddrc__perf_mon23 = 32'h00000000; +parameter mask_ddrc__perf_mon23 = 32'hFFFFFFFF; + +parameter ddrc__perf_mon30 = 32'hF8006280; +parameter val_ddrc__perf_mon30 = 32'h00000000; +parameter mask_ddrc__perf_mon30 = 32'h0000FFFF; + +parameter ddrc__perf_mon31 = 32'hF8006284; +parameter val_ddrc__perf_mon31 = 32'h00000000; +parameter mask_ddrc__perf_mon31 = 32'h0000FFFF; + +parameter ddrc__perf_mon32 = 32'hF8006288; +parameter val_ddrc__perf_mon32 = 32'h00000000; +parameter mask_ddrc__perf_mon32 = 32'h0000FFFF; + +parameter ddrc__perf_mon33 = 32'hF800628C; +parameter val_ddrc__perf_mon33 = 32'h00000000; +parameter mask_ddrc__perf_mon33 = 32'h0000FFFF; + +parameter ddrc__trusted_mem_cfg = 32'hF8006290; +parameter val_ddrc__trusted_mem_cfg = 32'h00000000; +parameter mask_ddrc__trusted_mem_cfg = 32'h0000FFFF; + +parameter ddrc__excl_access_cfg0 = 32'hF8006294; +parameter val_ddrc__excl_access_cfg0 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg0 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg1 = 32'hF8006298; +parameter val_ddrc__excl_access_cfg1 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg1 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg2 = 32'hF800629C; +parameter val_ddrc__excl_access_cfg2 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg2 = 32'h0003FFFF; + +parameter ddrc__excl_access_cfg3 = 32'hF80062A0; +parameter val_ddrc__excl_access_cfg3 = 32'h00000000; +parameter mask_ddrc__excl_access_cfg3 = 32'h0003FFFF; + +parameter ddrc__mode_reg_read = 32'hF80062A4; +parameter val_ddrc__mode_reg_read = 32'h00000000; +parameter mask_ddrc__mode_reg_read = 32'hFFFFFFFF; + +parameter ddrc__lpddr_ctrl0 = 32'hF80062A8; +parameter val_ddrc__lpddr_ctrl0 = 32'h00000000; +parameter mask_ddrc__lpddr_ctrl0 = 32'h00000FFF; + +parameter ddrc__lpddr_ctrl1 = 32'hF80062AC; +parameter val_ddrc__lpddr_ctrl1 = 32'h00000000; +parameter mask_ddrc__lpddr_ctrl1 = 32'hFFFFFFFF; + +parameter ddrc__lpddr_ctrl2 = 32'hF80062B0; +parameter val_ddrc__lpddr_ctrl2 = 32'h003C0015; +parameter mask_ddrc__lpddr_ctrl2 = 32'h003FFFFF; + +parameter ddrc__lpddr_ctrl3 = 32'hF80062B4; +parameter val_ddrc__lpddr_ctrl3 = 32'h00000601; +parameter mask_ddrc__lpddr_ctrl3 = 32'h0003FFFF; + +parameter ddrc__phy_wr_lvl_fsm = 32'hF80062B8; +parameter val_ddrc__phy_wr_lvl_fsm = 32'h00004444; +parameter mask_ddrc__phy_wr_lvl_fsm = 32'h00007FFF; + +parameter ddrc__phy_rd_lvl_fsm = 32'hF80062BC; +parameter val_ddrc__phy_rd_lvl_fsm = 32'h00008888; +parameter mask_ddrc__phy_rd_lvl_fsm = 32'h0000FFFF; + +parameter ddrc__phy_gate_lvl_fsm = 32'hF80062C0; +parameter val_ddrc__phy_gate_lvl_fsm = 32'h00004444; +parameter mask_ddrc__phy_gate_lvl_fsm = 32'h00007FFF; + + +// ************************************************************ +// Module debug_axim axim +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_axim__GLOBAL_CTRL = 32'hF880C000; +parameter val_debug_axim__GLOBAL_CTRL = 32'h00000002; +parameter mask_debug_axim__GLOBAL_CTRL = 32'h00000003; + +parameter debug_axim__GLOBAL_STATUS = 32'hF880C004; +parameter val_debug_axim__GLOBAL_STATUS = 32'h00001000; +parameter mask_debug_axim__GLOBAL_STATUS = 32'h00001FC3; + +parameter debug_axim__FILTER_CTRL = 32'hF880C010; +parameter val_debug_axim__FILTER_CTRL = 32'h00000000; +parameter mask_debug_axim__FILTER_CTRL = 32'h0000007F; + +parameter debug_axim__TRIGGER_CTRL = 32'hF880C020; +parameter val_debug_axim__TRIGGER_CTRL = 32'h00000000; +parameter mask_debug_axim__TRIGGER_CTRL = 32'h0000FFFF; + +parameter debug_axim__TRIGGER_STATUS = 32'hF880C024; +parameter val_debug_axim__TRIGGER_STATUS = 32'h00000000; +parameter mask_debug_axim__TRIGGER_STATUS = 32'h00000003; + +parameter debug_axim__PACKET_CTRL = 32'hF880C030; +parameter val_debug_axim__PACKET_CTRL = 32'h00070000; +parameter mask_debug_axim__PACKET_CTRL = 32'h0007FFFF; + +parameter debug_axim__TOUT_CTRL = 32'hF880C040; +parameter val_debug_axim__TOUT_CTRL = 32'h00000000; +parameter mask_debug_axim__TOUT_CTRL = 32'h0000007F; + +parameter debug_axim__TOUT_THRESH = 32'hF880C044; +parameter val_debug_axim__TOUT_THRESH = 32'h00008000; +parameter mask_debug_axim__TOUT_THRESH = 32'hFFFFFFFF; + +parameter debug_axim__FIFO_CURRENT = 32'hF880C050; +parameter val_debug_axim__FIFO_CURRENT = 32'h80000000; +parameter mask_debug_axim__FIFO_CURRENT = 32'hFFFFFFFF; + +parameter debug_axim__FIFO_HYSTER = 32'hF880C054; +parameter val_debug_axim__FIFO_HYSTER = 32'h00000100; +parameter mask_debug_axim__FIFO_HYSTER = 32'h000003FF; + +parameter debug_axim__SYNC_CURRENT = 32'hF880C060; +parameter val_debug_axim__SYNC_CURRENT = 32'h00000000; +parameter mask_debug_axim__SYNC_CURRENT = 32'h00000FFF; + +parameter debug_axim__SYNC_RELOAD = 32'hF880C064; +parameter val_debug_axim__SYNC_RELOAD = 32'h00000800; +parameter mask_debug_axim__SYNC_RELOAD = 32'h00000FFF; + +parameter debug_axim__TSTMP_CURRENT = 32'hF880C070; +parameter val_debug_axim__TSTMP_CURRENT = 32'h00000000; +parameter mask_debug_axim__TSTMP_CURRENT = 32'h00000000; + +parameter debug_axim__ADDR0_MASK = 32'hF880C200; +parameter val_debug_axim__ADDR0_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR0_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_LOWER = 32'hF880C204; +parameter val_debug_axim__ADDR0_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR0_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_UPPER = 32'hF880C208; +parameter val_debug_axim__ADDR0_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR0_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR0_MISC = 32'hF880C20C; +parameter val_debug_axim__ADDR0_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR0_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR1_MASK = 32'hF880C210; +parameter val_debug_axim__ADDR1_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR1_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_LOWER = 32'hF880C214; +parameter val_debug_axim__ADDR1_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR1_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_UPPER = 32'hF880C218; +parameter val_debug_axim__ADDR1_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR1_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR1_MISC = 32'hF880C21C; +parameter val_debug_axim__ADDR1_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR1_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR2_MASK = 32'hF880C220; +parameter val_debug_axim__ADDR2_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR2_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_LOWER = 32'hF880C224; +parameter val_debug_axim__ADDR2_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR2_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_UPPER = 32'hF880C228; +parameter val_debug_axim__ADDR2_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR2_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR2_MISC = 32'hF880C22C; +parameter val_debug_axim__ADDR2_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR2_MISC = 32'h00007FFF; + +parameter debug_axim__ADDR3_MASK = 32'hF880C230; +parameter val_debug_axim__ADDR3_MASK = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR3_MASK = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_LOWER = 32'hF880C234; +parameter val_debug_axim__ADDR3_LOWER = 32'h00000000; +parameter mask_debug_axim__ADDR3_LOWER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_UPPER = 32'hF880C238; +parameter val_debug_axim__ADDR3_UPPER = 32'h7FFFFFFC; +parameter mask_debug_axim__ADDR3_UPPER = 32'h7FFFFFFF; + +parameter debug_axim__ADDR3_MISC = 32'hF880C23C; +parameter val_debug_axim__ADDR3_MISC = 32'h00000000; +parameter mask_debug_axim__ADDR3_MISC = 32'h00007FFF; + +parameter debug_axim__ID0_MASK = 32'hF880C300; +parameter val_debug_axim__ID0_MASK = 32'h000003FF; +parameter mask_debug_axim__ID0_MASK = 32'h000003FF; + +parameter debug_axim__ID0_LOWER = 32'hF880C304; +parameter val_debug_axim__ID0_LOWER = 32'h00000000; +parameter mask_debug_axim__ID0_LOWER = 32'h000003FF; + +parameter debug_axim__ID0_UPPER = 32'hF880C308; +parameter val_debug_axim__ID0_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID0_UPPER = 32'h000003FF; + +parameter debug_axim__ID0_MISC = 32'hF880C30C; +parameter val_debug_axim__ID0_MISC = 32'h00000000; +parameter mask_debug_axim__ID0_MISC = 32'h00003FFF; + +parameter debug_axim__ID1_MASK = 32'hF880C310; +parameter val_debug_axim__ID1_MASK = 32'h000003FF; +parameter mask_debug_axim__ID1_MASK = 32'h000003FF; + +parameter debug_axim__ID1_LOWER = 32'hF880C314; +parameter val_debug_axim__ID1_LOWER = 32'h00000000; +parameter mask_debug_axim__ID1_LOWER = 32'h000003FF; + +parameter debug_axim__ID1_UPPER = 32'hF880C318; +parameter val_debug_axim__ID1_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID1_UPPER = 32'h000003FF; + +parameter debug_axim__ID1_MISC = 32'hF880C31C; +parameter val_debug_axim__ID1_MISC = 32'h00000000; +parameter mask_debug_axim__ID1_MISC = 32'h00003FFF; + +parameter debug_axim__ID2_MASK = 32'hF880C320; +parameter val_debug_axim__ID2_MASK = 32'h000003FF; +parameter mask_debug_axim__ID2_MASK = 32'h000003FF; + +parameter debug_axim__ID2_LOWER = 32'hF880C324; +parameter val_debug_axim__ID2_LOWER = 32'h00000000; +parameter mask_debug_axim__ID2_LOWER = 32'h000003FF; + +parameter debug_axim__ID2_UPPER = 32'hF880C328; +parameter val_debug_axim__ID2_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID2_UPPER = 32'h000003FF; + +parameter debug_axim__ID2_MISC = 32'hF880C32C; +parameter val_debug_axim__ID2_MISC = 32'h00000000; +parameter mask_debug_axim__ID2_MISC = 32'h00003FFF; + +parameter debug_axim__ID3_MASK = 32'hF880C330; +parameter val_debug_axim__ID3_MASK = 32'h000003FF; +parameter mask_debug_axim__ID3_MASK = 32'h000003FF; + +parameter debug_axim__ID3_LOWER = 32'hF880C334; +parameter val_debug_axim__ID3_LOWER = 32'h00000000; +parameter mask_debug_axim__ID3_LOWER = 32'h000003FF; + +parameter debug_axim__ID3_UPPER = 32'hF880C338; +parameter val_debug_axim__ID3_UPPER = 32'h000003FF; +parameter mask_debug_axim__ID3_UPPER = 32'h000003FF; + +parameter debug_axim__ID3_MISC = 32'hF880C33C; +parameter val_debug_axim__ID3_MISC = 32'h00000000; +parameter mask_debug_axim__ID3_MISC = 32'h00003FFF; + +parameter debug_axim__AXI_SEL = 32'hF880C800; +parameter val_debug_axim__AXI_SEL = 32'h00000000; +parameter mask_debug_axim__AXI_SEL = 32'h00000007; + +parameter debug_axim__IT_TRIGOUT = 32'hF880CED0; +parameter val_debug_axim__IT_TRIGOUT = 32'h00000000; +parameter mask_debug_axim__IT_TRIGOUT = 32'h00000001; + +parameter debug_axim__IT_TRIGOUTACK = 32'hF880CED4; +parameter val_debug_axim__IT_TRIGOUTACK = 32'h00000000; +parameter mask_debug_axim__IT_TRIGOUTACK = 32'h00000000; + +parameter debug_axim__IT_TRIGIN = 32'hF880CED8; +parameter val_debug_axim__IT_TRIGIN = 32'h00000000; +parameter mask_debug_axim__IT_TRIGIN = 32'h00000000; + +parameter debug_axim__IT_TRIGINACK = 32'hF880CEDC; +parameter val_debug_axim__IT_TRIGINACK = 32'h00000000; +parameter mask_debug_axim__IT_TRIGINACK = 32'h00000001; + +parameter debug_axim__IT_ATBDATA = 32'hF880CEEC; +parameter val_debug_axim__IT_ATBDATA = 32'h00000000; +parameter mask_debug_axim__IT_ATBDATA = 32'h0000001F; + +parameter debug_axim__IT_ATBSTATUS = 32'hF880CEF0; +parameter val_debug_axim__IT_ATBSTATUS = 32'h00000000; +parameter mask_debug_axim__IT_ATBSTATUS = 32'h00000000; + +parameter debug_axim__IT_ATBCTRL1 = 32'hF880CEF4; +parameter val_debug_axim__IT_ATBCTRL1 = 32'h00000000; +parameter mask_debug_axim__IT_ATBCTRL1 = 32'h0000007F; + +parameter debug_axim__IT_ATBCTRL0 = 32'hF880CEF8; +parameter val_debug_axim__IT_ATBCTRL0 = 32'h00000000; +parameter mask_debug_axim__IT_ATBCTRL0 = 32'h000003FF; + +parameter debug_axim__IT_CTRL = 32'hF880CF00; +parameter val_debug_axim__IT_CTRL = 32'h00000000; +parameter mask_debug_axim__IT_CTRL = 32'h00000001; + +parameter debug_axim__CLAIM_SET = 32'hF880CFA0; +parameter val_debug_axim__CLAIM_SET = 32'h00000001; +parameter mask_debug_axim__CLAIM_SET = 32'h0000000F; + +parameter debug_axim__CLAIM_CLEAR = 32'hF880CFA4; +parameter val_debug_axim__CLAIM_CLEAR = 32'h00000000; +parameter mask_debug_axim__CLAIM_CLEAR = 32'h0000000F; + +parameter debug_axim__LOCK_ACCESS = 32'hF880CFB0; +parameter val_debug_axim__LOCK_ACCESS = 32'h00000000; +parameter mask_debug_axim__LOCK_ACCESS = 32'hFFFFFFFF; + +parameter debug_axim__LOCK_STATUS = 32'hF880CFB4; +parameter val_debug_axim__LOCK_STATUS = 32'h00000003; +parameter mask_debug_axim__LOCK_STATUS = 32'h00000007; + +parameter debug_axim__AUTH_STATUS = 32'hF880CFB8; +parameter val_debug_axim__AUTH_STATUS = 32'h00000000; +parameter mask_debug_axim__AUTH_STATUS = 32'h00000033; + +parameter debug_axim__DEV_ID = 32'hF880CFC8; +parameter val_debug_axim__DEV_ID = 32'h00000000; +parameter mask_debug_axim__DEV_ID = 32'hFFFFFFFF; + +parameter debug_axim__DEV_TYPE = 32'hF880CFCC; +parameter val_debug_axim__DEV_TYPE = 32'h00000043; +parameter mask_debug_axim__DEV_TYPE = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID4 = 32'hF880CFD0; +parameter val_debug_axim__PERIPHID4 = 32'h00000003; +parameter mask_debug_axim__PERIPHID4 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID5 = 32'hF880CFD4; +parameter val_debug_axim__PERIPHID5 = 32'h00000000; +parameter mask_debug_axim__PERIPHID5 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID6 = 32'hF880CFD8; +parameter val_debug_axim__PERIPHID6 = 32'h00000000; +parameter mask_debug_axim__PERIPHID6 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID7 = 32'hF880CFDC; +parameter val_debug_axim__PERIPHID7 = 32'h00000000; +parameter mask_debug_axim__PERIPHID7 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID0 = 32'hF880CFE0; +parameter val_debug_axim__PERIPHID0 = 32'h000000B2; +parameter mask_debug_axim__PERIPHID0 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID1 = 32'hF880CFE4; +parameter val_debug_axim__PERIPHID1 = 32'h00000093; +parameter mask_debug_axim__PERIPHID1 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID2 = 32'hF880CFE8; +parameter val_debug_axim__PERIPHID2 = 32'h00000008; +parameter mask_debug_axim__PERIPHID2 = 32'hFFFFFFFF; + +parameter debug_axim__PERIPHID3 = 32'hF880CFEC; +parameter val_debug_axim__PERIPHID3 = 32'h00000002; +parameter mask_debug_axim__PERIPHID3 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID0 = 32'hF880CFF0; +parameter val_debug_axim__COMPID0 = 32'h0000000D; +parameter mask_debug_axim__COMPID0 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID1 = 32'hF880CFF4; +parameter val_debug_axim__COMPID1 = 32'h00000090; +parameter mask_debug_axim__COMPID1 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID2 = 32'hF880CFF8; +parameter val_debug_axim__COMPID2 = 32'h00000005; +parameter mask_debug_axim__COMPID2 = 32'hFFFFFFFF; + +parameter debug_axim__COMPID3 = 32'hF880CFFC; +parameter val_debug_axim__COMPID3 = 32'h000000B1; +parameter mask_debug_axim__COMPID3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_cti0 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_cti0__CTICONTROL = 32'hF8898000; +parameter val_debug_cpu_cti0__CTICONTROL = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICONTROL = 32'h00000001; + +parameter debug_cpu_cti0__CTIINTACK = 32'hF8898010; +parameter val_debug_cpu_cti0__CTIINTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINTACK = 32'h000000FF; + +parameter debug_cpu_cti0__CTIAPPSET = 32'hF8898014; +parameter val_debug_cpu_cti0__CTIAPPSET = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPSET = 32'h0000000F; + +parameter debug_cpu_cti0__CTIAPPCLEAR = 32'hF8898018; +parameter val_debug_cpu_cti0__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cpu_cti0__CTIAPPPULSE = 32'hF889801C; +parameter val_debug_cpu_cti0__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN0 = 32'hF8898020; +parameter val_debug_cpu_cti0__CTIINEN0 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN0 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN1 = 32'hF8898024; +parameter val_debug_cpu_cti0__CTIINEN1 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN1 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN2 = 32'hF8898028; +parameter val_debug_cpu_cti0__CTIINEN2 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN2 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN3 = 32'hF889802C; +parameter val_debug_cpu_cti0__CTIINEN3 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN3 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN4 = 32'hF8898030; +parameter val_debug_cpu_cti0__CTIINEN4 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN4 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN5 = 32'hF8898034; +parameter val_debug_cpu_cti0__CTIINEN5 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN5 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN6 = 32'hF8898038; +parameter val_debug_cpu_cti0__CTIINEN6 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN6 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIINEN7 = 32'hF889803C; +parameter val_debug_cpu_cti0__CTIINEN7 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIINEN7 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN0 = 32'hF88980A0; +parameter val_debug_cpu_cti0__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN1 = 32'hF88980A4; +parameter val_debug_cpu_cti0__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN2 = 32'hF88980A8; +parameter val_debug_cpu_cti0__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN3 = 32'hF88980AC; +parameter val_debug_cpu_cti0__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN4 = 32'hF88980B0; +parameter val_debug_cpu_cti0__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN5 = 32'hF88980B4; +parameter val_debug_cpu_cti0__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN6 = 32'hF88980B8; +parameter val_debug_cpu_cti0__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cpu_cti0__CTIOUTEN7 = 32'hF88980BC; +parameter val_debug_cpu_cti0__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cpu_cti0__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cpu_cti0__CTITRIGINSTATUS = 32'hF8898130; +parameter val_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cpu_cti0__CTITRIGOUTSTATUS = 32'hF8898134; +parameter val_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cpu_cti0__CTICHINSTATUS = 32'hF8898138; +parameter val_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICHINSTATUS = 32'h00000000; + +parameter debug_cpu_cti0__CTICHOUTSTATUS = 32'hF889813C; +parameter val_debug_cpu_cti0__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti0__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cpu_cti0__CTIGATE = 32'hF8898140; +parameter val_debug_cpu_cti0__CTIGATE = 32'h0000000F; +parameter mask_debug_cpu_cti0__CTIGATE = 32'h0000000F; + +parameter debug_cpu_cti0__ASICCTL = 32'hF8898144; +parameter val_debug_cpu_cti0__ASICCTL = 32'h00000000; +parameter mask_debug_cpu_cti0__ASICCTL = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHINACK = 32'hF8898EDC; +parameter val_debug_cpu_cti0__ITCHINACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHINACK = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGINACK = 32'hF8898EE0; +parameter val_debug_cpu_cti0__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGINACK = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHOUT = 32'hF8898EE4; +parameter val_debug_cpu_cti0__ITCHOUT = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHOUT = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGOUT = 32'hF8898EE8; +parameter val_debug_cpu_cti0__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGOUT = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHOUTACK = 32'hF8898EEC; +parameter val_debug_cpu_cti0__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHOUTACK = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGOUTACK = 32'hF8898EF0; +parameter val_debug_cpu_cti0__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cpu_cti0__ITCHIN = 32'hF8898EF4; +parameter val_debug_cpu_cti0__ITCHIN = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCHIN = 32'h0000000F; + +parameter debug_cpu_cti0__ITTRIGIN = 32'hF8898EF8; +parameter val_debug_cpu_cti0__ITTRIGIN = 32'h00000000; +parameter mask_debug_cpu_cti0__ITTRIGIN = 32'h000000FF; + +parameter debug_cpu_cti0__ITCTRL = 32'hF8898F00; +parameter val_debug_cpu_cti0__ITCTRL = 32'h00000000; +parameter mask_debug_cpu_cti0__ITCTRL = 32'h00000001; + +parameter debug_cpu_cti0__CTSR = 32'hF8898FA0; +parameter val_debug_cpu_cti0__CTSR = 32'h0000000F; +parameter mask_debug_cpu_cti0__CTSR = 32'h0000000F; + +parameter debug_cpu_cti0__CTCR = 32'hF8898FA4; +parameter val_debug_cpu_cti0__CTCR = 32'h00000000; +parameter mask_debug_cpu_cti0__CTCR = 32'h0000000F; + +parameter debug_cpu_cti0__LAR = 32'hF8898FB0; +parameter val_debug_cpu_cti0__LAR = 32'h00000000; +parameter mask_debug_cpu_cti0__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_cti0__LSR = 32'hF8898FB4; +parameter val_debug_cpu_cti0__LSR = 32'h00000003; +parameter mask_debug_cpu_cti0__LSR = 32'h00000007; + +parameter debug_cpu_cti0__ASR = 32'hF8898FB8; +parameter val_debug_cpu_cti0__ASR = 32'h00000005; +parameter mask_debug_cpu_cti0__ASR = 32'h00000005; + +parameter debug_cpu_cti0__DEVID = 32'hF8898FC8; +parameter val_debug_cpu_cti0__DEVID = 32'h00040800; +parameter mask_debug_cpu_cti0__DEVID = 32'h000FFFFF; + +parameter debug_cpu_cti0__DTIR = 32'hF8898FCC; +parameter val_debug_cpu_cti0__DTIR = 32'h00000014; +parameter mask_debug_cpu_cti0__DTIR = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID4 = 32'hF8898FD0; +parameter val_debug_cpu_cti0__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_cti0__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID5 = 32'hF8898FD4; +parameter val_debug_cpu_cti0__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID6 = 32'hF8898FD8; +parameter val_debug_cpu_cti0__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID7 = 32'hF8898FDC; +parameter val_debug_cpu_cti0__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID0 = 32'hF8898FE0; +parameter val_debug_cpu_cti0__PERIPHID0 = 32'h00000006; +parameter mask_debug_cpu_cti0__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID1 = 32'hF8898FE4; +parameter val_debug_cpu_cti0__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_cti0__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID2 = 32'hF8898FE8; +parameter val_debug_cpu_cti0__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cpu_cti0__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_cti0__PERIPHID3 = 32'hF8898FEC; +parameter val_debug_cpu_cti0__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_cti0__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID0 = 32'hF8898FF0; +parameter val_debug_cpu_cti0__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_cti0__COMPID0 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID1 = 32'hF8898FF4; +parameter val_debug_cpu_cti0__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_cti0__COMPID1 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID2 = 32'hF8898FF8; +parameter val_debug_cpu_cti0__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_cti0__COMPID2 = 32'h000000FF; + +parameter debug_cpu_cti0__COMPID3 = 32'hF8898FFC; +parameter val_debug_cpu_cti0__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_cti0__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_cti1 cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_cti1__CTICONTROL = 32'hF8899000; +parameter val_debug_cpu_cti1__CTICONTROL = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICONTROL = 32'h00000001; + +parameter debug_cpu_cti1__CTIINTACK = 32'hF8899010; +parameter val_debug_cpu_cti1__CTIINTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINTACK = 32'h000000FF; + +parameter debug_cpu_cti1__CTIAPPSET = 32'hF8899014; +parameter val_debug_cpu_cti1__CTIAPPSET = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPSET = 32'h0000000F; + +parameter debug_cpu_cti1__CTIAPPCLEAR = 32'hF8899018; +parameter val_debug_cpu_cti1__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cpu_cti1__CTIAPPPULSE = 32'hF889901C; +parameter val_debug_cpu_cti1__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN0 = 32'hF8899020; +parameter val_debug_cpu_cti1__CTIINEN0 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN0 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN1 = 32'hF8899024; +parameter val_debug_cpu_cti1__CTIINEN1 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN1 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN2 = 32'hF8899028; +parameter val_debug_cpu_cti1__CTIINEN2 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN2 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN3 = 32'hF889902C; +parameter val_debug_cpu_cti1__CTIINEN3 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN3 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN4 = 32'hF8899030; +parameter val_debug_cpu_cti1__CTIINEN4 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN4 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN5 = 32'hF8899034; +parameter val_debug_cpu_cti1__CTIINEN5 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN5 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN6 = 32'hF8899038; +parameter val_debug_cpu_cti1__CTIINEN6 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN6 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIINEN7 = 32'hF889903C; +parameter val_debug_cpu_cti1__CTIINEN7 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIINEN7 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN0 = 32'hF88990A0; +parameter val_debug_cpu_cti1__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN1 = 32'hF88990A4; +parameter val_debug_cpu_cti1__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN2 = 32'hF88990A8; +parameter val_debug_cpu_cti1__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN3 = 32'hF88990AC; +parameter val_debug_cpu_cti1__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN4 = 32'hF88990B0; +parameter val_debug_cpu_cti1__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN5 = 32'hF88990B4; +parameter val_debug_cpu_cti1__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN6 = 32'hF88990B8; +parameter val_debug_cpu_cti1__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cpu_cti1__CTIOUTEN7 = 32'hF88990BC; +parameter val_debug_cpu_cti1__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cpu_cti1__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cpu_cti1__CTITRIGINSTATUS = 32'hF8899130; +parameter val_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cpu_cti1__CTITRIGOUTSTATUS = 32'hF8899134; +parameter val_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cpu_cti1__CTICHINSTATUS = 32'hF8899138; +parameter val_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICHINSTATUS = 32'h00000000; + +parameter debug_cpu_cti1__CTICHOUTSTATUS = 32'hF889913C; +parameter val_debug_cpu_cti1__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cpu_cti1__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cpu_cti1__CTIGATE = 32'hF8899140; +parameter val_debug_cpu_cti1__CTIGATE = 32'h0000000F; +parameter mask_debug_cpu_cti1__CTIGATE = 32'h0000000F; + +parameter debug_cpu_cti1__ASICCTL = 32'hF8899144; +parameter val_debug_cpu_cti1__ASICCTL = 32'h00000000; +parameter mask_debug_cpu_cti1__ASICCTL = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHINACK = 32'hF8899EDC; +parameter val_debug_cpu_cti1__ITCHINACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHINACK = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGINACK = 32'hF8899EE0; +parameter val_debug_cpu_cti1__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGINACK = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHOUT = 32'hF8899EE4; +parameter val_debug_cpu_cti1__ITCHOUT = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHOUT = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGOUT = 32'hF8899EE8; +parameter val_debug_cpu_cti1__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGOUT = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHOUTACK = 32'hF8899EEC; +parameter val_debug_cpu_cti1__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHOUTACK = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGOUTACK = 32'hF8899EF0; +parameter val_debug_cpu_cti1__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cpu_cti1__ITCHIN = 32'hF8899EF4; +parameter val_debug_cpu_cti1__ITCHIN = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCHIN = 32'h0000000F; + +parameter debug_cpu_cti1__ITTRIGIN = 32'hF8899EF8; +parameter val_debug_cpu_cti1__ITTRIGIN = 32'h00000000; +parameter mask_debug_cpu_cti1__ITTRIGIN = 32'h000000FF; + +parameter debug_cpu_cti1__ITCTRL = 32'hF8899F00; +parameter val_debug_cpu_cti1__ITCTRL = 32'h00000000; +parameter mask_debug_cpu_cti1__ITCTRL = 32'h00000001; + +parameter debug_cpu_cti1__CTSR = 32'hF8899FA0; +parameter val_debug_cpu_cti1__CTSR = 32'h0000000F; +parameter mask_debug_cpu_cti1__CTSR = 32'h0000000F; + +parameter debug_cpu_cti1__CTCR = 32'hF8899FA4; +parameter val_debug_cpu_cti1__CTCR = 32'h00000000; +parameter mask_debug_cpu_cti1__CTCR = 32'h0000000F; + +parameter debug_cpu_cti1__LAR = 32'hF8899FB0; +parameter val_debug_cpu_cti1__LAR = 32'h00000000; +parameter mask_debug_cpu_cti1__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_cti1__LSR = 32'hF8899FB4; +parameter val_debug_cpu_cti1__LSR = 32'h00000003; +parameter mask_debug_cpu_cti1__LSR = 32'h00000007; + +parameter debug_cpu_cti1__ASR = 32'hF8899FB8; +parameter val_debug_cpu_cti1__ASR = 32'h00000005; +parameter mask_debug_cpu_cti1__ASR = 32'h00000005; + +parameter debug_cpu_cti1__DEVID = 32'hF8899FC8; +parameter val_debug_cpu_cti1__DEVID = 32'h00040800; +parameter mask_debug_cpu_cti1__DEVID = 32'h000FFFFF; + +parameter debug_cpu_cti1__DTIR = 32'hF8899FCC; +parameter val_debug_cpu_cti1__DTIR = 32'h00000014; +parameter mask_debug_cpu_cti1__DTIR = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID4 = 32'hF8899FD0; +parameter val_debug_cpu_cti1__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_cti1__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID5 = 32'hF8899FD4; +parameter val_debug_cpu_cti1__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID6 = 32'hF8899FD8; +parameter val_debug_cpu_cti1__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID7 = 32'hF8899FDC; +parameter val_debug_cpu_cti1__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID0 = 32'hF8899FE0; +parameter val_debug_cpu_cti1__PERIPHID0 = 32'h00000006; +parameter mask_debug_cpu_cti1__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID1 = 32'hF8899FE4; +parameter val_debug_cpu_cti1__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_cti1__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID2 = 32'hF8899FE8; +parameter val_debug_cpu_cti1__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cpu_cti1__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_cti1__PERIPHID3 = 32'hF8899FEC; +parameter val_debug_cpu_cti1__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_cti1__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID0 = 32'hF8899FF0; +parameter val_debug_cpu_cti1__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_cti1__COMPID0 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID1 = 32'hF8899FF4; +parameter val_debug_cpu_cti1__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_cti1__COMPID1 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID2 = 32'hF8899FF8; +parameter val_debug_cpu_cti1__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_cti1__COMPID2 = 32'h000000FF; + +parameter debug_cpu_cti1__COMPID3 = 32'hF8899FFC; +parameter val_debug_cpu_cti1__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_cti1__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_pmu0 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_pmu0__PMXEVCNTR0 = 32'hF8891000; +parameter val_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR0 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR1 = 32'hF8891004; +parameter val_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR1 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR2 = 32'hF8891008; +parameter val_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR2 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR3 = 32'hF889100C; +parameter val_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR3 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR4 = 32'hF8891010; +parameter val_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR4 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVCNTR5 = 32'hF8891014; +parameter val_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVCNTR5 = 32'h00000000; + +parameter debug_cpu_pmu0__PMCCNTR = 32'hF889107C; +parameter val_debug_cpu_pmu0__PMCCNTR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCCNTR = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER0 = 32'hF8891400; +parameter val_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER0 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER1 = 32'hF8891404; +parameter val_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER1 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER2 = 32'hF8891408; +parameter val_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER2 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER3 = 32'hF889140C; +parameter val_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER3 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER4 = 32'hF8891410; +parameter val_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER4 = 32'h00000000; + +parameter debug_cpu_pmu0__PMXEVTYPER5 = 32'hF8891414; +parameter val_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMXEVTYPER5 = 32'h00000000; + +parameter debug_cpu_pmu0__PMCNTENSET = 32'hF8891C00; +parameter val_debug_cpu_pmu0__PMCNTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCNTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMCNTENCLR = 32'hF8891C20; +parameter val_debug_cpu_pmu0__PMCNTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMCNTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMINTENSET = 32'hF8891C40; +parameter val_debug_cpu_pmu0__PMINTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMINTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMINTENCLR = 32'hF8891C60; +parameter val_debug_cpu_pmu0__PMINTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMINTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMOVSR = 32'hF8891C80; +parameter val_debug_cpu_pmu0__PMOVSR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMOVSR = 32'h00000000; + +parameter debug_cpu_pmu0__PMSWINC = 32'hF8891CA0; +parameter val_debug_cpu_pmu0__PMSWINC = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMSWINC = 32'h00000000; + +parameter debug_cpu_pmu0__PMCR = 32'hF8891E04; +parameter val_debug_cpu_pmu0__PMCR = 32'h41093000; +parameter mask_debug_cpu_pmu0__PMCR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu0__PMUSERENR = 32'hF8891E08; +parameter val_debug_cpu_pmu0__PMUSERENR = 32'h00000000; +parameter mask_debug_cpu_pmu0__PMUSERENR = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_pmu1 cortexa9_pmu +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_pmu1__PMXEVCNTR0 = 32'hF8893000; +parameter val_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR0 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR1 = 32'hF8893004; +parameter val_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR1 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR2 = 32'hF8893008; +parameter val_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR2 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR3 = 32'hF889300C; +parameter val_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR3 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR4 = 32'hF8893010; +parameter val_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR4 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVCNTR5 = 32'hF8893014; +parameter val_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVCNTR5 = 32'h00000000; + +parameter debug_cpu_pmu1__PMCCNTR = 32'hF889307C; +parameter val_debug_cpu_pmu1__PMCCNTR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCCNTR = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER0 = 32'hF8893400; +parameter val_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER0 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER1 = 32'hF8893404; +parameter val_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER1 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER2 = 32'hF8893408; +parameter val_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER2 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER3 = 32'hF889340C; +parameter val_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER3 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER4 = 32'hF8893410; +parameter val_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER4 = 32'h00000000; + +parameter debug_cpu_pmu1__PMXEVTYPER5 = 32'hF8893414; +parameter val_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMXEVTYPER5 = 32'h00000000; + +parameter debug_cpu_pmu1__PMCNTENSET = 32'hF8893C00; +parameter val_debug_cpu_pmu1__PMCNTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCNTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMCNTENCLR = 32'hF8893C20; +parameter val_debug_cpu_pmu1__PMCNTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMCNTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMINTENSET = 32'hF8893C40; +parameter val_debug_cpu_pmu1__PMINTENSET = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMINTENSET = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMINTENCLR = 32'hF8893C60; +parameter val_debug_cpu_pmu1__PMINTENCLR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMINTENCLR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMOVSR = 32'hF8893C80; +parameter val_debug_cpu_pmu1__PMOVSR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMOVSR = 32'h00000000; + +parameter debug_cpu_pmu1__PMSWINC = 32'hF8893CA0; +parameter val_debug_cpu_pmu1__PMSWINC = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMSWINC = 32'h00000000; + +parameter debug_cpu_pmu1__PMCR = 32'hF8893E04; +parameter val_debug_cpu_pmu1__PMCR = 32'h41093000; +parameter mask_debug_cpu_pmu1__PMCR = 32'hFFFFFFFF; + +parameter debug_cpu_pmu1__PMUSERENR = 32'hF8893E08; +parameter val_debug_cpu_pmu1__PMUSERENR = 32'h00000000; +parameter mask_debug_cpu_pmu1__PMUSERENR = 32'hFFFFFFFF; + + +// ************************************************************ +// Module debug_cpu_ptm0 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_ptm0__ETMCR = 32'hF889C000; +parameter val_debug_cpu_ptm0__ETMCR = 32'h00000400; +parameter mask_debug_cpu_ptm0__ETMCR = 32'h3FFFFFFF; + +parameter debug_cpu_ptm0__ETMCCR = 32'hF889C004; +parameter val_debug_cpu_ptm0__ETMCCR = 32'h8D294004; +parameter mask_debug_cpu_ptm0__ETMCCR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMTRIGGER = 32'hF889C008; +parameter val_debug_cpu_ptm0__ETMTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTRIGGER = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSR = 32'hF889C010; +parameter val_debug_cpu_ptm0__ETMSR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSR = 32'h0000000F; + +parameter debug_cpu_ptm0__ETMSCR = 32'hF889C014; +parameter val_debug_cpu_ptm0__ETMSCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSCR = 32'h00007FFF; + +parameter debug_cpu_ptm0__ETMTSSCR = 32'hF889C018; +parameter val_debug_cpu_ptm0__ETMTSSCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTSSCR = 32'h00FFFFFF; + +parameter debug_cpu_ptm0__ETMTECR1 = 32'hF889C024; +parameter val_debug_cpu_ptm0__ETMTECR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTECR1 = 32'h03FFFFFF; + +parameter debug_cpu_ptm0__ETMACVR1 = 32'hF889C040; +parameter val_debug_cpu_ptm0__ETMACVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR2 = 32'hF889C044; +parameter val_debug_cpu_ptm0__ETMACVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR2 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR3 = 32'hF889C048; +parameter val_debug_cpu_ptm0__ETMACVR3 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR3 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR4 = 32'hF889C04C; +parameter val_debug_cpu_ptm0__ETMACVR4 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR4 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR5 = 32'hF889C050; +parameter val_debug_cpu_ptm0__ETMACVR5 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR5 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR6 = 32'hF889C054; +parameter val_debug_cpu_ptm0__ETMACVR6 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR6 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR7 = 32'hF889C058; +parameter val_debug_cpu_ptm0__ETMACVR7 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR7 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACVR8 = 32'hF889C05C; +parameter val_debug_cpu_ptm0__ETMACVR8 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMACVR8 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMACTR1 = 32'hF889C080; +parameter val_debug_cpu_ptm0__ETMACTR1 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR1 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR2 = 32'hF889C084; +parameter val_debug_cpu_ptm0__ETMACTR2 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR2 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR3 = 32'hF889C088; +parameter val_debug_cpu_ptm0__ETMACTR3 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR3 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR4 = 32'hF889C08C; +parameter val_debug_cpu_ptm0__ETMACTR4 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR4 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR5 = 32'hF889C090; +parameter val_debug_cpu_ptm0__ETMACTR5 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR5 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR6 = 32'hF889C094; +parameter val_debug_cpu_ptm0__ETMACTR6 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR6 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR7 = 32'hF889C098; +parameter val_debug_cpu_ptm0__ETMACTR7 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR7 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMACTR8 = 32'hF889C09C; +parameter val_debug_cpu_ptm0__ETMACTR8 = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMACTR8 = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMCNTRLDVR1 = 32'hF889C140; +parameter val_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDVR2 = 32'hF889C144; +parameter val_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTENR1 = 32'hF889C150; +parameter val_debug_cpu_ptm0__ETMCNTENR1 = 32'h00020000; +parameter mask_debug_cpu_ptm0__ETMCNTENR1 = 32'h0003FFFF; + +parameter debug_cpu_ptm0__ETMCNTENR2 = 32'hF889C154; +parameter val_debug_cpu_ptm0__ETMCNTENR2 = 32'h00020000; +parameter mask_debug_cpu_ptm0__ETMCNTENR2 = 32'h0003FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'hF889C160; +parameter val_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'hF889C164; +parameter val_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTRLDEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCNTVR1 = 32'hF889C170; +parameter val_debug_cpu_ptm0__ETMCNTVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMCNTVR2 = 32'hF889C174; +parameter val_debug_cpu_ptm0__ETMCNTVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCNTVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm0__ETMSQ12EVR = 32'hF889C180; +parameter val_debug_cpu_ptm0__ETMSQ12EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ12EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ21EVR = 32'hF889C184; +parameter val_debug_cpu_ptm0__ETMSQ21EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ21EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ23EVR = 32'hF889C188; +parameter val_debug_cpu_ptm0__ETMSQ23EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ23EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ31EVR = 32'hF889C18C; +parameter val_debug_cpu_ptm0__ETMSQ31EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ31EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ32EVR = 32'hF889C190; +parameter val_debug_cpu_ptm0__ETMSQ32EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ32EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQ13EVR = 32'hF889C194; +parameter val_debug_cpu_ptm0__ETMSQ13EVR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQ13EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMSQR = 32'hF889C19C; +parameter val_debug_cpu_ptm0__ETMSQR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMSQR = 32'h00000003; + +parameter debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'hF889C1A0; +parameter val_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'hF889C1A4; +parameter val_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTOUTEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm0__ETMCIDCVR1 = 32'hF889C1B0; +parameter val_debug_cpu_ptm0__ETMCIDCVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCIDCVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMCIDCMR = 32'hF889C1BC; +parameter val_debug_cpu_ptm0__ETMCIDCMR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMCIDCMR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMSYNCFR = 32'hF889C1E0; +parameter val_debug_cpu_ptm0__ETMSYNCFR = 32'h00000400; +parameter mask_debug_cpu_ptm0__ETMSYNCFR = 32'h00000FFF; + +parameter debug_cpu_ptm0__ETMIDR = 32'hF889C1E4; +parameter val_debug_cpu_ptm0__ETMIDR = 32'h411CF300; +parameter mask_debug_cpu_ptm0__ETMIDR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMCCER = 32'hF889C1E8; +parameter val_debug_cpu_ptm0__ETMCCER = 32'h00C019A2; +parameter mask_debug_cpu_ptm0__ETMCCER = 32'h03FFFFFF; + +parameter debug_cpu_ptm0__ETMEXTINSELR = 32'hF889C1EC; +parameter val_debug_cpu_ptm0__ETMEXTINSELR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMEXTINSELR = 32'h00003FFF; + +parameter debug_cpu_ptm0__ETMAUXCR = 32'hF889C1FC; +parameter val_debug_cpu_ptm0__ETMAUXCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMAUXCR = 32'h0000000F; + +parameter debug_cpu_ptm0__ETMTRACEIDR = 32'hF889C200; +parameter val_debug_cpu_ptm0__ETMTRACEIDR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMTRACEIDR = 32'h0000007F; + +parameter debug_cpu_ptm0__OSLSR = 32'hF889C304; +parameter val_debug_cpu_ptm0__OSLSR = 32'h00000000; +parameter mask_debug_cpu_ptm0__OSLSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ETMPDSR = 32'hF889C314; +parameter val_debug_cpu_ptm0__ETMPDSR = 32'h00000001; +parameter mask_debug_cpu_ptm0__ETMPDSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__ITMISCOUT = 32'hF889CEDC; +parameter val_debug_cpu_ptm0__ITMISCOUT = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITMISCOUT = 32'h000003FF; + +parameter debug_cpu_ptm0__ITMISCIN = 32'hF889CEE0; +parameter val_debug_cpu_ptm0__ITMISCIN = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITMISCIN = 32'h00000020; + +parameter debug_cpu_ptm0__ITTRIGGER = 32'hF889CEE8; +parameter val_debug_cpu_ptm0__ITTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITTRIGGER = 32'h00000001; + +parameter debug_cpu_ptm0__ITATBDATA0 = 32'hF889CEEC; +parameter val_debug_cpu_ptm0__ITATBDATA0 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBDATA0 = 32'h0000001F; + +parameter debug_cpu_ptm0__ITATBCTR2 = 32'hF889CEF0; +parameter val_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBCTR2 = 32'h00000000; + +parameter debug_cpu_ptm0__ITATBID = 32'hF889CEF4; +parameter val_debug_cpu_ptm0__ITATBID = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBID = 32'h0000007F; + +parameter debug_cpu_ptm0__ITATBCTR0 = 32'hF889CEF8; +parameter val_debug_cpu_ptm0__ITATBCTR0 = 32'h00000000; +parameter mask_debug_cpu_ptm0__ITATBCTR0 = 32'h000003FF; + +parameter debug_cpu_ptm0__ETMITCTRL = 32'hF889CF00; +parameter val_debug_cpu_ptm0__ETMITCTRL = 32'h00000000; +parameter mask_debug_cpu_ptm0__ETMITCTRL = 32'h00000001; + +parameter debug_cpu_ptm0__CTSR = 32'hF889CFA0; +parameter val_debug_cpu_ptm0__CTSR = 32'h000000FF; +parameter mask_debug_cpu_ptm0__CTSR = 32'h000000FF; + +parameter debug_cpu_ptm0__CTCR = 32'hF889CFA4; +parameter val_debug_cpu_ptm0__CTCR = 32'h00000000; +parameter mask_debug_cpu_ptm0__CTCR = 32'h000000FF; + +parameter debug_cpu_ptm0__LAR = 32'hF889CFB0; +parameter val_debug_cpu_ptm0__LAR = 32'h00000000; +parameter mask_debug_cpu_ptm0__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__LSR = 32'hF889CFB4; +parameter val_debug_cpu_ptm0__LSR = 32'h00000003; +parameter mask_debug_cpu_ptm0__LSR = 32'h00000007; + +parameter debug_cpu_ptm0__ASR = 32'hF889CFB8; +parameter val_debug_cpu_ptm0__ASR = 32'h00000000; +parameter mask_debug_cpu_ptm0__ASR = 32'h000000F3; + +parameter debug_cpu_ptm0__DEVID = 32'hF889CFC8; +parameter val_debug_cpu_ptm0__DEVID = 32'h00000000; +parameter mask_debug_cpu_ptm0__DEVID = 32'hFFFFFFFF; + +parameter debug_cpu_ptm0__DTIR = 32'hF889CFCC; +parameter val_debug_cpu_ptm0__DTIR = 32'h00000013; +parameter mask_debug_cpu_ptm0__DTIR = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID4 = 32'hF889CFD0; +parameter val_debug_cpu_ptm0__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_ptm0__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID5 = 32'hF889CFD4; +parameter val_debug_cpu_ptm0__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID6 = 32'hF889CFD8; +parameter val_debug_cpu_ptm0__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID7 = 32'hF889CFDC; +parameter val_debug_cpu_ptm0__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID0 = 32'hF889CFE0; +parameter val_debug_cpu_ptm0__PERIPHID0 = 32'h00000050; +parameter mask_debug_cpu_ptm0__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID1 = 32'hF889CFE4; +parameter val_debug_cpu_ptm0__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_ptm0__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID2 = 32'hF889CFE8; +parameter val_debug_cpu_ptm0__PERIPHID2 = 32'h0000001B; +parameter mask_debug_cpu_ptm0__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_ptm0__PERIPHID3 = 32'hF889CFEC; +parameter val_debug_cpu_ptm0__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_ptm0__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID0 = 32'hF889CFF0; +parameter val_debug_cpu_ptm0__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_ptm0__COMPID0 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID1 = 32'hF889CFF4; +parameter val_debug_cpu_ptm0__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_ptm0__COMPID1 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID2 = 32'hF889CFF8; +parameter val_debug_cpu_ptm0__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_ptm0__COMPID2 = 32'h000000FF; + +parameter debug_cpu_ptm0__COMPID3 = 32'hF889CFFC; +parameter val_debug_cpu_ptm0__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_ptm0__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cpu_ptm1 ptm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cpu_ptm1__ETMCR = 32'hF889D000; +parameter val_debug_cpu_ptm1__ETMCR = 32'h00000400; +parameter mask_debug_cpu_ptm1__ETMCR = 32'h3FFFFFFF; + +parameter debug_cpu_ptm1__ETMCCR = 32'hF889D004; +parameter val_debug_cpu_ptm1__ETMCCR = 32'h8D294004; +parameter mask_debug_cpu_ptm1__ETMCCR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMTRIGGER = 32'hF889D008; +parameter val_debug_cpu_ptm1__ETMTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTRIGGER = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSR = 32'hF889D010; +parameter val_debug_cpu_ptm1__ETMSR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSR = 32'h0000000F; + +parameter debug_cpu_ptm1__ETMSCR = 32'hF889D014; +parameter val_debug_cpu_ptm1__ETMSCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSCR = 32'h00007FFF; + +parameter debug_cpu_ptm1__ETMTSSCR = 32'hF889D018; +parameter val_debug_cpu_ptm1__ETMTSSCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTSSCR = 32'h00FFFFFF; + +parameter debug_cpu_ptm1__ETMTECR1 = 32'hF889D024; +parameter val_debug_cpu_ptm1__ETMTECR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTECR1 = 32'h03FFFFFF; + +parameter debug_cpu_ptm1__ETMACVR1 = 32'hF889D040; +parameter val_debug_cpu_ptm1__ETMACVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR2 = 32'hF889D044; +parameter val_debug_cpu_ptm1__ETMACVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR2 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR3 = 32'hF889D048; +parameter val_debug_cpu_ptm1__ETMACVR3 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR3 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR4 = 32'hF889D04C; +parameter val_debug_cpu_ptm1__ETMACVR4 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR4 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR5 = 32'hF889D050; +parameter val_debug_cpu_ptm1__ETMACVR5 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR5 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR6 = 32'hF889D054; +parameter val_debug_cpu_ptm1__ETMACVR6 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR6 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR7 = 32'hF889D058; +parameter val_debug_cpu_ptm1__ETMACVR7 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR7 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACVR8 = 32'hF889D05C; +parameter val_debug_cpu_ptm1__ETMACVR8 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMACVR8 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMACTR1 = 32'hF889D080; +parameter val_debug_cpu_ptm1__ETMACTR1 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR1 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR2 = 32'hF889D084; +parameter val_debug_cpu_ptm1__ETMACTR2 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR2 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR3 = 32'hF889D088; +parameter val_debug_cpu_ptm1__ETMACTR3 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR3 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR4 = 32'hF889D08C; +parameter val_debug_cpu_ptm1__ETMACTR4 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR4 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR5 = 32'hF889D090; +parameter val_debug_cpu_ptm1__ETMACTR5 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR5 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR6 = 32'hF889D094; +parameter val_debug_cpu_ptm1__ETMACTR6 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR6 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR7 = 32'hF889D098; +parameter val_debug_cpu_ptm1__ETMACTR7 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR7 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMACTR8 = 32'hF889D09C; +parameter val_debug_cpu_ptm1__ETMACTR8 = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMACTR8 = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMCNTRLDVR1 = 32'hF889D140; +parameter val_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDVR2 = 32'hF889D144; +parameter val_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTENR1 = 32'hF889D150; +parameter val_debug_cpu_ptm1__ETMCNTENR1 = 32'h00020000; +parameter mask_debug_cpu_ptm1__ETMCNTENR1 = 32'h0003FFFF; + +parameter debug_cpu_ptm1__ETMCNTENR2 = 32'hF889D154; +parameter val_debug_cpu_ptm1__ETMCNTENR2 = 32'h00020000; +parameter mask_debug_cpu_ptm1__ETMCNTENR2 = 32'h0003FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'hF889D160; +parameter val_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'hF889D164; +parameter val_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTRLDEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCNTVR1 = 32'hF889D170; +parameter val_debug_cpu_ptm1__ETMCNTVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTVR1 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMCNTVR2 = 32'hF889D174; +parameter val_debug_cpu_ptm1__ETMCNTVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCNTVR2 = 32'h0000FFFF; + +parameter debug_cpu_ptm1__ETMSQ12EVR = 32'hF889D180; +parameter val_debug_cpu_ptm1__ETMSQ12EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ12EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ21EVR = 32'hF889D184; +parameter val_debug_cpu_ptm1__ETMSQ21EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ21EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ23EVR = 32'hF889D188; +parameter val_debug_cpu_ptm1__ETMSQ23EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ23EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ31EVR = 32'hF889D18C; +parameter val_debug_cpu_ptm1__ETMSQ31EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ31EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ32EVR = 32'hF889D190; +parameter val_debug_cpu_ptm1__ETMSQ32EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ32EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQ13EVR = 32'hF889D194; +parameter val_debug_cpu_ptm1__ETMSQ13EVR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQ13EVR = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMSQR = 32'hF889D19C; +parameter val_debug_cpu_ptm1__ETMSQR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMSQR = 32'h00000003; + +parameter debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'hF889D1A0; +parameter val_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR1 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'hF889D1A4; +parameter val_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTOUTEVR2 = 32'h0001FFFF; + +parameter debug_cpu_ptm1__ETMCIDCVR1 = 32'hF889D1B0; +parameter val_debug_cpu_ptm1__ETMCIDCVR1 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCIDCVR1 = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMCIDCMR = 32'hF889D1BC; +parameter val_debug_cpu_ptm1__ETMCIDCMR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMCIDCMR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMSYNCFR = 32'hF889D1E0; +parameter val_debug_cpu_ptm1__ETMSYNCFR = 32'h00000400; +parameter mask_debug_cpu_ptm1__ETMSYNCFR = 32'h00000FFF; + +parameter debug_cpu_ptm1__ETMIDR = 32'hF889D1E4; +parameter val_debug_cpu_ptm1__ETMIDR = 32'h411CF300; +parameter mask_debug_cpu_ptm1__ETMIDR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMCCER = 32'hF889D1E8; +parameter val_debug_cpu_ptm1__ETMCCER = 32'h00C019A2; +parameter mask_debug_cpu_ptm1__ETMCCER = 32'h03FFFFFF; + +parameter debug_cpu_ptm1__ETMEXTINSELR = 32'hF889D1EC; +parameter val_debug_cpu_ptm1__ETMEXTINSELR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMEXTINSELR = 32'h00003FFF; + +parameter debug_cpu_ptm1__ETMAUXCR = 32'hF889D1FC; +parameter val_debug_cpu_ptm1__ETMAUXCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMAUXCR = 32'h0000000F; + +parameter debug_cpu_ptm1__ETMTRACEIDR = 32'hF889D200; +parameter val_debug_cpu_ptm1__ETMTRACEIDR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMTRACEIDR = 32'h0000007F; + +parameter debug_cpu_ptm1__OSLSR = 32'hF889D304; +parameter val_debug_cpu_ptm1__OSLSR = 32'h00000000; +parameter mask_debug_cpu_ptm1__OSLSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ETMPDSR = 32'hF889D314; +parameter val_debug_cpu_ptm1__ETMPDSR = 32'h00000001; +parameter mask_debug_cpu_ptm1__ETMPDSR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__ITMISCOUT = 32'hF889DEDC; +parameter val_debug_cpu_ptm1__ITMISCOUT = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITMISCOUT = 32'h000003FF; + +parameter debug_cpu_ptm1__ITMISCIN = 32'hF889DEE0; +parameter val_debug_cpu_ptm1__ITMISCIN = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITMISCIN = 32'h00000020; + +parameter debug_cpu_ptm1__ITTRIGGER = 32'hF889DEE8; +parameter val_debug_cpu_ptm1__ITTRIGGER = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITTRIGGER = 32'h00000001; + +parameter debug_cpu_ptm1__ITATBDATA0 = 32'hF889DEEC; +parameter val_debug_cpu_ptm1__ITATBDATA0 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBDATA0 = 32'h0000001F; + +parameter debug_cpu_ptm1__ITATBCTR2 = 32'hF889DEF0; +parameter val_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBCTR2 = 32'h00000000; + +parameter debug_cpu_ptm1__ITATBID = 32'hF889DEF4; +parameter val_debug_cpu_ptm1__ITATBID = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBID = 32'h0000007F; + +parameter debug_cpu_ptm1__ITATBCTR0 = 32'hF889DEF8; +parameter val_debug_cpu_ptm1__ITATBCTR0 = 32'h00000000; +parameter mask_debug_cpu_ptm1__ITATBCTR0 = 32'h000003FF; + +parameter debug_cpu_ptm1__ETMITCTRL = 32'hF889DF00; +parameter val_debug_cpu_ptm1__ETMITCTRL = 32'h00000000; +parameter mask_debug_cpu_ptm1__ETMITCTRL = 32'h00000001; + +parameter debug_cpu_ptm1__CTSR = 32'hF889DFA0; +parameter val_debug_cpu_ptm1__CTSR = 32'h000000FF; +parameter mask_debug_cpu_ptm1__CTSR = 32'h000000FF; + +parameter debug_cpu_ptm1__CTCR = 32'hF889DFA4; +parameter val_debug_cpu_ptm1__CTCR = 32'h00000000; +parameter mask_debug_cpu_ptm1__CTCR = 32'h000000FF; + +parameter debug_cpu_ptm1__LAR = 32'hF889DFB0; +parameter val_debug_cpu_ptm1__LAR = 32'h00000000; +parameter mask_debug_cpu_ptm1__LAR = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__LSR = 32'hF889DFB4; +parameter val_debug_cpu_ptm1__LSR = 32'h00000003; +parameter mask_debug_cpu_ptm1__LSR = 32'h00000007; + +parameter debug_cpu_ptm1__ASR = 32'hF889DFB8; +parameter val_debug_cpu_ptm1__ASR = 32'h00000000; +parameter mask_debug_cpu_ptm1__ASR = 32'h000000F3; + +parameter debug_cpu_ptm1__DEVID = 32'hF889DFC8; +parameter val_debug_cpu_ptm1__DEVID = 32'h00000000; +parameter mask_debug_cpu_ptm1__DEVID = 32'hFFFFFFFF; + +parameter debug_cpu_ptm1__DTIR = 32'hF889DFCC; +parameter val_debug_cpu_ptm1__DTIR = 32'h00000013; +parameter mask_debug_cpu_ptm1__DTIR = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID4 = 32'hF889DFD0; +parameter val_debug_cpu_ptm1__PERIPHID4 = 32'h00000004; +parameter mask_debug_cpu_ptm1__PERIPHID4 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID5 = 32'hF889DFD4; +parameter val_debug_cpu_ptm1__PERIPHID5 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID5 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID6 = 32'hF889DFD8; +parameter val_debug_cpu_ptm1__PERIPHID6 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID6 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID7 = 32'hF889DFDC; +parameter val_debug_cpu_ptm1__PERIPHID7 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID7 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID0 = 32'hF889DFE0; +parameter val_debug_cpu_ptm1__PERIPHID0 = 32'h00000050; +parameter mask_debug_cpu_ptm1__PERIPHID0 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID1 = 32'hF889DFE4; +parameter val_debug_cpu_ptm1__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cpu_ptm1__PERIPHID1 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID2 = 32'hF889DFE8; +parameter val_debug_cpu_ptm1__PERIPHID2 = 32'h0000001B; +parameter mask_debug_cpu_ptm1__PERIPHID2 = 32'h000000FF; + +parameter debug_cpu_ptm1__PERIPHID3 = 32'hF889DFEC; +parameter val_debug_cpu_ptm1__PERIPHID3 = 32'h00000000; +parameter mask_debug_cpu_ptm1__PERIPHID3 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID0 = 32'hF889DFF0; +parameter val_debug_cpu_ptm1__COMPID0 = 32'h0000000D; +parameter mask_debug_cpu_ptm1__COMPID0 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID1 = 32'hF889DFF4; +parameter val_debug_cpu_ptm1__COMPID1 = 32'h00000090; +parameter mask_debug_cpu_ptm1__COMPID1 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID2 = 32'hF889DFF8; +parameter val_debug_cpu_ptm1__COMPID2 = 32'h00000005; +parameter mask_debug_cpu_ptm1__COMPID2 = 32'h000000FF; + +parameter debug_cpu_ptm1__COMPID3 = 32'hF889DFFC; +parameter val_debug_cpu_ptm1__COMPID3 = 32'h000000B1; +parameter mask_debug_cpu_ptm1__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_axim cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_axim__CTICONTROL = 32'hF880A000; +parameter val_debug_cti_axim__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_axim__CTICONTROL = 32'h00000001; + +parameter debug_cti_axim__CTIINTACK = 32'hF880A010; +parameter val_debug_cti_axim__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_axim__CTIINTACK = 32'h000000FF; + +parameter debug_cti_axim__CTIAPPSET = 32'hF880A014; +parameter val_debug_cti_axim__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_axim__CTIAPPCLEAR = 32'hF880A018; +parameter val_debug_cti_axim__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_axim__CTIAPPPULSE = 32'hF880A01C; +parameter val_debug_cti_axim__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_axim__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN0 = 32'hF880A020; +parameter val_debug_cti_axim__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN1 = 32'hF880A024; +parameter val_debug_cti_axim__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN2 = 32'hF880A028; +parameter val_debug_cti_axim__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN3 = 32'hF880A02C; +parameter val_debug_cti_axim__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN4 = 32'hF880A030; +parameter val_debug_cti_axim__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN5 = 32'hF880A034; +parameter val_debug_cti_axim__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN6 = 32'hF880A038; +parameter val_debug_cti_axim__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_axim__CTIINEN7 = 32'hF880A03C; +parameter val_debug_cti_axim__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_axim__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN0 = 32'hF880A0A0; +parameter val_debug_cti_axim__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN1 = 32'hF880A0A4; +parameter val_debug_cti_axim__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN2 = 32'hF880A0A8; +parameter val_debug_cti_axim__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN3 = 32'hF880A0AC; +parameter val_debug_cti_axim__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN4 = 32'hF880A0B0; +parameter val_debug_cti_axim__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN5 = 32'hF880A0B4; +parameter val_debug_cti_axim__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN6 = 32'hF880A0B8; +parameter val_debug_cti_axim__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_axim__CTIOUTEN7 = 32'hF880A0BC; +parameter val_debug_cti_axim__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_axim__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_axim__CTITRIGINSTATUS = 32'hF880A130; +parameter val_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_axim__CTITRIGOUTSTATUS = 32'hF880A134; +parameter val_debug_cti_axim__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_axim__CTICHINSTATUS = 32'hF880A138; +parameter val_debug_cti_axim__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_axim__CTICHOUTSTATUS = 32'hF880A13C; +parameter val_debug_cti_axim__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_axim__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_axim__CTIGATE = 32'hF880A140; +parameter val_debug_cti_axim__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_axim__CTIGATE = 32'h0000000F; + +parameter debug_cti_axim__ASICCTL = 32'hF880A144; +parameter val_debug_cti_axim__ASICCTL = 32'h00000000; +parameter mask_debug_cti_axim__ASICCTL = 32'h000000FF; + +parameter debug_cti_axim__ITCHINACK = 32'hF880AEDC; +parameter val_debug_cti_axim__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_axim__ITCHINACK = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGINACK = 32'hF880AEE0; +parameter val_debug_cti_axim__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_axim__ITCHOUT = 32'hF880AEE4; +parameter val_debug_cti_axim__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_axim__ITCHOUT = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGOUT = 32'hF880AEE8; +parameter val_debug_cti_axim__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_axim__ITCHOUTACK = 32'hF880AEEC; +parameter val_debug_cti_axim__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_axim__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGOUTACK = 32'hF880AEF0; +parameter val_debug_cti_axim__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_axim__ITCHIN = 32'hF880AEF4; +parameter val_debug_cti_axim__ITCHIN = 32'h00000000; +parameter mask_debug_cti_axim__ITCHIN = 32'h0000000F; + +parameter debug_cti_axim__ITTRIGIN = 32'hF880AEF8; +parameter val_debug_cti_axim__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_axim__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_axim__ITCTRL = 32'hF880AF00; +parameter val_debug_cti_axim__ITCTRL = 32'h00000000; +parameter mask_debug_cti_axim__ITCTRL = 32'h00000001; + +parameter debug_cti_axim__CTSR = 32'hF880AFA0; +parameter val_debug_cti_axim__CTSR = 32'h0000000F; +parameter mask_debug_cti_axim__CTSR = 32'h0000000F; + +parameter debug_cti_axim__CTCR = 32'hF880AFA4; +parameter val_debug_cti_axim__CTCR = 32'h00000000; +parameter mask_debug_cti_axim__CTCR = 32'h0000000F; + +parameter debug_cti_axim__LAR = 32'hF880AFB0; +parameter val_debug_cti_axim__LAR = 32'h00000000; +parameter mask_debug_cti_axim__LAR = 32'hFFFFFFFF; + +parameter debug_cti_axim__LSR = 32'hF880AFB4; +parameter val_debug_cti_axim__LSR = 32'h00000003; +parameter mask_debug_cti_axim__LSR = 32'h00000007; + +parameter debug_cti_axim__ASR = 32'hF880AFB8; +parameter val_debug_cti_axim__ASR = 32'h00000005; +parameter mask_debug_cti_axim__ASR = 32'h00000005; + +parameter debug_cti_axim__DEVID = 32'hF880AFC8; +parameter val_debug_cti_axim__DEVID = 32'h00040800; +parameter mask_debug_cti_axim__DEVID = 32'h000FFFFF; + +parameter debug_cti_axim__DTIR = 32'hF880AFCC; +parameter val_debug_cti_axim__DTIR = 32'h00000014; +parameter mask_debug_cti_axim__DTIR = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID4 = 32'hF880AFD0; +parameter val_debug_cti_axim__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_axim__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID5 = 32'hF880AFD4; +parameter val_debug_cti_axim__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID6 = 32'hF880AFD8; +parameter val_debug_cti_axim__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID7 = 32'hF880AFDC; +parameter val_debug_cti_axim__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID0 = 32'hF880AFE0; +parameter val_debug_cti_axim__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_axim__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID1 = 32'hF880AFE4; +parameter val_debug_cti_axim__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_axim__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID2 = 32'hF880AFE8; +parameter val_debug_cti_axim__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_axim__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_axim__PERIPHID3 = 32'hF880AFEC; +parameter val_debug_cti_axim__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_axim__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_axim__COMPID0 = 32'hF880AFF0; +parameter val_debug_cti_axim__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_axim__COMPID0 = 32'h000000FF; + +parameter debug_cti_axim__COMPID1 = 32'hF880AFF4; +parameter val_debug_cti_axim__COMPID1 = 32'h00000090; +parameter mask_debug_cti_axim__COMPID1 = 32'h000000FF; + +parameter debug_cti_axim__COMPID2 = 32'hF880AFF8; +parameter val_debug_cti_axim__COMPID2 = 32'h00000005; +parameter mask_debug_cti_axim__COMPID2 = 32'h000000FF; + +parameter debug_cti_axim__COMPID3 = 32'hF880AFFC; +parameter val_debug_cti_axim__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_axim__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_etb_tpiu cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_etb_tpiu__CTICONTROL = 32'hF8802000; +parameter val_debug_cti_etb_tpiu__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICONTROL = 32'h00000001; + +parameter debug_cti_etb_tpiu__CTIINTACK = 32'hF8802010; +parameter val_debug_cti_etb_tpiu__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINTACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__CTIAPPSET = 32'hF8802014; +parameter val_debug_cti_etb_tpiu__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIAPPCLEAR = 32'hF8802018; +parameter val_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIAPPPULSE = 32'hF880201C; +parameter val_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN0 = 32'hF8802020; +parameter val_debug_cti_etb_tpiu__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN1 = 32'hF8802024; +parameter val_debug_cti_etb_tpiu__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN2 = 32'hF8802028; +parameter val_debug_cti_etb_tpiu__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN3 = 32'hF880202C; +parameter val_debug_cti_etb_tpiu__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN4 = 32'hF8802030; +parameter val_debug_cti_etb_tpiu__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN5 = 32'hF8802034; +parameter val_debug_cti_etb_tpiu__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN6 = 32'hF8802038; +parameter val_debug_cti_etb_tpiu__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIINEN7 = 32'hF880203C; +parameter val_debug_cti_etb_tpiu__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN0 = 32'hF88020A0; +parameter val_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN1 = 32'hF88020A4; +parameter val_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN2 = 32'hF88020A8; +parameter val_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN3 = 32'hF88020AC; +parameter val_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN4 = 32'hF88020B0; +parameter val_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN5 = 32'hF88020B4; +parameter val_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN6 = 32'hF88020B8; +parameter val_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIOUTEN7 = 32'hF88020BC; +parameter val_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'hF8802130; +parameter val_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'hF8802134; +parameter val_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_etb_tpiu__CTICHINSTATUS = 32'hF8802138; +parameter val_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'hF880213C; +parameter val_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTIGATE = 32'hF8802140; +parameter val_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_etb_tpiu__CTIGATE = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ASICCTL = 32'hF8802144; +parameter val_debug_cti_etb_tpiu__ASICCTL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ASICCTL = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHINACK = 32'hF8802EDC; +parameter val_debug_cti_etb_tpiu__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHINACK = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGINACK = 32'hF8802EE0; +parameter val_debug_cti_etb_tpiu__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHOUT = 32'hF8802EE4; +parameter val_debug_cti_etb_tpiu__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHOUT = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGOUT = 32'hF8802EE8; +parameter val_debug_cti_etb_tpiu__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHOUTACK = 32'hF8802EEC; +parameter val_debug_cti_etb_tpiu__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGOUTACK = 32'hF8802EF0; +parameter val_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCHIN = 32'hF8802EF4; +parameter val_debug_cti_etb_tpiu__ITCHIN = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCHIN = 32'h0000000F; + +parameter debug_cti_etb_tpiu__ITTRIGIN = 32'hF8802EF8; +parameter val_debug_cti_etb_tpiu__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_etb_tpiu__ITCTRL = 32'hF8802F00; +parameter val_debug_cti_etb_tpiu__ITCTRL = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__ITCTRL = 32'h00000001; + +parameter debug_cti_etb_tpiu__CTSR = 32'hF8802FA0; +parameter val_debug_cti_etb_tpiu__CTSR = 32'h0000000F; +parameter mask_debug_cti_etb_tpiu__CTSR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__CTCR = 32'hF8802FA4; +parameter val_debug_cti_etb_tpiu__CTCR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__CTCR = 32'h0000000F; + +parameter debug_cti_etb_tpiu__LAR = 32'hF8802FB0; +parameter val_debug_cti_etb_tpiu__LAR = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__LAR = 32'hFFFFFFFF; + +parameter debug_cti_etb_tpiu__LSR = 32'hF8802FB4; +parameter val_debug_cti_etb_tpiu__LSR = 32'h00000003; +parameter mask_debug_cti_etb_tpiu__LSR = 32'h00000007; + +parameter debug_cti_etb_tpiu__ASR = 32'hF8802FB8; +parameter val_debug_cti_etb_tpiu__ASR = 32'h00000005; +parameter mask_debug_cti_etb_tpiu__ASR = 32'h00000005; + +parameter debug_cti_etb_tpiu__DEVID = 32'hF8802FC8; +parameter val_debug_cti_etb_tpiu__DEVID = 32'h00040800; +parameter mask_debug_cti_etb_tpiu__DEVID = 32'h000FFFFF; + +parameter debug_cti_etb_tpiu__DTIR = 32'hF8802FCC; +parameter val_debug_cti_etb_tpiu__DTIR = 32'h00000014; +parameter mask_debug_cti_etb_tpiu__DTIR = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID4 = 32'hF8802FD0; +parameter val_debug_cti_etb_tpiu__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_etb_tpiu__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID5 = 32'hF8802FD4; +parameter val_debug_cti_etb_tpiu__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID6 = 32'hF8802FD8; +parameter val_debug_cti_etb_tpiu__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID7 = 32'hF8802FDC; +parameter val_debug_cti_etb_tpiu__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID0 = 32'hF8802FE0; +parameter val_debug_cti_etb_tpiu__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_etb_tpiu__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID1 = 32'hF8802FE4; +parameter val_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_etb_tpiu__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID2 = 32'hF8802FE8; +parameter val_debug_cti_etb_tpiu__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_etb_tpiu__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__PERIPHID3 = 32'hF8802FEC; +parameter val_debug_cti_etb_tpiu__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_etb_tpiu__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID0 = 32'hF8802FF0; +parameter val_debug_cti_etb_tpiu__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_etb_tpiu__COMPID0 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID1 = 32'hF8802FF4; +parameter val_debug_cti_etb_tpiu__COMPID1 = 32'h00000090; +parameter mask_debug_cti_etb_tpiu__COMPID1 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID2 = 32'hF8802FF8; +parameter val_debug_cti_etb_tpiu__COMPID2 = 32'h00000005; +parameter mask_debug_cti_etb_tpiu__COMPID2 = 32'h000000FF; + +parameter debug_cti_etb_tpiu__COMPID3 = 32'hF8802FFC; +parameter val_debug_cti_etb_tpiu__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_etb_tpiu__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_cti_ftm cti +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_cti_ftm__CTICONTROL = 32'hF8809000; +parameter val_debug_cti_ftm__CTICONTROL = 32'h00000000; +parameter mask_debug_cti_ftm__CTICONTROL = 32'h00000001; + +parameter debug_cti_ftm__CTIINTACK = 32'hF8809010; +parameter val_debug_cti_ftm__CTIINTACK = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINTACK = 32'h000000FF; + +parameter debug_cti_ftm__CTIAPPSET = 32'hF8809014; +parameter val_debug_cti_ftm__CTIAPPSET = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPSET = 32'h0000000F; + +parameter debug_cti_ftm__CTIAPPCLEAR = 32'hF8809018; +parameter val_debug_cti_ftm__CTIAPPCLEAR = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPCLEAR = 32'h0000000F; + +parameter debug_cti_ftm__CTIAPPPULSE = 32'hF880901C; +parameter val_debug_cti_ftm__CTIAPPPULSE = 32'h00000000; +parameter mask_debug_cti_ftm__CTIAPPPULSE = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN0 = 32'hF8809020; +parameter val_debug_cti_ftm__CTIINEN0 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN0 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN1 = 32'hF8809024; +parameter val_debug_cti_ftm__CTIINEN1 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN1 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN2 = 32'hF8809028; +parameter val_debug_cti_ftm__CTIINEN2 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN2 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN3 = 32'hF880902C; +parameter val_debug_cti_ftm__CTIINEN3 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN3 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN4 = 32'hF8809030; +parameter val_debug_cti_ftm__CTIINEN4 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN4 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN5 = 32'hF8809034; +parameter val_debug_cti_ftm__CTIINEN5 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN5 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN6 = 32'hF8809038; +parameter val_debug_cti_ftm__CTIINEN6 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN6 = 32'h0000000F; + +parameter debug_cti_ftm__CTIINEN7 = 32'hF880903C; +parameter val_debug_cti_ftm__CTIINEN7 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIINEN7 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN0 = 32'hF88090A0; +parameter val_debug_cti_ftm__CTIOUTEN0 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN0 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN1 = 32'hF88090A4; +parameter val_debug_cti_ftm__CTIOUTEN1 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN1 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN2 = 32'hF88090A8; +parameter val_debug_cti_ftm__CTIOUTEN2 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN2 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN3 = 32'hF88090AC; +parameter val_debug_cti_ftm__CTIOUTEN3 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN3 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN4 = 32'hF88090B0; +parameter val_debug_cti_ftm__CTIOUTEN4 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN4 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN5 = 32'hF88090B4; +parameter val_debug_cti_ftm__CTIOUTEN5 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN5 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN6 = 32'hF88090B8; +parameter val_debug_cti_ftm__CTIOUTEN6 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN6 = 32'h0000000F; + +parameter debug_cti_ftm__CTIOUTEN7 = 32'hF88090BC; +parameter val_debug_cti_ftm__CTIOUTEN7 = 32'h00000000; +parameter mask_debug_cti_ftm__CTIOUTEN7 = 32'h0000000F; + +parameter debug_cti_ftm__CTITRIGINSTATUS = 32'hF8809130; +parameter val_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTITRIGINSTATUS = 32'h00000000; + +parameter debug_cti_ftm__CTITRIGOUTSTATUS = 32'hF8809134; +parameter val_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTITRIGOUTSTATUS = 32'h000000FF; + +parameter debug_cti_ftm__CTICHINSTATUS = 32'hF8809138; +parameter val_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTICHINSTATUS = 32'h00000000; + +parameter debug_cti_ftm__CTICHOUTSTATUS = 32'hF880913C; +parameter val_debug_cti_ftm__CTICHOUTSTATUS = 32'h00000000; +parameter mask_debug_cti_ftm__CTICHOUTSTATUS = 32'h0000000F; + +parameter debug_cti_ftm__CTIGATE = 32'hF8809140; +parameter val_debug_cti_ftm__CTIGATE = 32'h0000000F; +parameter mask_debug_cti_ftm__CTIGATE = 32'h0000000F; + +parameter debug_cti_ftm__ASICCTL = 32'hF8809144; +parameter val_debug_cti_ftm__ASICCTL = 32'h00000000; +parameter mask_debug_cti_ftm__ASICCTL = 32'h000000FF; + +parameter debug_cti_ftm__ITCHINACK = 32'hF8809EDC; +parameter val_debug_cti_ftm__ITCHINACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHINACK = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGINACK = 32'hF8809EE0; +parameter val_debug_cti_ftm__ITTRIGINACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGINACK = 32'h000000FF; + +parameter debug_cti_ftm__ITCHOUT = 32'hF8809EE4; +parameter val_debug_cti_ftm__ITCHOUT = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHOUT = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGOUT = 32'hF8809EE8; +parameter val_debug_cti_ftm__ITTRIGOUT = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGOUT = 32'h000000FF; + +parameter debug_cti_ftm__ITCHOUTACK = 32'hF8809EEC; +parameter val_debug_cti_ftm__ITCHOUTACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHOUTACK = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGOUTACK = 32'hF8809EF0; +parameter val_debug_cti_ftm__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGOUTACK = 32'h000000FF; + +parameter debug_cti_ftm__ITCHIN = 32'hF8809EF4; +parameter val_debug_cti_ftm__ITCHIN = 32'h00000000; +parameter mask_debug_cti_ftm__ITCHIN = 32'h0000000F; + +parameter debug_cti_ftm__ITTRIGIN = 32'hF8809EF8; +parameter val_debug_cti_ftm__ITTRIGIN = 32'h00000000; +parameter mask_debug_cti_ftm__ITTRIGIN = 32'h000000FF; + +parameter debug_cti_ftm__ITCTRL = 32'hF8809F00; +parameter val_debug_cti_ftm__ITCTRL = 32'h00000000; +parameter mask_debug_cti_ftm__ITCTRL = 32'h00000001; + +parameter debug_cti_ftm__CTSR = 32'hF8809FA0; +parameter val_debug_cti_ftm__CTSR = 32'h0000000F; +parameter mask_debug_cti_ftm__CTSR = 32'h0000000F; + +parameter debug_cti_ftm__CTCR = 32'hF8809FA4; +parameter val_debug_cti_ftm__CTCR = 32'h00000000; +parameter mask_debug_cti_ftm__CTCR = 32'h0000000F; + +parameter debug_cti_ftm__LAR = 32'hF8809FB0; +parameter val_debug_cti_ftm__LAR = 32'h00000000; +parameter mask_debug_cti_ftm__LAR = 32'hFFFFFFFF; + +parameter debug_cti_ftm__LSR = 32'hF8809FB4; +parameter val_debug_cti_ftm__LSR = 32'h00000003; +parameter mask_debug_cti_ftm__LSR = 32'h00000007; + +parameter debug_cti_ftm__ASR = 32'hF8809FB8; +parameter val_debug_cti_ftm__ASR = 32'h00000005; +parameter mask_debug_cti_ftm__ASR = 32'h00000005; + +parameter debug_cti_ftm__DEVID = 32'hF8809FC8; +parameter val_debug_cti_ftm__DEVID = 32'h00040800; +parameter mask_debug_cti_ftm__DEVID = 32'h000FFFFF; + +parameter debug_cti_ftm__DTIR = 32'hF8809FCC; +parameter val_debug_cti_ftm__DTIR = 32'h00000014; +parameter mask_debug_cti_ftm__DTIR = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID4 = 32'hF8809FD0; +parameter val_debug_cti_ftm__PERIPHID4 = 32'h00000004; +parameter mask_debug_cti_ftm__PERIPHID4 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID5 = 32'hF8809FD4; +parameter val_debug_cti_ftm__PERIPHID5 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID5 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID6 = 32'hF8809FD8; +parameter val_debug_cti_ftm__PERIPHID6 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID6 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID7 = 32'hF8809FDC; +parameter val_debug_cti_ftm__PERIPHID7 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID7 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID0 = 32'hF8809FE0; +parameter val_debug_cti_ftm__PERIPHID0 = 32'h00000006; +parameter mask_debug_cti_ftm__PERIPHID0 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID1 = 32'hF8809FE4; +parameter val_debug_cti_ftm__PERIPHID1 = 32'h000000B9; +parameter mask_debug_cti_ftm__PERIPHID1 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID2 = 32'hF8809FE8; +parameter val_debug_cti_ftm__PERIPHID2 = 32'h0000002B; +parameter mask_debug_cti_ftm__PERIPHID2 = 32'h000000FF; + +parameter debug_cti_ftm__PERIPHID3 = 32'hF8809FEC; +parameter val_debug_cti_ftm__PERIPHID3 = 32'h00000000; +parameter mask_debug_cti_ftm__PERIPHID3 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID0 = 32'hF8809FF0; +parameter val_debug_cti_ftm__COMPID0 = 32'h0000000D; +parameter mask_debug_cti_ftm__COMPID0 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID1 = 32'hF8809FF4; +parameter val_debug_cti_ftm__COMPID1 = 32'h00000090; +parameter mask_debug_cti_ftm__COMPID1 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID2 = 32'hF8809FF8; +parameter val_debug_cti_ftm__COMPID2 = 32'h00000005; +parameter mask_debug_cti_ftm__COMPID2 = 32'h000000FF; + +parameter debug_cti_ftm__COMPID3 = 32'hF8809FFC; +parameter val_debug_cti_ftm__COMPID3 = 32'h000000B1; +parameter mask_debug_cti_ftm__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_dap_rom dap +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_dap_rom__ROMENTRY00 = 32'hF8800000; +parameter val_debug_dap_rom__ROMENTRY00 = 32'h00001003; +parameter mask_debug_dap_rom__ROMENTRY00 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY01 = 32'hF8800004; +parameter val_debug_dap_rom__ROMENTRY01 = 32'h00002003; +parameter mask_debug_dap_rom__ROMENTRY01 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY02 = 32'hF8800008; +parameter val_debug_dap_rom__ROMENTRY02 = 32'h00003003; +parameter mask_debug_dap_rom__ROMENTRY02 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY03 = 32'hF880000C; +parameter val_debug_dap_rom__ROMENTRY03 = 32'h00004003; +parameter mask_debug_dap_rom__ROMENTRY03 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY04 = 32'hF8800010; +parameter val_debug_dap_rom__ROMENTRY04 = 32'h00005003; +parameter mask_debug_dap_rom__ROMENTRY04 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY05 = 32'hF8800014; +parameter val_debug_dap_rom__ROMENTRY05 = 32'h00009003; +parameter mask_debug_dap_rom__ROMENTRY05 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY06 = 32'hF8800018; +parameter val_debug_dap_rom__ROMENTRY06 = 32'h0000A003; +parameter mask_debug_dap_rom__ROMENTRY06 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY07 = 32'hF880001C; +parameter val_debug_dap_rom__ROMENTRY07 = 32'h0000B003; +parameter mask_debug_dap_rom__ROMENTRY07 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY08 = 32'hF8800020; +parameter val_debug_dap_rom__ROMENTRY08 = 32'h0000C003; +parameter mask_debug_dap_rom__ROMENTRY08 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY09 = 32'hF8800024; +parameter val_debug_dap_rom__ROMENTRY09 = 32'h00080003; +parameter mask_debug_dap_rom__ROMENTRY09 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY10 = 32'hF8800028; +parameter val_debug_dap_rom__ROMENTRY10 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY10 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY11 = 32'hF880002C; +parameter val_debug_dap_rom__ROMENTRY11 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY11 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY12 = 32'hF8800030; +parameter val_debug_dap_rom__ROMENTRY12 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY12 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY13 = 32'hF8800034; +parameter val_debug_dap_rom__ROMENTRY13 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY13 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY14 = 32'hF8800038; +parameter val_debug_dap_rom__ROMENTRY14 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY14 = 32'hFFFFFFFF; + +parameter debug_dap_rom__ROMENTRY15 = 32'hF880003C; +parameter val_debug_dap_rom__ROMENTRY15 = 32'h00000000; +parameter mask_debug_dap_rom__ROMENTRY15 = 32'hFFFFFFFF; + +parameter debug_dap_rom__PERIPHID4 = 32'hF8800FD0; +parameter val_debug_dap_rom__PERIPHID4 = 32'h00000003; +parameter mask_debug_dap_rom__PERIPHID4 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID5 = 32'hF8800FD4; +parameter val_debug_dap_rom__PERIPHID5 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID5 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID6 = 32'hF8800FD8; +parameter val_debug_dap_rom__PERIPHID6 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID6 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID7 = 32'hF8800FDC; +parameter val_debug_dap_rom__PERIPHID7 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID7 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID0 = 32'hF8800FE0; +parameter val_debug_dap_rom__PERIPHID0 = 32'h000000B2; +parameter mask_debug_dap_rom__PERIPHID0 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID1 = 32'hF8800FE4; +parameter val_debug_dap_rom__PERIPHID1 = 32'h00000093; +parameter mask_debug_dap_rom__PERIPHID1 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID2 = 32'hF8800FE8; +parameter val_debug_dap_rom__PERIPHID2 = 32'h00000008; +parameter mask_debug_dap_rom__PERIPHID2 = 32'h000000FF; + +parameter debug_dap_rom__PERIPHID3 = 32'hF8800FEC; +parameter val_debug_dap_rom__PERIPHID3 = 32'h00000000; +parameter mask_debug_dap_rom__PERIPHID3 = 32'h000000FF; + +parameter debug_dap_rom__COMPID0 = 32'hF8800FF0; +parameter val_debug_dap_rom__COMPID0 = 32'h0000000D; +parameter mask_debug_dap_rom__COMPID0 = 32'h000000FF; + +parameter debug_dap_rom__COMPID1 = 32'hF8800FF4; +parameter val_debug_dap_rom__COMPID1 = 32'h00000010; +parameter mask_debug_dap_rom__COMPID1 = 32'h000000FF; + +parameter debug_dap_rom__COMPID2 = 32'hF8800FF8; +parameter val_debug_dap_rom__COMPID2 = 32'h00000005; +parameter mask_debug_dap_rom__COMPID2 = 32'h000000FF; + +parameter debug_dap_rom__COMPID3 = 32'hF8800FFC; +parameter val_debug_dap_rom__COMPID3 = 32'h000000B1; +parameter mask_debug_dap_rom__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_etb etb +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_etb__RDP = 32'hF8801004; +parameter val_debug_etb__RDP = 32'h00000400; +parameter mask_debug_etb__RDP = 32'hFFFFFFFF; + +parameter debug_etb__STS = 32'hF880100C; +parameter val_debug_etb__STS = 32'h00000000; +parameter mask_debug_etb__STS = 32'h0000000F; + +parameter debug_etb__RRD = 32'hF8801010; +parameter val_debug_etb__RRD = 32'h00000000; +parameter mask_debug_etb__RRD = 32'hFFFFFFFF; + +parameter debug_etb__RRP = 32'hF8801014; +parameter val_debug_etb__RRP = 32'h00000000; +parameter mask_debug_etb__RRP = 32'h000003FF; + +parameter debug_etb__RWP = 32'hF8801018; +parameter val_debug_etb__RWP = 32'h00000000; +parameter mask_debug_etb__RWP = 32'h000003FF; + +parameter debug_etb__TRG = 32'hF880101C; +parameter val_debug_etb__TRG = 32'h00000000; +parameter mask_debug_etb__TRG = 32'h000003FF; + +parameter debug_etb__CTL = 32'hF8801020; +parameter val_debug_etb__CTL = 32'h00000000; +parameter mask_debug_etb__CTL = 32'h00000001; + +parameter debug_etb__RWD = 32'hF8801024; +parameter val_debug_etb__RWD = 32'h00000000; +parameter mask_debug_etb__RWD = 32'hFFFFFFFF; + +parameter debug_etb__FFSR = 32'hF8801300; +parameter val_debug_etb__FFSR = 32'h00000000; +parameter mask_debug_etb__FFSR = 32'h00000003; + +parameter debug_etb__FFCR = 32'hF8801304; +parameter val_debug_etb__FFCR = 32'h00000200; +parameter mask_debug_etb__FFCR = 32'h00003FFF; + +parameter debug_etb__ITMISCOP0 = 32'hF8801EE0; +parameter val_debug_etb__ITMISCOP0 = 32'h00000000; +parameter mask_debug_etb__ITMISCOP0 = 32'h00000003; + +parameter debug_etb__ITTRFLINACK = 32'hF8801EE4; +parameter val_debug_etb__ITTRFLINACK = 32'h00000000; +parameter mask_debug_etb__ITTRFLINACK = 32'h00000003; + +parameter debug_etb__ITTRFLIN = 32'hF8801EE8; +parameter val_debug_etb__ITTRFLIN = 32'h00000000; +parameter mask_debug_etb__ITTRFLIN = 32'h00000003; + +parameter debug_etb__ITATBDATA0 = 32'hF8801EEC; +parameter val_debug_etb__ITATBDATA0 = 32'h00000000; +parameter mask_debug_etb__ITATBDATA0 = 32'h0000001F; + +parameter debug_etb__ITATBCTR2 = 32'hF8801EF0; +parameter val_debug_etb__ITATBCTR2 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR2 = 32'h00000003; + +parameter debug_etb__ITATBCTR1 = 32'hF8801EF4; +parameter val_debug_etb__ITATBCTR1 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR1 = 32'h0000007F; + +parameter debug_etb__ITATBCTR0 = 32'hF8801EF8; +parameter val_debug_etb__ITATBCTR0 = 32'h00000000; +parameter mask_debug_etb__ITATBCTR0 = 32'h000003FF; + +parameter debug_etb__IMCR = 32'hF8801F00; +parameter val_debug_etb__IMCR = 32'h00000000; +parameter mask_debug_etb__IMCR = 32'h00000001; + +parameter debug_etb__CTSR = 32'hF8801FA0; +parameter val_debug_etb__CTSR = 32'h0000000F; +parameter mask_debug_etb__CTSR = 32'h0000000F; + +parameter debug_etb__CTCR = 32'hF8801FA4; +parameter val_debug_etb__CTCR = 32'h00000000; +parameter mask_debug_etb__CTCR = 32'h0000000F; + +parameter debug_etb__LAR = 32'hF8801FB0; +parameter val_debug_etb__LAR = 32'h00000000; +parameter mask_debug_etb__LAR = 32'hFFFFFFFF; + +parameter debug_etb__LSR = 32'hF8801FB4; +parameter val_debug_etb__LSR = 32'h00000003; +parameter mask_debug_etb__LSR = 32'h00000007; + +parameter debug_etb__ASR = 32'hF8801FB8; +parameter val_debug_etb__ASR = 32'h00000000; +parameter mask_debug_etb__ASR = 32'h000000FF; + +parameter debug_etb__DEVID = 32'hF8801FC8; +parameter val_debug_etb__DEVID = 32'h00000000; +parameter mask_debug_etb__DEVID = 32'h0000003F; + +parameter debug_etb__DTIR = 32'hF8801FCC; +parameter val_debug_etb__DTIR = 32'h00000021; +parameter mask_debug_etb__DTIR = 32'h000000FF; + +parameter debug_etb__PERIPHID4 = 32'hF8801FD0; +parameter val_debug_etb__PERIPHID4 = 32'h00000004; +parameter mask_debug_etb__PERIPHID4 = 32'h000000FF; + +parameter debug_etb__PERIPHID5 = 32'hF8801FD4; +parameter val_debug_etb__PERIPHID5 = 32'h00000000; +parameter mask_debug_etb__PERIPHID5 = 32'h000000FF; + +parameter debug_etb__PERIPHID6 = 32'hF8801FD8; +parameter val_debug_etb__PERIPHID6 = 32'h00000000; +parameter mask_debug_etb__PERIPHID6 = 32'h000000FF; + +parameter debug_etb__PERIPHID7 = 32'hF8801FDC; +parameter val_debug_etb__PERIPHID7 = 32'h00000000; +parameter mask_debug_etb__PERIPHID7 = 32'h000000FF; + +parameter debug_etb__PERIPHID0 = 32'hF8801FE0; +parameter val_debug_etb__PERIPHID0 = 32'h00000007; +parameter mask_debug_etb__PERIPHID0 = 32'h000000FF; + +parameter debug_etb__PERIPHID1 = 32'hF8801FE4; +parameter val_debug_etb__PERIPHID1 = 32'h000000B9; +parameter mask_debug_etb__PERIPHID1 = 32'h000000FF; + +parameter debug_etb__PERIPHID2 = 32'hF8801FE8; +parameter val_debug_etb__PERIPHID2 = 32'h0000002B; +parameter mask_debug_etb__PERIPHID2 = 32'h000000FF; + +parameter debug_etb__PERIPHID3 = 32'hF8801FEC; +parameter val_debug_etb__PERIPHID3 = 32'h00000000; +parameter mask_debug_etb__PERIPHID3 = 32'h000000FF; + +parameter debug_etb__COMPID0 = 32'hF8801FF0; +parameter val_debug_etb__COMPID0 = 32'h0000000D; +parameter mask_debug_etb__COMPID0 = 32'h000000FF; + +parameter debug_etb__COMPID1 = 32'hF8801FF4; +parameter val_debug_etb__COMPID1 = 32'h00000090; +parameter mask_debug_etb__COMPID1 = 32'h000000FF; + +parameter debug_etb__COMPID2 = 32'hF8801FF8; +parameter val_debug_etb__COMPID2 = 32'h00000005; +parameter mask_debug_etb__COMPID2 = 32'h000000FF; + +parameter debug_etb__COMPID3 = 32'hF8801FFC; +parameter val_debug_etb__COMPID3 = 32'h000000B1; +parameter mask_debug_etb__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_ftm ftm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_ftm__FTMGLBCTRL = 32'hF880B000; +parameter val_debug_ftm__FTMGLBCTRL = 32'h00000000; +parameter mask_debug_ftm__FTMGLBCTRL = 32'h00000001; + +parameter debug_ftm__FTMSTATUS = 32'hF880B004; +parameter val_debug_ftm__FTMSTATUS = 32'h00000082; +parameter mask_debug_ftm__FTMSTATUS = 32'h000000FF; + +parameter debug_ftm__FTMCONTROL = 32'hF880B008; +parameter val_debug_ftm__FTMCONTROL = 32'h00000000; +parameter mask_debug_ftm__FTMCONTROL = 32'h00000007; + +parameter debug_ftm__FTMP2FDBG0 = 32'hF880B00C; +parameter val_debug_ftm__FTMP2FDBG0 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG0 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG1 = 32'hF880B010; +parameter val_debug_ftm__FTMP2FDBG1 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG1 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG2 = 32'hF880B014; +parameter val_debug_ftm__FTMP2FDBG2 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG2 = 32'h000000FF; + +parameter debug_ftm__FTMP2FDBG3 = 32'hF880B018; +parameter val_debug_ftm__FTMP2FDBG3 = 32'h00000000; +parameter mask_debug_ftm__FTMP2FDBG3 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG0 = 32'hF880B01C; +parameter val_debug_ftm__FTMF2PDBG0 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG0 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG1 = 32'hF880B020; +parameter val_debug_ftm__FTMF2PDBG1 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG1 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG2 = 32'hF880B024; +parameter val_debug_ftm__FTMF2PDBG2 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG2 = 32'h000000FF; + +parameter debug_ftm__FTMF2PDBG3 = 32'hF880B028; +parameter val_debug_ftm__FTMF2PDBG3 = 32'h00000000; +parameter mask_debug_ftm__FTMF2PDBG3 = 32'h000000FF; + +parameter debug_ftm__CYCOUNTPRE = 32'hF880B02C; +parameter val_debug_ftm__CYCOUNTPRE = 32'h00000000; +parameter mask_debug_ftm__CYCOUNTPRE = 32'h0000000F; + +parameter debug_ftm__FTMSYNCRELOAD = 32'hF880B030; +parameter val_debug_ftm__FTMSYNCRELOAD = 32'h00000000; +parameter mask_debug_ftm__FTMSYNCRELOAD = 32'h00000FFF; + +parameter debug_ftm__FTMSYNCCOUT = 32'hF880B034; +parameter val_debug_ftm__FTMSYNCCOUT = 32'h00000000; +parameter mask_debug_ftm__FTMSYNCCOUT = 32'h00000FFF; + +parameter debug_ftm__FTMATID = 32'hF880B400; +parameter val_debug_ftm__FTMATID = 32'h00000000; +parameter mask_debug_ftm__FTMATID = 32'h0000007F; + +parameter debug_ftm__FTMITTRIGOUTACK = 32'hF880BED0; +parameter val_debug_ftm__FTMITTRIGOUTACK = 32'h00000000; +parameter mask_debug_ftm__FTMITTRIGOUTACK = 32'h0000000F; + +parameter debug_ftm__FTMITTRIGGER = 32'hF880BED4; +parameter val_debug_ftm__FTMITTRIGGER = 32'h00000000; +parameter mask_debug_ftm__FTMITTRIGGER = 32'h0000000F; + +parameter debug_ftm__FTMITTRACEDIS = 32'hF880BED8; +parameter val_debug_ftm__FTMITTRACEDIS = 32'h00000000; +parameter mask_debug_ftm__FTMITTRACEDIS = 32'h00000001; + +parameter debug_ftm__FTMITCYCCOUNT = 32'hF880BEDC; +parameter val_debug_ftm__FTMITCYCCOUNT = 32'h00000001; +parameter mask_debug_ftm__FTMITCYCCOUNT = 32'hFFFFFFFF; + +parameter debug_ftm__FTMITATBDATA0 = 32'hF880BEEC; +parameter val_debug_ftm__FTMITATBDATA0 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBDATA0 = 32'h0000001F; + +parameter debug_ftm__FTMITATBCTR2 = 32'hF880BEF0; +parameter val_debug_ftm__FTMITATBCTR2 = 32'h00000001; +parameter mask_debug_ftm__FTMITATBCTR2 = 32'h00000003; + +parameter debug_ftm__FTMITATBCTR1 = 32'hF880BEF4; +parameter val_debug_ftm__FTMITATBCTR1 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBCTR1 = 32'h0000007F; + +parameter debug_ftm__FTMITATBCTR0 = 32'hF880BEF8; +parameter val_debug_ftm__FTMITATBCTR0 = 32'h00000000; +parameter mask_debug_ftm__FTMITATBCTR0 = 32'h000003FF; + +parameter debug_ftm__FTMITCR = 32'hF880BF00; +parameter val_debug_ftm__FTMITCR = 32'h00000000; +parameter mask_debug_ftm__FTMITCR = 32'h00000001; + +parameter debug_ftm__CLAIMTAGSET = 32'hF880BFA0; +parameter val_debug_ftm__CLAIMTAGSET = 32'h000000FF; +parameter mask_debug_ftm__CLAIMTAGSET = 32'h000000FF; + +parameter debug_ftm__CLAIMTAGCLR = 32'hF880BFA4; +parameter val_debug_ftm__CLAIMTAGCLR = 32'h000000FF; +parameter mask_debug_ftm__CLAIMTAGCLR = 32'h000000FF; + +parameter debug_ftm__LOCK_ACCESS = 32'hF880BFB0; +parameter val_debug_ftm__LOCK_ACCESS = 32'h00000000; +parameter mask_debug_ftm__LOCK_ACCESS = 32'hFFFFFFFF; + +parameter debug_ftm__LOCK_STATUS = 32'hF880BFB4; +parameter val_debug_ftm__LOCK_STATUS = 32'h00000003; +parameter mask_debug_ftm__LOCK_STATUS = 32'h00000007; + +parameter debug_ftm__FTMAUTHSTATUS = 32'hF880BFB8; +parameter val_debug_ftm__FTMAUTHSTATUS = 32'h00000088; +parameter mask_debug_ftm__FTMAUTHSTATUS = 32'h000000FF; + +parameter debug_ftm__FTMDEVID = 32'hF880BFC8; +parameter val_debug_ftm__FTMDEVID = 32'h00000000; +parameter mask_debug_ftm__FTMDEVID = 32'h00000001; + +parameter debug_ftm__FTMDEV_TYPE = 32'hF880BFCC; +parameter val_debug_ftm__FTMDEV_TYPE = 32'h00000033; +parameter mask_debug_ftm__FTMDEV_TYPE = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID4 = 32'hF880BFD0; +parameter val_debug_ftm__FTMPERIPHID4 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID4 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID5 = 32'hF880BFD4; +parameter val_debug_ftm__FTMPERIPHID5 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID5 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID6 = 32'hF880BFD8; +parameter val_debug_ftm__FTMPERIPHID6 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID6 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID7 = 32'hF880BFDC; +parameter val_debug_ftm__FTMPERIPHID7 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID7 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID0 = 32'hF880BFE0; +parameter val_debug_ftm__FTMPERIPHID0 = 32'h00000001; +parameter mask_debug_ftm__FTMPERIPHID0 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID1 = 32'hF880BFE4; +parameter val_debug_ftm__FTMPERIPHID1 = 32'h00000090; +parameter mask_debug_ftm__FTMPERIPHID1 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID2 = 32'hF880BFE8; +parameter val_debug_ftm__FTMPERIPHID2 = 32'h0000000C; +parameter mask_debug_ftm__FTMPERIPHID2 = 32'h000000FF; + +parameter debug_ftm__FTMPERIPHID3 = 32'hF880BFEC; +parameter val_debug_ftm__FTMPERIPHID3 = 32'h00000000; +parameter mask_debug_ftm__FTMPERIPHID3 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID0 = 32'hF880BFF0; +parameter val_debug_ftm__FTMCOMPONID0 = 32'h0000000D; +parameter mask_debug_ftm__FTMCOMPONID0 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID1 = 32'hF880BFF4; +parameter val_debug_ftm__FTMCOMPONID1 = 32'h00000090; +parameter mask_debug_ftm__FTMCOMPONID1 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID2 = 32'hF880BFF8; +parameter val_debug_ftm__FTMCOMPONID2 = 32'h00000005; +parameter mask_debug_ftm__FTMCOMPONID2 = 32'h000000FF; + +parameter debug_ftm__FTMCOMPONID3 = 32'hF880BFFC; +parameter val_debug_ftm__FTMCOMPONID3 = 32'h000000B1; +parameter mask_debug_ftm__FTMCOMPONID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_funnel funnel +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_funnel__Control = 32'hF8804000; +parameter val_debug_funnel__Control = 32'h00000300; +parameter mask_debug_funnel__Control = 32'h00000FFF; + +parameter debug_funnel__PriControl = 32'hF8804004; +parameter val_debug_funnel__PriControl = 32'h00FAC688; +parameter mask_debug_funnel__PriControl = 32'h00FFFFFF; + +parameter debug_funnel__ITATBDATA0 = 32'hF8804EEC; +parameter val_debug_funnel__ITATBDATA0 = 32'h00000000; +parameter mask_debug_funnel__ITATBDATA0 = 32'h0000001F; + +parameter debug_funnel__ITATBCTR2 = 32'hF8804EF0; +parameter val_debug_funnel__ITATBCTR2 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR2 = 32'h00000003; + +parameter debug_funnel__ITATBCTR1 = 32'hF8804EF4; +parameter val_debug_funnel__ITATBCTR1 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR1 = 32'h0000007F; + +parameter debug_funnel__ITATBCTR0 = 32'hF8804EF8; +parameter val_debug_funnel__ITATBCTR0 = 32'h00000000; +parameter mask_debug_funnel__ITATBCTR0 = 32'h000003FF; + +parameter debug_funnel__IMCR = 32'hF8804F00; +parameter val_debug_funnel__IMCR = 32'h00000000; +parameter mask_debug_funnel__IMCR = 32'h00000001; + +parameter debug_funnel__CTSR = 32'hF8804FA0; +parameter val_debug_funnel__CTSR = 32'h0000000F; +parameter mask_debug_funnel__CTSR = 32'h0000000F; + +parameter debug_funnel__CTCR = 32'hF8804FA4; +parameter val_debug_funnel__CTCR = 32'h00000000; +parameter mask_debug_funnel__CTCR = 32'h0000000F; + +parameter debug_funnel__LAR = 32'hF8804FB0; +parameter val_debug_funnel__LAR = 32'h00000000; +parameter mask_debug_funnel__LAR = 32'hFFFFFFFF; + +parameter debug_funnel__LSR = 32'hF8804FB4; +parameter val_debug_funnel__LSR = 32'h00000003; +parameter mask_debug_funnel__LSR = 32'h00000007; + +parameter debug_funnel__ASR = 32'hF8804FB8; +parameter val_debug_funnel__ASR = 32'h00000000; +parameter mask_debug_funnel__ASR = 32'h000000FF; + +parameter debug_funnel__DEVID = 32'hF8804FC8; +parameter val_debug_funnel__DEVID = 32'h00000028; +parameter mask_debug_funnel__DEVID = 32'h000000FF; + +parameter debug_funnel__DTIR = 32'hF8804FCC; +parameter val_debug_funnel__DTIR = 32'h00000012; +parameter mask_debug_funnel__DTIR = 32'h000000FF; + +parameter debug_funnel__PERIPHID4 = 32'hF8804FD0; +parameter val_debug_funnel__PERIPHID4 = 32'h00000004; +parameter mask_debug_funnel__PERIPHID4 = 32'h000000FF; + +parameter debug_funnel__PERIPHID5 = 32'hF8804FD4; +parameter val_debug_funnel__PERIPHID5 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID5 = 32'h000000FF; + +parameter debug_funnel__PERIPHID6 = 32'hF8804FD8; +parameter val_debug_funnel__PERIPHID6 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID6 = 32'h000000FF; + +parameter debug_funnel__PERIPHID7 = 32'hF8804FDC; +parameter val_debug_funnel__PERIPHID7 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID7 = 32'h000000FF; + +parameter debug_funnel__PERIPHID0 = 32'hF8804FE0; +parameter val_debug_funnel__PERIPHID0 = 32'h00000008; +parameter mask_debug_funnel__PERIPHID0 = 32'h000000FF; + +parameter debug_funnel__PERIPHID1 = 32'hF8804FE4; +parameter val_debug_funnel__PERIPHID1 = 32'h000000B9; +parameter mask_debug_funnel__PERIPHID1 = 32'h000000FF; + +parameter debug_funnel__PERIPHID2 = 32'hF8804FE8; +parameter val_debug_funnel__PERIPHID2 = 32'h0000001B; +parameter mask_debug_funnel__PERIPHID2 = 32'h000000FF; + +parameter debug_funnel__PERIPHID3 = 32'hF8804FEC; +parameter val_debug_funnel__PERIPHID3 = 32'h00000000; +parameter mask_debug_funnel__PERIPHID3 = 32'h000000FF; + +parameter debug_funnel__COMPID0 = 32'hF8804FF0; +parameter val_debug_funnel__COMPID0 = 32'h0000000D; +parameter mask_debug_funnel__COMPID0 = 32'h000000FF; + +parameter debug_funnel__COMPID1 = 32'hF8804FF4; +parameter val_debug_funnel__COMPID1 = 32'h00000090; +parameter mask_debug_funnel__COMPID1 = 32'h000000FF; + +parameter debug_funnel__COMPID2 = 32'hF8804FF8; +parameter val_debug_funnel__COMPID2 = 32'h00000005; +parameter mask_debug_funnel__COMPID2 = 32'h000000FF; + +parameter debug_funnel__COMPID3 = 32'hF8804FFC; +parameter val_debug_funnel__COMPID3 = 32'h000000B1; +parameter mask_debug_funnel__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_itm itm +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_itm__StimPort00 = 32'hF8805000; +parameter val_debug_itm__StimPort00 = 32'h00000000; +parameter mask_debug_itm__StimPort00 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort01 = 32'hF8805004; +parameter val_debug_itm__StimPort01 = 32'h00000000; +parameter mask_debug_itm__StimPort01 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort02 = 32'hF8805008; +parameter val_debug_itm__StimPort02 = 32'h00000000; +parameter mask_debug_itm__StimPort02 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort03 = 32'hF880500C; +parameter val_debug_itm__StimPort03 = 32'h00000000; +parameter mask_debug_itm__StimPort03 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort04 = 32'hF8805010; +parameter val_debug_itm__StimPort04 = 32'h00000000; +parameter mask_debug_itm__StimPort04 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort05 = 32'hF8805014; +parameter val_debug_itm__StimPort05 = 32'h00000000; +parameter mask_debug_itm__StimPort05 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort06 = 32'hF8805018; +parameter val_debug_itm__StimPort06 = 32'h00000000; +parameter mask_debug_itm__StimPort06 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort07 = 32'hF880501C; +parameter val_debug_itm__StimPort07 = 32'h00000000; +parameter mask_debug_itm__StimPort07 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort08 = 32'hF8805020; +parameter val_debug_itm__StimPort08 = 32'h00000000; +parameter mask_debug_itm__StimPort08 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort09 = 32'hF8805024; +parameter val_debug_itm__StimPort09 = 32'h00000000; +parameter mask_debug_itm__StimPort09 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort10 = 32'hF8805028; +parameter val_debug_itm__StimPort10 = 32'h00000000; +parameter mask_debug_itm__StimPort10 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort11 = 32'hF880502C; +parameter val_debug_itm__StimPort11 = 32'h00000000; +parameter mask_debug_itm__StimPort11 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort12 = 32'hF8805030; +parameter val_debug_itm__StimPort12 = 32'h00000000; +parameter mask_debug_itm__StimPort12 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort13 = 32'hF8805034; +parameter val_debug_itm__StimPort13 = 32'h00000000; +parameter mask_debug_itm__StimPort13 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort14 = 32'hF8805038; +parameter val_debug_itm__StimPort14 = 32'h00000000; +parameter mask_debug_itm__StimPort14 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort15 = 32'hF880503C; +parameter val_debug_itm__StimPort15 = 32'h00000000; +parameter mask_debug_itm__StimPort15 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort16 = 32'hF8805040; +parameter val_debug_itm__StimPort16 = 32'h00000000; +parameter mask_debug_itm__StimPort16 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort17 = 32'hF8805044; +parameter val_debug_itm__StimPort17 = 32'h00000000; +parameter mask_debug_itm__StimPort17 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort18 = 32'hF8805048; +parameter val_debug_itm__StimPort18 = 32'h00000000; +parameter mask_debug_itm__StimPort18 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort19 = 32'hF880504C; +parameter val_debug_itm__StimPort19 = 32'h00000000; +parameter mask_debug_itm__StimPort19 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort20 = 32'hF8805050; +parameter val_debug_itm__StimPort20 = 32'h00000000; +parameter mask_debug_itm__StimPort20 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort21 = 32'hF8805054; +parameter val_debug_itm__StimPort21 = 32'h00000000; +parameter mask_debug_itm__StimPort21 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort22 = 32'hF8805058; +parameter val_debug_itm__StimPort22 = 32'h00000000; +parameter mask_debug_itm__StimPort22 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort23 = 32'hF880505C; +parameter val_debug_itm__StimPort23 = 32'h00000000; +parameter mask_debug_itm__StimPort23 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort24 = 32'hF8805060; +parameter val_debug_itm__StimPort24 = 32'h00000000; +parameter mask_debug_itm__StimPort24 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort25 = 32'hF8805064; +parameter val_debug_itm__StimPort25 = 32'h00000000; +parameter mask_debug_itm__StimPort25 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort26 = 32'hF8805068; +parameter val_debug_itm__StimPort26 = 32'h00000000; +parameter mask_debug_itm__StimPort26 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort27 = 32'hF880506C; +parameter val_debug_itm__StimPort27 = 32'h00000000; +parameter mask_debug_itm__StimPort27 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort28 = 32'hF8805070; +parameter val_debug_itm__StimPort28 = 32'h00000000; +parameter mask_debug_itm__StimPort28 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort29 = 32'hF8805074; +parameter val_debug_itm__StimPort29 = 32'h00000000; +parameter mask_debug_itm__StimPort29 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort30 = 32'hF8805078; +parameter val_debug_itm__StimPort30 = 32'h00000000; +parameter mask_debug_itm__StimPort30 = 32'hFFFFFFFF; + +parameter debug_itm__StimPort31 = 32'hF880507C; +parameter val_debug_itm__StimPort31 = 32'h00000000; +parameter mask_debug_itm__StimPort31 = 32'hFFFFFFFF; + +parameter debug_itm__TER = 32'hF8805E00; +parameter val_debug_itm__TER = 32'h00000000; +parameter mask_debug_itm__TER = 32'hFFFFFFFF; + +parameter debug_itm__TTR = 32'hF8805E20; +parameter val_debug_itm__TTR = 32'h00000000; +parameter mask_debug_itm__TTR = 32'hFFFFFFFF; + +parameter debug_itm__CR = 32'hF8805E80; +parameter val_debug_itm__CR = 32'h00000004; +parameter mask_debug_itm__CR = 32'h00FFFFFF; + +parameter debug_itm__SCR = 32'hF8805E90; +parameter val_debug_itm__SCR = 32'h00000400; +parameter mask_debug_itm__SCR = 32'h00000FFF; + +parameter debug_itm__ITTRIGOUTACK = 32'hF8805EE4; +parameter val_debug_itm__ITTRIGOUTACK = 32'h00000000; +parameter mask_debug_itm__ITTRIGOUTACK = 32'h00000001; + +parameter debug_itm__ITTRIGOUT = 32'hF8805EE8; +parameter val_debug_itm__ITTRIGOUT = 32'h00000000; +parameter mask_debug_itm__ITTRIGOUT = 32'h00000001; + +parameter debug_itm__ITATBDATA0 = 32'hF8805EEC; +parameter val_debug_itm__ITATBDATA0 = 32'h00000000; +parameter mask_debug_itm__ITATBDATA0 = 32'h00000003; + +parameter debug_itm__ITATBCTR2 = 32'hF8805EF0; +parameter val_debug_itm__ITATBCTR2 = 32'h00000001; +parameter mask_debug_itm__ITATBCTR2 = 32'h00000001; + +parameter debug_itm__ITATABCTR1 = 32'hF8805EF4; +parameter val_debug_itm__ITATABCTR1 = 32'h00000000; +parameter mask_debug_itm__ITATABCTR1 = 32'h0000007F; + +parameter debug_itm__ITATBCTR0 = 32'hF8805EF8; +parameter val_debug_itm__ITATBCTR0 = 32'h00000000; +parameter mask_debug_itm__ITATBCTR0 = 32'h00000003; + +parameter debug_itm__IMCR = 32'hF8805F00; +parameter val_debug_itm__IMCR = 32'h00000000; +parameter mask_debug_itm__IMCR = 32'h00000001; + +parameter debug_itm__CTSR = 32'hF8805FA0; +parameter val_debug_itm__CTSR = 32'h000000FF; +parameter mask_debug_itm__CTSR = 32'h000000FF; + +parameter debug_itm__CTCR = 32'hF8805FA4; +parameter val_debug_itm__CTCR = 32'h00000000; +parameter mask_debug_itm__CTCR = 32'h000000FF; + +parameter debug_itm__LAR = 32'hF8805FB0; +parameter val_debug_itm__LAR = 32'h00000000; +parameter mask_debug_itm__LAR = 32'hFFFFFFFF; + +parameter debug_itm__LSR = 32'hF8805FB4; +parameter val_debug_itm__LSR = 32'h00000003; +parameter mask_debug_itm__LSR = 32'h00000007; + +parameter debug_itm__ASR = 32'hF8805FB8; +parameter val_debug_itm__ASR = 32'h00000088; +parameter mask_debug_itm__ASR = 32'h000000FF; + +parameter debug_itm__DEVID = 32'hF8805FC8; +parameter val_debug_itm__DEVID = 32'h00000020; +parameter mask_debug_itm__DEVID = 32'h00001FFF; + +parameter debug_itm__DTIR = 32'hF8805FCC; +parameter val_debug_itm__DTIR = 32'h00000043; +parameter mask_debug_itm__DTIR = 32'h000000FF; + +parameter debug_itm__PERIPHID4 = 32'hF8805FD0; +parameter val_debug_itm__PERIPHID4 = 32'h00000004; +parameter mask_debug_itm__PERIPHID4 = 32'h000000FF; + +parameter debug_itm__PERIPHID5 = 32'hF8805FD4; +parameter val_debug_itm__PERIPHID5 = 32'h00000000; +parameter mask_debug_itm__PERIPHID5 = 32'h000000FF; + +parameter debug_itm__PERIPHID6 = 32'hF8805FD8; +parameter val_debug_itm__PERIPHID6 = 32'h00000000; +parameter mask_debug_itm__PERIPHID6 = 32'h000000FF; + +parameter debug_itm__PERIPHID7 = 32'hF8805FDC; +parameter val_debug_itm__PERIPHID7 = 32'h00000000; +parameter mask_debug_itm__PERIPHID7 = 32'h000000FF; + +parameter debug_itm__PERIPHID0 = 32'hF8805FE0; +parameter val_debug_itm__PERIPHID0 = 32'h00000013; +parameter mask_debug_itm__PERIPHID0 = 32'h000000FF; + +parameter debug_itm__PERIPHID1 = 32'hF8805FE4; +parameter val_debug_itm__PERIPHID1 = 32'h000000B9; +parameter mask_debug_itm__PERIPHID1 = 32'h000000FF; + +parameter debug_itm__PERIPHID2 = 32'hF8805FE8; +parameter val_debug_itm__PERIPHID2 = 32'h0000002B; +parameter mask_debug_itm__PERIPHID2 = 32'h000000FF; + +parameter debug_itm__PERIPHID3 = 32'hF8805FEC; +parameter val_debug_itm__PERIPHID3 = 32'h00000000; +parameter mask_debug_itm__PERIPHID3 = 32'h000000FF; + +parameter debug_itm__COMPID0 = 32'hF8805FF0; +parameter val_debug_itm__COMPID0 = 32'h0000000D; +parameter mask_debug_itm__COMPID0 = 32'h000000FF; + +parameter debug_itm__COMPID1 = 32'hF8805FF4; +parameter val_debug_itm__COMPID1 = 32'h00000090; +parameter mask_debug_itm__COMPID1 = 32'h000000FF; + +parameter debug_itm__COMPID2 = 32'hF8805FF8; +parameter val_debug_itm__COMPID2 = 32'h00000005; +parameter mask_debug_itm__COMPID2 = 32'h000000FF; + +parameter debug_itm__COMPID3 = 32'hF8805FFC; +parameter val_debug_itm__COMPID3 = 32'h000000B1; +parameter mask_debug_itm__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module debug_tpiu tpiu +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter debug_tpiu__SuppSize = 32'hF8803000; +parameter val_debug_tpiu__SuppSize = 32'hFFFFFFFF; +parameter mask_debug_tpiu__SuppSize = 32'hFFFFFFFF; + +parameter debug_tpiu__CurrentSize = 32'hF8803004; +parameter val_debug_tpiu__CurrentSize = 32'h00000001; +parameter mask_debug_tpiu__CurrentSize = 32'hFFFFFFFF; + +parameter debug_tpiu__SuppTrigMode = 32'hF8803100; +parameter val_debug_tpiu__SuppTrigMode = 32'h0000011F; +parameter mask_debug_tpiu__SuppTrigMode = 32'h0003FFFF; + +parameter debug_tpiu__TrigCount = 32'hF8803104; +parameter val_debug_tpiu__TrigCount = 32'h00000000; +parameter mask_debug_tpiu__TrigCount = 32'h000000FF; + +parameter debug_tpiu__TrigMult = 32'hF8803108; +parameter val_debug_tpiu__TrigMult = 32'h00000000; +parameter mask_debug_tpiu__TrigMult = 32'h0000001F; + +parameter debug_tpiu__SuppTest = 32'hF8803200; +parameter val_debug_tpiu__SuppTest = 32'h0003000F; +parameter mask_debug_tpiu__SuppTest = 32'h0003FFFF; + +parameter debug_tpiu__CurrentTest = 32'hF8803204; +parameter val_debug_tpiu__CurrentTest = 32'h00000000; +parameter mask_debug_tpiu__CurrentTest = 32'h0003FFFF; + +parameter debug_tpiu__TestRepeatCount = 32'hF8803208; +parameter val_debug_tpiu__TestRepeatCount = 32'h00000000; +parameter mask_debug_tpiu__TestRepeatCount = 32'h000000FF; + +parameter debug_tpiu__FFSR = 32'hF8803300; +parameter val_debug_tpiu__FFSR = 32'h00000006; +parameter mask_debug_tpiu__FFSR = 32'h00000007; + +parameter debug_tpiu__FFCR = 32'hF8803304; +parameter val_debug_tpiu__FFCR = 32'h00000000; +parameter mask_debug_tpiu__FFCR = 32'h00003FFF; + +parameter debug_tpiu__FormatSyncCount = 32'hF8803308; +parameter val_debug_tpiu__FormatSyncCount = 32'h00000040; +parameter mask_debug_tpiu__FormatSyncCount = 32'h00000FFF; + +parameter debug_tpiu__EXTCTLIn = 32'hF8803400; +parameter val_debug_tpiu__EXTCTLIn = 32'h00000000; +parameter mask_debug_tpiu__EXTCTLIn = 32'h000000FF; + +parameter debug_tpiu__EXTCTLOut = 32'hF8803404; +parameter val_debug_tpiu__EXTCTLOut = 32'h00000000; +parameter mask_debug_tpiu__EXTCTLOut = 32'h000000FF; + +parameter debug_tpiu__ITTRFLINACK = 32'hF8803EE4; +parameter val_debug_tpiu__ITTRFLINACK = 32'h00000000; +parameter mask_debug_tpiu__ITTRFLINACK = 32'h00000003; + +parameter debug_tpiu__ITTRFLIN = 32'hF8803EE8; +parameter val_debug_tpiu__ITTRFLIN = 32'h00000000; +parameter mask_debug_tpiu__ITTRFLIN = 32'h00000000; + +parameter debug_tpiu__ITATBDATA0 = 32'hF8803EEC; +parameter val_debug_tpiu__ITATBDATA0 = 32'h00000000; +parameter mask_debug_tpiu__ITATBDATA0 = 32'h00000000; + +parameter debug_tpiu__ITATBCTR2 = 32'hF8803EF0; +parameter val_debug_tpiu__ITATBCTR2 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR2 = 32'h00000003; + +parameter debug_tpiu__ITATBCTR1 = 32'hF8803EF4; +parameter val_debug_tpiu__ITATBCTR1 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR1 = 32'h00000000; + +parameter debug_tpiu__ITATBCTR0 = 32'hF8803EF8; +parameter val_debug_tpiu__ITATBCTR0 = 32'h00000000; +parameter mask_debug_tpiu__ITATBCTR0 = 32'h00000000; + +parameter debug_tpiu__IMCR = 32'hF8803F00; +parameter val_debug_tpiu__IMCR = 32'h00000000; +parameter mask_debug_tpiu__IMCR = 32'h00000001; + +parameter debug_tpiu__CTSR = 32'hF8803FA0; +parameter val_debug_tpiu__CTSR = 32'h0000000F; +parameter mask_debug_tpiu__CTSR = 32'h0000000F; + +parameter debug_tpiu__CTCR = 32'hF8803FA4; +parameter val_debug_tpiu__CTCR = 32'h00000000; +parameter mask_debug_tpiu__CTCR = 32'h0000000F; + +parameter debug_tpiu__LAR = 32'hF8803FB0; +parameter val_debug_tpiu__LAR = 32'h00000000; +parameter mask_debug_tpiu__LAR = 32'hFFFFFFFF; + +parameter debug_tpiu__LSR = 32'hF8803FB4; +parameter val_debug_tpiu__LSR = 32'h00000003; +parameter mask_debug_tpiu__LSR = 32'h00000007; + +parameter debug_tpiu__ASR = 32'hF8803FB8; +parameter val_debug_tpiu__ASR = 32'h00000000; +parameter mask_debug_tpiu__ASR = 32'h000000FF; + +parameter debug_tpiu__DEVID = 32'hF8803FC8; +parameter val_debug_tpiu__DEVID = 32'h000000A0; +parameter mask_debug_tpiu__DEVID = 32'h00000FFF; + +parameter debug_tpiu__DTIR = 32'hF8803FCC; +parameter val_debug_tpiu__DTIR = 32'h00000011; +parameter mask_debug_tpiu__DTIR = 32'h000000FF; + +parameter debug_tpiu__PERIPHID4 = 32'hF8803FD0; +parameter val_debug_tpiu__PERIPHID4 = 32'h00000004; +parameter mask_debug_tpiu__PERIPHID4 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID5 = 32'hF8803FD4; +parameter val_debug_tpiu__PERIPHID5 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID5 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID6 = 32'hF8803FD8; +parameter val_debug_tpiu__PERIPHID6 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID6 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID7 = 32'hF8803FDC; +parameter val_debug_tpiu__PERIPHID7 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID7 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID0 = 32'hF8803FE0; +parameter val_debug_tpiu__PERIPHID0 = 32'h00000012; +parameter mask_debug_tpiu__PERIPHID0 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID1 = 32'hF8803FE4; +parameter val_debug_tpiu__PERIPHID1 = 32'h000000B9; +parameter mask_debug_tpiu__PERIPHID1 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID2 = 32'hF8803FE8; +parameter val_debug_tpiu__PERIPHID2 = 32'h0000004B; +parameter mask_debug_tpiu__PERIPHID2 = 32'h000000FF; + +parameter debug_tpiu__PERIPHID3 = 32'hF8803FEC; +parameter val_debug_tpiu__PERIPHID3 = 32'h00000000; +parameter mask_debug_tpiu__PERIPHID3 = 32'h000000FF; + +parameter debug_tpiu__COMPID0 = 32'hF8803FF0; +parameter val_debug_tpiu__COMPID0 = 32'h0000000D; +parameter mask_debug_tpiu__COMPID0 = 32'h000000FF; + +parameter debug_tpiu__COMPID1 = 32'hF8803FF4; +parameter val_debug_tpiu__COMPID1 = 32'h00000090; +parameter mask_debug_tpiu__COMPID1 = 32'h000000FF; + +parameter debug_tpiu__COMPID2 = 32'hF8803FF8; +parameter val_debug_tpiu__COMPID2 = 32'h00000005; +parameter mask_debug_tpiu__COMPID2 = 32'h000000FF; + +parameter debug_tpiu__COMPID3 = 32'hF8803FFC; +parameter val_debug_tpiu__COMPID3 = 32'h000000B1; +parameter mask_debug_tpiu__COMPID3 = 32'h000000FF; + + +// ************************************************************ +// Module devcfg devcfg +// doc version: 1.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter devcfg__CTRL = 32'hF8007000; +parameter val_devcfg__CTRL = 32'h0C000000; +parameter mask_devcfg__CTRL = 32'hFFFFFFFF; + +parameter devcfg__LOCK = 32'hF8007004; +parameter val_devcfg__LOCK = 32'h00000000; +parameter mask_devcfg__LOCK = 32'hFFFFFFFF; + +parameter devcfg__CFG = 32'hF8007008; +parameter val_devcfg__CFG = 32'h0000050B; +parameter mask_devcfg__CFG = 32'hFFFFFFFF; + +parameter devcfg__INT_STS = 32'hF800700C; +parameter val_devcfg__INT_STS = 32'h00000000; +parameter mask_devcfg__INT_STS = 32'hFFFFFFFF; + +parameter devcfg__INT_MASK = 32'hF8007010; +parameter val_devcfg__INT_MASK = 32'hFFFFFFFF; +parameter mask_devcfg__INT_MASK = 32'hFFFFFFFF; + +parameter devcfg__STATUS = 32'hF8007014; +parameter val_devcfg__STATUS = 32'h40000820; +parameter mask_devcfg__STATUS = 32'hFFFFFFFF; + +parameter devcfg__DMA_SRC_ADDR = 32'hF8007018; +parameter val_devcfg__DMA_SRC_ADDR = 32'h00000000; +parameter mask_devcfg__DMA_SRC_ADDR = 32'hFFFFFFFF; + +parameter devcfg__DMA_DST_ADDR = 32'hF800701C; +parameter val_devcfg__DMA_DST_ADDR = 32'h00000000; +parameter mask_devcfg__DMA_DST_ADDR = 32'hFFFFFFFF; + +parameter devcfg__DMA_SRC_LEN = 32'hF8007020; +parameter val_devcfg__DMA_SRC_LEN = 32'h00000000; +parameter mask_devcfg__DMA_SRC_LEN = 32'hFFFFFFFF; + +parameter devcfg__DMA_DEST_LEN = 32'hF8007024; +parameter val_devcfg__DMA_DEST_LEN = 32'h00000000; +parameter mask_devcfg__DMA_DEST_LEN = 32'hFFFFFFFF; + +parameter devcfg__ROM_SHADOW = 32'hF8007028; +parameter val_devcfg__ROM_SHADOW = 32'h00000000; +parameter mask_devcfg__ROM_SHADOW = 32'hFFFFFFFF; + +parameter devcfg__MULTIBOOT_ADDR = 32'hF800702C; +parameter val_devcfg__MULTIBOOT_ADDR = 32'h00000000; +parameter mask_devcfg__MULTIBOOT_ADDR = 32'hFFFFFFFF; + +parameter devcfg__SW_ID = 32'hF8007030; +parameter val_devcfg__SW_ID = 32'h00000000; +parameter mask_devcfg__SW_ID = 32'hFFFFFFFF; + +parameter devcfg__UNLOCK = 32'hF8007034; +parameter val_devcfg__UNLOCK = 32'h00000000; +parameter mask_devcfg__UNLOCK = 32'hFFFFFFFF; + +parameter devcfg__MCTRL = 32'hF8007080; +parameter val_devcfg__MCTRL = 32'h00800000; +parameter mask_devcfg__MCTRL = 32'h0FFFFFFF; + +parameter devcfg__XADCIF_CFG = 32'hF8007100; +parameter val_devcfg__XADCIF_CFG = 32'h00001114; +parameter mask_devcfg__XADCIF_CFG = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_INT_STS = 32'hF8007104; +parameter val_devcfg__XADCIF_INT_STS = 32'h00000200; +parameter mask_devcfg__XADCIF_INT_STS = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_INT_MASK = 32'hF8007108; +parameter val_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; +parameter mask_devcfg__XADCIF_INT_MASK = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_MSTS = 32'hF800710C; +parameter val_devcfg__XADCIF_MSTS = 32'h00000500; +parameter mask_devcfg__XADCIF_MSTS = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_CMDFIFO = 32'hF8007110; +parameter val_devcfg__XADCIF_CMDFIFO = 32'h00000000; +parameter mask_devcfg__XADCIF_CMDFIFO = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_RDFIFO = 32'hF8007114; +parameter val_devcfg__XADCIF_RDFIFO = 32'h00000000; +parameter mask_devcfg__XADCIF_RDFIFO = 32'hFFFFFFFF; + +parameter devcfg__XADCIF_MCTL = 32'hF8007118; +parameter val_devcfg__XADCIF_MCTL = 32'h00000010; +parameter mask_devcfg__XADCIF_MCTL = 32'hFFFFFFFF; + + +// ************************************************************ +// Module dmac0_ns dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter dmac0_ns__DSR = 32'hF8004000; +parameter val_dmac0_ns__DSR = 32'h00000000; +parameter mask_dmac0_ns__DSR = 32'hFFFFFFFF; + +parameter dmac0_ns__DPC = 32'hF8004004; +parameter val_dmac0_ns__DPC = 32'h00000000; +parameter mask_dmac0_ns__DPC = 32'hFFFFFFFF; + +parameter dmac0_ns__INTEN = 32'hF8004020; +parameter val_dmac0_ns__INTEN = 32'h00000000; +parameter mask_dmac0_ns__INTEN = 32'hFFFFFFFF; + +parameter dmac0_ns__INT_EVENT_RIS = 32'hF8004024; +parameter val_dmac0_ns__INT_EVENT_RIS = 32'h00000000; +parameter mask_dmac0_ns__INT_EVENT_RIS = 32'hFFFFFFFF; + +parameter dmac0_ns__INTMIS = 32'hF8004028; +parameter val_dmac0_ns__INTMIS = 32'h00000000; +parameter mask_dmac0_ns__INTMIS = 32'hFFFFFFFF; + +parameter dmac0_ns__INTCLR = 32'hF800402C; +parameter val_dmac0_ns__INTCLR = 32'h00000000; +parameter mask_dmac0_ns__INTCLR = 32'hFFFFFFFF; + +parameter dmac0_ns__FSRD = 32'hF8004030; +parameter val_dmac0_ns__FSRD = 32'h00000000; +parameter mask_dmac0_ns__FSRD = 32'hFFFFFFFF; + +parameter dmac0_ns__FSRC = 32'hF8004034; +parameter val_dmac0_ns__FSRC = 32'h00000000; +parameter mask_dmac0_ns__FSRC = 32'hFFFFFFFF; + +parameter dmac0_ns__FTRD = 32'hF8004038; +parameter val_dmac0_ns__FTRD = 32'h00000000; +parameter mask_dmac0_ns__FTRD = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR0 = 32'hF8004040; +parameter val_dmac0_ns__FTR0 = 32'h00000000; +parameter mask_dmac0_ns__FTR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR1 = 32'hF8004044; +parameter val_dmac0_ns__FTR1 = 32'h00000000; +parameter mask_dmac0_ns__FTR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR2 = 32'hF8004048; +parameter val_dmac0_ns__FTR2 = 32'h00000000; +parameter mask_dmac0_ns__FTR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR3 = 32'hF800404C; +parameter val_dmac0_ns__FTR3 = 32'h00000000; +parameter mask_dmac0_ns__FTR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR4 = 32'hF8004050; +parameter val_dmac0_ns__FTR4 = 32'h00000000; +parameter mask_dmac0_ns__FTR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR5 = 32'hF8004054; +parameter val_dmac0_ns__FTR5 = 32'h00000000; +parameter mask_dmac0_ns__FTR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR6 = 32'hF8004058; +parameter val_dmac0_ns__FTR6 = 32'h00000000; +parameter mask_dmac0_ns__FTR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__FTR7 = 32'hF800405C; +parameter val_dmac0_ns__FTR7 = 32'h00000000; +parameter mask_dmac0_ns__FTR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR0 = 32'hF8004100; +parameter val_dmac0_ns__CSR0 = 32'h00000000; +parameter mask_dmac0_ns__CSR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC0 = 32'hF8004104; +parameter val_dmac0_ns__CPC0 = 32'h00000000; +parameter mask_dmac0_ns__CPC0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR1 = 32'hF8004108; +parameter val_dmac0_ns__CSR1 = 32'h00000000; +parameter mask_dmac0_ns__CSR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC1 = 32'hF800410C; +parameter val_dmac0_ns__CPC1 = 32'h00000000; +parameter mask_dmac0_ns__CPC1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR2 = 32'hF8004110; +parameter val_dmac0_ns__CSR2 = 32'h00000000; +parameter mask_dmac0_ns__CSR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC2 = 32'hF8004114; +parameter val_dmac0_ns__CPC2 = 32'h00000000; +parameter mask_dmac0_ns__CPC2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR3 = 32'hF8004118; +parameter val_dmac0_ns__CSR3 = 32'h00000000; +parameter mask_dmac0_ns__CSR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC3 = 32'hF800411C; +parameter val_dmac0_ns__CPC3 = 32'h00000000; +parameter mask_dmac0_ns__CPC3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR4 = 32'hF8004120; +parameter val_dmac0_ns__CSR4 = 32'h00000000; +parameter mask_dmac0_ns__CSR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC4 = 32'hF8004124; +parameter val_dmac0_ns__CPC4 = 32'h00000000; +parameter mask_dmac0_ns__CPC4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR5 = 32'hF8004128; +parameter val_dmac0_ns__CSR5 = 32'h00000000; +parameter mask_dmac0_ns__CSR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC5 = 32'hF800412C; +parameter val_dmac0_ns__CPC5 = 32'h00000000; +parameter mask_dmac0_ns__CPC5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR6 = 32'hF8004130; +parameter val_dmac0_ns__CSR6 = 32'h00000000; +parameter mask_dmac0_ns__CSR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC6 = 32'hF8004134; +parameter val_dmac0_ns__CPC6 = 32'h00000000; +parameter mask_dmac0_ns__CPC6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CSR7 = 32'hF8004138; +parameter val_dmac0_ns__CSR7 = 32'h00000000; +parameter mask_dmac0_ns__CSR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CPC7 = 32'hF800413C; +parameter val_dmac0_ns__CPC7 = 32'h00000000; +parameter mask_dmac0_ns__CPC7 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR0 = 32'hF8004400; +parameter val_dmac0_ns__SAR0 = 32'h00000000; +parameter mask_dmac0_ns__SAR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR0 = 32'hF8004404; +parameter val_dmac0_ns__DAR0 = 32'h00000000; +parameter mask_dmac0_ns__DAR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR0 = 32'hF8004408; +parameter val_dmac0_ns__CCR0 = 32'h00000000; +parameter mask_dmac0_ns__CCR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_0 = 32'hF800440C; +parameter val_dmac0_ns__LC0_0 = 32'h00000000; +parameter mask_dmac0_ns__LC0_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_0 = 32'hF8004410; +parameter val_dmac0_ns__LC1_0 = 32'h00000000; +parameter mask_dmac0_ns__LC1_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR1 = 32'hF8004420; +parameter val_dmac0_ns__SAR1 = 32'h00000000; +parameter mask_dmac0_ns__SAR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR1 = 32'hF8004424; +parameter val_dmac0_ns__DAR1 = 32'h00000000; +parameter mask_dmac0_ns__DAR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR1 = 32'hF8004428; +parameter val_dmac0_ns__CCR1 = 32'h00000000; +parameter mask_dmac0_ns__CCR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_1 = 32'hF800442C; +parameter val_dmac0_ns__LC0_1 = 32'h00000000; +parameter mask_dmac0_ns__LC0_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_1 = 32'hF8004430; +parameter val_dmac0_ns__LC1_1 = 32'h00000000; +parameter mask_dmac0_ns__LC1_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR2 = 32'hF8004440; +parameter val_dmac0_ns__SAR2 = 32'h00000000; +parameter mask_dmac0_ns__SAR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR2 = 32'hF8004444; +parameter val_dmac0_ns__DAR2 = 32'h00000000; +parameter mask_dmac0_ns__DAR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR2 = 32'hF8004448; +parameter val_dmac0_ns__CCR2 = 32'h00000000; +parameter mask_dmac0_ns__CCR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_2 = 32'hF800444C; +parameter val_dmac0_ns__LC0_2 = 32'h00000000; +parameter mask_dmac0_ns__LC0_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_2 = 32'hF8004450; +parameter val_dmac0_ns__LC1_2 = 32'h00000000; +parameter mask_dmac0_ns__LC1_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR3 = 32'hF8004460; +parameter val_dmac0_ns__SAR3 = 32'h00000000; +parameter mask_dmac0_ns__SAR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR3 = 32'hF8004464; +parameter val_dmac0_ns__DAR3 = 32'h00000000; +parameter mask_dmac0_ns__DAR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR3 = 32'hF8004468; +parameter val_dmac0_ns__CCR3 = 32'h00000000; +parameter mask_dmac0_ns__CCR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_3 = 32'hF800446C; +parameter val_dmac0_ns__LC0_3 = 32'h00000000; +parameter mask_dmac0_ns__LC0_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_3 = 32'hF8004470; +parameter val_dmac0_ns__LC1_3 = 32'h00000000; +parameter mask_dmac0_ns__LC1_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR4 = 32'hF8004480; +parameter val_dmac0_ns__SAR4 = 32'h00000000; +parameter mask_dmac0_ns__SAR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR4 = 32'hF8004484; +parameter val_dmac0_ns__DAR4 = 32'h00000000; +parameter mask_dmac0_ns__DAR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR4 = 32'hF8004488; +parameter val_dmac0_ns__CCR4 = 32'h00000000; +parameter mask_dmac0_ns__CCR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_4 = 32'hF800448C; +parameter val_dmac0_ns__LC0_4 = 32'h00000000; +parameter mask_dmac0_ns__LC0_4 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_4 = 32'hF8004490; +parameter val_dmac0_ns__LC1_4 = 32'h00000000; +parameter mask_dmac0_ns__LC1_4 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR5 = 32'hF80044A0; +parameter val_dmac0_ns__SAR5 = 32'h00000000; +parameter mask_dmac0_ns__SAR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR5 = 32'hF80044A4; +parameter val_dmac0_ns__DAR5 = 32'h00000000; +parameter mask_dmac0_ns__DAR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR5 = 32'hF80044A8; +parameter val_dmac0_ns__CCR5 = 32'h00000000; +parameter mask_dmac0_ns__CCR5 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_5 = 32'hF80044AC; +parameter val_dmac0_ns__LC0_5 = 32'h00000000; +parameter mask_dmac0_ns__LC0_5 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_5 = 32'hF80044B0; +parameter val_dmac0_ns__LC1_5 = 32'h00000000; +parameter mask_dmac0_ns__LC1_5 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR6 = 32'hF80044C0; +parameter val_dmac0_ns__SAR6 = 32'h00000000; +parameter mask_dmac0_ns__SAR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR6 = 32'hF80044C4; +parameter val_dmac0_ns__DAR6 = 32'h00000000; +parameter mask_dmac0_ns__DAR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR6 = 32'hF80044C8; +parameter val_dmac0_ns__CCR6 = 32'h00000000; +parameter mask_dmac0_ns__CCR6 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_6 = 32'hF80044CC; +parameter val_dmac0_ns__LC0_6 = 32'h00000000; +parameter mask_dmac0_ns__LC0_6 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_6 = 32'hF80044D0; +parameter val_dmac0_ns__LC1_6 = 32'h00000000; +parameter mask_dmac0_ns__LC1_6 = 32'hFFFFFFFF; + +parameter dmac0_ns__SAR7 = 32'hF80044E0; +parameter val_dmac0_ns__SAR7 = 32'h00000000; +parameter mask_dmac0_ns__SAR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__DAR7 = 32'hF80044E4; +parameter val_dmac0_ns__DAR7 = 32'h00000000; +parameter mask_dmac0_ns__DAR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__CCR7 = 32'hF80044E8; +parameter val_dmac0_ns__CCR7 = 32'h00000000; +parameter mask_dmac0_ns__CCR7 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC0_7 = 32'hF80044EC; +parameter val_dmac0_ns__LC0_7 = 32'h00000000; +parameter mask_dmac0_ns__LC0_7 = 32'hFFFFFFFF; + +parameter dmac0_ns__LC1_7 = 32'hF80044F0; +parameter val_dmac0_ns__LC1_7 = 32'h00000000; +parameter mask_dmac0_ns__LC1_7 = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGSTATUS = 32'hF8004D00; +parameter val_dmac0_ns__DBGSTATUS = 32'h00000000; +parameter mask_dmac0_ns__DBGSTATUS = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGCMD = 32'hF8004D04; +parameter val_dmac0_ns__DBGCMD = 32'h00000000; +parameter mask_dmac0_ns__DBGCMD = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGINST0 = 32'hF8004D08; +parameter val_dmac0_ns__DBGINST0 = 32'h00000000; +parameter mask_dmac0_ns__DBGINST0 = 32'hFFFFFFFF; + +parameter dmac0_ns__DBGINST1 = 32'hF8004D0C; +parameter val_dmac0_ns__DBGINST1 = 32'h00000000; +parameter mask_dmac0_ns__DBGINST1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR0 = 32'hF8004E00; +parameter val_dmac0_ns__CR0 = 32'h00000000; +parameter mask_dmac0_ns__CR0 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR1 = 32'hF8004E04; +parameter val_dmac0_ns__CR1 = 32'h00000000; +parameter mask_dmac0_ns__CR1 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR2 = 32'hF8004E08; +parameter val_dmac0_ns__CR2 = 32'h00000000; +parameter mask_dmac0_ns__CR2 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR3 = 32'hF8004E0C; +parameter val_dmac0_ns__CR3 = 32'h00000000; +parameter mask_dmac0_ns__CR3 = 32'hFFFFFFFF; + +parameter dmac0_ns__CR4 = 32'hF8004E10; +parameter val_dmac0_ns__CR4 = 32'h00000000; +parameter mask_dmac0_ns__CR4 = 32'hFFFFFFFF; + +parameter dmac0_ns__CRD = 32'hF8004E14; +parameter val_dmac0_ns__CRD = 32'h00000000; +parameter mask_dmac0_ns__CRD = 32'hFFFFFFFF; + +parameter dmac0_ns__WD = 32'hF8004E80; +parameter val_dmac0_ns__WD = 32'h00000000; +parameter mask_dmac0_ns__WD = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_0 = 32'hF8004FE0; +parameter val_dmac0_ns__periph_id_0 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_1 = 32'hF8004FE4; +parameter val_dmac0_ns__periph_id_1 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_2 = 32'hF8004FE8; +parameter val_dmac0_ns__periph_id_2 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__periph_id_3 = 32'hF8004FEC; +parameter val_dmac0_ns__periph_id_3 = 32'h00000000; +parameter mask_dmac0_ns__periph_id_3 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_0 = 32'hF8004FF0; +parameter val_dmac0_ns__pcell_id_0 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_0 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_1 = 32'hF8004FF4; +parameter val_dmac0_ns__pcell_id_1 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_1 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_2 = 32'hF8004FF8; +parameter val_dmac0_ns__pcell_id_2 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_2 = 32'hFFFFFFFF; + +parameter dmac0_ns__pcell_id_3 = 32'hF8004FFC; +parameter val_dmac0_ns__pcell_id_3 = 32'h00000000; +parameter mask_dmac0_ns__pcell_id_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module dmac0_s dmac +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter dmac0_s__DSR = 32'hF8003000; +parameter val_dmac0_s__DSR = 32'h00000000; +parameter mask_dmac0_s__DSR = 32'hFFFFFFFF; + +parameter dmac0_s__DPC = 32'hF8003004; +parameter val_dmac0_s__DPC = 32'h00000000; +parameter mask_dmac0_s__DPC = 32'hFFFFFFFF; + +parameter dmac0_s__INTEN = 32'hF8003020; +parameter val_dmac0_s__INTEN = 32'h00000000; +parameter mask_dmac0_s__INTEN = 32'hFFFFFFFF; + +parameter dmac0_s__INT_EVENT_RIS = 32'hF8003024; +parameter val_dmac0_s__INT_EVENT_RIS = 32'h00000000; +parameter mask_dmac0_s__INT_EVENT_RIS = 32'hFFFFFFFF; + +parameter dmac0_s__INTMIS = 32'hF8003028; +parameter val_dmac0_s__INTMIS = 32'h00000000; +parameter mask_dmac0_s__INTMIS = 32'hFFFFFFFF; + +parameter dmac0_s__INTCLR = 32'hF800302C; +parameter val_dmac0_s__INTCLR = 32'h00000000; +parameter mask_dmac0_s__INTCLR = 32'hFFFFFFFF; + +parameter dmac0_s__FSRD = 32'hF8003030; +parameter val_dmac0_s__FSRD = 32'h00000000; +parameter mask_dmac0_s__FSRD = 32'hFFFFFFFF; + +parameter dmac0_s__FSRC = 32'hF8003034; +parameter val_dmac0_s__FSRC = 32'h00000000; +parameter mask_dmac0_s__FSRC = 32'hFFFFFFFF; + +parameter dmac0_s__FTRD = 32'hF8003038; +parameter val_dmac0_s__FTRD = 32'h00000000; +parameter mask_dmac0_s__FTRD = 32'hFFFFFFFF; + +parameter dmac0_s__FTR0 = 32'hF8003040; +parameter val_dmac0_s__FTR0 = 32'h00000000; +parameter mask_dmac0_s__FTR0 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR1 = 32'hF8003044; +parameter val_dmac0_s__FTR1 = 32'h00000000; +parameter mask_dmac0_s__FTR1 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR2 = 32'hF8003048; +parameter val_dmac0_s__FTR2 = 32'h00000000; +parameter mask_dmac0_s__FTR2 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR3 = 32'hF800304C; +parameter val_dmac0_s__FTR3 = 32'h00000000; +parameter mask_dmac0_s__FTR3 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR4 = 32'hF8003050; +parameter val_dmac0_s__FTR4 = 32'h00000000; +parameter mask_dmac0_s__FTR4 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR5 = 32'hF8003054; +parameter val_dmac0_s__FTR5 = 32'h00000000; +parameter mask_dmac0_s__FTR5 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR6 = 32'hF8003058; +parameter val_dmac0_s__FTR6 = 32'h00000000; +parameter mask_dmac0_s__FTR6 = 32'hFFFFFFFF; + +parameter dmac0_s__FTR7 = 32'hF800305C; +parameter val_dmac0_s__FTR7 = 32'h00000000; +parameter mask_dmac0_s__FTR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR0 = 32'hF8003100; +parameter val_dmac0_s__CSR0 = 32'h00000000; +parameter mask_dmac0_s__CSR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC0 = 32'hF8003104; +parameter val_dmac0_s__CPC0 = 32'h00000000; +parameter mask_dmac0_s__CPC0 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR1 = 32'hF8003108; +parameter val_dmac0_s__CSR1 = 32'h00000000; +parameter mask_dmac0_s__CSR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC1 = 32'hF800310C; +parameter val_dmac0_s__CPC1 = 32'h00000000; +parameter mask_dmac0_s__CPC1 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR2 = 32'hF8003110; +parameter val_dmac0_s__CSR2 = 32'h00000000; +parameter mask_dmac0_s__CSR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC2 = 32'hF8003114; +parameter val_dmac0_s__CPC2 = 32'h00000000; +parameter mask_dmac0_s__CPC2 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR3 = 32'hF8003118; +parameter val_dmac0_s__CSR3 = 32'h00000000; +parameter mask_dmac0_s__CSR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC3 = 32'hF800311C; +parameter val_dmac0_s__CPC3 = 32'h00000000; +parameter mask_dmac0_s__CPC3 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR4 = 32'hF8003120; +parameter val_dmac0_s__CSR4 = 32'h00000000; +parameter mask_dmac0_s__CSR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC4 = 32'hF8003124; +parameter val_dmac0_s__CPC4 = 32'h00000000; +parameter mask_dmac0_s__CPC4 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR5 = 32'hF8003128; +parameter val_dmac0_s__CSR5 = 32'h00000000; +parameter mask_dmac0_s__CSR5 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC5 = 32'hF800312C; +parameter val_dmac0_s__CPC5 = 32'h00000000; +parameter mask_dmac0_s__CPC5 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR6 = 32'hF8003130; +parameter val_dmac0_s__CSR6 = 32'h00000000; +parameter mask_dmac0_s__CSR6 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC6 = 32'hF8003134; +parameter val_dmac0_s__CPC6 = 32'h00000000; +parameter mask_dmac0_s__CPC6 = 32'hFFFFFFFF; + +parameter dmac0_s__CSR7 = 32'hF8003138; +parameter val_dmac0_s__CSR7 = 32'h00000000; +parameter mask_dmac0_s__CSR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CPC7 = 32'hF800313C; +parameter val_dmac0_s__CPC7 = 32'h00000000; +parameter mask_dmac0_s__CPC7 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR0 = 32'hF8003400; +parameter val_dmac0_s__SAR0 = 32'h00000000; +parameter mask_dmac0_s__SAR0 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR0 = 32'hF8003404; +parameter val_dmac0_s__DAR0 = 32'h00000000; +parameter mask_dmac0_s__DAR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR0 = 32'hF8003408; +parameter val_dmac0_s__CCR0 = 32'h00800200; +parameter mask_dmac0_s__CCR0 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_0 = 32'hF800340C; +parameter val_dmac0_s__LC0_0 = 32'h00000000; +parameter mask_dmac0_s__LC0_0 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_0 = 32'hF8003410; +parameter val_dmac0_s__LC1_0 = 32'h00000000; +parameter mask_dmac0_s__LC1_0 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR1 = 32'hF8003420; +parameter val_dmac0_s__SAR1 = 32'h00000000; +parameter mask_dmac0_s__SAR1 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR1 = 32'hF8003424; +parameter val_dmac0_s__DAR1 = 32'h00000000; +parameter mask_dmac0_s__DAR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR1 = 32'hF8003428; +parameter val_dmac0_s__CCR1 = 32'h00800200; +parameter mask_dmac0_s__CCR1 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_1 = 32'hF800342C; +parameter val_dmac0_s__LC0_1 = 32'h00000000; +parameter mask_dmac0_s__LC0_1 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_1 = 32'hF8003430; +parameter val_dmac0_s__LC1_1 = 32'h00000000; +parameter mask_dmac0_s__LC1_1 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR2 = 32'hF8003440; +parameter val_dmac0_s__SAR2 = 32'h00000000; +parameter mask_dmac0_s__SAR2 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR2 = 32'hF8003444; +parameter val_dmac0_s__DAR2 = 32'h00000000; +parameter mask_dmac0_s__DAR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR2 = 32'hF8003448; +parameter val_dmac0_s__CCR2 = 32'h00800200; +parameter mask_dmac0_s__CCR2 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_2 = 32'hF800344C; +parameter val_dmac0_s__LC0_2 = 32'h00000000; +parameter mask_dmac0_s__LC0_2 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_2 = 32'hF8003450; +parameter val_dmac0_s__LC1_2 = 32'h00000000; +parameter mask_dmac0_s__LC1_2 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR3 = 32'hF8003460; +parameter val_dmac0_s__SAR3 = 32'h00000000; +parameter mask_dmac0_s__SAR3 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR3 = 32'hF8003464; +parameter val_dmac0_s__DAR3 = 32'h00000000; +parameter mask_dmac0_s__DAR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR3 = 32'hF8003468; +parameter val_dmac0_s__CCR3 = 32'h00800200; +parameter mask_dmac0_s__CCR3 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_3 = 32'hF800346C; +parameter val_dmac0_s__LC0_3 = 32'h00000000; +parameter mask_dmac0_s__LC0_3 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_3 = 32'hF8003470; +parameter val_dmac0_s__LC1_3 = 32'h00000000; +parameter mask_dmac0_s__LC1_3 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR4 = 32'hF8003480; +parameter val_dmac0_s__SAR4 = 32'h00000000; +parameter mask_dmac0_s__SAR4 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR4 = 32'hF8003484; +parameter val_dmac0_s__DAR4 = 32'h00000000; +parameter mask_dmac0_s__DAR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR4 = 32'hF8003488; +parameter val_dmac0_s__CCR4 = 32'h00800200; +parameter mask_dmac0_s__CCR4 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_4 = 32'hF800348C; +parameter val_dmac0_s__LC0_4 = 32'h00000000; +parameter mask_dmac0_s__LC0_4 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_4 = 32'hF8003490; +parameter val_dmac0_s__LC1_4 = 32'h00000000; +parameter mask_dmac0_s__LC1_4 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR5 = 32'hF80034A0; +parameter val_dmac0_s__SAR5 = 32'h00000000; +parameter mask_dmac0_s__SAR5 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR5 = 32'hF80034A4; +parameter val_dmac0_s__DAR5 = 32'h00000000; +parameter mask_dmac0_s__DAR5 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR5 = 32'hF80034A8; +parameter val_dmac0_s__CCR5 = 32'h00800200; +parameter mask_dmac0_s__CCR5 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_5 = 32'hF80034AC; +parameter val_dmac0_s__LC0_5 = 32'h00000000; +parameter mask_dmac0_s__LC0_5 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_5 = 32'hF80034B0; +parameter val_dmac0_s__LC1_5 = 32'h00000000; +parameter mask_dmac0_s__LC1_5 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR6 = 32'hF80034C0; +parameter val_dmac0_s__SAR6 = 32'h00000000; +parameter mask_dmac0_s__SAR6 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR6 = 32'hF80034C4; +parameter val_dmac0_s__DAR6 = 32'h00000000; +parameter mask_dmac0_s__DAR6 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR6 = 32'hF80034C8; +parameter val_dmac0_s__CCR6 = 32'h00800200; +parameter mask_dmac0_s__CCR6 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_6 = 32'hF80034CC; +parameter val_dmac0_s__LC0_6 = 32'h00000000; +parameter mask_dmac0_s__LC0_6 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_6 = 32'hF80034D0; +parameter val_dmac0_s__LC1_6 = 32'h00000000; +parameter mask_dmac0_s__LC1_6 = 32'hFFFFFFFF; + +parameter dmac0_s__SAR7 = 32'hF80034E0; +parameter val_dmac0_s__SAR7 = 32'h00000000; +parameter mask_dmac0_s__SAR7 = 32'hFFFFFFFF; + +parameter dmac0_s__DAR7 = 32'hF80034E4; +parameter val_dmac0_s__DAR7 = 32'h00000000; +parameter mask_dmac0_s__DAR7 = 32'hFFFFFFFF; + +parameter dmac0_s__CCR7 = 32'hF80034E8; +parameter val_dmac0_s__CCR7 = 32'h00800200; +parameter mask_dmac0_s__CCR7 = 32'hFFFFFFFF; + +parameter dmac0_s__LC0_7 = 32'hF80034EC; +parameter val_dmac0_s__LC0_7 = 32'h00000000; +parameter mask_dmac0_s__LC0_7 = 32'hFFFFFFFF; + +parameter dmac0_s__LC1_7 = 32'hF80034F0; +parameter val_dmac0_s__LC1_7 = 32'h00000000; +parameter mask_dmac0_s__LC1_7 = 32'hFFFFFFFF; + +parameter dmac0_s__DBGSTATUS = 32'hF8003D00; +parameter val_dmac0_s__DBGSTATUS = 32'h00000000; +parameter mask_dmac0_s__DBGSTATUS = 32'hFFFFFFFF; + +parameter dmac0_s__DBGCMD = 32'hF8003D04; +parameter val_dmac0_s__DBGCMD = 32'h00000000; +parameter mask_dmac0_s__DBGCMD = 32'hFFFFFFFF; + +parameter dmac0_s__DBGINST0 = 32'hF8003D08; +parameter val_dmac0_s__DBGINST0 = 32'h00000000; +parameter mask_dmac0_s__DBGINST0 = 32'hFFFFFFFF; + +parameter dmac0_s__DBGINST1 = 32'hF8003D0C; +parameter val_dmac0_s__DBGINST1 = 32'h00000000; +parameter mask_dmac0_s__DBGINST1 = 32'hFFFFFFFF; + +parameter dmac0_s__CR0 = 32'hF8003E00; +parameter val_dmac0_s__CR0 = 32'h001E3071; +parameter mask_dmac0_s__CR0 = 32'hFFFFFFFF; + +parameter dmac0_s__CR1 = 32'hF8003E04; +parameter val_dmac0_s__CR1 = 32'h00000074; +parameter mask_dmac0_s__CR1 = 32'hFFFFFFFF; + +parameter dmac0_s__CR2 = 32'hF8003E08; +parameter val_dmac0_s__CR2 = 32'h00000000; +parameter mask_dmac0_s__CR2 = 32'hFFFFFFFF; + +parameter dmac0_s__CR3 = 32'hF8003E0C; +parameter val_dmac0_s__CR3 = 32'h00000000; +parameter mask_dmac0_s__CR3 = 32'hFFFFFFFF; + +parameter dmac0_s__CR4 = 32'hF8003E10; +parameter val_dmac0_s__CR4 = 32'h00000000; +parameter mask_dmac0_s__CR4 = 32'hFFFFFFFF; + +parameter dmac0_s__CRD = 32'hF8003E14; +parameter val_dmac0_s__CRD = 32'h07FF7F73; +parameter mask_dmac0_s__CRD = 32'hFFFFFFFF; + +parameter dmac0_s__WD = 32'hF8003E80; +parameter val_dmac0_s__WD = 32'h00000000; +parameter mask_dmac0_s__WD = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_0 = 32'hF8003FE0; +parameter val_dmac0_s__periph_id_0 = 32'h00000030; +parameter mask_dmac0_s__periph_id_0 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_1 = 32'hF8003FE4; +parameter val_dmac0_s__periph_id_1 = 32'h00000013; +parameter mask_dmac0_s__periph_id_1 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_2 = 32'hF8003FE8; +parameter val_dmac0_s__periph_id_2 = 32'h00000024; +parameter mask_dmac0_s__periph_id_2 = 32'hFFFFFFFF; + +parameter dmac0_s__periph_id_3 = 32'hF8003FEC; +parameter val_dmac0_s__periph_id_3 = 32'h00000000; +parameter mask_dmac0_s__periph_id_3 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_0 = 32'hF8003FF0; +parameter val_dmac0_s__pcell_id_0 = 32'h0000000D; +parameter mask_dmac0_s__pcell_id_0 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_1 = 32'hF8003FF4; +parameter val_dmac0_s__pcell_id_1 = 32'h000000F0; +parameter mask_dmac0_s__pcell_id_1 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_2 = 32'hF8003FF8; +parameter val_dmac0_s__pcell_id_2 = 32'h00000005; +parameter mask_dmac0_s__pcell_id_2 = 32'hFFFFFFFF; + +parameter dmac0_s__pcell_id_3 = 32'hF8003FFC; +parameter val_dmac0_s__pcell_id_3 = 32'h000000B1; +parameter mask_dmac0_s__pcell_id_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module efuse_ctrl efuse_ctrl +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter efuse_ctrl__WR_LOCK = 32'hF800D000; +parameter val_efuse_ctrl__WR_LOCK = 32'h00000000; +parameter mask_efuse_ctrl__WR_LOCK = 32'hFFFFFFFF; + +parameter efuse_ctrl__WR_UNLOCK = 32'hF800D004; +parameter val_efuse_ctrl__WR_UNLOCK = 32'h00000000; +parameter mask_efuse_ctrl__WR_UNLOCK = 32'hFFFFFFFF; + +parameter efuse_ctrl__WR_LOCKSTA = 32'hF800D008; +parameter val_efuse_ctrl__WR_LOCKSTA = 32'h00000001; +parameter mask_efuse_ctrl__WR_LOCKSTA = 32'hFFFFFFFF; + +parameter efuse_ctrl__CFG = 32'hF800D00C; +parameter val_efuse_ctrl__CFG = 32'h00010F00; +parameter mask_efuse_ctrl__CFG = 32'hFFFFFFFF; + +parameter efuse_ctrl__STATUS = 32'hF800D010; +parameter val_efuse_ctrl__STATUS = 32'h00100000; +parameter mask_efuse_ctrl__STATUS = 32'hFFFFFFFF; + +parameter efuse_ctrl__CONTROL = 32'hF800D014; +parameter val_efuse_ctrl__CONTROL = 32'h00000003; +parameter mask_efuse_ctrl__CONTROL = 32'hFFFFFFFF; + +parameter efuse_ctrl__PGM_STBW = 32'hF800D018; +parameter val_efuse_ctrl__PGM_STBW = 32'h000002D0; +parameter mask_efuse_ctrl__PGM_STBW = 32'hFFFFFFFF; + +parameter efuse_ctrl__RD_STBW = 32'hF800D01C; +parameter val_efuse_ctrl__RD_STBW = 32'h0000000B; +parameter mask_efuse_ctrl__RD_STBW = 32'hFFFFFFFF; + + +// ************************************************************ +// Module gem0 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gem0__net_ctrl = 32'hE000B000; +parameter val_gem0__net_ctrl = 32'h00000000; +parameter mask_gem0__net_ctrl = 32'hFFFFFFFF; + +parameter gem0__net_cfg = 32'hE000B004; +parameter val_gem0__net_cfg = 32'h00080000; +parameter mask_gem0__net_cfg = 32'hFFFFFFFF; + +parameter gem0__net_status = 32'hE000B008; +parameter val_gem0__net_status = 32'h00000004; +parameter mask_gem0__net_status = 32'hFFFFFFFD; + +parameter gem0__user_io = 32'hE000B00C; +parameter val_gem0__user_io = 32'h00000000; +parameter mask_gem0__user_io = 32'h0000FFFF; + +parameter gem0__dma_cfg = 32'hE000B010; +parameter val_gem0__dma_cfg = 32'h00020784; +parameter mask_gem0__dma_cfg = 32'hFFFFFFFF; + +parameter gem0__tx_status = 32'hE000B014; +parameter val_gem0__tx_status = 32'h00000000; +parameter mask_gem0__tx_status = 32'hFFFFFFFF; + +parameter gem0__rx_qbar = 32'hE000B018; +parameter val_gem0__rx_qbar = 32'h00000000; +parameter mask_gem0__rx_qbar = 32'hFFFFFFFF; + +parameter gem0__tx_qbar = 32'hE000B01C; +parameter val_gem0__tx_qbar = 32'h00000000; +parameter mask_gem0__tx_qbar = 32'hFFFFFFFF; + +parameter gem0__rx_status = 32'hE000B020; +parameter val_gem0__rx_status = 32'h00000000; +parameter mask_gem0__rx_status = 32'hFFFFFFFF; + +parameter gem0__intr_status = 32'hE000B024; +parameter val_gem0__intr_status = 32'h00000000; +parameter mask_gem0__intr_status = 32'hFFFFFFFF; + +parameter gem0__intr_en = 32'hE000B028; +parameter val_gem0__intr_en = 32'h00000000; +parameter mask_gem0__intr_en = 32'h00000000; + +parameter gem0__intr_dis = 32'hE000B02C; +parameter val_gem0__intr_dis = 32'h00000000; +parameter mask_gem0__intr_dis = 32'h00000000; + +parameter gem0__intr_mask = 32'hE000B030; +parameter val_gem0__intr_mask = 32'h0001FFFF; +parameter mask_gem0__intr_mask = 32'hFC01FFFF; + +parameter gem0__phy_maint = 32'hE000B034; +parameter val_gem0__phy_maint = 32'h00000000; +parameter mask_gem0__phy_maint = 32'hFFFFFFFF; + +parameter gem0__rx_pauseq = 32'hE000B038; +parameter val_gem0__rx_pauseq = 32'h00000000; +parameter mask_gem0__rx_pauseq = 32'hFFFFFFFF; + +parameter gem0__tx_pauseq = 32'hE000B03C; +parameter val_gem0__tx_pauseq = 32'h0000FFFF; +parameter mask_gem0__tx_pauseq = 32'hFFFFFFFF; + +parameter gem0__tx_partial_st_fwd = 32'hE000B040; +parameter val_gem0__tx_partial_st_fwd = 32'h000003FF; +parameter mask_gem0__tx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem0__rx_partial_st_fwd = 32'hE000B044; +parameter val_gem0__rx_partial_st_fwd = 32'h000003FF; +parameter mask_gem0__rx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem0__hash_bot = 32'hE000B080; +parameter val_gem0__hash_bot = 32'h00000000; +parameter mask_gem0__hash_bot = 32'hFFFFFFFF; + +parameter gem0__hash_top = 32'hE000B084; +parameter val_gem0__hash_top = 32'h00000000; +parameter mask_gem0__hash_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_bot = 32'hE000B088; +parameter val_gem0__spec_addr1_bot = 32'h00000000; +parameter mask_gem0__spec_addr1_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_top = 32'hE000B08C; +parameter val_gem0__spec_addr1_top = 32'h00000000; +parameter mask_gem0__spec_addr1_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr2_bot = 32'hE000B090; +parameter val_gem0__spec_addr2_bot = 32'h00000000; +parameter mask_gem0__spec_addr2_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr2_top = 32'hE000B094; +parameter val_gem0__spec_addr2_top = 32'h00000000; +parameter mask_gem0__spec_addr2_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr3_bot = 32'hE000B098; +parameter val_gem0__spec_addr3_bot = 32'h00000000; +parameter mask_gem0__spec_addr3_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr3_top = 32'hE000B09C; +parameter val_gem0__spec_addr3_top = 32'h00000000; +parameter mask_gem0__spec_addr3_top = 32'hFFFFFFFF; + +parameter gem0__spec_addr4_bot = 32'hE000B0A0; +parameter val_gem0__spec_addr4_bot = 32'h00000000; +parameter mask_gem0__spec_addr4_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr4_top = 32'hE000B0A4; +parameter val_gem0__spec_addr4_top = 32'h00000000; +parameter mask_gem0__spec_addr4_top = 32'hFFFFFFFF; + +parameter gem0__type_id_match1 = 32'hE000B0A8; +parameter val_gem0__type_id_match1 = 32'h00000000; +parameter mask_gem0__type_id_match1 = 32'hFFFFFFFF; + +parameter gem0__type_id_match2 = 32'hE000B0AC; +parameter val_gem0__type_id_match2 = 32'h00000000; +parameter mask_gem0__type_id_match2 = 32'hFFFFFFFF; + +parameter gem0__type_id_match3 = 32'hE000B0B0; +parameter val_gem0__type_id_match3 = 32'h00000000; +parameter mask_gem0__type_id_match3 = 32'hFFFFFFFF; + +parameter gem0__type_id_match4 = 32'hE000B0B4; +parameter val_gem0__type_id_match4 = 32'h00000000; +parameter mask_gem0__type_id_match4 = 32'hFFFFFFFF; + +parameter gem0__wake_on_lan = 32'hE000B0B8; +parameter val_gem0__wake_on_lan = 32'h00000000; +parameter mask_gem0__wake_on_lan = 32'hFFFFFFFF; + +parameter gem0__ipg_stretch = 32'hE000B0BC; +parameter val_gem0__ipg_stretch = 32'h00000000; +parameter mask_gem0__ipg_stretch = 32'hFFFFFFFF; + +parameter gem0__stacked_vlan = 32'hE000B0C0; +parameter val_gem0__stacked_vlan = 32'h00000000; +parameter mask_gem0__stacked_vlan = 32'hFFFFFFFF; + +parameter gem0__tx_pfc_pause = 32'hE000B0C4; +parameter val_gem0__tx_pfc_pause = 32'h00000000; +parameter mask_gem0__tx_pfc_pause = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_mask_bot = 32'hE000B0C8; +parameter val_gem0__spec_addr1_mask_bot = 32'h00000000; +parameter mask_gem0__spec_addr1_mask_bot = 32'hFFFFFFFF; + +parameter gem0__spec_addr1_mask_top = 32'hE000B0CC; +parameter val_gem0__spec_addr1_mask_top = 32'h00000000; +parameter mask_gem0__spec_addr1_mask_top = 32'hFFFFFFFF; + +parameter gem0__module_id = 32'hE000B0FC; +parameter val_gem0__module_id = 32'h00020118; +parameter mask_gem0__module_id = 32'hFFFFFFFF; + +parameter gem0__octets_tx_bot = 32'hE000B100; +parameter val_gem0__octets_tx_bot = 32'h00000000; +parameter mask_gem0__octets_tx_bot = 32'hFFFFFFFF; + +parameter gem0__octets_tx_top = 32'hE000B104; +parameter val_gem0__octets_tx_top = 32'h00000000; +parameter mask_gem0__octets_tx_top = 32'hFFFFFFFF; + +parameter gem0__frames_tx = 32'hE000B108; +parameter val_gem0__frames_tx = 32'h00000000; +parameter mask_gem0__frames_tx = 32'hFFFFFFFF; + +parameter gem0__broadcast_frames_tx = 32'hE000B10C; +parameter val_gem0__broadcast_frames_tx = 32'h00000000; +parameter mask_gem0__broadcast_frames_tx = 32'hFFFFFFFF; + +parameter gem0__multi_frames_tx = 32'hE000B110; +parameter val_gem0__multi_frames_tx = 32'h00000000; +parameter mask_gem0__multi_frames_tx = 32'hFFFFFFFF; + +parameter gem0__pause_frames_tx = 32'hE000B114; +parameter val_gem0__pause_frames_tx = 32'h00000000; +parameter mask_gem0__pause_frames_tx = 32'hFFFFFFFF; + +parameter gem0__frames_64b_tx = 32'hE000B118; +parameter val_gem0__frames_64b_tx = 32'h00000000; +parameter mask_gem0__frames_64b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_65to127b_tx = 32'hE000B11C; +parameter val_gem0__frames_65to127b_tx = 32'h00000000; +parameter mask_gem0__frames_65to127b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_128to255b_tx = 32'hE000B120; +parameter val_gem0__frames_128to255b_tx = 32'h00000000; +parameter mask_gem0__frames_128to255b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_256to511b_tx = 32'hE000B124; +parameter val_gem0__frames_256to511b_tx = 32'h00000000; +parameter mask_gem0__frames_256to511b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_512to1023b_tx = 32'hE000B128; +parameter val_gem0__frames_512to1023b_tx = 32'h00000000; +parameter mask_gem0__frames_512to1023b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_1024to1518b_tx = 32'hE000B12C; +parameter val_gem0__frames_1024to1518b_tx = 32'h00000000; +parameter mask_gem0__frames_1024to1518b_tx = 32'hFFFFFFFF; + +parameter gem0__frames_gt1518b_tx = 32'hE000B130; +parameter val_gem0__frames_gt1518b_tx = 32'h00000000; +parameter mask_gem0__frames_gt1518b_tx = 32'hFFFFFFFF; + +parameter gem0__tx_under_runs = 32'hE000B134; +parameter val_gem0__tx_under_runs = 32'h00000000; +parameter mask_gem0__tx_under_runs = 32'hFFFFFFFF; + +parameter gem0__single_collisn_frames = 32'hE000B138; +parameter val_gem0__single_collisn_frames = 32'h00000000; +parameter mask_gem0__single_collisn_frames = 32'hFFFFFFFF; + +parameter gem0__multi_collisn_frames = 32'hE000B13C; +parameter val_gem0__multi_collisn_frames = 32'h00000000; +parameter mask_gem0__multi_collisn_frames = 32'hFFFFFFFF; + +parameter gem0__excessive_collisns = 32'hE000B140; +parameter val_gem0__excessive_collisns = 32'h00000000; +parameter mask_gem0__excessive_collisns = 32'hFFFFFFFF; + +parameter gem0__late_collisns = 32'hE000B144; +parameter val_gem0__late_collisns = 32'h00000000; +parameter mask_gem0__late_collisns = 32'hFFFFFFFF; + +parameter gem0__deferred_tx_frames = 32'hE000B148; +parameter val_gem0__deferred_tx_frames = 32'h00000000; +parameter mask_gem0__deferred_tx_frames = 32'hFFFFFFFF; + +parameter gem0__carrier_sense_errs = 32'hE000B14C; +parameter val_gem0__carrier_sense_errs = 32'h00000000; +parameter mask_gem0__carrier_sense_errs = 32'hFFFFFFFF; + +parameter gem0__octets_rx_bot = 32'hE000B150; +parameter val_gem0__octets_rx_bot = 32'h00000000; +parameter mask_gem0__octets_rx_bot = 32'hFFFFFFFF; + +parameter gem0__octets_rx_top = 32'hE000B154; +parameter val_gem0__octets_rx_top = 32'h00000000; +parameter mask_gem0__octets_rx_top = 32'hFFFFFFFF; + +parameter gem0__frames_rx = 32'hE000B158; +parameter val_gem0__frames_rx = 32'h00000000; +parameter mask_gem0__frames_rx = 32'hFFFFFFFF; + +parameter gem0__bdcast_fames_rx = 32'hE000B15C; +parameter val_gem0__bdcast_fames_rx = 32'h00000000; +parameter mask_gem0__bdcast_fames_rx = 32'hFFFFFFFF; + +parameter gem0__multi_frames_rx = 32'hE000B160; +parameter val_gem0__multi_frames_rx = 32'h00000000; +parameter mask_gem0__multi_frames_rx = 32'hFFFFFFFF; + +parameter gem0__pause_rx = 32'hE000B164; +parameter val_gem0__pause_rx = 32'h00000000; +parameter mask_gem0__pause_rx = 32'hFFFFFFFF; + +parameter gem0__frames_64b_rx = 32'hE000B168; +parameter val_gem0__frames_64b_rx = 32'h00000000; +parameter mask_gem0__frames_64b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_65to127b_rx = 32'hE000B16C; +parameter val_gem0__frames_65to127b_rx = 32'h00000000; +parameter mask_gem0__frames_65to127b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_128to255b_rx = 32'hE000B170; +parameter val_gem0__frames_128to255b_rx = 32'h00000000; +parameter mask_gem0__frames_128to255b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_256to511b_rx = 32'hE000B174; +parameter val_gem0__frames_256to511b_rx = 32'h00000000; +parameter mask_gem0__frames_256to511b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_512to1023b_rx = 32'hE000B178; +parameter val_gem0__frames_512to1023b_rx = 32'h00000000; +parameter mask_gem0__frames_512to1023b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_1024to1518b_rx = 32'hE000B17C; +parameter val_gem0__frames_1024to1518b_rx = 32'h00000000; +parameter mask_gem0__frames_1024to1518b_rx = 32'hFFFFFFFF; + +parameter gem0__frames_gt1518b_rx = 32'hE000B180; +parameter val_gem0__frames_gt1518b_rx = 32'h00000000; +parameter mask_gem0__frames_gt1518b_rx = 32'hFFFFFFFF; + +parameter gem0__undersz_rx = 32'hE000B184; +parameter val_gem0__undersz_rx = 32'h00000000; +parameter mask_gem0__undersz_rx = 32'hFFFFFFFF; + +parameter gem0__oversz_rx = 32'hE000B188; +parameter val_gem0__oversz_rx = 32'h00000000; +parameter mask_gem0__oversz_rx = 32'hFFFFFFFF; + +parameter gem0__jab_rx = 32'hE000B18C; +parameter val_gem0__jab_rx = 32'h00000000; +parameter mask_gem0__jab_rx = 32'hFFFFFFFF; + +parameter gem0__fcs_errors = 32'hE000B190; +parameter val_gem0__fcs_errors = 32'h00000000; +parameter mask_gem0__fcs_errors = 32'hFFFFFFFF; + +parameter gem0__length_field_errors = 32'hE000B194; +parameter val_gem0__length_field_errors = 32'h00000000; +parameter mask_gem0__length_field_errors = 32'hFFFFFFFF; + +parameter gem0__rx_symbol_errors = 32'hE000B198; +parameter val_gem0__rx_symbol_errors = 32'h00000000; +parameter mask_gem0__rx_symbol_errors = 32'hFFFFFFFF; + +parameter gem0__align_errors = 32'hE000B19C; +parameter val_gem0__align_errors = 32'h00000000; +parameter mask_gem0__align_errors = 32'hFFFFFFFF; + +parameter gem0__rx_resource_errors = 32'hE000B1A0; +parameter val_gem0__rx_resource_errors = 32'h00000000; +parameter mask_gem0__rx_resource_errors = 32'hFFFFFFFF; + +parameter gem0__rx_overrun_errors = 32'hE000B1A4; +parameter val_gem0__rx_overrun_errors = 32'h00000000; +parameter mask_gem0__rx_overrun_errors = 32'hFFFFFFFF; + +parameter gem0__ip_hdr_csum_errors = 32'hE000B1A8; +parameter val_gem0__ip_hdr_csum_errors = 32'h00000000; +parameter mask_gem0__ip_hdr_csum_errors = 32'hFFFFFFFF; + +parameter gem0__tcp_csum_errors = 32'hE000B1AC; +parameter val_gem0__tcp_csum_errors = 32'h00000000; +parameter mask_gem0__tcp_csum_errors = 32'hFFFFFFFF; + +parameter gem0__udp_csum_errors = 32'hE000B1B0; +parameter val_gem0__udp_csum_errors = 32'h00000000; +parameter mask_gem0__udp_csum_errors = 32'hFFFFFFFF; + +parameter gem0__timer_strobe_s = 32'hE000B1C8; +parameter val_gem0__timer_strobe_s = 32'h00000000; +parameter mask_gem0__timer_strobe_s = 32'hFFFFFFFF; + +parameter gem0__timer_strobe_ns = 32'hE000B1CC; +parameter val_gem0__timer_strobe_ns = 32'h00000000; +parameter mask_gem0__timer_strobe_ns = 32'hFFFFFFFF; + +parameter gem0__timer_s = 32'hE000B1D0; +parameter val_gem0__timer_s = 32'h00000000; +parameter mask_gem0__timer_s = 32'hFFFFFFFF; + +parameter gem0__timer_ns = 32'hE000B1D4; +parameter val_gem0__timer_ns = 32'h00000000; +parameter mask_gem0__timer_ns = 32'hFFFFFFFF; + +parameter gem0__timer_adjust = 32'hE000B1D8; +parameter val_gem0__timer_adjust = 32'h00000000; +parameter mask_gem0__timer_adjust = 32'hFFFFFFFF; + +parameter gem0__timer_incr = 32'hE000B1DC; +parameter val_gem0__timer_incr = 32'h00000000; +parameter mask_gem0__timer_incr = 32'hFFFFFFFF; + +parameter gem0__ptp_tx_s = 32'hE000B1E0; +parameter val_gem0__ptp_tx_s = 32'h00000000; +parameter mask_gem0__ptp_tx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_tx_ns = 32'hE000B1E4; +parameter val_gem0__ptp_tx_ns = 32'h00000000; +parameter mask_gem0__ptp_tx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_rx_s = 32'hE000B1E8; +parameter val_gem0__ptp_rx_s = 32'h00000000; +parameter mask_gem0__ptp_rx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_rx_ns = 32'hE000B1EC; +parameter val_gem0__ptp_rx_ns = 32'h00000000; +parameter mask_gem0__ptp_rx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_tx_s = 32'hE000B1F0; +parameter val_gem0__ptp_peer_tx_s = 32'h00000000; +parameter mask_gem0__ptp_peer_tx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_tx_ns = 32'hE000B1F4; +parameter val_gem0__ptp_peer_tx_ns = 32'h00000000; +parameter mask_gem0__ptp_peer_tx_ns = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_rx_s = 32'hE000B1F8; +parameter val_gem0__ptp_peer_rx_s = 32'h00000000; +parameter mask_gem0__ptp_peer_rx_s = 32'hFFFFFFFF; + +parameter gem0__ptp_peer_rx_ns = 32'hE000B1FC; +parameter val_gem0__ptp_peer_rx_ns = 32'h00000000; +parameter mask_gem0__ptp_peer_rx_ns = 32'hFFFFFFFF; + +parameter gem0__pcs_ctrl = 32'hE000B200; +parameter val_gem0__pcs_ctrl = 32'h00000000; +parameter mask_gem0__pcs_ctrl = 32'h00000000; + +parameter gem0__pcs_status = 32'hE000B204; +parameter val_gem0__pcs_status = 32'h00000000; +parameter mask_gem0__pcs_status = 32'h00000000; + +parameter gem0__pcs_upper_phy_id = 32'hE000B208; +parameter val_gem0__pcs_upper_phy_id = 32'h00000000; +parameter mask_gem0__pcs_upper_phy_id = 32'h00000000; + +parameter gem0__pcs_lower_phy_id = 32'hE000B20C; +parameter val_gem0__pcs_lower_phy_id = 32'h00000000; +parameter mask_gem0__pcs_lower_phy_id = 32'h00000000; + +parameter gem0__pcs_autoneg_ad = 32'hE000B210; +parameter val_gem0__pcs_autoneg_ad = 32'h00000000; +parameter mask_gem0__pcs_autoneg_ad = 32'h00000000; + +parameter gem0__pcs_autoneg_ability = 32'hE000B214; +parameter val_gem0__pcs_autoneg_ability = 32'h00000000; +parameter mask_gem0__pcs_autoneg_ability = 32'h00000000; + +parameter gem0__pcs_autonec_exp = 32'hE000B218; +parameter val_gem0__pcs_autonec_exp = 32'h00000000; +parameter mask_gem0__pcs_autonec_exp = 32'h00000000; + +parameter gem0__pcs_autoneg_next_pg = 32'hE000B21C; +parameter val_gem0__pcs_autoneg_next_pg = 32'h00000000; +parameter mask_gem0__pcs_autoneg_next_pg = 32'h00000000; + +parameter gem0__pcs_autoneg_pnext_pg = 32'hE000B220; +parameter val_gem0__pcs_autoneg_pnext_pg = 32'h00000000; +parameter mask_gem0__pcs_autoneg_pnext_pg = 32'h00000000; + +parameter gem0__pcs_extended_status = 32'hE000B23C; +parameter val_gem0__pcs_extended_status = 32'h00000000; +parameter mask_gem0__pcs_extended_status = 32'h00000000; + +parameter gem0__design_cfg1 = 32'hE000B280; +parameter val_gem0__design_cfg1 = 32'h02000000; +parameter mask_gem0__design_cfg1 = 32'h0E000000; + +parameter gem0__design_cfg2 = 32'hE000B284; +parameter val_gem0__design_cfg2 = 32'h2A813FFF; +parameter mask_gem0__design_cfg2 = 32'h3FCFFFFF; + +parameter gem0__design_cfg3 = 32'hE000B288; +parameter val_gem0__design_cfg3 = 32'h00000000; +parameter mask_gem0__design_cfg3 = 32'hFFFFFFFF; + +parameter gem0__design_cfg4 = 32'hE000B28C; +parameter val_gem0__design_cfg4 = 32'h00000000; +parameter mask_gem0__design_cfg4 = 32'hFFFFFFFF; + +parameter gem0__design_cfg5 = 32'hE000B290; +parameter val_gem0__design_cfg5 = 32'h002F2045; +parameter mask_gem0__design_cfg5 = 32'h0FFFFCFF; + +parameter gem0__design_cfg6 = 32'hE000B294; +parameter val_gem0__design_cfg6 = 32'h00000000; +parameter mask_gem0__design_cfg6 = 32'h00000000; + +parameter gem0__design_cfg7 = 32'hE000B298; +parameter val_gem0__design_cfg7 = 32'h00000000; +parameter mask_gem0__design_cfg7 = 32'h00000000; + +parameter gem0__isr_pq1 = 32'hE000B400; +parameter val_gem0__isr_pq1 = 32'h00000000; +parameter mask_gem0__isr_pq1 = 32'h00000000; + +parameter gem0__isr_pq2 = 32'hE000B404; +parameter val_gem0__isr_pq2 = 32'h00000000; +parameter mask_gem0__isr_pq2 = 32'h00000000; + +parameter gem0__isr_pq3 = 32'hE000B408; +parameter val_gem0__isr_pq3 = 32'h00000000; +parameter mask_gem0__isr_pq3 = 32'h00000000; + +parameter gem0__isr_pq4 = 32'hE000B40C; +parameter val_gem0__isr_pq4 = 32'h00000000; +parameter mask_gem0__isr_pq4 = 32'h00000000; + +parameter gem0__isr_pq5 = 32'hE000B410; +parameter val_gem0__isr_pq5 = 32'h00000000; +parameter mask_gem0__isr_pq5 = 32'h00000000; + +parameter gem0__isr_pq6 = 32'hE000B414; +parameter val_gem0__isr_pq6 = 32'h00000000; +parameter mask_gem0__isr_pq6 = 32'h00000000; + +parameter gem0__isr_pq7 = 32'hE000B418; +parameter val_gem0__isr_pq7 = 32'h00000000; +parameter mask_gem0__isr_pq7 = 32'h00000000; + +parameter gem0__tx_qbar_q1 = 32'hE000B440; +parameter val_gem0__tx_qbar_q1 = 32'h00000000; +parameter mask_gem0__tx_qbar_q1 = 32'h00000000; + +parameter gem0__tx_qbar_q2 = 32'hE000B444; +parameter val_gem0__tx_qbar_q2 = 32'h00000000; +parameter mask_gem0__tx_qbar_q2 = 32'h00000000; + +parameter gem0__tx_qbar_q3 = 32'hE000B448; +parameter val_gem0__tx_qbar_q3 = 32'h00000000; +parameter mask_gem0__tx_qbar_q3 = 32'h00000000; + +parameter gem0__tx_qbar_q4 = 32'hE000B44C; +parameter val_gem0__tx_qbar_q4 = 32'h00000000; +parameter mask_gem0__tx_qbar_q4 = 32'h00000000; + +parameter gem0__tx_qbar_q5 = 32'hE000B450; +parameter val_gem0__tx_qbar_q5 = 32'h00000000; +parameter mask_gem0__tx_qbar_q5 = 32'h00000000; + +parameter gem0__tx_qbar_q6 = 32'hE000B454; +parameter val_gem0__tx_qbar_q6 = 32'h00000000; +parameter mask_gem0__tx_qbar_q6 = 32'h00000000; + +parameter gem0__tx_qbar_q7 = 32'hE000B458; +parameter val_gem0__tx_qbar_q7 = 32'h00000000; +parameter mask_gem0__tx_qbar_q7 = 32'h00000000; + +parameter gem0__rx_qbar_q1 = 32'hE000B480; +parameter val_gem0__rx_qbar_q1 = 32'h00000000; +parameter mask_gem0__rx_qbar_q1 = 32'h00000000; + +parameter gem0__rx_qbar_q2 = 32'hE000B484; +parameter val_gem0__rx_qbar_q2 = 32'h00000000; +parameter mask_gem0__rx_qbar_q2 = 32'h00000000; + +parameter gem0__rx_qbar_q3 = 32'hE000B488; +parameter val_gem0__rx_qbar_q3 = 32'h00000000; +parameter mask_gem0__rx_qbar_q3 = 32'h00000000; + +parameter gem0__rx_qbar_q4 = 32'hE000B48C; +parameter val_gem0__rx_qbar_q4 = 32'h00000000; +parameter mask_gem0__rx_qbar_q4 = 32'h00000000; + +parameter gem0__rx_qbar_q5 = 32'hE000B490; +parameter val_gem0__rx_qbar_q5 = 32'h00000000; +parameter mask_gem0__rx_qbar_q5 = 32'h00000000; + +parameter gem0__rx_qbar_q6 = 32'hE000B494; +parameter val_gem0__rx_qbar_q6 = 32'h00000000; +parameter mask_gem0__rx_qbar_q6 = 32'h00000000; + +parameter gem0__rx_qbar_q7 = 32'hE000B498; +parameter val_gem0__rx_qbar_q7 = 32'h00000000; +parameter mask_gem0__rx_qbar_q7 = 32'h00000000; + +parameter gem0__rx_bufsz_q1 = 32'hE000B4A0; +parameter val_gem0__rx_bufsz_q1 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q1 = 32'h00000000; + +parameter gem0__rx_bufsz_q2 = 32'hE000B4A4; +parameter val_gem0__rx_bufsz_q2 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q2 = 32'h00000000; + +parameter gem0__rx_bufsz_q3 = 32'hE000B4A8; +parameter val_gem0__rx_bufsz_q3 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q3 = 32'h00000000; + +parameter gem0__rx_bufsz_q4 = 32'hE000B4AC; +parameter val_gem0__rx_bufsz_q4 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q4 = 32'h00000000; + +parameter gem0__rx_bufsz_q5 = 32'hE000B4B0; +parameter val_gem0__rx_bufsz_q5 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q5 = 32'h00000000; + +parameter gem0__rx_bufsz_q6 = 32'hE000B4B4; +parameter val_gem0__rx_bufsz_q6 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q6 = 32'h00000000; + +parameter gem0__rx_bufsz_q7 = 32'hE000B4B8; +parameter val_gem0__rx_bufsz_q7 = 32'h00000000; +parameter mask_gem0__rx_bufsz_q7 = 32'h00000000; + +parameter gem0__screen_t1_r0 = 32'hE000B500; +parameter val_gem0__screen_t1_r0 = 32'h00000000; +parameter mask_gem0__screen_t1_r0 = 32'h00000000; + +parameter gem0__screen_t1_r1 = 32'hE000B504; +parameter val_gem0__screen_t1_r1 = 32'h00000000; +parameter mask_gem0__screen_t1_r1 = 32'h00000000; + +parameter gem0__screen_t1_r2 = 32'hE000B508; +parameter val_gem0__screen_t1_r2 = 32'h00000000; +parameter mask_gem0__screen_t1_r2 = 32'h00000000; + +parameter gem0__screen_t1_r3 = 32'hE000B50C; +parameter val_gem0__screen_t1_r3 = 32'h00000000; +parameter mask_gem0__screen_t1_r3 = 32'h00000000; + +parameter gem0__screen_t1_r4 = 32'hE000B510; +parameter val_gem0__screen_t1_r4 = 32'h00000000; +parameter mask_gem0__screen_t1_r4 = 32'h00000000; + +parameter gem0__screen_t1_r5 = 32'hE000B514; +parameter val_gem0__screen_t1_r5 = 32'h00000000; +parameter mask_gem0__screen_t1_r5 = 32'h00000000; + +parameter gem0__screen_t1_r6 = 32'hE000B518; +parameter val_gem0__screen_t1_r6 = 32'h00000000; +parameter mask_gem0__screen_t1_r6 = 32'h00000000; + +parameter gem0__screen_t1_r7 = 32'hE000B51C; +parameter val_gem0__screen_t1_r7 = 32'h00000000; +parameter mask_gem0__screen_t1_r7 = 32'h00000000; + +parameter gem0__screen_t1_r8 = 32'hE000B520; +parameter val_gem0__screen_t1_r8 = 32'h00000000; +parameter mask_gem0__screen_t1_r8 = 32'h00000000; + +parameter gem0__screen_t1_r9 = 32'hE000B524; +parameter val_gem0__screen_t1_r9 = 32'h00000000; +parameter mask_gem0__screen_t1_r9 = 32'h00000000; + +parameter gem0__screen_t1_r10 = 32'hE000B528; +parameter val_gem0__screen_t1_r10 = 32'h00000000; +parameter mask_gem0__screen_t1_r10 = 32'h00000000; + +parameter gem0__screen_t1_r11 = 32'hE000B52C; +parameter val_gem0__screen_t1_r11 = 32'h00000000; +parameter mask_gem0__screen_t1_r11 = 32'h00000000; + +parameter gem0__screen_t1_r12 = 32'hE000B530; +parameter val_gem0__screen_t1_r12 = 32'h00000000; +parameter mask_gem0__screen_t1_r12 = 32'h00000000; + +parameter gem0__screen_t1_r13 = 32'hE000B534; +parameter val_gem0__screen_t1_r13 = 32'h00000000; +parameter mask_gem0__screen_t1_r13 = 32'h00000000; + +parameter gem0__screen_t1_r14 = 32'hE000B538; +parameter val_gem0__screen_t1_r14 = 32'h00000000; +parameter mask_gem0__screen_t1_r14 = 32'h00000000; + +parameter gem0__screen_t1_r15 = 32'hE000B53C; +parameter val_gem0__screen_t1_r15 = 32'h00000000; +parameter mask_gem0__screen_t1_r15 = 32'h00000000; + +parameter gem0__screen_t2_r0 = 32'hE000B540; +parameter val_gem0__screen_t2_r0 = 32'h00000000; +parameter mask_gem0__screen_t2_r0 = 32'h00000000; + +parameter gem0__screen_t2_r1 = 32'hE000B544; +parameter val_gem0__screen_t2_r1 = 32'h00000000; +parameter mask_gem0__screen_t2_r1 = 32'h00000000; + +parameter gem0__screen_t2_r2 = 32'hE000B548; +parameter val_gem0__screen_t2_r2 = 32'h00000000; +parameter mask_gem0__screen_t2_r2 = 32'h00000000; + +parameter gem0__screen_t2_r3 = 32'hE000B54C; +parameter val_gem0__screen_t2_r3 = 32'h00000000; +parameter mask_gem0__screen_t2_r3 = 32'h00000000; + +parameter gem0__screen_t2_r4 = 32'hE000B550; +parameter val_gem0__screen_t2_r4 = 32'h00000000; +parameter mask_gem0__screen_t2_r4 = 32'h00000000; + +parameter gem0__screen_t2_r5 = 32'hE000B554; +parameter val_gem0__screen_t2_r5 = 32'h00000000; +parameter mask_gem0__screen_t2_r5 = 32'h00000000; + +parameter gem0__screen_t2_r6 = 32'hE000B558; +parameter val_gem0__screen_t2_r6 = 32'h00000000; +parameter mask_gem0__screen_t2_r6 = 32'h00000000; + +parameter gem0__screen_t2_r7 = 32'hE000B55C; +parameter val_gem0__screen_t2_r7 = 32'h00000000; +parameter mask_gem0__screen_t2_r7 = 32'h00000000; + +parameter gem0__screen_t2_r8 = 32'hE000B560; +parameter val_gem0__screen_t2_r8 = 32'h00000000; +parameter mask_gem0__screen_t2_r8 = 32'h00000000; + +parameter gem0__screen_t2_r9 = 32'hE000B564; +parameter val_gem0__screen_t2_r9 = 32'h00000000; +parameter mask_gem0__screen_t2_r9 = 32'h00000000; + +parameter gem0__screen_t2_r10 = 32'hE000B568; +parameter val_gem0__screen_t2_r10 = 32'h00000000; +parameter mask_gem0__screen_t2_r10 = 32'h00000000; + +parameter gem0__screen_t2_r11 = 32'hE000B56C; +parameter val_gem0__screen_t2_r11 = 32'h00000000; +parameter mask_gem0__screen_t2_r11 = 32'h00000000; + +parameter gem0__screen_t2_r12 = 32'hE000B570; +parameter val_gem0__screen_t2_r12 = 32'h00000000; +parameter mask_gem0__screen_t2_r12 = 32'h00000000; + +parameter gem0__screen_t2_r13 = 32'hE000B574; +parameter val_gem0__screen_t2_r13 = 32'h00000000; +parameter mask_gem0__screen_t2_r13 = 32'h00000000; + +parameter gem0__screen_t2_r14 = 32'hE000B578; +parameter val_gem0__screen_t2_r14 = 32'h00000000; +parameter mask_gem0__screen_t2_r14 = 32'h00000000; + +parameter gem0__screen_t2_r15 = 32'hE000B57C; +parameter val_gem0__screen_t2_r15 = 32'h00000000; +parameter mask_gem0__screen_t2_r15 = 32'h00000000; + +parameter gem0__intr_en_pq1 = 32'hE000B600; +parameter val_gem0__intr_en_pq1 = 32'h00000000; +parameter mask_gem0__intr_en_pq1 = 32'h00000000; + +parameter gem0__intr_en_pq2 = 32'hE000B604; +parameter val_gem0__intr_en_pq2 = 32'h00000000; +parameter mask_gem0__intr_en_pq2 = 32'h00000000; + +parameter gem0__intr_en_pq3 = 32'hE000B608; +parameter val_gem0__intr_en_pq3 = 32'h00000000; +parameter mask_gem0__intr_en_pq3 = 32'h00000000; + +parameter gem0__intr_en_pq4 = 32'hE000B60C; +parameter val_gem0__intr_en_pq4 = 32'h00000000; +parameter mask_gem0__intr_en_pq4 = 32'h00000000; + +parameter gem0__intr_en_pq5 = 32'hE000B610; +parameter val_gem0__intr_en_pq5 = 32'h00000000; +parameter mask_gem0__intr_en_pq5 = 32'h00000000; + +parameter gem0__intr_en_pq6 = 32'hE000B614; +parameter val_gem0__intr_en_pq6 = 32'h00000000; +parameter mask_gem0__intr_en_pq6 = 32'h00000000; + +parameter gem0__intr_en_pq7 = 32'hE000B618; +parameter val_gem0__intr_en_pq7 = 32'h00000000; +parameter mask_gem0__intr_en_pq7 = 32'h00000000; + +parameter gem0__intr_dis_pq1 = 32'hE000B620; +parameter val_gem0__intr_dis_pq1 = 32'h00000000; +parameter mask_gem0__intr_dis_pq1 = 32'h00000000; + +parameter gem0__intr_dis_pq2 = 32'hE000B624; +parameter val_gem0__intr_dis_pq2 = 32'h00000000; +parameter mask_gem0__intr_dis_pq2 = 32'h00000000; + +parameter gem0__intr_dis_pq3 = 32'hE000B628; +parameter val_gem0__intr_dis_pq3 = 32'h00000000; +parameter mask_gem0__intr_dis_pq3 = 32'h00000000; + +parameter gem0__intr_dis_pq4 = 32'hE000B62C; +parameter val_gem0__intr_dis_pq4 = 32'h00000000; +parameter mask_gem0__intr_dis_pq4 = 32'h00000000; + +parameter gem0__intr_dis_pq5 = 32'hE000B630; +parameter val_gem0__intr_dis_pq5 = 32'h00000000; +parameter mask_gem0__intr_dis_pq5 = 32'h00000000; + +parameter gem0__intr_dis_pq6 = 32'hE000B634; +parameter val_gem0__intr_dis_pq6 = 32'h00000000; +parameter mask_gem0__intr_dis_pq6 = 32'h00000000; + +parameter gem0__intr_dis_pq7 = 32'hE000B638; +parameter val_gem0__intr_dis_pq7 = 32'h00000000; +parameter mask_gem0__intr_dis_pq7 = 32'h00000000; + +parameter gem0__intr_mask_pq1 = 32'hE000B640; +parameter val_gem0__intr_mask_pq1 = 32'h00000000; +parameter mask_gem0__intr_mask_pq1 = 32'h00000000; + +parameter gem0__intr_mask_pq2 = 32'hE000B644; +parameter val_gem0__intr_mask_pq2 = 32'h00000000; +parameter mask_gem0__intr_mask_pq2 = 32'h00000000; + +parameter gem0__intr_mask_pq3 = 32'hE000B648; +parameter val_gem0__intr_mask_pq3 = 32'h00000000; +parameter mask_gem0__intr_mask_pq3 = 32'h00000000; + +parameter gem0__intr_mask_pq4 = 32'hE000B64C; +parameter val_gem0__intr_mask_pq4 = 32'h00000000; +parameter mask_gem0__intr_mask_pq4 = 32'h00000000; + +parameter gem0__intr_mask_pq5 = 32'hE000B650; +parameter val_gem0__intr_mask_pq5 = 32'h00000000; +parameter mask_gem0__intr_mask_pq5 = 32'h00000000; + +parameter gem0__intr_mask_pq6 = 32'hE000B654; +parameter val_gem0__intr_mask_pq6 = 32'h00000000; +parameter mask_gem0__intr_mask_pq6 = 32'h00000000; + +parameter gem0__intr_mask_pq7 = 32'hE000B658; +parameter val_gem0__intr_mask_pq7 = 32'h00000000; +parameter mask_gem0__intr_mask_pq7 = 32'h00000000; + + +// ************************************************************ +// Module gem1 GEM +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gem1__net_ctrl = 32'hE000C000; +parameter val_gem1__net_ctrl = 32'h00000000; +parameter mask_gem1__net_ctrl = 32'hFFFFFFFF; + +parameter gem1__net_cfg = 32'hE000C004; +parameter val_gem1__net_cfg = 32'h00080000; +parameter mask_gem1__net_cfg = 32'hFFFFFFFF; + +parameter gem1__net_status = 32'hE000C008; +parameter val_gem1__net_status = 32'h00000004; +parameter mask_gem1__net_status = 32'hFFFFFFFD; + +parameter gem1__user_io = 32'hE000C00C; +parameter val_gem1__user_io = 32'h00000000; +parameter mask_gem1__user_io = 32'h0000FFFF; + +parameter gem1__dma_cfg = 32'hE000C010; +parameter val_gem1__dma_cfg = 32'h00020784; +parameter mask_gem1__dma_cfg = 32'hFFFFFFFF; + +parameter gem1__tx_status = 32'hE000C014; +parameter val_gem1__tx_status = 32'h00000000; +parameter mask_gem1__tx_status = 32'hFFFFFFFF; + +parameter gem1__rx_qbar = 32'hE000C018; +parameter val_gem1__rx_qbar = 32'h00000000; +parameter mask_gem1__rx_qbar = 32'hFFFFFFFF; + +parameter gem1__tx_qbar = 32'hE000C01C; +parameter val_gem1__tx_qbar = 32'h00000000; +parameter mask_gem1__tx_qbar = 32'hFFFFFFFF; + +parameter gem1__rx_status = 32'hE000C020; +parameter val_gem1__rx_status = 32'h00000000; +parameter mask_gem1__rx_status = 32'hFFFFFFFF; + +parameter gem1__intr_status = 32'hE000C024; +parameter val_gem1__intr_status = 32'h00000000; +parameter mask_gem1__intr_status = 32'hFFFFFFFF; + +parameter gem1__intr_en = 32'hE000C028; +parameter val_gem1__intr_en = 32'h00000000; +parameter mask_gem1__intr_en = 32'h00000000; + +parameter gem1__intr_dis = 32'hE000C02C; +parameter val_gem1__intr_dis = 32'h00000000; +parameter mask_gem1__intr_dis = 32'h00000000; + +parameter gem1__intr_mask = 32'hE000C030; +parameter val_gem1__intr_mask = 32'h0001FFFF; +parameter mask_gem1__intr_mask = 32'hFC01FFFF; + +parameter gem1__phy_maint = 32'hE000C034; +parameter val_gem1__phy_maint = 32'h00000000; +parameter mask_gem1__phy_maint = 32'hFFFFFFFF; + +parameter gem1__rx_pauseq = 32'hE000C038; +parameter val_gem1__rx_pauseq = 32'h00000000; +parameter mask_gem1__rx_pauseq = 32'hFFFFFFFF; + +parameter gem1__tx_pauseq = 32'hE000C03C; +parameter val_gem1__tx_pauseq = 32'h0000FFFF; +parameter mask_gem1__tx_pauseq = 32'hFFFFFFFF; + +parameter gem1__tx_partial_st_fwd = 32'hE000C040; +parameter val_gem1__tx_partial_st_fwd = 32'h000003FF; +parameter mask_gem1__tx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem1__rx_partial_st_fwd = 32'hE000C044; +parameter val_gem1__rx_partial_st_fwd = 32'h000003FF; +parameter mask_gem1__rx_partial_st_fwd = 32'hFFFFFFFF; + +parameter gem1__hash_bot = 32'hE000C080; +parameter val_gem1__hash_bot = 32'h00000000; +parameter mask_gem1__hash_bot = 32'hFFFFFFFF; + +parameter gem1__hash_top = 32'hE000C084; +parameter val_gem1__hash_top = 32'h00000000; +parameter mask_gem1__hash_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_bot = 32'hE000C088; +parameter val_gem1__spec_addr1_bot = 32'h00000000; +parameter mask_gem1__spec_addr1_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_top = 32'hE000C08C; +parameter val_gem1__spec_addr1_top = 32'h00000000; +parameter mask_gem1__spec_addr1_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr2_bot = 32'hE000C090; +parameter val_gem1__spec_addr2_bot = 32'h00000000; +parameter mask_gem1__spec_addr2_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr2_top = 32'hE000C094; +parameter val_gem1__spec_addr2_top = 32'h00000000; +parameter mask_gem1__spec_addr2_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr3_bot = 32'hE000C098; +parameter val_gem1__spec_addr3_bot = 32'h00000000; +parameter mask_gem1__spec_addr3_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr3_top = 32'hE000C09C; +parameter val_gem1__spec_addr3_top = 32'h00000000; +parameter mask_gem1__spec_addr3_top = 32'hFFFFFFFF; + +parameter gem1__spec_addr4_bot = 32'hE000C0A0; +parameter val_gem1__spec_addr4_bot = 32'h00000000; +parameter mask_gem1__spec_addr4_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr4_top = 32'hE000C0A4; +parameter val_gem1__spec_addr4_top = 32'h00000000; +parameter mask_gem1__spec_addr4_top = 32'hFFFFFFFF; + +parameter gem1__type_id_match1 = 32'hE000C0A8; +parameter val_gem1__type_id_match1 = 32'h00000000; +parameter mask_gem1__type_id_match1 = 32'hFFFFFFFF; + +parameter gem1__type_id_match2 = 32'hE000C0AC; +parameter val_gem1__type_id_match2 = 32'h00000000; +parameter mask_gem1__type_id_match2 = 32'hFFFFFFFF; + +parameter gem1__type_id_match3 = 32'hE000C0B0; +parameter val_gem1__type_id_match3 = 32'h00000000; +parameter mask_gem1__type_id_match3 = 32'hFFFFFFFF; + +parameter gem1__type_id_match4 = 32'hE000C0B4; +parameter val_gem1__type_id_match4 = 32'h00000000; +parameter mask_gem1__type_id_match4 = 32'hFFFFFFFF; + +parameter gem1__wake_on_lan = 32'hE000C0B8; +parameter val_gem1__wake_on_lan = 32'h00000000; +parameter mask_gem1__wake_on_lan = 32'hFFFFFFFF; + +parameter gem1__ipg_stretch = 32'hE000C0BC; +parameter val_gem1__ipg_stretch = 32'h00000000; +parameter mask_gem1__ipg_stretch = 32'hFFFFFFFF; + +parameter gem1__stacked_vlan = 32'hE000C0C0; +parameter val_gem1__stacked_vlan = 32'h00000000; +parameter mask_gem1__stacked_vlan = 32'hFFFFFFFF; + +parameter gem1__tx_pfc_pause = 32'hE000C0C4; +parameter val_gem1__tx_pfc_pause = 32'h00000000; +parameter mask_gem1__tx_pfc_pause = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_mask_bot = 32'hE000C0C8; +parameter val_gem1__spec_addr1_mask_bot = 32'h00000000; +parameter mask_gem1__spec_addr1_mask_bot = 32'hFFFFFFFF; + +parameter gem1__spec_addr1_mask_top = 32'hE000C0CC; +parameter val_gem1__spec_addr1_mask_top = 32'h00000000; +parameter mask_gem1__spec_addr1_mask_top = 32'hFFFFFFFF; + +parameter gem1__module_id = 32'hE000C0FC; +parameter val_gem1__module_id = 32'h00020118; +parameter mask_gem1__module_id = 32'hFFFFFFFF; + +parameter gem1__octets_tx_bot = 32'hE000C100; +parameter val_gem1__octets_tx_bot = 32'h00000000; +parameter mask_gem1__octets_tx_bot = 32'hFFFFFFFF; + +parameter gem1__octets_tx_top = 32'hE000C104; +parameter val_gem1__octets_tx_top = 32'h00000000; +parameter mask_gem1__octets_tx_top = 32'hFFFFFFFF; + +parameter gem1__frames_tx = 32'hE000C108; +parameter val_gem1__frames_tx = 32'h00000000; +parameter mask_gem1__frames_tx = 32'hFFFFFFFF; + +parameter gem1__broadcast_frames_tx = 32'hE000C10C; +parameter val_gem1__broadcast_frames_tx = 32'h00000000; +parameter mask_gem1__broadcast_frames_tx = 32'hFFFFFFFF; + +parameter gem1__multi_frames_tx = 32'hE000C110; +parameter val_gem1__multi_frames_tx = 32'h00000000; +parameter mask_gem1__multi_frames_tx = 32'hFFFFFFFF; + +parameter gem1__pause_frames_tx = 32'hE000C114; +parameter val_gem1__pause_frames_tx = 32'h00000000; +parameter mask_gem1__pause_frames_tx = 32'hFFFFFFFF; + +parameter gem1__frames_64b_tx = 32'hE000C118; +parameter val_gem1__frames_64b_tx = 32'h00000000; +parameter mask_gem1__frames_64b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_65to127b_tx = 32'hE000C11C; +parameter val_gem1__frames_65to127b_tx = 32'h00000000; +parameter mask_gem1__frames_65to127b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_128to255b_tx = 32'hE000C120; +parameter val_gem1__frames_128to255b_tx = 32'h00000000; +parameter mask_gem1__frames_128to255b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_256to511b_tx = 32'hE000C124; +parameter val_gem1__frames_256to511b_tx = 32'h00000000; +parameter mask_gem1__frames_256to511b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_512to1023b_tx = 32'hE000C128; +parameter val_gem1__frames_512to1023b_tx = 32'h00000000; +parameter mask_gem1__frames_512to1023b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_1024to1518b_tx = 32'hE000C12C; +parameter val_gem1__frames_1024to1518b_tx = 32'h00000000; +parameter mask_gem1__frames_1024to1518b_tx = 32'hFFFFFFFF; + +parameter gem1__frames_gt1518b_tx = 32'hE000C130; +parameter val_gem1__frames_gt1518b_tx = 32'h00000000; +parameter mask_gem1__frames_gt1518b_tx = 32'hFFFFFFFF; + +parameter gem1__tx_under_runs = 32'hE000C134; +parameter val_gem1__tx_under_runs = 32'h00000000; +parameter mask_gem1__tx_under_runs = 32'hFFFFFFFF; + +parameter gem1__single_collisn_frames = 32'hE000C138; +parameter val_gem1__single_collisn_frames = 32'h00000000; +parameter mask_gem1__single_collisn_frames = 32'hFFFFFFFF; + +parameter gem1__multi_collisn_frames = 32'hE000C13C; +parameter val_gem1__multi_collisn_frames = 32'h00000000; +parameter mask_gem1__multi_collisn_frames = 32'hFFFFFFFF; + +parameter gem1__excessive_collisns = 32'hE000C140; +parameter val_gem1__excessive_collisns = 32'h00000000; +parameter mask_gem1__excessive_collisns = 32'hFFFFFFFF; + +parameter gem1__late_collisns = 32'hE000C144; +parameter val_gem1__late_collisns = 32'h00000000; +parameter mask_gem1__late_collisns = 32'hFFFFFFFF; + +parameter gem1__deferred_tx_frames = 32'hE000C148; +parameter val_gem1__deferred_tx_frames = 32'h00000000; +parameter mask_gem1__deferred_tx_frames = 32'hFFFFFFFF; + +parameter gem1__carrier_sense_errs = 32'hE000C14C; +parameter val_gem1__carrier_sense_errs = 32'h00000000; +parameter mask_gem1__carrier_sense_errs = 32'hFFFFFFFF; + +parameter gem1__octets_rx_bot = 32'hE000C150; +parameter val_gem1__octets_rx_bot = 32'h00000000; +parameter mask_gem1__octets_rx_bot = 32'hFFFFFFFF; + +parameter gem1__octets_rx_top = 32'hE000C154; +parameter val_gem1__octets_rx_top = 32'h00000000; +parameter mask_gem1__octets_rx_top = 32'hFFFFFFFF; + +parameter gem1__frames_rx = 32'hE000C158; +parameter val_gem1__frames_rx = 32'h00000000; +parameter mask_gem1__frames_rx = 32'hFFFFFFFF; + +parameter gem1__bdcast_fames_rx = 32'hE000C15C; +parameter val_gem1__bdcast_fames_rx = 32'h00000000; +parameter mask_gem1__bdcast_fames_rx = 32'hFFFFFFFF; + +parameter gem1__multi_frames_rx = 32'hE000C160; +parameter val_gem1__multi_frames_rx = 32'h00000000; +parameter mask_gem1__multi_frames_rx = 32'hFFFFFFFF; + +parameter gem1__pause_rx = 32'hE000C164; +parameter val_gem1__pause_rx = 32'h00000000; +parameter mask_gem1__pause_rx = 32'hFFFFFFFF; + +parameter gem1__frames_64b_rx = 32'hE000C168; +parameter val_gem1__frames_64b_rx = 32'h00000000; +parameter mask_gem1__frames_64b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_65to127b_rx = 32'hE000C16C; +parameter val_gem1__frames_65to127b_rx = 32'h00000000; +parameter mask_gem1__frames_65to127b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_128to255b_rx = 32'hE000C170; +parameter val_gem1__frames_128to255b_rx = 32'h00000000; +parameter mask_gem1__frames_128to255b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_256to511b_rx = 32'hE000C174; +parameter val_gem1__frames_256to511b_rx = 32'h00000000; +parameter mask_gem1__frames_256to511b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_512to1023b_rx = 32'hE000C178; +parameter val_gem1__frames_512to1023b_rx = 32'h00000000; +parameter mask_gem1__frames_512to1023b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_1024to1518b_rx = 32'hE000C17C; +parameter val_gem1__frames_1024to1518b_rx = 32'h00000000; +parameter mask_gem1__frames_1024to1518b_rx = 32'hFFFFFFFF; + +parameter gem1__frames_gt1518b_rx = 32'hE000C180; +parameter val_gem1__frames_gt1518b_rx = 32'h00000000; +parameter mask_gem1__frames_gt1518b_rx = 32'hFFFFFFFF; + +parameter gem1__undersz_rx = 32'hE000C184; +parameter val_gem1__undersz_rx = 32'h00000000; +parameter mask_gem1__undersz_rx = 32'hFFFFFFFF; + +parameter gem1__oversz_rx = 32'hE000C188; +parameter val_gem1__oversz_rx = 32'h00000000; +parameter mask_gem1__oversz_rx = 32'hFFFFFFFF; + +parameter gem1__jab_rx = 32'hE000C18C; +parameter val_gem1__jab_rx = 32'h00000000; +parameter mask_gem1__jab_rx = 32'hFFFFFFFF; + +parameter gem1__fcs_errors = 32'hE000C190; +parameter val_gem1__fcs_errors = 32'h00000000; +parameter mask_gem1__fcs_errors = 32'hFFFFFFFF; + +parameter gem1__length_field_errors = 32'hE000C194; +parameter val_gem1__length_field_errors = 32'h00000000; +parameter mask_gem1__length_field_errors = 32'hFFFFFFFF; + +parameter gem1__rx_symbol_errors = 32'hE000C198; +parameter val_gem1__rx_symbol_errors = 32'h00000000; +parameter mask_gem1__rx_symbol_errors = 32'hFFFFFFFF; + +parameter gem1__align_errors = 32'hE000C19C; +parameter val_gem1__align_errors = 32'h00000000; +parameter mask_gem1__align_errors = 32'hFFFFFFFF; + +parameter gem1__rx_resource_errors = 32'hE000C1A0; +parameter val_gem1__rx_resource_errors = 32'h00000000; +parameter mask_gem1__rx_resource_errors = 32'hFFFFFFFF; + +parameter gem1__rx_overrun_errors = 32'hE000C1A4; +parameter val_gem1__rx_overrun_errors = 32'h00000000; +parameter mask_gem1__rx_overrun_errors = 32'hFFFFFFFF; + +parameter gem1__ip_hdr_csum_errors = 32'hE000C1A8; +parameter val_gem1__ip_hdr_csum_errors = 32'h00000000; +parameter mask_gem1__ip_hdr_csum_errors = 32'hFFFFFFFF; + +parameter gem1__tcp_csum_errors = 32'hE000C1AC; +parameter val_gem1__tcp_csum_errors = 32'h00000000; +parameter mask_gem1__tcp_csum_errors = 32'hFFFFFFFF; + +parameter gem1__udp_csum_errors = 32'hE000C1B0; +parameter val_gem1__udp_csum_errors = 32'h00000000; +parameter mask_gem1__udp_csum_errors = 32'hFFFFFFFF; + +parameter gem1__timer_strobe_s = 32'hE000C1C8; +parameter val_gem1__timer_strobe_s = 32'h00000000; +parameter mask_gem1__timer_strobe_s = 32'hFFFFFFFF; + +parameter gem1__timer_strobe_ns = 32'hE000C1CC; +parameter val_gem1__timer_strobe_ns = 32'h00000000; +parameter mask_gem1__timer_strobe_ns = 32'hFFFFFFFF; + +parameter gem1__timer_s = 32'hE000C1D0; +parameter val_gem1__timer_s = 32'h00000000; +parameter mask_gem1__timer_s = 32'hFFFFFFFF; + +parameter gem1__timer_ns = 32'hE000C1D4; +parameter val_gem1__timer_ns = 32'h00000000; +parameter mask_gem1__timer_ns = 32'hFFFFFFFF; + +parameter gem1__timer_adjust = 32'hE000C1D8; +parameter val_gem1__timer_adjust = 32'h00000000; +parameter mask_gem1__timer_adjust = 32'hFFFFFFFF; + +parameter gem1__timer_incr = 32'hE000C1DC; +parameter val_gem1__timer_incr = 32'h00000000; +parameter mask_gem1__timer_incr = 32'hFFFFFFFF; + +parameter gem1__ptp_tx_s = 32'hE000C1E0; +parameter val_gem1__ptp_tx_s = 32'h00000000; +parameter mask_gem1__ptp_tx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_tx_ns = 32'hE000C1E4; +parameter val_gem1__ptp_tx_ns = 32'h00000000; +parameter mask_gem1__ptp_tx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_rx_s = 32'hE000C1E8; +parameter val_gem1__ptp_rx_s = 32'h00000000; +parameter mask_gem1__ptp_rx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_rx_ns = 32'hE000C1EC; +parameter val_gem1__ptp_rx_ns = 32'h00000000; +parameter mask_gem1__ptp_rx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_tx_s = 32'hE000C1F0; +parameter val_gem1__ptp_peer_tx_s = 32'h00000000; +parameter mask_gem1__ptp_peer_tx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_tx_ns = 32'hE000C1F4; +parameter val_gem1__ptp_peer_tx_ns = 32'h00000000; +parameter mask_gem1__ptp_peer_tx_ns = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_rx_s = 32'hE000C1F8; +parameter val_gem1__ptp_peer_rx_s = 32'h00000000; +parameter mask_gem1__ptp_peer_rx_s = 32'hFFFFFFFF; + +parameter gem1__ptp_peer_rx_ns = 32'hE000C1FC; +parameter val_gem1__ptp_peer_rx_ns = 32'h00000000; +parameter mask_gem1__ptp_peer_rx_ns = 32'hFFFFFFFF; + +parameter gem1__pcs_ctrl = 32'hE000C200; +parameter val_gem1__pcs_ctrl = 32'h00000000; +parameter mask_gem1__pcs_ctrl = 32'h00000000; + +parameter gem1__pcs_status = 32'hE000C204; +parameter val_gem1__pcs_status = 32'h00000000; +parameter mask_gem1__pcs_status = 32'h00000000; + +parameter gem1__pcs_upper_phy_id = 32'hE000C208; +parameter val_gem1__pcs_upper_phy_id = 32'h00000000; +parameter mask_gem1__pcs_upper_phy_id = 32'h00000000; + +parameter gem1__pcs_lower_phy_id = 32'hE000C20C; +parameter val_gem1__pcs_lower_phy_id = 32'h00000000; +parameter mask_gem1__pcs_lower_phy_id = 32'h00000000; + +parameter gem1__pcs_autoneg_ad = 32'hE000C210; +parameter val_gem1__pcs_autoneg_ad = 32'h00000000; +parameter mask_gem1__pcs_autoneg_ad = 32'h00000000; + +parameter gem1__pcs_autoneg_ability = 32'hE000C214; +parameter val_gem1__pcs_autoneg_ability = 32'h00000000; +parameter mask_gem1__pcs_autoneg_ability = 32'h00000000; + +parameter gem1__pcs_autonec_exp = 32'hE000C218; +parameter val_gem1__pcs_autonec_exp = 32'h00000000; +parameter mask_gem1__pcs_autonec_exp = 32'h00000000; + +parameter gem1__pcs_autoneg_next_pg = 32'hE000C21C; +parameter val_gem1__pcs_autoneg_next_pg = 32'h00000000; +parameter mask_gem1__pcs_autoneg_next_pg = 32'h00000000; + +parameter gem1__pcs_autoneg_pnext_pg = 32'hE000C220; +parameter val_gem1__pcs_autoneg_pnext_pg = 32'h00000000; +parameter mask_gem1__pcs_autoneg_pnext_pg = 32'h00000000; + +parameter gem1__pcs_extended_status = 32'hE000C23C; +parameter val_gem1__pcs_extended_status = 32'h00000000; +parameter mask_gem1__pcs_extended_status = 32'h00000000; + +parameter gem1__design_cfg1 = 32'hE000C280; +parameter val_gem1__design_cfg1 = 32'h02000000; +parameter mask_gem1__design_cfg1 = 32'h0E000000; + +parameter gem1__design_cfg2 = 32'hE000C284; +parameter val_gem1__design_cfg2 = 32'h2A813FFF; +parameter mask_gem1__design_cfg2 = 32'h3FCFFFFF; + +parameter gem1__design_cfg3 = 32'hE000C288; +parameter val_gem1__design_cfg3 = 32'h00000000; +parameter mask_gem1__design_cfg3 = 32'hFFFFFFFF; + +parameter gem1__design_cfg4 = 32'hE000C28C; +parameter val_gem1__design_cfg4 = 32'h00000000; +parameter mask_gem1__design_cfg4 = 32'hFFFFFFFF; + +parameter gem1__design_cfg5 = 32'hE000C290; +parameter val_gem1__design_cfg5 = 32'h002F2045; +parameter mask_gem1__design_cfg5 = 32'h0FFFFCFF; + +parameter gem1__design_cfg6 = 32'hE000C294; +parameter val_gem1__design_cfg6 = 32'h00000000; +parameter mask_gem1__design_cfg6 = 32'h00000000; + +parameter gem1__design_cfg7 = 32'hE000C298; +parameter val_gem1__design_cfg7 = 32'h00000000; +parameter mask_gem1__design_cfg7 = 32'h00000000; + +parameter gem1__isr_pq1 = 32'hE000C400; +parameter val_gem1__isr_pq1 = 32'h00000000; +parameter mask_gem1__isr_pq1 = 32'h00000000; + +parameter gem1__isr_pq2 = 32'hE000C404; +parameter val_gem1__isr_pq2 = 32'h00000000; +parameter mask_gem1__isr_pq2 = 32'h00000000; + +parameter gem1__isr_pq3 = 32'hE000C408; +parameter val_gem1__isr_pq3 = 32'h00000000; +parameter mask_gem1__isr_pq3 = 32'h00000000; + +parameter gem1__isr_pq4 = 32'hE000C40C; +parameter val_gem1__isr_pq4 = 32'h00000000; +parameter mask_gem1__isr_pq4 = 32'h00000000; + +parameter gem1__isr_pq5 = 32'hE000C410; +parameter val_gem1__isr_pq5 = 32'h00000000; +parameter mask_gem1__isr_pq5 = 32'h00000000; + +parameter gem1__isr_pq6 = 32'hE000C414; +parameter val_gem1__isr_pq6 = 32'h00000000; +parameter mask_gem1__isr_pq6 = 32'h00000000; + +parameter gem1__isr_pq7 = 32'hE000C418; +parameter val_gem1__isr_pq7 = 32'h00000000; +parameter mask_gem1__isr_pq7 = 32'h00000000; + +parameter gem1__tx_qbar_q1 = 32'hE000C440; +parameter val_gem1__tx_qbar_q1 = 32'h00000000; +parameter mask_gem1__tx_qbar_q1 = 32'h00000000; + +parameter gem1__tx_qbar_q2 = 32'hE000C444; +parameter val_gem1__tx_qbar_q2 = 32'h00000000; +parameter mask_gem1__tx_qbar_q2 = 32'h00000000; + +parameter gem1__tx_qbar_q3 = 32'hE000C448; +parameter val_gem1__tx_qbar_q3 = 32'h00000000; +parameter mask_gem1__tx_qbar_q3 = 32'h00000000; + +parameter gem1__tx_qbar_q4 = 32'hE000C44C; +parameter val_gem1__tx_qbar_q4 = 32'h00000000; +parameter mask_gem1__tx_qbar_q4 = 32'h00000000; + +parameter gem1__tx_qbar_q5 = 32'hE000C450; +parameter val_gem1__tx_qbar_q5 = 32'h00000000; +parameter mask_gem1__tx_qbar_q5 = 32'h00000000; + +parameter gem1__tx_qbar_q6 = 32'hE000C454; +parameter val_gem1__tx_qbar_q6 = 32'h00000000; +parameter mask_gem1__tx_qbar_q6 = 32'h00000000; + +parameter gem1__tx_qbar_q7 = 32'hE000C458; +parameter val_gem1__tx_qbar_q7 = 32'h00000000; +parameter mask_gem1__tx_qbar_q7 = 32'h00000000; + +parameter gem1__rx_qbar_q1 = 32'hE000C480; +parameter val_gem1__rx_qbar_q1 = 32'h00000000; +parameter mask_gem1__rx_qbar_q1 = 32'h00000000; + +parameter gem1__rx_qbar_q2 = 32'hE000C484; +parameter val_gem1__rx_qbar_q2 = 32'h00000000; +parameter mask_gem1__rx_qbar_q2 = 32'h00000000; + +parameter gem1__rx_qbar_q3 = 32'hE000C488; +parameter val_gem1__rx_qbar_q3 = 32'h00000000; +parameter mask_gem1__rx_qbar_q3 = 32'h00000000; + +parameter gem1__rx_qbar_q4 = 32'hE000C48C; +parameter val_gem1__rx_qbar_q4 = 32'h00000000; +parameter mask_gem1__rx_qbar_q4 = 32'h00000000; + +parameter gem1__rx_qbar_q5 = 32'hE000C490; +parameter val_gem1__rx_qbar_q5 = 32'h00000000; +parameter mask_gem1__rx_qbar_q5 = 32'h00000000; + +parameter gem1__rx_qbar_q6 = 32'hE000C494; +parameter val_gem1__rx_qbar_q6 = 32'h00000000; +parameter mask_gem1__rx_qbar_q6 = 32'h00000000; + +parameter gem1__rx_qbar_q7 = 32'hE000C498; +parameter val_gem1__rx_qbar_q7 = 32'h00000000; +parameter mask_gem1__rx_qbar_q7 = 32'h00000000; + +parameter gem1__rx_bufsz_q1 = 32'hE000C4A0; +parameter val_gem1__rx_bufsz_q1 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q1 = 32'h00000000; + +parameter gem1__rx_bufsz_q2 = 32'hE000C4A4; +parameter val_gem1__rx_bufsz_q2 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q2 = 32'h00000000; + +parameter gem1__rx_bufsz_q3 = 32'hE000C4A8; +parameter val_gem1__rx_bufsz_q3 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q3 = 32'h00000000; + +parameter gem1__rx_bufsz_q4 = 32'hE000C4AC; +parameter val_gem1__rx_bufsz_q4 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q4 = 32'h00000000; + +parameter gem1__rx_bufsz_q5 = 32'hE000C4B0; +parameter val_gem1__rx_bufsz_q5 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q5 = 32'h00000000; + +parameter gem1__rx_bufsz_q6 = 32'hE000C4B4; +parameter val_gem1__rx_bufsz_q6 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q6 = 32'h00000000; + +parameter gem1__rx_bufsz_q7 = 32'hE000C4B8; +parameter val_gem1__rx_bufsz_q7 = 32'h00000000; +parameter mask_gem1__rx_bufsz_q7 = 32'h00000000; + +parameter gem1__screen_t1_r0 = 32'hE000C500; +parameter val_gem1__screen_t1_r0 = 32'h00000000; +parameter mask_gem1__screen_t1_r0 = 32'h00000000; + +parameter gem1__screen_t1_r1 = 32'hE000C504; +parameter val_gem1__screen_t1_r1 = 32'h00000000; +parameter mask_gem1__screen_t1_r1 = 32'h00000000; + +parameter gem1__screen_t1_r2 = 32'hE000C508; +parameter val_gem1__screen_t1_r2 = 32'h00000000; +parameter mask_gem1__screen_t1_r2 = 32'h00000000; + +parameter gem1__screen_t1_r3 = 32'hE000C50C; +parameter val_gem1__screen_t1_r3 = 32'h00000000; +parameter mask_gem1__screen_t1_r3 = 32'h00000000; + +parameter gem1__screen_t1_r4 = 32'hE000C510; +parameter val_gem1__screen_t1_r4 = 32'h00000000; +parameter mask_gem1__screen_t1_r4 = 32'h00000000; + +parameter gem1__screen_t1_r5 = 32'hE000C514; +parameter val_gem1__screen_t1_r5 = 32'h00000000; +parameter mask_gem1__screen_t1_r5 = 32'h00000000; + +parameter gem1__screen_t1_r6 = 32'hE000C518; +parameter val_gem1__screen_t1_r6 = 32'h00000000; +parameter mask_gem1__screen_t1_r6 = 32'h00000000; + +parameter gem1__screen_t1_r7 = 32'hE000C51C; +parameter val_gem1__screen_t1_r7 = 32'h00000000; +parameter mask_gem1__screen_t1_r7 = 32'h00000000; + +parameter gem1__screen_t1_r8 = 32'hE000C520; +parameter val_gem1__screen_t1_r8 = 32'h00000000; +parameter mask_gem1__screen_t1_r8 = 32'h00000000; + +parameter gem1__screen_t1_r9 = 32'hE000C524; +parameter val_gem1__screen_t1_r9 = 32'h00000000; +parameter mask_gem1__screen_t1_r9 = 32'h00000000; + +parameter gem1__screen_t1_r10 = 32'hE000C528; +parameter val_gem1__screen_t1_r10 = 32'h00000000; +parameter mask_gem1__screen_t1_r10 = 32'h00000000; + +parameter gem1__screen_t1_r11 = 32'hE000C52C; +parameter val_gem1__screen_t1_r11 = 32'h00000000; +parameter mask_gem1__screen_t1_r11 = 32'h00000000; + +parameter gem1__screen_t1_r12 = 32'hE000C530; +parameter val_gem1__screen_t1_r12 = 32'h00000000; +parameter mask_gem1__screen_t1_r12 = 32'h00000000; + +parameter gem1__screen_t1_r13 = 32'hE000C534; +parameter val_gem1__screen_t1_r13 = 32'h00000000; +parameter mask_gem1__screen_t1_r13 = 32'h00000000; + +parameter gem1__screen_t1_r14 = 32'hE000C538; +parameter val_gem1__screen_t1_r14 = 32'h00000000; +parameter mask_gem1__screen_t1_r14 = 32'h00000000; + +parameter gem1__screen_t1_r15 = 32'hE000C53C; +parameter val_gem1__screen_t1_r15 = 32'h00000000; +parameter mask_gem1__screen_t1_r15 = 32'h00000000; + +parameter gem1__screen_t2_r0 = 32'hE000C540; +parameter val_gem1__screen_t2_r0 = 32'h00000000; +parameter mask_gem1__screen_t2_r0 = 32'h00000000; + +parameter gem1__screen_t2_r1 = 32'hE000C544; +parameter val_gem1__screen_t2_r1 = 32'h00000000; +parameter mask_gem1__screen_t2_r1 = 32'h00000000; + +parameter gem1__screen_t2_r2 = 32'hE000C548; +parameter val_gem1__screen_t2_r2 = 32'h00000000; +parameter mask_gem1__screen_t2_r2 = 32'h00000000; + +parameter gem1__screen_t2_r3 = 32'hE000C54C; +parameter val_gem1__screen_t2_r3 = 32'h00000000; +parameter mask_gem1__screen_t2_r3 = 32'h00000000; + +parameter gem1__screen_t2_r4 = 32'hE000C550; +parameter val_gem1__screen_t2_r4 = 32'h00000000; +parameter mask_gem1__screen_t2_r4 = 32'h00000000; + +parameter gem1__screen_t2_r5 = 32'hE000C554; +parameter val_gem1__screen_t2_r5 = 32'h00000000; +parameter mask_gem1__screen_t2_r5 = 32'h00000000; + +parameter gem1__screen_t2_r6 = 32'hE000C558; +parameter val_gem1__screen_t2_r6 = 32'h00000000; +parameter mask_gem1__screen_t2_r6 = 32'h00000000; + +parameter gem1__screen_t2_r7 = 32'hE000C55C; +parameter val_gem1__screen_t2_r7 = 32'h00000000; +parameter mask_gem1__screen_t2_r7 = 32'h00000000; + +parameter gem1__screen_t2_r8 = 32'hE000C560; +parameter val_gem1__screen_t2_r8 = 32'h00000000; +parameter mask_gem1__screen_t2_r8 = 32'h00000000; + +parameter gem1__screen_t2_r9 = 32'hE000C564; +parameter val_gem1__screen_t2_r9 = 32'h00000000; +parameter mask_gem1__screen_t2_r9 = 32'h00000000; + +parameter gem1__screen_t2_r10 = 32'hE000C568; +parameter val_gem1__screen_t2_r10 = 32'h00000000; +parameter mask_gem1__screen_t2_r10 = 32'h00000000; + +parameter gem1__screen_t2_r11 = 32'hE000C56C; +parameter val_gem1__screen_t2_r11 = 32'h00000000; +parameter mask_gem1__screen_t2_r11 = 32'h00000000; + +parameter gem1__screen_t2_r12 = 32'hE000C570; +parameter val_gem1__screen_t2_r12 = 32'h00000000; +parameter mask_gem1__screen_t2_r12 = 32'h00000000; + +parameter gem1__screen_t2_r13 = 32'hE000C574; +parameter val_gem1__screen_t2_r13 = 32'h00000000; +parameter mask_gem1__screen_t2_r13 = 32'h00000000; + +parameter gem1__screen_t2_r14 = 32'hE000C578; +parameter val_gem1__screen_t2_r14 = 32'h00000000; +parameter mask_gem1__screen_t2_r14 = 32'h00000000; + +parameter gem1__screen_t2_r15 = 32'hE000C57C; +parameter val_gem1__screen_t2_r15 = 32'h00000000; +parameter mask_gem1__screen_t2_r15 = 32'h00000000; + +parameter gem1__intr_en_pq1 = 32'hE000C600; +parameter val_gem1__intr_en_pq1 = 32'h00000000; +parameter mask_gem1__intr_en_pq1 = 32'h00000000; + +parameter gem1__intr_en_pq2 = 32'hE000C604; +parameter val_gem1__intr_en_pq2 = 32'h00000000; +parameter mask_gem1__intr_en_pq2 = 32'h00000000; + +parameter gem1__intr_en_pq3 = 32'hE000C608; +parameter val_gem1__intr_en_pq3 = 32'h00000000; +parameter mask_gem1__intr_en_pq3 = 32'h00000000; + +parameter gem1__intr_en_pq4 = 32'hE000C60C; +parameter val_gem1__intr_en_pq4 = 32'h00000000; +parameter mask_gem1__intr_en_pq4 = 32'h00000000; + +parameter gem1__intr_en_pq5 = 32'hE000C610; +parameter val_gem1__intr_en_pq5 = 32'h00000000; +parameter mask_gem1__intr_en_pq5 = 32'h00000000; + +parameter gem1__intr_en_pq6 = 32'hE000C614; +parameter val_gem1__intr_en_pq6 = 32'h00000000; +parameter mask_gem1__intr_en_pq6 = 32'h00000000; + +parameter gem1__intr_en_pq7 = 32'hE000C618; +parameter val_gem1__intr_en_pq7 = 32'h00000000; +parameter mask_gem1__intr_en_pq7 = 32'h00000000; + +parameter gem1__intr_dis_pq1 = 32'hE000C620; +parameter val_gem1__intr_dis_pq1 = 32'h00000000; +parameter mask_gem1__intr_dis_pq1 = 32'h00000000; + +parameter gem1__intr_dis_pq2 = 32'hE000C624; +parameter val_gem1__intr_dis_pq2 = 32'h00000000; +parameter mask_gem1__intr_dis_pq2 = 32'h00000000; + +parameter gem1__intr_dis_pq3 = 32'hE000C628; +parameter val_gem1__intr_dis_pq3 = 32'h00000000; +parameter mask_gem1__intr_dis_pq3 = 32'h00000000; + +parameter gem1__intr_dis_pq4 = 32'hE000C62C; +parameter val_gem1__intr_dis_pq4 = 32'h00000000; +parameter mask_gem1__intr_dis_pq4 = 32'h00000000; + +parameter gem1__intr_dis_pq5 = 32'hE000C630; +parameter val_gem1__intr_dis_pq5 = 32'h00000000; +parameter mask_gem1__intr_dis_pq5 = 32'h00000000; + +parameter gem1__intr_dis_pq6 = 32'hE000C634; +parameter val_gem1__intr_dis_pq6 = 32'h00000000; +parameter mask_gem1__intr_dis_pq6 = 32'h00000000; + +parameter gem1__intr_dis_pq7 = 32'hE000C638; +parameter val_gem1__intr_dis_pq7 = 32'h00000000; +parameter mask_gem1__intr_dis_pq7 = 32'h00000000; + +parameter gem1__intr_mask_pq1 = 32'hE000C640; +parameter val_gem1__intr_mask_pq1 = 32'h00000000; +parameter mask_gem1__intr_mask_pq1 = 32'h00000000; + +parameter gem1__intr_mask_pq2 = 32'hE000C644; +parameter val_gem1__intr_mask_pq2 = 32'h00000000; +parameter mask_gem1__intr_mask_pq2 = 32'h00000000; + +parameter gem1__intr_mask_pq3 = 32'hE000C648; +parameter val_gem1__intr_mask_pq3 = 32'h00000000; +parameter mask_gem1__intr_mask_pq3 = 32'h00000000; + +parameter gem1__intr_mask_pq4 = 32'hE000C64C; +parameter val_gem1__intr_mask_pq4 = 32'h00000000; +parameter mask_gem1__intr_mask_pq4 = 32'h00000000; + +parameter gem1__intr_mask_pq5 = 32'hE000C650; +parameter val_gem1__intr_mask_pq5 = 32'h00000000; +parameter mask_gem1__intr_mask_pq5 = 32'h00000000; + +parameter gem1__intr_mask_pq6 = 32'hE000C654; +parameter val_gem1__intr_mask_pq6 = 32'h00000000; +parameter mask_gem1__intr_mask_pq6 = 32'h00000000; + +parameter gem1__intr_mask_pq7 = 32'hE000C658; +parameter val_gem1__intr_mask_pq7 = 32'h00000000; +parameter mask_gem1__intr_mask_pq7 = 32'h00000000; + + +// ************************************************************ +// Module gpio gpio +// doc version: +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpio__MASK_DATA_0_LSW = 32'hE000A000; +parameter val_gpio__MASK_DATA_0_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_0_LSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_0_MSW = 32'hE000A004; +parameter val_gpio__MASK_DATA_0_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_0_MSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_1_LSW = 32'hE000A008; +parameter val_gpio__MASK_DATA_1_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_1_LSW = 32'hFFFF0000; + +parameter gpio__MASK_DATA_1_MSW = 32'hE000A00C; +parameter val_gpio__MASK_DATA_1_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_1_MSW = 32'h003FFFC0; + +parameter gpio__MASK_DATA_2_LSW = 32'hE000A010; +parameter val_gpio__MASK_DATA_2_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_2_LSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_2_MSW = 32'hE000A014; +parameter val_gpio__MASK_DATA_2_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_2_MSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_3_LSW = 32'hE000A018; +parameter val_gpio__MASK_DATA_3_LSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_3_LSW = 32'hFFFFFFFF; + +parameter gpio__MASK_DATA_3_MSW = 32'hE000A01C; +parameter val_gpio__MASK_DATA_3_MSW = 32'h00000000; +parameter mask_gpio__MASK_DATA_3_MSW = 32'hFFFFFFFF; + +parameter gpio__DATA_0 = 32'hE000A040; +parameter val_gpio__DATA_0 = 32'h00000000; +parameter mask_gpio__DATA_0 = 32'h00000000; + +parameter gpio__DATA_1 = 32'hE000A044; +parameter val_gpio__DATA_1 = 32'h00000000; +parameter mask_gpio__DATA_1 = 32'h00000000; + +parameter gpio__DATA_2 = 32'hE000A048; +parameter val_gpio__DATA_2 = 32'h00000000; +parameter mask_gpio__DATA_2 = 32'hFFFFFFFF; + +parameter gpio__DATA_3 = 32'hE000A04C; +parameter val_gpio__DATA_3 = 32'h00000000; +parameter mask_gpio__DATA_3 = 32'hFFFFFFFF; + +parameter gpio__DATA_0_RO = 32'hE000A060; +parameter val_gpio__DATA_0_RO = 32'h00000000; +parameter mask_gpio__DATA_0_RO = 32'h00000000; + +parameter gpio__DATA_1_RO = 32'hE000A064; +parameter val_gpio__DATA_1_RO = 32'h00000000; +parameter mask_gpio__DATA_1_RO = 32'h00000000; + +parameter gpio__DATA_2_RO = 32'hE000A068; +parameter val_gpio__DATA_2_RO = 32'h00000000; +parameter mask_gpio__DATA_2_RO = 32'hFFFFFFFF; + +parameter gpio__DATA_3_RO = 32'hE000A06C; +parameter val_gpio__DATA_3_RO = 32'h00000000; +parameter mask_gpio__DATA_3_RO = 32'hFFFFFFFF; + +parameter gpio__BYPM_0 = 32'hE000A200; +parameter val_gpio__BYPM_0 = 32'h00000000; +parameter mask_gpio__BYPM_0 = 32'hFFFFFFFF; + +parameter gpio__DIRM_0 = 32'hE000A204; +parameter val_gpio__DIRM_0 = 32'h00000000; +parameter mask_gpio__DIRM_0 = 32'hFFFFFFFF; + +parameter gpio__OEN_0 = 32'hE000A208; +parameter val_gpio__OEN_0 = 32'h00000000; +parameter mask_gpio__OEN_0 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_0 = 32'hE000A20C; +parameter val_gpio__INT_MASK_0 = 32'h00000000; +parameter mask_gpio__INT_MASK_0 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_0 = 32'hE000A210; +parameter val_gpio__INT_EN_0 = 32'h00000000; +parameter mask_gpio__INT_EN_0 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_0 = 32'hE000A214; +parameter val_gpio__INT_DIS_0 = 32'h00000000; +parameter mask_gpio__INT_DIS_0 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_0 = 32'hE000A218; +parameter val_gpio__INT_STAT_0 = 32'h00000000; +parameter mask_gpio__INT_STAT_0 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_0 = 32'hE000A21C; +parameter val_gpio__INT_TYPE_0 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_0 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_0 = 32'hE000A220; +parameter val_gpio__INT_POLARITY_0 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_0 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_0 = 32'hE000A224; +parameter val_gpio__INT_ANY_0 = 32'h00000000; +parameter mask_gpio__INT_ANY_0 = 32'hFFFFFFFF; + +parameter gpio__BYPM_1 = 32'hE000A240; +parameter val_gpio__BYPM_1 = 32'h00000000; +parameter mask_gpio__BYPM_1 = 32'h003FFFFF; + +parameter gpio__DIRM_1 = 32'hE000A244; +parameter val_gpio__DIRM_1 = 32'h00000000; +parameter mask_gpio__DIRM_1 = 32'h003FFFFF; + +parameter gpio__OEN_1 = 32'hE000A248; +parameter val_gpio__OEN_1 = 32'h00000000; +parameter mask_gpio__OEN_1 = 32'h003FFFFF; + +parameter gpio__INT_MASK_1 = 32'hE000A24C; +parameter val_gpio__INT_MASK_1 = 32'h00000000; +parameter mask_gpio__INT_MASK_1 = 32'h003FFFFF; + +parameter gpio__INT_EN_1 = 32'hE000A250; +parameter val_gpio__INT_EN_1 = 32'h00000000; +parameter mask_gpio__INT_EN_1 = 32'h003FFFFF; + +parameter gpio__INT_DIS_1 = 32'hE000A254; +parameter val_gpio__INT_DIS_1 = 32'h00000000; +parameter mask_gpio__INT_DIS_1 = 32'h003FFFFF; + +parameter gpio__INT_STAT_1 = 32'hE000A258; +parameter val_gpio__INT_STAT_1 = 32'h00000000; +parameter mask_gpio__INT_STAT_1 = 32'h003FFFFF; + +parameter gpio__INT_TYPE_1 = 32'hE000A25C; +parameter val_gpio__INT_TYPE_1 = 32'h003FFFFF; +parameter mask_gpio__INT_TYPE_1 = 32'h003FFFFF; + +parameter gpio__INT_POLARITY_1 = 32'hE000A260; +parameter val_gpio__INT_POLARITY_1 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_1 = 32'h003FFFFF; + +parameter gpio__INT_ANY_1 = 32'hE000A264; +parameter val_gpio__INT_ANY_1 = 32'h00000000; +parameter mask_gpio__INT_ANY_1 = 32'h003FFFFF; + +parameter gpio__BYPM_2 = 32'hE000A280; +parameter val_gpio__BYPM_2 = 32'h00000000; +parameter mask_gpio__BYPM_2 = 32'hFFFFFFFF; + +parameter gpio__DIRM_2 = 32'hE000A284; +parameter val_gpio__DIRM_2 = 32'h00000000; +parameter mask_gpio__DIRM_2 = 32'hFFFFFFFF; + +parameter gpio__OEN_2 = 32'hE000A288; +parameter val_gpio__OEN_2 = 32'h00000000; +parameter mask_gpio__OEN_2 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_2 = 32'hE000A28C; +parameter val_gpio__INT_MASK_2 = 32'h00000000; +parameter mask_gpio__INT_MASK_2 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_2 = 32'hE000A290; +parameter val_gpio__INT_EN_2 = 32'h00000000; +parameter mask_gpio__INT_EN_2 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_2 = 32'hE000A294; +parameter val_gpio__INT_DIS_2 = 32'h00000000; +parameter mask_gpio__INT_DIS_2 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_2 = 32'hE000A298; +parameter val_gpio__INT_STAT_2 = 32'h00000000; +parameter mask_gpio__INT_STAT_2 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_2 = 32'hE000A29C; +parameter val_gpio__INT_TYPE_2 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_2 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_2 = 32'hE000A2A0; +parameter val_gpio__INT_POLARITY_2 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_2 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_2 = 32'hE000A2A4; +parameter val_gpio__INT_ANY_2 = 32'h00000000; +parameter mask_gpio__INT_ANY_2 = 32'hFFFFFFFF; + +parameter gpio__BYPM_3 = 32'hE000A2C0; +parameter val_gpio__BYPM_3 = 32'h00000000; +parameter mask_gpio__BYPM_3 = 32'hFFFFFFFF; + +parameter gpio__DIRM_3 = 32'hE000A2C4; +parameter val_gpio__DIRM_3 = 32'h00000000; +parameter mask_gpio__DIRM_3 = 32'hFFFFFFFF; + +parameter gpio__OEN_3 = 32'hE000A2C8; +parameter val_gpio__OEN_3 = 32'h00000000; +parameter mask_gpio__OEN_3 = 32'hFFFFFFFF; + +parameter gpio__INT_MASK_3 = 32'hE000A2CC; +parameter val_gpio__INT_MASK_3 = 32'h00000000; +parameter mask_gpio__INT_MASK_3 = 32'hFFFFFFFF; + +parameter gpio__INT_EN_3 = 32'hE000A2D0; +parameter val_gpio__INT_EN_3 = 32'h00000000; +parameter mask_gpio__INT_EN_3 = 32'hFFFFFFFF; + +parameter gpio__INT_DIS_3 = 32'hE000A2D4; +parameter val_gpio__INT_DIS_3 = 32'h00000000; +parameter mask_gpio__INT_DIS_3 = 32'hFFFFFFFF; + +parameter gpio__INT_STAT_3 = 32'hE000A2D8; +parameter val_gpio__INT_STAT_3 = 32'h00000000; +parameter mask_gpio__INT_STAT_3 = 32'hFFFFFFFF; + +parameter gpio__INT_TYPE_3 = 32'hE000A2DC; +parameter val_gpio__INT_TYPE_3 = 32'hFFFFFFFF; +parameter mask_gpio__INT_TYPE_3 = 32'hFFFFFFFF; + +parameter gpio__INT_POLARITY_3 = 32'hE000A2E0; +parameter val_gpio__INT_POLARITY_3 = 32'h00000000; +parameter mask_gpio__INT_POLARITY_3 = 32'hFFFFFFFF; + +parameter gpio__INT_ANY_3 = 32'hE000A2E4; +parameter val_gpio__INT_ANY_3 = 32'h00000000; +parameter mask_gpio__INT_ANY_3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module gpv_iou_switch gpv_iou_switch +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_iou_switch__Remap = 32'hE0200000; +parameter val_gpv_iou_switch__Remap = 32'h00000000; +parameter mask_gpv_iou_switch__Remap = 32'h000000FF; + +parameter gpv_iou_switch__security2_sdio0 = 32'hE0200008; +parameter val_gpv_iou_switch__security2_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__security2_sdio0 = 32'h00000001; + +parameter gpv_iou_switch__security3_sdio1 = 32'hE020000C; +parameter val_gpv_iou_switch__security3_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__security3_sdio1 = 32'h00000001; + +parameter gpv_iou_switch__security4_qspi = 32'hE0200010; +parameter val_gpv_iou_switch__security4_qspi = 32'h00000000; +parameter mask_gpv_iou_switch__security4_qspi = 32'h00000001; + +parameter gpv_iou_switch__security5_miou = 32'hE0200014; +parameter val_gpv_iou_switch__security5_miou = 32'h00000000; +parameter mask_gpv_iou_switch__security5_miou = 32'h00000001; + +parameter gpv_iou_switch__security6_apb_slaves = 32'hE0200018; +parameter val_gpv_iou_switch__security6_apb_slaves = 32'h00000000; +parameter mask_gpv_iou_switch__security6_apb_slaves = 32'h00007FFF; + +parameter gpv_iou_switch__security7_smc = 32'hE020001C; +parameter val_gpv_iou_switch__security7_smc = 32'h00000000; +parameter mask_gpv_iou_switch__security7_smc = 32'h00000001; + +parameter gpv_iou_switch__peripheral_id4 = 32'hE0201FD0; +parameter val_gpv_iou_switch__peripheral_id4 = 32'h00000004; +parameter mask_gpv_iou_switch__peripheral_id4 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id5 = 32'hE0201FD4; +parameter val_gpv_iou_switch__peripheral_id5 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id5 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id6 = 32'hE0201FD8; +parameter val_gpv_iou_switch__peripheral_id6 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id6 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id7 = 32'hE0201FDC; +parameter val_gpv_iou_switch__peripheral_id7 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id7 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id0 = 32'hE0201FE0; +parameter val_gpv_iou_switch__peripheral_id0 = 32'h00000001; +parameter mask_gpv_iou_switch__peripheral_id0 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id1 = 32'hE0201FE4; +parameter val_gpv_iou_switch__peripheral_id1 = 32'h000000B3; +parameter mask_gpv_iou_switch__peripheral_id1 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id2 = 32'hE0201FE8; +parameter val_gpv_iou_switch__peripheral_id2 = 32'h0000005B; +parameter mask_gpv_iou_switch__peripheral_id2 = 32'h000000FF; + +parameter gpv_iou_switch__peripheral_id3 = 32'hE0201FEC; +parameter val_gpv_iou_switch__peripheral_id3 = 32'h00000000; +parameter mask_gpv_iou_switch__peripheral_id3 = 32'h000000FF; + +parameter gpv_iou_switch__component_id0 = 32'hE0201FF0; +parameter val_gpv_iou_switch__component_id0 = 32'h0000000D; +parameter mask_gpv_iou_switch__component_id0 = 32'h000000FF; + +parameter gpv_iou_switch__component_id1 = 32'hE0201FF4; +parameter val_gpv_iou_switch__component_id1 = 32'h000000F0; +parameter mask_gpv_iou_switch__component_id1 = 32'h000000FF; + +parameter gpv_iou_switch__component_id2 = 32'hE0201FF8; +parameter val_gpv_iou_switch__component_id2 = 32'h00000005; +parameter mask_gpv_iou_switch__component_id2 = 32'h000000FF; + +parameter gpv_iou_switch__component_id3 = 32'hE0201FFC; +parameter val_gpv_iou_switch__component_id3 = 32'h000000B1; +parameter mask_gpv_iou_switch__component_id3 = 32'h000000FF; + +parameter gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'hE0202008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio0 = 32'h00000003; + +parameter gpv_iou_switch__ahb_cntl_sdio0 = 32'hE0202044; +parameter val_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__ahb_cntl_sdio0 = 32'h00000000; + +parameter gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'hE0203008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_sdio1 = 32'h00000003; + +parameter gpv_iou_switch__ahb_cntl_sdio1 = 32'hE0203044; +parameter val_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__ahb_cntl_sdio1 = 32'h00000000; + +parameter gpv_iou_switch__fn_mod_bm_iss_qspi = 32'hE0204008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_qspi = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_bm_iss_miou = 32'hE0205008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_miou = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_bm_iss_smc = 32'hE0207008; +parameter val_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_bm_iss_smc = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_gem0 = 32'hE0242028; +parameter val_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_gem0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_gem0 = 32'hE0242100; +parameter val_gpv_iou_switch__read_qos_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_gem0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_gem0 = 32'hE0242104; +parameter val_gpv_iou_switch__write_qos_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_gem0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_gem0 = 32'hE0242108; +parameter val_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_gem0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_gem1 = 32'hE0243028; +parameter val_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_gem1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_gem1 = 32'hE0243100; +parameter val_gpv_iou_switch__read_qos_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_gem1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_gem1 = 32'hE0243104; +parameter val_gpv_iou_switch__write_qos_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_gem1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_gem1 = 32'hE0243108; +parameter val_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_gem1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_usb0 = 32'hE0244028; +parameter val_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_usb0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_usb0 = 32'hE0244100; +parameter val_gpv_iou_switch__read_qos_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_usb0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_usb0 = 32'hE0244104; +parameter val_gpv_iou_switch__write_qos_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_usb0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_usb0 = 32'hE0244108; +parameter val_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_usb0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_usb1 = 32'hE0245028; +parameter val_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_usb1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_usb1 = 32'hE0245100; +parameter val_gpv_iou_switch__read_qos_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_usb1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_usb1 = 32'hE0245104; +parameter val_gpv_iou_switch__write_qos_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_usb1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_usb1 = 32'hE0245108; +parameter val_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_usb1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_sdio0 = 32'hE0246028; +parameter val_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_sdio0 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_sdio0 = 32'hE0246100; +parameter val_gpv_iou_switch__read_qos_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_sdio0 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_sdio0 = 32'hE0246104; +parameter val_gpv_iou_switch__write_qos_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_sdio0 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_sdio0 = 32'hE0246108; +parameter val_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_sdio0 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_ahb_sdio1 = 32'hE0247028; +parameter val_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_ahb_sdio1 = 32'h00000007; + +parameter gpv_iou_switch__read_qos_sdio1 = 32'hE0247100; +parameter val_gpv_iou_switch__read_qos_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__read_qos_sdio1 = 32'h0000000F; + +parameter gpv_iou_switch__write_qos_sdio1 = 32'hE0247104; +parameter val_gpv_iou_switch__write_qos_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__write_qos_sdio1 = 32'h0000000F; + +parameter gpv_iou_switch__fn_mod_iss_sdio1 = 32'hE0247108; +parameter val_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_sdio1 = 32'h00000003; + +parameter gpv_iou_switch__fn_mod_iss_siou = 32'hE0249108; +parameter val_gpv_iou_switch__fn_mod_iss_siou = 32'h00000000; +parameter mask_gpv_iou_switch__fn_mod_iss_siou = 32'h00000003; + + +// ************************************************************ +// Module gpv_qos301_cpu qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_cpu__qos_cntl = 32'hF894610C; +parameter val_gpv_qos301_cpu__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_cpu__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_cpu__max_ot = 32'hF8946110; +parameter val_gpv_qos301_cpu__max_ot = 32'h00000000; +parameter mask_gpv_qos301_cpu__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_cpu__max_comb_ot = 32'hF8946114; +parameter val_gpv_qos301_cpu__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_cpu__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_cpu__aw_p = 32'hF8946118; +parameter val_gpv_qos301_cpu__aw_p = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_p = 32'hFF000000; + +parameter gpv_qos301_cpu__aw_b = 32'hF894611C; +parameter val_gpv_qos301_cpu__aw_b = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_cpu__aw_r = 32'hF8946120; +parameter val_gpv_qos301_cpu__aw_r = 32'h00000000; +parameter mask_gpv_qos301_cpu__aw_r = 32'hFFF00000; + +parameter gpv_qos301_cpu__ar_p = 32'hF8946124; +parameter val_gpv_qos301_cpu__ar_p = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_p = 32'hFF000000; + +parameter gpv_qos301_cpu__ar_b = 32'hF8946128; +parameter val_gpv_qos301_cpu__ar_b = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_cpu__ar_r = 32'hF894612C; +parameter val_gpv_qos301_cpu__ar_r = 32'h00000000; +parameter mask_gpv_qos301_cpu__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_qos301_dmac qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_dmac__qos_cntl = 32'hF894710C; +parameter val_gpv_qos301_dmac__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_dmac__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_dmac__max_ot = 32'hF8947110; +parameter val_gpv_qos301_dmac__max_ot = 32'h00000000; +parameter mask_gpv_qos301_dmac__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_dmac__max_comb_ot = 32'hF8947114; +parameter val_gpv_qos301_dmac__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_dmac__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_dmac__aw_p = 32'hF8947118; +parameter val_gpv_qos301_dmac__aw_p = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_p = 32'hFF000000; + +parameter gpv_qos301_dmac__aw_b = 32'hF894711C; +parameter val_gpv_qos301_dmac__aw_b = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_dmac__aw_r = 32'hF8947120; +parameter val_gpv_qos301_dmac__aw_r = 32'h00000000; +parameter mask_gpv_qos301_dmac__aw_r = 32'hFFF00000; + +parameter gpv_qos301_dmac__ar_p = 32'hF8947124; +parameter val_gpv_qos301_dmac__ar_p = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_p = 32'hFF000000; + +parameter gpv_qos301_dmac__ar_b = 32'hF8947128; +parameter val_gpv_qos301_dmac__ar_b = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_dmac__ar_r = 32'hF894712C; +parameter val_gpv_qos301_dmac__ar_r = 32'h00000000; +parameter mask_gpv_qos301_dmac__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_qos301_iou qos301 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_qos301_iou__qos_cntl = 32'hF894810C; +parameter val_gpv_qos301_iou__qos_cntl = 32'h00000000; +parameter mask_gpv_qos301_iou__qos_cntl = 32'h000000FF; + +parameter gpv_qos301_iou__max_ot = 32'hF8948110; +parameter val_gpv_qos301_iou__max_ot = 32'h00000000; +parameter mask_gpv_qos301_iou__max_ot = 32'h3FFF3FFF; + +parameter gpv_qos301_iou__max_comb_ot = 32'hF8948114; +parameter val_gpv_qos301_iou__max_comb_ot = 32'h00000000; +parameter mask_gpv_qos301_iou__max_comb_ot = 32'h00007FFF; + +parameter gpv_qos301_iou__aw_p = 32'hF8948118; +parameter val_gpv_qos301_iou__aw_p = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_p = 32'hFF000000; + +parameter gpv_qos301_iou__aw_b = 32'hF894811C; +parameter val_gpv_qos301_iou__aw_b = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_b = 32'h0000FFFF; + +parameter gpv_qos301_iou__aw_r = 32'hF8948120; +parameter val_gpv_qos301_iou__aw_r = 32'h00000000; +parameter mask_gpv_qos301_iou__aw_r = 32'hFFF00000; + +parameter gpv_qos301_iou__ar_p = 32'hF8948124; +parameter val_gpv_qos301_iou__ar_p = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_p = 32'hFF000000; + +parameter gpv_qos301_iou__ar_b = 32'hF8948128; +parameter val_gpv_qos301_iou__ar_b = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_b = 32'h0000FFFF; + +parameter gpv_qos301_iou__ar_r = 32'hF894812C; +parameter val_gpv_qos301_iou__ar_r = 32'h00000000; +parameter mask_gpv_qos301_iou__ar_r = 32'hFFF00000; + + +// ************************************************************ +// Module gpv_trustzone nic301_addr_region_ctrl_registers +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter gpv_trustzone__Remap = 32'hF8900000; +parameter val_gpv_trustzone__Remap = 32'h00000000; +parameter mask_gpv_trustzone__Remap = 32'h000000C0; + +parameter gpv_trustzone__security_fssw_s0 = 32'hF890001C; +parameter val_gpv_trustzone__security_fssw_s0 = 32'h00000000; +parameter mask_gpv_trustzone__security_fssw_s0 = 32'h00000001; + +parameter gpv_trustzone__security_fssw_s1 = 32'hF8900020; +parameter val_gpv_trustzone__security_fssw_s1 = 32'h00000000; +parameter mask_gpv_trustzone__security_fssw_s1 = 32'h00000001; + +parameter gpv_trustzone__security_apb = 32'hF8900028; +parameter val_gpv_trustzone__security_apb = 32'h00000000; +parameter mask_gpv_trustzone__security_apb = 32'h0000003F; + + +// ************************************************************ +// Module i2c0 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter i2c0__Control_reg0 = 32'hE0004000; +parameter val_i2c0__Control_reg0 = 32'h00000000; +parameter mask_i2c0__Control_reg0 = 32'h0000FFFF; + +parameter i2c0__Status_reg0 = 32'hE0004004; +parameter val_i2c0__Status_reg0 = 32'h00000000; +parameter mask_i2c0__Status_reg0 = 32'h0000FFFF; + +parameter i2c0__I2C_address_reg0 = 32'hE0004008; +parameter val_i2c0__I2C_address_reg0 = 32'h00000000; +parameter mask_i2c0__I2C_address_reg0 = 32'h0000FFFF; + +parameter i2c0__I2C_data_reg0 = 32'hE000400C; +parameter val_i2c0__I2C_data_reg0 = 32'h00000000; +parameter mask_i2c0__I2C_data_reg0 = 32'h0000FFFF; + +parameter i2c0__Interrupt_status_reg0 = 32'hE0004010; +parameter val_i2c0__Interrupt_status_reg0 = 32'h00000000; +parameter mask_i2c0__Interrupt_status_reg0 = 32'h0000FFFF; + +parameter i2c0__Transfer_size_reg0 = 32'hE0004014; +parameter val_i2c0__Transfer_size_reg0 = 32'h00000000; +parameter mask_i2c0__Transfer_size_reg0 = 32'h000000FF; + +parameter i2c0__Slave_mon_pause_reg0 = 32'hE0004018; +parameter val_i2c0__Slave_mon_pause_reg0 = 32'h00000000; +parameter mask_i2c0__Slave_mon_pause_reg0 = 32'h000000FF; + +parameter i2c0__Time_out_reg0 = 32'hE000401C; +parameter val_i2c0__Time_out_reg0 = 32'h0000001F; +parameter mask_i2c0__Time_out_reg0 = 32'h000000FF; + +parameter i2c0__Intrpt_mask_reg0 = 32'hE0004020; +parameter val_i2c0__Intrpt_mask_reg0 = 32'h000002FF; +parameter mask_i2c0__Intrpt_mask_reg0 = 32'h0000FFFF; + +parameter i2c0__Intrpt_enable_reg0 = 32'hE0004024; +parameter val_i2c0__Intrpt_enable_reg0 = 32'h00000000; +parameter mask_i2c0__Intrpt_enable_reg0 = 32'h0000FFFF; + +parameter i2c0__Intrpt_disable_reg0 = 32'hE0004028; +parameter val_i2c0__Intrpt_disable_reg0 = 32'h00000000; +parameter mask_i2c0__Intrpt_disable_reg0 = 32'h0000FFFF; + + +// ************************************************************ +// Module i2c1 IIC +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter i2c1__Control_reg0 = 32'hE0005000; +parameter val_i2c1__Control_reg0 = 32'h00000000; +parameter mask_i2c1__Control_reg0 = 32'h0000FFFF; + +parameter i2c1__Status_reg0 = 32'hE0005004; +parameter val_i2c1__Status_reg0 = 32'h00000000; +parameter mask_i2c1__Status_reg0 = 32'h0000FFFF; + +parameter i2c1__I2C_address_reg0 = 32'hE0005008; +parameter val_i2c1__I2C_address_reg0 = 32'h00000000; +parameter mask_i2c1__I2C_address_reg0 = 32'h0000FFFF; + +parameter i2c1__I2C_data_reg0 = 32'hE000500C; +parameter val_i2c1__I2C_data_reg0 = 32'h00000000; +parameter mask_i2c1__I2C_data_reg0 = 32'h0000FFFF; + +parameter i2c1__Interrupt_status_reg0 = 32'hE0005010; +parameter val_i2c1__Interrupt_status_reg0 = 32'h00000000; +parameter mask_i2c1__Interrupt_status_reg0 = 32'h0000FFFF; + +parameter i2c1__Transfer_size_reg0 = 32'hE0005014; +parameter val_i2c1__Transfer_size_reg0 = 32'h00000000; +parameter mask_i2c1__Transfer_size_reg0 = 32'h000000FF; + +parameter i2c1__Slave_mon_pause_reg0 = 32'hE0005018; +parameter val_i2c1__Slave_mon_pause_reg0 = 32'h00000000; +parameter mask_i2c1__Slave_mon_pause_reg0 = 32'h000000FF; + +parameter i2c1__Time_out_reg0 = 32'hE000501C; +parameter val_i2c1__Time_out_reg0 = 32'h0000001F; +parameter mask_i2c1__Time_out_reg0 = 32'h000000FF; + +parameter i2c1__Intrpt_mask_reg0 = 32'hE0005020; +parameter val_i2c1__Intrpt_mask_reg0 = 32'h000002FF; +parameter mask_i2c1__Intrpt_mask_reg0 = 32'h0000FFFF; + +parameter i2c1__Intrpt_enable_reg0 = 32'hE0005024; +parameter val_i2c1__Intrpt_enable_reg0 = 32'h00000000; +parameter mask_i2c1__Intrpt_enable_reg0 = 32'h0000FFFF; + +parameter i2c1__Intrpt_disable_reg0 = 32'hE0005028; +parameter val_i2c1__Intrpt_disable_reg0 = 32'h00000000; +parameter mask_i2c1__Intrpt_disable_reg0 = 32'h0000FFFF; + + +// ************************************************************ +// Module l2cache L2Cpl310 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter l2cache__reg0_cache_id = 32'hF8F02000; +parameter val_l2cache__reg0_cache_id = 32'h410000C8; +parameter mask_l2cache__reg0_cache_id = 32'hFFFFFFFF; + +parameter l2cache__reg0_cache_type = 32'hF8F02004; +parameter val_l2cache__reg0_cache_type = 32'h9E300300; +parameter mask_l2cache__reg0_cache_type = 32'hFFFFFFFF; + +parameter l2cache__reg1_control = 32'hF8F02100; +parameter val_l2cache__reg1_control = 32'h00000000; +parameter mask_l2cache__reg1_control = 32'h7FFFFFFF; + +parameter l2cache__reg1_aux_control = 32'hF8F02104; +parameter val_l2cache__reg1_aux_control = 32'h02050000; +parameter mask_l2cache__reg1_aux_control = 32'hFFFFFFFF; + +parameter l2cache__reg1_tag_ram_control = 32'hF8F02108; +parameter val_l2cache__reg1_tag_ram_control = 32'h00000777; +parameter mask_l2cache__reg1_tag_ram_control = 32'hFFFFFFFF; + +parameter l2cache__reg1_data_ram_control = 32'hF8F0210C; +parameter val_l2cache__reg1_data_ram_control = 32'h00000777; +parameter mask_l2cache__reg1_data_ram_control = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter_ctrl = 32'hF8F02200; +parameter val_l2cache__reg2_ev_counter_ctrl = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter1_cfg = 32'hF8F02204; +parameter val_l2cache__reg2_ev_counter1_cfg = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter1_cfg = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter0_cfg = 32'hF8F02208; +parameter val_l2cache__reg2_ev_counter0_cfg = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter0_cfg = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter1 = 32'hF8F0220C; +parameter val_l2cache__reg2_ev_counter1 = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter1 = 32'hFFFFFFFF; + +parameter l2cache__reg2_ev_counter0 = 32'hF8F02210; +parameter val_l2cache__reg2_ev_counter0 = 32'h00000000; +parameter mask_l2cache__reg2_ev_counter0 = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_mask = 32'hF8F02214; +parameter val_l2cache__reg2_int_mask = 32'h00000000; +parameter mask_l2cache__reg2_int_mask = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_mask_status = 32'hF8F02218; +parameter val_l2cache__reg2_int_mask_status = 32'h00000000; +parameter mask_l2cache__reg2_int_mask_status = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_raw_status = 32'hF8F0221C; +parameter val_l2cache__reg2_int_raw_status = 32'h00000000; +parameter mask_l2cache__reg2_int_raw_status = 32'hFFFFFFFF; + +parameter l2cache__reg2_int_clear = 32'hF8F02220; +parameter val_l2cache__reg2_int_clear = 32'h00000000; +parameter mask_l2cache__reg2_int_clear = 32'hFFFFFFFF; + +parameter l2cache__reg7_cache_sync = 32'hF8F02730; +parameter val_l2cache__reg7_cache_sync = 32'h00000000; +parameter mask_l2cache__reg7_cache_sync = 32'hFFFFFFFF; + +parameter l2cache__reg7_inv_pa = 32'hF8F02770; +parameter val_l2cache__reg7_inv_pa = 32'h00000000; +parameter mask_l2cache__reg7_inv_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_inv_way = 32'hF8F0277C; +parameter val_l2cache__reg7_inv_way = 32'h00000000; +parameter mask_l2cache__reg7_inv_way = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_pa = 32'hF8F027B0; +parameter val_l2cache__reg7_clean_pa = 32'h00000000; +parameter mask_l2cache__reg7_clean_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_index = 32'hF8F027B8; +parameter val_l2cache__reg7_clean_index = 32'h00000000; +parameter mask_l2cache__reg7_clean_index = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_way = 32'hF8F027BC; +parameter val_l2cache__reg7_clean_way = 32'h00000000; +parameter mask_l2cache__reg7_clean_way = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_pa = 32'hF8F027F0; +parameter val_l2cache__reg7_clean_inv_pa = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_pa = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_index = 32'hF8F027F8; +parameter val_l2cache__reg7_clean_inv_index = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_index = 32'hFFFFFFFF; + +parameter l2cache__reg7_clean_inv_way = 32'hF8F027FC; +parameter val_l2cache__reg7_clean_inv_way = 32'h00000000; +parameter mask_l2cache__reg7_clean_inv_way = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown0 = 32'hF8F02900; +parameter val_l2cache__reg9_d_lockdown0 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown0 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown0 = 32'hF8F02904; +parameter val_l2cache__reg9_i_lockdown0 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown0 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown1 = 32'hF8F02908; +parameter val_l2cache__reg9_d_lockdown1 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown1 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown1 = 32'hF8F0290C; +parameter val_l2cache__reg9_i_lockdown1 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown1 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown2 = 32'hF8F02910; +parameter val_l2cache__reg9_d_lockdown2 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown2 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown2 = 32'hF8F02914; +parameter val_l2cache__reg9_i_lockdown2 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown2 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown3 = 32'hF8F02918; +parameter val_l2cache__reg9_d_lockdown3 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown3 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown3 = 32'hF8F0291C; +parameter val_l2cache__reg9_i_lockdown3 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown3 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown4 = 32'hF8F02920; +parameter val_l2cache__reg9_d_lockdown4 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown4 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown4 = 32'hF8F02924; +parameter val_l2cache__reg9_i_lockdown4 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown4 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown5 = 32'hF8F02928; +parameter val_l2cache__reg9_d_lockdown5 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown5 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown5 = 32'hF8F0292C; +parameter val_l2cache__reg9_i_lockdown5 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown5 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown6 = 32'hF8F02930; +parameter val_l2cache__reg9_d_lockdown6 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown6 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown6 = 32'hF8F02934; +parameter val_l2cache__reg9_i_lockdown6 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown6 = 32'hFFFFFFFF; + +parameter l2cache__reg9_d_lockdown7 = 32'hF8F02938; +parameter val_l2cache__reg9_d_lockdown7 = 32'h00000000; +parameter mask_l2cache__reg9_d_lockdown7 = 32'hFFFFFFFF; + +parameter l2cache__reg9_i_lockdown7 = 32'hF8F0293C; +parameter val_l2cache__reg9_i_lockdown7 = 32'h00000000; +parameter mask_l2cache__reg9_i_lockdown7 = 32'hFFFFFFFF; + +parameter l2cache__reg9_lock_line_en = 32'hF8F02950; +parameter val_l2cache__reg9_lock_line_en = 32'h00000000; +parameter mask_l2cache__reg9_lock_line_en = 32'hFFFFFFFF; + +parameter l2cache__reg9_unlock_way = 32'hF8F02954; +parameter val_l2cache__reg9_unlock_way = 32'h00000000; +parameter mask_l2cache__reg9_unlock_way = 32'hFFFFFFFF; + +parameter l2cache__reg12_addr_filtering_start = 32'hF8F02C00; +parameter val_l2cache__reg12_addr_filtering_start = 32'h40000001; +parameter mask_l2cache__reg12_addr_filtering_start = 32'hFFFFFFFF; + +parameter l2cache__reg12_addr_filtering_end = 32'hF8F02C04; +parameter val_l2cache__reg12_addr_filtering_end = 32'hFFF00000; +parameter mask_l2cache__reg12_addr_filtering_end = 32'hFFFFFFFF; + +parameter l2cache__reg15_debug_ctrl = 32'hF8F02F40; +parameter val_l2cache__reg15_debug_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_debug_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg15_prefetch_ctrl = 32'hF8F02F60; +parameter val_l2cache__reg15_prefetch_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_prefetch_ctrl = 32'hFFFFFFFF; + +parameter l2cache__reg15_power_ctrl = 32'hF8F02F80; +parameter val_l2cache__reg15_power_ctrl = 32'h00000000; +parameter mask_l2cache__reg15_power_ctrl = 32'hFFFFFFFF; + + +// ************************************************************ +// Module mpcore mpcore +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter mpcore__SCU_CONTROL_REGISTER = 32'hF8F00000; +parameter val_mpcore__SCU_CONTROL_REGISTER = 32'h00000002; +parameter mask_mpcore__SCU_CONTROL_REGISTER = 32'hFFFFFFFF; + +parameter mpcore__SCU_CONFIGURATION_REGISTER = 32'hF8F00004; +parameter val_mpcore__SCU_CONFIGURATION_REGISTER = 32'h00000501; +parameter mask_mpcore__SCU_CONFIGURATION_REGISTER = 32'hFFFFFFFF; + +parameter mpcore__SCU_CPU_Power_Status_Register = 32'hF8F00008; +parameter val_mpcore__SCU_CPU_Power_Status_Register = 32'h00000000; +parameter mask_mpcore__SCU_CPU_Power_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hF8F0000C; +parameter val_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'h00000000; +parameter mask_mpcore__SCU_Invalidate_All_Registers_in_Secure_State = 32'hFFFFFFFF; + +parameter mpcore__Filtering_Start_Address_Register = 32'hF8F00040; +parameter val_mpcore__Filtering_Start_Address_Register = 32'h00100000; +parameter mask_mpcore__Filtering_Start_Address_Register = 32'hFFFFFFFF; + +parameter mpcore__Filtering_End_Address_Register = 32'hF8F00044; +parameter val_mpcore__Filtering_End_Address_Register = 32'h00000000; +parameter mask_mpcore__Filtering_End_Address_Register = 32'hFFFFFFFF; + +parameter mpcore__SCU_Access_Control_Register_SAC = 32'hF8F00050; +parameter val_mpcore__SCU_Access_Control_Register_SAC = 32'h0000000F; +parameter mask_mpcore__SCU_Access_Control_Register_SAC = 32'hFFFFFFFF; + +parameter mpcore__SCU_Non_secure_Access_Control_Register = 32'hF8F00054; +parameter val_mpcore__SCU_Non_secure_Access_Control_Register = 32'h00000000; +parameter mask_mpcore__SCU_Non_secure_Access_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__ICCICR = 32'hF8F00100; +parameter val_mpcore__ICCICR = 32'h00000000; +parameter mask_mpcore__ICCICR = 32'hFFFFFFFF; + +parameter mpcore__ICCPMR = 32'hF8F00104; +parameter val_mpcore__ICCPMR = 32'h00000000; +parameter mask_mpcore__ICCPMR = 32'hFFFFFFFF; + +parameter mpcore__ICCBPR = 32'hF8F00108; +parameter val_mpcore__ICCBPR = 32'h00000002; +parameter mask_mpcore__ICCBPR = 32'hFFFFFFFF; + +parameter mpcore__ICCIAR = 32'hF8F0010C; +parameter val_mpcore__ICCIAR = 32'h000003FF; +parameter mask_mpcore__ICCIAR = 32'hFFFFFFFF; + +parameter mpcore__ICCEOIR = 32'hF8F00110; +parameter val_mpcore__ICCEOIR = 32'h00000000; +parameter mask_mpcore__ICCEOIR = 32'hFFFFFFFF; + +parameter mpcore__ICCRPR = 32'hF8F00114; +parameter val_mpcore__ICCRPR = 32'h000000FF; +parameter mask_mpcore__ICCRPR = 32'hFFFFFFFF; + +parameter mpcore__ICCHPIR = 32'hF8F00118; +parameter val_mpcore__ICCHPIR = 32'h000003FF; +parameter mask_mpcore__ICCHPIR = 32'hFFFFFFFF; + +parameter mpcore__ICCABPR = 32'hF8F0011C; +parameter val_mpcore__ICCABPR = 32'h00000003; +parameter mask_mpcore__ICCABPR = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR = 32'hF8F001FC; +parameter val_mpcore__ICCIDR = 32'h3901243B; +parameter mask_mpcore__ICCIDR = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Counter_Register0 = 32'hF8F00200; +parameter val_mpcore__Global_Timer_Counter_Register0 = 32'h00000000; +parameter mask_mpcore__Global_Timer_Counter_Register0 = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Counter_Register1 = 32'hF8F00204; +parameter val_mpcore__Global_Timer_Counter_Register1 = 32'h00000000; +parameter mask_mpcore__Global_Timer_Counter_Register1 = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Control_Register = 32'hF8F00208; +parameter val_mpcore__Global_Timer_Control_Register = 32'h00000000; +parameter mask_mpcore__Global_Timer_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Global_Timer_Interrupt_Status_Register = 32'hF8F0020C; +parameter val_mpcore__Global_Timer_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Global_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Comparator_Value_Register0 = 32'hF8F00210; +parameter val_mpcore__Comparator_Value_Register0 = 32'h00000000; +parameter mask_mpcore__Comparator_Value_Register0 = 32'hFFFFFFFF; + +parameter mpcore__Comparator_Value_Register1 = 32'hF8F00214; +parameter val_mpcore__Comparator_Value_Register1 = 32'h00000000; +parameter mask_mpcore__Comparator_Value_Register1 = 32'hFFFFFFFF; + +parameter mpcore__Auto_increment_Register = 32'hF8F00218; +parameter val_mpcore__Auto_increment_Register = 32'h00000000; +parameter mask_mpcore__Auto_increment_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Load_Register = 32'hF8F00600; +parameter val_mpcore__Private_Timer_Load_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Load_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Counter_Register = 32'hF8F00604; +parameter val_mpcore__Private_Timer_Counter_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Counter_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Control_Register = 32'hF8F00608; +parameter val_mpcore__Private_Timer_Control_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Private_Timer_Interrupt_Status_Register = 32'hF8F0060C; +parameter val_mpcore__Private_Timer_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Private_Timer_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Load_Register = 32'hF8F00620; +parameter val_mpcore__Watchdog_Load_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Load_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Counter_Register = 32'hF8F00624; +parameter val_mpcore__Watchdog_Counter_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Counter_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Control_Register = 32'hF8F00628; +parameter val_mpcore__Watchdog_Control_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Control_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Interrupt_Status_Register = 32'hF8F0062C; +parameter val_mpcore__Watchdog_Interrupt_Status_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Interrupt_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Reset_Status_Register = 32'hF8F00630; +parameter val_mpcore__Watchdog_Reset_Status_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Reset_Status_Register = 32'hFFFFFFFF; + +parameter mpcore__Watchdog_Disable_Register = 32'hF8F00634; +parameter val_mpcore__Watchdog_Disable_Register = 32'h00000000; +parameter mask_mpcore__Watchdog_Disable_Register = 32'hFFFFFFFF; + +parameter mpcore__ICDDCR = 32'hF8F01000; +parameter val_mpcore__ICDDCR = 32'h00000000; +parameter mask_mpcore__ICDDCR = 32'hFFFFFFFF; + +parameter mpcore__ICDICTR = 32'hF8F01004; +parameter val_mpcore__ICDICTR = 32'h00000C22; +parameter mask_mpcore__ICDICTR = 32'hE000FFFF; + +parameter mpcore__ICDIIDR = 32'hF8F01008; +parameter val_mpcore__ICDIIDR = 32'h0102043B; +parameter mask_mpcore__ICDIIDR = 32'hFFFFFFFF; + +parameter mpcore__ICDISR0 = 32'hF8F01080; +parameter val_mpcore__ICDISR0 = 32'h00000000; +parameter mask_mpcore__ICDISR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISR1 = 32'hF8F01084; +parameter val_mpcore__ICDISR1 = 32'h00000000; +parameter mask_mpcore__ICDISR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISR2 = 32'hF8F01088; +parameter val_mpcore__ICDISR2 = 32'h00000000; +parameter mask_mpcore__ICDISR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER0 = 32'hF8F01100; +parameter val_mpcore__ICDISER0 = 32'h0000FFFF; +parameter mask_mpcore__ICDISER0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER1 = 32'hF8F01104; +parameter val_mpcore__ICDISER1 = 32'h00000000; +parameter mask_mpcore__ICDISER1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISER2 = 32'hF8F01108; +parameter val_mpcore__ICDISER2 = 32'h00000000; +parameter mask_mpcore__ICDISER2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER0 = 32'hF8F01180; +parameter val_mpcore__ICDICER0 = 32'h0000FFFF; +parameter mask_mpcore__ICDICER0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER1 = 32'hF8F01184; +parameter val_mpcore__ICDICER1 = 32'h00000000; +parameter mask_mpcore__ICDICER1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICER2 = 32'hF8F01188; +parameter val_mpcore__ICDICER2 = 32'h00000000; +parameter mask_mpcore__ICDICER2 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR0 = 32'hF8F01200; +parameter val_mpcore__ICDISPR0 = 32'h00000000; +parameter mask_mpcore__ICDISPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR1 = 32'hF8F01204; +parameter val_mpcore__ICDISPR1 = 32'h00000000; +parameter mask_mpcore__ICDISPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDISPR2 = 32'hF8F01208; +parameter val_mpcore__ICDISPR2 = 32'h00000000; +parameter mask_mpcore__ICDISPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR0 = 32'hF8F01280; +parameter val_mpcore__ICDICPR0 = 32'h00000000; +parameter mask_mpcore__ICDICPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR1 = 32'hF8F01284; +parameter val_mpcore__ICDICPR1 = 32'h00000000; +parameter mask_mpcore__ICDICPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICPR2 = 32'hF8F01288; +parameter val_mpcore__ICDICPR2 = 32'h00000000; +parameter mask_mpcore__ICDICPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR0 = 32'hF8F01300; +parameter val_mpcore__ICDABR0 = 32'h00000000; +parameter mask_mpcore__ICDABR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR1 = 32'hF8F01304; +parameter val_mpcore__ICDABR1 = 32'h00000000; +parameter mask_mpcore__ICDABR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDABR2 = 32'hF8F01308; +parameter val_mpcore__ICDABR2 = 32'h00000000; +parameter mask_mpcore__ICDABR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR0 = 32'hF8F01400; +parameter val_mpcore__ICDIPR0 = 32'h00000000; +parameter mask_mpcore__ICDIPR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR1 = 32'hF8F01404; +parameter val_mpcore__ICDIPR1 = 32'h00000000; +parameter mask_mpcore__ICDIPR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR2 = 32'hF8F01408; +parameter val_mpcore__ICDIPR2 = 32'h00000000; +parameter mask_mpcore__ICDIPR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR3 = 32'hF8F0140C; +parameter val_mpcore__ICDIPR3 = 32'h00000000; +parameter mask_mpcore__ICDIPR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR4 = 32'hF8F01410; +parameter val_mpcore__ICDIPR4 = 32'h00000000; +parameter mask_mpcore__ICDIPR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR5 = 32'hF8F01414; +parameter val_mpcore__ICDIPR5 = 32'h00000000; +parameter mask_mpcore__ICDIPR5 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR6 = 32'hF8F01418; +parameter val_mpcore__ICDIPR6 = 32'h00000000; +parameter mask_mpcore__ICDIPR6 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR7 = 32'hF8F0141C; +parameter val_mpcore__ICDIPR7 = 32'h00000000; +parameter mask_mpcore__ICDIPR7 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR8 = 32'hF8F01420; +parameter val_mpcore__ICDIPR8 = 32'h00000000; +parameter mask_mpcore__ICDIPR8 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR9 = 32'hF8F01424; +parameter val_mpcore__ICDIPR9 = 32'h00000000; +parameter mask_mpcore__ICDIPR9 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR10 = 32'hF8F01428; +parameter val_mpcore__ICDIPR10 = 32'h00000000; +parameter mask_mpcore__ICDIPR10 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR11 = 32'hF8F0142C; +parameter val_mpcore__ICDIPR11 = 32'h00000000; +parameter mask_mpcore__ICDIPR11 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR12 = 32'hF8F01430; +parameter val_mpcore__ICDIPR12 = 32'h00000000; +parameter mask_mpcore__ICDIPR12 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR13 = 32'hF8F01434; +parameter val_mpcore__ICDIPR13 = 32'h00000000; +parameter mask_mpcore__ICDIPR13 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR14 = 32'hF8F01438; +parameter val_mpcore__ICDIPR14 = 32'h00000000; +parameter mask_mpcore__ICDIPR14 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR15 = 32'hF8F0143C; +parameter val_mpcore__ICDIPR15 = 32'h00000000; +parameter mask_mpcore__ICDIPR15 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR16 = 32'hF8F01440; +parameter val_mpcore__ICDIPR16 = 32'h00000000; +parameter mask_mpcore__ICDIPR16 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR17 = 32'hF8F01444; +parameter val_mpcore__ICDIPR17 = 32'h00000000; +parameter mask_mpcore__ICDIPR17 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR18 = 32'hF8F01448; +parameter val_mpcore__ICDIPR18 = 32'h00000000; +parameter mask_mpcore__ICDIPR18 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR19 = 32'hF8F0144C; +parameter val_mpcore__ICDIPR19 = 32'h00000000; +parameter mask_mpcore__ICDIPR19 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR20 = 32'hF8F01450; +parameter val_mpcore__ICDIPR20 = 32'h00000000; +parameter mask_mpcore__ICDIPR20 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR21 = 32'hF8F01454; +parameter val_mpcore__ICDIPR21 = 32'h00000000; +parameter mask_mpcore__ICDIPR21 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR22 = 32'hF8F01458; +parameter val_mpcore__ICDIPR22 = 32'h00000000; +parameter mask_mpcore__ICDIPR22 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPR23 = 32'hF8F0145C; +parameter val_mpcore__ICDIPR23 = 32'h00000000; +parameter mask_mpcore__ICDIPR23 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR0 = 32'hF8F01800; +parameter val_mpcore__ICDIPTR0 = 32'h01010101; +parameter mask_mpcore__ICDIPTR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR1 = 32'hF8F01804; +parameter val_mpcore__ICDIPTR1 = 32'h01010101; +parameter mask_mpcore__ICDIPTR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR2 = 32'hF8F01808; +parameter val_mpcore__ICDIPTR2 = 32'h01010101; +parameter mask_mpcore__ICDIPTR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR3 = 32'hF8F0180C; +parameter val_mpcore__ICDIPTR3 = 32'h01010101; +parameter mask_mpcore__ICDIPTR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR4 = 32'hF8F01810; +parameter val_mpcore__ICDIPTR4 = 32'h01010101; +parameter mask_mpcore__ICDIPTR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR5 = 32'hF8F01814; +parameter val_mpcore__ICDIPTR5 = 32'h01010101; +parameter mask_mpcore__ICDIPTR5 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR6 = 32'hF8F01818; +parameter val_mpcore__ICDIPTR6 = 32'h01010101; +parameter mask_mpcore__ICDIPTR6 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR7 = 32'hF8F0181C; +parameter val_mpcore__ICDIPTR7 = 32'h01010101; +parameter mask_mpcore__ICDIPTR7 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR8 = 32'hF8F01820; +parameter val_mpcore__ICDIPTR8 = 32'h01010101; +parameter mask_mpcore__ICDIPTR8 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR9 = 32'hF8F01824; +parameter val_mpcore__ICDIPTR9 = 32'h01010101; +parameter mask_mpcore__ICDIPTR9 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR10 = 32'hF8F01828; +parameter val_mpcore__ICDIPTR10 = 32'h01010101; +parameter mask_mpcore__ICDIPTR10 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR11 = 32'hF8F0182C; +parameter val_mpcore__ICDIPTR11 = 32'h01010101; +parameter mask_mpcore__ICDIPTR11 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR12 = 32'hF8F01830; +parameter val_mpcore__ICDIPTR12 = 32'h01010101; +parameter mask_mpcore__ICDIPTR12 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR13 = 32'hF8F01834; +parameter val_mpcore__ICDIPTR13 = 32'h01010101; +parameter mask_mpcore__ICDIPTR13 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR14 = 32'hF8F01838; +parameter val_mpcore__ICDIPTR14 = 32'h01010101; +parameter mask_mpcore__ICDIPTR14 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR15 = 32'hF8F0183C; +parameter val_mpcore__ICDIPTR15 = 32'h01010101; +parameter mask_mpcore__ICDIPTR15 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR16 = 32'hF8F01840; +parameter val_mpcore__ICDIPTR16 = 32'h01010101; +parameter mask_mpcore__ICDIPTR16 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR17 = 32'hF8F01844; +parameter val_mpcore__ICDIPTR17 = 32'h01010101; +parameter mask_mpcore__ICDIPTR17 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR18 = 32'hF8F01848; +parameter val_mpcore__ICDIPTR18 = 32'h01010101; +parameter mask_mpcore__ICDIPTR18 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR19 = 32'hF8F0184C; +parameter val_mpcore__ICDIPTR19 = 32'h01010101; +parameter mask_mpcore__ICDIPTR19 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR20 = 32'hF8F01850; +parameter val_mpcore__ICDIPTR20 = 32'h01010101; +parameter mask_mpcore__ICDIPTR20 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR21 = 32'hF8F01854; +parameter val_mpcore__ICDIPTR21 = 32'h01010101; +parameter mask_mpcore__ICDIPTR21 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR22 = 32'hF8F01858; +parameter val_mpcore__ICDIPTR22 = 32'h01010101; +parameter mask_mpcore__ICDIPTR22 = 32'hFFFFFFFF; + +parameter mpcore__ICDIPTR23 = 32'hF8F0185C; +parameter val_mpcore__ICDIPTR23 = 32'h01010101; +parameter mask_mpcore__ICDIPTR23 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR0 = 32'hF8F01C00; +parameter val_mpcore__ICDICFR0 = 32'hAAAAAAAA; +parameter mask_mpcore__ICDICFR0 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR1 = 32'hF8F01C04; +parameter val_mpcore__ICDICFR1 = 32'h7DC00000; +parameter mask_mpcore__ICDICFR1 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR2 = 32'hF8F01C08; +parameter val_mpcore__ICDICFR2 = 32'h55555555; +parameter mask_mpcore__ICDICFR2 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR3 = 32'hF8F01C0C; +parameter val_mpcore__ICDICFR3 = 32'h55555555; +parameter mask_mpcore__ICDICFR3 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR4 = 32'hF8F01C10; +parameter val_mpcore__ICDICFR4 = 32'h55555555; +parameter mask_mpcore__ICDICFR4 = 32'hFFFFFFFF; + +parameter mpcore__ICDICFR5 = 32'hF8F01C14; +parameter val_mpcore__ICDICFR5 = 32'h55555555; +parameter mask_mpcore__ICDICFR5 = 32'hFFFFFFFF; + +parameter mpcore__ppi_status = 32'hF8F01D00; +parameter val_mpcore__ppi_status = 32'h00000000; +parameter mask_mpcore__ppi_status = 32'hFFFFFFFF; + +parameter mpcore__spi_status_0 = 32'hF8F01D04; +parameter val_mpcore__spi_status_0 = 32'h00000000; +parameter mask_mpcore__spi_status_0 = 32'hFFFFFFFF; + +parameter mpcore__spi_status_1 = 32'hF8F01D08; +parameter val_mpcore__spi_status_1 = 32'h00000000; +parameter mask_mpcore__spi_status_1 = 32'hFFFFFFFF; + +parameter mpcore__ICDSGIR = 32'hF8F01F00; +parameter val_mpcore__ICDSGIR = 32'h00000000; +parameter mask_mpcore__ICDSGIR = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR4 = 32'hF8F01FD0; +parameter val_mpcore__ICPIDR4 = 32'h00000004; +parameter mask_mpcore__ICPIDR4 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR5 = 32'hF8F01FD4; +parameter val_mpcore__ICPIDR5 = 32'h00000000; +parameter mask_mpcore__ICPIDR5 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR6 = 32'hF8F01FD8; +parameter val_mpcore__ICPIDR6 = 32'h00000000; +parameter mask_mpcore__ICPIDR6 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR7 = 32'hF8F01FDC; +parameter val_mpcore__ICPIDR7 = 32'h00000000; +parameter mask_mpcore__ICPIDR7 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR0 = 32'hF8F01FE0; +parameter val_mpcore__ICPIDR0 = 32'h00000090; +parameter mask_mpcore__ICPIDR0 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR1 = 32'hF8F01FE4; +parameter val_mpcore__ICPIDR1 = 32'h000000B3; +parameter mask_mpcore__ICPIDR1 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR2 = 32'hF8F01FE8; +parameter val_mpcore__ICPIDR2 = 32'h0000001B; +parameter mask_mpcore__ICPIDR2 = 32'hFFFFFFFF; + +parameter mpcore__ICPIDR3 = 32'hF8F01FEC; +parameter val_mpcore__ICPIDR3 = 32'h00000000; +parameter mask_mpcore__ICPIDR3 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR0 = 32'hF8F01FF0; +parameter val_mpcore__ICCIDR0 = 32'h0000000D; +parameter mask_mpcore__ICCIDR0 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR1 = 32'hF8F01FF4; +parameter val_mpcore__ICCIDR1 = 32'h000000F0; +parameter mask_mpcore__ICCIDR1 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR2 = 32'hF8F01FF8; +parameter val_mpcore__ICCIDR2 = 32'h00000005; +parameter mask_mpcore__ICCIDR2 = 32'hFFFFFFFF; + +parameter mpcore__ICCIDR3 = 32'hF8F01FFC; +parameter val_mpcore__ICCIDR3 = 32'h000000B1; +parameter mask_mpcore__ICCIDR3 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module ocm ocm +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ocm__OCM_PARITY_CTRL = 32'hF800C000; +parameter val_ocm__OCM_PARITY_CTRL = 32'h00000000; +parameter mask_ocm__OCM_PARITY_CTRL = 32'hFFFFFFFF; + +parameter ocm__OCM_PARITY_ERRADDRESS = 32'hF800C004; +parameter val_ocm__OCM_PARITY_ERRADDRESS = 32'h00000000; +parameter mask_ocm__OCM_PARITY_ERRADDRESS = 32'hFFFFFFFF; + +parameter ocm__OCM_IRQ_STS = 32'hF800C008; +parameter val_ocm__OCM_IRQ_STS = 32'h00000000; +parameter mask_ocm__OCM_IRQ_STS = 32'hFFFFFFFF; + +parameter ocm__OCM_CONTROL = 32'hF800C00C; +parameter val_ocm__OCM_CONTROL = 32'h00000000; +parameter mask_ocm__OCM_CONTROL = 32'hFFFFFFFF; + + +// ************************************************************ +// Module qspi qspi +// doc version: 0.8, based on 11/01/10 Linear Quad-SPI Controller +// Design Specification document +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter qspi__Config_reg = 32'hE000D000; +parameter val_qspi__Config_reg = 32'h80000000; +parameter mask_qspi__Config_reg = 32'hFFFDFFFF; + +parameter qspi__Intr_status_REG = 32'hE000D004; +parameter val_qspi__Intr_status_REG = 32'h00000004; +parameter mask_qspi__Intr_status_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_en_REG = 32'hE000D008; +parameter val_qspi__Intrpt_en_REG = 32'h00000000; +parameter mask_qspi__Intrpt_en_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_dis_REG = 32'hE000D00C; +parameter val_qspi__Intrpt_dis_REG = 32'h00000000; +parameter mask_qspi__Intrpt_dis_REG = 32'hFFFFFFFF; + +parameter qspi__Intrpt_mask_REG = 32'hE000D010; +parameter val_qspi__Intrpt_mask_REG = 32'h00000000; +parameter mask_qspi__Intrpt_mask_REG = 32'hFFFFFFFF; + +parameter qspi__En_REG = 32'hE000D014; +parameter val_qspi__En_REG = 32'h00000000; +parameter mask_qspi__En_REG = 32'hFFFFFFFF; + +parameter qspi__Delay_REG = 32'hE000D018; +parameter val_qspi__Delay_REG = 32'h00000000; +parameter mask_qspi__Delay_REG = 32'hFFFFFFFF; + +parameter qspi__TXD0 = 32'hE000D01C; +parameter val_qspi__TXD0 = 32'h00000000; +parameter mask_qspi__TXD0 = 32'hFFFFFFFF; + +parameter qspi__Rx_data_REG = 32'hE000D020; +parameter val_qspi__Rx_data_REG = 32'h00000000; +parameter mask_qspi__Rx_data_REG = 32'hFFFFFFFF; + +parameter qspi__Slave_Idle_count_REG = 32'hE000D024; +parameter val_qspi__Slave_Idle_count_REG = 32'h000000FF; +parameter mask_qspi__Slave_Idle_count_REG = 32'hFFFFFFFF; + +parameter qspi__TX_thres_REG = 32'hE000D028; +parameter val_qspi__TX_thres_REG = 32'h00000001; +parameter mask_qspi__TX_thres_REG = 32'hFFFFFFFF; + +parameter qspi__RX_thres_REG = 32'hE000D02C; +parameter val_qspi__RX_thres_REG = 32'h00000001; +parameter mask_qspi__RX_thres_REG = 32'hFFFFFFFF; + +parameter qspi__GPIO = 32'hE000D030; +parameter val_qspi__GPIO = 32'h00000001; +parameter mask_qspi__GPIO = 32'hFFFFFFFF; + +parameter qspi__LPBK_DLY_ADJ = 32'hE000D038; +parameter val_qspi__LPBK_DLY_ADJ = 32'h00000033; +parameter mask_qspi__LPBK_DLY_ADJ = 32'hFFFFFFFF; + +parameter qspi__TXD1 = 32'hE000D080; +parameter val_qspi__TXD1 = 32'h00000000; +parameter mask_qspi__TXD1 = 32'hFFFFFFFF; + +parameter qspi__TXD2 = 32'hE000D084; +parameter val_qspi__TXD2 = 32'h00000000; +parameter mask_qspi__TXD2 = 32'hFFFFFFFF; + +parameter qspi__TXD3 = 32'hE000D088; +parameter val_qspi__TXD3 = 32'h00000000; +parameter mask_qspi__TXD3 = 32'hFFFFFFFF; + +parameter qspi__LQSPI_CFG = 32'hE000D0A0; +parameter val_qspi__LQSPI_CFG = 32'h03A002EB; +parameter mask_qspi__LQSPI_CFG = 32'hFBFF07FF; + +parameter qspi__LQSPI_STS = 32'hE000D0A4; +parameter val_qspi__LQSPI_STS = 32'h00000000; +parameter mask_qspi__LQSPI_STS = 32'h000001FF; + +parameter qspi__MOD_ID = 32'hE000D0FC; +parameter val_qspi__MOD_ID = 32'h01090101; +parameter mask_qspi__MOD_ID = 32'hFFFFFFFF; + + +// ************************************************************ +// Module sd0 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter sd0__SDMA_system_address_register = 32'hE0100000; +parameter val_sd0__SDMA_system_address_register = 32'h00000000; +parameter mask_sd0__SDMA_system_address_register = 32'hFFFFFFFF; + +parameter sd0__Block_Size_Block_Count = 32'hE0100004; +parameter val_sd0__Block_Size_Block_Count = 32'h00000000; +parameter mask_sd0__Block_Size_Block_Count = 32'hFFFFFFFF; + +parameter sd0__Argument = 32'hE0100008; +parameter val_sd0__Argument = 32'h00000000; +parameter mask_sd0__Argument = 32'hFFFFFFFF; + +parameter sd0__Transfer_Mode_Command = 32'hE010000C; +parameter val_sd0__Transfer_Mode_Command = 32'h00000000; +parameter mask_sd0__Transfer_Mode_Command = 32'h1FFFFFFF; + +parameter sd0__Response0 = 32'hE0100010; +parameter val_sd0__Response0 = 32'h00000000; +parameter mask_sd0__Response0 = 32'hFFFFFFFF; + +parameter sd0__Response1 = 32'hE0100014; +parameter val_sd0__Response1 = 32'h00000000; +parameter mask_sd0__Response1 = 32'hFFFFFFFF; + +parameter sd0__Response2 = 32'hE0100018; +parameter val_sd0__Response2 = 32'h00000000; +parameter mask_sd0__Response2 = 32'hFFFFFFFF; + +parameter sd0__Response3 = 32'hE010001C; +parameter val_sd0__Response3 = 32'h00000000; +parameter mask_sd0__Response3 = 32'hFFFFFFFF; + +parameter sd0__Buffer_Data_Port = 32'hE0100020; +parameter val_sd0__Buffer_Data_Port = 32'h00000000; +parameter mask_sd0__Buffer_Data_Port = 32'hFFFFFFFF; + +parameter sd0__Present_State = 32'hE0100024; +parameter val_sd0__Present_State = 32'h01F20000; +parameter mask_sd0__Present_State = 32'h01FFFFFF; + +parameter sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0100028; +parameter val_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; +parameter mask_sd0__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; + +parameter sd0__Clock_Control_Timeout_control_Software_reset = 32'hE010002C; +parameter val_sd0__Clock_Control_Timeout_control_Software_reset = 32'h00000000; +parameter mask_sd0__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; + +parameter sd0__Normal_interrupt_status_Error_interrupt_status = 32'hE0100030; +parameter val_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; +parameter mask_sd0__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; + +parameter sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0100034; +parameter val_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; +parameter mask_sd0__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; + +parameter sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0100038; +parameter val_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; +parameter mask_sd0__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; + +parameter sd0__Auto_CMD12_error_status = 32'hE010003C; +parameter val_sd0__Auto_CMD12_error_status = 32'h00000000; +parameter mask_sd0__Auto_CMD12_error_status = 32'h000000FF; + +parameter sd0__Capabilities = 32'hE0100040; +parameter val_sd0__Capabilities = 32'h69EC0080; +parameter mask_sd0__Capabilities = 32'h7FFFFFFF; + +parameter sd0__Maximum_current_capabilities = 32'hE0100048; +parameter val_sd0__Maximum_current_capabilities = 32'h00000001; +parameter mask_sd0__Maximum_current_capabilities = 32'h00FFFFFF; + +parameter sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0100050; +parameter val_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; +parameter mask_sd0__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; + +parameter sd0__ADMA_error_status = 32'hE0100054; +parameter val_sd0__ADMA_error_status = 32'h00000000; +parameter mask_sd0__ADMA_error_status = 32'h00000007; + +parameter sd0__ADMA_system_address = 32'hE0100058; +parameter val_sd0__ADMA_system_address = 32'h00000000; +parameter mask_sd0__ADMA_system_address = 32'hFFFFFFFF; + +parameter sd0__Boot_Timeout_control = 32'hE0100060; +parameter val_sd0__Boot_Timeout_control = 32'h00000000; +parameter mask_sd0__Boot_Timeout_control = 32'hFFFFFFFF; + +parameter sd0__Debug_Selection = 32'hE0100064; +parameter val_sd0__Debug_Selection = 32'h00000000; +parameter mask_sd0__Debug_Selection = 32'h00000001; + +parameter sd0__SPI_interrupt_support = 32'hE01000F0; +parameter val_sd0__SPI_interrupt_support = 32'h00000000; +parameter mask_sd0__SPI_interrupt_support = 32'h000000FF; + +parameter sd0__Slot_interrupt_status_Host_controller_version = 32'hE01000FC; +parameter val_sd0__Slot_interrupt_status_Host_controller_version = 32'h89010000; +parameter mask_sd0__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; + + +// ************************************************************ +// Module sd1 sdio +// doc version: 4.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter sd1__SDMA_system_address_register = 32'hE0101000; +parameter val_sd1__SDMA_system_address_register = 32'h00000000; +parameter mask_sd1__SDMA_system_address_register = 32'hFFFFFFFF; + +parameter sd1__Block_Size_Block_Count = 32'hE0101004; +parameter val_sd1__Block_Size_Block_Count = 32'h00000000; +parameter mask_sd1__Block_Size_Block_Count = 32'hFFFFFFFF; + +parameter sd1__Argument = 32'hE0101008; +parameter val_sd1__Argument = 32'h00000000; +parameter mask_sd1__Argument = 32'hFFFFFFFF; + +parameter sd1__Transfer_Mode_Command = 32'hE010100C; +parameter val_sd1__Transfer_Mode_Command = 32'h00000000; +parameter mask_sd1__Transfer_Mode_Command = 32'h1FFFFFFF; + +parameter sd1__Response0 = 32'hE0101010; +parameter val_sd1__Response0 = 32'h00000000; +parameter mask_sd1__Response0 = 32'hFFFFFFFF; + +parameter sd1__Response1 = 32'hE0101014; +parameter val_sd1__Response1 = 32'h00000000; +parameter mask_sd1__Response1 = 32'hFFFFFFFF; + +parameter sd1__Response2 = 32'hE0101018; +parameter val_sd1__Response2 = 32'h00000000; +parameter mask_sd1__Response2 = 32'hFFFFFFFF; + +parameter sd1__Response3 = 32'hE010101C; +parameter val_sd1__Response3 = 32'h00000000; +parameter mask_sd1__Response3 = 32'hFFFFFFFF; + +parameter sd1__Buffer_Data_Port = 32'hE0101020; +parameter val_sd1__Buffer_Data_Port = 32'h00000000; +parameter mask_sd1__Buffer_Data_Port = 32'hFFFFFFFF; + +parameter sd1__Present_State = 32'hE0101024; +parameter val_sd1__Present_State = 32'h01F20000; +parameter mask_sd1__Present_State = 32'h01FFFFFF; + +parameter sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hE0101028; +parameter val_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'h00000000; +parameter mask_sd1__Host_control_Power_control_Block_Gap_Control_Wakeup_control = 32'hFFFFFFFF; + +parameter sd1__Clock_Control_Timeout_control_Software_reset = 32'hE010102C; +parameter val_sd1__Clock_Control_Timeout_control_Software_reset = 32'h00000000; +parameter mask_sd1__Clock_Control_Timeout_control_Software_reset = 32'h07FFFFFF; + +parameter sd1__Normal_interrupt_status_Error_interrupt_status = 32'hE0101030; +parameter val_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h00000000; +parameter mask_sd1__Normal_interrupt_status_Error_interrupt_status = 32'h3FFFFFFF; + +parameter sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'hE0101034; +parameter val_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h00000000; +parameter mask_sd1__Normal_interrupt_status_enable_Error_interrupt_status_enable = 32'h3FFFFFFF; + +parameter sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'hE0101038; +parameter val_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h00000000; +parameter mask_sd1__Normal_interrupt_signal_enable_Error_interrupt_signal_enable = 32'h3FFFFFFF; + +parameter sd1__Auto_CMD12_error_status = 32'hE010103C; +parameter val_sd1__Auto_CMD12_error_status = 32'h00000000; +parameter mask_sd1__Auto_CMD12_error_status = 32'h000000FF; + +parameter sd1__Capabilities = 32'hE0101040; +parameter val_sd1__Capabilities = 32'h69EC0080; +parameter mask_sd1__Capabilities = 32'h7FFFFFFF; + +parameter sd1__Maximum_current_capabilities = 32'hE0101048; +parameter val_sd1__Maximum_current_capabilities = 32'h00000001; +parameter mask_sd1__Maximum_current_capabilities = 32'h00FFFFFF; + +parameter sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hE0101050; +parameter val_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'h00000000; +parameter mask_sd1__Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status = 32'hFFFFFFFF; + +parameter sd1__ADMA_error_status = 32'hE0101054; +parameter val_sd1__ADMA_error_status = 32'h00000000; +parameter mask_sd1__ADMA_error_status = 32'h00000007; + +parameter sd1__ADMA_system_address = 32'hE0101058; +parameter val_sd1__ADMA_system_address = 32'h00000000; +parameter mask_sd1__ADMA_system_address = 32'hFFFFFFFF; + +parameter sd1__Boot_Timeout_control = 32'hE0101060; +parameter val_sd1__Boot_Timeout_control = 32'h00000000; +parameter mask_sd1__Boot_Timeout_control = 32'hFFFFFFFF; + +parameter sd1__Debug_Selection = 32'hE0101064; +parameter val_sd1__Debug_Selection = 32'h00000000; +parameter mask_sd1__Debug_Selection = 32'h00000001; + +parameter sd1__SPI_interrupt_support = 32'hE01010F0; +parameter val_sd1__SPI_interrupt_support = 32'h00000000; +parameter mask_sd1__SPI_interrupt_support = 32'h000000FF; + +parameter sd1__Slot_interrupt_status_Host_controller_version = 32'hE01010FC; +parameter val_sd1__Slot_interrupt_status_Host_controller_version = 32'h89010000; +parameter mask_sd1__Slot_interrupt_status_Host_controller_version = 32'hFFFFFFFF; + + +// ************************************************************ +// Module slcr slcr +// doc version: 1.3, based on 11/18/2010 SLCR_spec.doc +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter slcr__SCL = 32'hF8000000; +parameter val_slcr__SCL = 32'h00000000; +parameter mask_slcr__SCL = 32'hFFFFFFFF; + +parameter slcr__SLCR_LOCK = 32'hF8000004; +parameter val_slcr__SLCR_LOCK = 32'h00000000; +parameter mask_slcr__SLCR_LOCK = 32'hFFFFFFFF; + +parameter slcr__SLCR_UNLOCK = 32'hF8000008; +parameter val_slcr__SLCR_UNLOCK = 32'h00000000; +parameter mask_slcr__SLCR_UNLOCK = 32'hFFFFFFFF; + +parameter slcr__SLCR_LOCKSTA = 32'hF800000C; +parameter val_slcr__SLCR_LOCKSTA = 32'h00000001; +parameter mask_slcr__SLCR_LOCKSTA = 32'hFFFFFFFF; + +parameter slcr__ARM_PLL_CTRL = 32'hF8000100; +parameter val_slcr__ARM_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__ARM_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_PLL_CTRL = 32'hF8000104; +parameter val_slcr__DDR_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__DDR_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__IO_PLL_CTRL = 32'hF8000108; +parameter val_slcr__IO_PLL_CTRL = 32'h0001A008; +parameter mask_slcr__IO_PLL_CTRL = 32'hFFFFFFFF; + +parameter slcr__PLL_STATUS = 32'hF800010C; +parameter val_slcr__PLL_STATUS = 32'h0000003F; +parameter mask_slcr__PLL_STATUS = 32'hFFFFFFFF; + +parameter slcr__ARM_PLL_CFG = 32'hF8000110; +parameter val_slcr__ARM_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__ARM_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__DDR_PLL_CFG = 32'hF8000114; +parameter val_slcr__DDR_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__DDR_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__IO_PLL_CFG = 32'hF8000118; +parameter val_slcr__IO_PLL_CFG = 32'h00177EA0; +parameter mask_slcr__IO_PLL_CFG = 32'hFFFFFFFF; + +parameter slcr__PLL_BG_CTRL = 32'hF800011C; +parameter val_slcr__PLL_BG_CTRL = 32'h00000000; +parameter mask_slcr__PLL_BG_CTRL = 32'hFFFFFFFF; + +parameter slcr__ARM_CLK_CTRL = 32'hF8000120; +parameter val_slcr__ARM_CLK_CTRL = 32'h1F000400; +parameter mask_slcr__ARM_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_CLK_CTRL = 32'hF8000124; +parameter val_slcr__DDR_CLK_CTRL = 32'h18400003; +parameter mask_slcr__DDR_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DCI_CLK_CTRL = 32'hF8000128; +parameter val_slcr__DCI_CLK_CTRL = 32'h01E03201; +parameter mask_slcr__DCI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__APER_CLK_CTRL = 32'hF800012C; +parameter val_slcr__APER_CLK_CTRL = 32'h01FFCCCD; +parameter mask_slcr__APER_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB0_CLK_CTRL = 32'hF8000130; +parameter val_slcr__USB0_CLK_CTRL = 32'h00101941; +parameter mask_slcr__USB0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB1_CLK_CTRL = 32'hF8000134; +parameter val_slcr__USB1_CLK_CTRL = 32'h00101941; +parameter mask_slcr__USB1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM0_RCLK_CTRL = 32'hF8000138; +parameter val_slcr__GEM0_RCLK_CTRL = 32'h00000001; +parameter mask_slcr__GEM0_RCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM1_RCLK_CTRL = 32'hF800013C; +parameter val_slcr__GEM1_RCLK_CTRL = 32'h00000001; +parameter mask_slcr__GEM1_RCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM0_CLK_CTRL = 32'hF8000140; +parameter val_slcr__GEM0_CLK_CTRL = 32'h00003C01; +parameter mask_slcr__GEM0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM1_CLK_CTRL = 32'hF8000144; +parameter val_slcr__GEM1_CLK_CTRL = 32'h00003C01; +parameter mask_slcr__GEM1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SMC_CLK_CTRL = 32'hF8000148; +parameter val_slcr__SMC_CLK_CTRL = 32'h00003C21; +parameter mask_slcr__SMC_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__LQSPI_CLK_CTRL = 32'hF800014C; +parameter val_slcr__LQSPI_CLK_CTRL = 32'h00002821; +parameter mask_slcr__LQSPI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SDIO_CLK_CTRL = 32'hF8000150; +parameter val_slcr__SDIO_CLK_CTRL = 32'h00001E03; +parameter mask_slcr__SDIO_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__UART_CLK_CTRL = 32'hF8000154; +parameter val_slcr__UART_CLK_CTRL = 32'h00003F03; +parameter mask_slcr__UART_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__SPI_CLK_CTRL = 32'hF8000158; +parameter val_slcr__SPI_CLK_CTRL = 32'h00003F03; +parameter mask_slcr__SPI_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_CLK_CTRL = 32'hF800015C; +parameter val_slcr__CAN_CLK_CTRL = 32'h00501903; +parameter mask_slcr__CAN_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_MIOCLK_CTRL = 32'hF8000160; +parameter val_slcr__CAN_MIOCLK_CTRL = 32'h00000000; +parameter mask_slcr__CAN_MIOCLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__DBG_CLK_CTRL = 32'hF8000164; +parameter val_slcr__DBG_CLK_CTRL = 32'h00000F03; +parameter mask_slcr__DBG_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__PCAP_CLK_CTRL = 32'hF8000168; +parameter val_slcr__PCAP_CLK_CTRL = 32'h00000F01; +parameter mask_slcr__PCAP_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__TOPSW_CLK_CTRL = 32'hF800016C; +parameter val_slcr__TOPSW_CLK_CTRL = 32'h00000000; +parameter mask_slcr__TOPSW_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_CLK_CTRL = 32'hF8000170; +parameter val_slcr__FPGA0_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA0_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_CTRL = 32'hF8000174; +parameter val_slcr__FPGA0_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA0_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_CNT = 32'hF8000178; +parameter val_slcr__FPGA0_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA0_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA0_THR_STA = 32'hF800017C; +parameter val_slcr__FPGA0_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA0_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA1_CLK_CTRL = 32'hF8000180; +parameter val_slcr__FPGA1_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA1_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_CTRL = 32'hF8000184; +parameter val_slcr__FPGA1_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA1_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_CNT = 32'hF8000188; +parameter val_slcr__FPGA1_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA1_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA1_THR_STA = 32'hF800018C; +parameter val_slcr__FPGA1_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA1_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA2_CLK_CTRL = 32'hF8000190; +parameter val_slcr__FPGA2_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA2_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_CTRL = 32'hF8000194; +parameter val_slcr__FPGA2_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA2_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_CNT = 32'hF8000198; +parameter val_slcr__FPGA2_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA2_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA2_THR_STA = 32'hF800019C; +parameter val_slcr__FPGA2_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA2_THR_STA = 32'hFFFFFFFF; + +parameter slcr__FPGA3_CLK_CTRL = 32'hF80001A0; +parameter val_slcr__FPGA3_CLK_CTRL = 32'h00101800; +parameter mask_slcr__FPGA3_CLK_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_CTRL = 32'hF80001A4; +parameter val_slcr__FPGA3_THR_CTRL = 32'h00000000; +parameter mask_slcr__FPGA3_THR_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_CNT = 32'hF80001A8; +parameter val_slcr__FPGA3_THR_CNT = 32'h00000000; +parameter mask_slcr__FPGA3_THR_CNT = 32'hFFFFFFFF; + +parameter slcr__FPGA3_THR_STA = 32'hF80001AC; +parameter val_slcr__FPGA3_THR_STA = 32'h00010000; +parameter mask_slcr__FPGA3_THR_STA = 32'hFFFFFFFF; + +parameter slcr__SRST_UART_CTRL = 32'hF80001B0; +parameter val_slcr__SRST_UART_CTRL = 32'h00000000; +parameter mask_slcr__SRST_UART_CTRL = 32'hFFFFFFFF; + +parameter slcr__BANDGAP_TRIM = 32'hF80001B8; +parameter val_slcr__BANDGAP_TRIM = 32'h0000001F; +parameter mask_slcr__BANDGAP_TRIM = 32'hFFFFFFFF; + +parameter slcr__CC_TEST = 32'hF80001BC; +parameter val_slcr__CC_TEST = 32'h00000000; +parameter mask_slcr__CC_TEST = 32'hFFFFFFFF; + +parameter slcr__PLL_PREDIVISOR = 32'hF80001C0; +parameter val_slcr__PLL_PREDIVISOR = 32'h00000001; +parameter mask_slcr__PLL_PREDIVISOR = 32'hFFFFFFFF; + +parameter slcr__CLK_621_TRUE = 32'hF80001C4; +parameter val_slcr__CLK_621_TRUE = 32'h00000001; +parameter mask_slcr__CLK_621_TRUE = 32'hFFFFFFC1; + +parameter slcr__PICTURE_DBG = 32'hF80001D0; +parameter val_slcr__PICTURE_DBG = 32'h00000000; +parameter mask_slcr__PICTURE_DBG = 32'hFFFFFFFF; + +parameter slcr__PICTURE_DBG_UCNT = 32'hF80001D4; +parameter val_slcr__PICTURE_DBG_UCNT = 32'h00000000; +parameter mask_slcr__PICTURE_DBG_UCNT = 32'hFFFFFFFF; + +parameter slcr__PICTURE_DBG_LCNT = 32'hF80001D8; +parameter val_slcr__PICTURE_DBG_LCNT = 32'h00000000; +parameter mask_slcr__PICTURE_DBG_LCNT = 32'hFFFFFFFF; + +parameter slcr__PSS_RST_CTRL = 32'hF8000200; +parameter val_slcr__PSS_RST_CTRL = 32'h00000000; +parameter mask_slcr__PSS_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDR_RST_CTRL = 32'hF8000204; +parameter val_slcr__DDR_RST_CTRL = 32'h00000000; +parameter mask_slcr__DDR_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__TOPSW_RST_CTRL = 32'hF8000208; +parameter val_slcr__TOPSW_RST_CTRL = 32'h00000000; +parameter mask_slcr__TOPSW_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DMAC_RST_CTRL = 32'hF800020C; +parameter val_slcr__DMAC_RST_CTRL = 32'h00000000; +parameter mask_slcr__DMAC_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__USB_RST_CTRL = 32'hF8000210; +parameter val_slcr__USB_RST_CTRL = 32'h00000000; +parameter mask_slcr__USB_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__GEM_RST_CTRL = 32'hF8000214; +parameter val_slcr__GEM_RST_CTRL = 32'h00000000; +parameter mask_slcr__GEM_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SDIO_RST_CTRL = 32'hF8000218; +parameter val_slcr__SDIO_RST_CTRL = 32'h00000000; +parameter mask_slcr__SDIO_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SPI_RST_CTRL = 32'hF800021C; +parameter val_slcr__SPI_RST_CTRL = 32'h00000000; +parameter mask_slcr__SPI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__CAN_RST_CTRL = 32'hF8000220; +parameter val_slcr__CAN_RST_CTRL = 32'h00000000; +parameter mask_slcr__CAN_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__I2C_RST_CTRL = 32'hF8000224; +parameter val_slcr__I2C_RST_CTRL = 32'h00000000; +parameter mask_slcr__I2C_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__UART_RST_CTRL = 32'hF8000228; +parameter val_slcr__UART_RST_CTRL = 32'h00000000; +parameter mask_slcr__UART_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__GPIO_RST_CTRL = 32'hF800022C; +parameter val_slcr__GPIO_RST_CTRL = 32'h00000000; +parameter mask_slcr__GPIO_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__LQSPI_RST_CTRL = 32'hF8000230; +parameter val_slcr__LQSPI_RST_CTRL = 32'h00000000; +parameter mask_slcr__LQSPI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__SMC_RST_CTRL = 32'hF8000234; +parameter val_slcr__SMC_RST_CTRL = 32'h00000000; +parameter mask_slcr__SMC_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__OCM_RST_CTRL = 32'hF8000238; +parameter val_slcr__OCM_RST_CTRL = 32'h00000000; +parameter mask_slcr__OCM_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__DEVCI_RST_CTRL = 32'hF800023C; +parameter val_slcr__DEVCI_RST_CTRL = 32'h00000000; +parameter mask_slcr__DEVCI_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__FPGA_RST_CTRL = 32'hF8000240; +parameter val_slcr__FPGA_RST_CTRL = 32'h01F33F0F; +parameter mask_slcr__FPGA_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__A9_CPU_RST_CTRL = 32'hF8000244; +parameter val_slcr__A9_CPU_RST_CTRL = 32'h00000000; +parameter mask_slcr__A9_CPU_RST_CTRL = 32'hFFFFFFFF; + +parameter slcr__RS_AWDT_CTRL = 32'hF800024C; +parameter val_slcr__RS_AWDT_CTRL = 32'h00000000; +parameter mask_slcr__RS_AWDT_CTRL = 32'hFFFFFFFF; + +parameter slcr__RST_REASON = 32'hF8000250; +parameter val_slcr__RST_REASON = 32'h00000040; +parameter mask_slcr__RST_REASON = 32'hFFFFFFFF; + +parameter slcr__RST_REASON_CLR = 32'hF8000254; +parameter val_slcr__RST_REASON_CLR = 32'h00000000; +parameter mask_slcr__RST_REASON_CLR = 32'hFFFFFFFF; + +parameter slcr__REBOOT_STATUS = 32'hF8000258; +parameter val_slcr__REBOOT_STATUS = 32'h00400000; +parameter mask_slcr__REBOOT_STATUS = 32'hFFFFFFFF; + +parameter slcr__BOOT_MODE = 32'hF800025C; +parameter val_slcr__BOOT_MODE = 32'h00000000; +parameter mask_slcr__BOOT_MODE = 32'hFFFFFFF0; + +parameter slcr__APU_CTRL = 32'hF8000300; +parameter val_slcr__APU_CTRL = 32'h00000000; +parameter mask_slcr__APU_CTRL = 32'hFFFFFFFF; + +parameter slcr__WDT_CLK_SEL = 32'hF8000304; +parameter val_slcr__WDT_CLK_SEL = 32'h00000000; +parameter mask_slcr__WDT_CLK_SEL = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_RAM0 = 32'hF8000400; +parameter val_slcr__TZ_OCM_RAM0 = 32'h00000000; +parameter mask_slcr__TZ_OCM_RAM0 = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_RAM1 = 32'hF8000404; +parameter val_slcr__TZ_OCM_RAM1 = 32'h00000000; +parameter mask_slcr__TZ_OCM_RAM1 = 32'hFFFFFFFF; + +parameter slcr__TZ_OCM_ROM = 32'hF8000408; +parameter val_slcr__TZ_OCM_ROM = 32'h00000000; +parameter mask_slcr__TZ_OCM_ROM = 32'hFFFFFFFF; + +parameter slcr__TZ_DDR_RAM = 32'hF8000430; +parameter val_slcr__TZ_DDR_RAM = 32'h00000000; +parameter mask_slcr__TZ_DDR_RAM = 32'h00000001; + +parameter slcr__TZ_DMA_NS = 32'hF8000440; +parameter val_slcr__TZ_DMA_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_DMA_IRQ_NS = 32'hF8000444; +parameter val_slcr__TZ_DMA_IRQ_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_IRQ_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_DMA_PERIPH_NS = 32'hF8000448; +parameter val_slcr__TZ_DMA_PERIPH_NS = 32'h00000000; +parameter mask_slcr__TZ_DMA_PERIPH_NS = 32'hFFFFFFFF; + +parameter slcr__TZ_GEM = 32'hF8000450; +parameter val_slcr__TZ_GEM = 32'h00000000; +parameter mask_slcr__TZ_GEM = 32'hFFFFFFFF; + +parameter slcr__TZ_SDIO = 32'hF8000454; +parameter val_slcr__TZ_SDIO = 32'h00000000; +parameter mask_slcr__TZ_SDIO = 32'hFFFFFFFF; + +parameter slcr__TZ_USB = 32'hF8000458; +parameter val_slcr__TZ_USB = 32'h00000000; +parameter mask_slcr__TZ_USB = 32'hFFFFFFFF; + +parameter slcr__TZ_FPGA_M = 32'hF8000484; +parameter val_slcr__TZ_FPGA_M = 32'h00000000; +parameter mask_slcr__TZ_FPGA_M = 32'hFFFFFFFF; + +parameter slcr__TZ_FPGA_AFI = 32'hF8000488; +parameter val_slcr__TZ_FPGA_AFI = 32'h00000000; +parameter mask_slcr__TZ_FPGA_AFI = 32'hFFFFFFFF; + +parameter slcr__DBG_CTRL = 32'hF8000500; +parameter val_slcr__DBG_CTRL = 32'h00000000; +parameter mask_slcr__DBG_CTRL = 32'hFFFFFFFF; + +parameter slcr__PSS_IDCODE = 32'hF8000530; +parameter val_slcr__PSS_IDCODE = 32'h03720093; +parameter mask_slcr__PSS_IDCODE = 32'h0FFE0FFF; + +parameter slcr__DDR_URGENT = 32'hF8000600; +parameter val_slcr__DDR_URGENT = 32'h00000000; +parameter mask_slcr__DDR_URGENT = 32'hFFFFFFFF; + +parameter slcr__DDR_CAL_START = 32'hF800060C; +parameter val_slcr__DDR_CAL_START = 32'h00000000; +parameter mask_slcr__DDR_CAL_START = 32'hFFFFFFFF; + +parameter slcr__DDR_REF_START = 32'hF8000614; +parameter val_slcr__DDR_REF_START = 32'h00000000; +parameter mask_slcr__DDR_REF_START = 32'hFFFFFFFF; + +parameter slcr__DDR_CMD_STA = 32'hF8000618; +parameter val_slcr__DDR_CMD_STA = 32'h00000000; +parameter mask_slcr__DDR_CMD_STA = 32'hFFFFFFFF; + +parameter slcr__DDR_URGENT_SEL = 32'hF800061C; +parameter val_slcr__DDR_URGENT_SEL = 32'h00000000; +parameter mask_slcr__DDR_URGENT_SEL = 32'hFFFFFFFF; + +parameter slcr__DDR_DFI_STATUS = 32'hF8000620; +parameter val_slcr__DDR_DFI_STATUS = 32'h00000000; +parameter mask_slcr__DDR_DFI_STATUS = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_00 = 32'hF8000700; +parameter val_slcr__MIO_PIN_00 = 32'h00001601; +parameter mask_slcr__MIO_PIN_00 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_01 = 32'hF8000704; +parameter val_slcr__MIO_PIN_01 = 32'h00001601; +parameter mask_slcr__MIO_PIN_01 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_02 = 32'hF8000708; +parameter val_slcr__MIO_PIN_02 = 32'h00000601; +parameter mask_slcr__MIO_PIN_02 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_03 = 32'hF800070C; +parameter val_slcr__MIO_PIN_03 = 32'h00000601; +parameter mask_slcr__MIO_PIN_03 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_04 = 32'hF8000710; +parameter val_slcr__MIO_PIN_04 = 32'h00000601; +parameter mask_slcr__MIO_PIN_04 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_05 = 32'hF8000714; +parameter val_slcr__MIO_PIN_05 = 32'h00000601; +parameter mask_slcr__MIO_PIN_05 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_06 = 32'hF8000718; +parameter val_slcr__MIO_PIN_06 = 32'h00000601; +parameter mask_slcr__MIO_PIN_06 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_07 = 32'hF800071C; +parameter val_slcr__MIO_PIN_07 = 32'h00000601; +parameter mask_slcr__MIO_PIN_07 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_08 = 32'hF8000720; +parameter val_slcr__MIO_PIN_08 = 32'h00000601; +parameter mask_slcr__MIO_PIN_08 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_09 = 32'hF8000724; +parameter val_slcr__MIO_PIN_09 = 32'h00001601; +parameter mask_slcr__MIO_PIN_09 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_10 = 32'hF8000728; +parameter val_slcr__MIO_PIN_10 = 32'h00001601; +parameter mask_slcr__MIO_PIN_10 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_11 = 32'hF800072C; +parameter val_slcr__MIO_PIN_11 = 32'h00001601; +parameter mask_slcr__MIO_PIN_11 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_12 = 32'hF8000730; +parameter val_slcr__MIO_PIN_12 = 32'h00001601; +parameter mask_slcr__MIO_PIN_12 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_13 = 32'hF8000734; +parameter val_slcr__MIO_PIN_13 = 32'h00001601; +parameter mask_slcr__MIO_PIN_13 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_14 = 32'hF8000738; +parameter val_slcr__MIO_PIN_14 = 32'h00001601; +parameter mask_slcr__MIO_PIN_14 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_15 = 32'hF800073C; +parameter val_slcr__MIO_PIN_15 = 32'h00001601; +parameter mask_slcr__MIO_PIN_15 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_16 = 32'hF8000740; +parameter val_slcr__MIO_PIN_16 = 32'h00001601; +parameter mask_slcr__MIO_PIN_16 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_17 = 32'hF8000744; +parameter val_slcr__MIO_PIN_17 = 32'h00001601; +parameter mask_slcr__MIO_PIN_17 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_18 = 32'hF8000748; +parameter val_slcr__MIO_PIN_18 = 32'h00001601; +parameter mask_slcr__MIO_PIN_18 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_19 = 32'hF800074C; +parameter val_slcr__MIO_PIN_19 = 32'h00001601; +parameter mask_slcr__MIO_PIN_19 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_20 = 32'hF8000750; +parameter val_slcr__MIO_PIN_20 = 32'h00001601; +parameter mask_slcr__MIO_PIN_20 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_21 = 32'hF8000754; +parameter val_slcr__MIO_PIN_21 = 32'h00001601; +parameter mask_slcr__MIO_PIN_21 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_22 = 32'hF8000758; +parameter val_slcr__MIO_PIN_22 = 32'h00001601; +parameter mask_slcr__MIO_PIN_22 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_23 = 32'hF800075C; +parameter val_slcr__MIO_PIN_23 = 32'h00001601; +parameter mask_slcr__MIO_PIN_23 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_24 = 32'hF8000760; +parameter val_slcr__MIO_PIN_24 = 32'h00001601; +parameter mask_slcr__MIO_PIN_24 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_25 = 32'hF8000764; +parameter val_slcr__MIO_PIN_25 = 32'h00001601; +parameter mask_slcr__MIO_PIN_25 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_26 = 32'hF8000768; +parameter val_slcr__MIO_PIN_26 = 32'h00001601; +parameter mask_slcr__MIO_PIN_26 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_27 = 32'hF800076C; +parameter val_slcr__MIO_PIN_27 = 32'h00001601; +parameter mask_slcr__MIO_PIN_27 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_28 = 32'hF8000770; +parameter val_slcr__MIO_PIN_28 = 32'h00001601; +parameter mask_slcr__MIO_PIN_28 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_29 = 32'hF8000774; +parameter val_slcr__MIO_PIN_29 = 32'h00001601; +parameter mask_slcr__MIO_PIN_29 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_30 = 32'hF8000778; +parameter val_slcr__MIO_PIN_30 = 32'h00001601; +parameter mask_slcr__MIO_PIN_30 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_31 = 32'hF800077C; +parameter val_slcr__MIO_PIN_31 = 32'h00001601; +parameter mask_slcr__MIO_PIN_31 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_32 = 32'hF8000780; +parameter val_slcr__MIO_PIN_32 = 32'h00001601; +parameter mask_slcr__MIO_PIN_32 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_33 = 32'hF8000784; +parameter val_slcr__MIO_PIN_33 = 32'h00001601; +parameter mask_slcr__MIO_PIN_33 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_34 = 32'hF8000788; +parameter val_slcr__MIO_PIN_34 = 32'h00001601; +parameter mask_slcr__MIO_PIN_34 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_35 = 32'hF800078C; +parameter val_slcr__MIO_PIN_35 = 32'h00001601; +parameter mask_slcr__MIO_PIN_35 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_36 = 32'hF8000790; +parameter val_slcr__MIO_PIN_36 = 32'h00001601; +parameter mask_slcr__MIO_PIN_36 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_37 = 32'hF8000794; +parameter val_slcr__MIO_PIN_37 = 32'h00001601; +parameter mask_slcr__MIO_PIN_37 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_38 = 32'hF8000798; +parameter val_slcr__MIO_PIN_38 = 32'h00001601; +parameter mask_slcr__MIO_PIN_38 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_39 = 32'hF800079C; +parameter val_slcr__MIO_PIN_39 = 32'h00001601; +parameter mask_slcr__MIO_PIN_39 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_40 = 32'hF80007A0; +parameter val_slcr__MIO_PIN_40 = 32'h00001601; +parameter mask_slcr__MIO_PIN_40 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_41 = 32'hF80007A4; +parameter val_slcr__MIO_PIN_41 = 32'h00001601; +parameter mask_slcr__MIO_PIN_41 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_42 = 32'hF80007A8; +parameter val_slcr__MIO_PIN_42 = 32'h00001601; +parameter mask_slcr__MIO_PIN_42 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_43 = 32'hF80007AC; +parameter val_slcr__MIO_PIN_43 = 32'h00001601; +parameter mask_slcr__MIO_PIN_43 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_44 = 32'hF80007B0; +parameter val_slcr__MIO_PIN_44 = 32'h00001601; +parameter mask_slcr__MIO_PIN_44 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_45 = 32'hF80007B4; +parameter val_slcr__MIO_PIN_45 = 32'h00001601; +parameter mask_slcr__MIO_PIN_45 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_46 = 32'hF80007B8; +parameter val_slcr__MIO_PIN_46 = 32'h00001601; +parameter mask_slcr__MIO_PIN_46 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_47 = 32'hF80007BC; +parameter val_slcr__MIO_PIN_47 = 32'h00001601; +parameter mask_slcr__MIO_PIN_47 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_48 = 32'hF80007C0; +parameter val_slcr__MIO_PIN_48 = 32'h00001601; +parameter mask_slcr__MIO_PIN_48 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_49 = 32'hF80007C4; +parameter val_slcr__MIO_PIN_49 = 32'h00001601; +parameter mask_slcr__MIO_PIN_49 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_50 = 32'hF80007C8; +parameter val_slcr__MIO_PIN_50 = 32'h00001601; +parameter mask_slcr__MIO_PIN_50 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_51 = 32'hF80007CC; +parameter val_slcr__MIO_PIN_51 = 32'h00001601; +parameter mask_slcr__MIO_PIN_51 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_52 = 32'hF80007D0; +parameter val_slcr__MIO_PIN_52 = 32'h00001601; +parameter mask_slcr__MIO_PIN_52 = 32'hFFFFFFFF; + +parameter slcr__MIO_PIN_53 = 32'hF80007D4; +parameter val_slcr__MIO_PIN_53 = 32'h00001601; +parameter mask_slcr__MIO_PIN_53 = 32'hFFFFFFFF; + +parameter slcr__MIO_FMIO_GEM_SEL = 32'hF8000800; +parameter val_slcr__MIO_FMIO_GEM_SEL = 32'h00000000; +parameter mask_slcr__MIO_FMIO_GEM_SEL = 32'hFFFFFFFF; + +parameter slcr__MIO_LOOPBACK = 32'hF8000804; +parameter val_slcr__MIO_LOOPBACK = 32'h00000000; +parameter mask_slcr__MIO_LOOPBACK = 32'hFFFFFFFF; + +parameter slcr__MIO_MST_TRI0 = 32'hF800080C; +parameter val_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; +parameter mask_slcr__MIO_MST_TRI0 = 32'hFFFFFFFF; + +parameter slcr__MIO_MST_TRI1 = 32'hF8000810; +parameter val_slcr__MIO_MST_TRI1 = 32'h003FFFFF; +parameter mask_slcr__MIO_MST_TRI1 = 32'hFFFFFFFF; + +parameter slcr__SD0_WP_CD_SEL = 32'hF8000830; +parameter val_slcr__SD0_WP_CD_SEL = 32'h00000000; +parameter mask_slcr__SD0_WP_CD_SEL = 32'hFFFFFFFF; + +parameter slcr__SD1_WP_CD_SEL = 32'hF8000834; +parameter val_slcr__SD1_WP_CD_SEL = 32'h00000000; +parameter mask_slcr__SD1_WP_CD_SEL = 32'hFFFFFFFF; + +parameter slcr__LVL_SHFTR_EN = 32'hF8000900; +parameter val_slcr__LVL_SHFTR_EN = 32'h00000000; +parameter mask_slcr__LVL_SHFTR_EN = 32'hFFFFFFFF; + +parameter slcr__OCM_CFG = 32'hF8000910; +parameter val_slcr__OCM_CFG = 32'h00000000; +parameter mask_slcr__OCM_CFG = 32'hFFFFFFFF; + +parameter slcr__CPU0_RAM0 = 32'hF8000A00; +parameter val_slcr__CPU0_RAM0 = 32'h00020202; +parameter mask_slcr__CPU0_RAM0 = 32'h00FFFFFF; + +parameter slcr__CPU0_RAM1 = 32'hF8000A04; +parameter val_slcr__CPU0_RAM1 = 32'h00020202; +parameter mask_slcr__CPU0_RAM1 = 32'h00FFFFFF; + +parameter slcr__CPU0_RAM2 = 32'hF8000A08; +parameter val_slcr__CPU0_RAM2 = 32'h02020202; +parameter mask_slcr__CPU0_RAM2 = 32'hFFFFFFFF; + +parameter slcr__CPU1_RAM0 = 32'hF8000A0C; +parameter val_slcr__CPU1_RAM0 = 32'h00020202; +parameter mask_slcr__CPU1_RAM0 = 32'h00FFFFFF; + +parameter slcr__CPU1_RAM1 = 32'hF8000A10; +parameter val_slcr__CPU1_RAM1 = 32'h00020202; +parameter mask_slcr__CPU1_RAM1 = 32'h00FFFFFF; + +parameter slcr__CPU1_RAM2 = 32'hF8000A14; +parameter val_slcr__CPU1_RAM2 = 32'h02020202; +parameter mask_slcr__CPU1_RAM2 = 32'hFFFFFFFF; + +parameter slcr__SCU_RAM = 32'hF8000A18; +parameter val_slcr__SCU_RAM = 32'h00000002; +parameter mask_slcr__SCU_RAM = 32'h000000FF; + +parameter slcr__L2C_RAM = 32'hF8000A1C; +parameter val_slcr__L2C_RAM = 32'h00020202; +parameter mask_slcr__L2C_RAM = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_GEM01 = 32'hF8000A30; +parameter val_slcr__IOU_RAM_GEM01 = 32'h09090909; +parameter mask_slcr__IOU_RAM_GEM01 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_USB01 = 32'hF8000A34; +parameter val_slcr__IOU_RAM_USB01 = 32'h09090909; +parameter mask_slcr__IOU_RAM_USB01 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_SDIO0 = 32'hF8000A38; +parameter val_slcr__IOU_RAM_SDIO0 = 32'h09090909; +parameter mask_slcr__IOU_RAM_SDIO0 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_SDIO1 = 32'hF8000A3C; +parameter val_slcr__IOU_RAM_SDIO1 = 32'h09090909; +parameter mask_slcr__IOU_RAM_SDIO1 = 32'hFFFFFFFF; + +parameter slcr__IOU_RAM_CAN0 = 32'hF8000A40; +parameter val_slcr__IOU_RAM_CAN0 = 32'h00090909; +parameter mask_slcr__IOU_RAM_CAN0 = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_CAN1 = 32'hF8000A44; +parameter val_slcr__IOU_RAM_CAN1 = 32'h00090909; +parameter mask_slcr__IOU_RAM_CAN1 = 32'h00FFFFFF; + +parameter slcr__IOU_RAM_LQSPI = 32'hF8000A48; +parameter val_slcr__IOU_RAM_LQSPI = 32'h00000909; +parameter mask_slcr__IOU_RAM_LQSPI = 32'h0000FFFF; + +parameter slcr__DMAC_RAM = 32'hF8000A50; +parameter val_slcr__DMAC_RAM = 32'h00000009; +parameter mask_slcr__DMAC_RAM = 32'h000000FF; + +parameter slcr__AFI0_RAM0 = 32'hF8000A60; +parameter val_slcr__AFI0_RAM0 = 32'h09090909; +parameter mask_slcr__AFI0_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI0_RAM1 = 32'hF8000A64; +parameter val_slcr__AFI0_RAM1 = 32'h09090909; +parameter mask_slcr__AFI0_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI0_RAM2 = 32'hF8000A68; +parameter val_slcr__AFI0_RAM2 = 32'h00000909; +parameter mask_slcr__AFI0_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI1_RAM0 = 32'hF8000A6C; +parameter val_slcr__AFI1_RAM0 = 32'h09090909; +parameter mask_slcr__AFI1_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI1_RAM1 = 32'hF8000A70; +parameter val_slcr__AFI1_RAM1 = 32'h09090909; +parameter mask_slcr__AFI1_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI1_RAM2 = 32'hF8000A74; +parameter val_slcr__AFI1_RAM2 = 32'h00000909; +parameter mask_slcr__AFI1_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI2_RAM0 = 32'hF8000A78; +parameter val_slcr__AFI2_RAM0 = 32'h09090909; +parameter mask_slcr__AFI2_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI2_RAM1 = 32'hF8000A7C; +parameter val_slcr__AFI2_RAM1 = 32'h09090909; +parameter mask_slcr__AFI2_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI2_RAM2 = 32'hF8000A80; +parameter val_slcr__AFI2_RAM2 = 32'h00000909; +parameter mask_slcr__AFI2_RAM2 = 32'h0000FFFF; + +parameter slcr__AFI3_RAM0 = 32'hF8000A84; +parameter val_slcr__AFI3_RAM0 = 32'h09090909; +parameter mask_slcr__AFI3_RAM0 = 32'hFFFFFFFF; + +parameter slcr__AFI3_RAM1 = 32'hF8000A88; +parameter val_slcr__AFI3_RAM1 = 32'h09090909; +parameter mask_slcr__AFI3_RAM1 = 32'hFFFFFFFF; + +parameter slcr__AFI3_RAM2 = 32'hF8000A8C; +parameter val_slcr__AFI3_RAM2 = 32'h00000909; +parameter mask_slcr__AFI3_RAM2 = 32'h0000FFFF; + +parameter slcr__OCM_RAM = 32'hF8000A90; +parameter val_slcr__OCM_RAM = 32'h01010101; +parameter mask_slcr__OCM_RAM = 32'hFFFFFFFF; + +parameter slcr__OCM_ROM0 = 32'hF8000A94; +parameter val_slcr__OCM_ROM0 = 32'h09090909; +parameter mask_slcr__OCM_ROM0 = 32'hFFFFFFFF; + +parameter slcr__OCM_ROM1 = 32'hF8000A98; +parameter val_slcr__OCM_ROM1 = 32'h09090909; +parameter mask_slcr__OCM_ROM1 = 32'hFFFFFFFF; + +parameter slcr__DEVCI_RAM = 32'hF8000AA0; +parameter val_slcr__DEVCI_RAM = 32'h00000909; +parameter mask_slcr__DEVCI_RAM = 32'h0000FFFF; + +parameter slcr__CSG_RAM = 32'hF8000AB0; +parameter val_slcr__CSG_RAM = 32'h00000001; +parameter mask_slcr__CSG_RAM = 32'h000000FF; + +parameter slcr__GPIOB_CTRL = 32'hF8000B00; +parameter val_slcr__GPIOB_CTRL = 32'h00000000; +parameter mask_slcr__GPIOB_CTRL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS18 = 32'hF8000B04; +parameter val_slcr__GPIOB_CFG_CMOS18 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS18 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS25 = 32'hF8000B08; +parameter val_slcr__GPIOB_CFG_CMOS25 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS25 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_CMOS33 = 32'hF8000B0C; +parameter val_slcr__GPIOB_CFG_CMOS33 = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_CMOS33 = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_LVTTL = 32'hF8000B10; +parameter val_slcr__GPIOB_CFG_LVTTL = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_LVTTL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_CFG_HSTL = 32'hF8000B14; +parameter val_slcr__GPIOB_CFG_HSTL = 32'h00000000; +parameter mask_slcr__GPIOB_CFG_HSTL = 32'hFFFFFFFF; + +parameter slcr__GPIOB_DRVR_BIAS_CTRL = 32'hF8000B18; +parameter val_slcr__GPIOB_DRVR_BIAS_CTRL = 32'h00000000; +parameter mask_slcr__GPIOB_DRVR_BIAS_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_ADDR0 = 32'hF8000B40; +parameter val_slcr__DDRIOB_ADDR0 = 32'h00000800; +parameter mask_slcr__DDRIOB_ADDR0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_ADDR1 = 32'hF8000B44; +parameter val_slcr__DDRIOB_ADDR1 = 32'h00000800; +parameter mask_slcr__DDRIOB_ADDR1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DATA0 = 32'hF8000B48; +parameter val_slcr__DDRIOB_DATA0 = 32'h00000800; +parameter mask_slcr__DDRIOB_DATA0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DATA1 = 32'hF8000B4C; +parameter val_slcr__DDRIOB_DATA1 = 32'h00000800; +parameter mask_slcr__DDRIOB_DATA1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DIFF0 = 32'hF8000B50; +parameter val_slcr__DDRIOB_DIFF0 = 32'h00000800; +parameter mask_slcr__DDRIOB_DIFF0 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DIFF1 = 32'hF8000B54; +parameter val_slcr__DDRIOB_DIFF1 = 32'h00000800; +parameter mask_slcr__DDRIOB_DIFF1 = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_CLOCK = 32'hF8000B58; +parameter val_slcr__DDRIOB_CLOCK = 32'h00000800; +parameter mask_slcr__DDRIOB_CLOCK = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hF8000B5C; +parameter val_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_ADDR = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hF8000B60; +parameter val_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_DATA = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hF8000B64; +parameter val_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_DIFF = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hF8000B68; +parameter val_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'h00000000; +parameter mask_slcr__DDRIOB_DRIVE_SLEW_CLOCK = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DDR_CTRL = 32'hF8000B6C; +parameter val_slcr__DDRIOB_DDR_CTRL = 32'h00000000; +parameter mask_slcr__DDRIOB_DDR_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DCI_CTRL = 32'hF8000B70; +parameter val_slcr__DDRIOB_DCI_CTRL = 32'h00000020; +parameter mask_slcr__DDRIOB_DCI_CTRL = 32'hFFFFFFFF; + +parameter slcr__DDRIOB_DCI_STATUS = 32'hF8000B74; +parameter val_slcr__DDRIOB_DCI_STATUS = 32'h00000000; +parameter mask_slcr__DDRIOB_DCI_STATUS = 32'hFFFFFFFF; + + +// ************************************************************ +// Module smcc pl353 +// doc version: 1.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter smcc__memc_status = 32'hE000E000; +parameter val_smcc__memc_status = 32'h00000000; +parameter mask_smcc__memc_status = 32'h00001FFF; + +parameter smcc__memif_cfg = 32'hE000E004; +parameter val_smcc__memif_cfg = 32'h00011205; +parameter mask_smcc__memif_cfg = 32'h0003FFFF; + +parameter smcc__memc_cfg_set = 32'hE000E008; +parameter val_smcc__memc_cfg_set = 32'h00000000; +parameter mask_smcc__memc_cfg_set = 32'h00000000; + +parameter smcc__memc_cfg_clr = 32'hE000E00C; +parameter val_smcc__memc_cfg_clr = 32'h00000000; +parameter mask_smcc__memc_cfg_clr = 32'h00000000; + +parameter smcc__direct_cmd = 32'hE000E010; +parameter val_smcc__direct_cmd = 32'h00000000; +parameter mask_smcc__direct_cmd = 32'h00000000; + +parameter smcc__set_cycles = 32'hE000E014; +parameter val_smcc__set_cycles = 32'h00000000; +parameter mask_smcc__set_cycles = 32'h00000000; + +parameter smcc__set_opmode = 32'hE000E018; +parameter val_smcc__set_opmode = 32'h00000000; +parameter mask_smcc__set_opmode = 32'h00000000; + +parameter smcc__refresh_period_0 = 32'hE000E020; +parameter val_smcc__refresh_period_0 = 32'h00000000; +parameter mask_smcc__refresh_period_0 = 32'h0000000F; + +parameter smcc__refresh_period_1 = 32'hE000E024; +parameter val_smcc__refresh_period_1 = 32'h00000000; +parameter mask_smcc__refresh_period_1 = 32'h0000000F; + +parameter smcc__sram_cycles0_0 = 32'hE000E100; +parameter val_smcc__sram_cycles0_0 = 32'h0002B3CC; +parameter mask_smcc__sram_cycles0_0 = 32'h001FFFFF; + +parameter smcc__opmode0_0 = 32'hE000E104; +parameter val_smcc__opmode0_0 = 32'hE2FE0800; +parameter mask_smcc__opmode0_0 = 32'hFFFFFFFF; + +parameter smcc__sram_cycles0_1 = 32'hE000E120; +parameter val_smcc__sram_cycles0_1 = 32'h0002B3CC; +parameter mask_smcc__sram_cycles0_1 = 32'h001FFFFF; + +parameter smcc__opmode0_1 = 32'hE000E124; +parameter val_smcc__opmode0_1 = 32'hE4FE0800; +parameter mask_smcc__opmode0_1 = 32'hFFFFFFFF; + +parameter smcc__nand_cycles1_0 = 32'hE000E180; +parameter val_smcc__nand_cycles1_0 = 32'h0024ABCC; +parameter mask_smcc__nand_cycles1_0 = 32'h00FFFFFF; + +parameter smcc__opmode1_0 = 32'hE000E184; +parameter val_smcc__opmode1_0 = 32'hE1FF0001; +parameter mask_smcc__opmode1_0 = 32'hFFFFFFFF; + +parameter smcc__user_status = 32'hE000E200; +parameter val_smcc__user_status = 32'h00000000; +parameter mask_smcc__user_status = 32'h000000FF; + +parameter smcc__user_config = 32'hE000E204; +parameter val_smcc__user_config = 32'h00000000; +parameter mask_smcc__user_config = 32'h00000000; + +parameter smcc__ecc_status_0 = 32'hE000E300; +parameter val_smcc__ecc_status_0 = 32'h00000000; +parameter mask_smcc__ecc_status_0 = 32'h3FFFFFFF; + +parameter smcc__ecc_memcfg_0 = 32'hE000E304; +parameter val_smcc__ecc_memcfg_0 = 32'h00000000; +parameter mask_smcc__ecc_memcfg_0 = 32'h00001FFF; + +parameter smcc__ecc_memcommand1_0 = 32'hE000E308; +parameter val_smcc__ecc_memcommand1_0 = 32'h00000000; +parameter mask_smcc__ecc_memcommand1_0 = 32'h01FFFFFF; + +parameter smcc__ecc_memcommand2_0 = 32'hE000E30C; +parameter val_smcc__ecc_memcommand2_0 = 32'h00000000; +parameter mask_smcc__ecc_memcommand2_0 = 32'h01FFFFFF; + +parameter smcc__ecc_addr0_0 = 32'hE000E310; +parameter val_smcc__ecc_addr0_0 = 32'h00000000; +parameter mask_smcc__ecc_addr0_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_addr1_0 = 32'hE000E314; +parameter val_smcc__ecc_addr1_0 = 32'h00000000; +parameter mask_smcc__ecc_addr1_0 = 32'h00FFFFFF; + +parameter smcc__ecc_value0_0 = 32'hE000E318; +parameter val_smcc__ecc_value0_0 = 32'h00000000; +parameter mask_smcc__ecc_value0_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value1_0 = 32'hE000E31C; +parameter val_smcc__ecc_value1_0 = 32'h00000000; +parameter mask_smcc__ecc_value1_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value2_0 = 32'hE000E320; +parameter val_smcc__ecc_value2_0 = 32'h00000000; +parameter mask_smcc__ecc_value2_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_value3_0 = 32'hE000E324; +parameter val_smcc__ecc_value3_0 = 32'h00000000; +parameter mask_smcc__ecc_value3_0 = 32'hFFFFFFFF; + +parameter smcc__ecc_status_1 = 32'hE000E400; +parameter val_smcc__ecc_status_1 = 32'h00000000; +parameter mask_smcc__ecc_status_1 = 32'h3FFFFFFF; + +parameter smcc__ecc_memcfg_1 = 32'hE000E404; +parameter val_smcc__ecc_memcfg_1 = 32'h00000043; +parameter mask_smcc__ecc_memcfg_1 = 32'h00001FFF; + +parameter smcc__ecc_memcommand1_1 = 32'hE000E408; +parameter val_smcc__ecc_memcommand1_1 = 32'h01300080; +parameter mask_smcc__ecc_memcommand1_1 = 32'h01FFFFFF; + +parameter smcc__ecc_memcommand2_1 = 32'hE000E40C; +parameter val_smcc__ecc_memcommand2_1 = 32'h01E00585; +parameter mask_smcc__ecc_memcommand2_1 = 32'h01FFFFFF; + +parameter smcc__ecc_addr0_1 = 32'hE000E410; +parameter val_smcc__ecc_addr0_1 = 32'h00000000; +parameter mask_smcc__ecc_addr0_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_addr1_1 = 32'hE000E414; +parameter val_smcc__ecc_addr1_1 = 32'h00000000; +parameter mask_smcc__ecc_addr1_1 = 32'h00FFFFFF; + +parameter smcc__ecc_value0_1 = 32'hE000E418; +parameter val_smcc__ecc_value0_1 = 32'h00000000; +parameter mask_smcc__ecc_value0_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value1_1 = 32'hE000E41C; +parameter val_smcc__ecc_value1_1 = 32'h00000000; +parameter mask_smcc__ecc_value1_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value2_1 = 32'hE000E420; +parameter val_smcc__ecc_value2_1 = 32'h00000000; +parameter mask_smcc__ecc_value2_1 = 32'hFFFFFFFF; + +parameter smcc__ecc_value3_1 = 32'hE000E424; +parameter val_smcc__ecc_value3_1 = 32'h00000000; +parameter mask_smcc__ecc_value3_1 = 32'hFFFFFFFF; + +parameter smcc__integration_test = 32'hE000EE00; +parameter val_smcc__integration_test = 32'h00000000; +parameter mask_smcc__integration_test = 32'hFFFFFFFF; + +parameter smcc__periph_id_0 = 32'hE000EFE0; +parameter val_smcc__periph_id_0 = 32'h00000053; +parameter mask_smcc__periph_id_0 = 32'h000000FF; + +parameter smcc__periph_id_1 = 32'hE000EFE4; +parameter val_smcc__periph_id_1 = 32'h00000013; +parameter mask_smcc__periph_id_1 = 32'h000000FF; + +parameter smcc__periph_id_2 = 32'hE000EFE8; +parameter val_smcc__periph_id_2 = 32'h00000054; +parameter mask_smcc__periph_id_2 = 32'h000000FF; + +parameter smcc__periph_id_3 = 32'hE000EFEC; +parameter val_smcc__periph_id_3 = 32'h00000000; +parameter mask_smcc__periph_id_3 = 32'h00000001; + +parameter smcc__pcell_id_0 = 32'hE000EFF0; +parameter val_smcc__pcell_id_0 = 32'h0000000D; +parameter mask_smcc__pcell_id_0 = 32'h000000FF; + +parameter smcc__pcell_id_1 = 32'hE000EFF4; +parameter val_smcc__pcell_id_1 = 32'h000000F0; +parameter mask_smcc__pcell_id_1 = 32'h000000FF; + +parameter smcc__pcell_id_2 = 32'hE000EFF8; +parameter val_smcc__pcell_id_2 = 32'h00000005; +parameter mask_smcc__pcell_id_2 = 32'h000000FF; + +parameter smcc__pcell_id_3 = 32'hE000EFFC; +parameter val_smcc__pcell_id_3 = 32'h000000B1; +parameter mask_smcc__pcell_id_3 = 32'h000000FF; + + +// ************************************************************ +// Module spi0 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter spi0__Config_reg0 = 32'hE0006000; +parameter val_spi0__Config_reg0 = 32'h00020000; +parameter mask_spi0__Config_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intr_status_reg0 = 32'hE0006004; +parameter val_spi0__Intr_status_reg0 = 32'h00000004; +parameter mask_spi0__Intr_status_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_en_reg0 = 32'hE0006008; +parameter val_spi0__Intrpt_en_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_dis_reg0 = 32'hE000600C; +parameter val_spi0__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter spi0__Intrpt_mask_reg0 = 32'hE0006010; +parameter val_spi0__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_spi0__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter spi0__En_reg0 = 32'hE0006014; +parameter val_spi0__En_reg0 = 32'h00000000; +parameter mask_spi0__En_reg0 = 32'hFFFFFFFF; + +parameter spi0__Delay_reg0 = 32'hE0006018; +parameter val_spi0__Delay_reg0 = 32'h00000000; +parameter mask_spi0__Delay_reg0 = 32'hFFFFFFFF; + +parameter spi0__Tx_data_reg0 = 32'hE000601C; +parameter val_spi0__Tx_data_reg0 = 32'h00000000; +parameter mask_spi0__Tx_data_reg0 = 32'hFFFFFFFF; + +parameter spi0__Rx_data_reg0 = 32'hE0006020; +parameter val_spi0__Rx_data_reg0 = 32'h00000000; +parameter mask_spi0__Rx_data_reg0 = 32'hFFFFFFFF; + +parameter spi0__Slave_Idle_count_reg0 = 32'hE0006024; +parameter val_spi0__Slave_Idle_count_reg0 = 32'h000000FF; +parameter mask_spi0__Slave_Idle_count_reg0 = 32'hFFFFFFFF; + +parameter spi0__TX_thres_reg0 = 32'hE0006028; +parameter val_spi0__TX_thres_reg0 = 32'h00000001; +parameter mask_spi0__TX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi0__RX_thres_reg0 = 32'hE000602C; +parameter val_spi0__RX_thres_reg0 = 32'h00000001; +parameter mask_spi0__RX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi0__Mod_id_reg0 = 32'hE00060FC; +parameter val_spi0__Mod_id_reg0 = 32'h00090106; +parameter mask_spi0__Mod_id_reg0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module spi1 SPI +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter spi1__Config_reg0 = 32'hE0007000; +parameter val_spi1__Config_reg0 = 32'h00020000; +parameter mask_spi1__Config_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intr_status_reg0 = 32'hE0007004; +parameter val_spi1__Intr_status_reg0 = 32'h00000004; +parameter mask_spi1__Intr_status_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_en_reg0 = 32'hE0007008; +parameter val_spi1__Intrpt_en_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_dis_reg0 = 32'hE000700C; +parameter val_spi1__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter spi1__Intrpt_mask_reg0 = 32'hE0007010; +parameter val_spi1__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_spi1__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter spi1__En_reg0 = 32'hE0007014; +parameter val_spi1__En_reg0 = 32'h00000000; +parameter mask_spi1__En_reg0 = 32'hFFFFFFFF; + +parameter spi1__Delay_reg0 = 32'hE0007018; +parameter val_spi1__Delay_reg0 = 32'h00000000; +parameter mask_spi1__Delay_reg0 = 32'hFFFFFFFF; + +parameter spi1__Tx_data_reg0 = 32'hE000701C; +parameter val_spi1__Tx_data_reg0 = 32'h00000000; +parameter mask_spi1__Tx_data_reg0 = 32'hFFFFFFFF; + +parameter spi1__Rx_data_reg0 = 32'hE0007020; +parameter val_spi1__Rx_data_reg0 = 32'h00000000; +parameter mask_spi1__Rx_data_reg0 = 32'hFFFFFFFF; + +parameter spi1__Slave_Idle_count_reg0 = 32'hE0007024; +parameter val_spi1__Slave_Idle_count_reg0 = 32'h000000FF; +parameter mask_spi1__Slave_Idle_count_reg0 = 32'hFFFFFFFF; + +parameter spi1__TX_thres_reg0 = 32'hE0007028; +parameter val_spi1__TX_thres_reg0 = 32'h00000001; +parameter mask_spi1__TX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi1__RX_thres_reg0 = 32'hE000702C; +parameter val_spi1__RX_thres_reg0 = 32'h00000001; +parameter mask_spi1__RX_thres_reg0 = 32'hFFFFFFFF; + +parameter spi1__Mod_id_reg0 = 32'hE00070FC; +parameter val_spi1__Mod_id_reg0 = 32'h00090106; +parameter mask_spi1__Mod_id_reg0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module swdt swdt +// doc version: 2.1 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter swdt__MODE = 32'hF8005000; +parameter val_swdt__MODE = 32'h000001C2; +parameter mask_swdt__MODE = 32'h00FFFFFF; + +parameter swdt__CONTROL = 32'hF8005004; +parameter val_swdt__CONTROL = 32'h03FFC3FC; +parameter mask_swdt__CONTROL = 32'h03FFFFFF; + +parameter swdt__RESTART = 32'hF8005008; +parameter val_swdt__RESTART = 32'h00000000; +parameter mask_swdt__RESTART = 32'h0000FFFF; + +parameter swdt__STATUS = 32'hF800500C; +parameter val_swdt__STATUS = 32'h00000000; +parameter mask_swdt__STATUS = 32'h00000001; + + +// ************************************************************ +// Module ttc0 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ttc0__Clock_Control_1 = 32'hF8001000; +parameter val_ttc0__Clock_Control_1 = 32'h00000000; +parameter mask_ttc0__Clock_Control_1 = 32'h0000007F; + +parameter ttc0__Clock_Control_2 = 32'hF8001004; +parameter val_ttc0__Clock_Control_2 = 32'h00000000; +parameter mask_ttc0__Clock_Control_2 = 32'h0000007F; + +parameter ttc0__Clock_Control_3 = 32'hF8001008; +parameter val_ttc0__Clock_Control_3 = 32'h00000000; +parameter mask_ttc0__Clock_Control_3 = 32'h0000007F; + +parameter ttc0__Counter_Control_1 = 32'hF800100C; +parameter val_ttc0__Counter_Control_1 = 32'h00000021; +parameter mask_ttc0__Counter_Control_1 = 32'h0000007F; + +parameter ttc0__Counter_Control_2 = 32'hF8001010; +parameter val_ttc0__Counter_Control_2 = 32'h00000021; +parameter mask_ttc0__Counter_Control_2 = 32'h0000007F; + +parameter ttc0__Counter_Control_3 = 32'hF8001014; +parameter val_ttc0__Counter_Control_3 = 32'h00000021; +parameter mask_ttc0__Counter_Control_3 = 32'h0000007F; + +parameter ttc0__Counter_Value_1 = 32'hF8001018; +parameter val_ttc0__Counter_Value_1 = 32'h00000000; +parameter mask_ttc0__Counter_Value_1 = 32'h0000FFFF; + +parameter ttc0__Counter_Value_2 = 32'hF800101C; +parameter val_ttc0__Counter_Value_2 = 32'h00000000; +parameter mask_ttc0__Counter_Value_2 = 32'h0000FFFF; + +parameter ttc0__Counter_Value_3 = 32'hF8001020; +parameter val_ttc0__Counter_Value_3 = 32'h00000000; +parameter mask_ttc0__Counter_Value_3 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_1 = 32'hF8001024; +parameter val_ttc0__Interval_Counter_1 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_2 = 32'hF8001028; +parameter val_ttc0__Interval_Counter_2 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Interval_Counter_3 = 32'hF800102C; +parameter val_ttc0__Interval_Counter_3 = 32'h00000000; +parameter mask_ttc0__Interval_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_1 = 32'hF8001030; +parameter val_ttc0__Match_1_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_2 = 32'hF8001034; +parameter val_ttc0__Match_1_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_1_Counter_3 = 32'hF8001038; +parameter val_ttc0__Match_1_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_1_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_1 = 32'hF800103C; +parameter val_ttc0__Match_2_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_2 = 32'hF8001040; +parameter val_ttc0__Match_2_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_2_Counter_3 = 32'hF8001044; +parameter val_ttc0__Match_2_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_2_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_1 = 32'hF8001048; +parameter val_ttc0__Match_3_Counter_1 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_1 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_2 = 32'hF800104C; +parameter val_ttc0__Match_3_Counter_2 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_2 = 32'h0000FFFF; + +parameter ttc0__Match_3_Counter_3 = 32'hF8001050; +parameter val_ttc0__Match_3_Counter_3 = 32'h00000000; +parameter mask_ttc0__Match_3_Counter_3 = 32'h0000FFFF; + +parameter ttc0__Interrupt_Register_1 = 32'hF8001054; +parameter val_ttc0__Interrupt_Register_1 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_1 = 32'h0000003F; + +parameter ttc0__Interrupt_Register_2 = 32'hF8001058; +parameter val_ttc0__Interrupt_Register_2 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_2 = 32'h0000003F; + +parameter ttc0__Interrupt_Register_3 = 32'hF800105C; +parameter val_ttc0__Interrupt_Register_3 = 32'h00000000; +parameter mask_ttc0__Interrupt_Register_3 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_1 = 32'hF8001060; +parameter val_ttc0__Interrupt_Enable_1 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_1 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_2 = 32'hF8001064; +parameter val_ttc0__Interrupt_Enable_2 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_2 = 32'h0000003F; + +parameter ttc0__Interrupt_Enable_3 = 32'hF8001068; +parameter val_ttc0__Interrupt_Enable_3 = 32'h00000000; +parameter mask_ttc0__Interrupt_Enable_3 = 32'h0000003F; + +parameter ttc0__Event_Control_Timer_1 = 32'hF800106C; +parameter val_ttc0__Event_Control_Timer_1 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_1 = 32'h00000007; + +parameter ttc0__Event_Control_Timer_2 = 32'hF8001070; +parameter val_ttc0__Event_Control_Timer_2 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_2 = 32'h00000007; + +parameter ttc0__Event_Control_Timer_3 = 32'hF8001074; +parameter val_ttc0__Event_Control_Timer_3 = 32'h00000000; +parameter mask_ttc0__Event_Control_Timer_3 = 32'h00000007; + +parameter ttc0__Event_Register_1 = 32'hF8001078; +parameter val_ttc0__Event_Register_1 = 32'h00000000; +parameter mask_ttc0__Event_Register_1 = 32'h0000FFFF; + +parameter ttc0__Event_Register_2 = 32'hF800107C; +parameter val_ttc0__Event_Register_2 = 32'h00000000; +parameter mask_ttc0__Event_Register_2 = 32'h0000FFFF; + +parameter ttc0__Event_Register_3 = 32'hF8001080; +parameter val_ttc0__Event_Register_3 = 32'h00000000; +parameter mask_ttc0__Event_Register_3 = 32'h0000FFFF; + + +// ************************************************************ +// Module ttc1 ttc +// doc version: 2.0 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter ttc1__Clock_Control_1 = 32'hF8002000; +parameter val_ttc1__Clock_Control_1 = 32'h00000000; +parameter mask_ttc1__Clock_Control_1 = 32'h0000007F; + +parameter ttc1__Clock_Control_2 = 32'hF8002004; +parameter val_ttc1__Clock_Control_2 = 32'h00000000; +parameter mask_ttc1__Clock_Control_2 = 32'h0000007F; + +parameter ttc1__Clock_Control_3 = 32'hF8002008; +parameter val_ttc1__Clock_Control_3 = 32'h00000000; +parameter mask_ttc1__Clock_Control_3 = 32'h0000007F; + +parameter ttc1__Counter_Control_1 = 32'hF800200C; +parameter val_ttc1__Counter_Control_1 = 32'h00000021; +parameter mask_ttc1__Counter_Control_1 = 32'h0000007F; + +parameter ttc1__Counter_Control_2 = 32'hF8002010; +parameter val_ttc1__Counter_Control_2 = 32'h00000021; +parameter mask_ttc1__Counter_Control_2 = 32'h0000007F; + +parameter ttc1__Counter_Control_3 = 32'hF8002014; +parameter val_ttc1__Counter_Control_3 = 32'h00000021; +parameter mask_ttc1__Counter_Control_3 = 32'h0000007F; + +parameter ttc1__Counter_Value_1 = 32'hF8002018; +parameter val_ttc1__Counter_Value_1 = 32'h00000000; +parameter mask_ttc1__Counter_Value_1 = 32'h0000FFFF; + +parameter ttc1__Counter_Value_2 = 32'hF800201C; +parameter val_ttc1__Counter_Value_2 = 32'h00000000; +parameter mask_ttc1__Counter_Value_2 = 32'h0000FFFF; + +parameter ttc1__Counter_Value_3 = 32'hF8002020; +parameter val_ttc1__Counter_Value_3 = 32'h00000000; +parameter mask_ttc1__Counter_Value_3 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_1 = 32'hF8002024; +parameter val_ttc1__Interval_Counter_1 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_2 = 32'hF8002028; +parameter val_ttc1__Interval_Counter_2 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Interval_Counter_3 = 32'hF800202C; +parameter val_ttc1__Interval_Counter_3 = 32'h00000000; +parameter mask_ttc1__Interval_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_1 = 32'hF8002030; +parameter val_ttc1__Match_1_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_2 = 32'hF8002034; +parameter val_ttc1__Match_1_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_1_Counter_3 = 32'hF8002038; +parameter val_ttc1__Match_1_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_1_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_1 = 32'hF800203C; +parameter val_ttc1__Match_2_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_2 = 32'hF8002040; +parameter val_ttc1__Match_2_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_2_Counter_3 = 32'hF8002044; +parameter val_ttc1__Match_2_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_2_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_1 = 32'hF8002048; +parameter val_ttc1__Match_3_Counter_1 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_1 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_2 = 32'hF800204C; +parameter val_ttc1__Match_3_Counter_2 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_2 = 32'h0000FFFF; + +parameter ttc1__Match_3_Counter_3 = 32'hF8002050; +parameter val_ttc1__Match_3_Counter_3 = 32'h00000000; +parameter mask_ttc1__Match_3_Counter_3 = 32'h0000FFFF; + +parameter ttc1__Interrupt_Register_1 = 32'hF8002054; +parameter val_ttc1__Interrupt_Register_1 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_1 = 32'h0000003F; + +parameter ttc1__Interrupt_Register_2 = 32'hF8002058; +parameter val_ttc1__Interrupt_Register_2 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_2 = 32'h0000003F; + +parameter ttc1__Interrupt_Register_3 = 32'hF800205C; +parameter val_ttc1__Interrupt_Register_3 = 32'h00000000; +parameter mask_ttc1__Interrupt_Register_3 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_1 = 32'hF8002060; +parameter val_ttc1__Interrupt_Enable_1 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_1 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_2 = 32'hF8002064; +parameter val_ttc1__Interrupt_Enable_2 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_2 = 32'h0000003F; + +parameter ttc1__Interrupt_Enable_3 = 32'hF8002068; +parameter val_ttc1__Interrupt_Enable_3 = 32'h00000000; +parameter mask_ttc1__Interrupt_Enable_3 = 32'h0000003F; + +parameter ttc1__Event_Control_Timer_1 = 32'hF800206C; +parameter val_ttc1__Event_Control_Timer_1 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_1 = 32'h00000007; + +parameter ttc1__Event_Control_Timer_2 = 32'hF8002070; +parameter val_ttc1__Event_Control_Timer_2 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_2 = 32'h00000007; + +parameter ttc1__Event_Control_Timer_3 = 32'hF8002074; +parameter val_ttc1__Event_Control_Timer_3 = 32'h00000000; +parameter mask_ttc1__Event_Control_Timer_3 = 32'h00000007; + +parameter ttc1__Event_Register_1 = 32'hF8002078; +parameter val_ttc1__Event_Register_1 = 32'h00000000; +parameter mask_ttc1__Event_Register_1 = 32'h0000FFFF; + +parameter ttc1__Event_Register_2 = 32'hF800207C; +parameter val_ttc1__Event_Register_2 = 32'h00000000; +parameter mask_ttc1__Event_Register_2 = 32'h0000FFFF; + +parameter ttc1__Event_Register_3 = 32'hF8002080; +parameter val_ttc1__Event_Register_3 = 32'h00000000; +parameter mask_ttc1__Event_Register_3 = 32'h0000FFFF; + + +// ************************************************************ +// Module uart0 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter uart0__Control_reg0 = 32'hE0000000; +parameter val_uart0__Control_reg0 = 32'h00000128; +parameter mask_uart0__Control_reg0 = 32'hFFFFFFFF; + +parameter uart0__mode_reg0 = 32'hE0000004; +parameter val_uart0__mode_reg0 = 32'h00000000; +parameter mask_uart0__mode_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_en_reg0 = 32'hE0000008; +parameter val_uart0__Intrpt_en_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_dis_reg0 = 32'hE000000C; +parameter val_uart0__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter uart0__Intrpt_mask_reg0 = 32'hE0000010; +parameter val_uart0__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_uart0__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter uart0__Chnl_int_sts_reg0 = 32'hE0000014; +parameter val_uart0__Chnl_int_sts_reg0 = 32'h00000200; +parameter mask_uart0__Chnl_int_sts_reg0 = 32'hFFFFFFFF; + +parameter uart0__Baud_rate_gen_reg0 = 32'hE0000018; +parameter val_uart0__Baud_rate_gen_reg0 = 32'h0000028B; +parameter mask_uart0__Baud_rate_gen_reg0 = 32'hFFFFFFFF; + +parameter uart0__Rcvr_timeout_reg0 = 32'hE000001C; +parameter val_uart0__Rcvr_timeout_reg0 = 32'h00000000; +parameter mask_uart0__Rcvr_timeout_reg0 = 32'hFFFFFFFF; + +parameter uart0__Rcvr_FIFO_trigger_level0 = 32'hE0000020; +parameter val_uart0__Rcvr_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart0__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; + +parameter uart0__Modem_ctrl_reg0 = 32'hE0000024; +parameter val_uart0__Modem_ctrl_reg0 = 32'h00000000; +parameter mask_uart0__Modem_ctrl_reg0 = 32'hFFFFFFFF; + +parameter uart0__Modem_sts_reg0 = 32'hE0000028; +parameter val_uart0__Modem_sts_reg0 = 32'h00000000; +parameter mask_uart0__Modem_sts_reg0 = 32'h00000000; + +parameter uart0__Channel_sts_reg0 = 32'hE000002C; +parameter val_uart0__Channel_sts_reg0 = 32'h00000000; +parameter mask_uart0__Channel_sts_reg0 = 32'hFFFFFFFF; + +parameter uart0__TX_RX_FIFO0 = 32'hE0000030; +parameter val_uart0__TX_RX_FIFO0 = 32'h00000000; +parameter mask_uart0__TX_RX_FIFO0 = 32'hFFFFFFFF; + +parameter uart0__Baud_rate_divider_reg0 = 32'hE0000034; +parameter val_uart0__Baud_rate_divider_reg0 = 32'h0000000F; +parameter mask_uart0__Baud_rate_divider_reg0 = 32'hFFFFFFFF; + +parameter uart0__Flow_delay_reg0 = 32'hE0000038; +parameter val_uart0__Flow_delay_reg0 = 32'h00000000; +parameter mask_uart0__Flow_delay_reg0 = 32'hFFFFFFFF; + +parameter uart0__IR_min_rcv_pulse_wdth0 = 32'hE000003C; +parameter val_uart0__IR_min_rcv_pulse_wdth0 = 32'h00000000; +parameter mask_uart0__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; + +parameter uart0__IR_transmitted_pulse_wdth0 = 32'hE0000040; +parameter val_uart0__IR_transmitted_pulse_wdth0 = 32'h00000000; +parameter mask_uart0__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; + +parameter uart0__Tx_FIFO_trigger_level0 = 32'hE0000044; +parameter val_uart0__Tx_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart0__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module uart1 UART +// doc version: 1.2 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter uart1__Control_reg0 = 32'hE0001000; +parameter val_uart1__Control_reg0 = 32'h00000128; +parameter mask_uart1__Control_reg0 = 32'hFFFFFFFF; + +parameter uart1__mode_reg0 = 32'hE0001004; +parameter val_uart1__mode_reg0 = 32'h00000000; +parameter mask_uart1__mode_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_en_reg0 = 32'hE0001008; +parameter val_uart1__Intrpt_en_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_en_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_dis_reg0 = 32'hE000100C; +parameter val_uart1__Intrpt_dis_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_dis_reg0 = 32'hFFFFFFFF; + +parameter uart1__Intrpt_mask_reg0 = 32'hE0001010; +parameter val_uart1__Intrpt_mask_reg0 = 32'h00000000; +parameter mask_uart1__Intrpt_mask_reg0 = 32'hFFFFFFFF; + +parameter uart1__Chnl_int_sts_reg0 = 32'hE0001014; +parameter val_uart1__Chnl_int_sts_reg0 = 32'h00000200; +parameter mask_uart1__Chnl_int_sts_reg0 = 32'hFFFFFFFF; + +parameter uart1__Baud_rate_gen_reg0 = 32'hE0001018; +parameter val_uart1__Baud_rate_gen_reg0 = 32'h0000028B; +parameter mask_uart1__Baud_rate_gen_reg0 = 32'hFFFFFFFF; + +parameter uart1__Rcvr_timeout_reg0 = 32'hE000101C; +parameter val_uart1__Rcvr_timeout_reg0 = 32'h00000000; +parameter mask_uart1__Rcvr_timeout_reg0 = 32'hFFFFFFFF; + +parameter uart1__Rcvr_FIFO_trigger_level0 = 32'hE0001020; +parameter val_uart1__Rcvr_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart1__Rcvr_FIFO_trigger_level0 = 32'hFFFFFFFF; + +parameter uart1__Modem_ctrl_reg0 = 32'hE0001024; +parameter val_uart1__Modem_ctrl_reg0 = 32'h00000000; +parameter mask_uart1__Modem_ctrl_reg0 = 32'hFFFFFFFF; + +parameter uart1__Modem_sts_reg0 = 32'hE0001028; +parameter val_uart1__Modem_sts_reg0 = 32'h00000000; +parameter mask_uart1__Modem_sts_reg0 = 32'h00000000; + +parameter uart1__Channel_sts_reg0 = 32'hE000102C; +parameter val_uart1__Channel_sts_reg0 = 32'h00000000; +parameter mask_uart1__Channel_sts_reg0 = 32'hFFFFFFFF; + +parameter uart1__TX_RX_FIFO0 = 32'hE0001030; +parameter val_uart1__TX_RX_FIFO0 = 32'h00000000; +parameter mask_uart1__TX_RX_FIFO0 = 32'hFFFFFFFF; + +parameter uart1__Baud_rate_divider_reg0 = 32'hE0001034; +parameter val_uart1__Baud_rate_divider_reg0 = 32'h0000000F; +parameter mask_uart1__Baud_rate_divider_reg0 = 32'hFFFFFFFF; + +parameter uart1__Flow_delay_reg0 = 32'hE0001038; +parameter val_uart1__Flow_delay_reg0 = 32'h00000000; +parameter mask_uart1__Flow_delay_reg0 = 32'hFFFFFFFF; + +parameter uart1__IR_min_rcv_pulse_wdth0 = 32'hE000103C; +parameter val_uart1__IR_min_rcv_pulse_wdth0 = 32'h00000000; +parameter mask_uart1__IR_min_rcv_pulse_wdth0 = 32'hFFFFFFFF; + +parameter uart1__IR_transmitted_pulse_wdth0 = 32'hE0001040; +parameter val_uart1__IR_transmitted_pulse_wdth0 = 32'h00000000; +parameter mask_uart1__IR_transmitted_pulse_wdth0 = 32'hFFFF00FF; + +parameter uart1__Tx_FIFO_trigger_level0 = 32'hE0001044; +parameter val_uart1__Tx_FIFO_trigger_level0 = 32'h00000020; +parameter mask_uart1__Tx_FIFO_trigger_level0 = 32'hFFFFFFFF; + + +// ************************************************************ +// Module usb0 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter usb0__ID = 32'hE0002000; +parameter val_usb0__ID = 32'hE441FA05; +parameter mask_usb0__ID = 32'hFFFFFFFF; + +parameter usb0__HWGENERAL = 32'hE0002004; +parameter val_usb0__HWGENERAL = 32'h00000083; +parameter mask_usb0__HWGENERAL = 32'h00000FFF; + +parameter usb0__HWHOST = 32'hE0002008; +parameter val_usb0__HWHOST = 32'h10020001; +parameter mask_usb0__HWHOST = 32'hFFFFFFFF; + +parameter usb0__HWDEVICE = 32'hE000200C; +parameter val_usb0__HWDEVICE = 32'h00000019; +parameter mask_usb0__HWDEVICE = 32'h0000003F; + +parameter usb0__HWTXBUF = 32'hE0002010; +parameter val_usb0__HWTXBUF = 32'h80060A10; +parameter mask_usb0__HWTXBUF = 32'hFFFFFFFF; + +parameter usb0__HWRXBUF = 32'hE0002014; +parameter val_usb0__HWRXBUF = 32'h00000A10; +parameter mask_usb0__HWRXBUF = 32'hFF00FFFF; + +parameter usb0__GPTIMER0LD = 32'hE0002080; +parameter val_usb0__GPTIMER0LD = 32'h00000000; +parameter mask_usb0__GPTIMER0LD = 32'h00FFFFFF; + +parameter usb0__GPTIMER0CTRL = 32'hE0002084; +parameter val_usb0__GPTIMER0CTRL = 32'h00000000; +parameter mask_usb0__GPTIMER0CTRL = 32'hFFFFFFFF; + +parameter usb0__GPTIMER1LD = 32'hE0002088; +parameter val_usb0__GPTIMER1LD = 32'h00000000; +parameter mask_usb0__GPTIMER1LD = 32'h00FFFFFF; + +parameter usb0__GPTIMER1CTRL = 32'hE000208C; +parameter val_usb0__GPTIMER1CTRL = 32'h00000000; +parameter mask_usb0__GPTIMER1CTRL = 32'hFFFFFFFF; + +parameter usb0__SBUSCFG = 32'hE0002090; +parameter val_usb0__SBUSCFG = 32'h00000003; +parameter mask_usb0__SBUSCFG = 32'h00000007; + +parameter usb0__CAPLENGTH_HCIVERSION = 32'hE0002100; +parameter val_usb0__CAPLENGTH_HCIVERSION = 32'h01000040; +parameter mask_usb0__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; + +parameter usb0__HCSPARAMS = 32'hE0002104; +parameter val_usb0__HCSPARAMS = 32'h00010011; +parameter mask_usb0__HCSPARAMS = 32'h0FFFFFFF; + +parameter usb0__HCCPARAMS = 32'hE0002108; +parameter val_usb0__HCCPARAMS = 32'h00000006; +parameter mask_usb0__HCCPARAMS = 32'h0000FFFF; + +parameter usb0__DCIVERSION = 32'hE0002120; +parameter val_usb0__DCIVERSION = 32'h00000001; +parameter mask_usb0__DCIVERSION = 32'h0000FFFF; + +parameter usb0__DCCPARAMS = 32'hE0002124; +parameter val_usb0__DCCPARAMS = 32'h0000018C; +parameter mask_usb0__DCCPARAMS = 32'h000001FF; + +parameter usb0__USBCMD = 32'hE0002140; +parameter val_usb0__USBCMD = 32'h00000B00; +parameter mask_usb0__USBCMD = 32'h00FFFFFF; + +parameter usb0__USBSTS = 32'hE0002144; +parameter val_usb0__USBSTS = 32'h00000000; +parameter mask_usb0__USBSTS = 32'h03FFFFFF; + +parameter usb0__USBINTR = 32'hE0002148; +parameter val_usb0__USBINTR = 32'h00000000; +parameter mask_usb0__USBINTR = 32'h03FF0FFF; + +parameter usb0__FRINDEX = 32'hE000214C; +parameter val_usb0__FRINDEX = 32'h00000000; +parameter mask_usb0__FRINDEX = 32'h00003FFF; + +parameter usb0__PERIODICLISTBASE_DEVICEADDR = 32'hE0002154; +parameter val_usb0__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; +parameter mask_usb0__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; + +parameter usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0002158; +parameter val_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; +parameter mask_usb0__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; + +parameter usb0__TTCTRL = 32'hE000215C; +parameter val_usb0__TTCTRL = 32'h00000000; +parameter mask_usb0__TTCTRL = 32'hFFFFFFFF; + +parameter usb0__BURSTSIZE = 32'hE0002160; +parameter val_usb0__BURSTSIZE = 32'h00001010; +parameter mask_usb0__BURSTSIZE = 32'h0001FFFF; + +parameter usb0__TXFILLTUNING = 32'hE0002164; +parameter val_usb0__TXFILLTUNING = 32'h00020000; +parameter mask_usb0__TXFILLTUNING = 32'h003FFFFF; + +parameter usb0__TXTTFILLTUNING = 32'hE0002168; +parameter val_usb0__TXTTFILLTUNING = 32'h00000000; +parameter mask_usb0__TXTTFILLTUNING = 32'h00001FFF; + +parameter usb0__IC_USB = 32'hE000216C; +parameter val_usb0__IC_USB = 32'h00000000; +parameter mask_usb0__IC_USB = 32'hFFFFFFFF; + +parameter usb0__ULPI_VIEWPORT = 32'hE0002170; +parameter val_usb0__ULPI_VIEWPORT = 32'h00000000; +parameter mask_usb0__ULPI_VIEWPORT = 32'hFFFFFFFF; + +parameter usb0__ENDPTNAK = 32'hE0002178; +parameter val_usb0__ENDPTNAK = 32'h00000000; +parameter mask_usb0__ENDPTNAK = 32'hFFFFFFFF; + +parameter usb0__ENDPTNAKEN = 32'hE000217C; +parameter val_usb0__ENDPTNAKEN = 32'h00000000; +parameter mask_usb0__ENDPTNAKEN = 32'hFFFFFFFF; + +parameter usb0__CONFIGFLAG = 32'hE0002180; +parameter val_usb0__CONFIGFLAG = 32'h00000001; +parameter mask_usb0__CONFIGFLAG = 32'hFFFFFFFF; + +parameter usb0__PORTSC1 = 32'hE0002184; +parameter val_usb0__PORTSC1 = 32'h00000000; +parameter mask_usb0__PORTSC1 = 32'hFFFFFFFF; + +parameter usb0__OTGSC = 32'hE00021A4; +parameter val_usb0__OTGSC = 32'h00000020; +parameter mask_usb0__OTGSC = 32'hFFFFFFFF; + +parameter usb0__USBMODE = 32'hE00021A8; +parameter val_usb0__USBMODE = 32'h00000000; +parameter mask_usb0__USBMODE = 32'h0000FFFF; + +parameter usb0__ENDPTSETUPSTAT = 32'hE00021AC; +parameter val_usb0__ENDPTSETUPSTAT = 32'h00000000; +parameter mask_usb0__ENDPTSETUPSTAT = 32'h0000FFFF; + +parameter usb0__ENDPTPRIME = 32'hE00021B0; +parameter val_usb0__ENDPTPRIME = 32'h00000000; +parameter mask_usb0__ENDPTPRIME = 32'hFFFFFFFF; + +parameter usb0__ENDPTFLUSH = 32'hE00021B4; +parameter val_usb0__ENDPTFLUSH = 32'h00000000; +parameter mask_usb0__ENDPTFLUSH = 32'hFFFFFFFF; + +parameter usb0__ENDPTSTAT = 32'hE00021B8; +parameter val_usb0__ENDPTSTAT = 32'h00000000; +parameter mask_usb0__ENDPTSTAT = 32'hFFFFFFFF; + +parameter usb0__ENDPTCOMPLETE = 32'hE00021BC; +parameter val_usb0__ENDPTCOMPLETE = 32'h00000000; +parameter mask_usb0__ENDPTCOMPLETE = 32'hFFFFFFFF; + +parameter usb0__ENDPTCTRL0 = 32'hE00021C0; +parameter val_usb0__ENDPTCTRL0 = 32'h00800080; +parameter mask_usb0__ENDPTCTRL0 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL1 = 32'hE00021C4; +parameter val_usb0__ENDPTCTRL1 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL1 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL2 = 32'hE00021C8; +parameter val_usb0__ENDPTCTRL2 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL2 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL3 = 32'hE00021CC; +parameter val_usb0__ENDPTCTRL3 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL3 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL4 = 32'hE00021D0; +parameter val_usb0__ENDPTCTRL4 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL4 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL5 = 32'hE00021D4; +parameter val_usb0__ENDPTCTRL5 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL5 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL6 = 32'hE00021D8; +parameter val_usb0__ENDPTCTRL6 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL6 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL7 = 32'hE00021DC; +parameter val_usb0__ENDPTCTRL7 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL7 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL8 = 32'hE00021E0; +parameter val_usb0__ENDPTCTRL8 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL8 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL9 = 32'hE00021E4; +parameter val_usb0__ENDPTCTRL9 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL9 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL10 = 32'hE00021E8; +parameter val_usb0__ENDPTCTRL10 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL10 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL11 = 32'hE00021EC; +parameter val_usb0__ENDPTCTRL11 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL11 = 32'h00FFFFFF; + +parameter usb0__ENDPTCTRL12 = 32'hE00021F0; +parameter val_usb0__ENDPTCTRL12 = 32'h00000000; +parameter mask_usb0__ENDPTCTRL12 = 32'h00FFFFFF; + + +// ************************************************************ +// Module usb1 usb +// doc version: 1.3 +// ************************************************************ + +// ADDRESS DEVFALUE MASK NAME +parameter usb1__ID = 32'hE0003000; +parameter val_usb1__ID = 32'hE441FA05; +parameter mask_usb1__ID = 32'hFFFFFFFF; + +parameter usb1__HWGENERAL = 32'hE0003004; +parameter val_usb1__HWGENERAL = 32'h00000083; +parameter mask_usb1__HWGENERAL = 32'h00000FFF; + +parameter usb1__HWHOST = 32'hE0003008; +parameter val_usb1__HWHOST = 32'h10020001; +parameter mask_usb1__HWHOST = 32'hFFFFFFFF; + +parameter usb1__HWDEVICE = 32'hE000300C; +parameter val_usb1__HWDEVICE = 32'h00000019; +parameter mask_usb1__HWDEVICE = 32'h0000003F; + +parameter usb1__HWTXBUF = 32'hE0003010; +parameter val_usb1__HWTXBUF = 32'h80060A10; +parameter mask_usb1__HWTXBUF = 32'hFFFFFFFF; + +parameter usb1__HWRXBUF = 32'hE0003014; +parameter val_usb1__HWRXBUF = 32'h00000A10; +parameter mask_usb1__HWRXBUF = 32'hFF00FFFF; + +parameter usb1__GPTIMER0LD = 32'hE0003080; +parameter val_usb1__GPTIMER0LD = 32'h00000000; +parameter mask_usb1__GPTIMER0LD = 32'h00FFFFFF; + +parameter usb1__GPTIMER0CTRL = 32'hE0003084; +parameter val_usb1__GPTIMER0CTRL = 32'h00000000; +parameter mask_usb1__GPTIMER0CTRL = 32'hFFFFFFFF; + +parameter usb1__GPTIMER1LD = 32'hE0003088; +parameter val_usb1__GPTIMER1LD = 32'h00000000; +parameter mask_usb1__GPTIMER1LD = 32'h00FFFFFF; + +parameter usb1__GPTIMER1CTRL = 32'hE000308C; +parameter val_usb1__GPTIMER1CTRL = 32'h00000000; +parameter mask_usb1__GPTIMER1CTRL = 32'hFFFFFFFF; + +parameter usb1__SBUSCFG = 32'hE0003090; +parameter val_usb1__SBUSCFG = 32'h00000003; +parameter mask_usb1__SBUSCFG = 32'h00000007; + +parameter usb1__CAPLENGTH_HCIVERSION = 32'hE0003100; +parameter val_usb1__CAPLENGTH_HCIVERSION = 32'h01000040; +parameter mask_usb1__CAPLENGTH_HCIVERSION = 32'hFFFFFFFF; + +parameter usb1__HCSPARAMS = 32'hE0003104; +parameter val_usb1__HCSPARAMS = 32'h00010011; +parameter mask_usb1__HCSPARAMS = 32'h0FFFFFFF; + +parameter usb1__HCCPARAMS = 32'hE0003108; +parameter val_usb1__HCCPARAMS = 32'h00000006; +parameter mask_usb1__HCCPARAMS = 32'h0000FFFF; + +parameter usb1__DCIVERSION = 32'hE0003120; +parameter val_usb1__DCIVERSION = 32'h00000001; +parameter mask_usb1__DCIVERSION = 32'h0000FFFF; + +parameter usb1__DCCPARAMS = 32'hE0003124; +parameter val_usb1__DCCPARAMS = 32'h0000018C; +parameter mask_usb1__DCCPARAMS = 32'h000001FF; + +parameter usb1__USBCMD = 32'hE0003140; +parameter val_usb1__USBCMD = 32'h00000B00; +parameter mask_usb1__USBCMD = 32'h00FFFFFF; + +parameter usb1__USBSTS = 32'hE0003144; +parameter val_usb1__USBSTS = 32'h00000000; +parameter mask_usb1__USBSTS = 32'h03FFFFFF; + +parameter usb1__USBINTR = 32'hE0003148; +parameter val_usb1__USBINTR = 32'h00000000; +parameter mask_usb1__USBINTR = 32'h03FF0FFF; + +parameter usb1__FRINDEX = 32'hE000314C; +parameter val_usb1__FRINDEX = 32'h00000000; +parameter mask_usb1__FRINDEX = 32'h00003FFF; + +parameter usb1__PERIODICLISTBASE_DEVICEADDR = 32'hE0003154; +parameter val_usb1__PERIODICLISTBASE_DEVICEADDR = 32'h00000000; +parameter mask_usb1__PERIODICLISTBASE_DEVICEADDR = 32'hFFFFFFFF; + +parameter usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hE0003158; +parameter val_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'h00000000; +parameter mask_usb1__ASYNCLISTADDR_ENDPOINTLISTADDR = 32'hFFFFFFFF; + +parameter usb1__TTCTRL = 32'hE000315C; +parameter val_usb1__TTCTRL = 32'h00000000; +parameter mask_usb1__TTCTRL = 32'hFFFFFFFF; + +parameter usb1__BURSTSIZE = 32'hE0003160; +parameter val_usb1__BURSTSIZE = 32'h00001010; +parameter mask_usb1__BURSTSIZE = 32'h0001FFFF; + +parameter usb1__TXFILLTUNING = 32'hE0003164; +parameter val_usb1__TXFILLTUNING = 32'h00020000; +parameter mask_usb1__TXFILLTUNING = 32'h003FFFFF; + +parameter usb1__TXTTFILLTUNING = 32'hE0003168; +parameter val_usb1__TXTTFILLTUNING = 32'h00000000; +parameter mask_usb1__TXTTFILLTUNING = 32'h00001FFF; + +parameter usb1__IC_USB = 32'hE000316C; +parameter val_usb1__IC_USB = 32'h00000000; +parameter mask_usb1__IC_USB = 32'hFFFFFFFF; + +parameter usb1__ULPI_VIEWPORT = 32'hE0003170; +parameter val_usb1__ULPI_VIEWPORT = 32'h00000000; +parameter mask_usb1__ULPI_VIEWPORT = 32'hFFFFFFFF; + +parameter usb1__ENDPTNAK = 32'hE0003178; +parameter val_usb1__ENDPTNAK = 32'h00000000; +parameter mask_usb1__ENDPTNAK = 32'hFFFFFFFF; + +parameter usb1__ENDPTNAKEN = 32'hE000317C; +parameter val_usb1__ENDPTNAKEN = 32'h00000000; +parameter mask_usb1__ENDPTNAKEN = 32'hFFFFFFFF; + +parameter usb1__CONFIGFLAG = 32'hE0003180; +parameter val_usb1__CONFIGFLAG = 32'h00000001; +parameter mask_usb1__CONFIGFLAG = 32'hFFFFFFFF; + +parameter usb1__PORTSC1 = 32'hE0003184; +parameter val_usb1__PORTSC1 = 32'h00000000; +parameter mask_usb1__PORTSC1 = 32'hFFFFFFFF; + +parameter usb1__OTGSC = 32'hE00031A4; +parameter val_usb1__OTGSC = 32'h00000020; +parameter mask_usb1__OTGSC = 32'hFFFFFFFF; + +parameter usb1__USBMODE = 32'hE00031A8; +parameter val_usb1__USBMODE = 32'h00000000; +parameter mask_usb1__USBMODE = 32'h0000FFFF; + +parameter usb1__ENDPTSETUPSTAT = 32'hE00031AC; +parameter val_usb1__ENDPTSETUPSTAT = 32'h00000000; +parameter mask_usb1__ENDPTSETUPSTAT = 32'h0000FFFF; + +parameter usb1__ENDPTPRIME = 32'hE00031B0; +parameter val_usb1__ENDPTPRIME = 32'h00000000; +parameter mask_usb1__ENDPTPRIME = 32'hFFFFFFFF; + +parameter usb1__ENDPTFLUSH = 32'hE00031B4; +parameter val_usb1__ENDPTFLUSH = 32'h00000000; +parameter mask_usb1__ENDPTFLUSH = 32'hFFFFFFFF; + +parameter usb1__ENDPTSTAT = 32'hE00031B8; +parameter val_usb1__ENDPTSTAT = 32'h00000000; +parameter mask_usb1__ENDPTSTAT = 32'hFFFFFFFF; + +parameter usb1__ENDPTCOMPLETE = 32'hE00031BC; +parameter val_usb1__ENDPTCOMPLETE = 32'h00000000; +parameter mask_usb1__ENDPTCOMPLETE = 32'hFFFFFFFF; + +parameter usb1__ENDPTCTRL0 = 32'hE00031C0; +parameter val_usb1__ENDPTCTRL0 = 32'h00800080; +parameter mask_usb1__ENDPTCTRL0 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL1 = 32'hE00031C4; +parameter val_usb1__ENDPTCTRL1 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL1 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL2 = 32'hE00031C8; +parameter val_usb1__ENDPTCTRL2 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL2 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL3 = 32'hE00031CC; +parameter val_usb1__ENDPTCTRL3 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL3 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL4 = 32'hE00031D0; +parameter val_usb1__ENDPTCTRL4 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL4 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL5 = 32'hE00031D4; +parameter val_usb1__ENDPTCTRL5 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL5 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL6 = 32'hE00031D8; +parameter val_usb1__ENDPTCTRL6 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL6 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL7 = 32'hE00031DC; +parameter val_usb1__ENDPTCTRL7 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL7 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL8 = 32'hE00031E0; +parameter val_usb1__ENDPTCTRL8 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL8 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL9 = 32'hE00031E4; +parameter val_usb1__ENDPTCTRL9 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL9 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL10 = 32'hE00031E8; +parameter val_usb1__ENDPTCTRL10 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL10 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL11 = 32'hE00031EC; +parameter val_usb1__ENDPTCTRL11 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL11 = 32'h00FFFFFF; + +parameter usb1__ENDPTCTRL12 = 32'hE00031F0; +parameter val_usb1__ENDPTCTRL12 = 32'h00000000; +parameter mask_usb1__ENDPTCTRL12 = 32'h00FFFFFF; diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_unused_ports.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_unused_ports.v new file mode 100644 index 0000000..23292b0 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/70fd/hdl/processing_system7_vip_v1_0_5_unused_ports.v @@ -0,0 +1,433 @@ +/***************************************************************************** + * File : processing_system7_vip_v1_0_5_unused_ports.v + * + * Date : 2012-11 + * + * Description : Semantic checks for unused ports. + * + *****************************************************************************/ + +/* CAN */ +assign CAN0_PHY_TX = 0; +assign CAN1_PHY_TX = 0; +always @(CAN0_PHY_RX or CAN1_PHY_RX) +begin + if(CAN0_PHY_RX | CAN1_PHY_RX) + $display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* ETHERNET */ +/* ------------------------------------------- */ + +assign ENET0_GMII_TX_EN = 0; +assign ENET0_GMII_TX_ER = 0; +assign ENET0_MDIO_MDC = 0; +assign ENET0_MDIO_O = 0; /// confirm +assign ENET0_MDIO_T = 0; +assign ENET0_PTP_DELAY_REQ_RX = 0; +assign ENET0_PTP_DELAY_REQ_TX = 0; +assign ENET0_PTP_PDELAY_REQ_RX = 0; +assign ENET0_PTP_PDELAY_REQ_TX = 0; +assign ENET0_PTP_PDELAY_RESP_RX = 0; +assign ENET0_PTP_PDELAY_RESP_TX = 0; +assign ENET0_PTP_SYNC_FRAME_RX = 0; +assign ENET0_PTP_SYNC_FRAME_TX = 0; +assign ENET0_SOF_RX = 0; +assign ENET0_SOF_TX = 0; +assign ENET0_GMII_TXD = 0; +always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or + ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or + ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD) +begin + if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN | + ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER | + ENET0_GMII_TX_CLK | ENET0_MDIO_I ) + $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); +end + +assign ENET1_GMII_TX_EN = 0; +assign ENET1_GMII_TX_ER = 0; +assign ENET1_MDIO_MDC = 0; +assign ENET1_MDIO_O = 0;/// confirm +assign ENET1_MDIO_T = 0; +assign ENET1_PTP_DELAY_REQ_RX = 0; +assign ENET1_PTP_DELAY_REQ_TX = 0; +assign ENET1_PTP_PDELAY_REQ_RX = 0; +assign ENET1_PTP_PDELAY_REQ_TX = 0; +assign ENET1_PTP_PDELAY_RESP_RX = 0; +assign ENET1_PTP_PDELAY_RESP_TX = 0; +assign ENET1_PTP_SYNC_FRAME_RX = 0; +assign ENET1_PTP_SYNC_FRAME_TX = 0; +assign ENET1_SOF_RX = 0; +assign ENET1_SOF_TX = 0; +assign ENET1_GMII_TXD = 0; +always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or + ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or + ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD) +begin + if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN | + ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER | + ENET1_GMII_TX_CLK | ENET1_MDIO_I ) + $display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* GPIO */ +/* ------------------------------------------- */ + +assign GPIO_O = 0; +assign GPIO_T = 0; +always@(GPIO_I) +begin +if(GPIO_I !== 0) + $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* I2C */ +/* ------------------------------------------- */ + +assign I2C0_SDA_O = 0; +assign I2C0_SDA_T = 0; +assign I2C0_SCL_O = 0; +assign I2C0_SCL_T = 0; +assign I2C1_SDA_O = 0; +assign I2C1_SDA_T = 0; +assign I2C1_SCL_O = 0; +assign I2C1_SCL_T = 0; +always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I ) +begin + if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I) + $display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* JTAG */ +/* ------------------------------------------- */ + +assign PJTAG_TD_T = 0; +assign PJTAG_TD_O = 0; +always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I) +begin + if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I) + $display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* SDIO */ +/* ------------------------------------------- */ + +assign SDIO0_CLK = 0; +assign SDIO0_CMD_O = 0; +assign SDIO0_CMD_T = 0; +assign SDIO0_DATA_O = 0; +assign SDIO0_DATA_T = 0; +assign SDIO0_LED = 0; +assign SDIO0_BUSPOW = 0; +assign SDIO0_BUSVOLT = 0; +always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP ) +begin + if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP ) + $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); +end + +assign SDIO1_CLK = 0; +assign SDIO1_CMD_O = 0; +assign SDIO1_CMD_T = 0; +assign SDIO1_DATA_O = 0; +assign SDIO1_DATA_T = 0; +assign SDIO1_LED = 0; +assign SDIO1_BUSPOW = 0; +assign SDIO1_BUSVOLT = 0; +always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP ) +begin + if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP ) + $display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* SPI */ +/* ------------------------------------------- */ + +assign SPI0_SCLK_O = 0; +assign SPI0_SCLK_T = 0; +assign SPI0_MOSI_O = 0; +assign SPI0_MOSI_T = 0; +assign SPI0_MISO_O = 0; +assign SPI0_MISO_T = 0; +assign SPI0_SS_O = 0; /// confirm +assign SPI0_SS1_O = 0;/// confirm +assign SPI0_SS2_O = 0;/// confirm +assign SPI0_SS_T = 0; +always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I) +begin + if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I) + $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); +end + +assign SPI1_SCLK_O = 0; +assign SPI1_SCLK_T = 0; +assign SPI1_MOSI_O = 0; +assign SPI1_MOSI_T = 0; +assign SPI1_MISO_O = 0; +assign SPI1_MISO_T = 0; +assign SPI1_SS_O = 0; +assign SPI1_SS1_O = 0; +assign SPI1_SS2_O = 0; +assign SPI1_SS_T = 0; +always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I) +begin + if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I) + $display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* UART */ +/* ------------------------------------------- */ +/// confirm +assign UART0_DTRN = 0; +assign UART0_RTSN = 0; +assign UART0_TX = 0; +always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX) +begin + if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX) + $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); +end + +assign UART1_DTRN = 0; +assign UART1_RTSN = 0; +assign UART1_TX = 0; +always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX) +begin + if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX) + $display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* TTC */ +/* ------------------------------------------- */ + +assign TTC0_WAVE0_OUT = 0; +assign TTC0_WAVE1_OUT = 0; +assign TTC0_WAVE2_OUT = 0; +always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN) +begin + if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN) + $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); +end + +assign TTC1_WAVE0_OUT = 0; +assign TTC1_WAVE1_OUT = 0; +assign TTC1_WAVE2_OUT = 0; +always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN) +begin + if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN) + $display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* WDT */ +/* ------------------------------------------- */ + +assign WDT_RST_OUT = 0; +always@(WDT_CLK_IN) +begin + if(WDT_CLK_IN) + $display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* TRACE */ +/* ------------------------------------------- */ + +assign TRACE_CTL = 0; +assign TRACE_DATA = 0; +always@(TRACE_CLK) +begin + if(TRACE_CLK) + $display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* USB */ +/* ------------------------------------------- */ +assign USB0_PORT_INDCTL = 0; +assign USB0_VBUS_PWRSELECT = 0; +always@(USB0_VBUS_PWRFAULT) +begin + if(USB0_VBUS_PWRFAULT) + $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); +end + +assign USB1_PORT_INDCTL = 0; +assign USB1_VBUS_PWRSELECT = 0; +always@(USB1_VBUS_PWRFAULT) +begin + if(USB1_VBUS_PWRFAULT) + $display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR); +end + +always@(SRAM_INTIN) +begin + if(SRAM_INTIN) + $display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* DMA */ +/* ------------------------------------------- */ + +assign DMA0_DATYPE = 0; +assign DMA0_DAVALID = 0; +assign DMA0_DRREADY = 0; +assign DMA0_RSTN = 0; +always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE) +begin + if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA1_DATYPE = 0; +assign DMA1_DAVALID = 0; +assign DMA1_DRREADY = 0; +assign DMA1_RSTN = 0; +always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE) +begin + if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA2_DATYPE = 0; +assign DMA2_DAVALID = 0; +assign DMA2_DRREADY = 0; +assign DMA2_RSTN = 0; +always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE) +begin + if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +assign DMA3_DATYPE = 0; +assign DMA3_DAVALID = 0; +assign DMA3_DRREADY = 0; +assign DMA3_RSTN = 0; +always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE) +begin + if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE) + $display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* FTM */ +/* ------------------------------------------- */ + +assign FTMT_F2P_TRIGACK = 0; +assign FTMT_P2F_TRIG = 0; +assign FTMT_P2F_DEBUG = 0; +always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or + FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK) +begin + if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK) + $display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* EVENT */ +/* ------------------------------------------- */ + +assign EVENT_EVENTO = 0; +assign EVENT_STANDBYWFE = 0; +assign EVENT_STANDBYWFI = 0; +always@(EVENT_EVENTI) +begin + if(EVENT_EVENTI) + $display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* MIO */ +/* ------------------------------------------- */ + +always@(MIO) +begin + if(MIO !== 0) + $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* FCLK_TRIG */ +/* ------------------------------------------- */ + +always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N ) +begin + if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N ) + $display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* MISC */ +/* ------------------------------------------- */ + +always@(FPGA_IDLE_N) +begin + if(FPGA_IDLE_N) + $display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR); +end + +always@(DDR_ARB) +begin + if(DDR_ARB !== 0) + $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR); +end + +always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ ) +begin + if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ) + $display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* DDR */ +/* ------------------------------------------- */ + +assign DDR_WEB = 0; +always@(DDR_Clk or DDR_CS_n) +begin +if(!DDR_CS_n) + $display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR); +end + +/* ------------------------------------------- */ +/* IRQ_P2F */ +/* ------------------------------------------- */ + +assign IRQ_P2F_DMAC_ABORT = 0; +assign IRQ_P2F_DMAC0 = 0; +assign IRQ_P2F_DMAC1 = 0; +assign IRQ_P2F_DMAC2 = 0; +assign IRQ_P2F_DMAC3 = 0; +assign IRQ_P2F_DMAC4 = 0; +assign IRQ_P2F_DMAC5 = 0; +assign IRQ_P2F_DMAC6 = 0; +assign IRQ_P2F_DMAC7 = 0; +assign IRQ_P2F_SMC = 0; +assign IRQ_P2F_QSPI = 0; +assign IRQ_P2F_CTI = 0; +assign IRQ_P2F_GPIO = 0; +assign IRQ_P2F_USB0 = 0; +assign IRQ_P2F_ENET0 = 0; +assign IRQ_P2F_ENET_WAKE0 = 0; +assign IRQ_P2F_SDIO0 = 0; +assign IRQ_P2F_I2C0 = 0; +assign IRQ_P2F_SPI0 = 0; +assign IRQ_P2F_UART0 = 0; +assign IRQ_P2F_CAN0 = 0; +assign IRQ_P2F_USB1 = 0; +assign IRQ_P2F_ENET1 = 0; +assign IRQ_P2F_ENET_WAKE1 = 0; +assign IRQ_P2F_SDIO1 = 0; +assign IRQ_P2F_I2C1 = 0; +assign IRQ_P2F_SPI1 = 0; +assign IRQ_P2F_UART1 = 0; +assign IRQ_P2F_CAN1 = 0; diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v new file mode 100644 index 0000000..98caca1 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_atc.v @@ -0,0 +1,409 @@ +//----------------------------------------------------------------------------- +//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved. +//-- +//-- This file contains confidential and proprietary information +//-- of Xilinx, Inc. and is protected under U.S. and +//-- international copyright and other intellectual property +//-- laws. +//-- +//-- DISCLAIMER +//-- This disclaimer is not a license and does not grant any +//-- rights to the materials distributed herewith. Except as +//-- otherwise provided in a valid license issued to you by +//-- Xilinx, and to the maximum extent permitted by applicable +//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +//-- (2) Xilinx shall not be liable (whether in contract or tort, +//-- including negligence, or under any other theory of +//-- liability) for any loss or damage of any kind or nature +//-- related to, arising under or in connection with these +//-- materials, including for any direct, or any indirect, +//-- special, incidental, or consequential loss or damage +//-- (including loss of data, profits, goodwill, or any type of +//-- loss or damage suffered as a result of any action brought +//-- by a third party) even if such damage or loss was +//-- reasonably foreseeable or Xilinx had been advised of the +//-- possibility of the same. +//-- +//-- CRITICAL APPLICATIONS +//-- Xilinx products are not designed or intended to be fail- +//-- safe, or for use in any application requiring fail-safe +//-- performance, such as life-support or safety devices or +//-- systems, Class III medical devices, nuclear facilities, +//-- applications related to the deployment of airbags, or any +//-- other applications that could lead to death, personal +//-- injury, or severe property or environmental damage +//-- (individually and collectively, "Critical +//-- Applications"). Customer assumes the sole risk and +//-- liability of any use of Xilinx products in Critical +//-- Applications, subject only to applicable laws and +//-- regulations governing limitations on product liability. +//-- +//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +//-- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: ACP Transaction Checker +// +// Check for optimized ACP transactions and flag if they are broken. +// +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// atc +// aw_atc +// w_atc +// b_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps +`default_nettype none + +module processing_system7_v5_5_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_ADDR_WIDTH = 32, + // Width of all ADDR signals on SI and MI side of checker. + // Range: 32. + parameter integer C_AXI_DATA_WIDTH = 64, + // Width of all DATA signals on SI and MI side of checker. + // Range: 64. + parameter integer C_AXI_AWUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_AXI_ARUSER_WIDTH = 1, + // Width of ARUSER signals. + // Range: >= 1. + parameter integer C_AXI_WUSER_WIDTH = 1, + // Width of WUSER signals. + // Range: >= 1. + parameter integer C_AXI_RUSER_WIDTH = 1, + // Width of RUSER signals. + // Range: >= 1. + parameter integer C_AXI_BUSER_WIDTH = 1 + // Width of BUSER signals. + // Range: >= 1. + ) + ( + // Global Signals + input wire ACLK, + input wire ARESETN, + + // Slave Interface Write Address Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, + input wire [4-1:0] S_AXI_AWLEN, + input wire [3-1:0] S_AXI_AWSIZE, + input wire [2-1:0] S_AXI_AWBURST, + input wire [2-1:0] S_AXI_AWLOCK, + input wire [4-1:0] S_AXI_AWCACHE, + input wire [3-1:0] S_AXI_AWPROT, + input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, + input wire S_AXI_AWVALID, + output wire S_AXI_AWREADY, + // Slave Interface Write Data Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID, + input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, + input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, + input wire S_AXI_WLAST, + input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, + input wire S_AXI_WVALID, + output wire S_AXI_WREADY, + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, + output wire [2-1:0] S_AXI_BRESP, + output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, + output wire S_AXI_BVALID, + input wire S_AXI_BREADY, + // Slave Interface Read Address Ports + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR, + input wire [4-1:0] S_AXI_ARLEN, + input wire [3-1:0] S_AXI_ARSIZE, + input wire [2-1:0] S_AXI_ARBURST, + input wire [2-1:0] S_AXI_ARLOCK, + input wire [4-1:0] S_AXI_ARCACHE, + input wire [3-1:0] S_AXI_ARPROT, + input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER, + input wire S_AXI_ARVALID, + output wire S_AXI_ARREADY, + // Slave Interface Read Data Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID, + output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA, + output wire [2-1:0] S_AXI_RRESP, + output wire S_AXI_RLAST, + output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, + output wire S_AXI_RVALID, + input wire S_AXI_RREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, + output wire [4-1:0] M_AXI_AWLEN, + output wire [3-1:0] M_AXI_AWSIZE, + output wire [2-1:0] M_AXI_AWBURST, + output wire [2-1:0] M_AXI_AWLOCK, + output wire [4-1:0] M_AXI_AWCACHE, + output wire [3-1:0] M_AXI_AWPROT, + output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, + output wire M_AXI_AWVALID, + input wire M_AXI_AWREADY, + // Master Interface Write Data Ports + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, + output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, + output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, + output wire M_AXI_WLAST, + output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, + output wire M_AXI_WVALID, + input wire M_AXI_WREADY, + // Master Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, + input wire [2-1:0] M_AXI_BRESP, + input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, + input wire M_AXI_BVALID, + output wire M_AXI_BREADY, + // Master Interface Read Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR, + output wire [4-1:0] M_AXI_ARLEN, + output wire [3-1:0] M_AXI_ARSIZE, + output wire [2-1:0] M_AXI_ARBURST, + output wire [2-1:0] M_AXI_ARLOCK, + output wire [4-1:0] M_AXI_ARCACHE, + output wire [3-1:0] M_AXI_ARPROT, + output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER, + output wire M_AXI_ARVALID, + input wire M_AXI_ARREADY, + // Master Interface Read Data Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID, + input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA, + input wire [2-1:0] M_AXI_RRESP, + input wire M_AXI_RLAST, + input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER, + input wire M_AXI_RVALID, + output wire M_AXI_RREADY, + + output wire ERROR_TRIGGER, + output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + localparam C_FIFO_DEPTH_LOG = 4; + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Internal reset. + reg ARESET; + + // AW->W command queue signals. + wire cmd_w_valid; + wire cmd_w_check; + wire [C_AXI_ID_WIDTH-1:0] cmd_w_id; + wire cmd_w_ready; + + // W->B command queue signals. + wire cmd_b_push; + wire cmd_b_error; + wire [C_AXI_ID_WIDTH-1:0] cmd_b_id; + wire cmd_b_full; + wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr; + wire cmd_b_ready; + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Internal Reset + ///////////////////////////////////////////////////////////////////////////// + always @ (posedge ACLK) begin + ARESET <= !ARESETN; + end + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Write Channels (AW/W/B) + ///////////////////////////////////////////////////////////////////////////// + + // Write Address Channel. + processing_system7_v5_5_aw_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH), + .C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH), + .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG) + ) write_addr_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (Out) + .cmd_w_valid (cmd_w_valid), + .cmd_w_check (cmd_w_check), + .cmd_w_id (cmd_w_id), + .cmd_w_ready (cmd_w_ready), + .cmd_b_addr (cmd_b_addr), + .cmd_b_ready (cmd_b_ready), + + // Slave Interface Write Address Ports + .S_AXI_AWID (S_AXI_AWID), + .S_AXI_AWADDR (S_AXI_AWADDR), + .S_AXI_AWLEN (S_AXI_AWLEN), + .S_AXI_AWSIZE (S_AXI_AWSIZE), + .S_AXI_AWBURST (S_AXI_AWBURST), + .S_AXI_AWLOCK (S_AXI_AWLOCK), + .S_AXI_AWCACHE (S_AXI_AWCACHE), + .S_AXI_AWPROT (S_AXI_AWPROT), + .S_AXI_AWUSER (S_AXI_AWUSER), + .S_AXI_AWVALID (S_AXI_AWVALID), + .S_AXI_AWREADY (S_AXI_AWREADY), + + // Master Interface Write Address Port + .M_AXI_AWID (M_AXI_AWID), + .M_AXI_AWADDR (M_AXI_AWADDR), + .M_AXI_AWLEN (M_AXI_AWLEN), + .M_AXI_AWSIZE (M_AXI_AWSIZE), + .M_AXI_AWBURST (M_AXI_AWBURST), + .M_AXI_AWLOCK (M_AXI_AWLOCK), + .M_AXI_AWCACHE (M_AXI_AWCACHE), + .M_AXI_AWPROT (M_AXI_AWPROT), + .M_AXI_AWUSER (M_AXI_AWUSER), + .M_AXI_AWVALID (M_AXI_AWVALID), + .M_AXI_AWREADY (M_AXI_AWREADY) + ); + + // Write Data channel. + processing_system7_v5_5_w_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH), + .C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH) + ) write_data_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (In) + .cmd_w_valid (cmd_w_valid), + .cmd_w_check (cmd_w_check), + .cmd_w_id (cmd_w_id), + .cmd_w_ready (cmd_w_ready), + + // Command Interface (Out) + .cmd_b_push (cmd_b_push), + .cmd_b_error (cmd_b_error), + .cmd_b_id (cmd_b_id), + .cmd_b_full (cmd_b_full), + + // Slave Interface Write Data Ports + .S_AXI_WID (S_AXI_WID), + .S_AXI_WDATA (S_AXI_WDATA), + .S_AXI_WSTRB (S_AXI_WSTRB), + .S_AXI_WLAST (S_AXI_WLAST), + .S_AXI_WUSER (S_AXI_WUSER), + .S_AXI_WVALID (S_AXI_WVALID), + .S_AXI_WREADY (S_AXI_WREADY), + + // Master Interface Write Data Ports + .M_AXI_WID (M_AXI_WID), + .M_AXI_WDATA (M_AXI_WDATA), + .M_AXI_WSTRB (M_AXI_WSTRB), + .M_AXI_WLAST (M_AXI_WLAST), + .M_AXI_WUSER (M_AXI_WUSER), + .M_AXI_WVALID (M_AXI_WVALID), + .M_AXI_WREADY (M_AXI_WREADY) + ); + + // Write Response channel. + processing_system7_v5_5_b_atc # + ( + .C_FAMILY (C_FAMILY), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH), + .C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG) + ) write_response_inst + ( + // Global Signals + .ARESET (ARESET), + .ACLK (ACLK), + + // Command Interface (In) + .cmd_b_push (cmd_b_push), + .cmd_b_error (cmd_b_error), + .cmd_b_id (cmd_b_id), + .cmd_b_full (cmd_b_full), + .cmd_b_addr (cmd_b_addr), + .cmd_b_ready (cmd_b_ready), + + // Slave Interface Write Response Ports + .S_AXI_BID (S_AXI_BID), + .S_AXI_BRESP (S_AXI_BRESP), + .S_AXI_BUSER (S_AXI_BUSER), + .S_AXI_BVALID (S_AXI_BVALID), + .S_AXI_BREADY (S_AXI_BREADY), + + // Master Interface Write Response Ports + .M_AXI_BID (M_AXI_BID), + .M_AXI_BRESP (M_AXI_BRESP), + .M_AXI_BUSER (M_AXI_BUSER), + .M_AXI_BVALID (M_AXI_BVALID), + .M_AXI_BREADY (M_AXI_BREADY), + + // Trigger detection + .ERROR_TRIGGER (ERROR_TRIGGER), + .ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID) + ); + + + + ///////////////////////////////////////////////////////////////////////////// + // Handle Read Channels (AR/R) + ///////////////////////////////////////////////////////////////////////////// + // Read Address Port + assign M_AXI_ARID = S_AXI_ARID; + assign M_AXI_ARADDR = S_AXI_ARADDR; + assign M_AXI_ARLEN = S_AXI_ARLEN; + assign M_AXI_ARSIZE = S_AXI_ARSIZE; + assign M_AXI_ARBURST = S_AXI_ARBURST; + assign M_AXI_ARLOCK = S_AXI_ARLOCK; + assign M_AXI_ARCACHE = S_AXI_ARCACHE; + assign M_AXI_ARPROT = S_AXI_ARPROT; + assign M_AXI_ARUSER = S_AXI_ARUSER; + assign M_AXI_ARVALID = S_AXI_ARVALID; + assign S_AXI_ARREADY = M_AXI_ARREADY; + + // Read Data Port + assign S_AXI_RID = M_AXI_RID; + assign S_AXI_RDATA = M_AXI_RDATA; + assign S_AXI_RRESP = M_AXI_RRESP; + assign S_AXI_RLAST = M_AXI_RLAST; + assign S_AXI_RUSER = M_AXI_RUSER; + assign S_AXI_RVALID = M_AXI_RVALID; + assign M_AXI_RREADY = S_AXI_RREADY; + + +endmodule +`default_nettype wire diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v new file mode 100644 index 0000000..25bbc9d --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_aw_atc.v @@ -0,0 +1,298 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Address Write Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// aw_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_aw_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_ADDR_WIDTH = 32, + // Width of all ADDR signals on SI and MI side of checker. + // Range: 32. + parameter integer C_AXI_AWUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_FIFO_DEPTH_LOG = 4 + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface + output reg cmd_w_valid, + output wire cmd_w_check, + output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, + input wire cmd_w_ready, + input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, + input wire cmd_b_ready, + + // Slave Interface Write Address Port + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR, + input wire [4-1:0] S_AXI_AWLEN, + input wire [3-1:0] S_AXI_AWSIZE, + input wire [2-1:0] S_AXI_AWBURST, + input wire [2-1:0] S_AXI_AWLOCK, + input wire [4-1:0] S_AXI_AWCACHE, + input wire [3-1:0] S_AXI_AWPROT, + input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER, + input wire S_AXI_AWVALID, + output wire S_AXI_AWREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID, + output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR, + output wire [4-1:0] M_AXI_AWLEN, + output wire [3-1:0] M_AXI_AWSIZE, + output wire [2-1:0] M_AXI_AWBURST, + output wire [2-1:0] M_AXI_AWLOCK, + output wire [4-1:0] M_AXI_AWCACHE, + output wire [3-1:0] M_AXI_AWPROT, + output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER, + output wire M_AXI_AWVALID, + input wire M_AXI_AWREADY + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + // Constants for burst types. + localparam [2-1:0] C_FIX_BURST = 2'b00; + localparam [2-1:0] C_INCR_BURST = 2'b01; + localparam [2-1:0] C_WRAP_BURST = 2'b10; + + // Constants for size. + localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011; + + // Constants for length. + localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011; + + // Constants for cacheline address. + localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0; + + // Command FIFO settings + localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; + localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + integer index; + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Transaction properties. + wire access_is_incr; + wire access_is_wrap; + wire access_is_coherent; + wire access_optimized_size; + wire incr_addr_boundary; + wire incr_is_optimized; + wire wrap_is_optimized; + wire access_is_optimized; + + // Command FIFO. + wire cmd_w_push; + reg cmd_full; + reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; + wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr; + reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Decode: + // + // Detect if transaction is of correct typ, size and length to qualify as + // an optimized transaction that has to be checked for errors. + // + ///////////////////////////////////////////////////////////////////////////// + + // Transaction burst type. + assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST ); + assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST ); + + // Transaction has to be Coherent. + assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) & + ( S_AXI_AWCACHE[1] == 1'b1 ); + + // Transaction cacheline boundary address. + assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET ); + + // Transaction length & size. + assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) & + ( S_AXI_AWLEN == C_OPTIMIZED_LEN ); + + // Transaction is optimized. + assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary; + assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size; + assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized ); + + + ///////////////////////////////////////////////////////////////////////////// + // Command FIFO: + // + // Since supported write interleaving is only 1, it is safe to use only a + // simple SRL based FIFO as a command queue. + // + ///////////////////////////////////////////////////////////////////////////// + + // Determine when transaction infromation is pushed to the FIFO. + assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full; + + // SRL FIFO Pointer. + always @ (posedge ACLK) begin + if (ARESET) begin + addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_w_push & ~cmd_w_ready ) begin + addr_ptr <= addr_ptr + 1; + end else if ( ~cmd_w_push & cmd_w_ready ) begin + addr_ptr <= addr_ptr - 1; + end + end + end + + // Total number of buffered commands. + assign all_addr_ptr = addr_ptr + cmd_b_addr + 2; + + // FIFO Flags. + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_full <= 1'b0; + cmd_w_valid <= 1'b0; + end else begin + if ( cmd_w_push & ~cmd_w_ready ) begin + cmd_w_valid <= 1'b1; + end else if ( ~cmd_w_push & cmd_w_ready ) begin + cmd_w_valid <= ( addr_ptr != 0 ); + end + if ( cmd_w_push & ~cmd_b_ready ) begin + // Going to full. + cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 ); + end else if ( ~cmd_w_push & cmd_b_ready ) begin + // Pop in middle of queue doesn't affect full status. + cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 ); + end + end + end + + // Infere SRL for storage. + always @ (posedge ACLK) begin + if ( cmd_w_push ) begin + for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin + data_srl[index+1] <= data_srl[index]; + end + data_srl[0] <= {access_is_optimized, S_AXI_AWID}; + end + end + + // Get current transaction info. + assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr]; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Stall commands if FIFO is full. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full; + + // Return ready with push back. + assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full; + + + ///////////////////////////////////////////////////////////////////////////// + // Address Write propagation: + // + // All information is simply forwarded on from the SI- to MI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign M_AXI_AWID = S_AXI_AWID; + assign M_AXI_AWADDR = S_AXI_AWADDR; + assign M_AXI_AWLEN = S_AXI_AWLEN; + assign M_AXI_AWSIZE = S_AXI_AWSIZE; + assign M_AXI_AWBURST = S_AXI_AWBURST; + assign M_AXI_AWLOCK = S_AXI_AWLOCK; + assign M_AXI_AWCACHE = S_AXI_AWCACHE; + assign M_AXI_AWPROT = S_AXI_AWPROT; + assign M_AXI_AWUSER = S_AXI_AWUSER; + + +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v new file mode 100644 index 0000000..36f280f --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_b_atc.v @@ -0,0 +1,413 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Write Response Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// b_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_b_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_BUSER_WIDTH = 1, + // Width of AWUSER signals. + // Range: >= 1. + parameter integer C_FIFO_DEPTH_LOG = 4 + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface + input wire cmd_b_push, + input wire cmd_b_error, + input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id, + output wire cmd_b_ready, + output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr, + output reg cmd_b_full, + + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID, + output reg [2-1:0] S_AXI_BRESP, + output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, + output wire S_AXI_BVALID, + input wire S_AXI_BREADY, + + // Master Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID, + input wire [2-1:0] M_AXI_BRESP, + input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER, + input wire M_AXI_BVALID, + output wire M_AXI_BREADY, + + // Trigger detection + output reg ERROR_TRIGGER, + output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + // Constants for packing levels. + localparam [2-1:0] C_RESP_OKAY = 2'b00; + localparam [2-1:0] C_RESP_EXOKAY = 2'b01; + localparam [2-1:0] C_RESP_SLVERROR = 2'b10; + localparam [2-1:0] C_RESP_DECERR = 2'b11; + + // Command FIFO settings + localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1; + localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG; + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + integer index; + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Command Queue. + reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr; + reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0]; + reg cmd_b_valid; + wire cmd_b_ready_i; + wire inject_error; + wire [C_AXI_ID_WIDTH-1:0] current_id; + + // Search command. + wire found_match; + wire use_match; + wire matching_id; + + // Manage valid command. + wire write_valid_cmd; + reg [C_FIFO_DEPTH-2:0] valid_cmd; + reg [C_FIFO_DEPTH-2:0] updated_valid_cmd; + reg [C_FIFO_DEPTH-2:0] next_valid_cmd; + reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr; + reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr; + + // Pipelined data + reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I; + reg [2-1:0] M_AXI_BRESP_I; + reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I; + reg M_AXI_BVALID_I; + wire M_AXI_BREADY_I; + + + ///////////////////////////////////////////////////////////////////////////// + // Command Queue: + // + // Keep track of depth of Queue to generate full flag. + // + // Also generate valid to mark pressence of commands in Queue. + // + // Maintain Queue and extract data from currently searched entry. + // + ///////////////////////////////////////////////////////////////////////////// + + // SRL FIFO Pointer. + always @ (posedge ACLK) begin + if (ARESET) begin + addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_b_push & ~cmd_b_ready_i ) begin + // Pushing data increase length/addr. + addr_ptr <= addr_ptr + 1; + end else if ( cmd_b_ready_i ) begin + // Collapse addr when data is popped. + addr_ptr <= collapsed_addr_ptr; + end + end + end + + // FIFO Flags. + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_b_full <= 1'b0; + cmd_b_valid <= 1'b0; + end else begin + if ( cmd_b_push & ~cmd_b_ready_i ) begin + cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 ); + cmd_b_valid <= 1'b1; + end else if ( ~cmd_b_push & cmd_b_ready_i ) begin + cmd_b_full <= 1'b0; + cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 ); + end + end + end + + // Infere SRL for storage. + always @ (posedge ACLK) begin + if ( cmd_b_push ) begin + for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin + data_srl[index+1] <= data_srl[index]; + end + data_srl[0] <= {cmd_b_error, cmd_b_id}; + end + end + + // Get current transaction info. + assign {inject_error, current_id} = data_srl[search_addr_ptr]; + + // Assign outputs. + assign cmd_b_addr = collapsed_addr_ptr; + + + ///////////////////////////////////////////////////////////////////////////// + // Search Command Queue: + // + // Search for matching valid command in queue. + // + // A command is found when an valid entry with correct ID is found. The queue + // is search from the oldest entry, i.e. from a high value. + // When new commands are pushed the search address has to be updated to always + // start the search from the oldest available. + // + ///////////////////////////////////////////////////////////////////////////// + + // Handle search addr. + always @ (posedge ACLK) begin + if (ARESET) begin + search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}}; + end else begin + if ( cmd_b_ready_i ) begin + // Collapse addr when data is popped. + search_addr_ptr <= collapsed_addr_ptr; + + end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin + // Skip non valid command. + search_addr_ptr <= search_addr_ptr - 1; + + end else if ( cmd_b_push ) begin + search_addr_ptr <= search_addr_ptr + 1; + + end + end + end + + // Check if searched command is valid and match ID (for existing response on MI side). + assign matching_id = ( M_AXI_BID_I == current_id ); + assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I; + assign use_match = found_match & S_AXI_BREADY; + + + ///////////////////////////////////////////////////////////////////////////// + // Track Used Commands: + // + // Actions that affect Valid Command: + // * When a new command is pushed + // => Shift valid vector one step + // * When a command is used + // => Clear corresponding valid bit + // + ///////////////////////////////////////////////////////////////////////////// + + // Valid command status is updated when a command is used or a new one is pushed. + assign write_valid_cmd = cmd_b_push | cmd_b_ready_i; + + // Update the used command valid bit. + always @ * + begin + updated_valid_cmd = valid_cmd; + updated_valid_cmd[search_addr_ptr] = ~use_match; + end + + // Shift valid vector when command is pushed. + always @ * + begin + if ( cmd_b_push ) begin + next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1}; + end else begin + next_valid_cmd = updated_valid_cmd; + end + end + + // Valid signals for next cycle. + always @ (posedge ACLK) begin + if (ARESET) begin + valid_cmd <= {C_FIFO_WIDTH{1'b0}}; + end else if ( write_valid_cmd ) begin + valid_cmd <= next_valid_cmd; + end + end + + // Detect oldest available command in Queue. + always @ * + begin + // Default to empty. + collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}}; + + for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin + if ( next_valid_cmd[index] ) begin + collapsed_addr_ptr = index; + end + end + end + + + ///////////////////////////////////////////////////////////////////////////// + // Pipe incoming data: + // + // The B channel is piped to improve timing and avoid impact in search + // mechanism due to late arriving signals. + // + ///////////////////////////////////////////////////////////////////////////// + + // Clock data. + always @ (posedge ACLK) begin + if (ARESET) begin + M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}}; + M_AXI_BRESP_I <= 2'b00; + M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}}; + M_AXI_BVALID_I <= 1'b0; + end else begin + if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin + M_AXI_BVALID_I <= 1'b0; + end + if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin + M_AXI_BID_I <= M_AXI_BID; + M_AXI_BRESP_I <= M_AXI_BRESP; + M_AXI_BUSER_I <= M_AXI_BUSER; + M_AXI_BVALID_I <= 1'b1; + end + end + end + + // Generate ready to get new transaction. + assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I; + + + ///////////////////////////////////////////////////////////////////////////// + // Inject Error: + // + // BRESP is modified according to command information. + // + ///////////////////////////////////////////////////////////////////////////// + + // Inject error in response. + always @ * + begin + if ( inject_error ) begin + S_AXI_BRESP = C_RESP_SLVERROR; + end else begin + S_AXI_BRESP = M_AXI_BRESP_I; + end + end + + // Handle interrupt generation. + always @ (posedge ACLK) begin + if (ARESET) begin + ERROR_TRIGGER <= 1'b0; + ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}}; + end else begin + if ( inject_error & cmd_b_ready_i ) begin + ERROR_TRIGGER <= 1'b1; + ERROR_TRANSACTION_ID <= M_AXI_BID_I; + end else begin + ERROR_TRIGGER <= 1'b0; + end + end + end + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Response is passed forward when a matching entry has been found in queue. + // Both ready and valid are set when the command is completed. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match; + + // Return ready with push back. + assign M_AXI_BREADY_I = cmd_b_valid & use_match; + + // Command has been handled. + assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match; + assign cmd_b_ready = cmd_b_ready_i; + + + ///////////////////////////////////////////////////////////////////////////// + // Write Response Propagation: + // + // All information is simply forwarded on from MI- to SI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign S_AXI_BID = M_AXI_BID_I; + assign S_AXI_BUSER = M_AXI_BUSER_I; + + +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v new file mode 100644 index 0000000..0c776b3 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_trace_buffer.v @@ -0,0 +1,310 @@ +// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Filename: trace_buffer.v +// Description: Trace port buffer +//----------------------------------------------------------------------------- +// Structure: This section shows the hierarchical structure of +// pss_wrapper. +// +// --processing_system7 +// | +// --trace_buffer +//----------------------------------------------------------------------------- + + +module processing_system7_v5_5_trace_buffer # + ( + parameter integer FIFO_SIZE = 128, + parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0, + parameter integer C_DELAY_CLKS = 12 + ) + ( + input wire TRACE_CLK, + input wire RST, + input wire TRACE_VALID_IN, + input wire [3:0] TRACE_ATID_IN, + input wire [31:0] TRACE_DATA_IN, + output wire TRACE_VALID_OUT, + output wire [3:0] TRACE_ATID_OUT, + output wire [31:0] TRACE_DATA_OUT + ); + +//------------------------------------------------------------ +// Architecture section +//------------------------------------------------------------ + +// function called clogb2 that returns an integer which has the +// value of the ceiling of the log base 2. + +function integer clogb2 (input integer bit_depth); + integer i; + integer temp_log; + begin + temp_log = 0; + for(i=bit_depth; i > 0; i = i>>1) + clogb2 = temp_log; + temp_log=temp_log+1; + end +endfunction + +localparam DEPTH = clogb2(FIFO_SIZE-1); + +wire [31:0] reset_zeros; +reg [31:0] trace_pedge; // write enable for FIFO +reg [31:0] ti; +reg [31:0] tom; + +reg [3:0] atid; + +reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory + +reg [4:0] dly_ctr; +reg [DEPTH-1:0] fifo_wp; +reg [DEPTH-1:0] fifo_rp; + +reg fifo_re; +wire fifo_empty; +wire fifo_full; +reg fifo_full_reg; + +assign reset_zeros = 32'h0; + + +// Pipeline Stage for Traceport ATID ports + always @(posedge TRACE_CLK) begin + // process pedge_ti + // rising clock edge + if((RST == 1'b1)) begin + atid <= reset_zeros; + end + else begin + atid <= TRACE_ATID_IN; + end + end + + assign TRACE_ATID_OUT = atid; + + ///////////////////////////////////////////// + // Generate FIFO data based on TRACE_VALID_IN + ///////////////////////////////////////////// + generate + if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector + ///////////////////////////////////////////// + + // memory update process + // Update memory when positive edge detected and FIFO not full + always @(posedge TRACE_CLK) begin + if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin + trace_fifo[fifo_wp] <= TRACE_DATA_IN; + end + end + + // fifo write pointer + always @(posedge TRACE_CLK) begin + // process + if(RST == 1'b1) begin + fifo_wp <= {DEPTH{1'b0}}; + end + else if(TRACE_VALID_IN ) begin + if(fifo_wp == (FIFO_SIZE - 1)) begin + if (fifo_empty) begin + fifo_wp <= {DEPTH{1'b0}}; + end + end + else begin + fifo_wp <= fifo_wp + 1; + end + end + end + + + ///////////////////////////////////////////// + // Generate FIFO data based on data edge + ///////////////////////////////////////////// + end else begin : gen_data_edge_detector + ///////////////////////////////////////////// + + + // purpose: check for pos edge on any trace input + always @(posedge TRACE_CLK) begin + // process pedge_ti + // rising clock edge + if((RST == 1'b1)) begin + ti <= reset_zeros; + trace_pedge <= reset_zeros; + end + else begin + ti <= TRACE_DATA_IN; + trace_pedge <= (~ti & TRACE_DATA_IN); + //trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti; + // posedge only + end + end + + // memory update process + // Update memory when positive edge detected and FIFO not full + always @(posedge TRACE_CLK) begin + if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin + trace_fifo[fifo_wp] <= trace_pedge; + end + end + + // fifo write pointer + always @(posedge TRACE_CLK) begin + // process + if(RST == 1'b1) begin + fifo_wp <= {DEPTH{1'b0}}; + end + else if(|(trace_pedge) == 1'b1) begin + if(fifo_wp == (FIFO_SIZE - 1)) begin + if (fifo_empty) begin + fifo_wp <= {DEPTH{1'b0}}; + end + end + else begin + fifo_wp <= fifo_wp + 1; + end + end + end + + + end + endgenerate + + + always @(posedge TRACE_CLK) begin + tom <= trace_fifo[fifo_rp] ; + end + + +// // fifo write pointer +// always @(posedge TRACE_CLK) begin +// // process +// if(RST == 1'b1) begin +// fifo_wp <= {DEPTH{1'b0}}; +// end +// else if(|(trace_pedge) == 1'b1) begin +// if(fifo_wp == (FIFO_SIZE - 1)) begin +// fifo_wp <= {DEPTH{1'b0}}; +// end +// else begin +// fifo_wp <= fifo_wp + 1; +// end +// end +// end + + + // fifo read pointer update + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + fifo_rp <= {DEPTH{1'b0}}; + fifo_re <= 1'b0; + end + else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin + fifo_re <= 1'b1; + if(fifo_rp == (FIFO_SIZE - 1)) begin + fifo_rp <= {DEPTH{1'b0}}; + end + else begin + fifo_rp <= fifo_rp + 1; + end + end + else begin + fifo_re <= 1'b0; + end + end + + // delay counter update + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + dly_ctr <= 5'h0; + end + else if (fifo_re == 1'b1) begin + dly_ctr <= C_DELAY_CLKS-1; + end + else if(dly_ctr != 5'h0) begin + dly_ctr <= dly_ctr - 1; + end + end + + // fifo empty update + assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0; + + // fifo full update + assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0; + + always @(posedge TRACE_CLK) begin + if(RST == 1'b1) begin + fifo_full_reg <= 1'b0; + end + else if (fifo_empty) begin + fifo_full_reg <= 1'b0; + end else begin + fifo_full_reg <= fifo_full; + end + end + +// always @(posedge TRACE_CLK) begin +// if(RST == 1'b1) begin +// fifo_full_reg <= 1'b0; +// end +// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin +// fifo_full_reg <= 1'b1; +// end +// else begin +// fifo_full_reg <= 1'b0; +// end +// end +// + assign TRACE_DATA_OUT = tom; + + assign TRACE_VALID_OUT = fifo_re; + + + + +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v new file mode 100644 index 0000000..8b19a70 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/8fd3/hdl/verilog/processing_system7_v5_5_w_atc.v @@ -0,0 +1,244 @@ +// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved. +// -- +// -- This file contains confidential and proprietary information +// -- of Xilinx, Inc. and is protected under U.S. and +// -- international copyright and other intellectual property +// -- laws. +// -- +// -- DISCLAIMER +// -- This disclaimer is not a license and does not grant any +// -- rights to the materials distributed herewith. Except as +// -- otherwise provided in a valid license issued to you by +// -- Xilinx, and to the maximum extent permitted by applicable +// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// -- (2) Xilinx shall not be liable (whether in contract or tort, +// -- including negligence, or under any other theory of +// -- liability) for any loss or damage of any kind or nature +// -- related to, arising under or in connection with these +// -- materials, including for any direct, or any indirect, +// -- special, incidental, or consequential loss or damage +// -- (including loss of data, profits, goodwill, or any type of +// -- loss or damage suffered as a result of any action brought +// -- by a third party) even if such damage or loss was +// -- reasonably foreseeable or Xilinx had been advised of the +// -- possibility of the same. +// -- +// -- CRITICAL APPLICATIONS +// -- Xilinx products are not designed or intended to be fail- +// -- safe, or for use in any application requiring fail-safe +// -- performance, such as life-support or safety devices or +// -- systems, Class III medical devices, nuclear facilities, +// -- applications related to the deployment of airbags, or any +// -- other applications that could lead to death, personal +// -- injury, or severe property or environmental damage +// -- (individually and collectively, "Critical +// -- Applications"). Customer assumes the sole risk and +// -- liability of any use of Xilinx products in Critical +// -- Applications, subject only to applicable laws and +// -- regulations governing limitations on product liability. +// -- +// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// -- PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// Description: Write Channel for ATC +// +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// w_atc +// +//-------------------------------------------------------------------------- +`timescale 1ps/1ps + + +module processing_system7_v5_5_w_atc # + ( + parameter C_FAMILY = "rtl", + // FPGA Family. Current version: virtex6, spartan6 or later. + parameter integer C_AXI_ID_WIDTH = 4, + // Width of all ID signals on SI and MI side of checker. + // Range: >= 1. + parameter integer C_AXI_DATA_WIDTH = 64, + // Width of all DATA signals on SI and MI side of checker. + // Range: 64. + parameter integer C_AXI_WUSER_WIDTH = 1 + // Width of AWUSER signals. + // Range: >= 1. + ) + ( + // Global Signals + input wire ARESET, + input wire ACLK, + + // Command Interface (In) + input wire cmd_w_valid, + input wire cmd_w_check, + input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id, + output wire cmd_w_ready, + + // Command Interface (Out) + output wire cmd_b_push, + output wire cmd_b_error, + output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id, + input wire cmd_b_full, + + // Slave Interface Write Port + input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID, + input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA, + input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB, + input wire S_AXI_WLAST, + input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER, + input wire S_AXI_WVALID, + output wire S_AXI_WREADY, + + // Master Interface Write Address Port + output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID, + output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA, + output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB, + output wire M_AXI_WLAST, + output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER, + output wire M_AXI_WVALID, + input wire M_AXI_WREADY + ); + + + ///////////////////////////////////////////////////////////////////////////// + // Local params + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Variables for generating parameter controlled instances. + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Functions + ///////////////////////////////////////////////////////////////////////////// + + + ///////////////////////////////////////////////////////////////////////////// + // Internal signals + ///////////////////////////////////////////////////////////////////////////// + + // Detecttion. + wire any_strb_deasserted; + wire incoming_strb_issue; + reg first_word; + reg strb_issue; + + // Data flow. + wire data_pop; + wire cmd_b_push_blocked; + reg cmd_b_push_i; + + + ///////////////////////////////////////////////////////////////////////////// + // Detect error: + // + // Detect and accumulate error when a transaction shall be scanned for + // potential issues. + // Accumulation of error is restarted for each ne transaction. + // + ///////////////////////////////////////////////////////////////////////////// + + // Check stobe information + assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} ); + assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted; + + // Keep track of first word in a transaction. + always @ (posedge ACLK) begin + if (ARESET) begin + first_word <= 1'b1; + end else if ( data_pop ) begin + first_word <= S_AXI_WLAST; + end + end + + // Keep track of error status. + always @ (posedge ACLK) begin + if (ARESET) begin + strb_issue <= 1'b0; + cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}}; + end else if ( data_pop ) begin + if ( first_word ) begin + strb_issue <= incoming_strb_issue; + end else begin + strb_issue <= incoming_strb_issue | strb_issue; + end + cmd_b_id <= cmd_w_id; + end + end + + assign cmd_b_error = strb_issue; + + + ///////////////////////////////////////////////////////////////////////////// + // Control command queue to B: + // + // Push command to B queue when all data for the transaction has flowed + // through. + // Delay pipelined command until there is room in the Queue. + // + ///////////////////////////////////////////////////////////////////////////// + + // Detect when data is popped. + assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // Push command when last word in transfered (pipelined). + always @ (posedge ACLK) begin + if (ARESET) begin + cmd_b_push_i <= 1'b0; + end else begin + cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked; + end + end + + // Detect if pipelined push is blocked. + assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full; + + // Assign output. + assign cmd_b_push = cmd_b_push_i & ~cmd_b_full; + + + ///////////////////////////////////////////////////////////////////////////// + // Transaction Throttling: + // + // Stall commands if FIFO is full or there is no valid command information + // from AW. + // + ///////////////////////////////////////////////////////////////////////////// + + // Propagate masked valid. + assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // Return ready with push back. + assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked; + + // End of burst. + assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST; + + + ///////////////////////////////////////////////////////////////////////////// + // Write propagation: + // + // All information is simply forwarded on from the SI- to MI-Side untouched. + // + ///////////////////////////////////////////////////////////////////////////// + + // 1:1 mapping. + assign M_AXI_WID = S_AXI_WID; + assign M_AXI_WDATA = S_AXI_WDATA; + assign M_AXI_WSTRB = S_AXI_WSTRB; + assign M_AXI_WLAST = S_AXI_WLAST; + assign M_AXI_WUSER = S_AXI_WUSER; + + +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v new file mode 100644 index 0000000..d6ec7f8 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v @@ -0,0 +1,670 @@ +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axis to vector +// A generic module to merge all axi signals into one signal called payload. +// This is strictly wires, so no clk, reset, aclken, valid/ready are required. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_axi2vector # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter integer C_AXI_PROTOCOL = 0, + parameter integer C_AXI_ID_WIDTH = 4, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AWPAYLOAD_WIDTH = 61, + parameter integer C_WPAYLOAD_WIDTH = 73, + parameter integer C_BPAYLOAD_WIDTH = 6, + parameter integer C_ARPAYLOAD_WIDTH = 61, + parameter integer C_RPAYLOAD_WIDTH = 69 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Slave Interface Write Address Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen, + input wire [3-1:0] s_axi_awsize, + input wire [2-1:0] s_axi_awburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock, + input wire [4-1:0] s_axi_awcache, + input wire [3-1:0] s_axi_awprot, + input wire [4-1:0] s_axi_awregion, + input wire [4-1:0] s_axi_awqos, + input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + + // Slave Interface Write Data Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid, + input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + input wire s_axi_wlast, + input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + + // Slave Interface Write Response Ports + output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output wire [2-1:0] s_axi_bresp, + output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + + // Slave Interface Read Address Ports + input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen, + input wire [3-1:0] s_axi_arsize, + input wire [2-1:0] s_axi_arburst, + input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock, + input wire [4-1:0] s_axi_arcache, + input wire [3-1:0] s_axi_arprot, + input wire [4-1:0] s_axi_arregion, + input wire [4-1:0] s_axi_arqos, + input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + + // Slave Interface Read Data Ports + output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output wire [2-1:0] s_axi_rresp, + output wire s_axi_rlast, + output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + + // payloads + output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload, + output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload, + input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload, + output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload, + input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload +); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +`include "axi_infrastructure_v1_1_0.vh" + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +// AXI4, AXI4LITE, AXI3 packing +assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr; +assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot; + +assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata; +assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb; + +assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH]; + +assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr; +assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot; + +assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH]; +assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH]; + +generate + if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing + assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize; + assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst; + assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache; + assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen; + assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock; + assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid; + assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos; + + assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast; + if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing + assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid; + end + else begin : gen_no_axi3_wid_packing + end + + assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH]; + + assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize; + assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst; + assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache; + assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen; + assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock; + assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid; + assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos; + + assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH]; + assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH]; + + if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals + assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion; + assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion; + end + else begin : gen_no_region_signals + end + if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals + assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser; + assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser; + assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH]; + assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser; + assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH]; + end + else begin : gen_no_user_signals + assign s_axi_buser = 'b0; + assign s_axi_ruser = 'b0; + end + end + else begin : gen_axi4lite_packing + assign s_axi_bid = 'b0; + assign s_axi_buser = 'b0; + + assign s_axi_rlast = 1'b1; + assign s_axi_rid = 'b0; + assign s_axi_ruser = 'b0; + end +endgenerate +endmodule + +`default_nettype wire + + +// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// Description: SRL based FIFO for AXIS/AXI Channels. +//-------------------------------------------------------------------------- + + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_axic_srl_fifo #( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter C_FAMILY = "virtex7", + parameter integer C_PAYLOAD_WIDTH = 1, + parameter integer C_FIFO_DEPTH = 16 // Range: 4-16. +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + input wire aclk, // Clock + input wire aresetn, // Reset + input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data + input wire s_valid, // Input data valid + output reg s_ready, // Input data ready + output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data + output reg m_valid, // Output data valid + input wire m_ready // Output data ready +); +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +// ceiling logb2 +function integer f_clogb2 (input integer size); + integer s; + begin + s = size; + s = s - 1; + for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1) + s = s >> 1; + end +endfunction // clogb2 + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// +localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH); + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// +reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index; +wire [4-1:0] fifo_addr; +wire push; +wire pop ; +reg areset_r1; + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +always @(posedge aclk) begin + areset_r1 <= ~aresetn; +end + +always @(posedge aclk) begin + if (~aresetn) begin + fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}}; + end + else begin + fifo_index <= push & ~pop ? fifo_index + 1'b1 : + ~push & pop ? fifo_index - 1'b1 : + fifo_index; + end +end + +assign push = s_valid & s_ready; + +always @(posedge aclk) begin + if (~aresetn) begin + s_ready <= 1'b0; + end + else begin + s_ready <= areset_r1 ? 1'b1 : + push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 : + ~push & pop ? 1'b1 : + s_ready; + end +end + +assign pop = m_valid & m_ready; + +always @(posedge aclk) begin + if (~aresetn) begin + m_valid <= 1'b0; + end + else begin + m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 : + push & ~pop ? 1'b1 : + m_valid; + end +end + +generate + if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr + assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; + assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}}; + end + else begin : gen_fifo_addr + assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0]; + end +endgenerate + + +generate + genvar i; + for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit + SRL16E + u_srl_fifo( + .Q ( m_payload[i] ) , + .A0 ( fifo_addr[0] ) , + .A1 ( fifo_addr[1] ) , + .A2 ( fifo_addr[2] ) , + .A3 ( fifo_addr[3] ) , + .CE ( push ) , + .CLK ( aclk ) , + .D ( s_payload[i] ) + ); + end +endgenerate + +endmodule + +`default_nettype wire + + +// (c) Copyright 2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +//----------------------------------------------------------------------------- +// +// axi to vector +// A generic module to merge all axi signals into one signal called payload. +// This is strictly wires, so no clk, reset, aclken, valid/ready are required. +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// + +`timescale 1ps/1ps +`default_nettype none + +(* DowngradeIPIdentifiedWarnings="yes" *) +module axi_infrastructure_v1_1_0_vector2axi # +( +/////////////////////////////////////////////////////////////////////////////// +// Parameter Definitions +/////////////////////////////////////////////////////////////////////////////// + parameter integer C_AXI_PROTOCOL = 0, + parameter integer C_AXI_ID_WIDTH = 4, + parameter integer C_AXI_ADDR_WIDTH = 32, + parameter integer C_AXI_DATA_WIDTH = 32, + parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0, + parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0, + parameter integer C_AXI_AWUSER_WIDTH = 1, + parameter integer C_AXI_WUSER_WIDTH = 1, + parameter integer C_AXI_BUSER_WIDTH = 1, + parameter integer C_AXI_ARUSER_WIDTH = 1, + parameter integer C_AXI_RUSER_WIDTH = 1, + parameter integer C_AWPAYLOAD_WIDTH = 61, + parameter integer C_WPAYLOAD_WIDTH = 73, + parameter integer C_BPAYLOAD_WIDTH = 6, + parameter integer C_ARPAYLOAD_WIDTH = 61, + parameter integer C_RPAYLOAD_WIDTH = 69 +) +( +/////////////////////////////////////////////////////////////////////////////// +// Port Declarations +/////////////////////////////////////////////////////////////////////////////// + // Slave Interface Write Address Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen, + output wire [3-1:0] m_axi_awsize, + output wire [2-1:0] m_axi_awburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock, + output wire [4-1:0] m_axi_awcache, + output wire [3-1:0] m_axi_awprot, + output wire [4-1:0] m_axi_awregion, + output wire [4-1:0] m_axi_awqos, + output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + + // Slave Interface Write Data Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid, + output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, + output wire m_axi_wlast, + output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + + // Slave Interface Write Response Ports + input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [2-1:0] m_axi_bresp, + input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + + // Slave Interface Read Address Ports + output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen, + output wire [3-1:0] m_axi_arsize, + output wire [2-1:0] m_axi_arburst, + output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock, + output wire [4-1:0] m_axi_arcache, + output wire [3-1:0] m_axi_arprot, + output wire [4-1:0] m_axi_arregion, + output wire [4-1:0] m_axi_arqos, + output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + + // Slave Interface Read Data Ports + input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [2-1:0] m_axi_rresp, + input wire m_axi_rlast, + input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + + // payloads + input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload, + input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload, + output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload, + input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload, + output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload +); + +//////////////////////////////////////////////////////////////////////////////// +// Functions +//////////////////////////////////////////////////////////////////////////////// +`include "axi_infrastructure_v1_1_0.vh" + +//////////////////////////////////////////////////////////////////////////////// +// Local parameters +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Wires/Reg declarations +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// BEGIN RTL +//////////////////////////////////////////////////////////////////////////////// + +// AXI4, AXI4LITE, AXI3 packing +assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH]; +assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH]; + +assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH]; +assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH]; + +assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp; + +assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH]; +assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH]; + +assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata; +assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp; + +generate + if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing + assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ; + assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH]; + assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH]; + assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ; + assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ; + assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ; + assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ; + + assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ; + if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing + assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ; + end + else begin : gen_no_axi3_wid_packing + assign m_axi_wid = 1'b0; + end + + assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid; + + assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ; + assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH]; + assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH]; + assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ; + assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ; + assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ; + assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ; + + assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast; + assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ; + + if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals + assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH]; + assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH]; + end + else begin : gen_no_region_signals + assign m_axi_awregion = 'b0; + assign m_axi_arregion = 'b0; + end + if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals + assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH]; + assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ; + assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ; + assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH]; + assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ; + end + else begin : gen_no_user_signals + assign m_axi_awuser = 'b0; + assign m_axi_wuser = 'b0; + assign m_axi_aruser = 'b0; + end + end + else begin : gen_axi4lite_packing + assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; + assign m_axi_awburst = 'b0; + assign m_axi_awcache = 'b0; + assign m_axi_awlen = 'b0; + assign m_axi_awlock = 'b0; + assign m_axi_awid = 'b0; + assign m_axi_awqos = 'b0; + + assign m_axi_wlast = 1'b1; + assign m_axi_wid = 'b0; + + + assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3; + assign m_axi_arburst = 'b0; + assign m_axi_arcache = 'b0; + assign m_axi_arlen = 'b0; + assign m_axi_arlock = 'b0; + assign m_axi_arid = 'b0; + assign m_axi_arqos = 'b0; + + assign m_axi_awregion = 'b0; + assign m_axi_arregion = 'b0; + + assign m_axi_awuser = 'b0; + assign m_axi_wuser = 'b0; + assign m_axi_aruser = 'b0; + end +endgenerate +endmodule + +`default_nettype wire + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/sim/design_1.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/sim/design_1.v new file mode 100644 index 0000000..7005c4f --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/sim/design_1.v @@ -0,0 +1,141 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +//Date : Fri Aug 17 17:41:43 2018 +//Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +//Command : generate_target design_1.bd +//Design : design_1 +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *) +module design_1 + (DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + led_op); + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [1:0]DDR_dm; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [15:0]DDR_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [1:0]DDR_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [1:0]DDR_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [31:0]FIXED_IO_mio; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb; + (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.LED_OP DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.LED_OP, LAYERED_METADATA undef" *) output led_op; + + wire led_0_led_op; + wire [14:0]processing_system7_0_DDR_ADDR; + wire [2:0]processing_system7_0_DDR_BA; + wire processing_system7_0_DDR_CAS_N; + wire processing_system7_0_DDR_CKE; + wire processing_system7_0_DDR_CK_N; + wire processing_system7_0_DDR_CK_P; + wire processing_system7_0_DDR_CS_N; + wire [1:0]processing_system7_0_DDR_DM; + wire [15:0]processing_system7_0_DDR_DQ; + wire [1:0]processing_system7_0_DDR_DQS_N; + wire [1:0]processing_system7_0_DDR_DQS_P; + wire processing_system7_0_DDR_ODT; + wire processing_system7_0_DDR_RAS_N; + wire processing_system7_0_DDR_RESET_N; + wire processing_system7_0_DDR_WE_N; + wire processing_system7_0_FCLK_CLK0; + wire processing_system7_0_FIXED_IO_DDR_VRN; + wire processing_system7_0_FIXED_IO_DDR_VRP; + wire [31:0]processing_system7_0_FIXED_IO_MIO; + wire processing_system7_0_FIXED_IO_PS_CLK; + wire processing_system7_0_FIXED_IO_PS_PORB; + wire processing_system7_0_FIXED_IO_PS_SRSTB; + + assign led_op = led_0_led_op; + design_1_led_0_0 led_0 + (.led_op(led_0_led_op), + .m_clock(processing_system7_0_FCLK_CLK0)); + design_1_processing_system7_0_0 processing_system7_0 + (.DDR_Addr(DDR_addr[14:0]), + .DDR_BankAddr(DDR_ba[2:0]), + .DDR_CAS_n(DDR_cas_n), + .DDR_CKE(DDR_cke), + .DDR_CS_n(DDR_cs_n), + .DDR_Clk(DDR_ck_p), + .DDR_Clk_n(DDR_ck_n), + .DDR_DM(DDR_dm[1:0]), + .DDR_DQ(DDR_dq[15:0]), + .DDR_DQS(DDR_dqs_p[1:0]), + .DDR_DQS_n(DDR_dqs_n[1:0]), + .DDR_DRSTB(DDR_reset_n), + .DDR_ODT(DDR_odt), + .DDR_RAS_n(DDR_ras_n), + .DDR_VRN(FIXED_IO_ddr_vrn), + .DDR_VRP(FIXED_IO_ddr_vrp), + .DDR_WEB(DDR_we_n), + .FCLK_CLK0(processing_system7_0_FCLK_CLK0), + .GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .I2C0_SCL_I(1'b0), + .I2C0_SDA_I(1'b0), + .IRQ_F2P(1'b0), + .MIO(FIXED_IO_mio[31:0]), + .M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0), + .M_AXI_GP0_ARREADY(1'b0), + .M_AXI_GP0_AWREADY(1'b0), + .M_AXI_GP0_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_BRESP({1'b0,1'b0}), + .M_AXI_GP0_BVALID(1'b0), + .M_AXI_GP0_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_RLAST(1'b0), + .M_AXI_GP0_RRESP({1'b0,1'b0}), + .M_AXI_GP0_RVALID(1'b0), + .M_AXI_GP0_WREADY(1'b0), + .PS_CLK(FIXED_IO_ps_clk), + .PS_PORB(FIXED_IO_ps_porb), + .PS_SRSTB(FIXED_IO_ps_srstb), + .SDIO0_CDN(1'b0), + .SDIO0_CLK_FB(1'b0), + .SDIO0_CMD_I(1'b0), + .SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}), + .SDIO0_WP(1'b0), + .SPI0_MISO_I(1'b0), + .SPI0_MOSI_I(1'b0), + .SPI0_SCLK_I(1'b0), + .SPI0_SS_I(1'b0), + .SPI1_MISO_I(1'b0), + .SPI1_MOSI_I(1'b0), + .SPI1_SCLK_I(1'b0), + .SPI1_SS_I(1'b0), + .UART0_RX(1'b1), + .USB0_VBUS_PWRFAULT(1'b0)); +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/synth/design_1.v b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/synth/design_1.v new file mode 100644 index 0000000..7005c4f --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/synth/design_1.v @@ -0,0 +1,141 @@ +//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 +//Date : Fri Aug 17 17:41:43 2018 +//Host : DESKTOP-4H60MTS running 64-bit major release (build 9200) +//Command : generate_target design_1.bd +//Design : design_1 +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=1,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "design_1.hwdef" *) +module design_1 + (DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + led_op); + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) inout [14:0]DDR_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [1:0]DDR_dm; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [15:0]DDR_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [1:0]DDR_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) inout [1:0]DDR_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_we_n; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout FIXED_IO_ddr_vrn; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout FIXED_IO_ddr_vrp; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [31:0]FIXED_IO_mio; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout FIXED_IO_ps_clk; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) inout FIXED_IO_ps_porb; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout FIXED_IO_ps_srstb; + (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.LED_OP DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.LED_OP, LAYERED_METADATA undef" *) output led_op; + + wire led_0_led_op; + wire [14:0]processing_system7_0_DDR_ADDR; + wire [2:0]processing_system7_0_DDR_BA; + wire processing_system7_0_DDR_CAS_N; + wire processing_system7_0_DDR_CKE; + wire processing_system7_0_DDR_CK_N; + wire processing_system7_0_DDR_CK_P; + wire processing_system7_0_DDR_CS_N; + wire [1:0]processing_system7_0_DDR_DM; + wire [15:0]processing_system7_0_DDR_DQ; + wire [1:0]processing_system7_0_DDR_DQS_N; + wire [1:0]processing_system7_0_DDR_DQS_P; + wire processing_system7_0_DDR_ODT; + wire processing_system7_0_DDR_RAS_N; + wire processing_system7_0_DDR_RESET_N; + wire processing_system7_0_DDR_WE_N; + wire processing_system7_0_FCLK_CLK0; + wire processing_system7_0_FIXED_IO_DDR_VRN; + wire processing_system7_0_FIXED_IO_DDR_VRP; + wire [31:0]processing_system7_0_FIXED_IO_MIO; + wire processing_system7_0_FIXED_IO_PS_CLK; + wire processing_system7_0_FIXED_IO_PS_PORB; + wire processing_system7_0_FIXED_IO_PS_SRSTB; + + assign led_op = led_0_led_op; + design_1_led_0_0 led_0 + (.led_op(led_0_led_op), + .m_clock(processing_system7_0_FCLK_CLK0)); + design_1_processing_system7_0_0 processing_system7_0 + (.DDR_Addr(DDR_addr[14:0]), + .DDR_BankAddr(DDR_ba[2:0]), + .DDR_CAS_n(DDR_cas_n), + .DDR_CKE(DDR_cke), + .DDR_CS_n(DDR_cs_n), + .DDR_Clk(DDR_ck_p), + .DDR_Clk_n(DDR_ck_n), + .DDR_DM(DDR_dm[1:0]), + .DDR_DQ(DDR_dq[15:0]), + .DDR_DQS(DDR_dqs_p[1:0]), + .DDR_DQS_n(DDR_dqs_n[1:0]), + .DDR_DRSTB(DDR_reset_n), + .DDR_ODT(DDR_odt), + .DDR_RAS_n(DDR_ras_n), + .DDR_VRN(FIXED_IO_ddr_vrn), + .DDR_VRP(FIXED_IO_ddr_vrp), + .DDR_WEB(DDR_we_n), + .FCLK_CLK0(processing_system7_0_FCLK_CLK0), + .GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .I2C0_SCL_I(1'b0), + .I2C0_SDA_I(1'b0), + .IRQ_F2P(1'b0), + .MIO(FIXED_IO_mio[31:0]), + .M_AXI_GP0_ACLK(processing_system7_0_FCLK_CLK0), + .M_AXI_GP0_ARREADY(1'b0), + .M_AXI_GP0_AWREADY(1'b0), + .M_AXI_GP0_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_BRESP({1'b0,1'b0}), + .M_AXI_GP0_BVALID(1'b0), + .M_AXI_GP0_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP0_RLAST(1'b0), + .M_AXI_GP0_RRESP({1'b0,1'b0}), + .M_AXI_GP0_RVALID(1'b0), + .M_AXI_GP0_WREADY(1'b0), + .PS_CLK(FIXED_IO_ps_clk), + .PS_PORB(FIXED_IO_ps_porb), + .PS_SRSTB(FIXED_IO_ps_srstb), + .SDIO0_CDN(1'b0), + .SDIO0_CLK_FB(1'b0), + .SDIO0_CMD_I(1'b0), + .SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}), + .SDIO0_WP(1'b0), + .SPI0_MISO_I(1'b0), + .SPI0_MOSI_I(1'b0), + .SPI0_SCLK_I(1'b0), + .SPI0_SS_I(1'b0), + .SPI1_MISO_I(1'b0), + .SPI1_MOSI_I(1'b0), + .SPI1_SCLK_I(1'b0), + .SPI1_SS_I(1'b0), + .UART0_RX(1'b1), + .USB0_VBUS_PWRFAULT(1'b0)); +endmodule diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui new file mode 100644 index 0000000..2114b15 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui @@ -0,0 +1,19 @@ +{ + ExpandedHierarchyInLayout: "", + guistr: "# # String gsaved with Nlview 6.8.5 2018-01-30 bk=1.4354 VDI=40 GEI=35 GUI=JA:1.6 non-TLS +# -string -flagsOSRD +preplace port DDR -pg 1 -y -120 -defaultsOSRD +preplace port FIXED_IO -pg 1 -y -160 -defaultsOSRD +preplace port led_op -pg 1 -y -140 -defaultsOSRD +preplace inst led_0 -pg 1 -lvl 2 -y -210 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 1 -y -270 -defaultsOSRD +preplace netloc processing_system7_0_DDR 1 1 2 NJ -430 670J +preplace netloc processing_system7_0_FIXED_IO 1 1 2 NJ -410 680J +preplace netloc processing_system7_0_FCLK_CLK0 1 0 2 0 -510 420 +preplace netloc led_0_led_op 1 2 1 660 +levelinfo -pg 1 -20 210 550 700 -top -630 -bot 410 +", +} +{ + da_ps7_cnt: "1", +} diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/mref/led/component.xml b/LED_Blink/LED_Blink.srcs/sources_1/bd/mref/led/component.xml new file mode 100644 index 0000000..7d4dbf5 --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/mref/led/component.xml @@ -0,0 +1,130 @@ + + + xilinx.com + module_ref + led + 1.0 + + + m_clock + + + + + + + CLK + + + m_clock + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + led + + + viewChecksum + 0b867e83 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + led + + + viewChecksum + 0b867e83 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + + + m_clock + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + led_op + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/led_v1_0.tcl + tclSource + CHECKSUM_f64a5dae + XGUI_VERSION_2 + + + + xilinx.com:module_ref:led:1.0 + + + Component_Name + led_v1_0 + + + + + + zynq + + + /UserIP + + led_v1_0 + level_1 + module_ref + + IPI + + 1 + 2018-08-17T08:41:28Z + + + 2018.2 + + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/bd/mref/led/xgui/led_v1_0.tcl b/LED_Blink/LED_Blink.srcs/sources_1/bd/mref/led/xgui/led_v1_0.tcl new file mode 100644 index 0000000..66195ab --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/bd/mref/led/xgui/led_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/LED_Blink/LED_Blink.srcs/sources_1/new/led.v b/LED_Blink/LED_Blink.srcs/sources_1/new/led.v new file mode 100644 index 0000000..50381ba --- /dev/null +++ b/LED_Blink/LED_Blink.srcs/sources_1/new/led.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2018/08/17 11:04:10 +// Design Name: +// Module Name: led +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +`define PERIOD 25000000 + +module led( + input m_clock, + output led_op + ); + reg [31:0] cnt = 0; + reg led_op_r = 0; + + assign led_op = led_op_r; + + always @(posedge m_clock) begin + if(cnt < `PERIOD) + cnt <= cnt + 1; + else begin + cnt <= 0; + led_op_r <= ~led_op_r; + end + end +endmodule diff --git a/LED_Blink/LED_Blink.xpr b/LED_Blink/LED_Blink.xpr new file mode 100644 index 0000000..eb8babd --- /dev/null +++ b/LED_Blink/LED_Blink.xpr @@ -0,0 +1,278 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/_readme.txt b/zynqberrydemo1/_readme.txt new file mode 100644 index 0000000..4a7d866 --- /dev/null +++ b/zynqberrydemo1/_readme.txt @@ -0,0 +1,73 @@ +Project Description +========================================================================== +Important notes: + 1.Please use short path name on Windows OS. The OS allows only 256 characters in normal path. + 2.Please do not use space character on path name. +========================================================================== +1. Create Command Files and open documentation links: + On Windows OS: run "_create_win_setup.cmd" and follow setup instructions + On Linux OS: run "_create_linux_setup.sh" and follow setup instructions +============================== +2. Create Vivado Project on Windows OS use instructions from option 1 of: + ===== + https://wiki.trenz-electronic.de/display/PD/Vivado+Projects + ===== + 1.Modify start setting: + ===== + Edit "design_basic_settings.cmd" with text editor: + Set your vivado installation path for edit: + @set XILDIR=C:\Xilinx + @set VIVADO_VERSION=2017.1 + In this example the it search in + C:\Xilinx\Vivado\2017.1 for VIVADO + C:\Xilinx\SDK\2017.1 for SDK (optional for some functionality, HSI/SDK) + C:\Xilinx\Vivado_Lab\2017.1 for VIVADO Labtools (optional for some functionality) + Set the correct part number for your pcb variant (see board_files/TE0710_board_files.csv), edit: + @set PARTNUMBER=1 + ===== + 2.Run "vivado_create_project_guimode.cmd" +============================== +2. Create Vivado Project on Linux use instructions from option 1 of: + ===== + https://wiki.trenz-electronic.de/display/PD/Vivado+Projects + ===== + 1.Modify start setting: + ===== + Edit "design_basic_settings.sh" with text editor: + Set your vivado installation path for edit: + @set XILDIR=/opt/Xilinx + @set VIVADO_VERSION=2017.1 + In this example the it search in + /opt/Vivado/2017.1 for VIVADO + /opt/SDK/2017.1 for SDK (optional for some functionality, HSI/SDK) + /opt/Vivado_Lab/2017.1 for VIVADO Labtools (optional for some functionality) + Set the correct part number for your pcb variant (see board_files/TE0710_board_files.csv), edit: + @set PARTNUMBER=1 + ===== + 2.Run "vivado_create_project_guimode.sh" +============================== +There are also other options available: + ===== + https://wiki.trenz-electronic.de/display/PD/Vivado+Projects +============================== +Attention: + ===== + Run design_clear_design_folders.cmd/sh clear all generated files and folders (vivado, workspace(hsi & sdk), vlog,...)! +============================== +Basic documentations: + ===== + Project Delivery: + https://wiki.trenz-electronic.de/display/PD/Project+Delivery + == + VIVADO/SDK/SDSoC + https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264 + == + Trenz Electronic SoMs + https://wiki.trenz-electronic.de/display/PD/All+Trenz+Electronic+SoMs + == + Additional Information for the are available on the download page of the design + https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic //Reference_Design// +============================== +===== +NOTES +===== \ No newline at end of file diff --git a/zynqberrydemo1/block_design/zsys_bd.tcl b/zynqberrydemo1/block_design/zsys_bd.tcl new file mode 100644 index 0000000..6b47c52 --- /dev/null +++ b/zynqberrydemo1/block_design/zsys_bd.tcl @@ -0,0 +1,1126 @@ +TE::UTILS::te_msg TE_BD-0 INFO "This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0726_7s:part0:3.1, FPGA: xc7z007sclg225-1 at 2017-06-12T13:37:13." +TE::UTILS::te_msg TE_BD-1 INFO "This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag # #TE_MOD# on the Block-Design tcl-file." + +################################################################ +# This is a generated script based on design: zsys +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2017.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source zsys_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z007sclg225-1 + set_property BOARD_PART trenz.biz:te0726_7s:part0:3.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +set design_name zsys + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: video_out +proc create_hier_cell_video_out { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_video_out() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 CLKWIZ_AXI + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 VDMA_AXI + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 VIDEO_OUT_AXI + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 VTC_AXI + + # Create pins + create_bd_pin -dir I -type clk axi_aclk + create_bd_pin -dir I -from 0 -to 0 -type rst axi_int_aresetn + create_bd_pin -dir I -from 0 -to 0 -type rst axi_per_aresetn + create_bd_pin -dir O hdmi_clk_n + create_bd_pin -dir O hdmi_clk_p + create_bd_pin -dir O -from 2 -to 0 hdmi_data_n + create_bd_pin -dir O -from 2 -to 0 hdmi_data_p + create_bd_pin -dir I -type clk ref_clk + create_bd_pin -dir O -type intr tx_dma_int + + # Create instance: Video_IO_2_HDMI_TMDS_0, and set properties + set Video_IO_2_HDMI_TMDS_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:Video_IO_2_HDMI_TMDS:1.0 Video_IO_2_HDMI_TMDS_0 ] + set_property -dict [ list \ +CONFIG.C_CLK_SWAP {true} \ +CONFIG.C_D0_SWAP {true} \ +CONFIG.C_INT_CLOCKING {false} \ +CONFIG.C_VIDEO_MODE {0} \ + ] $Video_IO_2_HDMI_TMDS_0 + + # Create instance: axi_mem_intercon, and set properties + set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] + set_property -dict [ list \ +CONFIG.NUM_MI {1} \ + ] $axi_mem_intercon + + # Create instance: axi_vdma_0, and set properties + set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0 ] + set_property -dict [ list \ +CONFIG.c_include_s2mm {0} \ +CONFIG.c_m_axi_mm2s_data_width {32} \ +CONFIG.c_mm2s_genlock_mode {0} \ +CONFIG.c_mm2s_linebuffer_depth {1024} \ +CONFIG.c_mm2s_max_burst_length {16} \ +CONFIG.c_num_fstores {1} \ +CONFIG.c_s2mm_genlock_mode {0} \ + ] $axi_vdma_0 + + # Create instance: axis_fb_conv_0, and set properties + set axis_fb_conv_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_fb_conv:1.0 axis_fb_conv_0 ] + + # Create instance: clk_wiz_1, and set properties + set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.4 clk_wiz_1 ] + set_property -dict [ list \ +CONFIG.CLKIN1_JITTER_PS {50.0} \ +CONFIG.CLKOUT1_JITTER {333.287} \ +CONFIG.CLKOUT1_PHASE_ERROR {322.999} \ +CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {74.250} \ +CONFIG.CLKOUT2_JITTER {256.477} \ +CONFIG.CLKOUT2_PHASE_ERROR {322.999} \ +CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {371.250} \ +CONFIG.CLKOUT2_USED {true} \ +CONFIG.CLKOUT3_JITTER {325.031} \ +CONFIG.CLKOUT3_PHASE_ERROR {569.784} \ +CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {100.000} \ +CONFIG.CLKOUT3_USED {false} \ +CONFIG.CLKOUT4_JITTER {357.108} \ +CONFIG.CLKOUT4_PHASE_ERROR {569.784} \ +CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {100.000} \ +CONFIG.CLKOUT4_USED {false} \ +CONFIG.JITTER_SEL {Min_O_Jitter} \ +CONFIG.MMCM_BANDWIDTH {HIGH} \ +CONFIG.MMCM_CLKFBOUT_MULT_F {37.125} \ +CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ +CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ +CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \ +CONFIG.MMCM_CLKOUT1_DIVIDE {2} \ +CONFIG.MMCM_CLKOUT2_DIVIDE {1} \ +CONFIG.MMCM_CLKOUT3_DIVIDE {1} \ +CONFIG.MMCM_DIVCLK_DIVIDE {10} \ +CONFIG.NUM_OUT_CLKS {2} \ +CONFIG.USE_DYN_RECONFIG {true} \ + ] $clk_wiz_1 + + # Create instance: v_axi4s_vid_out_0, and set properties + set v_axi4s_vid_out_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_axi4s_vid_out:4.0 v_axi4s_vid_out_0 ] + set_property -dict [ list \ +CONFIG.C_HAS_ASYNC_CLK {1} \ + ] $v_axi4s_vid_out_0 + + # Create instance: v_tc_0, and set properties + set v_tc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_tc:6.1 v_tc_0 ] + set_property -dict [ list \ +CONFIG.GEN_F0_VBLANK_HEND {1280} \ +CONFIG.GEN_F0_VBLANK_HSTART {1280} \ +CONFIG.GEN_F0_VFRAME_SIZE {750} \ +CONFIG.GEN_F0_VSYNC_HEND {1280} \ +CONFIG.GEN_F0_VSYNC_HSTART {1280} \ +CONFIG.GEN_F0_VSYNC_VEND {729} \ +CONFIG.GEN_F0_VSYNC_VSTART {724} \ +CONFIG.GEN_F1_VBLANK_HEND {1280} \ +CONFIG.GEN_F1_VBLANK_HSTART {1280} \ +CONFIG.GEN_F1_VFRAME_SIZE {750} \ +CONFIG.GEN_F1_VSYNC_HEND {1280} \ +CONFIG.GEN_F1_VSYNC_HSTART {1280} \ +CONFIG.GEN_F1_VSYNC_VEND {729} \ +CONFIG.GEN_F1_VSYNC_VSTART {724} \ +CONFIG.GEN_HACTIVE_SIZE {1280} \ +CONFIG.GEN_HFRAME_SIZE {1650} \ +CONFIG.GEN_HSYNC_END {1430} \ +CONFIG.GEN_HSYNC_START {1390} \ +CONFIG.GEN_VACTIVE_SIZE {720} \ +CONFIG.HAS_AXI4_LITE {true} \ +CONFIG.VIDEO_MODE {720p} \ +CONFIG.enable_detection {false} \ +CONFIG.max_clocks_per_line {4096} \ +CONFIG.max_lines_per_frame {2048} \ + ] $v_tc_0 + + # Create interface connections + connect_bd_intf_net -intf_net CLKWIZ_AXI_1 [get_bd_intf_pins CLKWIZ_AXI] [get_bd_intf_pins clk_wiz_1/s_axi_lite] + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins VIDEO_OUT_AXI] [get_bd_intf_pins axi_mem_intercon/M00_AXI] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins VDMA_AXI] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins VTC_AXI] [get_bd_intf_pins v_tc_0/ctrl] + connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_fb_conv_0/S_AXIS] + connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_MM2S [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S] + connect_bd_intf_net -intf_net axis_fb_conv_0_video_out [get_bd_intf_pins axis_fb_conv_0/video_out] [get_bd_intf_pins v_axi4s_vid_out_0/video_in] + connect_bd_intf_net -intf_net v_axi4s_vid_out_0_vid_io_out [get_bd_intf_pins Video_IO_2_HDMI_TMDS_0/vid_io_in] [get_bd_intf_pins v_axi4s_vid_out_0/vid_io_out] + connect_bd_intf_net -intf_net v_tc_0_vtiming_out [get_bd_intf_pins v_axi4s_vid_out_0/vtiming_in] [get_bd_intf_pins v_tc_0/vtiming_out] + + # Create port connections + connect_bd_net -net ARESETN_2 [get_bd_pins axi_int_aresetn] [get_bd_pins axi_mem_intercon/ARESETN] + connect_bd_net -net Video_IO_2_HDMI_TMDS_0_hdmi_clk_n [get_bd_pins hdmi_clk_n] [get_bd_pins Video_IO_2_HDMI_TMDS_0/hdmi_clk_n] + connect_bd_net -net Video_IO_2_HDMI_TMDS_0_hdmi_clk_p [get_bd_pins hdmi_clk_p] [get_bd_pins Video_IO_2_HDMI_TMDS_0/hdmi_clk_p] + connect_bd_net -net Video_IO_2_HDMI_TMDS_0_hdmi_data_n [get_bd_pins hdmi_data_n] [get_bd_pins Video_IO_2_HDMI_TMDS_0/hdmi_data_n] + connect_bd_net -net Video_IO_2_HDMI_TMDS_0_hdmi_data_p [get_bd_pins hdmi_data_p] [get_bd_pins Video_IO_2_HDMI_TMDS_0/hdmi_data_p] + connect_bd_net -net aclk_1 [get_bd_pins axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_vdma_0/m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axis_mm2s_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk] [get_bd_pins axis_fb_conv_0/s_axis_aclk] [get_bd_pins clk_wiz_1/s_axi_aclk] [get_bd_pins v_axi4s_vid_out_0/aclk] [get_bd_pins v_tc_0/s_axi_aclk] + connect_bd_net -net aresetn_1 [get_bd_pins axi_per_aresetn] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_vdma_0/axi_resetn] [get_bd_pins axis_fb_conv_0/s_axis_aresetn] [get_bd_pins clk_wiz_1/s_axi_aresetn] [get_bd_pins v_axi4s_vid_out_0/aresetn] [get_bd_pins v_tc_0/s_axi_aresetn] + connect_bd_net -net axi_vdma_0_mm2s_introut [get_bd_pins tx_dma_int] [get_bd_pins axi_vdma_0/mm2s_introut] + connect_bd_net -net clk_in1_1 [get_bd_pins ref_clk] [get_bd_pins clk_wiz_1/clk_in1] + connect_bd_net -net clk_wiz_1_clk_out2 [get_bd_pins Video_IO_2_HDMI_TMDS_0/video_clk5x_in] [get_bd_pins clk_wiz_1/clk_out2] + connect_bd_net -net clk_wiz_1_locked [get_bd_pins Video_IO_2_HDMI_TMDS_0/lock_in] [get_bd_pins clk_wiz_1/locked] + connect_bd_net -net v_axi4s_vid_out_0_vtg_ce [get_bd_pins v_axi4s_vid_out_0/vtg_ce] [get_bd_pins v_tc_0/gen_clken] + connect_bd_net -net video_clk_in_1 [get_bd_pins Video_IO_2_HDMI_TMDS_0/video_clk_in] [get_bd_pins clk_wiz_1/clk_out1] [get_bd_pins v_axi4s_vid_out_0/vid_io_out_clk] [get_bd_pins v_tc_0/clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: video_in +proc create_hier_cell_video_in { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_video_in() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 VDMA_AXI + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 VIDEO_IN_AXI + + # Create pins + create_bd_pin -dir I -type clk axi_aclk + create_bd_pin -dir I -from 0 -to 0 -type rst axi_aresetn + create_bd_pin -dir I -from 0 -to 0 axi_int_aresetn + create_bd_pin -dir I colors_mode + create_bd_pin -dir I csi_clk_n + create_bd_pin -dir I csi_clk_p + create_bd_pin -dir I -from 0 -to 0 csi_data_lp_n + create_bd_pin -dir I -from 0 -to 0 csi_data_lp_p + create_bd_pin -dir I -from 1 -to 0 csi_data_n + create_bd_pin -dir I -from 1 -to 0 csi_data_p + create_bd_pin -dir I -from 0 -to 0 enable + create_bd_pin -dir I -type rst ext_reset_in + create_bd_pin -dir I processing_clk + create_bd_pin -dir I ref_clk + create_bd_pin -dir O rx_dma_int + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ +CONFIG.NUM_MI {1} \ + ] $axi_interconnect_0 + + # Create instance: axi_vdma_0, and set properties + set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0 ] + set_property -dict [ list \ +CONFIG.c_include_mm2s {0} \ +CONFIG.c_include_s2mm_dre {1} \ +CONFIG.c_m_axi_s2mm_data_width {64} \ +CONFIG.c_mm2s_genlock_mode {0} \ +CONFIG.c_num_fstores {1} \ +CONFIG.c_s2mm_genlock_mode {0} \ +CONFIG.c_s2mm_linebuffer_depth {4096} \ +CONFIG.c_s2mm_max_burst_length {32} \ + ] $axi_vdma_0 + + # Create instance: axis_data_fifo_0, and set properties + set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ] + set_property -dict [ list \ +CONFIG.FIFO_DEPTH {16384} \ +CONFIG.HAS_TLAST {1} \ +CONFIG.IS_ACLK_ASYNC {1} \ +CONFIG.TDATA_NUM_BYTES {2} \ +CONFIG.TUSER_WIDTH {1} \ + ] $axis_data_fifo_0 + + # Create instance: axis_data_fifo_3, and set properties + set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_3 ] + + # Create instance: axis_data_fifo_4, and set properties + set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_4 ] + set_property -dict [ list \ +CONFIG.FIFO_DEPTH {4096} \ +CONFIG.IS_ACLK_ASYNC {1} \ + ] $axis_data_fifo_4 + + # Create instance: axis_raw_demosaic_0, and set properties + set axis_raw_demosaic_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_raw_demosaic:1.0 axis_raw_demosaic_0 ] + set_property -dict [ list \ +CONFIG.C_COLOR_POS {2} \ +CONFIG.C_IN_TYPE {1} \ +CONFIG.C_MODE {1} \ + ] $axis_raw_demosaic_0 + + # Create instance: axis_raw_unpack_0, and set properties + set axis_raw_unpack_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_raw_unpack:1.0 axis_raw_unpack_0 ] + set_property -dict [ list \ +CONFIG.C_IMP_TYPE {1} \ +CONFIG.C_OUT_TYPE {1} \ + ] $axis_raw_unpack_0 + + # Create instance: csi2_d_phy_rx_0, and set properties + set csi2_d_phy_rx_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:csi2_d_phy_rx:1.0 csi2_d_phy_rx_0 ] + set_property -dict [ list \ +CONFIG.C_ADD_IDELAYCTRL {true} \ +CONFIG.C_CALIB_WAIT {8191} \ +CONFIG.C_NUM_LP_LANES {1} \ +CONFIG.C_RATE_LIMIT {50} \ +CONFIG.C_USE_DELAY {true} \ + ] $csi2_d_phy_rx_0 + + # Create instance: csi_to_axis_0, and set properties + set csi_to_axis_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:csi_to_axis:1.0 csi_to_axis_0 ] + set_property -dict [ list \ +CONFIG.C_TIMEOUT {255} \ + ] $csi_to_axis_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create interface connections + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins csi_to_axis_0/M_AXIS] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins VDMA_AXI] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins VIDEO_IN_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_S2MM [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins axi_vdma_0/M_AXI_S2MM] + connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins axis_raw_unpack_0/S_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axis_data_fifo_3/M_AXIS] [get_bd_intf_pins axis_raw_demosaic_0/S_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins axi_vdma_0/S_AXIS_S2MM] [get_bd_intf_pins axis_data_fifo_4/M_AXIS] + connect_bd_intf_net -intf_net axis_raw_demosaic_0_M_AXIS [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins axis_raw_demosaic_0/M_AXIS] + connect_bd_intf_net -intf_net axis_raw_unpack_0_M_AXIS [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins axis_raw_unpack_0/M_AXIS] + connect_bd_intf_net -intf_net csi2_d_phy_rx_0_RX_MIPI_PPI [get_bd_intf_pins csi2_d_phy_rx_0/RX_MIPI_PPI] [get_bd_intf_pins csi_to_axis_0/RX_MIPI_PPI] + connect_bd_intf_net -intf_net csi_to_axis_0_data_err [get_bd_intf_pins csi2_d_phy_rx_0/data_err] [get_bd_intf_pins csi_to_axis_0/data_err] + + # Create port connections + connect_bd_net -net CSI_AXIS_RSTN [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins csi_to_axis_0/m_axis_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net ENABLE_STREAM [get_bd_pins enable] [get_bd_pins csi_to_axis_0/enable_in] + connect_bd_net -net axi_int_aresetn_1 [get_bd_pins axi_int_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] + connect_bd_net -net axi_vdma_0_s2mm_introut [get_bd_pins rx_dma_int] [get_bd_pins axi_vdma_0/s2mm_introut] + connect_bd_net -net colors_mode_1 [get_bd_pins colors_mode] [get_bd_pins axis_raw_demosaic_0/colors_mode] + connect_bd_net -net csi_clk_n_1 [get_bd_pins csi_clk_n] [get_bd_pins csi2_d_phy_rx_0/clk_rxn] + connect_bd_net -net csi_clk_p_1 [get_bd_pins csi_clk_p] [get_bd_pins csi2_d_phy_rx_0/clk_rxp] + connect_bd_net -net csi_data_lp_n_1 [get_bd_pins csi_data_lp_n] [get_bd_pins csi2_d_phy_rx_0/data_lp_n] + connect_bd_net -net csi_data_lp_p_1 [get_bd_pins csi_data_lp_p] [get_bd_pins csi2_d_phy_rx_0/data_lp_p] + connect_bd_net -net csi_data_n_1 [get_bd_pins csi_data_n] [get_bd_pins csi2_d_phy_rx_0/data_rxn] + connect_bd_net -net csi_data_p_1 [get_bd_pins csi_data_p] [get_bd_pins csi2_d_phy_rx_0/data_rxp] + connect_bd_net -net ext_reset_in_1 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] + connect_bd_net -net m_axi_aclk [get_bd_pins axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_vdma_0/m_axi_s2mm_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk] [get_bd_pins axi_vdma_0/s_axis_s2mm_aclk] [get_bd_pins axis_data_fifo_4/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins axi_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_vdma_0/axi_resetn] [get_bd_pins axis_data_fifo_4/m_axis_aresetn] + connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axis_data_fifo_0/m_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_raw_demosaic_0/axis_aresetn] [get_bd_pins axis_raw_unpack_0/axis_aresetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn] + connect_bd_net -net processing_clk_1 [get_bd_pins processing_clk] [get_bd_pins axis_data_fifo_0/m_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_raw_demosaic_0/axis_aclk] [get_bd_pins axis_raw_unpack_0/axis_aclk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] + connect_bd_net -net ref_clk_in_1 [get_bd_pins ref_clk] [get_bd_pins csi2_d_phy_rx_0/in_delay_clk] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins csi2_d_phy_rx_0/rxbyteclkhs] [get_bd_pins csi_to_axis_0/m_axis_aclk] [get_bd_pins csi_to_axis_0/rxbyteclkhs] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: resets +proc create_hier_cell_resets { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_resets() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + + # Create pins + create_bd_pin -dir I -type clk axi_clk + create_bd_pin -dir O -from 0 -to 0 -type rst axi_int_aresetn + create_bd_pin -dir O -from 0 -to 0 -type rst axi_per_aresetn + create_bd_pin -dir I -type rst ext_reset_in + + # Create instance: rst_processing_system7_0_50M, and set properties + set rst_processing_system7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_processing_system7_0_50M ] + + # Create port connections + connect_bd_net -net ext_reset_in_1 [get_bd_pins ext_reset_in] [get_bd_pins rst_processing_system7_0_50M/ext_reset_in] + connect_bd_net -net rst_processing_system7_0_50M_interconnect_aresetn [get_bd_pins axi_int_aresetn] [get_bd_pins rst_processing_system7_0_50M/interconnect_aresetn] + connect_bd_net -net rst_processing_system7_0_50M_peripheral_aresetn [get_bd_pins axi_per_aresetn] [get_bd_pins rst_processing_system7_0_50M/peripheral_aresetn] + connect_bd_net -net slowest_sync_clk_1 [get_bd_pins axi_clk] [get_bd_pins rst_processing_system7_0_50M/slowest_sync_clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: audio +proc create_hier_cell_audio { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_audio() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMA_RX_ACK + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMA_RX_REQ + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMA_TX_ACK + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMA_TX_REQ + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn + + # Create pins + create_bd_pin -dir I audio_clk + create_bd_pin -dir I -type clk axi_aclk + create_bd_pin -dir I -from 0 -to 0 -type rst axi_resetn + create_bd_pin -dir O pwm_l_out + create_bd_pin -dir O pwm_r_out + + # Create instance: axi_i2s_adi_0, and set properties + set axi_i2s_adi_0 [ create_bd_cell -type ip -vlnv digilentinc.com:user:axi_i2s_adi:1.2 axi_i2s_adi_0 ] + set_property -dict [ list \ +CONFIG.C_DMA_TYPE {1} \ + ] $axi_i2s_adi_0 + + # Create instance: axis_to_i2s_0, and set properties + set axis_to_i2s_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_to_i2s:1.0 axis_to_i2s_0 ] + + # Create instance: i2s_to_pwm_0, and set properties + set i2s_to_pwm_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:i2s_to_pwm:1.0 i2s_to_pwm_0 ] + + # Create instance: xadc_wiz_0, and set properties + set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ] + set_property -dict [ list \ +CONFIG.ADC_CONVERSION_RATE {1000} \ +CONFIG.DCLK_FREQUENCY {150} \ +CONFIG.ENABLE_AXI4STREAM {true} \ +CONFIG.ENABLE_RESET {true} \ +CONFIG.ENABLE_VCCDDRO_ALARM {false} \ +CONFIG.ENABLE_VCCPAUX_ALARM {false} \ +CONFIG.ENABLE_VCCPINT_ALARM {false} \ +CONFIG.INTERFACE_SELECTION {None} \ +CONFIG.OT_ALARM {false} \ +CONFIG.SINGLE_CHANNEL_SELECTION {VP_VN} \ +CONFIG.USER_TEMP_ALARM {false} \ +CONFIG.VCCAUX_ALARM {false} \ +CONFIG.VCCINT_ALARM {false} \ + ] $xadc_wiz_0 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins Vp_Vn] [get_bd_intf_pins xadc_wiz_0/Vp_Vn] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins DMA_TX_ACK] [get_bd_intf_pins axi_i2s_adi_0/DMA_TX_ACK] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins DMA_TX_REQ] [get_bd_intf_pins axi_i2s_adi_0/DMA_TX_REQ] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins DMA_RX_REQ] [get_bd_intf_pins axi_i2s_adi_0/DMA_RX_REQ] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins DMA_RX_ACK] [get_bd_intf_pins axi_i2s_adi_0/DMA_RX_ACK] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins S00_AXI] [get_bd_intf_pins axi_i2s_adi_0/S00_AXI] + connect_bd_intf_net -intf_net xadc_wiz_0_M_AXIS [get_bd_intf_pins axis_to_i2s_0/s_axis] [get_bd_intf_pins xadc_wiz_0/M_AXIS] + + # Create port connections + connect_bd_net -net BCLK [get_bd_pins axi_i2s_adi_0/BCLK_O] [get_bd_pins axis_to_i2s_0/i2s_bclk] [get_bd_pins i2s_to_pwm_0/i2s_bclk] + connect_bd_net -net DATA_CLK_I_1 [get_bd_pins audio_clk] [get_bd_pins axi_i2s_adi_0/DATA_CLK_I] + connect_bd_net -net LRCLK [get_bd_pins axi_i2s_adi_0/LRCLK_O] [get_bd_pins axis_to_i2s_0/i2s_lrclk] [get_bd_pins i2s_to_pwm_0/i2s_lrclk] + connect_bd_net -net i2s_to_pwm_0_pwm_l_out [get_bd_pins pwm_l_out] [get_bd_pins i2s_to_pwm_0/pwm_l_out] + connect_bd_net -net i2s_to_pwm_0_pwm_r_out [get_bd_pins pwm_r_out] [get_bd_pins i2s_to_pwm_0/pwm_r_out] + connect_bd_net -net m_axis_resetn_1 [get_bd_pins axi_resetn] [get_bd_pins axi_i2s_adi_0/DMA_REQ_RX_RSTN] [get_bd_pins axi_i2s_adi_0/DMA_REQ_TX_RSTN] [get_bd_pins axi_i2s_adi_0/s00_axi_aresetn] [get_bd_pins axis_to_i2s_0/s_axis_aresetn] [get_bd_pins xadc_wiz_0/m_axis_resetn] + connect_bd_net -net play_sdata [get_bd_pins axi_i2s_adi_0/SDATA_O] [get_bd_pins i2s_to_pwm_0/i2s_sdata] + connect_bd_net -net rec_sdata [get_bd_pins axi_i2s_adi_0/SDATA_I] [get_bd_pins axis_to_i2s_0/i2s_sdata] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins axi_aclk] [get_bd_pins axi_i2s_adi_0/DMA_REQ_RX_ACLK] [get_bd_pins axi_i2s_adi_0/DMA_REQ_TX_ACLK] [get_bd_pins axi_i2s_adi_0/s00_axi_aclk] [get_bd_pins axis_to_i2s_0/s_axis_aclk] [get_bd_pins i2s_to_pwm_0/clk_in] [get_bd_pins xadc_wiz_0/m_axis_aclk] [get_bd_pins xadc_wiz_0/s_axis_aclk] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports +# #TE_MOD# set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] +# #TE_MOD# set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + set GPIO_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_1 ] + set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ] + + # Create ports + set PWM_L [ create_bd_port -dir O PWM_L ] + set PWM_R [ create_bd_port -dir O PWM_R ] + set csi_c_clk_n [ create_bd_port -dir I csi_c_clk_n ] + set csi_c_clk_p [ create_bd_port -dir I csi_c_clk_p ] + set csi_d_lp_n [ create_bd_port -dir I -from 0 -to 0 csi_d_lp_n ] + set csi_d_lp_p [ create_bd_port -dir I -from 0 -to 0 csi_d_lp_p ] + set csi_d_n [ create_bd_port -dir I -from 1 -to 0 csi_d_n ] + set csi_d_p [ create_bd_port -dir I -from 1 -to 0 csi_d_p ] + set hdmi_clk_n [ create_bd_port -dir O hdmi_clk_n ] + set hdmi_clk_p [ create_bd_port -dir O hdmi_clk_p ] + set hdmi_data_n [ create_bd_port -dir O -from 2 -to 0 hdmi_data_n ] + set hdmi_data_p [ create_bd_port -dir O -from 2 -to 0 hdmi_data_p ] + + # Create instance: audio + create_hier_cell_audio [current_bd_instance .] audio + + # Create instance: axi_reg32_0, and set properties + set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0 ] + set_property -dict [ list \ +CONFIG.C_NUM_RO_REG {1} \ +CONFIG.C_NUM_WR_REG {1} \ + ] $axi_reg32_0 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] +# #TE_MOD#_Add next line# + apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1"} [get_bd_cells processing_system7_0] +# #TE_MOD#_Add next line# + set tcl_ext [];if { [catch {set tcl_ext [glob -join -dir ${TE::BOARDDEF_PATH}/carrier_extension/ *_preset.tcl]}] } {};foreach carrier_ext $tcl_ext { source $carrier_ext}; + set_property -dict [ list \ +CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ +CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {160.000000} \ +CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {12.307692} \ +CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_CLK0_FREQ {160000000} \ +CONFIG.PCW_CLK1_FREQ {100000000} \ +CONFIG.PCW_CLK2_FREQ {200000000} \ +CONFIG.PCW_CLK3_FREQ {12307692} \ +CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ +CONFIG.PCW_DM_WIDTH {2} \ +CONFIG.PCW_DQS_WIDTH {2} \ +CONFIG.PCW_DQ_WIDTH {16} \ +CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_EN_CLK1_PORT {1} \ +CONFIG.PCW_EN_CLK2_PORT {1} \ +CONFIG.PCW_EN_CLK3_PORT {1} \ +CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_GPIO {1} \ +CONFIG.PCW_EN_EMIO_I2C0 {1} \ +CONFIG.PCW_EN_EMIO_PJTAG {0} \ +CONFIG.PCW_EN_EMIO_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_SPI0 {0} \ +CONFIG.PCW_EN_EMIO_SPI1 {0} \ +CONFIG.PCW_EN_EMIO_TTC0 {1} \ +CONFIG.PCW_EN_EMIO_TTC1 {0} \ +CONFIG.PCW_EN_EMIO_UART0 {0} \ +CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ +CONFIG.PCW_EN_GPIO {1} \ +CONFIG.PCW_EN_I2C0 {1} \ +CONFIG.PCW_EN_I2C1 {1} \ +CONFIG.PCW_EN_QSPI {1} \ +CONFIG.PCW_EN_SDIO0 {0} \ +CONFIG.PCW_EN_SDIO1 {1} \ +CONFIG.PCW_EN_SPI0 {0} \ +CONFIG.PCW_EN_SPI1 {0} \ +CONFIG.PCW_EN_TTC0 {1} \ +CONFIG.PCW_EN_TTC1 {0} \ +CONFIG.PCW_EN_UART0 {0} \ +CONFIG.PCW_EN_UART1 {1} \ +CONFIG.PCW_EN_USB0 {1} \ +CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ +CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {4} \ +CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {26} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {5} \ +CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ +CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ +CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {160} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {12.288} \ +CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ +CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \ +CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \ +CONFIG.PCW_FTM_CTI_IN0 {} \ +CONFIG.PCW_FTM_CTI_IN2 {} \ +CONFIG.PCW_FTM_CTI_OUT0 {} \ +CONFIG.PCW_FTM_CTI_OUT2 {} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_EMIO_GPIO_IO {24} \ +CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {24} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ +CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \ +CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \ +CONFIG.PCW_I2C0_I2C0_IO {EMIO} \ +CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \ +CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \ +CONFIG.PCW_I2C1_I2C1_IO {MIO 48 .. 49} \ +CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \ +CONFIG.PCW_I2C_RESET_ENABLE {0} \ +CONFIG.PCW_I2C_RESET_SELECT {} \ +CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ +CONFIG.PCW_SD0_GRP_WP_IO {} \ +CONFIG.PCW_SD1_GRP_CD_ENABLE {1} \ +CONFIG.PCW_SD1_GRP_CD_IO {MIO 0} \ +CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \ +CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {16} \ +CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ +CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS0_IO {} \ +CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS2_IO {} \ +CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI1_GRP_SS0_IO {} \ +CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ +CONFIG.PCW_SPI1_GRP_SS2_IO {} \ +CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ +CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {32} \ +CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_TTC0_TTC0_IO {EMIO} \ +CONFIG.PCW_TTC1_TTC1_IO {} \ +CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ +CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {16} \ +CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ +CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NONE} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_IO {MIO 7} \ +CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ +CONFIG.PCW_USB_RESET_ENABLE {1} \ +CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ +CONFIG.PCW_USE_DMA0 {1} \ +CONFIG.PCW_USE_DMA1 {1} \ +CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ +CONFIG.PCW_USE_M_AXI_GP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP1 {1} \ + ] $processing_system7_0 + +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {780} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {550} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {53.995} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {77.166} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {700} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {520} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {57.044} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {81.244} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {86.1835} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {86.1835} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {86.1835} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {86.1835} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.614} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.434} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.029} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.005} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.433} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.318} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.070} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.082} \ +# #TE_MOD# #Empty Line + # Create instance: processing_system7_0_axi_periph, and set properties + set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ] + set_property -dict [ list \ +CONFIG.NUM_MI {6} \ + ] $processing_system7_0_axi_periph + + # Create instance: resets + create_hier_cell_resets [current_bd_instance .] resets + + # Create instance: video_in + create_hier_cell_video_in [current_bd_instance .] video_in + + # Create instance: video_out + create_hier_cell_video_out [current_bd_instance .] video_out + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ +CONFIG.NUM_PORTS {2} \ + ] $xlconcat_0 + + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + set_property -dict [ list \ +CONFIG.DIN_FROM {0} \ +CONFIG.DIN_TO {0} \ +CONFIG.DIN_WIDTH {32} \ + ] $xlslice_0 + + # Create instance: xlslice_1, and set properties + set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + set_property -dict [ list \ +CONFIG.DIN_FROM {1} \ +CONFIG.DIN_TO {1} \ +CONFIG.DIN_WIDTH {32} \ +CONFIG.DOUT_WIDTH {1} \ + ] $xlslice_1 + + # Create interface connections + connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_ports Vp_Vn] [get_bd_intf_pins audio/Vp_Vn] + connect_bd_intf_net -intf_net audio_DMA_RX_REQ [get_bd_intf_pins audio/DMA_RX_REQ] [get_bd_intf_pins processing_system7_0/DMA1_REQ] + connect_bd_intf_net -intf_net audio_DMA_TX_REQ [get_bd_intf_pins audio/DMA_TX_REQ] [get_bd_intf_pins processing_system7_0/DMA0_REQ] +# #TE_MOD# connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_DMA0_ACK [get_bd_intf_pins audio/DMA_TX_ACK] [get_bd_intf_pins processing_system7_0/DMA0_ACK] + connect_bd_intf_net -intf_net processing_system7_0_DMA1_ACK [get_bd_intf_pins audio/DMA_RX_ACK] [get_bd_intf_pins processing_system7_0/DMA1_ACK] +# #TE_MOD# connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] + connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_1] [get_bd_intf_pins processing_system7_0/GPIO_0] + connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI] [get_bd_intf_pins video_out/VDMA_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M01_AXI] [get_bd_intf_pins video_in/VDMA_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M02_AXI [get_bd_intf_pins audio/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_reg32_0/S_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M03_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M04_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M04_AXI] [get_bd_intf_pins video_out/VTC_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M05_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M05_AXI] [get_bd_intf_pins video_out/CLKWIZ_AXI] + connect_bd_intf_net -intf_net video_in_M00_AXI [get_bd_intf_pins processing_system7_0/S_AXI_HP1] [get_bd_intf_pins video_in/VIDEO_IN_AXI] + connect_bd_intf_net -intf_net video_out_M00_AXI [get_bd_intf_pins processing_system7_0/S_AXI_HP0] [get_bd_intf_pins video_out/VIDEO_OUT_AXI] + + # Create port connections + connect_bd_net -net audio_pwm_l_out [get_bd_ports PWM_L] [get_bd_pins audio/pwm_l_out] + connect_bd_net -net audio_pwm_r_out [get_bd_ports PWM_R] [get_bd_pins audio/pwm_r_out] + connect_bd_net -net axi_reg32_0_WR0 [get_bd_pins axi_reg32_0/WR0] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] + connect_bd_net -net csi_c_clk_n_1 [get_bd_ports csi_c_clk_n] [get_bd_pins video_in/csi_clk_n] + connect_bd_net -net csi_c_clk_p_1 [get_bd_ports csi_c_clk_p] [get_bd_pins video_in/csi_clk_p] + connect_bd_net -net csi_d_lp_n_1 [get_bd_ports csi_d_lp_n] [get_bd_pins video_in/csi_data_lp_n] + connect_bd_net -net csi_d_lp_p_1 [get_bd_ports csi_d_lp_p] [get_bd_pins video_in/csi_data_lp_p] + connect_bd_net -net csi_d_n_1 [get_bd_ports csi_d_n] [get_bd_pins video_in/csi_data_n] + connect_bd_net -net csi_d_p_1 [get_bd_ports csi_d_p] [get_bd_pins video_in/csi_data_p] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins audio/axi_aclk] [get_bd_pins axi_reg32_0/s_axi_aclk] [get_bd_pins processing_system7_0/DMA0_ACLK] [get_bd_pins processing_system7_0/DMA1_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/M01_ACLK] [get_bd_pins processing_system7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0_axi_periph/M03_ACLK] [get_bd_pins processing_system7_0_axi_periph/M04_ACLK] [get_bd_pins processing_system7_0_axi_periph/M05_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins resets/axi_clk] [get_bd_pins video_in/axi_aclk] [get_bd_pins video_in/processing_clk] [get_bd_pins video_out/axi_aclk] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_pins processing_system7_0/FCLK_CLK2] [get_bd_pins video_in/ref_clk] [get_bd_pins video_out/ref_clk] + connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_pins audio/audio_clk] [get_bd_pins processing_system7_0/FCLK_CLK3] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins resets/ext_reset_in] [get_bd_pins video_in/ext_reset_in] + connect_bd_net -net rst_processing_system7_0_50M_interconnect_aresetn [get_bd_pins processing_system7_0_axi_periph/ARESETN] [get_bd_pins resets/axi_int_aresetn] [get_bd_pins video_in/axi_int_aresetn] [get_bd_pins video_out/axi_int_aresetn] + connect_bd_net -net rst_processing_system7_0_50M_peripheral_aresetn [get_bd_pins audio/axi_resetn] [get_bd_pins axi_reg32_0/s_axi_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M03_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M04_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M05_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins resets/axi_per_aresetn] [get_bd_pins video_in/axi_aresetn] [get_bd_pins video_out/axi_per_aresetn] + connect_bd_net -net video_in_rx_dma_int [get_bd_pins video_in/rx_dma_int] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net video_out_hdmi_clk_n [get_bd_ports hdmi_clk_n] [get_bd_pins video_out/hdmi_clk_n] + connect_bd_net -net video_out_hdmi_clk_p [get_bd_ports hdmi_clk_p] [get_bd_pins video_out/hdmi_clk_p] + connect_bd_net -net video_out_hdmi_data_n [get_bd_ports hdmi_data_n] [get_bd_pins video_out/hdmi_data_n] + connect_bd_net -net video_out_hdmi_data_p [get_bd_ports hdmi_data_p] [get_bd_pins video_out/hdmi_data_p] + connect_bd_net -net video_out_mm2s_introut [get_bd_pins video_out/tx_dma_int] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlslice_0_Dout [get_bd_pins video_in/enable] [get_bd_pins xlslice_0/Dout] + connect_bd_net -net xlslice_1_Dout [get_bd_pins video_in/colors_mode] [get_bd_pins xlslice_1/Dout] + + # Create address segments + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs audio/axi_i2s_adi_0/S00_AXI/S00_AXI_reg] SEG_axi_i2s_adi_0_S00_AXI_reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_reg32_0/S_AXI/S_AXI_reg] SEG_axi_reg32_0_S_AXI_reg + create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video_out/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video_in/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg1 + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video_out/clk_wiz_1/s_axi_lite/Reg] SEG_clk_wiz_1_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video_out/v_tc_0/ctrl/Reg] SEG_v_tc_0_Reg + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces video_in/axi_vdma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces video_out/axi_vdma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + + diff --git a/zynqberrydemo1/board_files/TE0726/1.0/board.xml b/zynqberrydemo1/board_files/TE0726/1.0/board.xml new file mode 100644 index 0000000..01bb3f3 --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_01 Board File Image + + + + + + + 0.1 + + + + + 1.0 + + + ZYNQ-7 TE0726-01 ZynqBerry Board (form factor Raspberry Pi) with 128MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV01. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726/1.0/part0_pins.xml b/zynqberrydemo1/board_files/TE0726/1.0/part0_pins.xml new file mode 100644 index 0000000..f7ce2ba --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726/1.0/preset.xml b/zynqberrydemo1/board_files/TE0726/1.0/preset.xml new file mode 100644 index 0000000..aa55c3d --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/1.0/preset.xml @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726/2.1/board.xml b/zynqberrydemo1/board_files/TE0726/2.1/board.xml new file mode 100644 index 0000000..5fe89cf --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/2.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_R Board File Image + + + + + + + 0.3 + 0.2 + + + + + 2.1 + + + ZYNQ-7 TE0726-R ZynqBerry Board (form factor Raspberry Pi) with 128MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726/2.1/part0_pins.xml b/zynqberrydemo1/board_files/TE0726/2.1/part0_pins.xml new file mode 100644 index 0000000..1d0deec --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/2.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726/2.1/preset.xml b/zynqberrydemo1/board_files/TE0726/2.1/preset.xml new file mode 100644 index 0000000..e6f98eb --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/2.1/preset.xml @@ -0,0 +1,256 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726/3.1/board.xml b/zynqberrydemo1/board_files/TE0726/3.1/board.xml new file mode 100644 index 0000000..7facc84 --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/3.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_M Board File Image + + + + + + + 0.3 + 0.2 + + + + + 3.1 + + + ZYNQ-7 TE0726-M ZynqBerry Board (form factor Raspberry Pi) with 512MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726/3.1/part0_pins.xml b/zynqberrydemo1/board_files/TE0726/3.1/part0_pins.xml new file mode 100644 index 0000000..2c43aef --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/3.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726/3.1/preset.xml b/zynqberrydemo1/board_files/TE0726/3.1/preset.xml new file mode 100644 index 0000000..c9afaf8 --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726/3.1/preset.xml @@ -0,0 +1,283 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726_7S/3.1/board.xml b/zynqberrydemo1/board_files/TE0726_7S/3.1/board.xml new file mode 100644 index 0000000..14d4db1 --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726_7S/3.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_M Board File Image + + + + + + + 0.3 + 0.2 + + + + + 3.1 + + + ZYNQ-7S TE0726-07S ZynqBerry Board (form factor Raspberry Pi) with single ARM Cortex-A9, 512MB Memory, 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726_7S/3.1/part0_pins.xml b/zynqberrydemo1/board_files/TE0726_7S/3.1/part0_pins.xml new file mode 100644 index 0000000..0449cdd --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726_7S/3.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/zynqberrydemo1/board_files/TE0726_7S/3.1/preset.xml b/zynqberrydemo1/board_files/TE0726_7S/3.1/preset.xml new file mode 100644 index 0000000..764f8c6 --- /dev/null +++ b/zynqberrydemo1/board_files/TE0726_7S/3.1/preset.xml @@ -0,0 +1,283 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo1/console/readme.txt b/zynqberrydemo1/console/readme.txt new file mode 100644 index 0000000..922ccd0 --- /dev/null +++ b/zynqberrydemo1/console/readme.txt @@ -0,0 +1,4 @@ +Console command files for reference design root directory. +Use console command file for generation: +_create_linux_setup.sh +_create_win_setup.cmd \ No newline at end of file diff --git a/zynqberrydemo1/constraints/_i_bitgen_common.xdc b/zynqberrydemo1/constraints/_i_bitgen_common.xdc new file mode 100644 index 0000000..5c862d0 --- /dev/null +++ b/zynqberrydemo1/constraints/_i_bitgen_common.xdc @@ -0,0 +1,7 @@ +# +# Common BITGEN related settings for TE0726 +# +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + diff --git a/zynqberrydemo1/constraints/_i_common.xdc b/zynqberrydemo1/constraints/_i_common.xdc new file mode 100644 index 0000000..3077d50 --- /dev/null +++ b/zynqberrydemo1/constraints/_i_common.xdc @@ -0,0 +1,5 @@ +# +# +# +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] + diff --git a/zynqberrydemo1/constraints/_i_csi.xdc b/zynqberrydemo1/constraints/_i_csi.xdc new file mode 100644 index 0000000..77d913e --- /dev/null +++ b/zynqberrydemo1/constraints/_i_csi.xdc @@ -0,0 +1,18 @@ +set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p] +set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}] +set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}] +set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}] +set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}] +set_property INTERNAL_VREF 0.6 [get_iobanks 34] +set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}] +# RPI Camera 1 +create_clock -period 6.250 -name csi_clk -add [get_ports csi_c_clk_p] +# RPI Camera 2.1 +#create_clock -period 1.875 -name csi_clk -add [get_ports csi_c_clk_p] + diff --git a/zynqberrydemo1/constraints/_i_hdmi.xdc b/zynqberrydemo1/constraints/_i_hdmi.xdc new file mode 100644 index 0000000..39b9707 --- /dev/null +++ b/zynqberrydemo1/constraints/_i_hdmi.xdc @@ -0,0 +1,7 @@ +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p] +set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p] + +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[*]}] +set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}] +set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}] +set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}] diff --git a/zynqberrydemo1/constraints/_i_te0726.xdc b/zynqberrydemo1/constraints/_i_te0726.xdc new file mode 100644 index 0000000..c259487 --- /dev/null +++ b/zynqberrydemo1/constraints/_i_te0726.xdc @@ -0,0 +1,90 @@ +#set_property IOSTANDARD LVCMOS33 [get_ports spdif_tx_o] +#set_property PACKAGE_PIN K15 [get_ports spdif_tx_o] + +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[*]}] +# GPIO Pins +# GPIO2 +set_property PACKAGE_PIN K15 [get_ports {gpio_1_tri_io[0]}] +# GPIO3 +set_property PACKAGE_PIN J14 [get_ports {gpio_1_tri_io[1]}] +# GPIO4 +set_property PACKAGE_PIN H12 [get_ports {gpio_1_tri_io[2]}] +# GPIO5 +set_property PACKAGE_PIN N14 [get_ports {gpio_1_tri_io[3]}] +# GPIO6 +set_property PACKAGE_PIN R15 [get_ports {gpio_1_tri_io[4]}] +# GPIO7 +set_property PACKAGE_PIN L14 [get_ports {gpio_1_tri_io[5]}] +# GPIO8 +set_property PACKAGE_PIN L15 [get_ports {gpio_1_tri_io[6]}] +# GPIO9 +set_property PACKAGE_PIN J13 [get_ports {gpio_1_tri_io[7]}] +# GPIO10 +set_property PACKAGE_PIN H14 [get_ports {gpio_1_tri_io[8]}] +# GPIO11 +set_property PACKAGE_PIN J15 [get_ports {gpio_1_tri_io[9]}] +# GPIO12 +set_property PACKAGE_PIN M15 [get_ports {gpio_1_tri_io[10]}] +# GPIO13 +set_property PACKAGE_PIN R13 [get_ports {gpio_1_tri_io[11]}] +# GPIO16 +set_property PACKAGE_PIN L13 [get_ports {gpio_1_tri_io[12]}] +# GPIO17 +set_property PACKAGE_PIN G11 [get_ports {gpio_1_tri_io[13]}] +# GPIO18 +set_property PACKAGE_PIN H11 [get_ports {gpio_1_tri_io[14]}] +# GPIO19 +set_property PACKAGE_PIN R12 [get_ports {gpio_1_tri_io[15]}] +# GPIO20 +set_property PACKAGE_PIN M14 [get_ports {gpio_1_tri_io[16]}] +# GPIO21 +set_property PACKAGE_PIN P15 [get_ports {gpio_1_tri_io[17]}] +# GPIO22 +set_property PACKAGE_PIN H13 [get_ports {gpio_1_tri_io[18]}] +# GPIO23 +set_property PACKAGE_PIN J11 [get_ports {gpio_1_tri_io[19]}] +# GPIO24 +set_property PACKAGE_PIN K11 [get_ports {gpio_1_tri_io[20]}] +# GPIO25 +set_property PACKAGE_PIN K13 [get_ports {gpio_1_tri_io[21]}] +# GPIO26 +set_property PACKAGE_PIN L12 [get_ports {gpio_1_tri_io[22]}] +# GPIO27 +set_property PACKAGE_PIN G12 [get_ports {gpio_1_tri_io[23]}] + +## DSI_D0_N +#set_property PACKAGE_PIN F13 [get_ports {gpio_1_tri_io[24]}] +## DSI_D0_P +#set_property PACKAGE_PIN F14 [get_ports {gpio_1_tri_io[25]}] +## DSI_D1_N +#set_property PACKAGE_PIN F12 [get_ports {gpio_1_tri_io[26]}] +## DSI_D1_P +#set_property PACKAGE_PIN E13 [get_ports {gpio_1_tri_io[27]}] +## DSI_C_N +#set_property PACKAGE_PIN E11 [get_ports {gpio_1_tri_io[28]}] +## DSI_C_P +#set_property PACKAGE_PIN E12 [get_ports {gpio_1_tri_io[29]}] + +## CSI_D0_N +#set_property PACKAGE_PIN M11 [get_ports {gpio_1_tri_io[30]}] +## CSI_D0_P +#set_property PACKAGE_PIN M10 [get_ports {gpio_1_tri_io[31]}] +## CSI_D1_N +#set_property PACKAGE_PIN P14 [get_ports {gpio_1_tri_io[32]}] +## CSI_D2_P +#set_property PACKAGE_PIN P13 [get_ports {gpio_1_tri_io[33]}] +## CSI_C_N +#set_property PACKAGE_PIN N12 [get_ports {gpio_1_tri_io[34]}] +## CSI_C_P +#set_property PACKAGE_PIN N11 [get_ports {gpio_1_tri_io[35]}] +## PWM_R +##set_property PACKAGE_PIN N8 [get_ports {gpio_1_tri_io[36]}] +## PWM_L +##set_property PACKAGE_PIN N7 [get_ports {gpio_1_tri_io[37]}] + +# PWM_R +set_property PACKAGE_PIN N8 [get_ports PWM_R] +# PWM_L +set_property PACKAGE_PIN N7 [get_ports PWM_L] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_*] + diff --git a/zynqberrydemo1/constraints/_i_timing.xdc b/zynqberrydemo1/constraints/_i_timing.xdc new file mode 100644 index 0000000..07325db --- /dev/null +++ b/zynqberrydemo1/constraints/_i_timing.xdc @@ -0,0 +1,10 @@ +#set_clock_groups -asynchronous -group [get_clocks clk_fpga_3] -group [get_clocks clk_fpga_0] +#set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/tx_sync/out_data_reg[4]}] +#set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/SDATA_O_reg[0]}] +#set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_fpga_3] + +#set_false_path -from [get_pins {zsys_i/axi_reg32_0/U0/axi_reg32_v1_0_S_AXI_inst/slv_reg16_reg[1]/C}] -to [get_pins zsys_i/video_in/axis_raw_demosaic_0/U0/colors_mode_i_reg/D] +#set_false_path -from [get_pins zsys_i/video_in/csi_to_axis_0/U0/lane_align_inst/err_req_reg/C] -to [get_pins zsys_i/video_in/csi2_d_phy_rx_0/U0/clock_upd_req_reg/D] + +#set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_max_first_increment_reg[2]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D] +#set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D] \ No newline at end of file diff --git a/zynqberrydemo1/constraints/vivado_target.xdc b/zynqberrydemo1/constraints/vivado_target.xdc new file mode 100644 index 0000000..e69de29 diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/component.xml b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/component.xml new file mode 100644 index 0000000..5d57029 --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/component.xml @@ -0,0 +1,545 @@ + + + trenz.biz + user + Video_IO_2_HDMI_TMDS + 1.0 + + + vid_io_in + + + + + + + VBLANK + + + vid_vblank + + + + + ACTIVE_VIDEO + + + vid_active_video + + + + + VSYNC + + + vid_vsync + + + + + DATA + + + vid_data + + + + + HBLANK + + + vid_hblank + + + + + HSYNC + + + vid_hsync + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + Video_IO_2_HDMI_TMDS_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 1224790b + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + Video_IO_2_HDMI_TMDS_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 1224790b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 35d6fe5d + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 799cb8bb + + + + + + + video_clk_in + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_clk5x_in + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + lock_in + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + vid_data + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_active_video + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_hblank + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_vblank + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_hsync + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_vsync + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + hdmi_data_p + + out + + 2 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + hdmi_data_n + + out + + 2 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + hdmi_clk_p + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + hdmi_clk_n + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_CLK_SWAP + HDMI CLK P/N Swap + FALSE + + + C_D0_SWAP + HDMI D0 P/N Swap + FALSE + + + C_D1_SWAP + HDMI D1 P/N Swap + FALSE + + + C_D2_SWAP + HDMI D2 P/N Swap + FALSE + + + C_INT_CLOCKING + C Int Clocking + true + + + C_VIDEO_MODE + Video Mode + 0 + + + + + + choice_pairs_c4f3a1c9 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/tmds_encoder.vhd + vhdlSource + + + src/serdes_ddr.vhd + vhdlSource + + + hdl/dvi_encoder.vhd + vhdlSource + + + hdl/clock_system.vhd + vhdlSource + + + hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd + vhdlSource + CHECKSUM_e3ad9cc9 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/tmds_encoder.vhd + vhdlSource + USED_IN_ipstatic + + + src/serdes_ddr.vhd + vhdlSource + + + hdl/dvi_encoder.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/clock_system.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/Video_IO_2_HDMI_TMDS_v1_0.tcl + tclSource + CHECKSUM_60af6022 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_utilityxitfiles_view_fileset + + gui/Video_IO_2_HDMI_TMDS_v1_0.gtcl + GTCL + + + + Video_IO_2_HDMI_TMDS + + + Component_Name + Video_IO_2_HDMI_TMDS_v1_0 + + + C_CLK_SWAP + HDMI CLK P/N Swap + FALSE + + + C_D0_SWAP + HDMI D0 P/N Swap + FALSE + + + C_D1_SWAP + HDMI D1 P/N Swap + FALSE + + + C_D2_SWAP + HDMI D2 P/N Swap + FALSE + + + C_VIDEO_MODE + Video Mode + 0 + + + + true + + + + + + C_INT_CLOCKING + Internal Clocks System + true + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /Video_&_Image_Processing + + Video IO to HDMI TMDS Interface v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 26 + + xilinx.com:user:Video_IO_2_HDMI_TMDS:1.0 + + 2017-05-12T14:48:23Z + + b:/cores/2015.4/design/te0726/iotest/ip_lib/video_io_2_hdmi_tmds_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd new file mode 100644 index 0000000..71e5f47 --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd @@ -0,0 +1,229 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity Video_IO_2_HDMI_TMDS_v1_0 is +generic ( + -- Pin swap options + C_CLK_SWAP : boolean := FALSE; + C_D0_SWAP : boolean := FALSE; + C_D1_SWAP : boolean := FALSE; + C_D2_SWAP : boolean := FALSE; + + -- Clocking options + C_INT_CLOCKING : BOOLEAN := TRUE; + C_VIDEO_MODE : integer range 0 to 8 := 2 +-- 0 = VGA (640x480 @ 60 Hz) 25 250 24b +-- 1 = 480p (720x480 @ 60 Hz) 27 270 24b +-- 2 = SVGA (800x600 @ 60 Hz) 40 400 24b +-- 3 = XGA (1024x768 @ 60 Hz) 65 650 24b +-- 4 = HD (1366x768 @ 60 Hz) 85.5 855 24b +-- 5 = WXGA (1280x800 @ 60 Hz) 71 710 24b +-- 6 = HDTV 720p (1280x720 @ 60 Hz) 74.25 742.5 24b +-- 7 = HDTV 1080i (1920x1080 @ 60 Hz interlaced) 74.25 742.5 24b +-- 8 = SXGA (1280x1024 @ 60 Hz) 108 1080 24b +); +port ( + -- Clocks + video_clk_in : in STD_LOGIC; -- Main clock Input + video_clk5x_in : in STD_LOGIC; -- SERDES clock Input + lock_in : in STD_LOGIC; -- External PLL locking + -- Video IO Interface + vid_data : in STD_LOGIC_VECTOR(23 downto 0); + vid_active_video : in STD_LOGIC; + vid_hblank : in STD_LOGIC; + vid_vblank : in STD_LOGIC; + vid_hsync : in STD_LOGIC; + vid_vsync : in STD_LOGIC; + -- HDMI Interface + hdmi_data_p : out STD_LOGIC_VECTOR(2 downto 0); + hdmi_data_n : out STD_LOGIC_VECTOR(2 downto 0); + hdmi_clk_p : out STD_LOGIC; + hdmi_clk_n : out STD_LOGIC +); +end Video_IO_2_HDMI_TMDS_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of Video_IO_2_HDMI_TMDS_v1_0 is +---------------------------------------------------------------------------------- +component clock_system is +generic( + C_VIDEO_MODE : integer range 0 to 9 := 2 +); +port ( + clk_in : in STD_LOGIC; + pclk1x : out STD_LOGIC; + pclk5x : out STD_LOGIC; + lock : out STD_LOGIC +); +end component; + +component serdes_ddr is +port ( + clk_in : in STD_LOGIC; + clk_dv_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(9 downto 0); + data_out : out STD_LOGIC +); +end component; + +component dvi_encoder is +port ( + clkin : in STD_LOGIC; + rstin : in STD_LOGIC; + blue_din : in STD_LOGIC_VECTOR(7 downto 0); + green_din : in STD_LOGIC_VECTOR(7 downto 0); + red_din : in STD_LOGIC_VECTOR(7 downto 0); + hsync : in STD_LOGIC; + vsync : in STD_LOGIC; + de : in STD_LOGIC; + blue_dout : out STD_LOGIC_VECTOR(9 downto 0); + green_dout : out STD_LOGIC_VECTOR(9 downto 0); + red_dout : out STD_LOGIC_VECTOR(9 downto 0) +); +end component; +---------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +-- Clock system +signal pclk5x : STD_LOGIC; +signal pclk1x : STD_LOGIC; +signal lock : STD_LOGIC; +signal reset : STD_LOGIC; +signal serdes_rst : STD_LOGIC; +-- Video system +signal red_data : STD_LOGIC_VECTOR(7 downto 0); +signal green_data : STD_LOGIC_VECTOR(7 downto 0); +signal blue_data : STD_LOGIC_VECTOR(7 downto 0); +type s_data_type is array (5 downto 0) of STD_LOGIC_VECTOR(9 downto 0); +signal s_data_r : s_data_type; +signal s_data_o : s_data_type; +signal tmds_out : STD_LOGIC_VECTOR(3 downto 0); +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +int_clock_sys: if C_INT_CLOCKING = TRUE generate +begin + -- Clock system + clock_system_inst: clock_system + generic map( + C_VIDEO_MODE => C_VIDEO_MODE + ) + port map( + clk_in => video_clk_in, + pclk1x => pclk1x, + pclk5x => pclk5x, + lock => lock + ); +end generate; +ext_clock_sys: if C_INT_CLOCKING = FALSE generate +begin + lock <= lock_in; + pclk1x <= video_clk_in; + pclk5x <= video_clk5x_in; +end generate; +---------------------------------------------------------------------------------- +serdes_rst <= not lock; +reset <= net_gnd; +---------------------------------------------------------------------------------- +-- Video system +red_data <= vid_data(23 downto 16); +green_data <= vid_data( 7 downto 0); +blue_data <= vid_data(15 downto 8); +-- Encoder +enc_inst: dvi_encoder +port map( + clkin => pclk1x, + rstin => reset, + blue_din => blue_data, + green_din => green_data, + red_din => red_data, + hsync => vid_hsync, + vsync => vid_vsync, + de => vid_active_video, + blue_dout => s_data_r(0), + green_dout => s_data_r(1), + red_dout => s_data_r(2) +); +-- HDMI Clock generation +s_data_r(3) <= b"11111_00000"; +---------------------------------------------------------------------------------- +-- Bitswap +---------------------------------------------------------------------------------- +d0_direct: if C_D0_SWAP = FALSE generate + s_data_o(0) <= s_data_r(0); +end generate; +d0_inv: if C_D0_SWAP = TRUE generate + s_data_o(0) <= not s_data_r(0); +end generate; + +d1_direct: if C_D1_SWAP = FALSE generate + s_data_o(1) <= s_data_r(1); +end generate; +d1_inv: if C_D1_SWAP = TRUE generate + s_data_o(1) <= not s_data_r(1); +end generate; + +d2_direct: if C_D2_SWAP = FALSE generate + s_data_o(2) <= s_data_r(2); +end generate; +d2_inv: if C_D2_SWAP = TRUE generate + s_data_o(2) <= not s_data_r(2); +end generate; + +clk_direct: if C_CLK_SWAP = FALSE generate + s_data_o(3) <= s_data_r(3); +end generate; +clk_inv: if C_CLK_SWAP = TRUE generate + s_data_o(3) <= not s_data_r(3); +end generate; +---------------------------------------------------------------------------------- +-- Serdes +---------------------------------------------------------------------------------- +HDMI_ddr_lines_gen: for i in 0 to 3 generate +begin + serdes_ddr_inst: serdes_ddr + port map( + clk_in => pclk5x, + clk_dv_in => pclk1x, + reset_in => serdes_rst, + data_in => s_data_o(i), + data_out => tmds_out(i) + ); +end generate; +---------------------------------------------------------------------------------- +-- Output buffers +---------------------------------------------------------------------------------- +obufds_d0_inst: OBUFDS +port map( + I => tmds_out(0), + O => hdmi_data_p(0), + OB => hdmi_data_n(0) +); +obufds_d1_inst: OBUFDS +port map( + I => tmds_out(1), + O => hdmi_data_p(1), + OB => hdmi_data_n(1) +); +obufds_d2_inst: OBUFDS +port map( + I => tmds_out(2), + O => hdmi_data_p(2), + OB => hdmi_data_n(2) +); +obufds_clk_inst: OBUFDS +port map( + I => tmds_out(3), + O => hdmi_clk_p, + OB => hdmi_clk_n +); +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/clock_system.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/clock_system.vhd new file mode 100644 index 0000000..b0e23a8 --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/clock_system.vhd @@ -0,0 +1,282 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity clock_system is +generic( + C_VIDEO_MODE : integer range 0 to 8 := 2 +-- 0 = VGA (640x480 @ 60 Hz) 25 250 24b +-- 1 = 480p (720x480 @ 60 Hz) 27 270 24b +-- 2 = SVGA (800x600 @ 60 Hz) 40 400 24b +-- 3 = XGA (1024x768 @ 60 Hz) 65 650 24b +-- 4 = HD (1366x768 @ 60 Hz) 85.5 855 24b +-- 5 = WXGA (1280x800 @ 60 Hz) 71 710 24b +-- 6 = HDTV 720p (1280x720 @ 60 Hz) 74.25 742.5 24b +-- 7 = HDTV 1080i (1920x1080 @ 60 Hz interlaced) 74.25 742.5 24b +-- 8 = SXGA (1280x1024 @ 60 Hz) 108 1080 24b +); +port ( + clk_in : in STD_LOGIC; + pclk1x : out STD_LOGIC; + pclk5x : out STD_LOGIC; + lock : out STD_LOGIC +); +end clock_system; +------------------------------------------------------------------------------- +architecture Behavioral of clock_system is +------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +-- Clock system +signal clkfbout : STD_LOGIC; +signal pllclk5x_pll : STD_LOGIC; +signal pllclk5x_pll_g : STD_LOGIC; +signal pllclk1x_pll : STD_LOGIC; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +VGA_gen: if C_VIDEO_MODE = 0 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 40.0, + CLKFBOUT_MULT => 20, -- x10 clock + CLKOUT0_DIVIDE => 4, -- x5 clock + CLKOUT1_DIVIDE => 20, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +m480p_gen: if C_VIDEO_MODE = 1 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 37.037, + CLKFBOUT_MULT => 20, -- x10 clock + CLKOUT0_DIVIDE => 4, -- x5 clock + CLKOUT1_DIVIDE => 20, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +SVGA_gen: if C_VIDEO_MODE = 2 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 25.0, + CLKFBOUT_MULT => 20, -- x10 clock + CLKOUT0_DIVIDE => 4, -- x5 clock + CLKOUT1_DIVIDE => 20, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +XGA_gen: if C_VIDEO_MODE = 3 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 15.3846, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +HD_gen: if C_VIDEO_MODE = 4 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 11.6959, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +WXGA_gen: if C_VIDEO_MODE = 5 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 14.0845, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +HDTV_720p_gen: if C_VIDEO_MODE = 6 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 13.468, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +HDTV_1080p_gen: if C_VIDEO_MODE = 7 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 13.468, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +SXGA_gen: if C_VIDEO_MODE = 8 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 9.2592, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +dclk_BUFIO_inst : BUFIO +port map ( + I => pllclk5x_pll, + O => pclk5x +); + +out_clk_BUFG_inst : BUFG +port map ( + I => pllclk1x_pll, + O => pclk1x +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/convert_30to15_fifo.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/convert_30to15_fifo.vhd new file mode 100644 index 0000000..cdcde89 --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/convert_30to15_fifo.vhd @@ -0,0 +1,194 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity convert_30to15_fifo is +port ( + rst : in STD_LOGIC; -- reset + clk : in STD_LOGIC; -- clock input + clkx2 : in STD_LOGIC; -- 2x clock input + datain : in STD_LOGIC_VECTOR(29 downto 0); -- input data for 2:1 serialisation + dataout : out STD_LOGIC_VECTOR(14 downto 0) +); +end convert_30to15_fifo; +------------------------------------------------------------------------------- +architecture Behavioral of convert_30to15_fifo is +------------------------------------------------------------------------------- +constant net_vcc : STD_LOGIC := '1'; + +component dram16xn is +generic( + DATA_WIDTH : integer := 20 +); +port ( + clk : in STD_LOGIC; + write_en : in STD_LOGIC; + address : in STD_LOGIC_VECTOR(3 downto 0); + address_dp : in STD_LOGIC_VECTOR(3 downto 0); + data_in : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); + o_data_out : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); + o_data_out_dp : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) +); +end component; + +---------------------------------------------------- +-- Here we instantiate a 16x10 Dual Port RAM +-- and fill first it with data aligned to +-- clk domain +---------------------------------------------------- +signal wa : STD_LOGIC_VECTOR( 3 downto 0); -- RAM read address +signal wa_d : STD_LOGIC_VECTOR( 3 downto 0); -- RAM read address +signal ra : STD_LOGIC_VECTOR( 3 downto 0); -- RAM read address +signal ra_d : STD_LOGIC_VECTOR( 3 downto 0); -- RAM read address +signal dataint : STD_LOGIC_VECTOR(29 downto 0); -- RAM output + +constant ADDR0 : STD_LOGIC_VECTOR(3 downto 0) := "0000"; +constant ADDR1 : STD_LOGIC_VECTOR(3 downto 0) := "0001"; +constant ADDR2 : STD_LOGIC_VECTOR(3 downto 0) := "0010"; +constant ADDR3 : STD_LOGIC_VECTOR(3 downto 0) := "0011"; +constant ADDR4 : STD_LOGIC_VECTOR(3 downto 0) := "0100"; +constant ADDR5 : STD_LOGIC_VECTOR(3 downto 0) := "0101"; +constant ADDR6 : STD_LOGIC_VECTOR(3 downto 0) := "0110"; +constant ADDR7 : STD_LOGIC_VECTOR(3 downto 0) := "0111"; +constant ADDR8 : STD_LOGIC_VECTOR(3 downto 0) := "1000"; +constant ADDR9 : STD_LOGIC_VECTOR(3 downto 0) := "1001"; +constant ADDR10 : STD_LOGIC_VECTOR(3 downto 0) := "1010"; +constant ADDR11 : STD_LOGIC_VECTOR(3 downto 0) := "1011"; +constant ADDR12 : STD_LOGIC_VECTOR(3 downto 0) := "1100"; +constant ADDR13 : STD_LOGIC_VECTOR(3 downto 0) := "1101"; +constant ADDR14 : STD_LOGIC_VECTOR(3 downto 0) := "1110"; +constant ADDR15 : STD_LOGIC_VECTOR(3 downto 0) := "1111"; + +signal rstsync : STD_LOGIC; +signal rstsync_q : STD_LOGIC; +signal rstp : STD_LOGIC; +signal sync : STD_LOGIC; +signal db : STD_LOGIC_VECTOR(29 downto 0); +signal mux : STD_LOGIC_VECTOR(14 downto 0); +------------------------------------------------------------------------------- +attribute ASYNC_REG : string; +attribute ASYNC_REG of rstsync : signal is "true"; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +process(wa) +begin + case wa is + when ADDR0 => wa_d <= ADDR1 ; + when ADDR1 => wa_d <= ADDR2 ; + when ADDR2 => wa_d <= ADDR3 ; + when ADDR3 => wa_d <= ADDR4 ; + when ADDR4 => wa_d <= ADDR5 ; + when ADDR5 => wa_d <= ADDR6 ; + when ADDR6 => wa_d <= ADDR7 ; + when ADDR7 => wa_d <= ADDR8 ; + when ADDR8 => wa_d <= ADDR9 ; + when ADDR9 => wa_d <= ADDR10; + when ADDR10 => wa_d <= ADDR11; + when ADDR11 => wa_d <= ADDR12; + when ADDR12 => wa_d <= ADDR13; + when ADDR13 => wa_d <= ADDR14; + when ADDR14 => wa_d <= ADDR15; + when others => wa_d <= ADDR0; + end case; +end process; + +process(clk, rst) +begin + if(rst = '1')then + wa <= (others => '0'); + elsif(clk = '1' and clk'event)then + wa <= wa_d; + end if; +end process; + +-- Dual Port fifo to bridge data from clk to clkx2 +fifo_inst: dram16xn +generic map( + DATA_WIDTH => 30 +) +port map( + clk => clk, + write_en => net_vcc, + address => wa, + address_dp => ra, + data_in => datain, + o_data_out => open, + o_data_out_dp => dataint +); + +----------------------------------------------------------------/ +-- Here starts clk2x domain for fifo read out +-- FIFO read is set to be once every 2 cycles of clk2x in order +-- to keep up pace with the fifo write speed +-- Also FIFO read reset is delayed a bit in order to avoid +-- underflow. +----------------------------------------------------------------/ +process(ra) +begin + case ra is + when ADDR0 => ra_d <= ADDR1 ; + when ADDR1 => ra_d <= ADDR2 ; + when ADDR2 => ra_d <= ADDR3 ; + when ADDR3 => ra_d <= ADDR4 ; + when ADDR4 => ra_d <= ADDR5 ; + when ADDR5 => ra_d <= ADDR6 ; + when ADDR6 => ra_d <= ADDR7 ; + when ADDR7 => ra_d <= ADDR8 ; + when ADDR8 => ra_d <= ADDR9 ; + when ADDR9 => ra_d <= ADDR10; + when ADDR10 => ra_d <= ADDR11; + when ADDR11 => ra_d <= ADDR12; + when ADDR12 => ra_d <= ADDR13; + when ADDR13 => ra_d <= ADDR14; + when ADDR14 => ra_d <= ADDR15; + when others => ra_d <= ADDR0; + end case; +end process; + +fdp_rst: FDP +port map( + C => clkx2, + D => rst, + PRE => rst, + Q => rstsync +); + +fd_rstsync: FD +port map( + C => clkx2, + D => rstsync, + Q => rstsync_q +); + +fd_rstp: FD +port map( + C => clkx2, + D => rstsync_q, + Q => rstp +); + +mux <= db(14 downto 0) when (sync = '0') else db(29 downto 15); + +process(clkx2, rstp) +begin + if(rstp = '1')then + sync <= '0'; + ra <= (others => '0'); + elsif(clkx2 = '1' and clkx2'event)then + sync <= not sync; + if(sync = '1')then + ra <= ra_d; + db <= dataint; + end if; + dataout <= mux; + end if; +end process; +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dram16xn.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dram16xn.vhd new file mode 100644 index 0000000..e7d15c0 --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dram16xn.vhd @@ -0,0 +1,51 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity dram16xn is +generic( + DATA_WIDTH : integer := 20 +); +port ( + clk : in STD_LOGIC; + write_en : in STD_LOGIC; + address : in STD_LOGIC_VECTOR(3 downto 0); + address_dp : in STD_LOGIC_VECTOR(3 downto 0); + data_in : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); + o_data_out : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); + o_data_out_dp : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) +); +end dram16xn; +------------------------------------------------------------------------------- +architecture Behavioral of dram16xn is +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +bit_gen: for i in 0 to DATA_WIDTH-1 generate +begin + ram_inst: RAM16X1D + port map( + D => data_in(i), --insert input signal + WE => write_en, --insert Write Enable signal + WCLK => clk, --insert Write Clock signal + A0 => address(0), --insert Address 0 signal port SPO + A1 => address(1), --insert Address 1 signal port SPO + A2 => address(2), --insert Address 2 signal port SPO + A3 => address(3), --insert Address 3 signal port SPO + DPRA0 => address_dp(0), --insert Address 0 signal dual port DPO + DPRA1 => address_dp(1), --insert Address 1 signal dual port DPO + DPRA2 => address_dp(2), --insert Address 2 signal dual port DPO + DPRA3 => address_dp(3), --insert Address 3 signal dual port DPO + SPO => o_data_out(i), --insert output signal SPO + DPO => o_data_out_dp(i) --insert output signal DPO + ); +end generate; +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dvi_encoder.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dvi_encoder.vhd new file mode 100644 index 0000000..6f2154a --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dvi_encoder.vhd @@ -0,0 +1,75 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +---------------------------------------------------------------------------------- +entity dvi_encoder is +port ( + clkin : in STD_LOGIC; -- pixel clock + rstin : in STD_LOGIC; -- reset + blue_din : in STD_LOGIC_VECTOR(7 downto 0); -- Blue data in + green_din : in STD_LOGIC_VECTOR(7 downto 0); -- Green data in + red_din : in STD_LOGIC_VECTOR(7 downto 0); -- Red data in + hsync : in STD_LOGIC; -- hsync data + vsync : in STD_LOGIC; -- vsync data + de : in STD_LOGIC; -- data enable + blue_dout : out STD_LOGIC_VECTOR(9 downto 0); + green_dout : out STD_LOGIC_VECTOR(9 downto 0); + red_dout : out STD_LOGIC_VECTOR(9 downto 0) +); +end dvi_encoder; +------------------------------------------------------------------------------- +architecture Behavioral of dvi_encoder is +------------------------------------------------------------------------------- +constant net_gnd : STD_LOGIC := '0'; +component tmds_encoder is +port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(7 downto 0); + c0_in : in STD_LOGIC; + c1_in : in STD_LOGIC; + de_in : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR(9 downto 0) +); +end component; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +encb_inst: tmds_encoder +port map( + clk_in => clkin, + rst_in => rstin, + data_in => blue_din, + c0_in => hsync, + c1_in => vsync, + de_in => de, + data_out => blue_dout +); + +encg_inst: tmds_encoder +port map( + clk_in => clkin, + rst_in => rstin, + data_in => green_din, + c0_in => net_gnd, + c1_in => net_gnd, + de_in => de, + data_out => green_dout +); + +encr_inst: tmds_encoder +port map( + clk_in => clkin, + rst_in => rstin, + data_in => red_din, + c0_in => net_gnd, + c1_in => net_gnd, + de_in => de, + data_out => red_dout +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes.vhd new file mode 100644 index 0000000..44d7c3c --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes.vhd @@ -0,0 +1,79 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity serdes is +port ( + clk_in : in STD_LOGIC; + clk_dv_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(4 downto 0); + data_out : out STD_LOGIC +); +end serdes; +------------------------------------------------------------------------------- +architecture Behavioral of serdes is +------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +OSERDESE2_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "SDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "SDR", -- "BUF", "SDR" or "DDR" + -- DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + -- DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 5, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => data_out, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => open, + SHIFTOUT2 => open, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => data_in(0), + D2 => data_in(1), + D3 => data_in(2), + D4 => data_in(3), + D5 => data_in(4), + D6 => net_gnd, + D7 => net_gnd, + D8 => net_gnd, + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => net_gnd, + SHIFTIN2 => net_gnd, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes_ddr.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes_ddr.vhd new file mode 100644 index 0000000..df0dd2c --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes_ddr.vhd @@ -0,0 +1,128 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity serdes_ddr is +port ( + clk_in : in STD_LOGIC; + clk_dv_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(9 downto 0); + data_out : out STD_LOGIC +); +end serdes_ddr; +------------------------------------------------------------------------------- +architecture Behavioral of serdes_ddr is +------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +-- Signals +signal shift_a : STD_LOGIC; +signal shift_b : STD_LOGIC; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +OSERDESE2_m_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 10, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => data_out, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => open, + SHIFTOUT2 => open, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => data_in(0), + D2 => data_in(1), + D3 => data_in(2), + D4 => data_in(3), + D5 => data_in(4), + D6 => data_in(5), + D7 => data_in(6), + D8 => data_in(7), + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => shift_a, + SHIFTIN2 => shift_b, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); + +OSERDESE2_s_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 10, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => open, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => shift_a, + SHIFTOUT2 => shift_b, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => net_gnd, + D2 => net_gnd, + D3 => data_in(8), + D4 => data_in(9), + D5 => net_gnd, + D6 => net_gnd, + D7 => net_gnd, + D8 => net_gnd, + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => net_gnd, + SHIFTIN2 => net_gnd, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/tmds_encoder.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/tmds_encoder.vhd new file mode 100644 index 0000000..468dddb --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/tmds_encoder.vhd @@ -0,0 +1,180 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +---------------------------------------------------------------------------------- +entity tmds_encoder is +port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(7 downto 0); + c0_in : in STD_LOGIC; + c1_in : in STD_LOGIC; + de_in : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR(9 downto 0) +); +end tmds_encoder; +------------------------------------------------------------------------------- +architecture Behavioral of tmds_encoder is +------------------------------------------------------------------------------- +signal n1d : UNSIGNED(3 downto 0); -- number of 1s in din +signal din_q : STD_LOGIC_VECTOR(7 downto 0); +signal decision_a : STD_LOGIC; +signal decision_b : STD_LOGIC; +signal decision_c : STD_LOGIC; +signal q_m : STD_LOGIC_VECTOR(8 downto 0); +signal n1q_m : UNSIGNED(3 downto 0); -- number of 1s and 0s for q_m +signal n0q_m : UNSIGNED(3 downto 0); +signal cnt : UNSIGNED(4 downto 0); -- disparity counter, MSB is the sign bit + +constant CTRLTOKEN0 : STD_LOGIC_VECTOR(9 downto 0) := b"1101010100"; +constant CTRLTOKEN1 : STD_LOGIC_VECTOR(9 downto 0) := b"0010101011"; +constant CTRLTOKEN2 : STD_LOGIC_VECTOR(9 downto 0) := b"0101010100"; +constant CTRLTOKEN3 : STD_LOGIC_VECTOR(9 downto 0) := b"1010101011"; + +signal de_q : STD_LOGIC; +signal de_reg : STD_LOGIC; +signal c0_q : STD_LOGIC; +signal c1_q : STD_LOGIC; +signal c_reg : STD_LOGIC_VECTOR(1 downto 0); +signal q_m_reg : STD_LOGIC_VECTOR(8 downto 0); +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + n1d <= + resize(UNSIGNED(data_in(0 downto 0)),4) + + resize(UNSIGNED(data_in(1 downto 1)),4) + + resize(UNSIGNED(data_in(2 downto 2)),4) + + resize(UNSIGNED(data_in(3 downto 3)),4) + + resize(UNSIGNED(data_in(4 downto 4)),4) + + resize(UNSIGNED(data_in(5 downto 5)),4) + + resize(UNSIGNED(data_in(6 downto 6)),4) + + resize(UNSIGNED(data_in(7 downto 7)),4); + din_q <= data_in; + end if; +end process; + +--assign decision1 = (n1d > 4'h4) | ((n1d == 4'h4) & (din_q(0] == 1'b0)); +decision_a <= '1' when ((n1d > to_unsigned(4,4)) or ((n1d = to_unsigned(4,4)) and (din_q(0) = '0'))) else '0'; + +q_m(0) <= din_q(0); +q_m(1) <= (q_m(0) xnor din_q(1)) when (decision_a = '1') else (q_m(0) xor din_q(1)); +q_m(2) <= (q_m(1) xnor din_q(2)) when (decision_a = '1') else (q_m(1) xor din_q(2)); +q_m(3) <= (q_m(2) xnor din_q(3)) when (decision_a = '1') else (q_m(2) xor din_q(3)); +q_m(4) <= (q_m(3) xnor din_q(4)) when (decision_a = '1') else (q_m(3) xor din_q(4)); +q_m(5) <= (q_m(4) xnor din_q(5)) when (decision_a = '1') else (q_m(4) xor din_q(5)); +q_m(6) <= (q_m(5) xnor din_q(6)) when (decision_a = '1') else (q_m(5) xor din_q(6)); +q_m(7) <= (q_m(6) xnor din_q(7)) when (decision_a = '1') else (q_m(6) xor din_q(7)); +q_m(8) <= '0' when (decision_a = '1') else '1'; +------------------------------------------------------------------------------- +-- Stage 2: 9 bit -> 10 bit +-- Refer to DVI 1.0 Specification, page 29, Figure 3-5 +------------------------------------------------------------------------------- +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + n1q_m <= + resize(UNSIGNED(q_m(0 downto 0)),4) + + resize(UNSIGNED(q_m(1 downto 1)),4) + + resize(UNSIGNED(q_m(2 downto 2)),4) + + resize(UNSIGNED(q_m(3 downto 3)),4) + + resize(UNSIGNED(q_m(4 downto 4)),4) + + resize(UNSIGNED(q_m(5 downto 5)),4) + + resize(UNSIGNED(q_m(6 downto 6)),4) + + resize(UNSIGNED(q_m(7 downto 7)),4); + n0q_m <= + to_unsigned(8,4) - ( + resize(UNSIGNED(q_m(0 downto 0)),4) + + resize(UNSIGNED(q_m(1 downto 1)),4) + + resize(UNSIGNED(q_m(2 downto 2)),4) + + resize(UNSIGNED(q_m(3 downto 3)),4) + + resize(UNSIGNED(q_m(4 downto 4)),4) + + resize(UNSIGNED(q_m(5 downto 5)),4) + + resize(UNSIGNED(q_m(6 downto 6)),4) + + resize(UNSIGNED(q_m(7 downto 7)),4)); + end if; +end process; + +decision_b <= '1' when ((cnt = to_unsigned(0,5)) or (n1q_m = n0q_m)) else '0'; +------------------------------------------------------------------------------- +-- [(cnt > 0) and (N1q_m > N0q_m)] or [(cnt < 0) and (N0q_m > N1q_m)] +------------------------------------------------------------------------------- +decision_c <= '1' when ((cnt(4) = '0') and (n1q_m > n0q_m)) or ((cnt(4) = '1') and (n0q_m > n1q_m)) else '0'; +------------------------------------------------------------------------------- +-- pipe line alignment +------------------------------------------------------------------------------- +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + de_q <= de_in; + de_reg <= de_q; + c0_q <= c0_in; + c1_q <= c1_in; + q_m_reg <= q_m; + c_reg <= c1_q & c0_q; + end if; +end process; +------------------------------------------------------------------------------- +-- 10-bit out +-- disparity counter +------------------------------------------------------------------------------- +process(clk_in, rst_in) +begin + if(rst_in = '1')then + data_out <= (others => '0'); + cnt <= (others => '0'); + elsif(clk_in = '1' and clk_in'event)then + if(de_reg = '1')then + if(decision_b = '1')then + data_out(9) <= not q_m_reg(8); + data_out(8) <= q_m_reg(8); + if(q_m_reg(8) = '1')then + data_out(7 downto 0) <= q_m_reg(7 downto 0); + else + data_out(7 downto 0) <= not q_m_reg(7 downto 0); + end if; + if(q_m_reg(8) = '0')then + cnt <= cnt + resize(n0q_m,5) - resize(n1q_m,5); + else + cnt <= cnt + resize(n1q_m,5) - resize(n0q_m,5); + end if; + else + if(decision_c = '1')then + data_out(9) <= '1'; + data_out(8) <= q_m_reg(8); + data_out(7 downto 0) <= not q_m_reg(7 downto 0); + if(q_m_reg(8) = '1')then + cnt <= cnt + to_unsigned(2,5) + (resize(n0q_m,5) - resize(n1q_m,5)); + else + cnt <= cnt + (resize(n0q_m,5) - resize(n1q_m,5)); + end if; + else + data_out(9) <= '0'; + data_out(8) <= q_m_reg(8); + data_out(7 downto 0) <= q_m_reg(7 downto 0); + if(q_m_reg(8) = '0')then + cnt <= cnt - to_unsigned(2,5) + (resize(n1q_m,5) - resize(n0q_m,5)); + else + cnt <= cnt + (resize(n1q_m,5) - resize(n0q_m,5)); + end if; + end if; + end if; + else + case(c_reg)is + when "00" => data_out <= CTRLTOKEN0; + when "01" => data_out <= CTRLTOKEN1; + when "10" => data_out <= CTRLTOKEN2; + when others => data_out <= CTRLTOKEN3; + end case; + cnt <= (others => '0'); + end if; + end if; +end process; +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/src/serdes_ddr.vhd b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/src/serdes_ddr.vhd new file mode 100644 index 0000000..df0dd2c --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/src/serdes_ddr.vhd @@ -0,0 +1,128 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity serdes_ddr is +port ( + clk_in : in STD_LOGIC; + clk_dv_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(9 downto 0); + data_out : out STD_LOGIC +); +end serdes_ddr; +------------------------------------------------------------------------------- +architecture Behavioral of serdes_ddr is +------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +-- Signals +signal shift_a : STD_LOGIC; +signal shift_b : STD_LOGIC; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +OSERDESE2_m_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 10, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => data_out, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => open, + SHIFTOUT2 => open, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => data_in(0), + D2 => data_in(1), + D3 => data_in(2), + D4 => data_in(3), + D5 => data_in(4), + D6 => data_in(5), + D7 => data_in(6), + D8 => data_in(7), + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => shift_a, + SHIFTIN2 => shift_b, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); + +OSERDESE2_s_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 10, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => open, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => shift_a, + SHIFTOUT2 => shift_b, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => net_gnd, + D2 => net_gnd, + D3 => data_in(8), + D4 => data_in(9), + D5 => net_gnd, + D6 => net_gnd, + D7 => net_gnd, + D8 => net_gnd, + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => net_gnd, + SHIFTIN2 => net_gnd, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/xgui/Video_IO_2_HDMI_TMDS_v1_0.tcl b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/xgui/Video_IO_2_HDMI_TMDS_v1_0.tcl new file mode 100644 index 0000000..02321a4 --- /dev/null +++ b/zynqberrydemo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0/xgui/Video_IO_2_HDMI_TMDS_v1_0.tcl @@ -0,0 +1,119 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/Video_IO_2_HDMI_TMDS_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set Clocking [ipgui::add_group $IPINST -name "Clocking" -parent ${Page_0} -display_name {Clocking Options}] + ipgui::add_param $IPINST -name "C_INT_CLOCKING" -parent ${Clocking} + ipgui::add_param $IPINST -name "C_VIDEO_MODE" -parent ${Clocking} -widget comboBox + + #Adding Group + set Pins_swap [ipgui::add_group $IPINST -name "Pins swap" -parent ${Page_0}] + ipgui::add_param $IPINST -name "C_CLK_SWAP" -parent ${Pins_swap} + ipgui::add_param $IPINST -name "C_D0_SWAP" -parent ${Pins_swap} + ipgui::add_param $IPINST -name "C_D1_SWAP" -parent ${Pins_swap} + ipgui::add_param $IPINST -name "C_D2_SWAP" -parent ${Pins_swap} + + + +} + +proc update_PARAM_VALUE.C_VIDEO_MODE { PARAM_VALUE.C_VIDEO_MODE PARAM_VALUE.C_INT_CLOCKING } { + # Procedure called to update C_VIDEO_MODE when any of the dependent parameters in the arguments change + + set C_VIDEO_MODE ${PARAM_VALUE.C_VIDEO_MODE} + set C_INT_CLOCKING ${PARAM_VALUE.C_INT_CLOCKING} + set values(C_INT_CLOCKING) [get_property value $C_INT_CLOCKING] + if { [gen_USERPARAMETER_C_VIDEO_MODE_ENABLEMENT $values(C_INT_CLOCKING)] } { + set_property enabled true $C_VIDEO_MODE + } else { + set_property enabled false $C_VIDEO_MODE + } +} + +proc validate_PARAM_VALUE.C_VIDEO_MODE { PARAM_VALUE.C_VIDEO_MODE } { + # Procedure called to validate C_VIDEO_MODE + return true +} + +proc update_PARAM_VALUE.C_CLK_SWAP { PARAM_VALUE.C_CLK_SWAP } { + # Procedure called to update C_CLK_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_CLK_SWAP { PARAM_VALUE.C_CLK_SWAP } { + # Procedure called to validate C_CLK_SWAP + return true +} + +proc update_PARAM_VALUE.C_D0_SWAP { PARAM_VALUE.C_D0_SWAP } { + # Procedure called to update C_D0_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D0_SWAP { PARAM_VALUE.C_D0_SWAP } { + # Procedure called to validate C_D0_SWAP + return true +} + +proc update_PARAM_VALUE.C_D1_SWAP { PARAM_VALUE.C_D1_SWAP } { + # Procedure called to update C_D1_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D1_SWAP { PARAM_VALUE.C_D1_SWAP } { + # Procedure called to validate C_D1_SWAP + return true +} + +proc update_PARAM_VALUE.C_D2_SWAP { PARAM_VALUE.C_D2_SWAP } { + # Procedure called to update C_D2_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D2_SWAP { PARAM_VALUE.C_D2_SWAP } { + # Procedure called to validate C_D2_SWAP + return true +} + +proc update_PARAM_VALUE.C_INT_CLOCKING { PARAM_VALUE.C_INT_CLOCKING } { + # Procedure called to update C_INT_CLOCKING when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_INT_CLOCKING { PARAM_VALUE.C_INT_CLOCKING } { + # Procedure called to validate C_INT_CLOCKING + return true +} + + +proc update_MODELPARAM_VALUE.C_CLK_SWAP { MODELPARAM_VALUE.C_CLK_SWAP PARAM_VALUE.C_CLK_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_CLK_SWAP}] ${MODELPARAM_VALUE.C_CLK_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D0_SWAP { MODELPARAM_VALUE.C_D0_SWAP PARAM_VALUE.C_D0_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D0_SWAP}] ${MODELPARAM_VALUE.C_D0_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D1_SWAP { MODELPARAM_VALUE.C_D1_SWAP PARAM_VALUE.C_D1_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D1_SWAP}] ${MODELPARAM_VALUE.C_D1_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D2_SWAP { MODELPARAM_VALUE.C_D2_SWAP PARAM_VALUE.C_D2_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D2_SWAP}] ${MODELPARAM_VALUE.C_D2_SWAP} +} + +proc update_MODELPARAM_VALUE.C_INT_CLOCKING { MODELPARAM_VALUE.C_INT_CLOCKING PARAM_VALUE.C_INT_CLOCKING } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_INT_CLOCKING}] ${MODELPARAM_VALUE.C_INT_CLOCKING} +} + +proc update_MODELPARAM_VALUE.C_VIDEO_MODE { MODELPARAM_VALUE.C_VIDEO_MODE PARAM_VALUE.C_VIDEO_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_VIDEO_MODE}] ${MODELPARAM_VALUE.C_VIDEO_MODE} +} + diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/bd/bd.tcl b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/bd/bd.tcl new file mode 100644 index 0000000..4804aeb --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/component.xml b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/component.xml new file mode 100644 index 0000000..dc899b3 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/component.xml @@ -0,0 +1,1973 @@ + + + digilentinc.com + user + axi_i2s_adi + 1.2 + + + S00_AXI + + + + + + + + + AWADDR + + + s00_axi_awaddr + + + + + AWPROT + + + s00_axi_awprot + + + + + AWVALID + + + s00_axi_awvalid + + + + + AWREADY + + + s00_axi_awready + + + + + WDATA + + + s00_axi_wdata + + + + + WSTRB + + + s00_axi_wstrb + + + + + WVALID + + + s00_axi_wvalid + + + + + WREADY + + + s00_axi_wready + + + + + BRESP + + + s00_axi_bresp + + + + + BVALID + + + s00_axi_bvalid + + + + + BREADY + + + s00_axi_bready + + + + + ARADDR + + + s00_axi_araddr + + + + + ARPROT + + + s00_axi_arprot + + + + + ARVALID + + + s00_axi_arvalid + + + + + ARREADY + + + s00_axi_arready + + + + + RDATA + + + s00_axi_rdata + + + + + RRESP + + + s00_axi_rresp + + + + + RVALID + + + s00_axi_rvalid + + + + + RREADY + + + s00_axi_rready + + + + + + WIZ.DATA_WIDTH + 32 + + + WIZ.NUM_REG + 12 + + + SUPPORTS_NARROW_BURST + 0 + + + + + S00_AXI_RST + + + + + + + RST + + + s00_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S00_AXI_CLK + + + + + + + CLK + + + s00_axi_aclk + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + ASSOCIATED_RESET + s00_axi_aresetn + + + + + S_AXIS + + + + + + + TVALID + + + S_AXIS_TVALID + + + + + TLAST + + + S_AXIS_TLAST + + + + + TDATA + + + S_AXIS_TDATA + + + + + TREADY + + + S_AXIS_TREADY + + + + + + + optional + true + + + + + + S_AXIS_CLK + + + + + + + CLK + + + S_AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXIS + + + + + + optional + true + + + + + + M_AXIS + + + + + + + TVALID + + + M_AXIS_TVALID + + + + + TLAST + + + M_AXIS_TLAST + + + + + TDATA + + + M_AXIS_TDATA + + + + + TKEEP + + + M_AXIS_TKEEP + + + + + TREADY + + + M_AXIS_TREADY + + + + + + + optional + true + + + + + + M_AXIS_CLK + + + + + + + CLK + + + M_AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS + + + + + + optional + true + + + + + + DMA_TX_REQ + + + + + + + TUSER + + + DMA_REQ_TX_DRTYPE + + + + + TVALID + + + DMA_REQ_TX_DRVALID + + + + + TLAST + + + DMA_REQ_TX_DRLAST + + + + + TREADY + + + DMA_REQ_TX_DRREADY + + + + + + + optional + false + + + + + + DMA_TX_ACK + + + + + + + TUSER + + + DMA_REQ_TX_DATYPE + + + + + TVALID + + + DMA_REQ_TX_DAVALID + + + + + TREADY + + + DMA_REQ_TX_DAREADY + + + + + + + optional + false + + + + + + DMA_RX_REQ + + + + + + + TUSER + + + DMA_REQ_RX_DRTYPE + + + + + TVALID + + + DMA_REQ_RX_DRVALID + + + + + TLAST + + + DMA_REQ_RX_DRLAST + + + + + TREADY + + + DMA_REQ_RX_DRREADY + + + + + + + optional + false + + + + + + DMA_RX_ACK + + + + + + + TUSER + + + DMA_REQ_RX_DATYPE + + + + + TVALID + + + DMA_REQ_RX_DAVALID + + + + + TREADY + + + DMA_REQ_RX_DAREADY + + + + + + + optional + false + + + + + + DMA_TX_CLK + + + + + + + CLK + + + DMA_REQ_TX_ACLK + + + + + + ASSOCIATED_BUSIF + DMA_TX_REQ:DMA_TX_ACK + + + ASSOCIATED_RESET + DMA_REQ_TX_RSTN + + + + + + optional + false + + + + + + DMA_TX_RST + + + + + + + RST + + + DMA_REQ_TX_RSTN + + + + + + POLARITY + ACTIVE_LOW + + + + + + optional + false + + + + + + DMA_RX_CLK + + + + + + + CLK + + + DMA_REQ_RX_ACLK + + + + + + ASSOCIATED_BUSIF + DMA_RX_REQ:DMA_RX_ACK + + + ASSOCIATED_RESET + DMA_REQ_RX_RSTN + + + + + + optional + false + + + + + + DMA_RX_RST + + + + + + + RST + + + DMA_REQ_RX_RSTN + + + + + + POLARITY + ACTIVE_LOW + + + + + + optional + false + + + + + + + + S00_AXI + + S00_AXI_reg + 0 + 4096 + 32 + register + + + OFFSET_BASE_PARAM + C_S00_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S00_AXI_HIGHADDR + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axi_i2s_adi_v1_2 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + c5577600 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axi_i2s_adi_v1_2 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + c5577600 + + + + + xilinx_softwaredriver + Software Driver + :vivado.xilinx.com:sw.driver + + xilinx_softwaredriver_view_fileset + + + + viewChecksum + d0fc4f4c + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e9171d0c + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + DATA_CLK_I + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + BCLK_O + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + LRCLK_O + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + SDATA_O + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + SDATA_I + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + MUTEN_O + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + 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DMA_REQ_TX_DAREADY + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DRVALID + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DRTYPE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DRLAST + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DRREADY + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_RSTN + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DAVALID + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DATYPE + + in + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DAREADY + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DRVALID + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DRTYPE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DRLAST + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DRREADY + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + 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xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_S00_AXI_DATA_WIDTH + C S00 AXI DATA WIDTH + Width of S_AXI data bus + 32 + + + C_S00_AXI_ADDR_WIDTH + C S00 AXI ADDR WIDTH + Width of S_AXI address bus + 6 + + + C_SLOT_WIDTH + C Slot Width + 24 + + + C_LRCLK_POL + C Lrclk Pol + 0 + + + C_BCLK_POL + C Bclk Pol + 0 + + + C_DMA_TYPE + C Dma Type + 0 + + + C_NUM_CH + C Num Ch + 1 + + + C_HAS_TX + C Has Tx + 1 + + + C_HAS_RX + C Has Rx + 1 + + + + + + choices_0 + 32 + + + choices_1 + 1 + 0 + + + choices_2 + 0 + 1 + + + choices_3 + 0 + 1 + + + choices_4 + 0 + 1 + + + choices_5 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choices_6 + 0 + 1 + + + choices_7 + 0 + 1 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axi_i2s_adi_v1_2.vhd + vhdlSource + CHECKSUM_c1ef5310 + + + hdl/i2s_rx.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/i2s_tx.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/i2s_clkgen.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/fifo_synchronizer.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/i2s_controller.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/adi_common/axi_ctrlif.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/adi_common/axi_streaming_dma_rx_fifo.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/adi_common/pl330_dma_fifo.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/adi_common/axi_streaming_dma_tx_fifo.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/adi_common/dma_fifo.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/axi_i2s_adi_S_AXI.vhd + vhdlSource + CHECKSUM_8dec4efa + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axi_i2s_adi_v1_2.vhd + vhdlSource + + + hdl/i2s_rx.vhd + vhdlSource + + + hdl/i2s_tx.vhd + vhdlSource + + + hdl/i2s_clkgen.vhd + vhdlSource + + + hdl/fifo_synchronizer.vhd + vhdlSource + + + hdl/i2s_controller.vhd + vhdlSource + + + hdl/adi_common/axi_ctrlif.vhd + vhdlSource + + + hdl/adi_common/axi_streaming_dma_rx_fifo.vhd + vhdlSource + + + hdl/adi_common/pl330_dma_fifo.vhd + vhdlSource + + + hdl/adi_common/axi_streaming_dma_tx_fifo.vhd + vhdlSource + + + hdl/adi_common/dma_fifo.vhd + vhdlSource + + + hdl/axi_i2s_adi_S_AXI.vhd + vhdlSource + + + + xilinx_softwaredriver_view_fileset + + drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.mdd + mdd + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl + tclSource + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/src/Makefile + unknown + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.h + cSource + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c + cSource + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c + cSource + USED_IN_hw_handoff + + + + xilinx_xpgui_view_fileset + + xgui/axi_i2s_adi_v1_2.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_70145134 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + Sends and receives audio data to/from an ADI I2S audio codec + + + C_S00_AXI_BASEADDR + AXI BASEADDR + 0xFFFFFFFF + + + + false + + + + + + C_S00_AXI_HIGHADDR + AXI HIGHADDR + 0x00000000 + + + + false + + + + + + Component_Name + axi_i2s_adi_v1_2 + + + C_LRCLK_POL + LRCLK Polarity + 0 + + + C_BCLK_POL + BCLK Polarity + 0 + + + C_DMA_TYPE + DMA Type + 0 + + + C_HAS_TX + Enable Audio Output + 1 + + + C_HAS_RX + Enable Audio Input + 1 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + AXI_Peripheral + + AXI I2S Audio + Digilent + http://www.digilentinc.com + 1 + + natinst.com:user:axi_i2s_adi:1.2 + + 2015-03-05T05:38:11Z + + C:/sam_work/Vivado_projects/14_4/ip_repo/axi_i2s_adi_1.2 + C:/sam_work/Vivado_projects/14_4/ip_repo/axi_i2s_adi_1.2 + + + + 2014.4 + + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl new file mode 100644 index 0000000..25ef87e --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "axi_i2s_adi" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c new file mode 100644 index 0000000..f950fdd --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c @@ -0,0 +1,6 @@ + + +/***************************** Include Files *******************************/ +#include "axi_i2s_adi.h" + +/************************** Function Definitions ***************************/ diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.h b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.h new file mode 100644 index 0000000..d13f29d --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.h @@ -0,0 +1,87 @@ + +#ifndef AXI_I2S_ADI_H +#define AXI_I2S_ADI_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define AXI_I2S_ADI_S00_AXI_SLV_REG0_OFFSET 0 +#define AXI_I2S_ADI_S00_AXI_SLV_REG1_OFFSET 4 +#define AXI_I2S_ADI_S00_AXI_SLV_REG2_OFFSET 8 +#define AXI_I2S_ADI_S00_AXI_SLV_REG3_OFFSET 12 +#define AXI_I2S_ADI_S00_AXI_SLV_REG4_OFFSET 16 +#define AXI_I2S_ADI_S00_AXI_SLV_REG5_OFFSET 20 +#define AXI_I2S_ADI_S00_AXI_SLV_REG6_OFFSET 24 +#define AXI_I2S_ADI_S00_AXI_SLV_REG7_OFFSET 28 +#define AXI_I2S_ADI_S00_AXI_SLV_REG8_OFFSET 32 +#define AXI_I2S_ADI_S00_AXI_SLV_REG9_OFFSET 36 +#define AXI_I2S_ADI_S00_AXI_SLV_REG10_OFFSET 40 +#define AXI_I2S_ADI_S00_AXI_SLV_REG11_OFFSET 44 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a AXI_I2S_ADI register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the AXI_I2S_ADIdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void AXI_I2S_ADI_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define AXI_I2S_ADI_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a AXI_I2S_ADI register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the AXI_I2S_ADI device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 AXI_I2S_ADI_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define AXI_I2S_ADI_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the AXI_I2S_ADI instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus AXI_I2S_ADI_Reg_SelfTest(void * baseaddr_p); + +#endif // AXI_I2S_ADI_H diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c new file mode 100644 index 0000000..3fe1e5a --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c @@ -0,0 +1,60 @@ + +/***************************** Include Files *******************************/ +#include "axi_i2s_adi.h" +#include "xparameters.h" +#include "stdio.h" +#include "xil_io.h" + +/************************** Constant Definitions ***************************/ +#define READ_WRITE_MUL_FACTOR 0x10 + +/************************** Function Definitions ***************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the AXI_I2S_ADIinstance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus AXI_I2S_ADI_Reg_SelfTest(void * baseaddr_p) +{ + u32 baseaddr; + int write_loop_index; + int read_loop_index; + int Index; + + baseaddr = (u32) baseaddr_p; + + xil_printf("******************************\n\r"); + xil_printf("* User Peripheral Self Test\n\r"); + xil_printf("******************************\n\n\r"); + + /* + * Write to user logic slave module register(s) and read back + */ + xil_printf("User logic slave module test...\n\r"); + + for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) + AXI_I2S_ADI_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); + for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) + if ( AXI_I2S_ADI_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ + xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); + return XST_FAILURE; + } + + xil_printf(" - slave register write/read passed\n\n\r"); + + return XST_SUCCESS; +} diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/axi_i2s_adi_v1_2_tb.v b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/axi_i2s_adi_v1_2_tb.v new file mode 100644 index 0000000..34f4457 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/axi_i2s_adi_v1_2_tb.v @@ -0,0 +1,184 @@ + +`timescale 1 ns / 1 ps + +`include "axi_i2s_adi_v1_2_tb_include.vh" + +// lite_response Type Defines +`define RESPONSE_OKAY 2'b00 +`define RESPONSE_EXOKAY 2'b01 +`define RESP_BUS_WIDTH 2 +`define BURST_TYPE_INCR 2'b01 +`define BURST_TYPE_WRAP 2'b10 + +// AMBA AXI4 Lite Range Constants +`define S00_AXI_MAX_BURST_LENGTH 1 +`define S00_AXI_DATA_BUS_WIDTH 32 +`define S00_AXI_ADDRESS_BUS_WIDTH 32 +`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8 + +module axi_i2s_adi_v1_2_tb; + reg tb_ACLK; + reg tb_ARESETn; + + // Create an instance of the example tb + `BD_WRAPPER dut (.ACLK(tb_ACLK), + .ARESETN(tb_ARESETn)); + + // Local Variables + + // AMBA S00_AXI AXI4 Lite Local Reg + reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite; + reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0]; + reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response; + reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress; + reg [3-1:0] S00_AXI_mtestProtection_lite; + integer S00_AXI_mtestvectorlite; // Master side testvector + integer S00_AXI_mtestdatasizelite; + integer result_slave_lite; + + + // Simple Reset Generator and test + initial begin + tb_ARESETn = 1'b0; + #500; + // Release the reset on the posedge of the clk. + @(posedge tb_ACLK); + tb_ARESETn = 1'b1; + @(posedge tb_ACLK); + end + + // Simple Clock Generator + initial tb_ACLK = 1'b0; + always #10 tb_ACLK = !tb_ACLK; + + //------------------------------------------------------------------------ + // TEST LEVEL API: CHECK_RESPONSE_OKAY + //------------------------------------------------------------------------ + // Description: + // CHECK_RESPONSE_OKAY(lite_response) + // This task checks if the return lite_response is equal to OKAY + //------------------------------------------------------------------------ + task automatic CHECK_RESPONSE_OKAY; + input [`RESP_BUS_WIDTH-1:0] response; + begin + if (response !== `RESPONSE_OKAY) begin + $display("TESTBENCH ERROR! lite_response is not OKAY", + "\n expected = 0x%h",`RESPONSE_OKAY, + "\n actual = 0x%h",response); + $stop; + end + end + endtask + + //------------------------------------------------------------------------ + // TEST LEVEL API: COMPARE_LITE_DATA + //------------------------------------------------------------------------ + // Description: + // COMPARE_LITE_DATA(expected,actual) + // This task checks if the actual data is equal to the expected data. + // X is used as don't care but it is not permitted for the full vector + // to be don't care. + //------------------------------------------------------------------------ + task automatic COMPARE_LITE_DATA; + input expected; + input actual; + begin + if (expected === 'hx || actual === 'hx) begin + $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); + result_slave_lite = 0; + $stop; + end + + if (actual != expected) begin + $display("TESTBENCH ERROR! Data expected is not equal to actual.", + "\nexpected = 0x%h",expected, + "\nactual = 0x%h",actual); + result_slave_lite = 0; + $stop; + end + else + begin + $display("TESTBENCH Passed! Data expected is equal to actual.", + "\n expected = 0x%h",expected, + "\n actual = 0x%h",actual); + end + end + endtask + + task automatic S00_AXI_TEST; + begin + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST : S00_AXI"); + $display("Simple register write and read example"); + $display("---------------------------------------------------------"); + + S00_AXI_mtestvectorlite = 0; + S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS; + S00_AXI_mtestProtection_lite = 0; + S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE; + + result_slave_lite = 1; + + for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1) + begin + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress, + S00_AXI_mtestProtection_lite, + S00_AXI_test_data_lite[S00_AXI_mtestvectorlite], + S00_AXI_mtestdatasizelite, + S00_AXI_lite_response); + $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response); + CHECK_RESPONSE_OKAY(S00_AXI_lite_response); + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress, + S00_AXI_mtestProtection_lite, + S00_AXI_rd_data_lite, + S00_AXI_lite_response); + $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response); + CHECK_RESPONSE_OKAY(S00_AXI_lite_response); + COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite); + $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite); + S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004; + end + + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); + if ( result_slave_lite ) begin + $display("PTGEN_TEST: PASSED!"); + end else begin + $display("PTGEN_TEST: FAILED!"); + end + $display("---------------------------------------------------------"); + end + endtask + + // Create the test vectors + initial begin + // When performing debug enable all levels of INFO messages. + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1); + + // Create test data vectors + S00_AXI_test_data_lite[0] = 32'h0101FFFF; + S00_AXI_test_data_lite[1] = 32'habcd0001; + S00_AXI_test_data_lite[2] = 32'hdead0011; + S00_AXI_test_data_lite[3] = 32'hbeef0011; + end + + // Drive the BFM + initial begin + // Wait for end of reset + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + S00_AXI_TEST(); + + end + +endmodule diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/design.tcl b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/design.tcl new file mode 100644 index 0000000..28acdfc --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/design.tcl @@ -0,0 +1,91 @@ +proc create_ipi_design { offsetfile design_name } { + create_bd_design $design_name + open_bd_design $design_name + + # Create Clock and Reset Ports + set ACLK [ create_bd_port -dir I -type clk ACLK ] + set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK + set ARESETN [ create_bd_port -dir I -type rst ARESETN ] + set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN + set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK + + # Create instance: axi_i2s_adi_0, and set properties + set axi_i2s_adi_0 [ create_bd_cell -type ip -vlnv natinst.com:user:axi_i2s_adi:1.2 axi_i2s_adi_0] + + # Create instance: master_0, and set properties + set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0] + set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0 + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins axi_i2s_adi_0/S00_AXI] + + # Create port connections + connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins axi_i2s_adi_0/S00_AXI_ACLK] + connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins axi_i2s_adi_0/S00_AXI_ARESETN] + + # Auto assign address + assign_bd_address + + # Copy all address to interface_address.vh file + set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/axi_i2s_adi_v1_2_tb_include.vh" + set fp [open $offset_file "w"] + puts $fp "`ifndef axi_i2s_adi_v1_2_tb_include_vh_" + puts $fp "`define axi_i2s_adi_v1_2_tb_include_vh_\n" + puts $fp "//Configuration current bd names" + puts $fp "`define BD_INST_NAME ${design_name}_i" + puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" + puts $fp "//Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]] + set offset_hex [string replace $offset 0 1 "32'h"] + puts $fp "`define S00_AXI_SLAVE_ADDRESS ${offset_hex}" + + puts $fp "`endif" + close $fp +} + +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores natinst.com:user:axi_i2s_adi:1.2]]]] +set test_bench_file ${ip_path}/example_designs/bfm_design/axi_i2s_adi_v1_2_tb.v +set interface_address_vh_file "" + +# Set IP Repository and Update IP Catalogue +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "axi_i2s_adi_v1_2_bfm_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +create_ipi_design interface_address_vh_file ${design_name} +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +set_property SOURCE_SET sources_1 [get_filesets sim_1] +import_files -fileset sim_1 -norecurse -force $test_bench_file +remove_files -quiet -fileset sim_1 axi_i2s_adi_v1_2_tb_include.vh +import_files -fileset sim_1 -norecurse -force $interface_address_vh_file +set_property top axi_i2s_adi_v1_2_tb [get_filesets sim_1] +set_property top_lib {} [get_filesets sim_1] +set_property top_file {} [get_filesets sim_1] +launch_xsim -simset sim_1 -mode behavioral +restart +run 1000 us diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/axi_i2s_adi_v1_2_hw_test.tcl b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/axi_i2s_adi_v1_2_hw_test.tcl new file mode 100644 index 0000000..21eba43 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/axi_i2s_adi_v1_2_hw_test.tcl @@ -0,0 +1,45 @@ +# Runtime Tcl commands to interact with - axi_i2s_adi_v1_2 + +# Sourcing design address info tcl +set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd +source ${bd_path}/axi_i2s_adi_v1_2_include.tcl + +# jtag axi master interface hardware name, change as per your design. +set jtag_axi_master hw_axi_1 +set ec 0 + +# hw test script +# Delete all previous axis transactions +if { [llength [get_hw_axi_txns -quiet]] } { + delete_hw_axi_txn [get_hw_axi_txns -quiet] +} + + +# Test all lite slaves. +set wdata_1 abcd1234 + +# Test: S00_AXI +# Create a write transaction at s00_axi_addr address +create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 +# Create a read transaction at s00_axi_addr address +create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr +# Initiate transactions +run_hw_axi r_s00_axi_addr +run_hw_axi w_s00_axi_addr +run_hw_axi r_s00_axi_addr +set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] +# Compare read data +if { $rdata_tmp == $wdata_1 } { + puts "Data comparison test pass for - S00_AXI" +} else { + puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" + inc ec +} + +# Check error flag +if { $ec == 0 } { + puts "PTGEN_TEST: PASSED!" +} else { + puts "PTGEN_TEST: FAILED!" +} + diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/design.tcl b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/design.tcl new file mode 100644 index 0000000..254844c --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/design.tcl @@ -0,0 +1,175 @@ + +proc create_ipi_design { offsetfile design_name } { + + create_bd_design $design_name + open_bd_design $design_name + + # Create and configure Clock/Reset + create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 + create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 + + #check if current_board is set, if true - figure out required clocks. + set is_board_clock_found 0 + set is_board_reset_found 0 + set external_reset_port "" + set external_clock_port "" + + if { [current_board_part -quiet] != "" } { + + #check if any reset interface exists in board. + set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ] + if { $board_reset ne "" } { + set is_board_reset_found 1 + apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design] + apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design] + set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]] + if { $external_rst ne "" } { + set external_reset_port [get_property NAME $external_rst] + } + } else { + send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually." + } + + # check for differential clock, exclude any special clocks which has TYPE property. + set board_clock_busifs "" + foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] { + set type [get_property PARAM.TYPE $busif] + if { $type == "" } { + set board_clock_busifs $busif + break + } + } + if { $board_clock_busifs ne "" } { + apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design] + set is_board_clock_found 1 + } else { + # check for single ended clock + set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ] + if { $board_sclock_busifs ne "" } { + apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design] + set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]] + if { $external_clk ne "" } { + set external_clock_port [get_property NAME $external_clk] + } + set is_board_clock_found 1 + } else { + send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually." + } + } + + } else { + send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually." + } + + #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning. + if { $is_board_reset_found == 0 } { + create_bd_port -dir I -type rst reset_rtl + set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] + set external_reset_port reset_rtl + } + if { $is_board_clock_found == 0 } { + create_bd_port -dir I -type clk clock_rtl + connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] + set external_clock_port clock_rtl + } + + #Avoid IPI DRC, make clock port synchronous to reset + if { $external_clock_port ne "" && $external_reset_port ne "" } { + set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] + } + + # Connect other sys_reset pins + connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] + + # Create instance: axi_i2s_adi_0, and set properties + set axi_i2s_adi_0 [ create_bd_cell -type ip -vlnv natinst.com:user:axi_i2s_adi:1.2 axi_i2s_adi_0 ] + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] + set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] + connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Create instance: axi_peri_interconnect, and set properties + set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] + connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] + set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] + + set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Connect all clock & reset of axi_i2s_adi_0 slave interfaces.. + connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins axi_i2s_adi_0/S00_AXI] + connect_bd_net [get_bd_pins axi_i2s_adi_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_i2s_adi_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + + # Auto assign address + assign_bd_address + + # Copy all address to axi_i2s_adi_v1_2_include.tcl file + set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/axi_i2s_adi_v1_2_include.tcl" + set fp [open $offset_file "w"] + puts $fp "# Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_i2s_adi_0_S00_AXI_* ]] + puts $fp "set s00_axi_addr ${offset}" + + close $fp +} + +# Set IP Repository and Update IP Catalogue +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores natinst.com:user:axi_i2s_adi:1.2]]]] +set hw_test_file ${ip_path}/example_designs/debug_hw_design/axi_i2s_adi_v1_2_hw_test.tcl + +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "axi_i2s_adi_v1_2_hw_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +set intf_address_include_file "" +create_ipi_design intf_address_include_file ${design_name} +save_bd_design +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +puts "-------------------------------------------------------------------------------------------------" +puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " +puts " please perform following steps to test design in targeted board." +puts "1. Generate bitstream" +puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" +puts "3. Download generated bitstream" +puts "4. Run generated hardware test using below command, this invokes basic read/write operation" +puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" +puts " : source -notrace ${hw_test_file}" +puts "-------------------------------------------------------------------------------------------------" + diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_ctrlif.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_ctrlif.vhd new file mode 100644 index 0000000..972b2c2 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_ctrlif.vhd @@ -0,0 +1,151 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_ctrlif is + generic + ( + C_NUM_REG : integer := 32; + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 32; + C_FAMILY : string := "virtex6" + ); + port + ( + -- AXI bus interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_RREADY : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_AWREADY : out std_logic; + + rd_addr : out integer range 0 to C_NUM_REG - 1; + rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + rd_ack : out std_logic; + rd_stb : in std_logic; + + wr_addr : out integer range 0 to C_NUM_REG - 1; + wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + wr_ack : in std_logic; + wr_stb : out std_logic + ); +end entity axi_ctrlif; + + +architecture Behavioral of axi_ctrlif is + type state_type is (IDLE, RESP, ACK); + signal rd_state : state_type; + signal wr_state : state_type; +begin + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + rd_state <= IDLE; + else + case rd_state is + when IDLE => + if S_AXI_ARVALID = '1' then + rd_state <= RESP; + rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); + end if; + when RESP => + if rd_stb = '1' and S_AXI_RREADY = '1' then + rd_state <= IDLE; + end if; + when others => null; + end case; + end if; + end if; + end process; + + S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; + S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; + S_AXI_RRESP <= "00"; + rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; + S_AXI_RDATA <= rd_data; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + wr_state <= IDLE; + else + case wr_state is + when IDLE => + if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then + wr_state <= ACK; + end if; + when ACK => + wr_state <= RESP; + when RESP => + if S_AXI_BREADY = '1' then + wr_state <= IDLE; + end if; + end case; + end if; + end if; + end process; + + wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; + wr_data <= S_AXI_WDATA; + wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); + + S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; + S_AXI_WREADY <= '1' when wr_state = ACK else '0'; + + S_AXI_BRESP <= "00"; + S_AXI_BVALID <= '1' when wr_state = RESP else '0'; +end; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_rx_fifo.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_rx_fifo.vhd new file mode 100644 index 0000000..99154a2 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_rx_fifo.vhd @@ -0,0 +1,80 @@ +library ieee; +use ieee.std_logic_1164.all; + +library adi_common_v1_00_a; +use adi_common_v1_00_a.dma_fifo; + +entity axi_streaming_dma_rx_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + period_len : in integer range 0 to 65535; + + -- Read port + M_AXIS_ACLK : in std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of axi_streaming_dma_rx_fifo is + signal out_stb : std_logic; + + signal period_count : integer range 0 to 65535; + signal last : std_logic; +begin + + M_AXIS_TVALID <= out_stb; + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => in_stb, + in_ack => in_ack, + in_data => in_data, + out_stb => out_stb, + out_ack => M_AXIS_TREADY, + out_data => M_AXIS_TDATA + ); + + M_AXIS_TKEEP <= "1111"; + M_AXIS_TLAST <= '1' when period_count = 0 else '0'; + + period_counter: process(M_AXIS_ACLK) is + begin + if resetn = '0' then + period_count <= period_len; + else + if out_stb = '1' and M_AXIS_TREADY = '1' then + if period_count = 0 then + period_count <= period_len; + else + period_count <= period_count - 1; + end if; + end if; + end if; + end process; +end; \ No newline at end of file diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd new file mode 100644 index 0000000..5d50208 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd @@ -0,0 +1,74 @@ +library ieee; +use ieee.std_logic_1164.all; + +library adi_common_v1_00_a; +use adi_common_v1_00_a.dma_fifo; + +entity axi_streaming_dma_tx_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + -- Write port + S_AXIS_ACLK : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TVALID : in std_logic; + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of axi_streaming_dma_tx_fifo is + signal in_ack : std_logic; + signal drain_dma : Boolean; +begin + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => S_AXIS_TVALID, + in_ack => in_ack, + in_data => S_AXIS_TDATA, + out_stb => out_stb, + out_ack => out_ack, + out_data => out_data + ); + + drain_process: process (S_AXIS_ACLK) is + variable enable_d1 : Boolean; + begin + if rising_edge(S_AXIS_ACLK) then + if resetn = '0' then + drain_dma <= False; + else + if S_AXIS_TLAST = '1' then + drain_dma <= False; + elsif enable_d1 and enable then + drain_dma <= True; + end if; + enable_d1 := enable; + end if; + end if; + end process; + + S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0'; +end; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/dma_fifo.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/dma_fifo.vhd new file mode 100644 index 0000000..5339d73 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/dma_fifo.vhd @@ -0,0 +1,69 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dma_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of dma_fifo is + + constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1; + type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0); + signal data_fifo : MEM; + signal wr_addr : natural range 0 to FIFO_MAX; + signal rd_addr : natural range 0 to FIFO_MAX; + signal full, empty : Boolean; + +begin + in_ack <= '0' when full else '1'; + + out_stb <= '0' when empty else '1'; + out_data <= data_fifo(rd_addr); + + fifo: process (clk) is + variable free_cnt : integer range 0 to FIFO_MAX + 1; + begin + if rising_edge(clk) then + if (resetn = '0') or (fifo_reset = '1') then + wr_addr <= 0; + rd_addr <= 0; + free_cnt := FIFO_MAX + 1; + empty <= True; + full <= False; + else + if in_stb = '1' and not full then + data_fifo(wr_addr) <= in_data; + wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1); + free_cnt := free_cnt - 1; + end if; + + if out_ack = '1' and not empty then + rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1); + free_cnt := free_cnt + 1; + end if; + + full <= free_cnt = 0; + empty <= free_cnt = FIFO_MAX + 1; + end if; + end if; + end process; +end; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/pl330_dma_fifo.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/pl330_dma_fifo.vhd new file mode 100644 index 0000000..2e53bbc --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/pl330_dma_fifo.vhd @@ -0,0 +1,140 @@ +library ieee; +use ieee.std_logic_1164.all; + +library adi_common_v1_00_a; +use adi_common_v1_00_a.dma_fifo; + +entity pl330_dma_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32; + FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- PL330 DMA interface + dclk : in std_logic; + dresetn : in std_logic; + davalid : in std_logic; + daready : out std_logic; + datype : in std_logic_vector(1 downto 0); + drvalid : out std_logic; + drready : in std_logic; + drtype : out std_logic_vector(1 downto 0); + drlast : out std_logic; + + DBG : out std_logic_vector(7 downto 0) + ); +end; + +architecture imp of pl330_dma_fifo is + signal request_data : Boolean; + + type state_type is (IDLE, REQUEST, WAITING, FLUSH); + signal state : state_type; + signal i_in_ack : std_logic; + signal i_out_stb : std_logic; +begin + + in_ack <= i_in_ack; + out_stb <= i_out_stb; + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => in_stb, + in_ack => i_in_ack, + in_data => in_data, + out_stb => i_out_stb, + out_ack => out_ack, + out_data => out_data + ); + + request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1'; + + drlast <= '0'; + daready <= '1'; + + drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0'; + drtype <= "00" when state = REQUEST else "10"; + + DBG(0) <= davalid; + DBG(2 downto 1) <= datype; + DBG(3) <= '1' when request_data else '0'; + + process (state) + begin + case state is + when IDLE => DBG(5 downto 4) <= "00"; + when REQUEST => DBG(5 downto 4) <= "01"; + when WAITING => DBG(5 downto 4) <= "10"; + when FLUSH => DBG(5 downto 4) <= "11"; + end case; + end process; + + pl330_req_fsm: process (dclk) is + begin + if rising_edge(dclk) then + if dresetn = '0' then + state <= IDLE; + else + -- The controller may send a FLUSH request at any time and it won't + -- respond to any of our requests until we've ack the FLUSH request. + -- The FLUSH request is also supposed to reset our state machine, so + -- go back to idle after having acked the FLUSH. + if davalid = '1' and datype = "10" then + state <= FLUSH; + else + case state is + -- Nothing to do, wait for the fifo to run empty + when IDLE => + if request_data and enable then + state <= REQUEST; + end if; + -- Send out a request to the PL330 + when REQUEST => + if drready = '1' then + state <= WAITING; + end if; + -- Wait for a ACK from the PL330 that it did transfer the data + when WAITING => + if fifo_reset = '1' then + state <= IDLE; + elsif davalid = '1' then + if datype = "00" then + state <= IDLE; + end if; + end if; + -- Send out an ACK for the flush + when FLUSH => + if drready = '1' then + state <= IDLE; + end if; + end case; + end if; + end if; + end if; + end process; +end; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_S_AXI.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_S_AXI.vhd new file mode 100644 index 0000000..26c72ae --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_S_AXI.vhd @@ -0,0 +1,361 @@ +-------------------------------------------------------------------------------- +-- +-- File: +-- axi_i2s_adi_S_AXI.vhd +-- +-- Module: +-- AXIS I2S Controller AXI Slave Interface +-- +-- Author: +-- Tinghui Wang (Steve) +-- Sam Bobrowicz +-- +-- Description: +-- AXI-Lite Register Interface for AXI I2S Controller +-- +-- Copyright notice: +-- Copyright (C) 2014 Digilent Inc. +-- +-- License: +-- This program is free software; distributed under the terms of +-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +-- OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity axi_i2s_adi_S_AXI is + generic ( + -- Users to add parameters here + + -- User parameters ends + -- Do not modify the parameters beyond this line + + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + rd_addr : out integer range 0 to 12 - 1; + rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + rd_ack : out std_logic; + + wr_addr : out integer range 0 to 12 - 1; + wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + wr_stb : out std_logic; + -- User ports ends + -- Do not modify the ports beyond this line + + -- Global Clock Signal + S_AXI_ACLK : in std_logic; + -- Global Reset Signal. This Signal is Active LOW + S_AXI_ARESETN : in std_logic; + -- Write address (issued by master, acceped by Slave) + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Write channel Protection type. This signal indicates the + -- privilege and security level of the transaction, and whether + -- the transaction is a data access or an instruction access. + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + -- Write address valid. This signal indicates that the master signaling + -- valid write address and control information. + S_AXI_AWVALID : in std_logic; + -- Write address ready. This signal indicates that the slave is ready + -- to accept an address and associated control signals. + S_AXI_AWREADY : out std_logic; + -- Write data (issued by master, acceped by Slave) + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Write strobes. This signal indicates which byte lanes hold + -- valid data. There is one write strobe bit for each eight + -- bits of the write data bus. + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + -- Write valid. This signal indicates that valid write + -- data and strobes are available. + S_AXI_WVALID : in std_logic; + -- Write ready. This signal indicates that the slave + -- can accept the write data. + S_AXI_WREADY : out std_logic; + -- Write response. This signal indicates the status + -- of the write transaction. + S_AXI_BRESP : out std_logic_vector(1 downto 0); + -- Write response valid. This signal indicates that the channel + -- is signaling a valid write response. + S_AXI_BVALID : out std_logic; + -- Response ready. This signal indicates that the master + -- can accept a write response. + S_AXI_BREADY : in std_logic; + -- Read address (issued by master, acceped by Slave) + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Protection type. This signal indicates the privilege + -- and security level of the transaction, and whether the + -- transaction is a data access or an instruction access. + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + -- Read address valid. This signal indicates that the channel + -- is signaling valid read address and control information. + S_AXI_ARVALID : in std_logic; + -- Read address ready. This signal indicates that the slave is + -- ready to accept an address and associated control signals. + S_AXI_ARREADY : out std_logic; + -- Read data (issued by slave) + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Read response. This signal indicates the status of the + -- read transfer. + S_AXI_RRESP : out std_logic_vector(1 downto 0); + -- Read valid. This signal indicates that the channel is + -- signaling the required read data. + S_AXI_RVALID : out std_logic; + -- Read ready. This signal indicates that the master can + -- accept the read data and response information. + S_AXI_RREADY : in std_logic + ); +end axi_i2s_adi_S_AXI; + +architecture arch_imp of axi_i2s_adi_S_AXI is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + wr_data <= S_AXI_WDATA; + wr_addr <= to_integer(unsigned(axi_awaddr((C_S_AXI_ADDR_WIDTH - 1) downto 2))); + wr_stb <= slv_reg_wren; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + rd_ack <= slv_reg_rden; + reg_data_out <= rd_data; + rd_addr <= to_integer(unsigned(axi_araddr((C_S_AXI_ADDR_WIDTH - 1) downto 2))); + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + + -- Add user logic here + + + -- User logic ends + +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_v1_2.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_v1_2.vhd new file mode 100644 index 0000000..83c3f39 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_v1_2.vhd @@ -0,0 +1,469 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library axi_i2s_adi_v1_00_a; +use axi_i2s_adi_v1_00_a.i2s_controller; + +library adi_common_v1_00_a; +use adi_common_v1_00_a.axi_streaming_dma_rx_fifo; +use adi_common_v1_00_a.axi_streaming_dma_tx_fifo; +use adi_common_v1_00_a.pl330_dma_fifo; +use adi_common_v1_00_a.axi_ctrlif; + + +entity axi_i2s_adi_v1_2 is + generic ( + -- Users to add parameters here + C_SLOT_WIDTH : integer := 24; + C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_DMA_TYPE : integer := 0; + C_NUM_CH : integer := 1; + C_HAS_TX : integer := 1; + C_HAS_RX : integer := 1; + -- User parameters ends + -- Do not modify the parameters beyond this line + + + -- Parameters of Axi Slave Bus Interface S00_AXI + C_S00_AXI_DATA_WIDTH : integer := 32; + C_S00_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + -- Users to add ports here + -- Serial Data interface + DATA_CLK_I : in std_logic; + BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); + LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); + SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); + SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); + MUTEN_O : out std_logic; + + -- AXI Streaming DMA TX interface + S_AXIS_ACLK : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TVALID : in std_logic; + + -- AXI Streaming DMA RX interface + M_AXIS_ACLK : in std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + + --PL330 DMA TX interface + DMA_REQ_TX_ACLK : in std_logic; + DMA_REQ_TX_RSTN : in std_logic; + DMA_REQ_TX_DAVALID : in std_logic; + DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0); + DMA_REQ_TX_DAREADY : out std_logic; + DMA_REQ_TX_DRVALID : out std_logic; + DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0); + DMA_REQ_TX_DRLAST : out std_logic; + DMA_REQ_TX_DRREADY : in std_logic; + + -- PL330 DMA RX interface + DMA_REQ_RX_ACLK : in std_logic; + DMA_REQ_RX_RSTN : in std_logic; + DMA_REQ_RX_DAVALID : in std_logic; + DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0); + DMA_REQ_RX_DAREADY : out std_logic; + DMA_REQ_RX_DRVALID : out std_logic; + DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0); + DMA_REQ_RX_DRLAST : out std_logic; + DMA_REQ_RX_DRREADY : in std_logic; + -- User ports ends + -- Do not modify the ports beyond this line + + + -- Ports of Axi Slave Bus Interface S00_AXI + s00_axi_aclk : in std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic + ); +end axi_i2s_adi_v1_2; + +architecture arch_imp of axi_i2s_adi_v1_2 is + + -- component declaration + component axi_i2s_adi_S_AXI is + generic ( + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + rd_addr : out integer range 0 to 12 - 1; + rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + rd_ack : out std_logic; + + wr_addr : out integer range 0 to 12 - 1; + wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + wr_stb : out std_logic; + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic + ); + end component axi_i2s_adi_S_AXI; + + signal i2s_reset : std_logic; +signal tx_fifo_reset : std_logic; +signal tx_enable : Boolean; +signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0); +signal tx_ack : std_logic; +signal tx_stb : std_logic; +signal tx_fifo_full : std_logic; +signal tx_fifo_empty : std_logic; +signal tx_in_ack : std_logic; + + +signal rx_enable : Boolean; +signal rx_fifo_reset : std_logic; +signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0); +signal rx_ack : std_logic; +signal rx_stb : std_logic; +signal rx_fifo_full : std_logic; +signal rx_fifo_empty : std_logic; +signal rx_out_stb : std_logic; + +signal bclk_div_rate : natural range 0 to 255; +signal lrclk_div_rate : natural range 0 to 255; + +signal period_len : integer range 0 to 65535; + +signal I2S_RESET_REG : std_logic_vector(31 downto 0); +signal I2S_CONTROL_REG : std_logic_vector(31 downto 0); +signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0); +signal PERIOD_LEN_REG : std_logic_vector(31 downto 0); + +constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8)))); + +-- Audio samples FIFO +constant RAM_ADDR_WIDTH : integer := 7; +type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0); + +-- RX FIFO signals +signal audio_fifo_rx : RAM_TYPE; +signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1; +signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1; +signal tvalid : std_logic := '0'; +signal rx_tlast : std_logic; +signal drain_tx_dma : std_logic; + +signal rx_sample : std_logic_vector(23 downto 0); + +signal wr_data : std_logic_vector(31 downto 0); +signal rd_data : std_logic_vector(31 downto 0); +signal wr_addr : integer range 0 to 11; +signal rd_addr : integer range 0 to 11; +signal wr_stb : std_logic; +signal rd_ack : std_logic; +signal tx_fifo_stb : std_logic; +signal rx_fifo_ack : std_logic; +signal cnt : integer range 0 to 2**16-1; + +begin + +-- Instantiation of Axi Bus Interface S00_AXI +axi_i2s_adi_S_AXI_inst : axi_i2s_adi_S_AXI + generic map ( + C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH + ) + port map ( + rd_addr => rd_addr, + rd_data => rd_data, + rd_ack => rd_ack, + + wr_addr => wr_addr, + wr_data => wr_data, + wr_stb => wr_stb, + S_AXI_ACLK => s00_axi_aclk, + S_AXI_ARESETN => s00_axi_aresetn, + S_AXI_AWADDR => s00_axi_awaddr, + S_AXI_AWPROT => s00_axi_awprot, + S_AXI_AWVALID => s00_axi_awvalid, + S_AXI_AWREADY => s00_axi_awready, + S_AXI_WDATA => s00_axi_wdata, + S_AXI_WSTRB => s00_axi_wstrb, + S_AXI_WVALID => s00_axi_wvalid, + S_AXI_WREADY => s00_axi_wready, + S_AXI_BRESP => s00_axi_bresp, + S_AXI_BVALID => s00_axi_bvalid, + S_AXI_BREADY => s00_axi_bready, + S_AXI_ARADDR => s00_axi_araddr, + S_AXI_ARPROT => s00_axi_arprot, + S_AXI_ARVALID => s00_axi_arvalid, + S_AXI_ARREADY => s00_axi_arready, + S_AXI_RDATA => s00_axi_rdata, + S_AXI_RRESP => s00_axi_rresp, + S_AXI_RVALID => s00_axi_rvalid, + S_AXI_RREADY => s00_axi_rready + ); + + -- Add user logic here +process (s00_axi_aclk) + begin + if rising_edge(s00_axi_aclk) then + if s00_axi_aresetn = '0' then + cnt <= 0; + else + cnt <= (cnt + 1) mod 2**16; + end if; + end if; + end process; + + streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate + tx_fifo : entity axi_streaming_dma_tx_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24 + ) + port map( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + S_AXIS_ACLK => S_AXIS_ACLK, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8), + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TVALID => S_AXIS_TVALID, + + out_stb => tx_stb, + out_ack => tx_ack, + out_data => tx_data + ); + end generate; + + streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate + rx_fifo : entity axi_streaming_dma_rx_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24 + ) + port map( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + period_len => period_len, + + in_stb => rx_stb, + in_ack => rx_ack, + in_data => rx_data, + + M_AXIS_ACLK => M_AXIS_ACLK, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8), + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TKEEP => M_AXIS_TKEEP + ); + + M_AXIS_TDATA(7 downto 0) <= (others => '0'); + end generate; + + pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate + tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0'; + + tx_fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24, + FIFO_DIRECTION => 0 + ) + port map ( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + in_data => wr_data(31 downto 8), + in_stb => tx_fifo_stb, + in_ack => tx_in_ack, + + out_ack => tx_ack, + out_stb => tx_stb, + out_data => tx_data, + + dclk => DMA_REQ_TX_ACLK, + dresetn => DMA_REQ_TX_RSTN, + davalid => DMA_REQ_TX_DAVALID, + daready => DMA_REQ_TX_DAREADY, + datype => DMA_REQ_TX_DATYPE, + drvalid => DMA_REQ_TX_DRVALID, + drready => DMA_REQ_TX_DRREADY, + drtype => DMA_REQ_TX_DRTYPE, + drlast => DMA_REQ_TX_DRLAST + ); + end generate; + + + pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate + rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0'; + + rx_fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24, + FIFO_DIRECTION => 1 + ) + port map ( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + fifo_reset => rx_fifo_reset, + enable => rx_enable, + + in_ack => rx_ack, + in_stb => rx_stb, + in_data => rx_data, + + out_data => rx_sample, + out_ack => rx_fifo_ack, + out_stb => rx_out_stb, + + dclk => DMA_REQ_RX_ACLK, + dresetn => DMA_REQ_RX_RSTN, + davalid => DMA_REQ_RX_DAVALID, + daready => DMA_REQ_RX_DAREADY, + datype => DMA_REQ_RX_DATYPE, + drvalid => DMA_REQ_RX_DRVALID, + drready => DMA_REQ_RX_DRREADY, + drtype => DMA_REQ_RX_DRTYPE, + drlast => DMA_REQ_RX_DRLAST + ); + end generate; + + ctrl : entity i2s_controller + generic map ( + C_SLOT_WIDTH => C_SLOT_WIDTH, + C_BCLK_POL => C_BCLK_POL, + C_LRCLK_POL => C_LRCLK_POL, + C_NUM_CH => C_NUM_CH, + C_HAS_TX => C_HAS_TX, + C_HAS_RX => C_HAS_RX + ) + port map ( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + + data_clk => DATA_CLK_I, + BCLK_O => BCLK_O, + LRCLK_O => LRCLK_O, + SDATA_O => SDATA_O, + SDATA_I => SDATA_I, + + tx_enable => tx_enable, + tx_ack => tx_ack, + tx_stb => tx_stb, + tx_data => tx_data, + + rx_enable => rx_enable, + rx_ack => rx_ack, + rx_stb => rx_stb, + rx_data => rx_data, + + bclk_div_rate => bclk_div_rate, + lrclk_div_rate => lrclk_div_rate + ); + + + + tx_fifo_full <= not(tx_in_ack); + tx_fifo_empty <= not(tx_stb); + rx_fifo_full <= not(rx_ack); + rx_fifo_empty <= not(rx_out_stb); + i2s_reset <= I2S_RESET_REG(0); + tx_fifo_reset <= I2S_RESET_REG(1); + rx_fifo_reset <= I2S_RESET_REG(2); + tx_enable <= I2S_CONTROL_REG(0) = '1'; + rx_enable <= I2S_CONTROL_REG(1) = '1'; + MUTEN_O <= not(I2S_CONTROL_REG(2)); + bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0))); + lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16))); + period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0))); + + process(rd_addr) + begin + case rd_addr is + when 1 => rd_data <= I2S_CONTROL_REG and x"00000007"; + when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff"; + when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff"; + when 8 => rd_data <= x"0000000" & rx_fifo_full & rx_fifo_empty & tx_fifo_full & tx_fifo_empty; + when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8)); + when others => rd_data <= (others => '0'); + end case; + end process; + + process(s00_axi_aclk) is + begin + if rising_edge(s00_axi_aclk) then + if s00_axi_aresetn = '0' then + I2S_RESET_REG <= (others => '0'); + I2S_CONTROL_REG <= (others => '0'); + I2S_CLK_CONTROL_REG <= (others => '0'); + PERIOD_LEN_REG <= (others => '0'); + else + -- Auto-clear the Reset Register bits + I2S_RESET_REG(0) <= '0'; + I2S_RESET_REG(1) <= '0'; + I2S_RESET_REG(2) <= '0'; + if wr_stb = '1' then + case wr_addr is + when 0 => I2S_RESET_REG <= wr_data; + when 1 => I2S_CONTROL_REG <= wr_data; + when 2 => I2S_CLK_CONTROL_REG <= wr_data; + when 6 => PERIOD_LEN_REG <= wr_data; + when others => null; + end case; + end if; + end if; + end if; + end process; + -- User logic ends + +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/fifo_synchronizer.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/fifo_synchronizer.vhd new file mode 100644 index 0000000..0218f34 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/fifo_synchronizer.vhd @@ -0,0 +1,108 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_synchronizer is + generic ( + DEPTH : integer := 4; + WIDTH : integer := 2 + ); + port ( + resetn : in std_logic; + + in_clk : in std_logic; + in_data : in std_logic_vector(WIDTH - 1 downto 0); + in_tick : in std_logic; + + out_clk : in std_logic; + out_data : out std_logic_vector(WIDTH - 1 downto 0); + out_tick : out std_logic + ); + +end fifo_synchronizer; + +architecture impl of fifo_synchronizer is + type DATA_SYNC_FIFO_TYPE is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0); + signal fifo: DATA_SYNC_FIFO_TYPE; + + signal rd_addr : natural range 0 to DEPTH - 1; + signal wr_addr : natural range 0 to DEPTH - 1; + + signal tick : std_logic; + signal tick_d1 : std_logic; + signal tick_d2 : std_logic; +begin + + process (in_clk) + begin + if rising_edge(in_clk) then + if resetn = '0' then + wr_addr <= 0; + tick <= '0'; + else + if in_tick = '1' then + fifo(wr_addr) <= in_data; + wr_addr <= (wr_addr + 1) mod DEPTH; + tick <= not tick; + end if; + end if; + end if; + end process; + + process (out_clk) + begin + if rising_edge(out_clk) then + if resetn = '0' then + rd_addr <= 0; + tick_d1 <= '0'; + tick_d2 <= '0'; + else + tick_d1 <= tick; + tick_d2 <= tick_d1; + out_tick <= tick_d1 xor tick_d2; + if (tick_d1 xor tick_d2) = '1' then + rd_addr <= (rd_addr + 1) mod DEPTH; + out_data <= fifo(rd_addr); + end if; + end if; + end if; + end process; + +end; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_clkgen.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_clkgen.vhd new file mode 100644 index 0000000..874099a --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_clkgen.vhd @@ -0,0 +1,133 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity i2s_clkgen is + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + + enable : in Boolean ; -- Enable clockgen + + tick : in std_logic; + + bclk_div_rate : in natural range 0 to 255; + lrclk_div_rate : in natural range 0 to 255; + + bclk : out std_logic; -- Bit Clock + lrclk : out std_logic; -- Frame Clock + channel_sync : out std_logic; + frame_sync : out std_logic + ); +end i2s_clkgen; + +architecture Behavioral of i2s_clkgen is + signal reset_int : Boolean; + + signal prev_bclk_div_rate : natural range 0 to 255; + signal prev_lrclk_div_rate : natural range 0 to 255; + + signal bclk_count : natural range 0 to 255; + signal lrclk_count : natural range 0 to 255; + + signal bclk_int : std_logic; + signal lrclk_int : std_logic; + + signal lrclk_tick : Boolean; +begin + + reset_int <= resetn = '0' or not enable; + + bclk <= bclk_int; + lrclk <= lrclk_int; + +----------------------------------------------------------------------------------- +-- Serial clock generation BCLK_O +----------------------------------------------------------------------------------- + bclk_gen: process(clk) + begin + if rising_edge(clk) then + prev_bclk_div_rate <= bclk_div_rate; + if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then + bclk_int <= '1'; + bclk_count <= bclk_div_rate; + else + if tick = '1' then + if bclk_count = bclk_div_rate then + bclk_count <= 0; + bclk_int <= not bclk_int; + else + bclk_count <= bclk_count + 1; + end if; + end if; + end if; + end if; + end process bclk_gen; + + lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1'; + + channel_sync <= '1' when lrclk_count = 1 else '0'; + frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0'; + +----------------------------------------------------------------------------------- +-- Frame clock generator LRCLK_O +----------------------------------------------------------------------------------- + lrclk_gen: process(clk) + begin + if rising_edge(clk) then + prev_lrclk_div_rate <= lrclk_div_rate; + -- Reset + if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then + lrclk_int <= '1'; + lrclk_count <= lrclk_div_rate; + else + if lrclk_tick then + if lrclk_count = lrclk_div_rate then + lrclk_count <= 0; + lrclk_int <= not lrclk_int; + else + lrclk_count <= lrclk_count + 1; + end if; + end if; + end if; + end if; + end process lrclk_gen; + +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_controller.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_controller.vhd new file mode 100644 index 0000000..59bde04 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_controller.vhd @@ -0,0 +1,282 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +library axi_i2s_adi_v1_00_a; +use axi_i2s_adi_v1_00_a.fifo_synchronizer; +use axi_i2s_adi_v1_00_a.i2s_clkgen; +use axi_i2s_adi_v1_00_a.i2s_tx; +use axi_i2s_adi_v1_00_a.i2s_rx; + +entity i2s_controller is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_NUM_CH : integer := 1; + C_HAS_TX : integer := 1; + C_HAS_RX : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + + data_clk : in std_logic; -- Data clock should be less than clk / 4 + BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock + LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock + SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output + SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input + + tx_enable : in Boolean; -- Enable TX + tx_ack : out std_logic; -- Request new Slot Data + tx_stb : in std_logic; -- Request new Slot Data + tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in + + rx_enable : in Boolean; -- Enable RX + rx_ack : in std_logic; + rx_stb : out std_logic; -- Valid Slot Data + rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out + + -- Runtime parameter + bclk_div_rate : in natural range 0 to 255; + lrclk_div_rate : in natural range 0 to 255 + ); +end i2s_controller; + +architecture Behavioral of i2s_controller is +constant NUM_TX : integer := C_HAS_TX * C_NUM_CH; +constant NUM_RX : integer := C_HAS_RX * C_NUM_CH; + +signal enable : Boolean; + +signal tick : std_logic; +signal tick_d1 : std_logic; +signal tick_d2 : std_logic; + +signal BCLK_O_int : std_logic; +signal LRCLK_O_int : std_logic; + +signal tx_bclk : std_logic; +signal tx_lrclk : std_logic; +signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0); +signal tx_tick : std_logic; +signal tx_channel_sync : std_logic; +signal tx_frame_sync : std_logic; + +signal bclk_tick : std_logic; + +signal rx_bclk : std_logic; +signal rx_lrclk : std_logic; +signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0); +signal rx_channel_sync : std_logic; +signal rx_frame_sync : std_logic; + +signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0); +signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0); +signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0); +signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0); + +begin + enable <= rx_enable or tx_enable; + + -- Generate tick signal in the DATA_CLK_I domain + process (data_clk) + begin + if rising_edge(data_clk) then + if resetn = '0' then + tick <= '0'; + else + tick <= not tick; + end if; + end if; + end process; + + process (clk) + begin + if rising_edge(clk) then + if resetn = '0' then + tick_d1 <= '0'; + tick_d2 <= '0'; + else + tick_d1 <= tick; + tick_d2 <= tick_d1; + end if; + end if; + end process; + + tx_tick <= tick_d2 xor tick_d1; + + tx_sync_fifo_in(0) <= tx_channel_sync; + tx_sync_fifo_in(1) <= tx_frame_sync; + tx_sync_fifo_in(2) <= tx_bclk; + tx_sync_fifo_in(3) <= tx_lrclk; + tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata; + + process (data_clk) + begin + if rising_edge(data_clk) then + if resetn = '0' then + BCLK_O <= (others => '1'); + LRCLK_O <= (others => '1'); + SDATA_O <= (others => '0'); + else + if C_BCLK_POL = 0 then + BCLK_O <= (others => tx_sync_fifo_out(2)); + else + BCLK_O <= (others => not tx_sync_fifo_out(2)); + end if; + + if C_LRCLK_POL = 0 then + LRCLK_O <= (others => tx_sync_fifo_out(3)); + else + LRCLK_O <= (others => not tx_sync_fifo_out(3)); + end if; + + if C_HAS_TX = 1 then + SDATA_O <= tx_sync_fifo_out(3 + NUM_TX downto 4); + end if; + + if C_HAS_RX = 1 then + rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0); + rx_sync_fifo_in(3 + NUM_RX downto 4) <= SDATA_I; + end if; + end if; + end if; + end process; + + tx_sync: entity fifo_synchronizer + generic map ( + DEPTH => 4, + WIDTH => NUM_TX + 4 + ) + port map ( + resetn => resetn, + in_clk => clk, + in_data => tx_sync_fifo_in, + in_tick => tx_tick, + + out_clk => data_clk, + out_data => tx_sync_fifo_out + ); + + clkgen: entity i2s_clkgen + port map( + clk => clk, + resetn => resetn, + enable => enable, + tick => tx_tick, + + bclk_div_rate => bclk_div_rate, + lrclk_div_rate => lrclk_div_rate, + + channel_sync => tx_channel_sync, + frame_sync => tx_frame_sync, + + bclk => tx_bclk, + lrclk => tx_lrclk + ); + + tx_gen: if C_HAS_TX = 1 generate + tx: entity i2s_tx + generic map ( + C_SLOT_WIDTH => C_SLOT_WIDTH, + C_NUM => NUM_TX + ) + port map ( + clk => clk, + resetn => resetn, + enable => tx_enable, + + channel_sync => tx_channel_sync, + frame_sync => tx_frame_sync, + bclk => tx_bclk, + sdata => tx_sdata, + + ack => tx_ack, + stb => tx_stb, + data => tx_data + ); + end generate; + + rx_gen: if C_HAS_RX = 1 generate + rx: entity i2s_rx + generic map ( + C_SLOT_WIDTH => C_SLOT_WIDTH, + C_NUM => NUM_RX + ) + port map ( + clk => clk, + resetn => resetn, + enable => rx_enable, + + channel_sync => rx_channel_sync, + frame_sync => rx_frame_sync, + bclk => rx_bclk, + sdata => rx_sdata, + + ack => rx_ack, + stb => rx_stb, + data => rx_data + ); + + rx_channel_sync <= rx_sync_fifo_out(0); + rx_frame_sync <= rx_sync_fifo_out(1); + rx_bclk <= rx_sync_fifo_out(2); + rx_lrclk <= rx_sync_fifo_out(3); + rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4); + + rx_sync: entity fifo_synchronizer + generic map ( + DEPTH => 4, + WIDTH => NUM_RX + 4 + ) + port map ( + resetn => resetn, + in_clk => data_clk, + in_data => rx_sync_fifo_in, + in_tick => '1', + + out_clk => clk, + out_data => rx_sync_fifo_out + ); + + end generate; + +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_rx.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_rx.vhd new file mode 100644 index 0000000..aa4e584 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_rx.vhd @@ -0,0 +1,180 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2s_rx is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_NUM : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + enable : in Boolean; -- Enable RX + + bclk : in std_logic; -- Bit Clock + channel_sync : in std_logic; -- Channel Sync + frame_sync : in std_logic; -- Frame Sync + sdata : in std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output + + stb : out std_logic; -- Data available + ack : in std_logic; -- Data has been consumed + data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in + ); +end i2s_rx; + +architecture Behavioral of i2s_rx is + type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0); + type mem_latched is array (0 to C_NUM - 1) of std_logic_vector(C_SLOT_WIDTH - 1 downto 0); + signal data_int : mem; + signal data_latched : mem_latched; + signal reset_int : Boolean; + signal enable_int : Boolean; + + signal bit_sync : std_logic; + signal channel_sync_int : std_logic; + signal frame_sync_int : std_logic; + + signal bclk_d1 : std_logic; + + type sequencer_state_type is (IDLE, ACTIVE); + signal sequencer_state : sequencer_state_type; + signal seq : natural range 0 to C_NUM - 1; + + signal ovf_frame_cnt : natural range 0 to 1; +begin + + reset_int <= (resetn = '0') or not enable; + + process (clk) + begin + if rising_edge(clk) then + if resetn = '0' then + bclk_d1 <= '0'; + else + bclk_d1 <= bclk; + end if; + end if; + end process; + + bit_sync <= (bclk xor bclk_d1) and bclk; + channel_sync_int <= channel_sync and bit_sync; + frame_sync_int <= frame_sync and bit_sync; + + stb <= '1' when sequencer_state = ACTIVE else '0'; + + sequencer: process (clk) + begin + if rising_edge(clk) then + if reset_int or not enable_int then + sequencer_state <= IDLE; + ovf_frame_cnt <= 0; + seq <= 0; + else + case sequencer_state is + when IDLE => + if channel_sync_int = '1' then + if ovf_frame_cnt = 0 then + sequencer_state <= ACTIVE; + else + ovf_frame_cnt <= (ovf_frame_cnt + 1) mod 2; + end if; + end if; + when ACTIVE => + -- The unlikely event the last ack came in in the same clock + -- cyclce as the channel sync signal will still be treated + -- as an overflow. This keeps the logic simple + if ack = '1' then + if seq = C_NUM - 1 then + sequencer_state <= IDLE; + seq <= 0; + else + seq <= seq + 1; + end if; + end if; + if channel_sync_int = '1' then + ovf_frame_cnt <= (ovf_frame_cnt + 1) mod 2; + end if; + end case; + end if; + end if; + end process; + + data <= data_latched(seq); + + gen: for i in 0 to C_NUM - 1 generate + + unserialize_data: process(clk) + begin + if rising_edge(clk) then + if reset_int then + data_int(i) <= (others => '0'); + elsif bit_sync = '1' then + if channel_sync = '1' then + if sequencer_state = IDLE then + data_latched(i) <= data_int(i)(31 downto 32 - C_SLOT_WIDTH); +-- data_latched(i) <= data_int(i)(31 downto 32 - +-- C_SLOT_WIDTH + 8) & +-- std_logic_vector(to_unsigned(i+1,8)); + end if; + end if; + data_int(i) <= data_int(i)(30 downto 0) & sdata(i); + end if; + end if; + end process unserialize_data; + end generate; + + enable_sync: process (clk) + begin + if rising_edge(clk) then + if reset_int then + enable_int <= False; + else + if enable and frame_sync_int = '1' then + enable_int <= True; + elsif not enable then + enable_int <= False; + end if; + end if; + end if; + end process enable_sync; + +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_tx.vhd b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_tx.vhd new file mode 100644 index 0000000..a055d15 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/hdl/i2s_tx.vhd @@ -0,0 +1,134 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity i2s_tx is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_NUM : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + enable : in Boolean; -- Enable TX + + bclk : in std_logic; -- Bit Clock + channel_sync : in std_logic; -- Channel Sync + frame_sync : in std_logic; -- Frame Sync + sdata : out std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output + + ack : out std_logic; -- Request new Slot Data + stb : in std_logic; -- Request new Slot Data + data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in + ); +end i2s_tx; + +architecture Behavioral of i2s_tx is + type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0); + signal data_int : mem; + signal reset_int : Boolean; + signal enable_int : Boolean; + + signal bit_sync : std_logic; + signal channel_sync_int : std_logic; + signal frame_sync_int : std_logic; + signal channel_sync_int_d1 : std_logic; + + signal bclk_d1 : std_logic; +begin + + reset_int <= resetn = '0' or not enable; + + process (clk) + begin + if rising_edge(clk) then + if resetn = '0' then + bclk_d1 <= '0'; + channel_sync_int_d1 <= '0'; + else + bclk_d1 <= bclk; + channel_sync_int_d1 <= channel_sync_int; + end if; + end if; + end process; + + bit_sync <= (bclk xor bclk_d1) and not bclk; + channel_sync_int <= channel_sync and bit_sync; + frame_sync_int <= frame_sync and bit_sync; + + ack <= '1' when channel_sync_int_d1 = '1' and enable_int else '0'; + + gen: for i in 0 to C_NUM - 1 generate + + serialize_data: process(clk) + begin + if rising_edge(clk) then + if reset_int then + data_int(i)(31 downto 0) <= (others => '0'); + elsif bit_sync = '1' then + if channel_sync_int = '1' then + data_int(i)(31 downto 32-C_SLOT_WIDTH) <= data; + data_int(i)(31-C_SLOT_WIDTH downto 0) <= (others => '0'); + else + data_int(i) <= data_int(i)(30 downto 0) & '0'; + end if; + end if; + end if; + end process serialize_data; + sdata(i) <= data_int(i)(31) when enable_int else '0'; + + end generate; + + enable_sync: process (clk) + begin + if rising_edge(clk) then + if reset_int then + enable_int <= False; + else + if enable and frame_sync_int = '1' and stb = '1' then + enable_int <= True; + elsif not enable then + enable_int <= False; + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/xgui/axi_i2s_adi_v1_2.tcl b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/xgui/axi_i2s_adi_v1_2.tcl new file mode 100644 index 0000000..df0c86f --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_i2s_adi_1.2/xgui/axi_i2s_adi_v1_2.tcl @@ -0,0 +1,105 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_LRCLK_POL" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_BCLK_POL" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_DMA_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_HAS_TX" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_HAS_RX" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_BCLK_POL { PARAM_VALUE.C_BCLK_POL } { + # Procedure called to update C_BCLK_POL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_BCLK_POL { PARAM_VALUE.C_BCLK_POL } { + # Procedure called to validate C_BCLK_POL + return true +} + +proc update_PARAM_VALUE.C_DMA_TYPE { PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to update C_DMA_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_DMA_TYPE { PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to validate C_DMA_TYPE + return true +} + +proc update_PARAM_VALUE.C_HAS_RX { PARAM_VALUE.C_HAS_RX } { + # Procedure called to update C_HAS_RX when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_HAS_RX { PARAM_VALUE.C_HAS_RX } { + # Procedure called to validate C_HAS_RX + return true +} + +proc update_PARAM_VALUE.C_HAS_TX { PARAM_VALUE.C_HAS_TX } { + # Procedure called to update C_HAS_TX when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_HAS_TX { PARAM_VALUE.C_HAS_TX } { + # Procedure called to validate C_HAS_TX + return true +} + +proc update_PARAM_VALUE.C_LRCLK_POL { PARAM_VALUE.C_LRCLK_POL } { + # Procedure called to update C_LRCLK_POL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_LRCLK_POL { PARAM_VALUE.C_LRCLK_POL } { + # Procedure called to validate C_LRCLK_POL + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to validate C_S00_AXI_BASEADDR + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to validate C_S00_AXI_HIGHADDR + return true +} + + +proc update_MODELPARAM_VALUE.C_LRCLK_POL { MODELPARAM_VALUE.C_LRCLK_POL PARAM_VALUE.C_LRCLK_POL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_LRCLK_POL}] ${MODELPARAM_VALUE.C_LRCLK_POL} +} + +proc update_MODELPARAM_VALUE.C_BCLK_POL { MODELPARAM_VALUE.C_BCLK_POL PARAM_VALUE.C_BCLK_POL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_BCLK_POL}] ${MODELPARAM_VALUE.C_BCLK_POL} +} + +proc update_MODELPARAM_VALUE.C_DMA_TYPE { MODELPARAM_VALUE.C_DMA_TYPE PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_DMA_TYPE}] ${MODELPARAM_VALUE.C_DMA_TYPE} +} + +proc update_MODELPARAM_VALUE.C_HAS_TX { MODELPARAM_VALUE.C_HAS_TX PARAM_VALUE.C_HAS_TX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_HAS_TX}] ${MODELPARAM_VALUE.C_HAS_TX} +} + +proc update_MODELPARAM_VALUE.C_HAS_RX { MODELPARAM_VALUE.C_HAS_RX PARAM_VALUE.C_HAS_RX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_HAS_RX}] ${MODELPARAM_VALUE.C_HAS_RX} +} + diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/axi_reg32_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/component.xml b/zynqberrydemo1/ip_lib/axi_reg32_1.0/component.xml new file mode 100644 index 0000000..f1f9721 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/component.xml @@ -0,0 +1,2288 @@ + + + trenz.biz + user + axi_reg32 + 1.0 + + + S_AXI + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + WIZ.DATA_WIDTH + 32 + + + WIZ.NUM_REG + 32 + + + SUPPORTS_NARROW_BURST + 0 + + + + + S_AXI_RST + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S_AXI_CLK + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + + + S_AXI + + S_AXI_reg + 0 + 4096 + 32 + register + + + OFFSET_BASE_PARAM + C_S_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S_AXI_HIGHADDR + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axi_reg32_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + e1c055d0 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axi_reg32_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + e1c055d0 + + + + + xilinx_softwaredriver + Software Driver + :vivado.xilinx.com:sw.driver + + xilinx_softwaredriver_view_fileset + + + + viewChecksum + 61d40803 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c9c5ebb6 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + a8354ffc + + + + + + + RR0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + RR1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + RR2 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + 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Width of S_AXI address bus + 7 + + + C_REG_WIDTH + C Reg Width + 32 + + + + false + + + + + + C_NUM_RO_REG + C Num Ro Reg + 2 + + + C_NUM_WR_REG + C Num Wr Reg + 2 + + + C_WR_READABLE + C Wr Readable + true + + + C_RR0_ALIAS + C Rr0 Alias + RR0 + + + C_RR1_ALIAS + C Rr1 Alias + RR1 + + + C_WR0_ALIAS + C Wr0 Alias + WR0 + + + C_WR1_ALIAS + C Wr1 Alias + WR1 + + + C_RR2_ALIAS + C Rr2 Alias + RR2 + + + C_RR3_ALIAS + C Rr3 Alias + RR3 + + + C_RR4_ALIAS + C Rr4 Alias + RR4 + + + C_RR5_ALIAS + C Rr5 Alias + RR5 + + + C_RR6_ALIAS + C Rr6 Alias + RR6 + + + C_RR7_ALIAS + C Rr7 Alias + RR7 + + + C_RR8_ALIAS + C Rr8 Alias + RR8 + + + C_RR9_ALIAS + C Rr9 Alias + RR9 + + + C_RR10_ALIAS + C Rr10 Alias + RR10 + + + C_RR11_ALIAS + C Rr11 Alias + RR11 + + + C_RR12_ALIAS + C Rr12 Alias + RR12 + + + C_RR13_ALIAS + C Rr13 Alias + RR13 + + + C_RR14_ALIAS + C Rr14 Alias + RR14 + + + C_RR15_ALIAS + C Rr15 Alias + RR15 + + + C_WR2_ALIAS + C Wr2 Alias + WR2 + + + C_WR3_ALIAS + C Wr3 Alias + WR3 + + + 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C_WR13_DEFAULT + C Wr13 Default + 0 + + + C_WR14_DEFAULT + C Wr14 Default + 0 + + + C_WR15_DEFAULT + C Wr15 Default + 0 + + + + + + choices_0 + 32 + + + choices_1 + 1 + 0 + + + choices_2 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + choices_3 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axi_reg32_v1_0_S_AXI.vhd + vhdlSource + axi_lib + + + hdl/axi_reg32_v1_0.vhd + vhdlSource + CHECKSUM_99fe5a45 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axi_reg32_v1_0_S_AXI.vhd + vhdlSource + axi_lib + + + hdl/axi_reg32_v1_0.vhd + vhdlSource + + + + xilinx_softwaredriver_view_fileset + + drivers/axi_reg32_v1_0/data/axi_reg32.mdd + mdd + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/data/axi_reg32.tcl + tclSource + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/src/Makefile + unknown + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/src/axi_reg32.h + cSource + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/src/axi_reg32.c + cSource + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/src/axi_reg32_selftest.c + cSource + USED_IN_hw_handoff + + + + xilinx_xpgui_view_fileset + + xgui/axi_reg32_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_11b62932 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_utilityxitfiles_view_fileset + + gui/axi_reg32_v1_0.gtcl + GTCL + + + + AXI Register Bank 16/16 v1.0 + + + C_S_AXI_DATA_WIDTH + C S AXI DATA WIDTH + Width of S_AXI data bus + 32 + + + + false + + + + + + C_S_AXI_ADDR_WIDTH + C S AXI ADDR WIDTH + Width of S_AXI address bus + 7 + + + + false + + + + + + C_S_AXI_BASEADDR + C S AXI BASEADDR + 0xFFFFFFFF + + + + false + + + + + + C_S_AXI_HIGHADDR + C S AXI HIGHADDR + 0x00000000 + + + + false + + + + + + Component_Name + axi_reg32_v1_0 + + + C_NUM_RO_REG + Number of input registers + 2 + + + C_NUM_WR_REG + Number of output registers + 2 + + + C_WR_READABLE + Output registers are readable + true + + + C_RR0_ALIAS + RR0 + RR0 + + + + true + + + + + + C_RR1_ALIAS + RR1 + RR1 + + + + true + + + + + + C_WR0_ALIAS + WR0 + WR0 + + + C_WR1_ALIAS + WR1 + WR1 + + + C_RR2_ALIAS + RR2 + RR2 + + + C_RR3_ALIAS + RR3 + RR3 + + + C_RR4_ALIAS + RR4 + RR4 + + + C_RR5_ALIAS + RR5 + RR5 + + + C_RR6_ALIAS + RR6 + RR6 + + + C_RR7_ALIAS + RR7 + RR7 + + + C_RR8_ALIAS + RR8 + RR8 + + + C_RR9_ALIAS + RR9 + RR9 + + + C_RR10_ALIAS + RR10 + RR10 + + + C_RR11_ALIAS + RR11 + RR11 + + + C_RR12_ALIAS + RR12 + RR12 + + + C_RR13_ALIAS + RR13 + RR13 + + + C_RR14_ALIAS + RR14 + RR14 + + + C_RR15_ALIAS + RR15 + RR15 + + + C_WR2_ALIAS + WR2 + WR2 + + + C_WR3_ALIAS + WR3 + WR3 + + + C_WR4_ALIAS + WR4 + WR4 + + + C_WR5_ALIAS + WR5 + WR5 + + + C_WR6_ALIAS + WR6 + WR6 + + + C_WR7_ALIAS + WR7 + WR7 + + + C_WR8_ALIAS + WR8 + WR8 + + + C_WR9_ALIAS + WR9 + WR9 + + + C_WR10_ALIAS + WR10 + WR10 + + + C_WR11_ALIAS + WR11 + WR11 + + + C_WR12_ALIAS + WR12 + WR12 + + + C_WR13_ALIAS + WR13 + WR13 + + + C_WR14_ALIAS + WR14 + WR14 + + + C_WR15_ALIAS + WR15 + WR15 + + + C_WR0_DEFAULT + WR0 Value + 0 + + + C_WR1_DEFAULT + WR1 Value + 0 + + + C_WR2_DEFAULT + WR2 Value + 0 + + + C_WR3_DEFAULT + WR3 Value + 0 + + + C_WR4_DEFAULT + WR4 Value + 0 + + + C_WR5_DEFAULT + WR5 Value + 0 + + + C_WR6_DEFAULT + WR6 Value + 0 + + + C_WR7_DEFAULT + WR7 Value + 0 + + + C_WR8_DEFAULT + WR8 Value + 0 + + + C_WR9_DEFAULT + WR9 Value + 0 + + + C_WR10_DEFAULT + WR10 Value + 0 + + + C_WR11_DEFAULT + WR11 Value + 0 + + + C_WR12_DEFAULT + WR12 Value + 0 + + + C_WR13_DEFAULT + WR13 Value + 0 + + + C_WR14_DEFAULT + WR14 Value + 0 + + + C_WR15_DEFAULT + WR15 Value + 0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + AXI_Peripheral + + AXI Register Bank 16/16 v1.0 + Trenz Electronic GmbH + 13 + 2015-12-03T08:47:21Z + + b:/cores/2014.4/ip/axi_reg32_1.0 + + + + 2014.4 + + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/data/axi_reg32.tcl b/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/data/axi_reg32.tcl new file mode 100644 index 0000000..9044b7c --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/data/axi_reg32.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "axi_reg32" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" +} diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.c b/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.c new file mode 100644 index 0000000..1db5c5c --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.c @@ -0,0 +1,6 @@ + + +/***************************** Include Files *******************************/ +#include "axi_reg32.h" + +/************************** Function Definitions ***************************/ diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.h b/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.h new file mode 100644 index 0000000..58bb7b4 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.h @@ -0,0 +1,107 @@ + +#ifndef AXI_REG32_H +#define AXI_REG32_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define RR0_OFFSET 0 +#define RR1_OFFSET 4 +#define RR2_OFFSET 8 +#define RR3_OFFSET 12 +#define RR4_OFFSET 16 +#define RR5_OFFSET 20 +#define RR6_OFFSET 24 +#define RR7_OFFSET 28 +#define RR8_OFFSET 32 +#define RR9_OFFSET 36 +#define RR10_OFFSET 40 +#define RR11_OFFSET 44 +#define RR12_OFFSET 48 +#define RR13_OFFSET 52 +#define RR14_OFFSET 56 +#define RR15_OFFSET 60 +#define WR0_OFFSET 64 +#define WR1_OFFSET 68 +#define WR2_OFFSET 72 +#define WR3_OFFSET 76 +#define WR4_OFFSET 80 +#define WR5_OFFSET 84 +#define WR6_OFFSET 88 +#define WR7_OFFSET 92 +#define WR8_OFFSET 96 +#define WR9_OFFSET 100 +#define WR10_OFFSET 104 +#define WR11_OFFSET 108 +#define WR12_OFFSET 112 +#define WR13_OFFSET 116 +#define WR14_OFFSET 120 +#define WR15_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a AXI_REG32 register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the AXI_REG32device. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void AXI_REG32_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define AXI_REG32_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a AXI_REG32 register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the AXI_REG32 device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 AXI_REG32_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define AXI_REG32_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the AXI_REG32 instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus AXI_REG32_Reg_SelfTest(void * baseaddr_p); + +#endif // AXI_REG32_H diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32_selftest.c b/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32_selftest.c new file mode 100644 index 0000000..dc45655 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32_selftest.c @@ -0,0 +1,60 @@ + +/***************************** Include Files *******************************/ +#include "axi_reg32.h" +#include "xparameters.h" +#include "stdio.h" +#include "xil_io.h" + +/************************** Constant Definitions ***************************/ +#define READ_WRITE_MUL_FACTOR 0x10 + +/************************** Function Definitions ***************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the AXI_REG32instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus AXI_REG32_Reg_SelfTest(void * baseaddr_p) +{ + u32 baseaddr; + int write_loop_index; + int read_loop_index; + int Index; + + baseaddr = (u32) baseaddr_p; + + xil_printf("******************************\n\r"); + xil_printf("* User Peripheral Self Test\n\r"); + xil_printf("******************************\n\n\r"); + + /* + * Write to user logic slave module register(s) and read back + */ + xil_printf("User logic slave module test...\n\r"); + + for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) + AXI_REG32_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); + for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) + if ( AXI_REG32_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ + xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); + return XST_FAILURE; + } + + xil_printf(" - slave register write/read passed\n\n\r"); + + return XST_SUCCESS; +} diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/bfm_design/axi_reg32_v1_0_tb.v b/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/bfm_design/axi_reg32_v1_0_tb.v new file mode 100644 index 0000000..a2b9560 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/bfm_design/axi_reg32_v1_0_tb.v @@ -0,0 +1,184 @@ + +`timescale 1 ns / 1 ps + +`include "axi_reg32_v1_0_tb_include.vh" + +// lite_response Type Defines +`define RESPONSE_OKAY 2'b00 +`define RESPONSE_EXOKAY 2'b01 +`define RESP_BUS_WIDTH 2 +`define BURST_TYPE_INCR 2'b01 +`define BURST_TYPE_WRAP 2'b10 + +// AMBA AXI4 Lite Range Constants +`define S_AXI_MAX_BURST_LENGTH 1 +`define S_AXI_DATA_BUS_WIDTH 32 +`define S_AXI_ADDRESS_BUS_WIDTH 32 +`define S_AXI_MAX_DATA_SIZE (`S_AXI_DATA_BUS_WIDTH*`S_AXI_MAX_BURST_LENGTH)/8 + +module axi_reg32_v1_0_tb; + reg tb_ACLK; + reg tb_ARESETn; + + // Create an instance of the example tb + `BD_WRAPPER dut (.ACLK(tb_ACLK), + .ARESETN(tb_ARESETn)); + + // Local Variables + + // AMBA S_AXI AXI4 Lite Local Reg + reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_rd_data_lite; + reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_test_data_lite [3:0]; + reg [`RESP_BUS_WIDTH-1:0] S_AXI_lite_response; + reg [`S_AXI_ADDRESS_BUS_WIDTH-1:0] S_AXI_mtestAddress; + reg [3-1:0] S_AXI_mtestProtection_lite; + integer S_AXI_mtestvectorlite; // Master side testvector + integer S_AXI_mtestdatasizelite; + integer result_slave_lite; + + + // Simple Reset Generator and test + initial begin + tb_ARESETn = 1'b0; + #500; + // Release the reset on the posedge of the clk. + @(posedge tb_ACLK); + tb_ARESETn = 1'b1; + @(posedge tb_ACLK); + end + + // Simple Clock Generator + initial tb_ACLK = 1'b0; + always #10 tb_ACLK = !tb_ACLK; + + //------------------------------------------------------------------------ + // TEST LEVEL API: CHECK_RESPONSE_OKAY + //------------------------------------------------------------------------ + // Description: + // CHECK_RESPONSE_OKAY(lite_response) + // This task checks if the return lite_response is equal to OKAY + //------------------------------------------------------------------------ + task automatic CHECK_RESPONSE_OKAY; + input [`RESP_BUS_WIDTH-1:0] response; + begin + if (response !== `RESPONSE_OKAY) begin + $display("TESTBENCH ERROR! lite_response is not OKAY", + "\n expected = 0x%h",`RESPONSE_OKAY, + "\n actual = 0x%h",response); + $stop; + end + end + endtask + + //------------------------------------------------------------------------ + // TEST LEVEL API: COMPARE_LITE_DATA + //------------------------------------------------------------------------ + // Description: + // COMPARE_LITE_DATA(expected,actual) + // This task checks if the actual data is equal to the expected data. + // X is used as don't care but it is not permitted for the full vector + // to be don't care. + //------------------------------------------------------------------------ + task automatic COMPARE_LITE_DATA; + input expected; + input actual; + begin + if (expected === 'hx || actual === 'hx) begin + $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); + result_slave_lite = 0; + $stop; + end + + if (actual != expected) begin + $display("TESTBENCH ERROR! Data expected is not equal to actual.", + "\nexpected = 0x%h",expected, + "\nactual = 0x%h",actual); + result_slave_lite = 0; + $stop; + end + else + begin + $display("TESTBENCH Passed! Data expected is equal to actual.", + "\n expected = 0x%h",expected, + "\n actual = 0x%h",actual); + end + end + endtask + + task automatic S_AXI_TEST; + begin + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST : S_AXI"); + $display("Simple register write and read example"); + $display("---------------------------------------------------------"); + + S_AXI_mtestvectorlite = 0; + S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS; + S_AXI_mtestProtection_lite = 0; + S_AXI_mtestdatasizelite = `S_AXI_MAX_DATA_SIZE; + + result_slave_lite = 1; + + for (S_AXI_mtestvectorlite = 0; S_AXI_mtestvectorlite <= 3; S_AXI_mtestvectorlite = S_AXI_mtestvectorlite + 1) + begin + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S_AXI_mtestAddress, + S_AXI_mtestProtection_lite, + S_AXI_test_data_lite[S_AXI_mtestvectorlite], + S_AXI_mtestdatasizelite, + S_AXI_lite_response); + $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_lite_response); + CHECK_RESPONSE_OKAY(S_AXI_lite_response); + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_mtestAddress, + S_AXI_mtestProtection_lite, + S_AXI_rd_data_lite, + S_AXI_lite_response); + $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_rd_data_lite,S_AXI_lite_response); + CHECK_RESPONSE_OKAY(S_AXI_lite_response); + COMPARE_LITE_DATA(S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_rd_data_lite); + $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S_AXI_mtestvectorlite,S_AXI_mtestvectorlite); + S_AXI_mtestAddress = S_AXI_mtestAddress + 32'h00000004; + end + + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!"); + if ( result_slave_lite ) begin + $display("PTGEN_TEST: PASSED!"); + end else begin + $display("PTGEN_TEST: FAILED!"); + end + $display("---------------------------------------------------------"); + end + endtask + + // Create the test vectors + initial begin + // When performing debug enable all levels of INFO messages. + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1); + + // Create test data vectors + S_AXI_test_data_lite[0] = 32'h0101FFFF; + S_AXI_test_data_lite[1] = 32'habcd0001; + S_AXI_test_data_lite[2] = 32'hdead0011; + S_AXI_test_data_lite[3] = 32'hbeef0011; + end + + // Drive the BFM + initial begin + // Wait for end of reset + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + S_AXI_TEST(); + + end + +endmodule diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/bfm_design/design.tcl b/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/bfm_design/design.tcl new file mode 100644 index 0000000..019686e --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/bfm_design/design.tcl @@ -0,0 +1,91 @@ +proc create_ipi_design { offsetfile design_name } { + create_bd_design $design_name + open_bd_design $design_name + + # Create Clock and Reset Ports + set ACLK [ create_bd_port -dir I -type clk ACLK ] + set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK + set ARESETN [ create_bd_port -dir I -type rst ARESETN ] + set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN + set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK + + # Create instance: axi_reg32_0, and set properties + set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0] + + # Create instance: master_0, and set properties + set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0] + set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0 + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins axi_reg32_0/S_AXI] + + # Create port connections + connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins axi_reg32_0/S_AXI_ACLK] + connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins axi_reg32_0/S_AXI_ARESETN] + + # Auto assign address + assign_bd_address + + # Copy all address to interface_address.vh file + set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/axi_reg32_v1_0_tb_include.vh" + set fp [open $offset_file "w"] + puts $fp "`ifndef axi_reg32_v1_0_tb_include_vh_" + puts $fp "`define axi_reg32_v1_0_tb_include_vh_\n" + puts $fp "//Configuration current bd names" + puts $fp "`define BD_INST_NAME ${design_name}_i" + puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" + puts $fp "//Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]] + set offset_hex [string replace $offset 0 1 "32'h"] + puts $fp "`define S_AXI_SLAVE_ADDRESS ${offset_hex}" + + puts $fp "`endif" + close $fp +} + +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores trenz.biz:user:axi_reg32:1.0]]]] +set test_bench_file ${ip_path}/example_designs/bfm_design/axi_reg32_v1_0_tb.v +set interface_address_vh_file "" + +# Set IP Repository and Update IP Catalogue +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "axi_reg32_v1_0_bfm_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +create_ipi_design interface_address_vh_file ${design_name} +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +set_property SOURCE_SET sources_1 [get_filesets sim_1] +import_files -fileset sim_1 -norecurse -force $test_bench_file +remove_files -quiet -fileset sim_1 axi_reg32_v1_0_tb_include.vh +import_files -fileset sim_1 -norecurse -force $interface_address_vh_file +set_property top axi_reg32_v1_0_tb [get_filesets sim_1] +set_property top_lib {} [get_filesets sim_1] +set_property top_file {} [get_filesets sim_1] +launch_xsim -simset sim_1 -mode behavioral +restart +run 1000 us diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/axi_reg32_v1_0_hw_test.tcl b/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/axi_reg32_v1_0_hw_test.tcl new file mode 100644 index 0000000..2f63ccb --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/axi_reg32_v1_0_hw_test.tcl @@ -0,0 +1,45 @@ +# Runtime Tcl commands to interact with - axi_reg32_v1_0 + +# Sourcing design address info tcl +set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd +source ${bd_path}/axi_reg32_v1_0_include.tcl + +# jtag axi master interface hardware name, change as per your design. +set jtag_axi_master hw_axi_1 +set ec 0 + +# hw test script +# Delete all previous axis transactions +if { [llength [get_hw_axi_txns -quiet]] } { + delete_hw_axi_txn [get_hw_axi_txns -quiet] +} + + +# Test all lite slaves. +set wdata_1 abcd1234 + +# Test: S_AXI +# Create a write transaction at s_axi_addr address +create_hw_axi_txn w_s_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s_axi_addr -data $wdata_1 +# Create a read transaction at s_axi_addr address +create_hw_axi_txn r_s_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s_axi_addr +# Initiate transactions +run_hw_axi r_s_axi_addr +run_hw_axi w_s_axi_addr +run_hw_axi r_s_axi_addr +set rdata_tmp [get_property DATA [get_hw_axi_txn r_s_axi_addr]] +# Compare read data +if { $rdata_tmp == $wdata_1 } { + puts "Data comparison test pass for - S_AXI" +} else { + puts "Data comparison test fail for - S_AXI, expected-$wdata_1 actual-$rdata_tmp" + inc ec +} + +# Check error flag +if { $ec == 0 } { + puts "PTGEN_TEST: PASSED!" +} else { + puts "PTGEN_TEST: FAILED!" +} + diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/design.tcl b/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/design.tcl new file mode 100644 index 0000000..77acc83 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/design.tcl @@ -0,0 +1,175 @@ + +proc create_ipi_design { offsetfile design_name } { + + create_bd_design $design_name + open_bd_design $design_name + + # Create and configure Clock/Reset + create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 + create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 + + #check if current_board is set, if true - figure out required clocks. + set is_board_clock_found 0 + set is_board_reset_found 0 + set external_reset_port "" + set external_clock_port "" + + if { [current_board_part -quiet] != "" } { + + #check if any reset interface exists in board. + set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ] + if { $board_reset ne "" } { + set is_board_reset_found 1 + apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design] + apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design] + set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]] + if { $external_rst ne "" } { + set external_reset_port [get_property NAME $external_rst] + } + } else { + send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually." + } + + # check for differential clock, exclude any special clocks which has TYPE property. + set board_clock_busifs "" + foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] { + set type [get_property PARAM.TYPE $busif] + if { $type == "" } { + set board_clock_busifs $busif + break + } + } + if { $board_clock_busifs ne "" } { + apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design] + set is_board_clock_found 1 + } else { + # check for single ended clock + set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ] + if { $board_sclock_busifs ne "" } { + apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design] + set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]] + if { $external_clk ne "" } { + set external_clock_port [get_property NAME $external_clk] + } + set is_board_clock_found 1 + } else { + send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually." + } + } + + } else { + send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually." + } + + #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning. + if { $is_board_reset_found == 0 } { + create_bd_port -dir I -type rst reset_rtl + set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] + set external_reset_port reset_rtl + } + if { $is_board_clock_found == 0 } { + create_bd_port -dir I -type clk clock_rtl + connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] + set external_clock_port clock_rtl + } + + #Avoid IPI DRC, make clock port synchronous to reset + if { $external_clock_port ne "" && $external_reset_port ne "" } { + set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] + } + + # Connect other sys_reset pins + connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] + + # Create instance: axi_reg32_0, and set properties + set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0 ] + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] + set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] + connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Create instance: axi_peri_interconnect, and set properties + set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] + connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] + set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] + + set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Connect all clock & reset of axi_reg32_0 slave interfaces.. + connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins axi_reg32_0/S_AXI] + connect_bd_net [get_bd_pins axi_reg32_0/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_reg32_0/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + + # Auto assign address + assign_bd_address + + # Copy all address to axi_reg32_v1_0_include.tcl file + set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/axi_reg32_v1_0_include.tcl" + set fp [open $offset_file "w"] + puts $fp "# Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_reg32_0_S_AXI_* ]] + puts $fp "set s_axi_addr ${offset}" + + close $fp +} + +# Set IP Repository and Update IP Catalogue +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores trenz.biz:user:axi_reg32:1.0]]]] +set hw_test_file ${ip_path}/example_designs/debug_hw_design/axi_reg32_v1_0_hw_test.tcl + +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "axi_reg32_v1_0_hw_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +set intf_address_include_file "" +create_ipi_design intf_address_include_file ${design_name} +save_bd_design +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +puts "-------------------------------------------------------------------------------------------------" +puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " +puts " please perform following steps to test design in targeted board." +puts "1. Generate bitstream" +puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" +puts "3. Download generated bitstream" +puts "4. Run generated hardware test using below command, this invokes basic read/write operation" +puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" +puts " : source -notrace ${hw_test_file}" +puts "-------------------------------------------------------------------------------------------------" + diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0.vhd b/zynqberrydemo1/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0.vhd new file mode 100644 index 0000000..7cc74c8 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0.vhd @@ -0,0 +1,263 @@ +---------------------------------------------------------------------------------------------------- +--! @file axi_reg32_v1_0.vhd +--! @brief xxx +--! @author Antti Lukats +--! @version 1.0 +--! @date 2015 +--! @copyright Copyright 2015 Trenz Electronic GmbH +--! @license MIT License +--! @pre Vivado 2014.4+ +---------------------------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library axi_lib; + use axi_lib.all; + + +entity axi_reg32_v1_0 is + generic ( + -- Users to add parameters here + C_NUM_RO_REG : integer range 0 to 16 := 16; + C_NUM_WR_REG : integer range 0 to 16 := 16; + + C_WR_READABLE: boolean := true; + + C_RR0_ALIAS : string := "RR0"; + C_RR1_ALIAS : string := "RR1"; + C_RR2_ALIAS : string := "RR2"; + C_RR3_ALIAS : string := "RR3"; + + C_RR4_ALIAS : string := "RR4"; + C_RR5_ALIAS : string := "RR5"; + C_RR6_ALIAS : string := "RR6"; + C_RR7_ALIAS : string := "RR7"; + + C_RR8_ALIAS : string := "RR8"; + C_RR9_ALIAS : string := "RR9"; + C_RR10_ALIAS : string := "RR10"; + C_RR11_ALIAS : string := "RR11"; + + C_RR12_ALIAS : string := "RR12"; + C_RR13_ALIAS : string := "RR13"; + C_RR14_ALIAS : string := "RR14"; + C_RR15_ALIAS : string := "RR15"; + + -- + C_WR0_ALIAS : string := "WR0"; + C_WR1_ALIAS : string := "WR1"; + C_WR2_ALIAS : string := "WR2"; + C_WR3_ALIAS : string := "WR3"; + + C_WR4_ALIAS : string := "WR4"; + C_WR5_ALIAS : string := "WR5"; + C_WR6_ALIAS : string := "WR6"; + C_WR7_ALIAS : string := "WR7"; + + C_WR8_ALIAS : string := "WR8"; + C_WR9_ALIAS : string := "WR9"; + C_WR10_ALIAS : string := "WR10"; + C_WR11_ALIAS : string := "WR11"; + + C_WR12_ALIAS : string := "WR12"; + C_WR13_ALIAS : string := "WR13"; + C_WR14_ALIAS : string := "WR14"; + C_WR15_ALIAS : string := "WR15"; + + C_WR0_DEFAULT : integer := 0; + C_WR1_DEFAULT : integer := 0; + C_WR2_DEFAULT : integer := 0; + C_WR3_DEFAULT : integer := 0; + C_WR4_DEFAULT : integer := 0; + C_WR5_DEFAULT : integer := 0; + C_WR6_DEFAULT : integer := 0; + C_WR7_DEFAULT : integer := 0; + C_WR8_DEFAULT : integer := 0; + C_WR9_DEFAULT : integer := 0; + C_WR10_DEFAULT : integer := 0; + C_WR11_DEFAULT : integer := 0; + C_WR12_DEFAULT : integer := 0; + C_WR13_DEFAULT : integer := 0; + C_WR14_DEFAULT : integer := 0; + C_WR15_DEFAULT : integer := 0; + + + C_REG_WIDTH : integer range 8 to 32 := 32; + -- User parameters ends + -- Do not modify the parameters beyond this line + + + -- Parameters of Axi Slave Bus Interface S_AXI + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 7 + ); + port ( + -- Users to add ports here + + RR0 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR1 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR2 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR3 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR4 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR5 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR6 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR7 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR8 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR9 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR10 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR11 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR12 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR13 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR14 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR15 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR0 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR1 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR2 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR3 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR4 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR5 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR6 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR7 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR8 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR9 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR10 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR11 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR12 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR13 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR14 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR15 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + + -- User ports ends + -- Do not modify the ports beyond this line + + + -- Ports of Axi Slave Bus Interface S_AXI + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_awprot : in std_logic_vector(2 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_arprot : in std_logic_vector(2 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic + ); +end axi_reg32_v1_0; + +architecture arch_imp of axi_reg32_v1_0 is + +begin + +-- Instantiation of Axi Bus Interface S_AXI +axi_reg32_v1_0_S_AXI_inst : entity axi_lib.axi_reg32_v1_0_S_AXI + generic map ( + C_NUM_RO_REG => C_NUM_RO_REG, + C_NUM_WR_REG => C_NUM_WR_REG, + C_WR_READABLE => C_WR_READABLE, + + C_WR0_DEFAULT => C_WR0_DEFAULT, + C_WR1_DEFAULT => C_WR1_DEFAULT, + C_WR2_DEFAULT => C_WR2_DEFAULT, + C_WR3_DEFAULT => C_WR3_DEFAULT, + C_WR4_DEFAULT => C_WR4_DEFAULT, + C_WR5_DEFAULT => C_WR5_DEFAULT, + C_WR6_DEFAULT => C_WR6_DEFAULT, + C_WR7_DEFAULT => C_WR7_DEFAULT, + C_WR8_DEFAULT => C_WR8_DEFAULT, + C_WR9_DEFAULT => C_WR9_DEFAULT, + C_WR10_DEFAULT => C_WR10_DEFAULT, + C_WR11_DEFAULT => C_WR11_DEFAULT, + C_WR12_DEFAULT => C_WR12_DEFAULT, + C_WR13_DEFAULT => C_WR13_DEFAULT, + C_WR14_DEFAULT => C_WR14_DEFAULT, + C_WR15_DEFAULT => C_WR15_DEFAULT, + + C_REG_WIDTH => C_REG_WIDTH, + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH + ) + port map ( + RR0 => RR0, + RR1 => RR1, + RR2 => RR2, + RR3 => RR3, + RR4 => RR4, + RR5 => RR5, + RR6 => RR6, + RR7 => RR7, + RR8 => RR8, + RR9 => RR9, + RR10 => RR10, + RR11 => RR11, + RR12 => RR12, + RR13 => RR13, + RR14 => RR14, + RR15 => RR15, + + WR0 => WR0, + WR1 => WR1, + WR2 => WR2, + WR3 => WR3, + WR4 => WR4, + WR5 => WR5, + WR6 => WR6, + WR7 => WR7, + WR8 => WR8, + WR9 => WR9, + WR10 => WR10, + WR11 => WR11, + WR12 => WR12, + WR13 => WR13, + WR14 => WR14, + WR15 => WR15, + + S_AXI_ACLK => s_axi_aclk, + S_AXI_ARESETN => s_axi_aresetn, + S_AXI_AWADDR => s_axi_awaddr, + S_AXI_AWPROT => s_axi_awprot, + S_AXI_AWVALID => s_axi_awvalid, + S_AXI_AWREADY => s_axi_awready, + S_AXI_WDATA => s_axi_wdata, + S_AXI_WSTRB => s_axi_wstrb, + S_AXI_WVALID => s_axi_wvalid, + S_AXI_WREADY => s_axi_wready, + S_AXI_BRESP => s_axi_bresp, + S_AXI_BVALID => s_axi_bvalid, + S_AXI_BREADY => s_axi_bready, + S_AXI_ARADDR => s_axi_araddr, + S_AXI_ARPROT => s_axi_arprot, + S_AXI_ARVALID => s_axi_arvalid, + S_AXI_ARREADY => s_axi_arready, + S_AXI_RDATA => s_axi_rdata, + S_AXI_RRESP => s_axi_rresp, + S_AXI_RVALID => s_axi_rvalid, + S_AXI_RREADY => s_axi_rready + ); + + -- Add user logic here + + -- User logic ends + +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0_S_AXI.vhd b/zynqberrydemo1/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0_S_AXI.vhd new file mode 100644 index 0000000..670d6f0 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0_S_AXI.vhd @@ -0,0 +1,766 @@ +---------------------------------------------------------------------------------------------------- +--! @file axi_reg32_v1_0_S_AXI.vhd +--! @brief xxx +--! @author Antti Lukats +--! @version 1.0 +--! @date 2015 +--! @copyright Copyright 2015 Trenz Electronic GmbH +--! @license MIT License +--! @pre Vivado 2014.4+ +---------------------------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library axi_lib; + use axi_lib.all; + +entity axi_reg32_v1_0_S_AXI is + generic ( + -- Users to add parameters here + C_NUM_RO_REG : integer range 0 to 16 := 2; + C_NUM_WR_REG : integer range 0 to 16 := 2; + C_WR_READABLE: boolean := true; + + + C_WR0_DEFAULT : integer := 0; + C_WR1_DEFAULT : integer := 0; + C_WR2_DEFAULT : integer := 0; + C_WR3_DEFAULT : integer := 0; + C_WR4_DEFAULT : integer := 0; + C_WR5_DEFAULT : integer := 0; + C_WR6_DEFAULT : integer := 0; + C_WR7_DEFAULT : integer := 0; + C_WR8_DEFAULT : integer := 0; + C_WR9_DEFAULT : integer := 0; + C_WR10_DEFAULT : integer := 0; + C_WR11_DEFAULT : integer := 0; + C_WR12_DEFAULT : integer := 0; + C_WR13_DEFAULT : integer := 0; + C_WR14_DEFAULT : integer := 0; + C_WR15_DEFAULT : integer := 0; + + C_REG_WIDTH : integer range 8 to 32 := 32; + -- User parameters ends + -- Do not modify the parameters beyond this line + + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 7 + ); + port ( + -- Users to add ports here + + RR0 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR1 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR2 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR3 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR4 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR5 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR6 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR7 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR8 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR9 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR10 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR11 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR12 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR13 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR14 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR15 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR0 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR1 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR2 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR3 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR4 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR5 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR6 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR7 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR8 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR9 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR10 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR11 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR12 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR13 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR14 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR15 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + + -- User ports ends + -- Do not modify the ports beyond this line + + -- Global Clock Signal + S_AXI_ACLK : in std_logic; + -- Global Reset Signal. This Signal is Active LOW + S_AXI_ARESETN : in std_logic; + -- Write address (issued by master, acceped by Slave) + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Write channel Protection type. This signal indicates the + -- privilege and security level of the transaction, and whether + -- the transaction is a data access or an instruction access. + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + -- Write address valid. This signal indicates that the master signaling + -- valid write address and control information. + S_AXI_AWVALID : in std_logic; + -- Write address ready. This signal indicates that the slave is ready + -- to accept an address and associated control signals. + S_AXI_AWREADY : out std_logic; + -- Write data (issued by master, acceped by Slave) + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Write strobes. This signal indicates which byte lanes hold + -- valid data. There is one write strobe bit for each eight + -- bits of the write data bus. + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + -- Write valid. This signal indicates that valid write + -- data and strobes are available. + S_AXI_WVALID : in std_logic; + -- Write ready. This signal indicates that the slave + -- can accept the write data. + S_AXI_WREADY : out std_logic; + -- Write response. This signal indicates the status + -- of the write transaction. + S_AXI_BRESP : out std_logic_vector(1 downto 0); + -- Write response valid. This signal indicates that the channel + -- is signaling a valid write response. + S_AXI_BVALID : out std_logic; + -- Response ready. This signal indicates that the master + -- can accept a write response. + S_AXI_BREADY : in std_logic; + -- Read address (issued by master, acceped by Slave) + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Protection type. This signal indicates the privilege + -- and security level of the transaction, and whether the + -- transaction is a data access or an instruction access. + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + -- Read address valid. This signal indicates that the channel + -- is signaling valid read address and control information. + S_AXI_ARVALID : in std_logic; + -- Read address ready. This signal indicates that the slave is + -- ready to accept an address and associated control signals. + S_AXI_ARREADY : out std_logic; + -- Read data (issued by slave) + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Read response. This signal indicates the status of the + -- read transfer. + S_AXI_RRESP : out std_logic_vector(1 downto 0); + -- Read valid. This signal indicates that the channel is + -- signaling the required read data. + S_AXI_RVALID : out std_logic; + -- Read ready. This signal indicates that the master can + -- accept the read data and response information. + S_AXI_RREADY : in std_logic + ); +end axi_reg32_v1_0_S_AXI; + +architecture arch_imp of axi_reg32_v1_0_S_AXI is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 4; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 32 + signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + + signal slv_reg16r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg17r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg18r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg19r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg20r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg21r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg22r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg23r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg24r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg25r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg26r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg27r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg28r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg29r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg30r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg31r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal byte_index : integer; + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + process (S_AXI_ACLK) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + slv_reg16 <= STD_LOGIC_VECTOR(to_unsigned(C_WR0_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg17 <= STD_LOGIC_VECTOR(to_unsigned(C_WR1_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg18 <= STD_LOGIC_VECTOR(to_unsigned(C_WR2_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg19 <= STD_LOGIC_VECTOR(to_unsigned(C_WR3_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg20 <= STD_LOGIC_VECTOR(to_unsigned(C_WR4_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg21 <= STD_LOGIC_VECTOR(to_unsigned(C_WR5_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg22 <= STD_LOGIC_VECTOR(to_unsigned(C_WR6_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg23 <= STD_LOGIC_VECTOR(to_unsigned(C_WR7_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg24 <= STD_LOGIC_VECTOR(to_unsigned(C_WR8_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg25 <= STD_LOGIC_VECTOR(to_unsigned(C_WR9_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg26 <= STD_LOGIC_VECTOR(to_unsigned(C_WR10_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg27 <= STD_LOGIC_VECTOR(to_unsigned(C_WR11_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg28 <= STD_LOGIC_VECTOR(to_unsigned(C_WR12_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg29 <= STD_LOGIC_VECTOR(to_unsigned(C_WR13_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg30 <= STD_LOGIC_VECTOR(to_unsigned(C_WR14_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg31 <= STD_LOGIC_VECTOR(to_unsigned(C_WR15_DEFAULT,C_S_AXI_DATA_WIDTH)); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"10000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 16 + slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 17 + slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 18 + slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 19 + slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 20 + slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 21 + slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 22 + slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 23 + slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 24 + slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 25 + slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 26 + slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 27 + slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 28 + slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 29 + slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 30 + slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 31 + slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16r, slv_reg17r, slv_reg18r, slv_reg19r, slv_reg20r, slv_reg21r, slv_reg22r, slv_reg23r, slv_reg24r, slv_reg25r, slv_reg26r, slv_reg27r, slv_reg28r, slv_reg29r, slv_reg30r, slv_reg31r, axi_araddr, S_AXI_ARESETN, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"00000" => + reg_data_out <= slv_reg0; + when b"00001" => + reg_data_out <= slv_reg1; + when b"00010" => + reg_data_out <= slv_reg2; + when b"00011" => + reg_data_out <= slv_reg3; + when b"00100" => + reg_data_out <= slv_reg4; + when b"00101" => + reg_data_out <= slv_reg5; + when b"00110" => + reg_data_out <= slv_reg6; + when b"00111" => + reg_data_out <= slv_reg7; + when b"01000" => + reg_data_out <= slv_reg8; + when b"01001" => + reg_data_out <= slv_reg9; + when b"01010" => + reg_data_out <= slv_reg10; + when b"01011" => + reg_data_out <= slv_reg11; + when b"01100" => + reg_data_out <= slv_reg12; + when b"01101" => + reg_data_out <= slv_reg13; + when b"01110" => + reg_data_out <= slv_reg14; + when b"01111" => + reg_data_out <= slv_reg15; + + when b"10000" => + reg_data_out <= slv_reg16r; + when b"10001" => + reg_data_out <= slv_reg17r; + when b"10010" => + reg_data_out <= slv_reg18r; + when b"10011" => + reg_data_out <= slv_reg19r; + when b"10100" => + reg_data_out <= slv_reg20r; + when b"10101" => + reg_data_out <= slv_reg21r; + when b"10110" => + reg_data_out <= slv_reg22r; + when b"10111" => + reg_data_out <= slv_reg23r; + when b"11000" => + reg_data_out <= slv_reg24r; + when b"11001" => + reg_data_out <= slv_reg25r; + when b"11010" => + reg_data_out <= slv_reg26r; + when b"11011" => + reg_data_out <= slv_reg27r; + when b"11100" => + reg_data_out <= slv_reg28r; + when b"11101" => + reg_data_out <= slv_reg29r; + when b"11110" => + reg_data_out <= slv_reg30r; + when b"11111" => + reg_data_out <= slv_reg31r; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + + slv_reg0 <= RR0; + slv_reg1 <= RR1; + slv_reg2 <= RR2; + slv_reg3 <= RR3; + slv_reg4 <= RR4; + slv_reg5 <= RR5; + slv_reg6 <= RR6; + slv_reg7 <= RR7; + slv_reg8 <= RR8; + slv_reg9 <= RR9; + slv_reg10 <= RR10; + slv_reg11 <= RR11; + slv_reg12 <= RR12; + slv_reg13 <= RR13; + slv_reg14 <= RR14; + slv_reg15 <= RR15; + + WR0 <= slv_reg16; + WR1 <= slv_reg17; + WR2 <= slv_reg18; + WR3 <= slv_reg19; + WR4 <= slv_reg20; + WR5 <= slv_reg21; + WR6 <= slv_reg22; + WR7 <= slv_reg23; + WR8 <= slv_reg24; + WR9 <= slv_reg25; + WR10 <= slv_reg26; + WR11 <= slv_reg27; + WR12 <= slv_reg28; + WR13 <= slv_reg29; + WR14 <= slv_reg30; + WR15 <= slv_reg31; + + +WR_readable_Gen: if C_WR_READABLE = true generate + slv_reg16r <= slv_reg16; +WR17_Gen: if C_NUM_WR_REG > 1 generate + slv_reg17r <= slv_reg17; +end generate; +WR18_Gen: if C_NUM_WR_REG > 2 generate + slv_reg18r <= slv_reg18; +end generate; +WR19_Gen: if C_NUM_WR_REG > 3 generate + slv_reg19r <= slv_reg19; +end generate; +WR20_Gen: if C_NUM_WR_REG > 4 generate + slv_reg20r <= slv_reg20; +end generate; +WR21_Gen: if C_NUM_WR_REG > 5 generate + slv_reg21r <= slv_reg21; +end generate; +WR22_Gen: if C_NUM_WR_REG > 6 generate + slv_reg22r <= slv_reg22; +end generate; +WR23_Gen: if C_NUM_WR_REG > 7 generate + slv_reg23r <= slv_reg23; +end generate; +WR24_Gen: if C_NUM_WR_REG > 8 generate + slv_reg24r <= slv_reg24; +end generate; +WR25_Gen: if C_NUM_WR_REG > 9 generate + slv_reg25r <= slv_reg25; +end generate; +WR26_Gen: if C_NUM_WR_REG > 10 generate + slv_reg26r <= slv_reg26; +end generate; +WR27_Gen: if C_NUM_WR_REG > 11 generate + slv_reg27r <= slv_reg27; +end generate; +WR28_Gen: if C_NUM_WR_REG > 12 generate + slv_reg28r <= slv_reg28; +end generate; +WR29_Gen: if C_NUM_WR_REG > 13 generate + slv_reg29r <= slv_reg29; +end generate; +WR30_Gen: if C_NUM_WR_REG > 14 generate + slv_reg30r <= slv_reg30; +end generate; +WR31_Gen: if C_NUM_WR_REG > 15 generate + slv_reg31r <= slv_reg31; +end generate; + +end generate WR_readable_Gen; + +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axi_reg32_1.0/xgui/axi_reg32_v1_0.tcl b/zynqberrydemo1/ip_lib/axi_reg32_1.0/xgui/axi_reg32_v1_0.tcl new file mode 100644 index 0000000..631cdd0 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axi_reg32_1.0/xgui/axi_reg32_v1_0.tcl @@ -0,0 +1,853 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/axi_reg32_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0" -display_name {AXI}] + ipgui::add_param $IPINST -name "C_S_AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S_AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S_AXI_BASEADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S_AXI_HIGHADDR" -parent ${Page_0} + + #Adding Page + set Read_Registers [ipgui::add_page $IPINST -name "Read Registers" -display_name {Input Registers}] + ipgui::add_param $IPINST -name "C_NUM_RO_REG" -parent ${Read_Registers} -widget comboBox + #Adding Group + set Input_Registe_Alias [ipgui::add_group $IPINST -name "Input Registe Alias" -parent ${Read_Registers} -display_name {Input Register Alias}] + ipgui::add_param $IPINST -name "C_RR0_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR1_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR2_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR3_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR4_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR5_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR6_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR7_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR8_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR9_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR10_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR11_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR12_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR13_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR14_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR15_ALIAS" -parent ${Input_Registe_Alias} + + + #Adding Page + set Output_Registers [ipgui::add_page $IPINST -name "Output Registers"] + ipgui::add_param $IPINST -name "C_WR_READABLE" -parent ${Output_Registers} + ipgui::add_param $IPINST -name "C_NUM_WR_REG" -parent ${Output_Registers} -widget comboBox + #Adding Group + set Registers [ipgui::add_group $IPINST -name "Registers" -parent ${Output_Registers} -layout horizontal] + #Adding Group + set Register_Aliases [ipgui::add_group $IPINST -name "Register Aliases" -parent ${Registers} -display_name {Aliases}] + ipgui::add_param $IPINST -name "C_WR0_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR1_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR2_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR3_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR4_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR5_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR6_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR7_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR8_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR9_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR10_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR11_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR12_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR13_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR14_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR15_ALIAS" -parent ${Register_Aliases} + + #Adding Group + set Default [ipgui::add_group $IPINST -name "Default" -parent ${Registers}] + ipgui::add_param $IPINST -name "C_WR0_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR1_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR2_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR3_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR4_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR5_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR6_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR7_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR8_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR9_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR10_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR11_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR12_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR13_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR14_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR15_DEFAULT" -parent ${Default} + + + + +} + +proc update_PARAM_VALUE.C_NUM_RO_REG { PARAM_VALUE.C_NUM_RO_REG } { + # Procedure called to update C_NUM_RO_REG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_NUM_RO_REG { PARAM_VALUE.C_NUM_RO_REG } { + # Procedure called to validate C_NUM_RO_REG + return true +} + +proc update_PARAM_VALUE.C_NUM_WR_REG { PARAM_VALUE.C_NUM_WR_REG } { + # Procedure called to update C_NUM_WR_REG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_NUM_WR_REG { PARAM_VALUE.C_NUM_WR_REG } { + # Procedure called to validate C_NUM_WR_REG + return true +} + +proc update_PARAM_VALUE.C_RR0_ALIAS { PARAM_VALUE.C_RR0_ALIAS } { + # Procedure called to update C_RR0_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR0_ALIAS { PARAM_VALUE.C_RR0_ALIAS } { + # Procedure called to validate C_RR0_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR10_ALIAS { PARAM_VALUE.C_RR10_ALIAS } { + # Procedure called to update C_RR10_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR10_ALIAS { PARAM_VALUE.C_RR10_ALIAS } { + # Procedure called to validate C_RR10_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR11_ALIAS { PARAM_VALUE.C_RR11_ALIAS } { + # Procedure called to update C_RR11_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR11_ALIAS { PARAM_VALUE.C_RR11_ALIAS } { + # Procedure called to validate C_RR11_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR12_ALIAS { PARAM_VALUE.C_RR12_ALIAS } { + # Procedure called to update C_RR12_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR12_ALIAS { PARAM_VALUE.C_RR12_ALIAS } { + # Procedure called to validate C_RR12_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR13_ALIAS { PARAM_VALUE.C_RR13_ALIAS } { + # Procedure called to update C_RR13_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR13_ALIAS { PARAM_VALUE.C_RR13_ALIAS } { + # Procedure called to validate C_RR13_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR14_ALIAS { PARAM_VALUE.C_RR14_ALIAS } { + # Procedure called to update C_RR14_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR14_ALIAS { PARAM_VALUE.C_RR14_ALIAS } { + # Procedure called to validate C_RR14_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR15_ALIAS { PARAM_VALUE.C_RR15_ALIAS } { + # Procedure called to update C_RR15_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR15_ALIAS { PARAM_VALUE.C_RR15_ALIAS } { + # Procedure called to validate C_RR15_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR1_ALIAS { PARAM_VALUE.C_RR1_ALIAS } { + # Procedure called to update C_RR1_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR1_ALIAS { PARAM_VALUE.C_RR1_ALIAS } { + # Procedure called to validate C_RR1_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR2_ALIAS { PARAM_VALUE.C_RR2_ALIAS } { + # Procedure called to update C_RR2_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR2_ALIAS { PARAM_VALUE.C_RR2_ALIAS } { + # Procedure called to validate C_RR2_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR3_ALIAS { PARAM_VALUE.C_RR3_ALIAS } { + # Procedure called to update C_RR3_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR3_ALIAS { PARAM_VALUE.C_RR3_ALIAS } { + # Procedure called to validate C_RR3_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR4_ALIAS { PARAM_VALUE.C_RR4_ALIAS } { + # Procedure called to update C_RR4_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR4_ALIAS { PARAM_VALUE.C_RR4_ALIAS } { + # Procedure called to validate C_RR4_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR5_ALIAS { PARAM_VALUE.C_RR5_ALIAS } { + # Procedure called to update C_RR5_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR5_ALIAS { PARAM_VALUE.C_RR5_ALIAS } { + # Procedure called to validate C_RR5_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR6_ALIAS { PARAM_VALUE.C_RR6_ALIAS } { + # Procedure called to update C_RR6_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR6_ALIAS { PARAM_VALUE.C_RR6_ALIAS } { + # Procedure called to validate C_RR6_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR7_ALIAS { PARAM_VALUE.C_RR7_ALIAS } { + # Procedure called to update C_RR7_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR7_ALIAS { PARAM_VALUE.C_RR7_ALIAS } { + # Procedure called to validate C_RR7_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR8_ALIAS { PARAM_VALUE.C_RR8_ALIAS } { + # Procedure called to update C_RR8_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR8_ALIAS { PARAM_VALUE.C_RR8_ALIAS } { + # Procedure called to validate C_RR8_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR9_ALIAS { PARAM_VALUE.C_RR9_ALIAS } { + # Procedure called to update C_RR9_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR9_ALIAS { PARAM_VALUE.C_RR9_ALIAS } { + # Procedure called to validate C_RR9_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR0_ALIAS { PARAM_VALUE.C_WR0_ALIAS } { + # Procedure called to update C_WR0_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR0_ALIAS { PARAM_VALUE.C_WR0_ALIAS } { + # Procedure called to validate C_WR0_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR0_DEFAULT { PARAM_VALUE.C_WR0_DEFAULT } { + # Procedure called to update C_WR0_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR0_DEFAULT { PARAM_VALUE.C_WR0_DEFAULT } { + # Procedure called to validate C_WR0_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR10_ALIAS { PARAM_VALUE.C_WR10_ALIAS } { + # Procedure called to update C_WR10_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR10_ALIAS { PARAM_VALUE.C_WR10_ALIAS } { + # Procedure called to validate C_WR10_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR10_DEFAULT { PARAM_VALUE.C_WR10_DEFAULT } { + # Procedure called to update C_WR10_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR10_DEFAULT { PARAM_VALUE.C_WR10_DEFAULT } { + # Procedure called to validate C_WR10_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR11_ALIAS { PARAM_VALUE.C_WR11_ALIAS } { + # Procedure called to update C_WR11_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR11_ALIAS { PARAM_VALUE.C_WR11_ALIAS } { + # Procedure called to validate C_WR11_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR11_DEFAULT { PARAM_VALUE.C_WR11_DEFAULT } { + # Procedure called to update C_WR11_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR11_DEFAULT { PARAM_VALUE.C_WR11_DEFAULT } { + # Procedure called to validate C_WR11_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR12_ALIAS { PARAM_VALUE.C_WR12_ALIAS } { + # Procedure called to update C_WR12_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR12_ALIAS { PARAM_VALUE.C_WR12_ALIAS } { + # Procedure called to validate C_WR12_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR12_DEFAULT { PARAM_VALUE.C_WR12_DEFAULT } { + # Procedure called to update C_WR12_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR12_DEFAULT { PARAM_VALUE.C_WR12_DEFAULT } { + # Procedure called to validate C_WR12_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR13_ALIAS { PARAM_VALUE.C_WR13_ALIAS } { + # Procedure called to update C_WR13_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR13_ALIAS { PARAM_VALUE.C_WR13_ALIAS } { + # Procedure called to validate C_WR13_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR13_DEFAULT { PARAM_VALUE.C_WR13_DEFAULT } { + # Procedure called to update C_WR13_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR13_DEFAULT { PARAM_VALUE.C_WR13_DEFAULT } { + # Procedure called to validate C_WR13_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR14_ALIAS { PARAM_VALUE.C_WR14_ALIAS } { + # Procedure called to update C_WR14_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR14_ALIAS { PARAM_VALUE.C_WR14_ALIAS } { + # Procedure called to validate C_WR14_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR14_DEFAULT { PARAM_VALUE.C_WR14_DEFAULT } { + # Procedure called to update C_WR14_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR14_DEFAULT { PARAM_VALUE.C_WR14_DEFAULT } { + # Procedure called to validate C_WR14_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR15_ALIAS { PARAM_VALUE.C_WR15_ALIAS } { + # Procedure called to update C_WR15_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR15_ALIAS { PARAM_VALUE.C_WR15_ALIAS } { + # Procedure called to validate C_WR15_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR15_DEFAULT { PARAM_VALUE.C_WR15_DEFAULT } { + # Procedure called to update C_WR15_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR15_DEFAULT { PARAM_VALUE.C_WR15_DEFAULT } { + # Procedure called to validate C_WR15_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR1_ALIAS { PARAM_VALUE.C_WR1_ALIAS } { + # Procedure called to update C_WR1_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR1_ALIAS { PARAM_VALUE.C_WR1_ALIAS } { + # Procedure called to validate C_WR1_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR1_DEFAULT { PARAM_VALUE.C_WR1_DEFAULT } { + # Procedure called to update C_WR1_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR1_DEFAULT { PARAM_VALUE.C_WR1_DEFAULT } { + # Procedure called to validate C_WR1_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR2_ALIAS { PARAM_VALUE.C_WR2_ALIAS } { + # Procedure called to update C_WR2_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR2_ALIAS { PARAM_VALUE.C_WR2_ALIAS } { + # Procedure called to validate C_WR2_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR2_DEFAULT { PARAM_VALUE.C_WR2_DEFAULT } { + # Procedure called to update C_WR2_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR2_DEFAULT { PARAM_VALUE.C_WR2_DEFAULT } { + # Procedure called to validate C_WR2_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR3_ALIAS { PARAM_VALUE.C_WR3_ALIAS } { + # Procedure called to update C_WR3_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR3_ALIAS { PARAM_VALUE.C_WR3_ALIAS } { + # Procedure called to validate C_WR3_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR3_DEFAULT { PARAM_VALUE.C_WR3_DEFAULT } { + # Procedure called to update C_WR3_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR3_DEFAULT { PARAM_VALUE.C_WR3_DEFAULT } { + # Procedure called to validate C_WR3_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR4_ALIAS { PARAM_VALUE.C_WR4_ALIAS } { + # Procedure called to update C_WR4_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR4_ALIAS { PARAM_VALUE.C_WR4_ALIAS } { + # Procedure called to validate C_WR4_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR4_DEFAULT { PARAM_VALUE.C_WR4_DEFAULT } { + # Procedure called to update C_WR4_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR4_DEFAULT { PARAM_VALUE.C_WR4_DEFAULT } { + # Procedure called to validate C_WR4_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR5_ALIAS { PARAM_VALUE.C_WR5_ALIAS } { + # Procedure called to update C_WR5_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR5_ALIAS { PARAM_VALUE.C_WR5_ALIAS } { + # Procedure called to validate C_WR5_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR5_DEFAULT { PARAM_VALUE.C_WR5_DEFAULT } { + # Procedure called to update C_WR5_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR5_DEFAULT { PARAM_VALUE.C_WR5_DEFAULT } { + # Procedure called to validate C_WR5_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR6_ALIAS { PARAM_VALUE.C_WR6_ALIAS } { + # Procedure called to update C_WR6_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR6_ALIAS { PARAM_VALUE.C_WR6_ALIAS } { + # Procedure called to validate C_WR6_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR6_DEFAULT { PARAM_VALUE.C_WR6_DEFAULT } { + # Procedure called to update C_WR6_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR6_DEFAULT { PARAM_VALUE.C_WR6_DEFAULT } { + # Procedure called to validate C_WR6_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR7_ALIAS { PARAM_VALUE.C_WR7_ALIAS } { + # Procedure called to update C_WR7_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR7_ALIAS { PARAM_VALUE.C_WR7_ALIAS } { + # Procedure called to validate C_WR7_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR7_DEFAULT { PARAM_VALUE.C_WR7_DEFAULT } { + # Procedure called to update C_WR7_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR7_DEFAULT { PARAM_VALUE.C_WR7_DEFAULT } { + # Procedure called to validate C_WR7_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR8_ALIAS { PARAM_VALUE.C_WR8_ALIAS } { + # Procedure called to update C_WR8_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR8_ALIAS { PARAM_VALUE.C_WR8_ALIAS } { + # Procedure called to validate C_WR8_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR8_DEFAULT { PARAM_VALUE.C_WR8_DEFAULT } { + # Procedure called to update C_WR8_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR8_DEFAULT { PARAM_VALUE.C_WR8_DEFAULT } { + # Procedure called to validate C_WR8_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR9_ALIAS { PARAM_VALUE.C_WR9_ALIAS } { + # Procedure called to update C_WR9_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR9_ALIAS { PARAM_VALUE.C_WR9_ALIAS } { + # Procedure called to validate C_WR9_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR9_DEFAULT { PARAM_VALUE.C_WR9_DEFAULT } { + # Procedure called to update C_WR9_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR9_DEFAULT { PARAM_VALUE.C_WR9_DEFAULT } { + # Procedure called to validate C_WR9_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR_READABLE { PARAM_VALUE.C_WR_READABLE } { + # Procedure called to update C_WR_READABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR_READABLE { PARAM_VALUE.C_WR_READABLE } { + # Procedure called to validate C_WR_READABLE + return true +} + +proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to validate C_S_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S_AXI_BASEADDR { PARAM_VALUE.C_S_AXI_BASEADDR } { + # Procedure called to update C_S_AXI_BASEADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_BASEADDR { PARAM_VALUE.C_S_AXI_BASEADDR } { + # Procedure called to validate C_S_AXI_BASEADDR + return true +} + +proc update_PARAM_VALUE.C_S_AXI_HIGHADDR { PARAM_VALUE.C_S_AXI_HIGHADDR } { + # Procedure called to update C_S_AXI_HIGHADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_HIGHADDR { PARAM_VALUE.C_S_AXI_HIGHADDR } { + # Procedure called to validate C_S_AXI_HIGHADDR + return true +} + + +proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_REG_WIDTH { MODELPARAM_VALUE.C_REG_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + # WARNING: There is no corresponding user parameter named "C_REG_WIDTH". Setting updated value from the model parameter. +set_property value 32 ${MODELPARAM_VALUE.C_REG_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_NUM_RO_REG { MODELPARAM_VALUE.C_NUM_RO_REG PARAM_VALUE.C_NUM_RO_REG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_NUM_RO_REG}] ${MODELPARAM_VALUE.C_NUM_RO_REG} +} + +proc update_MODELPARAM_VALUE.C_NUM_WR_REG { MODELPARAM_VALUE.C_NUM_WR_REG PARAM_VALUE.C_NUM_WR_REG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_NUM_WR_REG}] ${MODELPARAM_VALUE.C_NUM_WR_REG} +} + +proc update_MODELPARAM_VALUE.C_WR_READABLE { MODELPARAM_VALUE.C_WR_READABLE PARAM_VALUE.C_WR_READABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR_READABLE}] ${MODELPARAM_VALUE.C_WR_READABLE} +} + +proc update_MODELPARAM_VALUE.C_RR0_ALIAS { MODELPARAM_VALUE.C_RR0_ALIAS PARAM_VALUE.C_RR0_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR0_ALIAS}] ${MODELPARAM_VALUE.C_RR0_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR1_ALIAS { MODELPARAM_VALUE.C_RR1_ALIAS PARAM_VALUE.C_RR1_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR1_ALIAS}] ${MODELPARAM_VALUE.C_RR1_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR0_ALIAS { MODELPARAM_VALUE.C_WR0_ALIAS PARAM_VALUE.C_WR0_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR0_ALIAS}] ${MODELPARAM_VALUE.C_WR0_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR1_ALIAS { MODELPARAM_VALUE.C_WR1_ALIAS PARAM_VALUE.C_WR1_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR1_ALIAS}] ${MODELPARAM_VALUE.C_WR1_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR2_ALIAS { MODELPARAM_VALUE.C_RR2_ALIAS PARAM_VALUE.C_RR2_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR2_ALIAS}] ${MODELPARAM_VALUE.C_RR2_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR3_ALIAS { MODELPARAM_VALUE.C_RR3_ALIAS PARAM_VALUE.C_RR3_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR3_ALIAS}] ${MODELPARAM_VALUE.C_RR3_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR4_ALIAS { MODELPARAM_VALUE.C_RR4_ALIAS PARAM_VALUE.C_RR4_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR4_ALIAS}] ${MODELPARAM_VALUE.C_RR4_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR5_ALIAS { MODELPARAM_VALUE.C_RR5_ALIAS PARAM_VALUE.C_RR5_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR5_ALIAS}] ${MODELPARAM_VALUE.C_RR5_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR6_ALIAS { MODELPARAM_VALUE.C_RR6_ALIAS PARAM_VALUE.C_RR6_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR6_ALIAS}] ${MODELPARAM_VALUE.C_RR6_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR7_ALIAS { MODELPARAM_VALUE.C_RR7_ALIAS PARAM_VALUE.C_RR7_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR7_ALIAS}] ${MODELPARAM_VALUE.C_RR7_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR8_ALIAS { MODELPARAM_VALUE.C_RR8_ALIAS PARAM_VALUE.C_RR8_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR8_ALIAS}] ${MODELPARAM_VALUE.C_RR8_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR9_ALIAS { MODELPARAM_VALUE.C_RR9_ALIAS PARAM_VALUE.C_RR9_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR9_ALIAS}] ${MODELPARAM_VALUE.C_RR9_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR10_ALIAS { MODELPARAM_VALUE.C_RR10_ALIAS PARAM_VALUE.C_RR10_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR10_ALIAS}] ${MODELPARAM_VALUE.C_RR10_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR11_ALIAS { MODELPARAM_VALUE.C_RR11_ALIAS PARAM_VALUE.C_RR11_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR11_ALIAS}] ${MODELPARAM_VALUE.C_RR11_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR12_ALIAS { MODELPARAM_VALUE.C_RR12_ALIAS PARAM_VALUE.C_RR12_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR12_ALIAS}] ${MODELPARAM_VALUE.C_RR12_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR13_ALIAS { MODELPARAM_VALUE.C_RR13_ALIAS PARAM_VALUE.C_RR13_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR13_ALIAS}] ${MODELPARAM_VALUE.C_RR13_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR14_ALIAS { MODELPARAM_VALUE.C_RR14_ALIAS PARAM_VALUE.C_RR14_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR14_ALIAS}] ${MODELPARAM_VALUE.C_RR14_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR15_ALIAS { MODELPARAM_VALUE.C_RR15_ALIAS PARAM_VALUE.C_RR15_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR15_ALIAS}] ${MODELPARAM_VALUE.C_RR15_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR2_ALIAS { MODELPARAM_VALUE.C_WR2_ALIAS PARAM_VALUE.C_WR2_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR2_ALIAS}] ${MODELPARAM_VALUE.C_WR2_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR3_ALIAS { MODELPARAM_VALUE.C_WR3_ALIAS PARAM_VALUE.C_WR3_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR3_ALIAS}] ${MODELPARAM_VALUE.C_WR3_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR4_ALIAS { MODELPARAM_VALUE.C_WR4_ALIAS PARAM_VALUE.C_WR4_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR4_ALIAS}] ${MODELPARAM_VALUE.C_WR4_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR5_ALIAS { MODELPARAM_VALUE.C_WR5_ALIAS PARAM_VALUE.C_WR5_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR5_ALIAS}] ${MODELPARAM_VALUE.C_WR5_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR6_ALIAS { MODELPARAM_VALUE.C_WR6_ALIAS PARAM_VALUE.C_WR6_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR6_ALIAS}] ${MODELPARAM_VALUE.C_WR6_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR7_ALIAS { MODELPARAM_VALUE.C_WR7_ALIAS PARAM_VALUE.C_WR7_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR7_ALIAS}] ${MODELPARAM_VALUE.C_WR7_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR8_ALIAS { MODELPARAM_VALUE.C_WR8_ALIAS PARAM_VALUE.C_WR8_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR8_ALIAS}] ${MODELPARAM_VALUE.C_WR8_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR9_ALIAS { MODELPARAM_VALUE.C_WR9_ALIAS PARAM_VALUE.C_WR9_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR9_ALIAS}] ${MODELPARAM_VALUE.C_WR9_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR10_ALIAS { MODELPARAM_VALUE.C_WR10_ALIAS PARAM_VALUE.C_WR10_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR10_ALIAS}] ${MODELPARAM_VALUE.C_WR10_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR11_ALIAS { MODELPARAM_VALUE.C_WR11_ALIAS PARAM_VALUE.C_WR11_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR11_ALIAS}] ${MODELPARAM_VALUE.C_WR11_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR12_ALIAS { MODELPARAM_VALUE.C_WR12_ALIAS PARAM_VALUE.C_WR12_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR12_ALIAS}] ${MODELPARAM_VALUE.C_WR12_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR13_ALIAS { MODELPARAM_VALUE.C_WR13_ALIAS PARAM_VALUE.C_WR13_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR13_ALIAS}] ${MODELPARAM_VALUE.C_WR13_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR14_ALIAS { MODELPARAM_VALUE.C_WR14_ALIAS PARAM_VALUE.C_WR14_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR14_ALIAS}] ${MODELPARAM_VALUE.C_WR14_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR15_ALIAS { MODELPARAM_VALUE.C_WR15_ALIAS PARAM_VALUE.C_WR15_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR15_ALIAS}] ${MODELPARAM_VALUE.C_WR15_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR0_DEFAULT { MODELPARAM_VALUE.C_WR0_DEFAULT PARAM_VALUE.C_WR0_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR0_DEFAULT}] ${MODELPARAM_VALUE.C_WR0_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR1_DEFAULT { MODELPARAM_VALUE.C_WR1_DEFAULT PARAM_VALUE.C_WR1_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR1_DEFAULT}] ${MODELPARAM_VALUE.C_WR1_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR2_DEFAULT { MODELPARAM_VALUE.C_WR2_DEFAULT PARAM_VALUE.C_WR2_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR2_DEFAULT}] ${MODELPARAM_VALUE.C_WR2_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR3_DEFAULT { MODELPARAM_VALUE.C_WR3_DEFAULT PARAM_VALUE.C_WR3_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR3_DEFAULT}] ${MODELPARAM_VALUE.C_WR3_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR4_DEFAULT { MODELPARAM_VALUE.C_WR4_DEFAULT PARAM_VALUE.C_WR4_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR4_DEFAULT}] ${MODELPARAM_VALUE.C_WR4_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR5_DEFAULT { MODELPARAM_VALUE.C_WR5_DEFAULT PARAM_VALUE.C_WR5_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR5_DEFAULT}] ${MODELPARAM_VALUE.C_WR5_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR6_DEFAULT { MODELPARAM_VALUE.C_WR6_DEFAULT PARAM_VALUE.C_WR6_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR6_DEFAULT}] ${MODELPARAM_VALUE.C_WR6_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR7_DEFAULT { MODELPARAM_VALUE.C_WR7_DEFAULT PARAM_VALUE.C_WR7_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR7_DEFAULT}] ${MODELPARAM_VALUE.C_WR7_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR8_DEFAULT { MODELPARAM_VALUE.C_WR8_DEFAULT PARAM_VALUE.C_WR8_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR8_DEFAULT}] ${MODELPARAM_VALUE.C_WR8_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR9_DEFAULT { MODELPARAM_VALUE.C_WR9_DEFAULT PARAM_VALUE.C_WR9_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR9_DEFAULT}] ${MODELPARAM_VALUE.C_WR9_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR10_DEFAULT { MODELPARAM_VALUE.C_WR10_DEFAULT PARAM_VALUE.C_WR10_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR10_DEFAULT}] ${MODELPARAM_VALUE.C_WR10_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR11_DEFAULT { MODELPARAM_VALUE.C_WR11_DEFAULT PARAM_VALUE.C_WR11_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR11_DEFAULT}] ${MODELPARAM_VALUE.C_WR11_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR12_DEFAULT { MODELPARAM_VALUE.C_WR12_DEFAULT PARAM_VALUE.C_WR12_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR12_DEFAULT}] ${MODELPARAM_VALUE.C_WR12_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR13_DEFAULT { MODELPARAM_VALUE.C_WR13_DEFAULT PARAM_VALUE.C_WR13_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR13_DEFAULT}] ${MODELPARAM_VALUE.C_WR13_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR14_DEFAULT { MODELPARAM_VALUE.C_WR14_DEFAULT PARAM_VALUE.C_WR14_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR14_DEFAULT}] ${MODELPARAM_VALUE.C_WR14_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR15_DEFAULT { MODELPARAM_VALUE.C_WR15_DEFAULT PARAM_VALUE.C_WR15_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR15_DEFAULT}] ${MODELPARAM_VALUE.C_WR15_DEFAULT} +} + diff --git a/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/component.xml b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/component.xml new file mode 100644 index 0000000..3affb02 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/component.xml @@ -0,0 +1,369 @@ + + + trenz.biz + user + axis_audio_pwm + 1.0 + + + S00_AXIS + + + + + + + TDATA + + + s00_axis_tdata + + + + + TVALID + + + s00_axis_tvalid + + + + + TREADY + + + s00_axis_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + + + S00_AXIS_RST + + + + + + + RST + + + s00_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S00_AXIS_CLK + + + + + + + CLK + + + s00_axis_aclk + + + + + + ASSOCIATED_BUSIF + S00_AXIS + + + ASSOCIATED_RESET + s00_axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_audio_pwm_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + e37e5f7b + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_audio_pwm_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + e37e5f7b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 85d97987 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + pwm_l_out + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + pwm_r_out + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tdata + + in + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_SYS_FREQ + C Sys Freq + 150000000 + + + C_PWM_FREQ + C Pwm Freq + 100000 + + + + + + choice_list_6fc15197 + 32 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd + vhdlSource + + + hdl/axis_audio_pwm_v1_0.vhd + vhdlSource + CHECKSUM_b42f8d78 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/axis_audio_pwm_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_audio_pwm_v1_0.tcl + tclSource + CHECKSUM_8d217f22 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + AXI4-Stream Audio PWM v1.0 + + + Component_Name + axis_audio_pwm_v1_0 + + + C_SYS_FREQ + Clock Frequency + 150000000 + + + C_PWM_FREQ + PWM Frequency + 100000 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /AXI_Peripheral + /Digital_Signal_Processing/Modulation + /Embedded_Processing/AXI_Peripheral/Low_Speed_Peripheral + + AXI4-Stream Audio PWM v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 4 + + xilinx.com:user:axis_audio_pwm:1.0 + + 2016-04-01T12:30:24Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_audio_pwm_1.0 + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_audio_pwm_1.0 + + + + 2015.4.2 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0.vhd b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0.vhd new file mode 100644 index 0000000..0d849c6 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0.vhd @@ -0,0 +1,86 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity axis_audio_pwm_v1_0 is +generic ( + C_SYS_FREQ : INTEGER := 150000000; + C_PWM_FREQ : INTEGER := 100000 -- Usually from 50 to 100 kHz +); +port ( + -- PWM Outs + pwm_l_out : out STD_LOGIC; + pwm_r_out : out STD_LOGIC; + -- Ports of Axi Slave Bus Interface S00_AXIS + s00_axis_aclk : in STD_LOGIC; + s00_axis_aresetn : in STD_LOGIC; + s00_axis_tready : out STD_LOGIC; + s00_axis_tdata : in STD_LOGIC_VECTOR(31 downto 0); + s00_axis_tvalid : in STD_LOGIC +); +end axis_audio_pwm_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_audio_pwm_v1_0 is +---------------------------------------------------------------------------------- +constant C_CNT_MAX : INTEGER := 32767; +constant C_CNT_MIN : INTEGER := -32767; +constant C_STEP : INTEGER := 131072 / (C_SYS_FREQ/C_PWM_FREQ); +---------------------------------------------------------------------------------- +signal left_ch_val : SIGNED(15 downto 0); -- Data latches +signal right_ch_val : SIGNED(15 downto 0); +signal pwm_cnt : SIGNED(15 downto 0); -- Reference signal +signal pwm_cnt_dir : STD_LOGIC; -- Saw direction +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +s00_axis_tready <= '1'; -- Always ready +-- Data latch +process(s00_axis_aclk) +begin + if(s00_axis_aclk = '1' and s00_axis_aclk'event)then + if(s00_axis_tvalid = '1')then + left_ch_val <= SIGNED(s00_axis_tdata(15 downto 0)); + right_ch_val <= SIGNED(s00_axis_tdata(31 downto 16)); + end if; + end if; +end process; + +-- PWM Coding +process(s00_axis_aclk) +begin + if(s00_axis_aclk = '1' and s00_axis_aclk'event)then + -- Triangle reference signal + if(pwm_cnt_dir = '0')then -- Up count + if(pwm_cnt >= TO_SIGNED((C_CNT_MAX - C_STEP),16))then + pwm_cnt_dir <= '1'; + pwm_cnt <= pwm_cnt - C_STEP; + else + pwm_cnt <= pwm_cnt + C_STEP; + end if; + else -- Down count + if(pwm_cnt <= TO_SIGNED((C_CNT_MIN + C_STEP),16))then + pwm_cnt_dir <= '0'; + pwm_cnt <= pwm_cnt + C_STEP; + else + pwm_cnt <= pwm_cnt - C_STEP; + end if; + end if; + -- Comparators + if(left_ch_val > pwm_cnt)then + pwm_l_out <= '1'; + else + pwm_l_out <= '0'; + end if; + if(right_ch_val > pwm_cnt)then + pwm_r_out <= '1'; + else + pwm_r_out <= '0'; + end if; + end if; +end process; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd new file mode 100644 index 0000000..227c142 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd @@ -0,0 +1,177 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axis_audio_pwm_v1_0_S00_AXIS is + generic ( + -- Users to add parameters here + + -- User parameters ends + -- Do not modify the parameters beyond this line + + -- AXI4Stream sink: Data Width + C_S_AXIS_TDATA_WIDTH : integer := 32 + ); + port ( + -- Users to add ports here + + -- User ports ends + -- Do not modify the ports beyond this line + + -- AXI4Stream sink: Clock + S_AXIS_ACLK : in std_logic; + -- AXI4Stream sink: Reset + S_AXIS_ARESETN : in std_logic; + -- Ready to accept data in + S_AXIS_TREADY : out std_logic; + -- Data in + S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0); + -- Byte qualifier + S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0); + -- Indicates boundary of last packet + S_AXIS_TLAST : in std_logic; + -- Data is in valid + S_AXIS_TVALID : in std_logic + ); +end axis_audio_pwm_v1_0_S00_AXIS; + +architecture arch_imp of axis_audio_pwm_v1_0_S00_AXIS is + -- function called clogb2 that returns an integer which has the + -- value of the ceiling of the log base 2. + function clogb2 (bit_depth : integer) return integer is + variable depth : integer := bit_depth; + begin + if (depth = 0) then + return(0); + else + for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers + if(depth <= 1) then + return(clogb2); + else + depth := depth / 2; + end if; + end loop; + end if; + end; + + -- Total number of input data. + constant NUMBER_OF_INPUT_WORDS : integer := 8; + -- bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO. + constant bit_num : integer := clogb2(NUMBER_OF_INPUT_WORDS-1); + -- Define the states of state machine + -- The control state machine oversees the writing of input streaming data to the FIFO, + -- and outputs the streaming data from the FIFO + type state is ( IDLE, -- This is the initial/idle state + WRITE_FIFO); -- In this state FIFO is written with the + -- input stream data S_AXIS_TDATA + signal axis_tready : std_logic; + -- State variable + signal mst_exec_state : state; + -- FIFO implementation signals + signal byte_index : integer; + -- FIFO write enable + signal fifo_wren : std_logic; + -- FIFO full flag + signal fifo_full_flag : std_logic; + -- FIFO write pointer + signal write_pointer : integer range 0 to bit_num-1 ; + -- sink has accepted all the streaming data and stored in FIFO + signal writes_done : std_logic; + + type BYTE_FIFO_TYPE is array (0 to (NUMBER_OF_INPUT_WORDS-1)) of std_logic_vector(((C_S_AXIS_TDATA_WIDTH/4)-1)downto 0); +begin + -- I/O Connections assignments + + S_AXIS_TREADY <= axis_tready; + -- Control state machine implementation + process(S_AXIS_ACLK) + begin + if (rising_edge (S_AXIS_ACLK)) then + if(S_AXIS_ARESETN = '0') then + -- Synchronous reset (active low) + mst_exec_state <= IDLE; + else + case (mst_exec_state) is + when IDLE => + -- The sink starts accepting tdata when + -- there tvalid is asserted to mark the + -- presence of valid streaming data + if (S_AXIS_TVALID = '1')then + mst_exec_state <= WRITE_FIFO; + else + mst_exec_state <= IDLE; + end if; + + when WRITE_FIFO => + -- When the sink has accepted all the streaming input data, + -- the interface swiches functionality to a streaming master + if (writes_done = '1') then + mst_exec_state <= IDLE; + else + -- The sink accepts and stores tdata + -- into FIFO + mst_exec_state <= WRITE_FIFO; + end if; + + when others => + mst_exec_state <= IDLE; + + end case; + end if; + end if; + end process; + -- AXI Streaming Sink + -- + -- The example design sink is always ready to accept the S_AXIS_TDATA until + -- the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words. + axis_tready <= '1' when ((mst_exec_state = WRITE_FIFO) and (write_pointer <= NUMBER_OF_INPUT_WORDS-1)) else '0'; + + process(S_AXIS_ACLK) + begin + if (rising_edge (S_AXIS_ACLK)) then + if(S_AXIS_ARESETN = '0') then + write_pointer <= 0; + writes_done <= '0'; + else + if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) then + if (fifo_wren = '1') then + -- write pointer is incremented after every write to the FIFO + -- when FIFO write signal is enabled. + write_pointer <= write_pointer + 1; + writes_done <= '0'; + end if; + if ((write_pointer = NUMBER_OF_INPUT_WORDS-1) or S_AXIS_TLAST = '1') then + -- reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data + -- has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage). + writes_done <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- FIFO write enable generation + fifo_wren <= S_AXIS_TVALID and axis_tready; + + -- FIFO Implementation + FIFO_GEN: for byte_index in 0 to (C_S_AXIS_TDATA_WIDTH/8-1) generate + + signal stream_data_fifo : BYTE_FIFO_TYPE; + begin + -- Streaming input data is stored in FIFO + process(S_AXIS_ACLK) + begin + if (rising_edge (S_AXIS_ACLK)) then + if (fifo_wren = '1') then + stream_data_fifo(write_pointer) <= S_AXIS_TDATA((byte_index*8+7) downto (byte_index*8)); + end if; + end if; + end process; + + end generate FIFO_GEN; + + -- Add user logic here + + -- User logic ends + +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/xgui/axis_audio_pwm_v1_0.tcl b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/xgui/axis_audio_pwm_v1_0.tcl new file mode 100644 index 0000000..3fa319f --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_audio_pwm_1.0/xgui/axis_audio_pwm_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_PWM_FREQ" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_SYS_FREQ" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_PWM_FREQ { PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to update C_PWM_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_PWM_FREQ { PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to validate C_PWM_FREQ + return true +} + +proc update_PARAM_VALUE.C_SYS_FREQ { PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to update C_SYS_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_SYS_FREQ { PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to validate C_SYS_FREQ + return true +} + + +proc update_MODELPARAM_VALUE.C_SYS_FREQ { MODELPARAM_VALUE.C_SYS_FREQ PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_SYS_FREQ}] ${MODELPARAM_VALUE.C_SYS_FREQ} +} + +proc update_MODELPARAM_VALUE.C_PWM_FREQ { MODELPARAM_VALUE.C_PWM_FREQ PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_PWM_FREQ}] ${MODELPARAM_VALUE.C_PWM_FREQ} +} + diff --git a/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/component.xml b/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/component.xml new file mode 100644 index 0000000..e02e2b6 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/component.xml @@ -0,0 +1,515 @@ + + + trenz.biz + user + axis_fb_conv + 1.0 + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TUSER + + + s_axis_tuser + + + + + + WIZ.DATA_WIDTH + 32 + + + + + video_out + + + + + + + TDATA + + + video_out_tdata + + + + + TLAST + + + video_out_tlast + + + + + TVALID + + + video_out_tvalid + + + + + TREADY + + + video_out_tready + + + + + TUSER + + + video_out_tuser + + + + + + WIZ.DATA_WIDTH + 32 + + + + + S_AXIS_RST + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S_AXIS_CLK + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS:video_out + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_fb_conv_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + c2b53453 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_fb_conv_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + c2b53453 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e24204be + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tdata + + out + + 23 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tlast + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tuser + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_FB_MODE + C Fb Mode + 1 + + + + false + + + + + + + + + choices_0 + 32 + + + choices_1 + 32 + + + choices_2 + 0 + 1 + + + + + xilinx_vhdlsynthesis_view_fileset + + src/axis_fb_conv_v1_0.vhd + vhdlSource + CHECKSUM_6e7698d9 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + src/axis_fb_conv_v1_0.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_fb_conv_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_bc827756 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + axis_fb_conv_v1.0 + + + Component_Name + axis_fb_conv_v1_0 + + + C_FB_MODE + Framebuffer Mode + 1 + + + + false + + + + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + AXI_Peripheral + + axis_fb_conv_v1.0 + Trenz Electronic GmbH + 5 + 2015-06-04T13:44:40Z + + b:/cores/2014.4/ip/axis_fb_conv_1.0 + + + + 2014.4 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/src/axis_fb_conv_v1_0.vhd b/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/src/axis_fb_conv_v1_0.vhd new file mode 100644 index 0000000..6177079 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/src/axis_fb_conv_v1_0.vhd @@ -0,0 +1,78 @@ +---------------------------------------------------------------------------------------------------- +--! @file axis_fb_conv_v1_0.vhd +--! @brief Simple remapper to convert 16 or 32 bit AXI4-Stream into Xilinx 24 bit Video Stream +--! @author Antti Lukats +--! @version 1.0 +--! @date 2015 +--! @copyright Copyright 2015 Trenz Electronic GmbH +--! @license BSD +--! @pre Vivado 2014.4+ +--! @pre Xilinx VDMA configured with 16 or 32 bit output +---------------------------------------------------------------------------------------------------- + +--! Use standard library +library ieee; +--! Use logic elements + use ieee.std_logic_1164.all; + +--! AXI4-Stream Remapper to be used with: +--! Linux Simple Frame Buffer driver, +--! Xilinx VDMA and Xilinx AXI4-stream to Video Out IP Cores. +entity axis_fb_conv_v1_0 is + generic ( + --! Format: The format of the framebuffer surface. Valid values are: + --! r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b). + --! a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r). + C_FB_MODE : integer range 0 to 1 := 1 --! Mode is set as: 0 = r5g6b5, 1 = a8b8g8r8 + ); + port ( + s_axis_aclk : in std_logic; --! not used + s_axis_aresetn : in std_logic; --! not used + --------------------------------------------------------------------- + s_axis_tready : out std_logic; --! direct bypass + s_axis_tdata : in std_logic_vector(C_FB_MODE*16+16-1 downto 0); --! Pixel data from VDMA IP Core + s_axis_tlast : in std_logic; --! end of line: direct bypass + s_axis_tuser : in std_logic; --! SOF: direct bypass + s_axis_tvalid : in std_logic; --! direct bypass + --------------------------------------------------------------------- + video_out_tvalid : out std_logic; --! direct from input Stream TVALID + video_out_tdata : out std_logic_vector(23 downto 0); --! Remapped TDATA + video_out_tlast : out std_logic; --! direct from input Stream TLAST + video_out_tuser : out std_logic; --! direct from input Stream TUSER + video_out_tready : in std_logic --! direct to input Stream TREADY + ); +end axis_fb_conv_v1_0; + +--! Simple remapper, only function is remap, there is no other logic used +architecture arch_imp of axis_fb_conv_v1_0 is + +signal r : std_logic_vector(7 downto 0) := (others => '0'); --! Red Component +signal g : std_logic_vector(7 downto 0) := (others => '0'); --! Green Component +signal b : std_logic_vector(7 downto 0) := (others => '0'); --! Blue Component +signal a : std_logic_vector(7 downto 0) := (others => '0'); --! Transparency, not used currently + +begin + video_out_tvalid <= s_axis_tvalid; -- Direct bypass + video_out_tlast <= s_axis_tlast; -- Direct bypass + video_out_tuser <= s_axis_tuser; -- Direct bypass + s_axis_tready <= video_out_tready; -- Direct bypass + +-- r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b). +Video_16_bit_Gen: if C_FB_MODE = 0 generate + r(7 downto 3) <= s_axis_tdata(15 downto 11); + g(7 downto 2) <= s_axis_tdata(10 downto 5); + b(7 downto 3) <= s_axis_tdata(4 downto 0); +end generate Video_16_bit_Gen; + +-- a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r). +Video_32_bit_Gen: if C_FB_MODE = 1 generate + b(7 downto 0) <= s_axis_tdata(23 downto 16); + g(7 downto 0) <= s_axis_tdata(15 downto 8); + r(7 downto 0) <= s_axis_tdata(7 downto 0); +end generate Video_32_bit_Gen; + +-- construct Xilinx Video RGB format +-- R B G, see PG044 +video_out_tdata(23 downto 0) <= r & b & g; + +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/xgui/axis_fb_conv_v1_0.tcl b/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/xgui/axis_fb_conv_v1_0.tcl new file mode 100644 index 0000000..a29491b --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_fb_conv_1.0/xgui/axis_fb_conv_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_FB_MODE" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_FB_MODE { PARAM_VALUE.C_FB_MODE } { + # Procedure called to update C_FB_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_FB_MODE { PARAM_VALUE.C_FB_MODE } { + # Procedure called to validate C_FB_MODE + return true +} + + +proc update_MODELPARAM_VALUE.C_FB_MODE { MODELPARAM_VALUE.C_FB_MODE PARAM_VALUE.C_FB_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_FB_MODE}] ${MODELPARAM_VALUE.C_FB_MODE} +} + diff --git a/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/component.xml b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/component.xml new file mode 100644 index 0000000..3956dca --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/component.xml @@ -0,0 +1,586 @@ + + + trenz.biz + user + axis_raw_demosaic + 1.0 + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TUSER + + + s_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + TUSER + + + m_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + axis_aresetn + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_aclk + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS:M_AXIS + + + ASSOCIATED_RESET + axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_raw_demosaic_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 340c8292 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_raw_demosaic_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 340c8292 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 766ecffa + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + colors_mode + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_RAW_WIDTH + C Raw Width + 10 + + + C_MODE + C Mode + 1 + + + C_IN_TYPE + C In Type + 1 + + + C_COLOR_POS + C Color Pos + 0 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_f5adc799 + 10 + 8 + + + choice_pairs_719c03b1 + 1 + 4 + + + choice_pairs_8aadb9bc + 0 + 1 + 2 + + + choice_pairs_e37d2356 + 0 + 1 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/dualport_ram.vhd + vhdlSource + + + hdl/gamma_rom.vhd + vhdlSource + + + hdl/axis_raw_demosaic_v1_0.vhd + vhdlSource + CHECKSUM_d52eb58c + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dualport_ram.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/gamma_rom.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/axis_raw_demosaic_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_raw_demosaic_v1_0.tcl + tclSource + CHECKSUM_6e4393c6 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + RAW format demosaic + + + Component_Name + axis_raw_demosaic_v1_0 + + + C_RAW_WIDTH + Raw Width + 10 + + + C_MODE + Mode + 1 + + + C_IN_TYPE + Input Type + 1 + + + C_COLOR_POS + Colors Position + 0 + + + + + + virtex7 + artix7 + kintex7 + qzynq + zynq + + + /AXI_Peripheral + /Video_&_Image_Processing + + RAW Demosaic v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 20 + + xilinx.com:user:axis_raw_demosaic:1.0 + + 2017-05-18T06:15:26Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_raw_demosaic_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_raw_demosaic_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/axis_raw_demosaic_v1_0.vhd b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/axis_raw_demosaic_v1_0.vhd new file mode 100644 index 0000000..f7b861b --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/axis_raw_demosaic_v1_0.vhd @@ -0,0 +1,252 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity axis_raw_demosaic_v1_0 is +generic ( + C_MODE : integer range 0 to 1 := 1; + C_COLOR_POS : integer range 0 to 2 := 0; + C_IN_TYPE : integer range 1 to 4 := 1; + C_RAW_WIDTH : integer := 10 +); +port ( + axis_aclk : in STD_LOGIC; + axis_aresetn : in STD_LOGIC; + + colors_mode : in STD_LOGIC; + + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_IN_TYPE*16-1 downto 0); + s_axis_tuser : in STD_LOGIC; + s_axis_tlast : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_IN_TYPE*32-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC +); +end axis_raw_demosaic_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_raw_demosaic_v1_0 is +---------------------------------------------------------------------------------- +component dualport_ram is +port ( + clk : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR(10 downto 0); + addrb : in STD_LOGIC_VECTOR(10 downto 0); + dia : in STD_LOGIC_VECTOR(9 downto 0); + dob : out STD_LOGIC_VECTOR(9 downto 0) +); +end component; + +component gamma_rom is +port( + addra : in STD_LOGIC_VECTOR(9 downto 0); + clka : in STD_LOGIC; + douta : out STD_LOGIC_VECTOR(7 downto 0) +); +end component; +---------------------------------------------------------------------------------- +signal tx_alpha : STD_LOGIC_VECTOR(7 downto 0); +signal tx_blue : STD_LOGIC_VECTOR(7 downto 0); +signal tx_green : STD_LOGIC_VECTOR(7 downto 0); +signal tx_red : STD_LOGIC_VECTOR(7 downto 0); +signal x_cnt : UNSIGNED(15 downto 0); +signal y_cnt : UNSIGNED(15 downto 0); +type sm_state_type is (ST_IDLE, ST_PROCESS, ST_SEND); +signal sm_state : sm_state_type := ST_IDLE; +signal up_pixel_data : STD_LOGIC_VECTOR(C_RAW_WIDTH-1 downto 0); +signal pixel_data : STD_LOGIC_VECTOR(C_RAW_WIDTH-1 downto 0); +signal position : STD_LOGIC_VECTOR(1 downto 0); +signal tx_valid : STD_LOGIC; +signal tx_user : STD_LOGIC; +signal tx_last : STD_LOGIC; +signal x_wr_addr : UNSIGNED(15 downto 0); +signal x_rd_addr : UNSIGNED(15 downto 0); +signal ram_write : STD_LOGIC; +signal ram_wr_addr : STD_LOGIC_VECTOR(10 downto 0); +signal ram_rd_addr : STD_LOGIC_VECTOR(10 downto 0); +signal ram_wr_data : STD_LOGIC_VECTOR( 9 downto 0); +signal ram_rd_data : STD_LOGIC_VECTOR( 9 downto 0); +type raw_pixel is array (3 downto 0) of STD_LOGIC_VECTOR(C_RAW_WIDTH-1 downto 0); +signal pixel : raw_pixel; +type std_pixel is array (3 downto 0) of STD_LOGIC_VECTOR(7 downto 0); +signal pixel_gamma : std_pixel; +signal colors_mode_i : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +ram_wr_addr <= STD_LOGIC_VECTOR(x_wr_addr(10 downto 0)); +ram_rd_addr <= STD_LOGIC_VECTOR(x_rd_addr(10 downto 0)); +ram_wr_data <= pixel(0); +up_pixel_data <= ram_rd_data; +pixel_data <= s_axis_tdata(C_RAW_WIDTH-1 downto 0); +---------------------------------------------------------------------------------- +ram_inst: dualport_ram +port map( + clk => axis_aclk, + wea => ram_write, + addra => ram_wr_addr, + addrb => ram_rd_addr, + dia => ram_wr_data, + dob => ram_rd_data +); +---------------------------------------------------------------------------------- +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_state is + when ST_IDLE => + if(s_axis_tvalid = '1')then + sm_state <= ST_PROCESS; + pixel(0) <= pixel_data; + pixel(1) <= pixel(0); + pixel(2) <= up_pixel_data; + pixel(3) <= pixel(2); + tx_user <= s_axis_tuser; + tx_last <= s_axis_tlast; + x_wr_addr <= x_cnt; + ram_write <= '1'; + position <= y_cnt(0) & x_cnt(0); + if(s_axis_tlast = '1')then + x_cnt <= (others => '0'); + x_rd_addr <= (others => '0'); + else + x_cnt <= x_cnt + 1; + x_rd_addr <= x_cnt + 1; + end if; + if(s_axis_tuser = '1')then + y_cnt <= (others => '0'); + elsif(s_axis_tlast = '1')then + y_cnt <= y_cnt + 1; + end if; + else + ram_write <= '0'; + end if; + when ST_PROCESS => + ram_write <= '0'; + sm_state <= ST_SEND; + when ST_SEND => + if(m_axis_tready = '1')then + if(s_axis_tvalid = '0')then + sm_state <= ST_IDLE; + ram_write <= '0'; + else + sm_state <= ST_PROCESS; + pixel(0) <= pixel_data; + pixel(1) <= pixel(0); + pixel(2) <= up_pixel_data; + pixel(3) <= pixel(2); + tx_user <= s_axis_tuser; + tx_last <= s_axis_tlast; + x_wr_addr <= x_cnt; + ram_write <= '1'; + position <= y_cnt(0) & x_cnt(0); + if(s_axis_tlast = '1')then + x_cnt <= (others => '0'); + x_rd_addr <= (others => '0'); + else + x_cnt <= x_cnt + 1; + x_rd_addr <= x_cnt + 1; + end if; + if(s_axis_tuser = '1')then + y_cnt <= (others => '0'); + elsif(s_axis_tlast = '1')then + y_cnt <= y_cnt + 1; + end if; + end if; + end if; + end case; + end if; +end process; +---------------------------------------------------------------------------------- +gamma_rom_gen: for i in 0 to 3 generate +begin + pa_gamma_inst: gamma_rom + port map( + addra => pixel(i), + clka => axis_aclk, + douta => pixel_gamma(i) + ); +end generate; +---------------------------------------------------------------------------------- +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + if(C_COLOR_POS = 0)then + colors_mode_i <= '0'; + elsif(C_COLOR_POS = 1)then + colors_mode_i <= '1'; + else -- C_COLOR_POS = 2 + colors_mode_i <= colors_mode; + end if; + end if; +end process; +---------------------------------------------------------------------------------- +tx_alpha <= (others => '0'); +-- Demosaic (Color) +demosaic_gen: if C_MODE = 1 generate +begin + + process(sm_state, m_axis_tready) + begin + case sm_state is + when ST_IDLE => s_axis_tready <= '1'; + when ST_PROCESS => s_axis_tready <= '0'; + when ST_SEND => s_axis_tready <= m_axis_tready; + end case; + end process; + + m_axis_tvalid <= '1' when (sm_state = ST_SEND) else '0'; + m_axis_tuser <= tx_user; + m_axis_tlast <= tx_last; + + process(position, tx_alpha, pixel_gamma, colors_mode_i) + begin + if(colors_mode_i = '0')then + case position is + when "01" => m_axis_tdata <= tx_alpha & pixel_gamma(1) & pixel_gamma(0) & pixel_gamma(2); + when "00" => m_axis_tdata <= tx_alpha & pixel_gamma(0) & pixel_gamma(1) & pixel_gamma(3); + when "11" => m_axis_tdata <= tx_alpha & pixel_gamma(3) & pixel_gamma(1) & pixel_gamma(0); + when "10" => m_axis_tdata <= tx_alpha & pixel_gamma(2) & pixel_gamma(0) & pixel_gamma(1); + when others => null; + end case; + else + case position is + when "01" => m_axis_tdata <= tx_alpha & pixel_gamma(2) & pixel_gamma(0) & pixel_gamma(1); + when "00" => m_axis_tdata <= tx_alpha & pixel_gamma(3) & pixel_gamma(1) & pixel_gamma(0); + when "11" => m_axis_tdata <= tx_alpha & pixel_gamma(0) & pixel_gamma(1) & pixel_gamma(3); + when "10" => m_axis_tdata <= tx_alpha & pixel_gamma(1) & pixel_gamma(0) & pixel_gamma(2); + when others => null; + end case; + end if; + end process; + +end generate; +---------------------------------------------------------------------------------- +-- Bypass (Raw grayscale) +bypass_gen: if C_MODE = 0 generate +begin + s_axis_tready <= m_axis_tready; + m_axis_tvalid <= s_axis_tvalid; + m_axis_tuser <= s_axis_tuser; + m_axis_tlast <= s_axis_tlast; + data_gen: for i in 0 to C_IN_TYPE-1 generate + begin + m_axis_tdata(i*32+31 downto i*32) <= x"00" & + s_axis_tdata(i*16+9 downto i*16+2) & + s_axis_tdata(i*16+9 downto i*16+2) & + s_axis_tdata(i*16+9 downto i*16+2); + end generate; +end generate; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/dualport_ram.vhd b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/dualport_ram.vhd new file mode 100644 index 0000000..85042bc --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/dualport_ram.vhd @@ -0,0 +1,39 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.STD_LOGIC_unsigned.all; +---------------------------------------------------------------------------------- +entity dualport_ram is +port ( + clk : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR(10 downto 0); + addrb : in STD_LOGIC_VECTOR(10 downto 0); + dia : in STD_LOGIC_VECTOR(9 downto 0); + dob : out STD_LOGIC_VECTOR(9 downto 0) +); +end dualport_ram; +---------------------------------------------------------------------------------- +architecture dualport_ram_arch of dualport_ram is +type ram_type is array (2047 downto 0) of STD_LOGIC_VECTOR (9 downto 0); +signal ram : ram_type; +---------------------------------------------------------------------------------- +attribute block_ram : boolean; +attribute block_ram of ram : signal is TRUE; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process (clk) +begin + if (clk'event and clk = '1') then + if (wea = '1') then + ram(conv_integer(addra)) <= dia; + end if; + dob <= ram(conv_integer(addrb)); + end if; +end process; +---------------------------------------------------------------------------------- +end dualport_ram_arch; diff --git a/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/gamma_rom.vhd b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/gamma_rom.vhd new file mode 100644 index 0000000..fc84945 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/hdl/gamma_rom.vhd @@ -0,0 +1,98 @@ +---------------------------------------------------------------------------------- +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.STD_LOGIC_arith.all; +use ieee.STD_LOGIC_unsigned.all; +---------------------------------------------------------------------------------- +entity gamma_rom is +port( + addra : in STD_LOGIC_VECTOR(9 downto 0); + clka : in STD_LOGIC; + douta : out STD_LOGIC_VECTOR(7 downto 0) +); +end gamma_rom; +---------------------------------------------------------------------------------- +architecture Behavioral of gamma_rom is +---------------------------------------------------------------------------------- +type rom_type is array (1023 downto 0) of std_logic_vector (7 downto 0); +signal rom : rom_type := ( +x"ff", x"ff", x"ff", x"ff", x"fe", x"fe", x"fe", x"fe", x"fe", x"fe", x"fe", x"fd", x"fd", x"fd", x"fd", x"fd", +x"fd", x"fd", x"fc", x"fc", x"fc", x"fc", x"fc", x"fc", x"fc", x"fc", x"fb", x"fb", x"fb", x"fb", x"fb", x"fb", +x"fb", x"fa", x"fa", x"fa", x"fa", x"fa", x"fa", x"fa", x"f9", x"f9", x"f9", x"f9", x"f9", x"f9", x"f9", x"f8", +x"f8", x"f8", x"f8", x"f8", x"f8", x"f8", x"f7", x"f7", x"f7", x"f7", x"f7", x"f7", x"f7", x"f6", x"f6", x"f6", +x"f6", x"f6", x"f6", x"f6", x"f5", x"f5", x"f5", x"f5", x"f5", x"f5", x"f5", x"f4", x"f4", x"f4", x"f4", x"f4", +x"f4", x"f4", x"f3", x"f3", x"f3", x"f3", x"f3", x"f3", x"f3", x"f2", x"f2", x"f2", x"f2", x"f2", x"f2", x"f2", +x"f1", x"f1", x"f1", x"f1", x"f1", x"f1", x"f1", x"f0", x"f0", x"f0", x"f0", x"f0", x"f0", x"f0", x"ef", x"ef", +x"ef", x"ef", x"ef", x"ef", x"ef", x"ee", x"ee", x"ee", x"ee", x"ee", x"ee", x"ed", x"ed", x"ed", x"ed", x"ed", +x"ed", x"ed", x"ec", x"ec", x"ec", x"ec", x"ec", x"ec", x"ec", x"eb", x"eb", x"eb", x"eb", x"eb", x"eb", x"eb", +x"ea", x"ea", x"ea", x"ea", x"ea", x"ea", x"e9", x"e9", x"e9", x"e9", x"e9", x"e9", x"e9", x"e8", x"e8", x"e8", +x"e8", x"e8", x"e8", x"e8", x"e7", x"e7", x"e7", x"e7", x"e7", x"e7", x"e7", x"e6", x"e6", x"e6", x"e6", x"e6", +x"e6", x"e5", x"e5", x"e5", x"e5", x"e5", x"e5", x"e5", x"e4", x"e4", x"e4", x"e4", x"e4", x"e4", x"e3", x"e3", +x"e3", x"e3", x"e3", x"e3", x"e3", x"e2", x"e2", x"e2", x"e2", x"e2", x"e2", x"e2", x"e1", x"e1", x"e1", x"e1", +x"e1", x"e1", x"e0", x"e0", x"e0", x"e0", x"e0", x"e0", x"e0", x"df", x"df", x"df", x"df", x"df", x"df", x"de", +x"de", x"de", x"de", x"de", x"de", x"de", x"dd", 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x"41", x"40", x"40", x"40", x"3f", x"3f", x"3e", x"3e", +x"3d", x"3d", x"3d", x"3c", x"3c", x"3b", x"3b", x"3a", x"3a", x"39", x"39", x"39", x"38", x"38", x"37", x"37", +x"36", x"36", x"35", x"35", x"34", x"34", x"33", x"33", x"32", x"32", x"31", x"31", x"30", x"30", x"2f", x"2f", +x"2e", x"2e", x"2d", x"2c", x"2c", x"2b", x"2b", x"2a", x"2a", x"29", x"28", x"28", x"27", x"26", x"26", x"25", +x"25", x"24", x"23", x"23", x"22", x"21", x"20", x"20", x"1f", x"1e", x"1d", x"1d", x"1c", x"1b", x"1a", x"19", +x"18", x"18", x"17", x"16", x"15", x"13", x"12", x"11", x"10", x"0f", x"0d", x"0c", x"0a", x"08", x"05", x"00" +); +attribute rom_style : string; +attribute rom_style of rom : signal is "block"; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process (clka) +begin + if rising_edge(clka) then + douta <= rom(conv_integer(addra)); + end if; +end process; +---------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/xgui/axis_raw_demosaic_v1_0.tcl b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/xgui/axis_raw_demosaic_v1_0.tcl new file mode 100644 index 0000000..b4dad42 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_demosaic_1.0/xgui/axis_raw_demosaic_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_MODE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_IN_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_RAW_WIDTH" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_COLOR_POS" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_COLOR_POS { PARAM_VALUE.C_COLOR_POS } { + # Procedure called to update C_COLOR_POS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_COLOR_POS { PARAM_VALUE.C_COLOR_POS } { + # Procedure called to validate C_COLOR_POS + return true +} + +proc update_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to update C_IN_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to validate C_IN_TYPE + return true +} + +proc update_PARAM_VALUE.C_MODE { PARAM_VALUE.C_MODE } { + # Procedure called to update C_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_MODE { PARAM_VALUE.C_MODE } { + # Procedure called to validate C_MODE + return true +} + +proc update_PARAM_VALUE.C_RAW_WIDTH { PARAM_VALUE.C_RAW_WIDTH } { + # Procedure called to update C_RAW_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RAW_WIDTH { PARAM_VALUE.C_RAW_WIDTH } { + # Procedure called to validate C_RAW_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_RAW_WIDTH { MODELPARAM_VALUE.C_RAW_WIDTH PARAM_VALUE.C_RAW_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RAW_WIDTH}] ${MODELPARAM_VALUE.C_RAW_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_MODE { MODELPARAM_VALUE.C_MODE PARAM_VALUE.C_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_MODE}] ${MODELPARAM_VALUE.C_MODE} +} + +proc update_MODELPARAM_VALUE.C_IN_TYPE { MODELPARAM_VALUE.C_IN_TYPE PARAM_VALUE.C_IN_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IN_TYPE}] ${MODELPARAM_VALUE.C_IN_TYPE} +} + +proc update_MODELPARAM_VALUE.C_COLOR_POS { MODELPARAM_VALUE.C_COLOR_POS PARAM_VALUE.C_COLOR_POS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_COLOR_POS}] ${MODELPARAM_VALUE.C_COLOR_POS} +} + diff --git a/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/component.xml b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/component.xml new file mode 100644 index 0000000..7574af6 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/component.xml @@ -0,0 +1,524 @@ + + + trenz.biz + user + axis_raw_unpack + 1.0 + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TUSER + + + s_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + TUSER + + + m_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + axis_aresetn + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_aclk + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS:M_AXIS + + + ASSOCIATED_RESET + axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_raw_unpack_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 71a3a0ad + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_raw_unpack_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 71a3a0ad + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 18ee627c + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + + C_IMP_TYPE + C Imp Type + 0 + + + C_OUT_TYPE + C Out Type + 4 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_719c03b1 + 1 + 4 + + + choice_pairs_a91bb82a + 0 + 1 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/srl_fifo.vhd + vhdlSource + + + hdl/axis_raw_unpack_v1_0.vhd + vhdlSource + CHECKSUM_4d998fbe + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/srl_fifo.vhd + vhdlSource + + + hdl/axis_raw_unpack_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_raw_unpack_v1_0.tcl + tclSource + CHECKSUM_13a7b1e1 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + RAW10 2 Lanes format unpack + + + Component_Name + axis_raw_unpack_v1_0 + + + C_IMP_TYPE + Implementation Type + 0 + + + C_OUT_TYPE + Output Type + 4 + + + + + + virtex7 + artix7 + zynq + kintex7 + + + /AXI_Peripheral + /Video_&_Image_Processing + + RAW10 Unpack v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 17 + + xilinx.com:user:axis_raw_unpack:1.0 + + 2017-05-17T15:02:49Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_raw_unpack_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_raw_unpack_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/hdl/axis_raw_unpack_v1_0.vhd b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/hdl/axis_raw_unpack_v1_0.vhd new file mode 100644 index 0000000..82940b6 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/hdl/axis_raw_unpack_v1_0.vhd @@ -0,0 +1,288 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +Library UNISIM; +use UNISIM.vcomponents.all; +Library UNIMACRO; +use UNIMACRO.vcomponents.all; +---------------------------------------------------------------------------------- +entity axis_raw_unpack_v1_0 is +generic ( + C_IMP_TYPE : integer range 0 to 1 := 0; + C_OUT_TYPE : integer range 1 to 4 := 4 +); +port ( + axis_aclk : in STD_LOGIC; + axis_aresetn : in STD_LOGIC; + -- Ports of Axi Slave Bus Interface S_AXIS + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(15 downto 0); + s_axis_tuser : in STD_LOGIC; + s_axis_tlast : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + -- Ports of Axi Master Bus Interface M_AXIS + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_OUT_TYPE*16-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC +); +end axis_raw_unpack_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_raw_unpack_v1_0 is +---------------------------------------------------------------------------------- +constant C_DEVICE : STRING := "7SERIES"; +constant C_FIFO_SIZE : STRING := "18Kb"; +type sm_rx_state_type is (ST_IDLE, ST_PA, ST_PB, ST_PC, ST_PD); +signal sm_rx_state : sm_rx_state_type := ST_IDLE; +type sm_tx_state_type is (ST_WAIT, ST_TXA, ST_TXB, ST_TXC, ST_TXD); +signal sm_tx_state : sm_tx_state_type := ST_WAIT; +type sm_rxp_state_type is (ST_PIDLE, ST_PPA, ST_PPB, ST_PPC, ST_PPD, ST_PPW); +signal sm_rxp_state : sm_rxp_state_type := ST_PIDLE; + +signal pixels_data : STD_LOGIC_VECTOR(39 downto 0); +signal last : STD_LOGIC; +signal user : STD_LOGIC; +signal pixel_a : STD_LOGIC_VECTOR(9 downto 0); +signal pixel_b : STD_LOGIC_VECTOR(9 downto 0); +signal pixel_c : STD_LOGIC_VECTOR(9 downto 0); +signal pixel_d : STD_LOGIC_VECTOR(9 downto 0); +signal pixels_valid : STD_LOGIC; +signal buffer_we : STD_LOGIC; +signal buffer_re : STD_LOGIC; +signal buffer_full : STD_LOGIC; +signal buffer_empty : STD_LOGIC; +signal buffer_in_data : STD_LOGIC_VECTOR(41 downto 0); +signal buffer_out_data : STD_LOGIC_VECTOR(41 downto 0); + +component srl_fifo is +generic( + C_DEPTH : integer := 32; + C_WIDTH : integer := 8 +); +port ( + clk_in : in STD_LOGIC; + we_in : in STD_LOGIC; + re_in : in STD_LOGIC; + full_out : out STD_LOGIC; + empty_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0) +); +end component; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +-- 16 bit input implementation +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_rx_state is + when ST_IDLE => + buffer_we <= '0'; + if(s_axis_tvalid = '1')then + pixels_data( 9 downto 2) <= s_axis_tdata( 7 downto 0); -- P0 + pixels_data(19 downto 12) <= s_axis_tdata(15 downto 8); -- P1 + user <= s_axis_tuser; + if(s_axis_tlast /= '1')then + sm_rx_state <= ST_PA; + end if; + end if; + + when ST_PA => + buffer_we <= '0'; + if(s_axis_tvalid = '1')then + pixels_data(29 downto 22) <= s_axis_tdata( 7 downto 0); -- P2 + pixels_data(39 downto 32) <= s_axis_tdata(15 downto 8); -- P3 + if(s_axis_tuser = '1')then -- Problem + sm_rx_state <= ST_PA; + elsif(s_axis_tlast /= '1')then + sm_rx_state <= ST_PB; + else + sm_rx_state <= ST_IDLE; + end if; + end if; + + when ST_PB => + if((s_axis_tvalid = '1') and (buffer_full = '0'))then + pixel_a( 9 downto 2) <= pixels_data( 9 downto 2); + pixel_a( 1 downto 0) <= s_axis_tdata( 1 downto 0); + pixel_b( 9 downto 2) <= pixels_data(19 downto 12); + pixel_b( 1 downto 0) <= s_axis_tdata( 3 downto 2); + pixel_c( 9 downto 2) <= pixels_data(29 downto 22); + pixel_c( 1 downto 0) <= s_axis_tdata( 5 downto 4); + pixel_d( 9 downto 2) <= pixels_data(39 downto 32); + pixel_d( 1 downto 0) <= s_axis_tdata( 7 downto 6); + last <= s_axis_tlast; + buffer_we <= '1'; + pixels_data( 9 downto 2) <= s_axis_tdata(15 downto 8); + if(s_axis_tuser = '1')then -- Problem + sm_rx_state <= ST_PA; + elsif(s_axis_tlast /= '1')then + sm_rx_state <= ST_PC; + else + sm_rx_state <= ST_IDLE; + end if; + end if; + + when ST_PC => + buffer_we <= '0'; + if(s_axis_tvalid = '1')then + pixels_data(19 downto 12) <= s_axis_tdata( 7 downto 0); -- P1 + pixels_data(29 downto 22) <= s_axis_tdata(15 downto 8); -- P2 + if(s_axis_tuser = '1')then -- Problem + sm_rx_state <= ST_PA; + elsif(s_axis_tlast /= '1')then + sm_rx_state <= ST_PD; + else + sm_rx_state <= ST_IDLE; + end if; + end if; + + when ST_PD => + if((s_axis_tvalid = '1') and (buffer_full = '0'))then + pixel_a( 9 downto 2) <= pixels_data( 9 downto 2); + pixel_a( 1 downto 0) <= s_axis_tdata( 9 downto 8); + pixel_b( 9 downto 2) <= pixels_data(19 downto 12); + pixel_b( 1 downto 0) <= s_axis_tdata(11 downto 10); + pixel_c( 9 downto 2) <= pixels_data(29 downto 22); + pixel_c( 1 downto 0) <= s_axis_tdata(13 downto 12); + pixel_d( 9 downto 2) <= s_axis_tdata( 7 downto 0); + pixel_d( 1 downto 0) <= s_axis_tdata(15 downto 14); + buffer_we <= '1'; + user <= '0'; + last <= s_axis_tlast; + if(s_axis_tuser = '1')then -- Problem + sm_rx_state <= ST_PA; + else + sm_rx_state <= ST_IDLE; + end if; + end if; + end case; + end if; +end process; + +process(sm_rx_state, pixels_valid) +begin + case sm_rx_state is + when ST_IDLE => s_axis_tready <= '1'; + when ST_PA => s_axis_tready <= '1'; + when ST_PB => s_axis_tready <= not buffer_full; + when ST_PC => s_axis_tready <= '1'; + when ST_PD => s_axis_tready <= not buffer_full; + end case; +end process; +---------------------------------------------------------------------------------- +reg_buf_gen: if C_IMP_TYPE = 0 generate +begin + process(axis_aclk) + begin + if(axis_aclk = '1' and axis_aclk'event)then + if(pixels_valid = '0')then + if(((sm_rx_state = ST_PB) or (sm_rx_state = ST_PD)) and (s_axis_tvalid = '1'))then + pixels_valid <= '1'; + end if; + else + if(buffer_re = '1')then + pixels_valid <= '0'; + end if; + end if; + end if; + end process; + + buffer_full <= pixels_valid; + buffer_empty <= not pixels_valid; + buffer_out_data <= last & user & pixel_d & pixel_c & pixel_b & pixel_a; + +end generate; +---------------------------------------------------------------------------------- +fifo_buf_gen: if C_IMP_TYPE = 1 generate +begin + buffer_in_data <= last & user & pixel_d & pixel_c & pixel_b & pixel_a; + + FIFO_inst: srl_fifo + generic map( + C_DEPTH => 32, + C_WIDTH => 42 + ) + port map( + clk_in => axis_aclk, + we_in => buffer_we, + re_in => buffer_re, + full_out => buffer_full, + empty_out => buffer_empty, + data_in => buffer_in_data, + data_out => buffer_out_data + ); +end generate; +---------------------------------------------------------------------------------- +serial_out_gen: if C_OUT_TYPE = 1 generate +begin + process(axis_aclk) + begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_tx_state is + when ST_WAIT => + if(buffer_empty = '0')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0); + m_axis_tuser <= buffer_out_data(40); + m_axis_tlast <= '0'; + sm_tx_state <= ST_TXA; + end if; + when ST_TXA => + if(m_axis_tready = '1')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(19 downto 10); + m_axis_tuser <= '0'; + m_axis_tlast <= '0'; + sm_tx_state <= ST_TXB; + end if; + when ST_TXB => + if(m_axis_tready = '1')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(29 downto 20); + m_axis_tuser <= '0'; + m_axis_tlast <= '0'; + sm_tx_state <= ST_TXC; + end if; + when ST_TXC => + if(m_axis_tready = '1')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(39 downto 30); + m_axis_tuser <= '0'; + m_axis_tlast <= buffer_out_data(41); + sm_tx_state <= ST_TXD; + end if; + when ST_TXD => + if(m_axis_tready = '1')then + if(buffer_empty = '0')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0); + m_axis_tuser <= buffer_out_data(40); + m_axis_tlast <= '0'; + sm_tx_state <= ST_TXA; + else + sm_tx_state <= ST_WAIT; + m_axis_tlast <= '0'; + end if; + end if; + end case; + end if; + end process; + buffer_re <= '1' when ((sm_tx_state = ST_TXC) and (m_axis_tready = '1')) else '0'; + m_axis_tvalid <= '1' when (sm_tx_state /= ST_WAIT) else '0'; +end generate; -- serial_out_gen + +parallel4_out_gen: if C_OUT_TYPE = 4 generate +begin + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0); + m_axis_tdata(31 downto 16) <= "000000" & buffer_out_data(19 downto 10); + m_axis_tdata(47 downto 32) <= "000000" & buffer_out_data(29 downto 20); + m_axis_tdata(63 downto 48) <= "000000" & buffer_out_data(39 downto 30); + m_axis_tuser <= buffer_out_data(40); + m_axis_tlast <= buffer_out_data(41); + m_axis_tvalid <= not buffer_empty; + buffer_re <= m_axis_tready; +end generate; -- parallel4_out_gen +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/hdl/srl_fifo.vhd b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/hdl/srl_fifo.vhd new file mode 100644 index 0000000..4330b33 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/hdl/srl_fifo.vhd @@ -0,0 +1,113 @@ +------------------------------------------------------------------------------- +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko +-- +-- SRL based FWPT FIFO +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VComponents.all; +------------------------------------------------------------------------------- +entity srl_fifo is +generic( + C_DEPTH : integer := 64; + C_WIDTH : integer := 8 +); +port ( + clk_in : in STD_LOGIC; + we_in : in STD_LOGIC; + re_in : in STD_LOGIC; + full_out : out STD_LOGIC; + empty_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0) +); +end srl_fifo; +------------------------------------------------------------------------------- +architecture Behavioral of srl_fifo is +------------------------------------------------------------------------------- +type arr_type is array(C_DEPTH/32 downto 0) of STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); +signal ddata : arr_type; +type arrp_type is array(C_DEPTH/32+1 downto 0) of STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); +signal cdata : arrp_type; +signal word_cnt : UNSIGNED(5 downto 0); +signal addr_cnt : UNSIGNED(4 downto 0); +signal srl_addr : STD_LOGIC_VECTOR(4 downto 0); +signal srl_ce : STD_LOGIC; +type fifo_state_type is (ST_EMPTY, ST_NOT_EMPTY, ST_FULL); +signal fifo_state : fifo_state_type := ST_EMPTY; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +cdata(0) <= data_in; +width_gen: for i in C_WIDTH - 1 downto 0 generate +begin + depth_gen: for j in (C_DEPTH/32)-1 downto 0 generate + begin + SRLC32E_1 : SRLC32E + port map ( + D => cdata(j)(i), + Q => ddata(j)(i), + Q31 => cdata(j+1)(i), + A => srl_addr(4 downto 0), + CE => srl_ce, + CLK => clk_in + ); + end generate; +end generate; +srl_addr <= STD_LOGIC_VECTOR(addr_cnt); + +full_out <= '1' when (fifo_state = ST_FULL ) else '0'; +empty_out <= '1' when (fifo_state = ST_EMPTY) else '0'; +srl_ce <= '1' when ((we_in = '1') and (fifo_state /= ST_FULL)) else '0'; + +single_stage_gen: if C_DEPTH = 32 generate +begin + data_out <= ddata(0); +end generate; +multi_stage_gen: if C_DEPTH > 32 generate +begin + data_out <= ddata(TO_INTEGER(addr_cnt(addr_cnt'high downto 5))); +end generate; + +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + case fifo_state is + when ST_EMPTY => + addr_cnt <= (others => '0'); + if(we_in = '1')then + word_cnt <= TO_UNSIGNED(1, word_cnt'length); + fifo_state <= ST_NOT_EMPTY; + end if; + when ST_NOT_EMPTY => + if(we_in = '1')then + if(re_in = '0')then -- Write + if(word_cnt = TO_UNSIGNED((C_DEPTH-1), word_cnt'length))then + fifo_state <= ST_FULL; + end if; + word_cnt <= word_cnt + 1; + addr_cnt <= addr_cnt + 1; + end if; + elsif(re_in = '1')then + if(word_cnt = TO_UNSIGNED(1, word_cnt'length))then + fifo_state <= ST_EMPTY; + word_cnt <= word_cnt - 1; + else + word_cnt <= word_cnt - 1; + addr_cnt <= addr_cnt - 1; + end if; + end if; + when ST_FULL => + if(re_in = '1')then + word_cnt <= word_cnt - 1; + addr_cnt <= addr_cnt - 1; + fifo_state <= ST_NOT_EMPTY; + end if; + end case; + end if; +end process; +------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/src/srl_fifo.vhd b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/src/srl_fifo.vhd new file mode 100644 index 0000000..a853ac4 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/src/srl_fifo.vhd @@ -0,0 +1,111 @@ +------------------------------------------------------------------------------- +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko +-- +-- SRL based FWPT FIFO +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VComponents.all; +------------------------------------------------------------------------------- +entity srl_fifo is +generic( + C_DEPTH : integer := 32; + C_WIDTH : integer := 8 +); +port ( + clk_in : in STD_LOGIC; + we_in : in STD_LOGIC; + re_in : in STD_LOGIC; + full_out : out STD_LOGIC; + empty_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0) +); +end srl_fifo; +------------------------------------------------------------------------------- +architecture Behavioral of srl_fifo is +------------------------------------------------------------------------------- +type arr_type is array(C_DEPTH/32 downto 0) of STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); +signal ddata : arr_type; +type arrp_type is array(C_DEPTH/32+1 downto 0) of STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); +signal cdata : arrp_type; +signal word_cnt : UNSIGNED(5 downto 0); +signal addr_cnt : UNSIGNED(4 downto 0); +signal srl_addr : STD_LOGIC_VECTOR(4 downto 0); +signal srl_ce : STD_LOGIC; +type fifo_state_type is (ST_EMPTY, ST_NOT_EMPTY, ST_FULL); +signal fifo_state : fifo_state_type := ST_EMPTY; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +cdata(0) <= data_in; +width_gen: for i in C_WIDTH - 1 downto 0 generate +begin + depth_gen: for j in C_DEPTH/32 downto 0 generate + begin + SRLC32E_1 : SRLC32E + port map ( + D => cdata(j)(i), + Q => ddata(j)(i), + Q31 => cdata(j+1)(i), + A => srl_addr(4 downto 0), + CE => srl_ce, + CLK => clk_in + ); + end generate; +end generate; +srl_addr <= STD_LOGIC_VECTOR(addr_cnt); + +full_out <= '1' when (fifo_state = ST_FULL ) else '0'; +empty_out <= '1' when (fifo_state = ST_EMPTY) else '0'; +srl_ce <= '1' when ((we_in = '1') and ((fifo_state /= ST_FULL) or (re_in = '1'))) else '0'; + +single_stage_gen: if C_DEPTH = 32 generate +begin + data_out <= ddata(0); +end generate; +-- multi_stage_gen: if C_DEPTH > 32 generate +-- begin + -- data_out <= ddata(TO_INTEGER(addr_cnt(addr_cnt'high downto 5))); +-- end generate; + +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + case fifo_state is + when ST_EMPTY => + if(we_in = '1')then + word_cnt <= word_cnt + 1; + fifo_state <= ST_NOT_EMPTY; + end if; + when ST_NOT_EMPTY => + if(we_in = '1')then + if(re_in = '0')then -- Write + if(word_cnt = TO_UNSIGNED((C_DEPTH-1), word_cnt'width))then + fifo_state <= ST_FULL; + end if; + word_cnt <= word_cnt + 1; + addr_cnt <= addr_cnt + 1; + end if; + elsif(re_in = '1')then + if(word_cnt = TO_UNSIGNED(1, word_cnt'width))then + fifo_state <= ST_EMPTY; + word_cnt <= word_cnt - 1; + else + word_cnt <= word_cnt - 1; + addr_cnt <= addr_cnt - 1; + end if; + end if; + when ST_FULL => + if((re_in = '1') and (we_in = '0'))then + word_cnt <= word_cnt - 1; + addr_cnt <= addr_cnt - 1; + end if; + end case; + end if; +end process; +------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/xgui/axis_raw_unpack_v1_0.tcl b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/xgui/axis_raw_unpack_v1_0.tcl new file mode 100644 index 0000000..cbb2c6c --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_raw_unpack_1.0/xgui/axis_raw_unpack_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_IMP_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_OUT_TYPE" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_IMP_TYPE { PARAM_VALUE.C_IMP_TYPE } { + # Procedure called to update C_IMP_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IMP_TYPE { PARAM_VALUE.C_IMP_TYPE } { + # Procedure called to validate C_IMP_TYPE + return true +} + +proc update_PARAM_VALUE.C_OUT_TYPE { PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to update C_OUT_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_OUT_TYPE { PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to validate C_OUT_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.C_IMP_TYPE { MODELPARAM_VALUE.C_IMP_TYPE PARAM_VALUE.C_IMP_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IMP_TYPE}] ${MODELPARAM_VALUE.C_IMP_TYPE} +} + +proc update_MODELPARAM_VALUE.C_OUT_TYPE { MODELPARAM_VALUE.C_OUT_TYPE PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_OUT_TYPE}] ${MODELPARAM_VALUE.C_OUT_TYPE} +} + diff --git a/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/component.xml b/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/component.xml new file mode 100644 index 0000000..b9448e0 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/component.xml @@ -0,0 +1,324 @@ + + + trenz.biz + user + axis_to_i2s + 1.0 + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_to_i2s + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 5b9a2668 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_to_i2s + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5b9a2668 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f64a5dae + + + + + + + s_axis_aclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aresetn + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_bclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_lrclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_sdata + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/axis_to_i2s.vhd + vhdlSource + CHECKSUM_5b9a2668 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/axis_to_i2s.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_to_i2s_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + AXI4-Stream to I2S v1.0 + + + Component_Name + axis_to_i2s_v1_0 + + + + + + virtex7 + kintex7 + artix7 + zynq + + + /Embedded_Processing/AXI_Peripheral + /Embedded_Processing/AXI_Peripheral/Low_Speed_Peripheral + /UserIP + + AXI4-Stream to I2S v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 4 + + xilinx.com:user:axis_to_i2s:1.0 + + 2016-04-29T07:00:54Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_to_i2s_1.0 + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_to_i2s_1.0 + + + + 2015.4.2 + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/hdl/axis_to_i2s.vhd b/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/hdl/axis_to_i2s.vhd new file mode 100644 index 0000000..fa14fc3 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/hdl/axis_to_i2s.vhd @@ -0,0 +1,66 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity axis_to_i2s is +port ( + -- Ports of Axi Slave Bus Interface S_AXIS + s_axis_aclk : in STD_LOGIC; + s_axis_aresetn : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(15 downto 0); + s_axis_tvalid : in STD_LOGIC; + -- I2S Signals + i2s_bclk : in STD_LOGIC; + i2s_lrclk : in STD_LOGIC; + i2s_sdata : out STD_LOGIC +); +end axis_to_i2s; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_to_i2s is +---------------------------------------------------------------------------------- +signal input_data : STD_LOGIC_VECTOR(15 downto 0); +signal bclk_sr : STD_LOGIC_VECTOR( 1 downto 0); +signal lrclk_sr : STD_LOGIC_VECTOR( 1 downto 0); +signal data_sr : STD_LOGIC_VECTOR(31 downto 0); +signal load_flag : STD_LOGIC; +signal channel_flag : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +s_axis_tready <= '1'; +process(s_axis_aclk) +begin + if(s_axis_aclk = '1' and s_axis_aclk'event)then + bclk_sr <= bclk_sr(0) & i2s_bclk; + lrclk_sr <= lrclk_sr(0) & i2s_lrclk; + if(s_axis_tvalid = '1')then + input_data <= s_axis_tdata; + end if; + + if((lrclk_sr = "10") or (lrclk_sr = "01"))then -- LR Edge + channel_flag <= '1'; + elsif(bclk_sr = "01")then -- Rising edge + channel_flag <= '0'; + end if; + + if(bclk_sr = "01")then -- Rising edge + load_flag <= channel_flag; + end if; + + if(bclk_sr = "10")then -- Falling edge + if(load_flag = '1')then + data_sr <= input_data & x"0000"; + else + data_sr <= data_sr(30 downto 0) & '0'; + end if; + end if; + end if; +end process; +i2s_sdata <= data_sr(31); +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/xgui/axis_to_i2s_v1_0.tcl b/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/xgui/axis_to_i2s_v1_0.tcl new file mode 100644 index 0000000..66195ab --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_to_i2s_1.0/xgui/axis_to_i2s_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/component.xml b/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/component.xml new file mode 100644 index 0000000..8c3a78c --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/component.xml @@ -0,0 +1,535 @@ + + + trenz.biz + user + axis_video_dwidth_converter + 1.0 + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TUSER + + + s_axis_tuser + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + + + axis_aresetn + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_aclk + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis:m_axis + + + ASSOCIATED_RESET + axis_aresetn + + + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_video_dwidth_converter_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + c5686eda + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_video_dwidth_converter_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + c5686eda + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 6001f6d0 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_IN_TYPE + C In Type + 1 + + + C_OUT_TYPE + C Out Type + 1 + + + C_DATA_WIDTH + C Data Width + 32 + + + + + + choice_list_07c83d4f + 16 + 32 + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_719c03b1 + 1 + 4 + + + choice_pairs_95e1d6c3 + 1 + 2 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axis_video_dwidth_converter_v1_0.vhd + vhdlSource + CHECKSUM_c5686eda + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axis_video_dwidth_converter_v1_0.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_video_dwidth_converter_v1_0.tcl + tclSource + CHECKSUM_7e8a0bf1 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + AXI4-Stream Video Data Width Converter + + + Component_Name + axis_video_dwidth_converter_v1_0 + + + C_IN_TYPE + Input Type + 1 + + + C_OUT_TYPE + Output Type + 1 + + + C_DATA_WIDTH + Data Width + 32 + + + + + + zynq + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + qzynq + azynq + virtexu + virtexuplus + kintexuplus + zynquplus + kintexu + + + /AXI_Peripheral + /Video_&_Image_Processing + + AXI4-Stream Video Data Width Converter v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 9 + + xilinx.com:user:axis_video_dwidth_converter:1.0 + + 2017-05-17T13:30:41Z + + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_video_dwidth_converter_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_video_dwidth_converter_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/hdl/axis_video_dwidth_converter_v1_0.vhd b/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/hdl/axis_video_dwidth_converter_v1_0.vhd new file mode 100644 index 0000000..723cbee --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/hdl/axis_video_dwidth_converter_v1_0.vhd @@ -0,0 +1,146 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity axis_video_dwidth_converter_v1_0 is +generic ( + C_DATA_WIDTH : integer := 32; + C_IN_TYPE : integer range 1 to 4 := 4; + C_OUT_TYPE : integer range 1 to 4 := 1 +); +port ( + axis_aclk : in STD_LOGIC; + axis_aresetn : in STD_LOGIC; + -- Ports of Axi Slave Bus Interface S_AXIS + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_IN_TYPE*C_DATA_WIDTH-1 downto 0); + s_axis_tuser : in STD_LOGIC; + s_axis_tlast : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + -- Ports of Axi Master Bus Interface M_AXIS + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC +); +end axis_video_dwidth_converter_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_video_dwidth_converter_v1_0 is +---------------------------------------------------------------------------------- +type sm_state_type is (ST_IDLE, ST_1W, ST_2W, ST_3W); +signal sm_state : sm_state_type := ST_IDLE; +signal tdata_buffer : STD_LOGIC_VECTOR((C_IN_TYPE-C_OUT_TYPE)*C_DATA_WIDTH-1 downto 0); +signal tlast_buffer : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +bypass_gen: if ((C_IN_TYPE = 1) and (C_OUT_TYPE = 1))generate +begin + m_axis_tvalid <= s_axis_tvalid; + m_axis_tdata <= s_axis_tdata; + m_axis_tuser <= s_axis_tuser; + m_axis_tlast <= s_axis_tlast; + s_axis_tready <= m_axis_tready; +end generate; +---------------------------------------------------------------------------------- +repack_gen: if ((C_IN_TYPE /= 1) or (C_OUT_TYPE /= 1)) generate +begin + process(sm_state, s_axis_tvalid) + begin + case sm_state is + when ST_IDLE => m_axis_tvalid <= s_axis_tvalid; + when ST_1W => m_axis_tvalid <= '1'; + when ST_2W => m_axis_tvalid <= '1'; + when ST_3W => m_axis_tvalid <= '1'; + end case; + end process; + + process(sm_state, s_axis_tuser) + begin + case sm_state is + when ST_IDLE => m_axis_tuser <= s_axis_tuser; + when ST_1W => m_axis_tuser <= '0'; + when ST_2W => m_axis_tuser <= '0'; + when ST_3W => m_axis_tuser <= '0'; + end case; + end process; + + process(sm_state, s_axis_tuser) + begin + case sm_state is + when ST_IDLE => m_axis_tlast <= '0'; + when ST_1W => + if(C_OUT_TYPE = 2)then + m_axis_tlast <= tlast_buffer; + else + m_axis_tlast <= '0'; + end if; + when ST_2W => m_axis_tlast <= '0'; + when ST_3W => m_axis_tlast <= tlast_buffer; + end case; + end process; + + out_1p_gen: if C_OUT_TYPE = 1 generate + begin + process(sm_state, s_axis_tdata, tdata_buffer) + begin + case sm_state is + when ST_IDLE => m_axis_tdata <= s_axis_tdata(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + when ST_1W => m_axis_tdata <= tdata_buffer(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + when ST_2W => m_axis_tdata <= tdata_buffer(C_OUT_TYPE*C_DATA_WIDTH*2-1 downto C_OUT_TYPE*C_DATA_WIDTH*1); + when ST_3W => m_axis_tdata <= tdata_buffer(C_OUT_TYPE*C_DATA_WIDTH*3-1 downto C_OUT_TYPE*C_DATA_WIDTH*2); + end case; + end process; + end generate; + + out_2p_gen: if C_OUT_TYPE = 2 generate + begin + process(sm_state, s_axis_tdata, tdata_buffer) + begin + case sm_state is + when ST_IDLE => m_axis_tdata <= s_axis_tdata(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + when ST_1W => m_axis_tdata <= tdata_buffer(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + when others => null; + end case; + end process; + end generate; + + process(axis_aclk) + begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_state is + when ST_IDLE => + if((s_axis_tvalid = '1') and (m_axis_tready = '1'))then + tdata_buffer <= s_axis_tdata(s_axis_tdata'left downto C_OUT_TYPE*C_DATA_WIDTH); + tlast_buffer <= s_axis_tlast; + sm_state <= ST_1W; + end if; + when ST_1W => + if(m_axis_tready = '1')then + if(C_OUT_TYPE = 2)then + sm_state <= ST_IDLE; + else + sm_state <= ST_2W; + end if; + end if; + when ST_2W => + if(m_axis_tready = '1')then + sm_state <= ST_3W; + end if; + when ST_3W => + if(m_axis_tready = '1')then + sm_state <= ST_IDLE; + end if; + end case; + end if; + end process; + + s_axis_tready <= m_axis_tready when sm_state = ST_IDLE else '0'; +end generate; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/xgui/axis_video_dwidth_converter_v1_0.tcl b/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/xgui/axis_video_dwidth_converter_v1_0.tcl new file mode 100644 index 0000000..6b5cb6a --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_video_dwidth_converter_1.0/xgui/axis_video_dwidth_converter_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_IN_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_OUT_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_DATA_WIDTH" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_DATA_WIDTH { PARAM_VALUE.C_DATA_WIDTH } { + # Procedure called to update C_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_DATA_WIDTH { PARAM_VALUE.C_DATA_WIDTH } { + # Procedure called to validate C_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to update C_IN_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to validate C_IN_TYPE + return true +} + +proc update_PARAM_VALUE.C_OUT_TYPE { PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to update C_OUT_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_OUT_TYPE { PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to validate C_OUT_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.C_IN_TYPE { MODELPARAM_VALUE.C_IN_TYPE PARAM_VALUE.C_IN_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IN_TYPE}] ${MODELPARAM_VALUE.C_IN_TYPE} +} + +proc update_MODELPARAM_VALUE.C_OUT_TYPE { MODELPARAM_VALUE.C_OUT_TYPE PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_OUT_TYPE}] ${MODELPARAM_VALUE.C_OUT_TYPE} +} + +proc update_MODELPARAM_VALUE.C_DATA_WIDTH { MODELPARAM_VALUE.C_DATA_WIDTH PARAM_VALUE.C_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_DATA_WIDTH}] ${MODELPARAM_VALUE.C_DATA_WIDTH} +} + diff --git a/zynqberrydemo1/ip_lib/axis_video_resize_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/axis_video_resize_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_video_resize_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/axis_video_resize_1.0/component.xml b/zynqberrydemo1/ip_lib/axis_video_resize_1.0/component.xml new file mode 100644 index 0000000..8183acb --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_video_resize_1.0/component.xml @@ -0,0 +1,521 @@ + + + trenz.biz + user + axis_video_resize + 1.0 + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TUSER + + + s_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + TUSER + + + m_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + axis_aresetn + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_aclk + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS:M_AXIS + + + ASSOCIATED_RESET + axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_video_resize_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 3d0341d7 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_video_resize_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 3d0341d7 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b9a712e9 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + s_axis_tdata + + in + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_HORISONTAL_RES + C Horisontal Res + 1280 + + + C_VERTICAL_RES + C Vertical Res + 720 + + + C_IN_TYPE + C In Type + 1 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_719c03b1 + 1 + 4 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axis_video_resize_v1_0.vhd + vhdlSource + CHECKSUM_3d0341d7 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axis_video_resize_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_video_resize_v1_0.tcl + tclSource + CHECKSUM_ea8138be + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + Resize video stream + + + Component_Name + axis_video_resize_v1_0 + + + C_HORISONTAL_RES + Horisontal Resolution + 1280 + + + C_VERTICAL_RES + Vertical Resolution + 720 + + + C_IN_TYPE + Input Type + 1 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /AXI_Peripheral + /Video_&_Image_Processing + + Video Resize v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 5 + + xilinx.com:user:axis_video_resize:1.0 + + 2017-05-16T12:54:08Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_video_resize_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_video_resize_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/axis_video_resize_1.0/hdl/axis_video_resize_v1_0.vhd b/zynqberrydemo1/ip_lib/axis_video_resize_1.0/hdl/axis_video_resize_v1_0.vhd new file mode 100644 index 0000000..a70a46e --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_video_resize_1.0/hdl/axis_video_resize_v1_0.vhd @@ -0,0 +1,115 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity axis_video_resize_v1_0 is +generic ( + C_IN_TYPE : integer range 1 to 4 := 1; + C_HORISONTAL_RES : integer := 1280; + C_VERTICAL_RES : integer := 720 +); +port ( + axis_aclk : in STD_LOGIC; + axis_aresetn : in STD_LOGIC; + -- Ports of Axi Slave Bus Interface S_AXIS + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_IN_TYPE*32-1 downto 0); + s_axis_tuser : in STD_LOGIC; + s_axis_tlast : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + + -- Ports of Axi Master Bus Interface M_AXIS + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_IN_TYPE*32-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC + ); +end axis_video_resize_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_video_resize_v1_0 is +---------------------------------------------------------------------------------- +signal hor_cnt : UNSIGNED(15 downto 0); +signal ver_cnt : UNSIGNED(15 downto 0); +type sm_state_type is (ST_IDLE, ST_HOR_LINE, ST_HOR_CROP); +signal sm_state : sm_state_type := ST_IDLE; +signal vert_pass : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +s_axis_tready <= m_axis_tready; +m_axis_tdata <= s_axis_tdata; +m_axis_tuser <= s_axis_tuser; +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_state is + when ST_IDLE => -- Wait for start of frame + vert_pass <= '1'; + ver_cnt <= TO_UNSIGNED(0,16); + hor_cnt <= TO_UNSIGNED(C_IN_TYPE,16); + if((s_axis_tvalid = '1') and (m_axis_tready = '1') and (s_axis_tuser = '1'))then + sm_state <= ST_HOR_LINE; + end if; + when ST_HOR_LINE => + if((s_axis_tvalid = '1') and (m_axis_tready = '1'))then + if(s_axis_tuser = '1')then + ver_cnt <= TO_UNSIGNED(0,16); + vert_pass <= '1'; + elsif(s_axis_tlast = '1')then + if(ver_cnt >= TO_UNSIGNED((C_VERTICAL_RES-1),16))then + vert_pass <= '0'; + end if; + ver_cnt <= ver_cnt + 1; + end if; + + if(s_axis_tlast = '1')then + hor_cnt <= TO_UNSIGNED(0,16); + else + if(hor_cnt >= TO_UNSIGNED((C_HORISONTAL_RES - C_IN_TYPE),16))then + sm_state <= ST_HOR_CROP; + end if; + hor_cnt <= hor_cnt + TO_UNSIGNED(C_IN_TYPE, 16); + end if; + end if; + when ST_HOR_CROP => + if((s_axis_tvalid = '1') and (m_axis_tready = '1') and (s_axis_tlast = '1'))then + hor_cnt <= TO_UNSIGNED(0,16); + sm_state <= ST_HOR_LINE; + if(ver_cnt >= TO_UNSIGNED((C_VERTICAL_RES-1),16))then + vert_pass <= '0'; + end if; + ver_cnt <= ver_cnt + 1; + end if; + end case; + end if; +end process; + +process(sm_state, s_axis_tvalid, s_axis_tuser, vert_pass) +begin + case sm_state is + when ST_IDLE => m_axis_tvalid <= s_axis_tvalid and s_axis_tuser; + when ST_HOR_LINE => m_axis_tvalid <= s_axis_tvalid and (vert_pass or s_axis_tuser); + when ST_HOR_CROP => m_axis_tvalid <= '0'; + end case; +end process; + +process(sm_state, hor_cnt) +begin + case sm_state is + when ST_IDLE => m_axis_tlast <= '0'; + when ST_HOR_LINE => + if(hor_cnt >= TO_UNSIGNED((C_HORISONTAL_RES - C_IN_TYPE),16))then + m_axis_tlast <= '1'; + else + m_axis_tlast <= '0'; + end if; + when ST_HOR_CROP => m_axis_tlast <= '0'; + end case; +end process; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/axis_video_resize_1.0/xgui/axis_video_resize_v1_0.tcl b/zynqberrydemo1/ip_lib/axis_video_resize_1.0/xgui/axis_video_resize_v1_0.tcl new file mode 100644 index 0000000..75490a1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/axis_video_resize_1.0/xgui/axis_video_resize_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_IN_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_HORISONTAL_RES" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_VERTICAL_RES" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_HORISONTAL_RES { PARAM_VALUE.C_HORISONTAL_RES } { + # Procedure called to update C_HORISONTAL_RES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_HORISONTAL_RES { PARAM_VALUE.C_HORISONTAL_RES } { + # Procedure called to validate C_HORISONTAL_RES + return true +} + +proc update_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to update C_IN_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to validate C_IN_TYPE + return true +} + +proc update_PARAM_VALUE.C_VERTICAL_RES { PARAM_VALUE.C_VERTICAL_RES } { + # Procedure called to update C_VERTICAL_RES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_VERTICAL_RES { PARAM_VALUE.C_VERTICAL_RES } { + # Procedure called to validate C_VERTICAL_RES + return true +} + + +proc update_MODELPARAM_VALUE.C_HORISONTAL_RES { MODELPARAM_VALUE.C_HORISONTAL_RES PARAM_VALUE.C_HORISONTAL_RES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_HORISONTAL_RES}] ${MODELPARAM_VALUE.C_HORISONTAL_RES} +} + +proc update_MODELPARAM_VALUE.C_VERTICAL_RES { MODELPARAM_VALUE.C_VERTICAL_RES PARAM_VALUE.C_VERTICAL_RES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_VERTICAL_RES}] ${MODELPARAM_VALUE.C_VERTICAL_RES} +} + +proc update_MODELPARAM_VALUE.C_IN_TYPE { MODELPARAM_VALUE.C_IN_TYPE PARAM_VALUE.C_IN_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IN_TYPE}] ${MODELPARAM_VALUE.C_IN_TYPE} +} + diff --git a/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/component.xml b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/component.xml new file mode 100644 index 0000000..c91798f --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/component.xml @@ -0,0 +1,1035 @@ + + + trenz.biz + user + csi2_d_phy_rx + 1.0 + + + RX_MIPI_PPI + RX_MIPI_PPI + RX_MIPI_PPI + + + + + + + DL1_RXACTIVEHS + + + dl1_rxactivehs + + + + + CL_ENABLE + + + cl_enable + + + + + DL1_RXDATAHS + + + dl1_datahs + + + + + CL_STOPSTATE + + + cl_stopstate + + + + + DL0_RXSYNCHS + + + dl0_rxsynchs + + + + + DL1_RXVALIDHS + + + dl1_rxvalidhs + + + + + DL0_RXACTIVEHS + + + dl0_rxactivehs + + + + + DL1_RXSYNCHS + + + dl1_rxsynchs + + + + + CL_RXCLKACTIVEHS + + + cl_rxclkactivehs + + + + + DL0_ENABLE + + + dl0_enable + + + + + DL0_RXDATAHS + + + dl0_datahs + + + + + DL1_ENABLE + + + dl1_enable + + + + + DL0_RXVALIDHS + + + dl0_rxvalidhs + + + + + DL2_RXSYNCHS + + + dl2_rxsynchs + + + + + DL3_RXACTIVEHS + + + dl3_rxactivehs + + + + + DL3_RXDATAHS + + + dl3_datahs + + + + + DL2_RXDATAHS + + + dl2_datahs + + + + + DL3_RXSYNCHS + + + dl3_rxsynchs + + + + + DL3_RXVALIDHS + + + dl3_rxvalidhs + + + + + DL3_ENABLE + + + dl3_enable + + + + + DL2_RXVALIDHS + + + dl2_rxvalidhs + + + + + DL2_RXACTIVEHS + + + dl2_rxactivehs + + + + + DL2_ENABLE + + + dl2_enable + + + + + + in_delay_clk + + + + + + + CLK + + + in_delay_clk + + + + + + data_err + + + + + + + ACK + + + trig_ack + + + + + TRIG + + + trig_req + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + csi2_d_phy_rx + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 705bfa8d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + csi2_d_phy_rx + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f9df0448 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b6781f17 + + + + + + + in_delay_clk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + clk_rxp + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_rxn + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_rxp + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_rxn + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_lp_p + + in + + 0 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + true + + + + + + data_lp_n + + in + + 0 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + true + + + + + + trig_req + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + trig_ack + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rxbyteclkhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cl_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + cl_stopstate + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cl_rxclkactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl0_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + dl0_rxactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl0_rxvalidhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl0_rxsynchs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl0_datahs + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl1_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + dl1_rxactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl1_rxvalidhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl1_rxsynchs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl1_datahs + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl2_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + dl2_rxactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl2_rxvalidhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl2_rxsynchs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl2_datahs + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl3_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + dl3_rxactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl3_rxvalidhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl3_rxsynchs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl3_datahs + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_NUM_LANES + C Num Lanes + 2 + + + C_NUM_LP_LANES + C Num Lp Lanes + 1 + + + C_D0_SWAP + C D0 Swap + FALSE + + + C_D1_SWAP + C D1 Swap + FALSE + + + C_D2_SWAP + C D2 Swap + FALSE + + + C_D3_SWAP + C D3 Swap + FALSE + + + C_DIFF_TERM + C Diff Term + FALSE + + + C_ADD_IDELAYCTRL + C Add Idelayctrl + FALSE + + + C_IODELAY_GROUP + C Iodelay Group + csi_dly_grp + + + C_USE_DELAY + C Use Delay + TRUE + + + C_CALIB_WAIT + C Calib Wait + 2047 + + + C_RATE_LIMIT + C Rate Limit + 10 + + + + + + choice_list_e6469819 + 1 + 2 + 4 + + + choice_list_f5166eba + 0 + 1 + 2 + 4 + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/csi2_d_phy_rx.xdc + xdc + USED_IN_implementation + USED_IN_synthesis + + + hdl/phy_clock_system.vhd + vhdlSource + + + hdl/line_if.vhd + vhdlSource + + + hdl/csi2_d_phy_rx.vhd + vhdlSource + CHECKSUM_8021b24b + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/phy_clock_system.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/line_if.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/csi2_d_phy_rx.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/csi2_d_phy_rx_v1_0.tcl + tclSource + CHECKSUM_30433af4 + XGUI_VERSION_2 + + + + CSI-2 D-PHY RX Interface + + + C_NUM_LANES + Data Lanes + 2 + + + C_NUM_LP_LANES + LP Lanes + 1 + + + C_D0_SWAP + D0 P/N Swap + FALSE + + + C_D1_SWAP + D1 P/N Swap + FALSE + + + C_D2_SWAP + D2 P/N Swap + FALSE + + + C_D3_SWAP + D3 P/N Swap + FALSE + + + C_DIFF_TERM + Add Differential Termination + FALSE + + + C_ADD_IDELAYCTRL + Add Idelayctrl + FALSE + + + C_IODELAY_GROUP + Iodelay Group Name + csi_dly_grp + + + Component_Name + csi2_d_phy_rx_v1_0 + + + C_USE_DELAY + Use Delay + TRUE + + + C_CALIB_WAIT + Calibration Cycle + 2047 + + + C_RATE_LIMIT + Error Rate Limit + 10 + + + + + + virtex7 + artix7 + kintex7 + zynq + qzynq + + + /UserIP + /Video_&_Image_Processing + + CSI-2 D-PHY RX v1_0 + Trenz Electronic GmbH + http://www.trenz.biz + 35 + + xilinx.com:user:csi2_d_phy_rx:1.0 + + 2017-05-24T13:20:36Z + + + b:/cores/2015.4/design/te0726/demo/ip_lib/csi2_d_phy_rx_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/csi2_d_phy_rx_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.vhd b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.vhd new file mode 100644 index 0000000..0d0bf83 --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.vhd @@ -0,0 +1,293 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; +Library UNISIM; +use UNISIM.vcomponents.all; +---------------------------------------------------------------------------------- +entity csi2_d_phy_rx is +generic ( + C_NUM_LANES : integer range 1 to 4 := 2; -- Number of data lanes + C_NUM_LP_LANES : integer range 0 to 4 := 1; -- Number of lanes that support LP input + C_D0_SWAP : BOOLEAN := FALSE; + C_D1_SWAP : BOOLEAN := FALSE; + C_D2_SWAP : BOOLEAN := FALSE; + C_D3_SWAP : BOOLEAN := FALSE; + ------------------------------------------------------------------------------- + C_USE_DELAY : BOOLEAN := TRUE; + C_DIFF_TERM : BOOLEAN := FALSE; + C_ADD_IDELAYCTRL : BOOLEAN := FALSE; + C_IODELAY_GROUP : STRING := "csi_dly_grp"; + C_CALIB_WAIT : INTEGER := 2047; + C_RATE_LIMIT : INTEGER := 10 +); +port ( + in_delay_clk : in STD_LOGIC; + -- Camera physical interface + clk_rxp : in STD_LOGIC; + clk_rxn : in STD_LOGIC; + data_rxp : in STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); + data_rxn : in STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); + data_lp_p : in STD_LOGIC_VECTOR(C_NUM_LP_LANES-1 downto 0); + data_lp_n : in STD_LOGIC_VECTOR(C_NUM_LP_LANES-1 downto 0); + -- Calibration + trig_req : in STD_LOGIC; + trig_ack : out STD_LOGIC; + -- MIPI PPI + rxbyteclkhs : out STD_LOGIC; -- Main byte clock bitrate/8 + cl_enable : in STD_LOGIC := '1'; -- PPI ShutDown ? + cl_stopstate : out STD_LOGIC; -- PPI StopState + cl_rxclkactivehs : out STD_LOGIC; -- optional, PPI RxClkActiveHS + dl0_enable : in STD_LOGIC; + dl0_rxactivehs : out STD_LOGIC; + dl0_rxvalidhs : out STD_LOGIC; + dl0_rxsynchs : out STD_LOGIC; + dl0_datahs : out STD_LOGIC_VECTOR(7 downto 0); + dl1_enable : in STD_LOGIC; + dl1_rxactivehs : out STD_LOGIC; + dl1_rxvalidhs : out STD_LOGIC; + dl1_rxsynchs : out STD_LOGIC; + dl1_datahs : out STD_LOGIC_VECTOR(7 downto 0); + dl2_enable : in STD_LOGIC; + dl2_rxactivehs : out STD_LOGIC; + dl2_rxvalidhs : out STD_LOGIC; + dl2_rxsynchs : out STD_LOGIC; + dl2_datahs : out STD_LOGIC_VECTOR(7 downto 0); + dl3_enable : in STD_LOGIC; + dl3_rxactivehs : out STD_LOGIC; + dl3_rxvalidhs : out STD_LOGIC; + dl3_rxsynchs : out STD_LOGIC; + dl3_datahs : out STD_LOGIC_VECTOR(7 downto 0) +); +end csi2_d_phy_rx; +---------------------------------------------------------------------------------- +architecture Behavioral of csi2_d_phy_rx is +---------------------------------------------------------------------------------- +component phy_clock_system is +generic ( + C_USE_DELAY : BOOLEAN := FALSE; + C_DIFF_TERM : BOOLEAN := FALSE; + C_IODELAY_GROUP : STRING := "csi_dly_grp"; + C_CALIB_WAIT : INTEGER := 2047; + C_ACC_LIMIT : INTEGER := 100000; + C_RATE_LIMIT : INTEGER := 5 +); +port ( + clock_upd_req : in STD_LOGIC; + clock_upd_ack : out STD_LOGIC; + in_clk_p : in STD_LOGIC; + in_clk_n : in STD_LOGIC; + in_ref_clk : in STD_LOGIC; + out_dclk : out STD_LOGIC; + out_pclk : out STD_LOGIC; + out_uclk : out STD_LOGIC +); +end component; + +component line_if is +generic ( + C_DIFF_TERM : BOOLEAN := FALSE +); +port ( + in_d_p : in STD_LOGIC; + in_d_n : in STD_LOGIC; + in_pclk : in STD_LOGIC; + in_dclk : in STD_LOGIC; + in_rst : in STD_LOGIC; + out_data : out STD_LOGIC_VECTOR(7 downto 0) +); +end component; +---------------------------------------------------------------------------------- +constant C_ACC_LIMIT : INTEGER := 1000000; +attribute IODELAY_GROUP : STRING; +signal rst_iserdes : STD_LOGIC; +signal dclk : STD_LOGIC; +signal pclk : STD_LOGIC; +signal uclk : STD_LOGIC; +signal prev_raw_valid : STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); +signal line_raw_sync : STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); +signal line_raw_out : STD_LOGIC_VECTOR(C_NUM_LANES*8-1 downto 0); +signal raw_valid : STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); +signal raw_fe_data : STD_LOGIC_VECTOR(C_NUM_LANES*8-1 downto 0); +signal raw_fe_valid : STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); +signal swap_vec : STD_LOGIC_VECTOR(3 downto 0); +signal clock_upd_req : STD_LOGIC; +signal clock_upd_ack : STD_LOGIC; +signal data_err_i : UNSIGNED(C_NUM_LANES-1 downto 0); +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +swap_vec(0) <= '1' when C_D0_SWAP = TRUE else '0'; +swap_vec(1) <= '1' when C_D1_SWAP = TRUE else '0'; +swap_vec(2) <= '1' when C_D2_SWAP = TRUE else '0'; +swap_vec(3) <= '1' when C_D3_SWAP = TRUE else '0'; +---------------------------------------------------------------------------------- +IDELAYCTRL_gen: if (C_ADD_IDELAYCTRL = TRUE) and (C_USE_DELAY = TRUE) generate +attribute IODELAY_GROUP of IdlyCtrl_inst_0 : label is C_IODELAY_GROUP; +begin + IdlyCtrl_inst_0 : IDELAYCTRL + port map ( + REFCLK => in_delay_clk, + RST => '0', + RDY => open + ); +end generate; +---------------------------------------------------------------------------------- +process(in_delay_clk) +begin + if(in_delay_clk = '1' and in_delay_clk'event)then + clock_upd_req <= trig_req; + end if; +end process; +---------------------------------------------------------------------------------- +clock_system_inst: phy_clock_system +generic map( + C_USE_DELAY => C_USE_DELAY, + C_DIFF_TERM => C_DIFF_TERM, + C_IODELAY_GROUP => C_IODELAY_GROUP, + C_CALIB_WAIT => C_CALIB_WAIT, + C_ACC_LIMIT => C_ACC_LIMIT, + C_RATE_LIMIT => C_RATE_LIMIT +) +port map( + clock_upd_req => clock_upd_req, + clock_upd_ack => clock_upd_ack, + in_clk_p => clk_rxp, + in_clk_n => clk_rxn, + in_ref_clk => in_delay_clk, + out_dclk => dclk, + out_pclk => pclk, + out_uclk => uclk +); +rst_iserdes <= '0'; + +bits_gen: for i in 0 to C_NUM_LANES-1 generate +begin + line_if_inst: line_if + generic map( + C_DIFF_TERM => C_DIFF_TERM + ) + port map( + in_d_p => data_rxp(i), + in_d_n => data_rxn(i), + in_pclk => pclk, + in_dclk => dclk, + in_rst => rst_iserdes, + out_data => line_raw_out(i*8+7 downto i*8) + ); +end generate; + +without_lp_gen: if C_NUM_LP_LANES = 0 generate +begin + raw_valid <= (others => '1'); + line_raw_sync <= (others => '0'); +end generate; + +with_lp_gen: if C_NUM_LP_LANES > 0 generate +begin +process(pclk) +begin + if(pclk = '1' and pclk'event)then + for i in 0 to C_NUM_LP_LANES-1 loop + raw_valid(i) <= not (data_lp_p(i) or data_lp_n(i)); + prev_raw_valid(i) <= raw_valid(i); + if((prev_raw_valid(i) = '0') and ((data_lp_p(i) or data_lp_n(i)) = '0'))then + line_raw_sync(i) <= '1'; + else + line_raw_sync(i) <= '0'; + end if; + end loop; + end if; +end process; + +ext_lp_gen: if C_NUM_LP_LANES < C_NUM_LANES generate +begin + process(pclk) + begin + if(pclk = '1' and pclk'event)then + for i in C_NUM_LP_LANES to C_NUM_LANES-1 loop + raw_valid(i) <= not (data_lp_p(0) or data_lp_n(0)); + prev_raw_valid(i) <= raw_valid(i); + if((prev_raw_valid(i) = '0') and ((data_lp_p(0) or data_lp_n(0)) = '0'))then + line_raw_sync(i) <= '1'; + else + line_raw_sync(i) <= '0'; + end if; + end loop; + end if; + end process; +end generate; +end generate; + +process(uclk) +begin + if(uclk = '0' and uclk'event)then + for i in 0 to C_NUM_LANES-1 loop + if(swap_vec(i) = '0')then + raw_fe_data(i*8+7 downto i*8) <= line_raw_out(i*8+7 downto i*8); + else + raw_fe_data(i*8+7 downto i*8) <= not line_raw_out(i*8+7 downto i*8); + end if; + end loop; + raw_fe_valid <= raw_valid; + end if; +end process; + +process(uclk) +begin + if(uclk = '1' and uclk'event)then + dl0_rxvalidhs <= raw_fe_valid(0); + dl0_rxactivehs <= raw_fe_valid(0); + dl0_datahs <= raw_fe_data(7 downto 0); + dl0_rxsynchs <= line_raw_sync(0); + end if; +end process; + +lane_1_gen: if C_NUM_LANES > 1 generate +begin + process(uclk) + begin + if(uclk = '1' and uclk'event)then + dl1_rxvalidhs <= raw_fe_valid(1); + dl1_rxactivehs <= raw_fe_valid(1); + dl1_datahs <= raw_fe_data(15 downto 8); + dl1_rxsynchs <= line_raw_sync(1); + end if; + end process; +end generate; + +lane_2_gen: if C_NUM_LANES > 2 generate +begin + process(uclk) + begin + if(uclk = '1' and uclk'event)then + dl2_rxvalidhs <= raw_fe_valid(2); + dl2_rxactivehs <= raw_fe_valid(2); + dl2_datahs <= raw_fe_data(23 downto 16); + dl2_rxsynchs <= line_raw_sync(2); + end if; + end process; +end generate; + +lane_3_gen: if C_NUM_LANES > 3 generate +begin + process(uclk) + begin + if(uclk = '1' and uclk'event)then + dl3_rxvalidhs <= raw_fe_valid(3); + dl3_rxactivehs <= raw_fe_valid(3); + dl3_datahs <= raw_fe_data(31 downto 24); + dl3_rxsynchs <= line_raw_sync(3); + end if; + end process; +end generate; + +rxbyteclkhs <= uclk; -- Main byte clock bitrate/8 +cl_stopstate <= '0'; -- PPI StopState +cl_rxclkactivehs <= '1'; -- optional, PPI RxClkActiveHS +---------------------------------------------------------------------------------- +end Behavioral; + diff --git a/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.xdc b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.xdc new file mode 100644 index 0000000..c7c796f --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.xdc @@ -0,0 +1,4 @@ +set_false_path -from [get_pins clock_system_inst/invers_clk_s_reg/C] -to [get_pins clock_system_inst/dly_gen.BUFGCTRL_inst/S1] +set_false_path -from [get_pins clock_system_inst/invers_clk_c_reg/C] -to [get_pins clock_system_inst/dly_gen.BUFGCTRL_inst/CE1] +set_false_path -from [get_pins clock_system_inst/direct_clk_s_reg/C] -to [get_pins clock_system_inst/dly_gen.BUFGCTRL_inst/S0] +set_false_path -from [get_pins clock_system_inst/direct_clk_c_reg/C] -to [get_pins clock_system_inst/dly_gen.BUFGCTRL_inst/CE0] diff --git a/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/line_if.vhd b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/line_if.vhd new file mode 100644 index 0000000..0e879fb --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/line_if.vhd @@ -0,0 +1,97 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity line_if is +generic ( + C_DIFF_TERM : BOOLEAN := FALSE +); +port ( + in_d_p : in STD_LOGIC; + in_d_n : in STD_LOGIC; + in_pclk : in STD_LOGIC; + in_dclk : in STD_LOGIC; + in_rst : in STD_LOGIC; + out_data : out STD_LOGIC_VECTOR(7 downto 0) +); +end line_if; +---------------------------------------------------------------------------------- +architecture arch_imp of line_if is +---------------------------------------------------------------------------------- +signal data_s : STD_LOGIC; +signal data_iserdes : STD_LOGIC_VECTOR(7 downto 0); +signal dclk_n : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +d_ibufds_inst : IBUFDS +generic map ( + DIFF_TERM => C_DIFF_TERM +) +port map ( + I => in_d_p, + IB => in_d_n, + O => data_s +); + +dclk_n <= not in_dclk; +ISERDESE2_inst : ISERDESE2 +generic map ( + DATA_RATE => "DDR", -- DDR, SDR + DATA_WIDTH => 8, -- Parallel data width (2-8,10,14) + DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE) + DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE) + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "NETWORKING", -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE + IOBDELAY => "NONE", -- NONE, BOTH, IBUF, IFD + NUM_CE => 2, -- Number of clock enables (1,2) + OFB_USED => "FALSE", -- Select OFB path (FALSE, TRUE) + SERDES_MODE => "MASTER", -- MASTER, SLAVE + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' +) +port map ( + O => open, -- 1-bit output: Combinatorial output + Q1 => data_iserdes(7), + Q2 => data_iserdes(6), + Q3 => data_iserdes(5), + Q4 => data_iserdes(4), + Q5 => data_iserdes(3), + Q6 => data_iserdes(2), + Q7 => data_iserdes(1), + Q8 => data_iserdes(0), + SHIFTOUT1 => open, + SHIFTOUT2 => open, + BITSLIP => '0', -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to + CE1 => '1', + CE2 => '1', + CLKDIVP => '0', -- 1-bit input: TBD + CLK => in_dclk, -- 1-bit input: High-speed clock + CLKB => dclk_n, -- 1-bit input: High-speed secondary clock + CLKDIV => in_pclk, -- 1-bit input: Divided clock + OCLK => '0', -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" + DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion + DYNCLKSEL => '0', -- 1-bit input: Dynamic CLK/CLKB inversion + D => data_s, -- 1-bit input: Data input + DDLY => '0', -- 1-bit input: Serial data from IDELAYE2 + OFB => '0', -- 1-bit input: Data feedback from OSERDESE2 + OCLKB => '0', -- 1-bit input: High speed negative edge output clock + RST => in_rst, -- 1-bit input: Active high asynchronous reset + SHIFTIN1 => '0', + SHIFTIN2 => '0' +); + +out_data <= data_iserdes; +--------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/phy_clock_system.vhd b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/phy_clock_system.vhd new file mode 100644 index 0000000..942a2c1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/hdl/phy_clock_system.vhd @@ -0,0 +1,316 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity phy_clock_system is +generic ( + C_USE_DELAY : BOOLEAN := FALSE; + C_DIFF_TERM : BOOLEAN := FALSE; + C_IDELAY_TYPE : STRING := "FIXED"; + C_IODELAY_GROUP : STRING := "csi_dly_grp"; + C_ACC_LIMIT : INTEGER := 100000; + C_RATE_LIMIT : INTEGER := 5; + C_CALIB_WAIT : INTEGER := 2047 +); +port ( + -- Debug + --cntvalue_out : out STD_LOGIC_VECTOR(4 downto 0); + --state_out : out STD_LOGIC_VECTOR(3 downto 0); + + clock_upd_req : in STD_LOGIC; + clock_upd_ack : out STD_LOGIC; + in_clk_p : in STD_LOGIC; + in_clk_n : in STD_LOGIC; + in_ref_clk : in STD_LOGIC; + out_dclk : out STD_LOGIC; + out_pclk : out STD_LOGIC; + out_uclk : out STD_LOGIC +); +end phy_clock_system; +---------------------------------------------------------------------------------- +architecture arch_imp of phy_clock_system is +---------------------------------------------------------------------------------- +attribute IODELAY_GROUP : STRING; +---------------------------------------------------------------------------------- +signal clk_g : STD_LOGIC; -- Clock after IBUFGDS +signal clk_d : STD_LOGIC; -- Clock after IDELAYE2 +signal clk_dn : STD_LOGIC; -- Clock after IDELAYE2 +signal clk_dg : STD_LOGIC; -- Clock after IBUFGDS +signal clk_bufmr : STD_LOGIC; +signal clk_bufio : STD_LOGIC; +signal clk_bufr : STD_LOGIC; +signal rst_bufmr : STD_LOGIC; +type sm_state_type is (ST_CHECK, ST_FIND_GOOD, ST_GOOD_WAIT, + ST_FIND_BAD, ST_BAD_WAIT, ST_CALK_DLY, ST_SET_DLY, ST_SET_WAIT); +signal sm_state : sm_state_type; +signal wait_cnt : integer range 0 to C_CALIB_WAIT; +signal delay_ce : STD_LOGIC; +signal delay_rst : STD_LOGIC; +signal delay_set : STD_LOGIC; +signal delay_set_val : STD_LOGIC_VECTOR(4 downto 0); +signal curr_delay : UNSIGNED(4 downto 0); +signal start_dly : UNSIGNED(5 downto 0); +signal end_dly : UNSIGNED(5 downto 0); +signal sum_dly : UNSIGNED(5 downto 0); +signal invers_clk : STD_LOGIC := '0'; +signal direct_clk : STD_LOGIC := '1'; +signal direct_clk_s : STD_LOGIC; +signal invers_clk_s : STD_LOGIC := '0'; +signal direct_clk_c : STD_LOGIC; +signal invers_clk_c : STD_LOGIC := '0'; +signal req_i : STD_LOGIC; +signal err_sr : STD_LOGIC_VECTOR(1 downto 0); +signal acc_cnt : INTEGER range 0 to C_ACC_LIMIT-1; +signal acc_val : INTEGER range 0 to C_ACC_LIMIT-1; +signal err_rate : INTEGER range 0 to C_ACC_LIMIT-1; +---------------------------------------------------------------------------------- +attribute ASYNC_REG : string; +attribute ASYNC_REG of req_i : signal is "true"; +attribute keep : string; +attribute keep of direct_clk_s : signal is "true"; +attribute keep of direct_clk_c : signal is "true"; +attribute keep of invers_clk_s : signal is "true"; +attribute keep of invers_clk_c : signal is "true"; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +-- Test +clk_ibufgds_inst : IBUFGDS +generic map ( + DIFF_TERM => C_DIFF_TERM +) +port map ( + I => in_clk_p, + IB => in_clk_n, + O => clk_g +); + +process(in_ref_clk) +begin + if(in_ref_clk = '1' and in_ref_clk'event)then + direct_clk_s <= not invers_clk; + invers_clk_s <= invers_clk; + direct_clk_c <= not invers_clk; + invers_clk_c <= invers_clk; + end if; +end process; +--direct_clk <= not invers_clk; + +dly_gen: if C_USE_DELAY = TRUE generate +attribute IODELAY_GROUP of IDELAYE2_inst : label is C_IODELAY_GROUP; +begin + IDELAYE2_inst : IDELAYE2 + generic map ( + CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE) + DELAY_SRC => "IDATAIN", -- Delay input (IDATAIN, DATAIN) + HIGH_PERFORMANCE_MODE => "TRUE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE") + IDELAY_TYPE => "VAR_LOAD", -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE + IDELAY_VALUE => 0, -- Input delay tap setting (0-31) + PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE + REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0). + SIGNAL_PATTERN => "CLOCK" -- DATA, CLOCK input signal + ) + port map ( + --CNTVALUEOUT => cntvalue_out,-- 5-bit output: Counter value output + CNTVALUEOUT => open, -- 5-bit output: Counter value output + DATAOUT => clk_d, -- 1-bit output: Delayed data output + C => in_ref_clk, -- 1-bit input: Clock input + CE => '0', -- 1-bit input: Active high enable increment/decrement input + CINVCTRL => '0', -- 1-bit input: Dynamic clock inversion input + CNTVALUEIN => delay_set_val, -- 5-bit input: Counter value input + DATAIN => '0', -- 1-bit input: Internal delay data input + IDATAIN => clk_g, -- 1-bit input: Data input from the I/O + INC => '1', -- 1-bit input: Increment / Decrement tap delay input + LD => delay_set, -- 1-bit input: Load IDELAY_VALUE input + LDPIPEEN => '0', -- 1-bit input: Enable PIPELINE register to load data input + REGRST => '0' -- 1-bit input: Active-high reset tap-delay input + ); + clk_dn <= not clk_d; + + BUFGCTRL_inst : BUFGCTRL + generic map ( + INIT_OUT => 0, -- Initial value of BUFGCTRL output (0/1) + PRESELECT_I0 => FALSE, -- BUFGCTRL output uses I0 input (TRUE/FALSE) + PRESELECT_I1 => FALSE -- BUFGCTRL output uses I1 input (TRUE/FALSE) + ) + port map ( + O => clk_dg, -- 1-bit output: Clock Output pin + CE0 => direct_clk_c, -- 1-bit input: Clock enable input for I0 input + CE1 => invers_clk_c, -- 1-bit input: Clock enable input for I1 input + I0 => clk_d, -- 1-bit input: Primary clock input + I1 => clk_dn, -- 1-bit input: Secondary clock input + IGNORE0 => '0', -- 1-bit input: Clock ignore input for I0 + IGNORE1 => '0', -- 1-bit input: Clock ignore input for I1 + S0 => direct_clk_s, -- 1-bit input: Clock select input for I0 + S1 => invers_clk_s -- 1-bit input: Clock select input for I1 + ); + + process(in_ref_clk) + begin + if(in_ref_clk = '1' and in_ref_clk'event)then + req_i <= clock_upd_req; + clock_upd_ack <= req_i; + err_sr <= err_sr(0) & req_i; + if(acc_cnt = C_ACC_LIMIT-1)then + acc_cnt <= 0; + err_rate <= acc_val; + acc_val <= 0; + else + if(err_sr = "01")then + acc_val <= acc_val + 1; + end if; + acc_cnt <= acc_cnt + 1; + end if; + end if; + end process; + + process(in_ref_clk) + begin + if(in_ref_clk = '1' and in_ref_clk'event)then + case sm_state is + when ST_CHECK => + if(err_rate > C_RATE_LIMIT)then + sm_state <= ST_GOOD_WAIT; + curr_delay <= (others => '0'); + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + else + delay_set <= '0'; + end if; + + when ST_FIND_GOOD => + if(req_i = '0')then -- We found start of the eye + sm_state <= ST_FIND_BAD; + start_dly <= resize(curr_delay,6); + else + if(curr_delay < TO_UNSIGNED(31,5))then + curr_delay <= curr_delay + 1; + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + sm_state <= ST_GOOD_WAIT; + else -- Data not found + invers_clk <= not invers_clk; + curr_delay <= (others => '0'); + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + sm_state <= ST_GOOD_WAIT; + end if; + end if; + + when ST_GOOD_WAIT => + delay_set <= '0'; + if(wait_cnt = 0)then + sm_state <= ST_FIND_GOOD; + else + wait_cnt <= wait_cnt - 1; + end if; + + when ST_FIND_BAD => + if((req_i = '1') or (curr_delay = TO_UNSIGNED(31,5)))then -- We found end of the eye + sm_state <= ST_CALK_DLY; + end_dly <= resize(curr_delay,6); + else + curr_delay <= curr_delay + 1; + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + sm_state <= ST_BAD_WAIT; + end if; + + when ST_BAD_WAIT => + delay_set <= '0'; + if(wait_cnt = 0)then + sm_state <= ST_FIND_BAD; + else + wait_cnt <= wait_cnt - 1; + end if; + + when ST_CALK_DLY => + sum_dly <= start_dly + end_dly; + sm_state <= ST_SET_DLY; + + when ST_SET_DLY => + curr_delay <= sum_dly(5 downto 1); + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + sm_state <= ST_SET_WAIT; + + when ST_SET_WAIT => + delay_set <= '0'; + if(wait_cnt = 0)then + sm_state <= ST_CHECK; + else + wait_cnt <= wait_cnt - 1; + end if; + end case; + end if; + end process; + delay_set_val <= STD_LOGIC_VECTOR(curr_delay); + + -- process(in_ref_clk) + -- begin + -- if(in_ref_clk = '1' and in_ref_clk'event)then + -- case sm_state is + -- when ST_CHECK => state_out <= x"0"; + -- when ST_FIND_GOOD => state_out <= x"2"; + -- when ST_GOOD_WAIT => state_out <= x"3"; + -- when ST_FIND_BAD => state_out <= x"4"; + -- when ST_BAD_WAIT => state_out <= x"5"; + -- when ST_CALK_DLY => state_out <= x"6"; + -- when ST_SET_DLY => state_out <= x"7"; + -- when ST_SET_WAIT => state_out <= x"8"; + -- end case; + -- end if; + -- end process; + +end generate; + +no_dly_gen: if C_USE_DELAY = FALSE generate +begin + clk_dg <= clk_g; +end generate; + +BUFMRCE_inst : BUFMRCE +generic map ( + CE_TYPE => "ASYNC", -- SYNC, ASYNC + INIT_OUT => 0 -- Initial output and stopped polarity, (0-1) +) +port map ( + O => clk_bufmr, -- 1-bit output: Clock output (connect to BUFIOs/BUFRs) + CE => '1', -- 1-bit input: Active high buffer enable + I => clk_dg -- 1-bit input: Clock input (Connect to IBUF) +); + +BUFIO_inst : BUFIO +port map ( + O => clk_bufio, -- 1-bit output: Clock output (connect to I/O clock loads). + I => clk_bufmr -- 1-bit input: Clock input (connect to an IBUF or BUFMR). +); +out_dclk <= clk_bufio; + +rst_bufmr <= '0'; +BUFR_inst : BUFR +generic map ( + BUFR_DIVIDE => "4", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" + SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES" +) +port map ( + O => clk_bufr, -- 1-bit output: Clock output port + CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only) + CLR => rst_bufmr, -- 1-bit input: Active high, asynchronous clear (Divided modes only) + I => clk_bufmr -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect +); +out_pclk <= clk_bufr; + +usr_BUFG_inst : BUFG +port map ( + O => out_uclk, -- 1-bit output: Clock output + I => clk_bufr -- 1-bit input: Clock input +); +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/xgui/csi2_d_phy_rx_v1_0.tcl b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/xgui/csi2_d_phy_rx_v1_0.tcl new file mode 100644 index 0000000..ad3c5bd --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi2_d_phy_rx_1.0/xgui/csi2_d_phy_rx_v1_0.tcl @@ -0,0 +1,198 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_NUM_LANES" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_NUM_LP_LANES" -parent ${Page_0} -widget comboBox + #Adding Group + set Camera_Interface [ipgui::add_group $IPINST -name "Camera Interface" -parent ${Page_0}] + ipgui::add_param $IPINST -name "C_DIFF_TERM" -parent ${Camera_Interface} + ipgui::add_param $IPINST -name "C_D0_SWAP" -parent ${Camera_Interface} + ipgui::add_param $IPINST -name "C_D1_SWAP" -parent ${Camera_Interface} + ipgui::add_param $IPINST -name "C_D2_SWAP" -parent ${Camera_Interface} + set C_D3_SWAP [ipgui::add_param $IPINST -name "C_D3_SWAP" -parent ${Camera_Interface}] + set_property tooltip {D3 P/N Swap} ${C_D3_SWAP} + + #Adding Group + set Clocking_System [ipgui::add_group $IPINST -name "Clocking System" -parent ${Page_0}] + ipgui::add_param $IPINST -name "C_USE_DELAY" -parent ${Clocking_System} + set C_IODELAY_GROUP [ipgui::add_param $IPINST -name "C_IODELAY_GROUP" -parent ${Clocking_System}] + set_property tooltip {Iodelay Group} ${C_IODELAY_GROUP} + ipgui::add_param $IPINST -name "C_ADD_IDELAYCTRL" -parent ${Clocking_System} + ipgui::add_param $IPINST -name "C_CALIB_WAIT" -parent ${Clocking_System} + ipgui::add_param $IPINST -name "C_RATE_LIMIT" -parent ${Clocking_System} + + + +} + +proc update_PARAM_VALUE.C_ADD_IDELAYCTRL { PARAM_VALUE.C_ADD_IDELAYCTRL } { + # Procedure called to update C_ADD_IDELAYCTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_ADD_IDELAYCTRL { PARAM_VALUE.C_ADD_IDELAYCTRL } { + # Procedure called to validate C_ADD_IDELAYCTRL + return true +} + +proc update_PARAM_VALUE.C_CALIB_WAIT { PARAM_VALUE.C_CALIB_WAIT } { + # Procedure called to update C_CALIB_WAIT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_CALIB_WAIT { PARAM_VALUE.C_CALIB_WAIT } { + # Procedure called to validate C_CALIB_WAIT + return true +} + +proc update_PARAM_VALUE.C_D0_SWAP { PARAM_VALUE.C_D0_SWAP } { + # Procedure called to update C_D0_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D0_SWAP { PARAM_VALUE.C_D0_SWAP } { + # Procedure called to validate C_D0_SWAP + return true +} + +proc update_PARAM_VALUE.C_D1_SWAP { PARAM_VALUE.C_D1_SWAP } { + # Procedure called to update C_D1_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D1_SWAP { PARAM_VALUE.C_D1_SWAP } { + # Procedure called to validate C_D1_SWAP + return true +} + +proc update_PARAM_VALUE.C_D2_SWAP { PARAM_VALUE.C_D2_SWAP } { + # Procedure called to update C_D2_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D2_SWAP { PARAM_VALUE.C_D2_SWAP } { + # Procedure called to validate C_D2_SWAP + return true +} + +proc update_PARAM_VALUE.C_D3_SWAP { PARAM_VALUE.C_D3_SWAP } { + # Procedure called to update C_D3_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D3_SWAP { PARAM_VALUE.C_D3_SWAP } { + # Procedure called to validate C_D3_SWAP + return true +} + +proc update_PARAM_VALUE.C_DIFF_TERM { PARAM_VALUE.C_DIFF_TERM } { + # Procedure called to update C_DIFF_TERM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_DIFF_TERM { PARAM_VALUE.C_DIFF_TERM } { + # Procedure called to validate C_DIFF_TERM + return true +} + +proc update_PARAM_VALUE.C_IODELAY_GROUP { PARAM_VALUE.C_IODELAY_GROUP } { + # Procedure called to update C_IODELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IODELAY_GROUP { PARAM_VALUE.C_IODELAY_GROUP } { + # Procedure called to validate C_IODELAY_GROUP + return true +} + +proc update_PARAM_VALUE.C_NUM_LANES { PARAM_VALUE.C_NUM_LANES } { + # Procedure called to update C_NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_NUM_LANES { PARAM_VALUE.C_NUM_LANES } { + # Procedure called to validate C_NUM_LANES + return true +} + +proc update_PARAM_VALUE.C_NUM_LP_LANES { PARAM_VALUE.C_NUM_LP_LANES } { + # Procedure called to update C_NUM_LP_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_NUM_LP_LANES { PARAM_VALUE.C_NUM_LP_LANES } { + # Procedure called to validate C_NUM_LP_LANES + return true +} + +proc update_PARAM_VALUE.C_RATE_LIMIT { PARAM_VALUE.C_RATE_LIMIT } { + # Procedure called to update C_RATE_LIMIT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RATE_LIMIT { PARAM_VALUE.C_RATE_LIMIT } { + # Procedure called to validate C_RATE_LIMIT + return true +} + +proc update_PARAM_VALUE.C_USE_DELAY { PARAM_VALUE.C_USE_DELAY } { + # Procedure called to update C_USE_DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_USE_DELAY { PARAM_VALUE.C_USE_DELAY } { + # Procedure called to validate C_USE_DELAY + return true +} + + +proc update_MODELPARAM_VALUE.C_NUM_LANES { MODELPARAM_VALUE.C_NUM_LANES PARAM_VALUE.C_NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_NUM_LANES}] ${MODELPARAM_VALUE.C_NUM_LANES} +} + +proc update_MODELPARAM_VALUE.C_NUM_LP_LANES { MODELPARAM_VALUE.C_NUM_LP_LANES PARAM_VALUE.C_NUM_LP_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_NUM_LP_LANES}] ${MODELPARAM_VALUE.C_NUM_LP_LANES} +} + +proc update_MODELPARAM_VALUE.C_D0_SWAP { MODELPARAM_VALUE.C_D0_SWAP PARAM_VALUE.C_D0_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D0_SWAP}] ${MODELPARAM_VALUE.C_D0_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D1_SWAP { MODELPARAM_VALUE.C_D1_SWAP PARAM_VALUE.C_D1_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D1_SWAP}] ${MODELPARAM_VALUE.C_D1_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D2_SWAP { MODELPARAM_VALUE.C_D2_SWAP PARAM_VALUE.C_D2_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D2_SWAP}] ${MODELPARAM_VALUE.C_D2_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D3_SWAP { MODELPARAM_VALUE.C_D3_SWAP PARAM_VALUE.C_D3_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D3_SWAP}] ${MODELPARAM_VALUE.C_D3_SWAP} +} + +proc update_MODELPARAM_VALUE.C_DIFF_TERM { MODELPARAM_VALUE.C_DIFF_TERM PARAM_VALUE.C_DIFF_TERM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_DIFF_TERM}] ${MODELPARAM_VALUE.C_DIFF_TERM} +} + +proc update_MODELPARAM_VALUE.C_ADD_IDELAYCTRL { MODELPARAM_VALUE.C_ADD_IDELAYCTRL PARAM_VALUE.C_ADD_IDELAYCTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_ADD_IDELAYCTRL}] ${MODELPARAM_VALUE.C_ADD_IDELAYCTRL} +} + +proc update_MODELPARAM_VALUE.C_IODELAY_GROUP { MODELPARAM_VALUE.C_IODELAY_GROUP PARAM_VALUE.C_IODELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IODELAY_GROUP}] ${MODELPARAM_VALUE.C_IODELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.C_USE_DELAY { MODELPARAM_VALUE.C_USE_DELAY PARAM_VALUE.C_USE_DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_USE_DELAY}] ${MODELPARAM_VALUE.C_USE_DELAY} +} + +proc update_MODELPARAM_VALUE.C_CALIB_WAIT { MODELPARAM_VALUE.C_CALIB_WAIT PARAM_VALUE.C_CALIB_WAIT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_CALIB_WAIT}] ${MODELPARAM_VALUE.C_CALIB_WAIT} +} + +proc update_MODELPARAM_VALUE.C_RATE_LIMIT { MODELPARAM_VALUE.C_RATE_LIMIT PARAM_VALUE.C_RATE_LIMIT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RATE_LIMIT}] ${MODELPARAM_VALUE.C_RATE_LIMIT} +} + diff --git a/zynqberrydemo1/ip_lib/csi_to_axis_1.0/bd/bd.tcl b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo1/ip_lib/csi_to_axis_1.0/component.xml b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/component.xml new file mode 100644 index 0000000..f123cdd --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/component.xml @@ -0,0 +1,1180 @@ + + + trenz.biz + user + csi_to_axis + 1.0 + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + + + RX_MIPI_PPI + RX_MIPI_PPI + RX_MIPI_PPI + + + + + + + DL1_RXACTIVEHS + + + dl1_rxactivehs + + + + + DL0_RXSYNCHS + + + dl0_rxsynchs + + + + + DL1_RXVALIDHS + + + dl1_rxvalidhs + + + + + CL_ENABLE + + + cl_enable + + + + + DL1_RXDATAHS + + + dl1_datahs + + + + + DL0_RXACTIVEHS + + + dl0_rxactivehs + + + + + CL_STOPSTATE + + + cl_stopstate + + + + + DL1_RXSYNCHS + + + dl1_rxsynchs + + + + + DL0_ENABLE + + + dl0_enable + + + + + DL0_RXDATAHS + + + dl0_datahs + + + + + DL1_ENABLE + + + dl1_enable + + + + + DL0_RXVALIDHS + + + dl0_rxvalidhs + + + + + CL_RXCLKACTIVEHS + + + cl_rxclkactivehs + + + + + DL2_RXSYNCHS + + + dl2_rxsynchs + + + + + DL3_RXACTIVEHS + + + dl3_rxactivehs + + + + + DL3_RXDATAHS + + + dl3_datahs + + + + + DL2_RXDATAHS + + + dl2_datahs + + + + + DL3_RXSYNCHS + + + dl3_rxsynchs + + + + + DL3_RXVALIDHS + + + dl3_rxvalidhs + + + + + DL3_ENABLE + + + dl3_enable + + + + + DL2_RXVALIDHS + + + dl2_rxvalidhs + + + + + DL2_RXACTIVEHS + + + dl2_rxactivehs + + + + + DL2_ENABLE + + + dl2_enable + + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + M_AXIS + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + data_err + + + + + + + ACK + + + trig_ack + + + + + TRIG + + + trig_req + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + csi_to_axis_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 86b17c2f + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + csi_to_axis_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + c5d94c0e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3bb3a441 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + enable_in + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + rxbyteclkhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + cl_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + cl_stopstate + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + cl_rxclkactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl0_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + dl0_rxactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl0_rxvalidhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl0_rxsynchs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl0_datahs + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl1_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + true + + + + + + dl1_rxactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + dl1_rxvalidhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + dl1_rxsynchs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + dl1_datahs + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + dl2_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + dl2_rxactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + dl2_rxvalidhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + dl2_rxsynchs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + dl2_datahs + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + dl3_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + dl3_rxactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + dl3_rxvalidhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + dl3_rxsynchs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + dl3_datahs + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + trig_req + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + trig_ack + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + m_axis_tdata + + out + + 15 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + m_axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_M_AXIS_TDATA_WIDTH + C M AXIS TDATA WIDTH + Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + 32 + + + C_LANES + C Lanes + 2 + + + C_TIMEOUT + C Timeout + 127 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_e6469819 + 1 + 2 + 4 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/csi_to_axis.xdc + xdc + USED_IN_implementation + USED_IN_synthesis + + + hdl/csi2_parser.vhd + vhdlSource + + + hdl/lane_align.vhd + vhdlSource + + + hdl/lane_merge.vhd + vhdlSource + + + hdl/csi_to_axis_v1_0.vhd + vhdlSource + CHECKSUM_9c64e067 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/csi2_parser.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/lane_align.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/lane_merge.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/csi_to_axis_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/csi_to_axis_v1_0.tcl + tclSource + CHECKSUM_67ac9fac + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + CSI-2 to AXI4-Stream + + + C_M_AXIS_TDATA_WIDTH + C M AXIS TDATA WIDTH + Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + 32 + + + + false + + + + + + Component_Name + csi_to_axis_v1_0 + + + C_LANES + Data Lanes + 2 + + + C_TIMEOUT + Line Align Timeout + 127 + + + + + + virtex7 + artix7 + kintex7 + zynq + qzynq + + + /AXI_Peripheral + /Video_&_Image_Processing + + CSI-2 to AXI4-Stream v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 46 + + xilinx.com:user:csi_to_axis:1.0 + + 2017-05-17T10:14:06Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/csi_to_axis_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/csi_to_axis_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi2_parser.vhd b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi2_parser.vhd new file mode 100644 index 0000000..6b76fdb --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi2_parser.vhd @@ -0,0 +1,147 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity csi2_parser is +generic( + C_LANES : INTEGER range 1 to 4 := 2 +); +port ( + enable_in : in STD_LOGIC; + resync_out : out STD_LOGIC; + axis_aclk : in STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + s_axis_tvalid : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + + frame_start_dbg : out STD_LOGIC; + line_start_dbg : out STD_LOGIC; + packet_id_dbg : out STD_LOGIC_VECTOR(7 downto 0); + packet_id_upd : out STD_LOGIC; + packet_size_dbg : out STD_LOGIC_VECTOR(15 downto 0); + transfer_cnt_dbg : out STD_LOGIC_VECTOR(15 downto 0) +); +end csi2_parser; +---------------------------------------------------------------------------------- +architecture arch_imp of csi2_parser is +---------------------------------------------------------------------------------- +constant C_SOT : STD_LOGIC_VECTOR(7 downto 0) := x"B8"; +constant C_RAW10 : STD_LOGIC_VECTOR(7 downto 0) := x"2B"; +constant C_EOF : STD_LOGIC_VECTOR(7 downto 0) := x"01"; +constant C_WAIT : INTEGER := 15; +---------------------------------------------------------------------------------- +type sm_state_type is (ST_IDLE, ST_HDRA, ST_HDRB, ST_TRANSFER, ST_RESYNC); +signal sm_state : sm_state_type := ST_IDLE; +---------------------------------------------------------------------------------- +signal packet_size : STD_LOGIC_VECTOR(15 downto 0); +signal packet_cs : STD_LOGIC_VECTOR( 7 downto 0); +signal packet_id : STD_LOGIC_VECTOR( 7 downto 0); +signal transfer_cnt : UNSIGNED(15 downto 0); +signal start_of_frame : STD_LOGIC; +signal start_of_line : STD_LOGIC; +signal enable_req : STD_LOGIC; +signal enable : STD_LOGIC; +signal wait_cnt : INTEGER range 0 to C_WAIT-1 := 0; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + m_axis_tdata <= s_axis_tdata; + enable_req <= enable_in; + case sm_state is + when ST_IDLE => + m_axis_tvalid <= '0'; + m_axis_tlast <= '0'; + packet_id_upd <= '0'; + if(s_axis_tvalid = '1')then + if((s_axis_tdata(7 downto 0) = C_SOT) and (s_axis_tdata(15 downto 8) = C_SOT))then + sm_state <= ST_HDRA; + else + sm_state <= ST_RESYNC; + end if; + end if; + when ST_RESYNC => + m_axis_tvalid <= '0'; + m_axis_tlast <= '0'; + if(s_axis_tvalid = '0')then + sm_state <= ST_IDLE; + end if; + when ST_HDRA => + if(s_axis_tvalid = '1')then + packet_size( 7 downto 0) <= s_axis_tdata(15 downto 8); + packet_id <= s_axis_tdata( 7 downto 0); + if((s_axis_tdata( 7 downto 0) = C_RAW10) or (s_axis_tdata( 7 downto 0) = C_EOF))then -- Correct ID + sm_state <= ST_HDRB; + else + sm_state <= ST_RESYNC; + end if; + else + sm_state <= ST_RESYNC; + end if; + when ST_HDRB => + if(s_axis_tvalid = '1')then + packet_cs <= s_axis_tdata(15 downto 8); + packet_size(15 downto 8) <= s_axis_tdata( 7 downto 0); + if(packet_id = C_RAW10)then + sm_state <= ST_TRANSFER; + transfer_cnt <= (others => '0'); + start_of_line <= '1'; + else + sm_state <= ST_RESYNC; + packet_id_dbg <= packet_id; + packet_id_upd <= '1'; + end if; + if(packet_id = C_EOF)then + start_of_frame <= '1'; + enable <= enable_req; + end if; + else + sm_state <= ST_RESYNC; + end if; + when ST_TRANSFER => + if(s_axis_tvalid = '1')then + start_of_frame <= '0'; + start_of_line <= '0'; + m_axis_tuser <= start_of_frame; + m_axis_tvalid <= enable; + if(transfer_cnt >= (UNSIGNED(packet_size)-2))then + m_axis_tlast <= '1'; + sm_state <= ST_RESYNC; + else + transfer_cnt <= transfer_cnt + 2; + end if; + else + m_axis_tlast <= '1'; + sm_state <= ST_IDLE; + end if; + end case; + end if; +end process; + +frame_start_dbg <= start_of_frame; +line_start_dbg <= start_of_line; +packet_size_dbg <= packet_size; +transfer_cnt_dbg <= STD_LOGIC_VECTOR(transfer_cnt); + +process(sm_state) +begin + if( + ((sm_state = ST_IDLE) and (s_axis_tvalid = '1') and ((s_axis_tdata(7 downto 0) /= C_SOT) or (s_axis_tdata(15 downto 8) /= C_SOT))) or + ((sm_state = ST_HDRA) and not ((s_axis_tdata( 7 downto 0) = C_RAW10) or (s_axis_tdata( 7 downto 0) = C_EOF))) + )then + resync_out <= '1'; + else + resync_out <= '0'; + end if; +end process; +--------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis.xdc b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis.xdc new file mode 100644 index 0000000..d270ab4 --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis.xdc @@ -0,0 +1 @@ +set_false_path -to [get_pins parser_inst/enable_req_reg/D] \ No newline at end of file diff --git a/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis_v1_0.vhd b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis_v1_0.vhd new file mode 100644 index 0000000..a475d76 --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis_v1_0.vhd @@ -0,0 +1,272 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity csi_to_axis_v1_0 is +generic ( + C_M_AXIS_TDATA_WIDTH : INTEGER := 32; + C_LANES : INTEGER range 1 to 4 := 2; + C_TIMEOUT : INTEGER := 127 +); +port ( + -- Transfer enable + enable_in : in STD_LOGIC; + -- MIPI PPI + rxbyteclkhs : in STD_LOGIC; + cl_enable : out STD_LOGIC := '1'; + cl_stopstate : in STD_LOGIC; + cl_rxclkactivehs : in STD_LOGIC; + dl0_enable : out STD_LOGIC := '1'; + dl0_rxactivehs : in STD_LOGIC; + dl0_rxvalidhs : in STD_LOGIC; + dl0_rxsynchs : in STD_LOGIC; + dl0_datahs : in STD_LOGIC_VECTOR(7 downto 0); + dl1_enable : out STD_LOGIC; + dl1_rxactivehs : in STD_LOGIC; + dl1_rxvalidhs : in STD_LOGIC; + dl1_rxsynchs : in STD_LOGIC; + dl1_datahs : in STD_LOGIC_VECTOR(7 downto 0); + dl2_enable : out STD_LOGIC; + dl2_rxactivehs : in STD_LOGIC; + dl2_rxvalidhs : in STD_LOGIC; + dl2_rxsynchs : in STD_LOGIC; + dl2_datahs : in STD_LOGIC_VECTOR(7 downto 0); + dl3_enable : out STD_LOGIC; + dl3_rxactivehs : in STD_LOGIC; + dl3_rxvalidhs : in STD_LOGIC; + dl3_rxsynchs : in STD_LOGIC; + dl3_datahs : in STD_LOGIC_VECTOR(7 downto 0); + -- Status + trig_req : out STD_LOGIC; + trig_ack : in STD_LOGIC; + -- AXIS + m_axis_aclk : in STD_LOGIC; + m_axis_aresetn : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC + -- -- Debug +-- raw_data_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- raw_valid_dbg : out STD_LOGIC_VECTOR( 1 downto 0); +-- align_data_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- align_valid_dbg : out STD_LOGIC_VECTOR( 1 downto 0); +-- merge_data_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- merge_valid_dbg : out STD_LOGIC; +-- frame_start_dbg : out STD_LOGIC; +-- line_start_dbg : out STD_LOGIC; +-- parse_data_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- parse_valid_dbg : out STD_LOGIC; +-- parse_user_dbg : out STD_LOGIC; +-- parse_last_dbg : out STD_LOGIC; +-- packet_id_dbg : out STD_LOGIC_VECTOR( 7 downto 0); +-- packet_id_upd_dbd : out STD_LOGIC; +-- packet_size_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- transfer_cnt_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- align_resync_dbg : out STD_LOGIC; +-- merge_resync_dbg : out STD_LOGIC +); +end csi_to_axis_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of csi_to_axis_v1_0 is +---------------------------------------------------------------------------------- +component lane_align is +generic( + C_LANES : INTEGER range 1 to 4 := 2; + C_TIMEOUT : INTEGER := 127 +); +port ( + clk_in : in STD_LOGIC; + resync : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_in : in STD_LOGIC_VECTOR(C_LANES-1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_out : out STD_LOGIC_VECTOR(C_LANES-1 downto 0); + err_req : out STD_LOGIC; + err_ack : in STD_LOGIC +); +end component; + +component lane_merge is +generic( + C_LANES : INTEGER range 1 to 4 := 2 +); +port( + clk_in : in STD_LOGIC; + resync_in : in STD_LOGIC; + resync_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_in : in STD_LOGIC_VECTOR(C_LANES-1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_out : out STD_LOGIC +); +end component; + +component csi2_parser is +generic( + C_LANES : INTEGER range 1 to 4 := 2 +); +port ( + enable_in : in STD_LOGIC; + resync_out : out STD_LOGIC; + axis_aclk : in STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + s_axis_tvalid : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + -- Debug + frame_start_dbg : out STD_LOGIC; + line_start_dbg : out STD_LOGIC; + packet_id_dbg : out STD_LOGIC_VECTOR(7 downto 0); + packet_id_upd : out STD_LOGIC; + packet_size_dbg : out STD_LOGIC_VECTOR(15 downto 0); + transfer_cnt_dbg : out STD_LOGIC_VECTOR(15 downto 0) +); +end component; +---------------------------------------------------------------------------------- +signal pclk : STD_LOGIC; +signal raw_data : STD_LOGIC_VECTOR(8*C_LANES-1 downto 0); +signal align_data : STD_LOGIC_VECTOR(8*C_LANES-1 downto 0); +signal merge_data : STD_LOGIC_VECTOR(8*C_LANES-1 downto 0); +signal raw_valid : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +signal align_valid : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +signal merge_valid : STD_LOGIC; +signal tuser_drv : STD_LOGIC; +signal tlast_drv : STD_LOGIC; +signal tvalid_drv : STD_LOGIC; +signal tdata_drv : STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); +signal frame_start : STD_LOGIC; +signal line_start : STD_LOGIC; +signal packet_id : STD_LOGIC_VECTOR(7 downto 0); +signal packet_id_upd : STD_LOGIC; +signal packet_size : STD_LOGIC_VECTOR(15 downto 0); +signal transfer_cnt : STD_LOGIC_VECTOR(15 downto 0); +signal align_resync : STD_LOGIC; +signal merge_resync : STD_LOGIC; +signal parse_resync : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +pclk <= rxbyteclkhs; -- Main byte clock bitrate/8 +cl_enable <= '1'; -- PPI ShutDown ? +---------------------------------------------------------------------------------- +-- Lane 0 +dl0_enable <= '1'; +raw_valid(0) <= dl0_rxvalidhs; +raw_data( 7 downto 0) <= dl0_datahs; +---------------------------------------------------------------------------------- +-- Lane 1 +lane_1_gen: if C_LANES > 1 generate +begin + dl1_enable <= '1'; + raw_valid(1) <= dl1_rxvalidhs; + raw_data(15 downto 8) <= dl1_datahs; +end generate; +---------------------------------------------------------------------------------- +-- Lane 2 +lane_2_gen: if C_LANES > 2 generate +begin + dl2_enable <= '1'; + raw_valid(2) <= dl2_rxvalidhs; + raw_data(23 downto 16) <= dl2_datahs; +end generate; +---------------------------------------------------------------------------------- +-- Lane 3 +lane_3_gen: if C_LANES > 3 generate +begin + dl3_enable <= '1'; + raw_valid(3) <= dl3_rxvalidhs; + raw_data(31 downto 24) <= dl3_datahs; +end generate; +---------------------------------------------------------------------------------- +lane_align_inst: lane_align +generic map( + C_LANES => C_LANES, + C_TIMEOUT => C_TIMEOUT +) +port map( + clk_in => pclk, + resync => align_resync, + data_in => raw_data, + valid_in => raw_valid, + data_out => align_data, + valid_out => align_valid, + err_req => trig_req, + err_ack => trig_ack +); +---------------------------------------------------------------------------------- +lane_merge_inst: lane_merge +generic map( + C_LANES => C_LANES +) +port map( + clk_in => pclk, + resync_in => parse_resync, + resync_out => merge_resync, + data_in => align_data, + valid_in => align_valid, + data_out => merge_data, + valid_out => merge_valid +); +---------------------------------------------------------------------------------- +align_resync <= merge_resync or parse_resync; +---------------------------------------------------------------------------------- +parser_inst: csi2_parser +generic map( + C_LANES => C_LANES +) +port map( + enable_in => enable_in, + resync_out => parse_resync, + axis_aclk => pclk, + s_axis_tdata => merge_data, + s_axis_tvalid => merge_valid, + m_axis_tvalid => tvalid_drv, + m_axis_tdata => tdata_drv, + m_axis_tuser => tuser_drv, + m_axis_tlast => tlast_drv, + + frame_start_dbg => frame_start, + line_start_dbg => line_start, + packet_id_dbg => packet_id, + packet_id_upd => packet_id_upd, + packet_size_dbg => packet_size, + transfer_cnt_dbg => transfer_cnt +); +---------------------------------------------------------------------------------- +m_axis_tvalid <= tvalid_drv; +m_axis_tdata <= tdata_drv; +m_axis_tuser <= tuser_drv; +m_axis_tlast <= tlast_drv; +---------------------------------------------------------------------------------- +-- Debug +---------------------------------------------------------------------------------- +--raw_data_dbg <= raw_data; +--raw_valid_dbg <= raw_valid; +--align_data_dbg <= align_data; +--align_valid_dbg <= align_valid; +--merge_data_dbg <= merge_data; +--merge_valid_dbg <= merge_valid; +--frame_start_dbg <= frame_start; +--line_start_dbg <= line_start; +--parse_data_dbg <= tdata_drv; +--parse_valid_dbg <= tvalid_drv; +--parse_user_dbg <= tuser_drv; +--parse_last_dbg <= tlast_drv; +--packet_id_dbg <= packet_id; +--packet_id_upd_dbd <= packet_id_upd; +--packet_size_dbg <= packet_size; +--transfer_cnt_dbg <= transfer_cnt; +--align_resync_dbg <= align_resync; +--merge_resync_dbg <= merge_resync; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/lane_align.vhd b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/lane_align.vhd new file mode 100644 index 0000000..40ddf67 --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/lane_align.vhd @@ -0,0 +1,123 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity lane_align is +generic( + C_LANES : INTEGER range 1 to 4 := 2; + C_TIMEOUT : INTEGER := 127 +); +port ( + clk_in : in STD_LOGIC; + resync : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_in : in STD_LOGIC_VECTOR(C_LANES-1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_out : out STD_LOGIC_VECTOR(C_LANES-1 downto 0); + err_req : out STD_LOGIC; + err_ack : in STD_LOGIC +); +end lane_align; +---------------------------------------------------------------------------------- +architecture arch_imp of lane_align is +---------------------------------------------------------------------------------- +constant C_SOT : STD_LOGIC_VECTOR(15 downto 0) := x"B800"; +constant ones_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0) := (others => '1'); +constant zero_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0) := (others => '0'); +constant C_CNT_LIMIT : integer := 1; +---------------------------------------------------------------------------------- +type sr_data_type is array (0 to C_LANES-1) of STD_LOGIC_VECTOR(23 downto 0); +signal data_sr : sr_data_type; +type buf_data_type is array (0 to C_LANES-1) of STD_LOGIC_VECTOR(15 downto 0); +signal data_dly : buf_data_type; +signal sot_found : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +type shift_type is array (0 to C_LANES-1) of integer range 0 to 8; +signal data_shift_det : shift_type; +signal data_shift : shift_type; +signal transfer : STD_LOGIC_VECTOR(C_LANES-1 downto 0); + +type to_cnt_type is array (0 to C_LANES-1) of integer range 0 to C_TIMEOUT; +signal to_cnt : to_cnt_type; +signal to_flag : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +---------------------------------------------------------------------------------- +signal err_ack_i : STD_LOGIC; +attribute ASYNC_REG : string; +attribute ASYNC_REG of err_ack_i : signal is "true"; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process(data_sr) +begin + sot_found <= (others => '0'); + data_shift_det <= (others => 0); + for j in 0 to C_LANES-1 loop + for i in 0 to 8 loop + if(data_sr(j)(i+15 downto i) = C_SOT)then + sot_found(j) <= '1'; + data_shift_det(j) <= i; + end if; + end loop; + end loop; +end process; + +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + --err_ack_i <= err_ack; + err_req <= '0'; + for i in 0 to C_LANES-1 loop + + if(valid_in(i) = '1')then + data_sr(i) <= data_in(i*8+7 downto i*8) & data_sr(i)(23 downto 8); + end if; + data_dly(i) <= data_sr(i)(23 downto 8); + + if(transfer(i) = '0')then + if((valid_in(i) = '1') and (sot_found(i) = '1'))then + data_shift <= data_shift_det; + transfer(i) <= '1'; + end if; + if(valid_in(i) = '1')then + if(sot_found(i) = '1')then + to_flag(i) <= '0'; + to_cnt(i) <= 0; + else + if(to_cnt(i) /= C_TIMEOUT)then + to_cnt(i) <= to_cnt(i) + 1; + else + to_flag(i) <= '1'; + end if; + end if; + end if; + else + if((valid_in(i) = '0') or (resync = '1'))then + transfer(i) <= '0'; + to_cnt(i) <= 0; + end if; + end if; + + -- if(to_cnt(i) = C_TIMEOUT-1)then + -- err_req <= '1'; + -- elsif(err_ack_i)then + -- err_req <= '0'; + -- end if; + end loop; + if(UNSIGNED(to_flag) /= TO_UNSIGNED(0,C_LANES))then + err_req <= '1'; + else + err_req <= '0'; + end if; + end if; +end process; + +out_gen: for i in 0 to C_LANES-1 generate +begin + data_out(i*8+7 downto i*8) <= data_dly(i)(data_shift(i)+7 downto data_shift(i)); + valid_out(i) <= transfer(i); +end generate; +--------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/lane_merge.vhd b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/lane_merge.vhd new file mode 100644 index 0000000..6906471 --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/hdl/lane_merge.vhd @@ -0,0 +1,118 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity lane_merge is +generic( + C_LANES : INTEGER range 1 to 4 := 2 +); +port ( + clk_in : in STD_LOGIC; + resync_in : in STD_LOGIC; + resync_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_in : in STD_LOGIC_VECTOR(C_LANES-1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_out : out STD_LOGIC +); +end lane_merge; +---------------------------------------------------------------------------------- +architecture arch_imp of lane_merge is +---------------------------------------------------------------------------------- +constant C_SOT : STD_LOGIC_VECTOR(7 downto 0) := x"B8"; +constant ones_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0) := (others => '1'); +constant zero_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0) := (others => '0'); +---------------------------------------------------------------------------------- +type sm_state_type is (ST_IDLE, ST_FIRST, ST_TRANSFER, ST_RESYNC); +signal sm_state : sm_state_type := ST_IDLE; +---------------------------------------------------------------------------------- +signal data_dl : STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); +signal valid_dl : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +signal align_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + data_dl <= data_in; + valid_dl <= valid_in; + case sm_state is + when ST_IDLE => + if(valid_in /= zero_vec)then + align_vec <= valid_in; + sm_state <= ST_FIRST; + -- valid_out <= '1'; + -- else + -- valid_out <= '0'; + end if; + when ST_FIRST => + if((valid_in /= ones_vec) or (resync_in = '1'))then + align_vec <= (others => '0'); + sm_state <= ST_RESYNC; + resync_out <= '1'; + else + sm_state <= ST_TRANSFER; + valid_out <= '1'; + for i in 0 to C_LANES-1 loop + if(data_in(i*8+7 downto i*8) = C_SOT)then + align_vec(i) <= '0'; -- Not delayed + else + align_vec(i) <= '1'; -- Delayed + end if; + end loop; + end if; + + when ST_TRANSFER => + -- if((valid_in /= ones_vec) or (resync_in = '1'))then + -- align_vec <= (others => '0'); + -- sm_state <= ST_RESYNC; + -- resync_out <= '1'; + -- valid_out <= '0'; + -- end if; + if(valid_in /= ones_vec)then + align_vec <= (others => '0'); + sm_state <= ST_IDLE; + valid_out <= '0'; + elsif(resync_in = '1')then + align_vec <= (others => '0'); + sm_state <= ST_RESYNC; + resync_out <= '1'; + valid_out <= '0'; + end if; + when ST_RESYNC => + resync_out <= '0'; + if(valid_in = zero_vec)then + sm_state <= ST_IDLE; + end if; + end case; + + --valid_out <= '0'; + --valid_out <= '1'; + for i in 0 to C_LANES-1 loop + --if(valid_dl(i) = '1')then + -- valid_out <= '1'; + --end if; + -- if(align_vec(i) = '1')then + -- if(valid_dl(i) = '0')then + -- valid_out <= '0'; + -- end if; + -- else + -- if(valid_in(i) = '0')then + -- valid_out <= '0'; + -- end if; + -- end if; + if(align_vec(i) = '1')then + data_out(i*8+7 downto i*8) <= data_dl(i*8+7 downto i*8); + else + data_out(i*8+7 downto i*8) <= data_in(i*8+7 downto i*8); + end if; + end loop; + end if; +end process; +--------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/csi_to_axis_1.0/xgui/csi_to_axis_v1_0.tcl b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/xgui/csi_to_axis_v1_0.tcl new file mode 100644 index 0000000..bea5392 --- /dev/null +++ b/zynqberrydemo1/ip_lib/csi_to_axis_1.0/xgui/csi_to_axis_v1_0.tcl @@ -0,0 +1,56 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set C_M_AXIS_TDATA_WIDTH [ipgui::add_param $IPINST -name "C_M_AXIS_TDATA_WIDTH" -parent ${Page_0} -widget comboBox] + set_property tooltip {Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.} ${C_M_AXIS_TDATA_WIDTH} + ipgui::add_param $IPINST -name "C_LANES" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_TIMEOUT" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_LANES { PARAM_VALUE.C_LANES } { + # Procedure called to update C_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_LANES { PARAM_VALUE.C_LANES } { + # Procedure called to validate C_LANES + return true +} + +proc update_PARAM_VALUE.C_TIMEOUT { PARAM_VALUE.C_TIMEOUT } { + # Procedure called to update C_TIMEOUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_TIMEOUT { PARAM_VALUE.C_TIMEOUT } { + # Procedure called to validate C_TIMEOUT + return true +} + +proc update_PARAM_VALUE.C_M_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } { + # Procedure called to update C_M_AXIS_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } { + # Procedure called to validate C_M_AXIS_TDATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH { MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M_AXIS_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_LANES { MODELPARAM_VALUE.C_LANES PARAM_VALUE.C_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_LANES}] ${MODELPARAM_VALUE.C_LANES} +} + +proc update_MODELPARAM_VALUE.C_TIMEOUT { MODELPARAM_VALUE.C_TIMEOUT PARAM_VALUE.C_TIMEOUT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_TIMEOUT}] ${MODELPARAM_VALUE.C_TIMEOUT} +} + diff --git a/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/component.xml b/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/component.xml new file mode 100644 index 0000000..8e19f3e --- /dev/null +++ b/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/component.xml @@ -0,0 +1,228 @@ + + + trenz.biz + user + i2s_to_pwm + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + i2s_to_pwm + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 560fdf3f + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + i2s_to_pwm + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 560fdf3f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 85d97987 + + + + + + + clk_in + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_bclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_lrclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_sdata + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pwm_l_out + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pwm_r_out + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_SYS_FREQ + C Sys Freq + 150000000 + + + C_PWM_FREQ + C Pwm Freq + 100000 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/i2s_to_pwm.vhd + vhdlSource + CHECKSUM_560fdf3f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/i2s_to_pwm.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/i2s_to_pwm_v1_0.tcl + tclSource + CHECKSUM_8d217f22 + XGUI_VERSION_2 + + + + I2S to PWM v1.0 + + + C_SYS_FREQ + Clock Frequency + 150000000 + + + C_PWM_FREQ + PWM Frequency + 100000 + + + Component_Name + i2s_to_pwm_v1_0 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /Communication_&_Networking/Serial_Interfaces + /Digital_Signal_Processing/Modulation + /UserIP + + I2S to PWM v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 7 + + xilinx.com:user:i2s_to_pwm:1.0 + + 2016-04-04T15:47:26Z + + + b:/cores/2015.4/design/te0726/demo/ip_lib/i2s_to_pwm_1.0 + b:/cores/2015.4/design/te0726/demo/ip_lib/i2s_to_pwm_1.0 + + + + 2015.4.2 + + + + + + + diff --git a/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/hdl/i2s_to_pwm.vhd b/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/hdl/i2s_to_pwm.vhd new file mode 100644 index 0000000..1e989ba --- /dev/null +++ b/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/hdl/i2s_to_pwm.vhd @@ -0,0 +1,133 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity i2s_to_pwm is +generic ( + C_SYS_FREQ : INTEGER := 150000000; + C_PWM_FREQ : INTEGER := 100000 -- Usually from 50 to 100 kHz +); +port ( + -- General + clk_in : in STD_LOGIC; + -- I2S Signals + i2s_bclk : in STD_LOGIC; + i2s_lrclk : in STD_LOGIC; + i2s_sdata : in STD_LOGIC; + -- PWM Outs + pwm_l_out : out STD_LOGIC; + pwm_r_out : out STD_LOGIC +); +end i2s_to_pwm; +---------------------------------------------------------------------------------- +architecture arch_imp of i2s_to_pwm is +---------------------------------------------------------------------------------- +-- For 16 bit sound +constant C_S_CNT_MAX : INTEGER := 32767; +constant C_S_CNT_MIN : INTEGER := -32767; +constant C_STEP : INTEGER := 131072 / (C_SYS_FREQ/C_PWM_FREQ); +---------------------------------------------------------------------------------- +signal left_s_ch_val : SIGNED(15 downto 0); -- Data latches +signal right_s_ch_val : SIGNED(15 downto 0); +signal pwm_s_cnt : SIGNED(15 downto 0); -- Reference signal +signal pwm_s_cnt_dir : STD_LOGIC; -- Saw direction +---------------------------------------------------------------------------------- +signal bclk_sr : STD_LOGIC_VECTOR(1 downto 0); +signal lrclk_sr : STD_LOGIC_VECTOR(1 downto 0); +signal sdata : STD_LOGIC; +---------------------------------------------------------------------------------- +signal bit_addr : INTEGER range 0 to 31; +signal data_reg : STD_LOGIC_VECTOR(31 downto 0); +signal lsb_left : STD_LOGIC; +signal lsb_right : STD_LOGIC; +signal update_left : STD_LOGIC; +signal update_right : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +-- I2S Decode +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + bclk_sr <= bclk_sr(0) & i2s_bclk; + lrclk_sr <= lrclk_sr(0) & i2s_lrclk; + sdata <= i2s_sdata; + if(lrclk_sr = "01")then -- End of left + lsb_left <= '1'; + elsif(bclk_sr = "01")then -- Rising edge + lsb_left <= '0'; + end if; + if(lrclk_sr = "10")then -- End of rigth + lsb_right <= '1'; + elsif(bclk_sr = "01")then -- Rising edge + lsb_right <= '0'; + end if; + + if(bclk_sr = "01")then -- Rising edge + if((lsb_left = '1') or (lsb_right = '1'))then + bit_addr <= 31; + elsif(bit_addr /= 0)then + bit_addr <= bit_addr - 1; + end if; + data_reg(bit_addr) <= sdata; + update_left <= lsb_left; + update_right <= lsb_right; + else + update_left <= '0'; + update_right <= '0'; + end if; + + if(update_left = '1')then + left_s_ch_val <= SIGNED(data_reg(31 downto 16)); + end if; + if(update_right = '1')then + right_s_ch_val <= SIGNED(data_reg(31 downto 16)); + end if; + end if; +end process; + +-- PWM Coding +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + -- Triangle reference signal + if(pwm_s_cnt_dir = '0')then -- Up count + if(pwm_s_cnt >= TO_SIGNED((C_S_CNT_MAX - C_STEP),16))then + pwm_s_cnt_dir <= '1'; + pwm_s_cnt <= pwm_s_cnt - C_STEP; + else + pwm_s_cnt <= pwm_s_cnt + C_STEP; + end if; + else -- Down count + if(pwm_s_cnt <= TO_SIGNED((C_S_CNT_MIN + C_STEP),16))then + pwm_s_cnt_dir <= '0'; + pwm_s_cnt <= pwm_s_cnt + C_STEP; + else + pwm_s_cnt <= pwm_s_cnt - C_STEP; + end if; + end if; + end if; +end process; + +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + -- Comparators + if(left_s_ch_val > pwm_s_cnt)then + pwm_l_out <= '1'; + else + pwm_l_out <= '0'; + end if; + if(right_s_ch_val > pwm_s_cnt)then + pwm_r_out <= '1'; + else + pwm_r_out <= '0'; + end if; + end if; +end process; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/xgui/i2s_to_pwm_v1_0.tcl b/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/xgui/i2s_to_pwm_v1_0.tcl new file mode 100644 index 0000000..3fa319f --- /dev/null +++ b/zynqberrydemo1/ip_lib/i2s_to_pwm_1.0/xgui/i2s_to_pwm_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_PWM_FREQ" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_SYS_FREQ" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_PWM_FREQ { PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to update C_PWM_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_PWM_FREQ { PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to validate C_PWM_FREQ + return true +} + +proc update_PARAM_VALUE.C_SYS_FREQ { PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to update C_SYS_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_SYS_FREQ { PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to validate C_SYS_FREQ + return true +} + + +proc update_MODELPARAM_VALUE.C_SYS_FREQ { MODELPARAM_VALUE.C_SYS_FREQ PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_SYS_FREQ}] ${MODELPARAM_VALUE.C_SYS_FREQ} +} + +proc update_MODELPARAM_VALUE.C_PWM_FREQ { MODELPARAM_VALUE.C_PWM_FREQ PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_PWM_FREQ}] ${MODELPARAM_VALUE.C_PWM_FREQ} +} + diff --git a/zynqberrydemo1/os/petalinux/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h b/zynqberrydemo1/os/petalinux/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h new file mode 100644 index 0000000..18e88e0 --- /dev/null +++ b/zynqberrydemo1/os/petalinux/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h @@ -0,0 +1,175 @@ +/* + * This file is auto-generated by PetaLinux SDK + * DO NOT MODIFY this file, the modification will not persist + */ + +#ifndef __PLNX_CONFIG_H +#define __PLNX_CONFIG_H + +/* Board oscillator frequency */ +#define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400} + +/* use serial multi for all serial devices */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +/* Board name */ + +/* processor - ps7_cortexa9_0 */ +#define CONFIG_CPU_FREQ_HZ 666666687 +#define CONFIG_CLOCKS +#define CONFIG_CMD_CLK +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds" + +/* main_memory - ps7_ddr_0 */ + +/* Memory testing handling */ +#define CONFIG_SYS_MEMTEST_START 0x0 +#define CONFIG_SYS_MEMTEST_END (0x0 + 0x1000) +#define CONFIG_SYS_TEXT_BASE 0x00400000 +#define CONFIG_SYS_LOAD_ADDR 0x0 /* default load address */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* Size of malloc() pool */ +#define SIZE 0xC00000 +#define CONFIG_SYS_MALLOC_LEN SIZE + +/* Physical Memory Map */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* uart - ps7_uart_1 */ +#define CONFIG_ZYNQ_SERIAL +#define PSSERIAL0 "psserial0=setenv stdout ttyPS0;setenv stdin ttyPS0\0" +#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0" +#define CONSOLE_ARG "console=console=ttyPS0,115200\0" +#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0" +#define CONFIG_BAUDRATE 115200 + +/* spi_flash - ps7_qspi_0 */ +#define XILINX_PS7_QSPI_CLK_FREQ_HZ 190476196 +#define CONFIG_SF_DEFAULT_SPEED (XILINX_PS7_QSPI_CLK_FREQ_HZ / 4) +#define CONFIG_SF_DUAL_FLASH +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +/* sdio - ps7_sd_1 */ +#define CONFIG_ZYNQ_SDHCI1 0xE0101000 +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SUPPORT_VFAT +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 + +/* devcfg - ps7_dev_cfg_0 */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA_LOADFS + +/* ps7_scutimer_0 */ +#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) + +/* FPGA */ + +/* Make the BOOTM LEN big enough for the compressed image */ +#define CONFIG_SYS_BOOTM_LEN 0xF000000 + + +/* BOOTP options */ +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/*Command line configuration.*/ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_SAVES + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_LONGHELP + +/* architecture dependent code */ +#define CONFIG_SYS_USR_EXCEP /* user exception */ +#define CONFIG_SYS_HZ 1000 + +/* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Don't define BOOTARGS, we get it from the DTB chosen fragment */ +#undef CONFIG_BOOTARGS + +#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ + +#define CONFIG_LMB + +/* Initial memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ 0x08000000 + +/* PREBOOT */ +#define CONFIG_PREBOOT "echo U-BOOT for petalinux;setenv preboot; echo; " + +/* Extra U-Boot Env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + SERIAL_MULTI \ + CONSOLE_ARG \ + PSSERIAL0 \ + "importbootenv=echo \"Importing environment from SD ...\"; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "loadbootenv=load mmc $sdbootdev:$partid ${loadbootenv_addr} ${bootenv}\0" \ + "sd_uEnvtxt_existence_test=test -e mmc $sdbootdev:$partid /uEnv.txt\0" \ + "uenvboot=" \ + "if run sd_uEnvtxt_existence_test; then" \ + "run loadbootenv" \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv; \0" \ + "sdboot=echo boot Petalinux; run uenvboot ; mmcinfo && fatload mmc 0 ${netstart} ${kernel_img} && bootm \0" \ + "autoload=no\0" \ + "clobstart=0x10000000\0" \ + "netstart=0x10000000\0" \ + "dtbnetstart=0x11800000\0" \ + "loadaddr=0x10000000\0" \ + "boot_img=BOOT.BIN\0" \ + "install_boot=mmcinfo && fatwrite mmc 0 ${clobstart} ${boot_img} ${filesize}\0" \ + "bootenvsize=0x20000\0" \ + "bootenvstart=0x500000\0" \ + "eraseenv=sf probe 0 && sf erase ${bootenvstart} ${bootenvsize}\0" \ + "jffs2_img=rootfs.jffs2\0" \ + "sd_update_jffs2=echo Updating jffs2 from SD; mmcinfo && fatload mmc 0:1 ${clobstart} ${jffs2_img} && run install_jffs2\0" \ + "install_jffs2=sf probe 0 && sf erase ${jffs2start} ${jffs2size} && " \ + "sf write ${clobstart} ${jffs2start} ${filesize}\0" \ + "kernel_img=image.ub\0" \ + "install_kernel=mmcinfo && fatwrite mmc 0 ${clobstart} ${kernel_img} ${filesize}\0" \ + "cp_kernel2ram=mmcinfo && fatload mmc 0 ${netstart} ${kernel_img}\0" \ + "dtb_img=system.dtb\0" \ + "sd_update_dtb=echo Updating dtb from SD; mmcinfo && fatload mmc 0:1 ${clobstart} ${dtb_img} && run install_dtb\0" \ + "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \ + "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \ + "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \ + "default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \ +"" + +/* BOOTCOMMAND */ +#define CONFIG_BOOTCOMMAND "run default_bootcmd" + +#endif /* __PLNX_CONFIG_H */ diff --git a/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c new file mode 100644 index 0000000..4456768 --- /dev/null +++ b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c @@ -0,0 +1,359 @@ +/* +* +* gpio-demo app +* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or (b) that interact +* with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_ROOT "/sys/class/gpio" +#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0])) + +static enum {NONE, IN, OUT, CYLON, KIT} gpio_opt = NONE; + +static const unsigned long cylon[] = { + 0x00000080, 0x00000040, 0x00000020, 0x00000010, + 0x00000008, 0x00000004, 0x00000002, 0x00000001, + 0x00000002, 0x00000004, 0x00000008, + 0x00000010, 0x00000020, 0x00000040, 0x00000080, +}; + +static const unsigned long kit[] = { + 0x000000e0, 0x00000070, 0x00000038, 0x0000001c, + 0x0000000e, 0x00000007, 0x00000003, 0x00000001, + 0x00000003, 0x00000007, 0x0000000e, + 0x0000001c, 0x00000038, 0x00000070, 0x000000e0, +}; + +static int gl_gpio_base = 0; + +static void usage (char *argv0) +{ + char *basename = strrchr(argv0, '/'); + if (!basename) + basename = argv0; + + fprintf(stderr, + "Usage: %s [-g GPIO_BASE] COMMAND\n" + "\twhere COMMAND is one of:\n" + "\t\t-i\t\tInput value from GPIO and print it\n" + "\t\t-o\tVALUE\tOutput value to GPIO\n" + "\t\t-c\t\tCylon test pattern\n" + "\t\t-k\t\t KIT test pattern\n" + "\tGPIO_BASE indicates which GPIO chip to talk to (The number can be \n" + "\tfound at /sys/class/gpio/gpiochipN).\n" + "\tThe highest gpiochipN is the first gpio listed in the dts file, \n" + "\tand the lowest gpiochipN is the last gpio listed in the dts file.\n" + "\tE.g.If the gpiochip240 is the LED_8bit gpio, and I want to output '1' \n" + "\tto the LED_8bit gpio, the command should be:\n" + "\t\tgpio-demo -g 240 -o 1\n" + "\n" + "\tgpio-demo written by Xilinx Inc.\n" + "\n" + , basename); + exit(-2); +} + +static int open_gpio_channel(int gpio_base) +{ + char gpio_nchan_file[128]; + int gpio_nchan_fd; + int gpio_max; + int nchannel; + char nchannel_str[5]; + char *cptr; + int c; + char channel_str[5]; + + char *gpio_export_file = "/sys/class/gpio/export"; + int export_fd=0; + + /* Check how many channels the GPIO chip has */ + sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base); + gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY); + if (gpio_nchan_fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); + return -1; + } + read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str)); + close(gpio_nchan_fd); + nchannel=(int)strtoul(nchannel_str, &cptr, 0); + if (cptr == nchannel_str) { + fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str); + exit(1); + } + + /* Open files for each GPIO channel */ + export_fd=open(gpio_export_file, O_WRONLY); + if (export_fd < 0) { + fprintf(stderr, "Cannot open GPIO to export %d\n", gpio_base); + return -1; + } + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(channel_str, "%d", c); + write(export_fd, channel_str, (strlen(channel_str)+1)); + } + close(export_fd); + return nchannel; +} + +static int close_gpio_channel(int gpio_base) +{ + char gpio_nchan_file[128]; + int gpio_nchan_fd; + int gpio_max; + int nchannel; + char nchannel_str[5]; + char *cptr; + int c; + char channel_str[5]; + + char *gpio_unexport_file = "/sys/class/gpio/unexport"; + int unexport_fd=0; + + /* Check how many channels the GPIO chip has */ + sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base); + gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY); + if (gpio_nchan_fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); + return -1; + } + read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str)); + close(gpio_nchan_fd); + nchannel=(int)strtoul(nchannel_str, &cptr, 0); + if (cptr == nchannel_str) { + fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str); + exit(1); + } + + /* Close opened files for each GPIO channel */ + unexport_fd=open(gpio_unexport_file, O_WRONLY); + if (unexport_fd < 0) { + fprintf(stderr, "Cannot close GPIO by writing unexport %d\n", gpio_base); + return -1; + } + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(channel_str, "%d", c); + write(unexport_fd, channel_str, (strlen(channel_str)+1)); + } + close(unexport_fd); + return 0; +} + +static int set_gpio_direction(int gpio_base, int nchannel, char *direction) +{ + char gpio_dir_file[128]; + int direction_fd=0; + int gpio_max; + int c; + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(gpio_dir_file, "/sys/class/gpio/gpio%d/direction",c); + direction_fd=open(gpio_dir_file, O_RDWR); + if (direction_fd < 0) { + fprintf(stderr, "Cannot open the direction file for GPIO %d\n", c); + return 1; + } + write(direction_fd, direction, (strlen(direction)+1)); + close(direction_fd); + } + return 0; +} + +static int set_gpio_value(int gpio_base, int nchannel, int value) +{ + char gpio_val_file[128]; + int val_fd=0; + int gpio_max; + char val_str[2]; + int c; + + gpio_max = gpio_base + nchannel; + + for(c = gpio_base; c < gpio_max; c++) { + sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c); + val_fd=open(gpio_val_file, O_RDWR); + if (val_fd < 0) { + fprintf(stderr, "Cannot open the value file of GPIO %d\n", c); + return -1; + } + sprintf(val_str,"%d", (value & 1)); + write(val_fd, val_str, sizeof(val_str)); + close(val_fd); + value >>= 1; + } + return 0; +} + +static int get_gpio_value(int gpio_base, int nchannel) +{ + char gpio_val_file[128]; + int val_fd=0; + int gpio_max; + char val_str[2]; + char *cptr; + int value = 0; + int c; + + gpio_max = gpio_base + nchannel; + + for(c = gpio_max-1; c >= gpio_base; c--) { + sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c); + val_fd=open(gpio_val_file, O_RDWR); + if (val_fd < 0) { + fprintf(stderr, "Cannot open GPIO to export %d\n", c); + return -1; + } + read(val_fd, val_str, sizeof(val_str)); + value <<= 1; + value += (int)strtoul(val_str, &cptr, 0); + if (cptr == optarg) { + fprintf(stderr, "Failed to change %s into integer", val_str); + } + close(val_fd); + } + return value; +} + +void signal_handler(int sig) +{ + switch (sig) { + case SIGTERM: + case SIGHUP: + case SIGQUIT: + case SIGINT: + close_gpio_channel(gl_gpio_base); + exit(0) ; + default: + break; + } +} + +int main(int argc, char *argv[]) +{ + extern char *optarg; + char *cptr; + int gpio_value = 0; + int nchannel = 0; + + int c; + int i; + + opterr = 0; + + while ((c = getopt(argc, argv, "g:io:ck")) != -1) { + switch (c) { + case 'g': + gl_gpio_base = (int)strtoul(optarg, &cptr, 0); + if (cptr == optarg) + usage(argv[0]); + break; + case 'i': + gpio_opt = IN; + break; + case 'o': + gpio_opt = OUT; + gpio_value = (int)strtoul(optarg, &cptr, 0); + if (cptr == optarg) + usage(argv[0]); + break; + case 'c': + gpio_opt = CYLON; + break; + case 'k': + gpio_opt = KIT; + break; + case '?': + usage(argv[0]); + default: + usage(argv[0]); + + } + } + + if (gl_gpio_base == 0) { + usage(argv[0]); + } + + nchannel = open_gpio_channel(gl_gpio_base); + signal(SIGTERM, signal_handler); /* catch kill signal */ + signal(SIGHUP, signal_handler); /* catch hang up signal */ + signal(SIGQUIT, signal_handler); /* catch quit signal */ + signal(SIGINT, signal_handler); /* catch a CTRL-c signal */ + switch (gpio_opt) { + case IN: + set_gpio_direction(gl_gpio_base, nchannel, "in"); + gpio_value=get_gpio_value(gl_gpio_base, nchannel); + fprintf(stdout,"0x%08X\n", gpio_value); + break; + case OUT: + set_gpio_direction(gl_gpio_base, nchannel, "out"); + set_gpio_value(gl_gpio_base, nchannel, gpio_value); + break; + case CYLON: +#define CYLON_DELAY_USECS (10000) + set_gpio_direction(gl_gpio_base, nchannel, "out"); + for (;;) { + for(i=0; i < ARRAY_SIZE(cylon); i++) { + gpio_value=(int)cylon[i]; + set_gpio_value(gl_gpio_base, nchannel, gpio_value); + } + usleep(CYLON_DELAY_USECS); + } + case KIT: +#define KIT_DELAY_USECS (10000) + set_gpio_direction(gl_gpio_base, nchannel, "out"); + for (;;) { + for (i=0; i +#include +#include +#include +#include + +void usage(char *prog) +{ + printf("usage: %s ADDR\n",prog); + printf("\n"); + printf("ADDR may be specified as hex values\n"); +} + + +int main(int argc, char *argv[]) +{ + int fd; + void *ptr; + unsigned addr, page_addr, page_offset; + unsigned page_size=sysconf(_SC_PAGESIZE); + + if(argc!=2) { + usage(argv[0]); + exit(-1); + } + + fd=open("/dev/mem",O_RDONLY); + if(fd<1) { + perror(argv[0]); + exit(-1); + } + + addr=strtoul(argv[1],NULL,0); + page_addr=(addr & ~(page_size-1)); + page_offset=addr-page_addr; + + ptr=mmap(NULL,page_size,PROT_READ,MAP_SHARED,fd,(addr & ~(page_size-1))); + if((int)ptr==-1) { + perror(argv[0]); + exit(-1); + } + + printf("0x%08x\n",*((unsigned *)(ptr+page_offset))); + return 0; +} + + diff --git a/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c new file mode 100644 index 0000000..e1b2f16 --- /dev/null +++ b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c @@ -0,0 +1,81 @@ +/* +* poke utility - for those who remember the good old days! +* + +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or (b) that interact +* with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include + +void usage(char *prog) +{ + printf("usage: %s ADDR VAL\n",prog); + printf("\n"); + printf("ADDR and VAL may be specified as hex values\n"); +} + +int main(int argc, char *argv[]) +{ + int fd; + void *ptr; + unsigned val; + unsigned addr, page_addr, page_offset; + unsigned page_size=sysconf(_SC_PAGESIZE); + + fd=open("/dev/mem",O_RDWR); + if(fd<1) { + perror(argv[0]); + exit(-1); + } + + if(argc!=3) { + usage(argv[0]); + exit(-1); + } + + addr=strtoul(argv[1],NULL,0); + val=strtoul(argv[2],NULL,0); + + page_addr=(addr & ~(page_size-1)); + page_offset=addr-page_addr; + + ptr=mmap(NULL,page_size,PROT_READ|PROT_WRITE,MAP_SHARED,fd,(addr & ~(page_size-1))); + if((int)ptr==-1) { + perror(argv[0]); + exit(-1); + } + + *((unsigned *)(ptr+page_offset))=val; + return 0; +} diff --git a/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/rpicam.c b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/rpicam.c new file mode 100644 index 0000000..24cd13c --- /dev/null +++ b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/rpicam.c @@ -0,0 +1,191 @@ +/* +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko + */ +#include +#include +#include +#include +#include +#include +#include +#include "sensor_config.h" + +#define CAMERA_V1_3_IIC_ADDRESS 0x36 +#define CAMERA_V2_1_IIC_ADDRESS 0x10 + +#define CS_CMMN_CHIP_ID_H 0x300A +#define CS_CMMN_CHIP_ID_L 0x300B + +unsigned char i2c_reg_read(int dev_file, unsigned char dev_addr, const unsigned short reg_addr){ + __u8 inbuf[2]; + __u8 outbuf[2]; + struct i2c_rdwr_ioctl_data packets; + struct i2c_msg messages[2]; + + /* + * In order to read a register, we first do a "dummy write" by writing + * 0 bytes to the register we want to read from. This is similar to + * the packet in set_i2c_register, except it's 1 byte rather than 2. + */ + outbuf[0] = reg_addr >> 8; + outbuf[1] = reg_addr & 0xFF; + messages[0].addr = dev_addr; + messages[0].flags = 0; + messages[0].len = 2, //sizeof(outbuf); + messages[0].buf = &outbuf; + /* The data will get returned in this structure */ + messages[1].addr = dev_addr; + messages[1].flags = I2C_M_RD; /* | I2C_M_NOSTART*/ + messages[1].len = 1, //sizeof(inbuf); + messages[1].buf = inbuf; + + /* Send the request to the kernel and get the result back */ + packets.msgs = messages; + packets.nmsgs = 2; + if(ioctl(dev_file, I2C_RDWR, &packets) < 0) { + perror("Unable to send data"); + return 1; + } + + return inbuf[0]; +} + +int i2c_reg_write(int dev_file, unsigned char dev_addr, unsigned short reg_addr, unsigned char reg_data) +{ + unsigned char outbuf[3]; + struct i2c_rdwr_ioctl_data packets; + struct i2c_msg messages[1]; + + messages[0].addr = dev_addr; + messages[0].flags = 0; + messages[0].len = sizeof(outbuf); + messages[0].buf = &outbuf; + /* The first byte indicates which register we'll write */ + outbuf[0] = reg_addr >> 8; + outbuf[1] = reg_addr & 0xFF; + outbuf[2] = reg_data; + /* Transfer the i2c packets to the kernel and verify it worked */ + packets.msgs = messages; + packets.nmsgs = 1; + if(ioctl(dev_file, I2C_RDWR, &packets) < 0) { + perror("Unable to send data"); + return 1; + } + + return 0; +} + +static void i2c_set_write(int dev_file, unsigned char dev_addr, struct sensor_cmd *set){ + int i; + for(i=0; set[i].reg != TABLE_END; i++){ + i2c_reg_write(dev_file, dev_addr, set[i].reg, set[i].val); + } +} + +static void imx219_crop(int dev_file, unsigned char dev_addr, struct sensor_rect crop_rect){ + i2c_reg_write(dev_file, dev_addr, 0x0164, crop_rect.left >> 8); + i2c_reg_write(dev_file, dev_addr, 0x0165, crop_rect.left & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x0166, (crop_rect.width - 1) >> 8); + i2c_reg_write(dev_file, dev_addr, 0x0167, (crop_rect.width - 1) & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x0168, crop_rect.top >> 8); + i2c_reg_write(dev_file, dev_addr, 0x0169, crop_rect.top & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x016A, (crop_rect.height - 1) >> 8); + i2c_reg_write(dev_file, dev_addr, 0x016B, (crop_rect.height - 1) & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x016C, crop_rect.width >> 8); + i2c_reg_write(dev_file, dev_addr, 0x016D, crop_rect.width & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x016E, crop_rect.height >> 8); + i2c_reg_write(dev_file, dev_addr, 0x016F, crop_rect.height & 0xff); +} + + +int main(int argc, char *argv[]) +{ + int i2c_file; + unsigned short model_id; + unsigned int lot_id; + unsigned short chip_id; + unsigned char ret; + + printf("Raspberry Pi Camera Init v1.3\n"); + if(argc < 2){ + printf("%s /dev/i2c-X [mode]\n",argv[0]); + return 0; + } + + if ((i2c_file = open(argv[1], O_RDWR)) < 0) { + perror("Unable to open i2c control file"); + return 0; + } + + if(!((i2c_reg_read(i2c_file, CAMERA_V1_3_IIC_ADDRESS, CS_CMMN_CHIP_ID_H) != 0x56) || (i2c_reg_read(i2c_file, CAMERA_V1_3_IIC_ADDRESS, CS_CMMN_CHIP_ID_L) != 0x47))){ + printf("Camera V1.X configuration\n"); + i2c_reg_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, 0x0100, 0x00); // Disable + i2c_reg_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, 0x0103, 0x01); // Reset + usleep(1); // Wait + i2c_reg_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, 0x0103, 0x00); // Reset + usleep(10 * 1000); // Wait + i2c_set_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, ov5647_sensor_common_10bit); // Load common configuration + i2c_set_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, ov5647_sensor_1296_968_30); // Load specific configuration + i2c_reg_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, 0x0100, 0x01); // Enable + printf("Camera init complete.\n"); + close(i2c_file); + return 1; + } + + printf("Camera V2.X configuration\n"); + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0000); + if (ret < 0) { + perror("Failure to read Model ID (high byte)\n"); + return 0; + } + model_id = ret << 8; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0001); + if (ret < 0) { + perror("Failure to read Model ID (low byte)\n"); + return 0; + } + model_id |= ret; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0004); + if (ret < 0) { + perror("Failure to read Lot ID (high byte)\n"); + return 0; + } + lot_id = ret << 16; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0005); + if (ret < 0) { + perror("Failure to read Lot ID (mid byte)\n"); + return 0; + } + lot_id |= ret << 8; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0006); + if (ret < 0) { + perror("Failure to read Lot ID (low byte)\n"); + return 0; + } + lot_id |= ret; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x000D); + if (ret < 0) { + perror("Failure to read Chip ID (high byte)\n"); + return 0; + } + chip_id = ret << 8; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x000E); + if (ret < 0) { + perror("Failure to read Chip ID (low byte)\n"); + return 0; + } + chip_id |= ret; + if (model_id != 0x0219) { + perror("Model not supported!\n"); + return 0; + } + + printf("Found 2.X Camera Model ID 0x%04x, Lot ID 0x%06x, Chip ID 0x%04x\n", model_id, lot_id, chip_id); + i2c_set_write(i2c_file, CAMERA_V2_1_IIC_ADDRESS, imx219_720p_regs); + printf("Camera init complete.\n"); + + close(i2c_file); + return 3; +} + diff --git a/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/sensor_config.h b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/sensor_config.h new file mode 100644 index 0000000..8f062a5 --- /dev/null +++ b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/sensor_config.h @@ -0,0 +1,705 @@ + +#ifndef SENSOR_CONFIG_H_ +#define SENSOR_CONFIG_H_ + + +#define TABLE_END 0xffff + +//----------------------------------------------------------------------------------------- + +// atomar register element +struct sensor_cmd { + unsigned short reg; + unsigned char val; +}; + +//----------------------------------------------------------------------------------------- + +static struct sensor_cmd ov5647_sensor_common_10bit[] = { + { 0x3034, 0x1A }, // 10 bit mode +// { 0x3034, 0x10 }, // 8 bit mode + { 0x503D, 0x00 }, // Test Pattern + { 0x3035, 0x21 }, // CLK DIV + { 0x3036, 0x46 }, // PLL MULT + { 0x303c, 0x11 }, // PLLS CP + { 0x3106, 0xf5 }, // PLL DIV + { 0x3821, 0x07 }, // TIMING TC + { 0x3820, 0x41 }, // TIMING TC + { 0x3827, 0xec }, + { 0x370c, 0x0f }, + { 0x3612, 0x59 }, + { 0x3503, 0x00 }, // AEC/AGC + { 0x5000, 0x89 }, // Lens Correction + { 0x5001, 0x01 }, // AWB + { 0x5002, 0x41 }, // AWB GAIN, OPT, WIN + { 0x5003, 0x0A }, // BIN + { 0x5a00, 0x08 }, + { 0x3000, 0x00 }, + { 0x3001, 0x00 }, + { 0x3002, 0x00 }, + { 0x3016, 0x08 }, + { 0x3017, 0xe0 }, + { 0x3018, 0x44 }, + { 0x301c, 0xf8 }, + { 0x301d, 0xf0 }, + { 0x3a18, 0x00 }, + { 0x3a19, 0xf8 }, + { 0x3c01, 0x80 }, // 50/60HZ Detection + { 0x3b07, 0x0c }, + { 0x380c, 0x07 }, + { 0x380d, 0x68 }, + { 0x380e, 0x03 }, + { 0x380f, 0xd8 }, + { 0x3814, 0x31 }, + { 0x3815, 0x31 }, + { 0x3708, 0x64 }, + { 0x3709, 0x52 }, + { 0x3630, 0x2e }, + { 0x3632, 0xe2 }, + { 0x3633, 0x23 }, + { 0x3634, 0x44 }, + { 0x3636, 0x06 }, + { 0x3620, 0x65 }, // V BINNING + { 0x3621, 0xe1 }, // H BINNING + { 0x3600, 0x37 }, + { 0x3704, 0xa0 }, + { 0x3703, 0x5a }, + { 0x3715, 0x78 }, + { 0x3717, 0x01 }, + { 0x3731, 0x02 }, + { 0x370b, 0x60 }, + { 0x3705, 0x1a }, + { 0x3f05, 0x02 }, + { 0x3f06, 0x10 }, + { 0x3f01, 0x0a }, + { 0x3a08, 0x01 }, + { 0x3a09, 0x27 }, + { 0x3a0a, 0x00 }, + { 0x3a0b, 0xf6 }, + { 0x3a0d, 0x04 }, + { 0x3a0e, 0x03 }, + { 0x3a0f, 0x58 }, + { 0x3a10, 0x50 }, + { 0x3a1b, 0x58 }, + { 0x3a1e, 0x50 }, + { 0x3a11, 0x60 }, + { 0x3a1f, 0x28 }, + { 0x4001, 0x02 }, + { 0x4004, 0x02 }, + { 0x4000, 0x09 }, + { 0x4837, 0x24 }, + { 0x4050, 0x6e }, + { 0x4051, 0x8f }, + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +static struct sensor_cmd ov5647_sensor_common_test[] = { + { 0x3034, 0x1A }, // 10 bit mode + { 0x503D, 0x80 }, +// { 0x3035, 0x21 }, +// { 0x3036, 0x46 }, +// { 0x303c, 0x11 }, + { 0x3106, 0xf5 }, +// { 0x3821, 0x07 }, +// { 0x3820, 0x41 }, + { 0x3827, 0xec }, + { 0x370c, 0x0f }, +// { 0x3612, 0x59 }, +// { 0x3618, 0x00 }, + { 0x5000, 0x06 }, + { 0x5001, 0x00 }, + { 0x5002, 0x40 }, + { 0x5003, 0x08 }, + { 0x5a00, 0x08 }, + { 0x3000, 0x00 }, + { 0x3001, 0x00 }, + { 0x3002, 0x00 }, + { 0x3016, 0x08 }, + { 0x3017, 0xe0 }, + { 0x3018, 0x44 }, + { 0x301c, 0xf8 }, + { 0x301d, 0xf0 }, + { 0x3a18, 0x00 }, + { 0x3a19, 0xf8 }, + { 0x3c01, 0x80 }, + { 0x3b07, 0x0c }, +// { 0x380c, 0x07 }, +// { 0x380d, 0x68 }, +// { 0x380e, 0x03 }, +// { 0x380f, 0xd8 }, +// { 0x3814, 0x31 }, +// { 0x3815, 0x31 }, +// { 0x3708, 0x64 }, +// { 0x3709, 0x52 }, + { 0x3630, 0x2e }, + { 0x3632, 0xe2 }, + { 0x3633, 0x23 }, + { 0x3634, 0x44 }, + { 0x3636, 0x06 }, + { 0x3620, 0x64 }, + { 0x3621, 0xe0 }, + { 0x3600, 0x37 }, + { 0x3704, 0xa0 }, + { 0x3703, 0x5a }, + { 0x3715, 0x78 }, + { 0x3717, 0x01 }, + { 0x3731, 0x02 }, + { 0x370b, 0x60 }, + { 0x3705, 0x1a }, + { 0x3f05, 0x02 }, + { 0x3f06, 0x10 }, + { 0x3f01, 0x0a }, +// { 0x3a08, 0x01 }, +// { 0x3a09, 0x27 }, +// { 0x3a0a, 0x00 }, +// { 0x3a0b, 0xf6 }, +// { 0x3a0d, 0x04 }, +// { 0x3a0e, 0x03 }, + { 0x3a0f, 0x58 }, + { 0x3a10, 0x50 }, + { 0x3a1b, 0x58 }, + { 0x3a1e, 0x50 }, + { 0x3a11, 0x60 }, + { 0x3a1f, 0x28 }, + { 0x4001, 0x02 }, +// { 0x4004, 0x02 }, + { 0x4000, 0x09 }, +// { 0x4837, 0x24 }, + { 0x4050, 0x6e }, + { 0x4051, 0x8f }, + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +/* 2592 x 1944 @ 15 fps */ + /* + * MIPI Link : 425.000 Mbps + * Pixel clock : 85.000 MHz + * Timing zone : 2752 x 1974 + * FPS : 15.6 + */ +static struct sensor_cmd ov5647_sensor_2592_1944_15[] = { + { 0x3035, 0x21 }, + { 0x3036, 0x66 }, + { 0x303c, 0x11 }, + { 0x3821, 0x06 }, + { 0x3820, 0x00 }, + { 0x3612, 0x5b }, + { 0x3618, 0x04 }, + { 0x380c, 0x0a }, + { 0x380d, 0xc0 }, + { 0x380e, 0x07 }, + { 0x380f, 0xb6 }, + { 0x3814, 0x11 }, + { 0x3815, 0x11 }, + { 0x3708, 0x64 }, + { 0x3709, 0x12 }, + { 0x3808, 0x0a }, + { 0x3809, 0x20 }, + { 0x380a, 0x07 }, + { 0x380b, 0x98 }, + { 0x3800, 0x00 }, + { 0x3801, 0x0c }, + { 0x3802, 0x00 }, + { 0x3803, 0x02 }, + { 0x3804, 0x0a }, + { 0x3805, 0x33 }, + { 0x3806, 0x07 }, + { 0x3807, 0xa1 }, + { 0x3a08, 0x01 }, + { 0x3a09, 0x28 }, + { 0x3a0a, 0x00 }, + { 0x3a0b, 0xf6 }, + { 0x3a0d, 0x07 }, + { 0x3a0e, 0x06 }, + { 0x4004, 0x04 }, + { 0x4837, 0x19 }, + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +/* 1936 x 1088 @ 30 fps */ + /* + * MIPI Link : 416.667 Mbps + * Pixel clock : 83.333 MHz + * Timing zone : 2416 x 1104 + * FPS : 31.2 + */ +static struct sensor_cmd ov5647_sensor_1936_1088_30[] = { + { 0x3035, 0x21 }, + { 0x3036, 0x64 }, + { 0x303c, 0x11 }, + { 0x3821, 0x06 }, + { 0x3820, 0x00 }, + { 0x3612, 0x5b }, + { 0x3618, 0x04 }, + { 0x380c, 0x09 }, + { 0x380d, 0x70 }, + { 0x380e, 0x04 }, + { 0x380f, 0x50 }, + { 0x3814, 0x11 }, + { 0x3815, 0x11 }, + { 0x3708, 0x64 }, + { 0x3709, 0x12 }, + { 0x3808, 0x07 }, + { 0x3809, 0x90 }, /* 80 */ + { 0x380a, 0x04 }, + { 0x380b, 0x40 }, /* 38 */ + { 0x3800, 0x01 }, + { 0x3801, 0x54 }, /* 5c */ + { 0x3802, 0x01 }, + { 0x3803, 0xb0 }, /* b2 */ + { 0x3804, 0x08 }, + { 0x3805, 0xeb }, /* e3 */ + { 0x3806, 0x05 }, + { 0x3807, 0xf3 }, /* f1 */ + { 0x3a08, 0x01 }, + { 0x3a09, 0x4b }, + { 0x3a0a, 0x01 }, + { 0x3a0b, 0x13 }, + { 0x3a0d, 0x04 }, + { 0x3a0e, 0x03 }, + { 0x4004, 0x04 }, + { 0x4837, 0x19 }, + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +/* 1296 x 968 @ 30 fps */ + /* + * MIPI Link : 291.667 Mbps + * Pixel clock : 58.333 MHz + * Timing zone : 1896 x 984 + * FPS : 31.3 + */ +static struct sensor_cmd ov5647_sensor_1296_968_30[] = { + { 0x3035, 0x21 }, + { 0x3036, 0x46 }, + { 0x303c, 0x11 }, + { 0x3821, 0x07 }, + { 0x3820, 0x41 }, + { 0x3612, 0x59 }, + { 0x3618, 0x00 }, + { 0x380c, 0x07 }, + { 0x380d, 0x68 }, + { 0x380e, 0x03 }, + { 0x380f, 0xd8 }, + { 0x3814, 0x31 }, + { 0x3815, 0x31 }, + { 0x3708, 0x64 }, + { 0x3709, 0x52 }, + { 0x3808, 0x05 }, + { 0x3809, 0x10 }, /* 00 */ + { 0x380a, 0x03 }, + { 0x380b, 0xc8 }, /* c0 */ + { 0x3800, 0x00 }, + { 0x3801, 0x00 }, /* 18 */ + { 0x3802, 0x00 }, + { 0x3803, 0x08 }, /* 0e */ + { 0x3804, 0x0a }, + { 0x3805, 0x3b }, /* 27 */ + { 0x3806, 0x07 }, + { 0x3807, 0x9b }, /* 95 */ + { 0x3a08, 0x01 }, + { 0x3a09, 0x27 }, + { 0x3a0a, 0x00 }, + { 0x3a0b, 0xf6 }, + { 0x3a0d, 0x04 }, + { 0x3a0e, 0x03 }, + { 0x4004, 0x02 }, + { 0x4837, 0x24 }, + + { 0x5001, 0x01 }, // AWB on + { 0x5002, 0x41 }, // AWB on + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +/* 1280 x 720 @ 30 fps */ + /* + * MIPI Link : 291.667 Mbps + * Pixel clock : 58.333 MHz + * Timing zone : 1896 x 984 + * FPS : 31.3 + */ +static struct sensor_cmd ov5647_sensor_1280_720_30[] = { + { 0x3035, 0x21 }, // * + { 0x3036, 0x46 }, // * PLL multiplier + { 0x303c, 0x11 }, // * PLL div + { 0x3821, 0x07 }, // * Timing + { 0x3820, 0x41 }, // * Timing + { 0x3612, 0x59 }, // ? + { 0x3618, 0x00 }, // ? + { 0x380c, 0x07 }, // * Horisontal size [12:8] 1896 + { 0x380d, 0x68 }, // * Horisontal size [7:0] + { 0x380e, 0x03 }, // * total vertical size [9:8] 984 + { 0x380f, 0xd8 }, // * total vertical size [7:0] + { 0x3814, 0x31 }, // * timing x inc + { 0x3815, 0x31 }, // * timing y inc + { 0x3708, 0x64 }, // + { 0x3709, 0x52 }, // + { 0x3808, 0x05 }, // out horisontal [11:8] 1280 + { 0x3809, 0x00 }, // out horisontal [7:0] + { 0x380a, 0x02 }, // out vertical [11:8] 720 + { 0x380b, 0xd0 }, // out vertical [7:0] + { 0x3800, 0x00 }, // + X start [11:8] + { 0x3801, 0x00 }, // + X start [7:0] /* 18 */ + { 0x3802, 0x00 }, // + Y start [11:8] + { 0x3803, 0x08 }, // + Y start [7:0] /* 0e */ + { 0x3804, 0x0a }, // + X end [11:8] + { 0x3805, 0x3b }, // + X end [7:0] /* 27 */ + { 0x3806, 0x07 }, // + Y end [11:8] + { 0x3807, 0x9b }, // + Y end [7:0] /* 95 */ + { 0x3a08, 0x01 }, // + { 0x3a09, 0x27 }, // + { 0x3a0a, 0x00 }, // + { 0x3a0b, 0xf6 }, // + { 0x3a0d, 0x04 }, // + { 0x3a0e, 0x03 }, // + { 0x4004, 0x02 }, // + { 0x4837, 0x24 }, // * PCLK period + + { 0x5001, 0x01 }, // AWB on + { 0x5002, 0x41 }, // AWB on + + { TABLE_END, 0x00 }, // +}; + +//----------------------------------------------------------------------------------------- + +static struct sensor_cmd ov5647_sensor_640_480_90[] = { + { 0x3035, 0x11 }, + { 0x3036, 0x2a }, + { 0x3821, 0x07 }, + { 0x3820, 0x41 }, + { 0x3612, 0x49 }, + { 0x3618, 0x00 }, + { 0x380c, 0x07 }, + { 0x380d, 0x30 }, + { 0x380e, 0x01 }, + { 0x380f, 0x78 }, + { 0x3814, 0x71 }, + { 0x3815, 0x31 }, + { 0x3709, 0x52 }, + { 0x3808, 0x02 }, + { 0x3809, 0x80 }, + { 0x380a, 0x01 }, + { 0x380b, 0xe8 }, + { 0x3800, 0x00 }, + { 0x3801, 0x10 }, + { 0x3802, 0x00 }, + { 0x3803, 0x00 }, + { 0x3804, 0x0a }, + { 0x3805, 0x2f }, + { 0x3806, 0x07 }, + { 0x3807, 0x9f }, + { 0x4004, 0x02 }, + { TABLE_END, 0x00 }, // +}; + +//----------------------------------------------------------------------------------------- +static const struct sensor_cmd imx219_miscellaneous[] = { + { 0x30EB, 0x05 }, /* Access Code for address over 0x3000 */ + { 0x30EB, 0x0C }, /* Access Code for address over 0x3000 */ + { 0x300A, 0xFF }, /* Access Code for address over 0x3000 */ + { 0x300B, 0xFF }, /* Access Code for address over 0x3000 */ + { 0x30EB, 0x05 }, /* Access Code for address over 0x3000 */ + { 0x30EB, 0x09 }, /* Access Code for address over 0x3000 */ + { 0x0114, 0x03 }, /* CSI_LANE_MODE[1:0} */ + { 0x0128, 0x00 }, /* DPHY_CNTRL */ + { 0x012A, 0x18 }, /* EXCK_FREQ[15:8] */ + { 0x012B, 0x00 }, /* EXCK_FREQ[7:0] */ + { 0x0160, 0x0A }, /* FRM_LENGTH_A[15:8] */ + { 0x0161, 0x83 }, /* FRM_LENGTH_A[7:0] */ + { 0x0162, 0x0D }, /* LINE_LENGTH_A[15:8] */ + { 0x0163, 0x78 }, /* LINE_LENGTH_A[7:0] */ + { 0x0170, 0x01 }, /* X_ODD_INC_A[2:0] */ + { 0x0171, 0x01 }, /* Y_ODD_INC_A[2:0] */ + { 0x0174, 0x00 }, /* BINNING_MODE_H_A */ + { 0x0175, 0x00 }, /* BINNING_MODE_V_A */ + { 0x018C, 0x0A }, /* CSI_DATA_FORMAT_A[15:8] */ + { 0x018D, 0x0A }, /* CSI_DATA_FORMAT_A[7:0] */ + { 0x0301, 0x05 }, /* VTPXCK_DIV */ + { 0x0303, 0x01 }, /* VTSYCK_DIV */ + { 0x0304, 0x03 }, /* PREPLLCK_VT_DIV[3:0] */ + { 0x0305, 0x03 }, /* PREPLLCK_OP_DIV[3:0] */ + { 0x0306, 0x00 }, /* PLL_VT_MPY[10:8] */ + { 0x0307, 0x57 }, /* PLL_VT_MPY[7:0] */ + { 0x0309, 0x0A }, /* OPPXCK_DIV[4:0] */ + { 0x030B, 0x01 }, /* OPSYCK_DIV */ + { 0x030C, 0x00 }, /* PLL_OP_MPY[10:8] */ + { 0x030D, 0x5A }, /* PLL_OP_MPY[7:0] */ + { 0x455E, 0x00 }, /* CIS Tuning */ + { 0x471E, 0x4B }, /* CIS Tuning */ + { 0x4767, 0x0F }, /* CIS Tuning */ + { 0x4750, 0x14 }, /* CIS Tuning */ + { 0x4540, 0x00 }, /* CIS Tuning */ + { 0x47B4, 0x14 }, /* CIS Tuning */ + { 0x4713, 0x30 }, /* CIS Tuning */ + { 0x478B, 0x10 }, /* CIS Tuning */ + { 0x478F, 0x10 }, /* CIS Tuning */ + { 0x4793, 0x10 }, /* CIS Tuning */ + { 0x4797, 0x0E }, /* CIS Tuning */ + { 0x479B, 0x0E }, /* CIS Tuning */ + { TABLE_END, 0x00 } +}; +/* 3280x2464@15 FPS */ +static const struct sensor_cmd imx219_1test[] = { + {0x0100, 0x00}, // 0=OFF, 1=Stream, 2=MAX + {0x30EB, 0x05}, + {0x30EB, 0x0C}, + {0x300A, 0xFF}, + {0x300B, 0xFF}, + {0x30EB, 0x05}, + {0x30EB, 0x09}, + {0x0114, 0x01}, // CSI MIPI Lanes [1:0] (0x01=2, 0x03=4) + {0x0128, 0x00}, // DPHY_CNTRL + {0x012A, 0x18}, // EXCK_FREQ [15:8] + {0x012B, 0x00}, // EXCK_FREQ [7:0] + {0x0157, 0x00}, // Analog Gain + {0x0158, 0x00}, // Digital Gain [15:8] + {0x0159, 0x00}, // Digital Gain [7:0] + // {0x015A, 0x01}, // Shutter/Integration Time [15:8] + // {0x015B, 0x00}, // Shutter/Integration Time [7:0] + {0x0160, 0x09}, // Frame Length [15:8] + {0x0161, 0xC8}, // Frame Length [7:0] + {0x0162, 0x0D}, // Line Length [15:8] + {0x0163, 0x78}, // Line Length [7:0] + {0x0164, 0x00}, + {0x0165, 0x00}, + {0x0166, 0x0C}, + {0x0167, 0xCF}, + {0x0168, 0x00}, + {0x0169, 0x00}, + {0x016A, 0x09}, + {0x016B, 0x9F}, + {0x016C, 0x0C}, + {0x016D, 0xD0}, + {0x016E, 0x09}, + {0x016F, 0xA0}, + {0x0170, 0x01}, // X_ODD_INC [2:0] + {0x0171, 0x01}, // Y_ODD_INC [2:0] + {0x0172, 0x03}, + {0x0174, 0x00}, // Binning Mode H_A + {0x0175, 0x00}, // Binning Mode V_A + {0x018C, 0x0A}, // CSI Data Format [15:8] + {0x018D, 0x0A}, // CSI Data Format [7:0] + {0x0301, 0x05}, // VTPXCK_DIV + {0x0303, 0x01}, // VTSYCK_DIV + {0x0304, 0x03}, // PREPLLCK_VT_DIV [3:0] + {0x0305, 0x03}, // PREPLLCK_OP_DIV [3:0] + {0x0306, 0x00}, // PLL_VT_MPY [10:8] + {0x0307, 0x2B}, // PLL_VT_MPY [7:0] + {0x0309, 0x0A}, // OPPXCK_DIV [4:0] + {0x030B, 0x01}, // OPSYCK_DIV + {0x030C, 0x00}, // PLL_OP_MPY [10:8] + {0x030D, 0x55}, // PLL_OP_MPY [7:0] + {0x455E, 0x00}, // CIS Tuning ? + {0x471E, 0x4B}, // CIS Tuning ? + {0x4767, 0x0F}, // CIS Tuning ? + {0x4750, 0x14}, // CIS Tuning ? + {0x4540, 0x00}, // CIS Tuning ? + {0x47B4, 0x14}, // CIS Tuning ? + {0x4713, 0x30}, // CIS Tuning ? + {0x478B, 0x10}, // CIS Tuning ? + {0x478F, 0x10}, // CIS Tuning ? + {0x4797, 0x0E}, // CIS Tuning ? + {0x479B, 0x0E}, // CIS Tuning ? + {TABLE_END, 0x00} +}; + +static struct sensor_cmd imx219_720p_regs[] = { //720: 1280*720@30fps + {0x30EB, 0x05}, + {0x30EB, 0x0C}, + {0x300A, 0xFF}, + {0x300B, 0xFF}, + {0x30EB, 0x05}, + {0x30EB, 0x09}, + + {0x0114, 0x01}, // CSI_LANE_MODE = 2-lane + {0x0128, 0x00}, // DPHY_CTRL = auto mode + + {0x012A, 0x13}, // EXCLK_FREQ[15:8] + {0x012B, 0x34}, // EXCLK_FREQ[7:0] = 4916 MHz + + {0x0160, 0x04}, // FRM_LENGTH_A[15:8] + {0x0161, 0x60}, // FRM_LENGTH_A[7:0] = 1120 + {0x0162, 0x0D}, // LINE_LENGTH_A[15:8] + {0x0163, 0x78}, // LINE_LENGTH_A[7:0] = 3448 + {0x0164, 0x01}, // XADD_STA_A[11:8] + {0x0165, 0x58}, // XADD_STA_A[7:0] = X top left = 344 + {0x0166, 0x0B}, // XADD_END_A[11:8] + {0x0167, 0x77}, // XADD_END_A[7:0] = X bottom right = 2935 + {0x0168, 0x01}, // YADD_STA_A[11:8] + {0x0169, 0xF0}, // YADD_STA_A[7:0] = Y top left = 496 + {0x016A, 0x07}, // YADD_END_A[11:8] + {0x016B, 0xAF}, // YADD_END_A[7:0] = Y bottom right = 1967 + {0x016C, 0x05}, // x_output_size[11:8] + {0x016D, 0x10}, // x_output_size[7:0] = 1296 + {0x016E, 0x02}, // y_output_size[11:8] + {0x016F, 0xE0}, // y_output_size[7:0] = 736 + {0x0170, 0x01}, // X_ODD_INC_A + {0x0171, 0x01}, // Y_ODD_INC_A + {0x0174, 0x01}, // BINNING_MODE_H_A = x2-binning + {0x0175, 0x01}, // BINNING_MODE_V_A = x2-binning +// {0x0174, 0x00}, // BINNING_MODE_H_A = no-binning +// {0x0175, 0x00}, // BINNING_MODE_V_A = no-binning + {0x0176, 0x01}, // BINNING_CAL_MODE_H_A + {0x0177, 0x01}, // BINNING_CAL_MODE_V_A + {0x018C, 0x0A}, // CSI_DATA_FORMAT_A[15:8] + {0x018D, 0x0A}, // CSI_DATA_FORMAT_A[7:0] + {0x0301, 0x05}, + {0x0303, 0x01}, + {0x0304, 0x02}, + {0x0305, 0x02}, + {0x0309, 0x0A}, // OPPXCK_DIV + {0x030B, 0x01}, // OPSYCK_DIV + + {0x0306, 0x00}, // PLL_VT_MPY[10:8] + //{0x0307, 0x2E}, // PLL_VT_MPY[7:0] = 46 + {0x0307, 0x17}, // PLL_VT_MPY[7:0] = 23 + //{0x0307, 0x0F}, // PLL_VT_MPY[7:0] = 15 + + {0x030C, 0x00}, // PLL_OP_MPY[10:8] + //{0x030D, 0x5C}, // PLL_OP_MPY[7:0] = 92 + {0x030D, 0x2E}, // PLL_OP_MPY[7:0] = 46 + //{0x030D, 0x1E}, // PLL_OP_MPY[7:0] = 30 + + {0x455E, 0x00}, + {0x471E, 0x4B}, + {0x4767, 0x0F}, + {0x4750, 0x14}, + {0x4540, 0x00}, + {0x47B4, 0x14}, + {0x4713, 0x30}, + {0x478B, 0x10}, + {0x478F, 0x10}, + {0x4793, 0x10}, + {0x4797, 0x0E}, + {0x479B, 0x0E}, + //{0x0601, 0x02}, // Test pattern = Color bar + {0x0601, 0x00}, // Test pattern = Normal work + {0x0620, 0x00}, // TP_WINDOW_X_OFFSET[11:8] + {0x0621, 0x00}, // TP_WINDOW_X_OFFSET[7:0] + {0x0621, 0x00}, // TP_WINDOW_Y_OFFSET[11:8] + {0x0623, 0x00}, // TP_WINDOW_Y_OFFSET[7:0] + {0x0624, 0x05}, // TP_WINDOW_WIDTH[11:8] + {0x0625, 0x00}, // TP_WINDOW_WIDTH[7:0] = 1280 + {0x0626, 0x02}, // TP_WINDOW_HEIGHT[11:8] + {0x0627, 0xD0}, // TP_WINDOW_HEIGHT[7:0] = 720 + {0x0100, 0x01}, /* mode select streaming on */ + {TABLE_END, 0x00} +}; + +static struct sensor_cmd imx219_720p_45fps_regs[] = { //720: 1280*720@45fps + {0x30EB, 0x05}, + {0x30EB, 0x0C}, + {0x300A, 0xFF}, + {0x300B, 0xFF}, + {0x30EB, 0x05}, + {0x30EB, 0x09}, + + {0x0114, 0x01}, + {0x0128, 0x00}, + + {0x012A, 0x13}, // EXCLK_FREQ[15:8] + {0x012B, 0x34}, // EXCLK_FREQ[7:0] = 4916 MHz + +// {0x012A, 0x09}, // EXCLK_FREQ[15:8] +// {0x012B, 0x9A}, // EXCLK_FREQ[7:0] = 2458 MHz + +// {0x012A, 0x26}, // * EXCLK_FREQ[15:8] +// {0x012B, 0x68}, // * EXCLK_FREQ[7:0] = 4916 MHz +// {0x012A, 0x18}, // * EXCLK_FREQ[15:8] +// {0x012B, 0x00}, // * EXCLK_FREQ[7:0] = 4916 MHz + + {0x0160, 0x04}, + {0x0161, 0x60}, + {0x0162, 0x0D}, + {0x0163, 0x78}, + {0x0164, 0x01}, + {0x0165, 0x58}, + {0x0166, 0x0B}, + {0x0167, 0x77}, + {0x0168, 0x01}, + {0x0169, 0xF0}, + {0x016A, 0x07}, + {0x016B, 0xAF}, + {0x016C, 0x05}, + {0x016D, 0x10}, + {0x016E, 0x02}, + {0x016F, 0xE0}, + {0x0170, 0x01}, + {0x0171, 0x01}, + {0x0174, 0x01}, + {0x0175, 0x01}, + {0x0176, 0x01}, + {0x0177, 0x01}, + {0x018C, 0x0A}, + {0x018D, 0x0A}, + {0x0301, 0x05}, + {0x0303, 0x01}, + {0x0304, 0x02}, + {0x0305, 0x02}, + {0x0306, 0x00}, + {0x0307, 0x2E}, + {0x0309, 0x0A}, + {0x030B, 0x01}, + + //{0x030C, 0x00}, // PLL_OP_MPY[10:8] + //{0x030D, 0x5C}, // PLL_OP_MPY[7:0] = 92 + + {0x030C, 0x00}, // PLL_OP_MPY[10:8] + {0x030D, 0xB8}, // PLL_OP_MPY[7:0] = 184 + + {0x455E, 0x00}, + {0x471E, 0x4B}, + {0x4767, 0x0F}, + {0x4750, 0x14}, + {0x4540, 0x00}, + {0x47B4, 0x14}, + {0x4713, 0x30}, + {0x478B, 0x10}, + {0x478F, 0x10}, + {0x4793, 0x10}, + {0x4797, 0x0E}, + {0x479B, 0x0E}, + {0x0100, 0x01}, /* mode select streaming on */ + {TABLE_END, 0x00} +}; + + + +static const struct sensor_cmd imx219_start[] = { + {0x0100, 0x01}, /* mode select streaming on */ + {TABLE_END, 0x00} +}; +static const struct sensor_cmd imx219_stop[] = { + {0x0100, 0x00}, /* mode select streaming off */ + {TABLE_END, 0x00} +}; +static const struct sensor_cmd imx219_test_color_bar[] = { + {0x0600, 0x00}, + {0x0601, 0x02}, + {TABLE_END, 0x00} +}; + +struct sensor_rect { + unsigned short left; + unsigned short top; + unsigned short width; + unsigned short height; +}; + +static const struct sensor_rect imx219_center_1280x720_rect = { + 1000, 872, 1280, 720 +}; + + +#endif diff --git a/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/startup/files/startup.c b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/startup/files/startup.c new file mode 100644 index 0000000..62523b0 --- /dev/null +++ b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-apps/startup/files/startup.c @@ -0,0 +1,39 @@ +/* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or (b) that interact +* with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include + +int main(int argc, char **argv) +{ + printf("Hello World!\n"); + + return 0; +} diff --git a/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h new file mode 100644 index 0000000..918e64b --- /dev/null +++ b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h @@ -0,0 +1,5 @@ + +#include + +#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; fatload mmc 0 0x1FC00000 u-boot.rgba" + diff --git a/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-modules/te-audio-codec/files/te-audio-codec.c b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-modules/te-audio-codec/files/te-audio-codec.c new file mode 100644 index 0000000..5b9575d --- /dev/null +++ b/zynqberrydemo1/os/petalinux/project-spec/meta-user/recipes-modules/te-audio-codec/files/te-audio-codec.c @@ -0,0 +1,99 @@ +/* + * ALSA SoC SPDIF DIT driver + * + * This driver is used by controllers which can operate in DIT (SPDI/F) where + * no codec is needed. This file provides stub codec that can be used + * in these configurations. TI DaVinci Audio controller uses this driver. + * + * Author: Steve Chen, + * Copyright: (C) 2009 MontaVista Software, Inc., + * Copyright: (C) 2009 Texas Instruments, India + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "te-audio-codec" + +#define STUB_RATES (SNDRV_PCM_RATE_8000_192000 | \ + SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \ + SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000) +#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dapm_widget dit_widgets[] = { + SND_SOC_DAPM_OUTPUT("te-out"), +}; + +static const struct snd_soc_dapm_route dit_routes[] = { + { "te-out", NULL, "Playback" }, +}; + +static struct snd_soc_codec_driver soc_codec_spdif_dit = { + .component_driver = { + .dapm_widgets = dit_widgets, + .num_dapm_widgets = ARRAY_SIZE(dit_widgets), + .dapm_routes = dit_routes, + .num_dapm_routes = ARRAY_SIZE(dit_routes), + }, +}; + +static struct snd_soc_dai_driver dit_stub_dai = { + .name = "dit-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 384, + .rates = STUB_RATES, + .formats = STUB_FORMATS, + }, +}; + +static int spdif_dit_probe(struct platform_device *pdev) +{ + return snd_soc_register_codec(&pdev->dev, &soc_codec_spdif_dit, + &dit_stub_dai, 1); +} + +static int spdif_dit_remove(struct platform_device *pdev) +{ + snd_soc_unregister_codec(&pdev->dev); + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id spdif_dit_dt_ids[] = { + { .compatible = "te,te-audio", }, + { } +}; +MODULE_DEVICE_TABLE(of, spdif_dit_dt_ids); +#endif + +static struct platform_driver spdif_dit_driver = { + .probe = spdif_dit_probe, + .remove = spdif_dit_remove, + .driver = { + .name = DRV_NAME, + .of_match_table = of_match_ptr(spdif_dit_dt_ids), + }, +}; + +module_platform_driver(spdif_dit_driver); + +MODULE_AUTHOR("Steve Chen "); +MODULE_DESCRIPTION("SPDIF dummy codec driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRV_NAME); + diff --git a/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_io_report.txt b/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_io_report.txt new file mode 100644 index 0000000..12a90a6 --- /dev/null +++ b/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_io_report.txt @@ -0,0 +1,267 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Mon Jun 12 14:19:13 2017 +| Host : W8-64-02 running 64-bit major release (build 9200) +| Command : report_io -force -file B:/Design/cores/2017.1/design/TE0726/zynqberrydemo1/vivado/zynqberrydemo1.runs/impl_1/zynqberrydemo1_io_report.txt -format text +| Design : zsys_wrapper +| Device : xc7z007s +| Speed File : -1 +| Package : clg225 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 130 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | ++------------+-------------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A2 | DDR_dq[1] | | PS_DDR_DQ1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A3 | DDR_dq[7] | | PS_DDR_DQ7_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A4 | DDR_dq[5] | | PS_DDR_DQ5_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A5 | FIXED_IO_mio[1] | | PS_MIO1_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| A7 | FIXED_IO_mio[3] | | PS_MIO3_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A8 | FIXED_IO_mio[2] | | PS_MIO2_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A9 | FIXED_IO_mio[5] | | PS_MIO5_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A10 | FIXED_IO_mio[6] | | PS_MIO6_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A12 | FIXED_IO_mio[30] | | PS_MIO52_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A13 | FIXED_IO_mio[26] | | PS_MIO38_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A14 | FIXED_IO_mio[23] | | PS_MIO35_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A15 | FIXED_IO_mio[16] | | PS_MIO28_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B1 | DDR_dm[0] | | PS_DDR_DM0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| B4 | DDR_dq[4] | | PS_DDR_DQ4_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B6 | FIXED_IO_mio[8] | | PS_MIO8_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B7 | FIXED_IO_mio[12] | | PS_MIO12_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B9 | FIXED_IO_mio[14] | | PS_MIO14_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B10 | FIXED_IO_mio[11] | | PS_MIO11_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B11 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B12 | FIXED_IO_mio[28] | | PS_MIO48_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| B14 | FIXED_IO_mio[24] | | PS_MIO36_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B15 | FIXED_IO_mio[18] | | PS_MIO30_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C1 | DDR_dq[3] | | PS_DDR_DQ3_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C3 | DDR_dq[6] | | PS_DDR_DQ6_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C4 | DDR_dq[2] | | PS_DDR_DQ2_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C6 | FIXED_IO_mio[13] | | PS_MIO13_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C8 | FIXED_IO_mio[4] | | PS_MIO4_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C9 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C10 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| C11 | FIXED_IO_mio[21] | | PS_MIO33_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C12 | FIXED_IO_mio[19] | | PS_MIO31_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C13 | FIXED_IO_mio[31] | | PS_MIO53_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C14 | FIXED_IO_mio[25] | | PS_MIO37_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D1 | DDR_dq[9] | | PS_DDR_DQ9_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D3 | DDR_dm[1] | | PS_DDR_DM1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D4 | DDR_dq[0] | | PS_DDR_DQ0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D5 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | +| D6 | FIXED_IO_mio[10] | | PS_MIO10_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| D8 | FIXED_IO_mio[0] | | PS_MIO0_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D9 | FIXED_IO_mio[7] | | PS_MIO7_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D10 | FIXED_IO_mio[15] | | PS_MIO15_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D11 | FIXED_IO_mio[17] | | PS_MIO29_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D13 | FIXED_IO_mio[29] | | PS_MIO49_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D14 | FIXED_IO_mio[27] | | PS_MIO39_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D15 | FIXED_IO_mio[22] | | PS_MIO34_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| E1 | DDR_dq[8] | | PS_DDR_DQ8_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| E2 | DDR_dq[10] | | PS_DDR_DQ10_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| E3 | DDR_dq[11] | | PS_DDR_DQ11_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| E4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E6 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E8 | | | RSVDGND | GND | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| E11 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | +| E12 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | +| E13 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | +| E14 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| E15 | FIXED_IO_mio[20] | | PS_MIO32_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| F1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| F2 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| F3 | DDR_dq[12] | | PS_DDR_DQ12_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| F4 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | +| F5 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | +| F6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | +| F7 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | +| F8 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | +| F9 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| F10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F11 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | +| F12 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | +| F13 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | +| F14 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | +| F15 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | +| G1 | DDR_dq[13] | | PS_DDR_DQ13_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| G2 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| G3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G4 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G6 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| G7 | Vp_Vn_v_p | Dedicated | VP_0 | INPUT | LVCMOS18* | 0 | | | | NONE | | UNFIXED | | | | NONE | +| G8 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | +| G9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| G11 | gpio_1_tri_io[13] | High Range | IO_L1P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G12 | gpio_1_tri_io[23] | High Range | IO_L2P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G14 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | +| G15 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | +| H1 | DDR_dq[14] | | PS_DDR_DQ14_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| H2 | DDR_dq[15] | | PS_DDR_DQ15_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| H3 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| H4 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | +| H5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| H6 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H7 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | +| H8 | Vp_Vn_v_n | Dedicated | VN_0 | INPUT | LVCMOS18* | 0 | | | | NONE | | UNFIXED | | | | NONE | +| H9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| H10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H11 | gpio_1_tri_io[14] | High Range | IO_L6P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H12 | gpio_1_tri_io[2] | High Range | IO_L1N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H13 | gpio_1_tri_io[18] | High Range | IO_L2N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H14 | gpio_1_tri_io[8] | High Range | IO_L3N_T0_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H15 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | +| J1 | DDR_addr[10] | | PS_DDR_A10_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| J2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| J3 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| J4 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | +| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| J7 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | +| J8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| J11 | gpio_1_tri_io[19] | High Range | IO_L6N_T0_VREF_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J12 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| J13 | gpio_1_tri_io[7] | High Range | IO_L5P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J14 | gpio_1_tri_io[1] | High Range | IO_L5N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J15 | gpio_1_tri_io[9] | High Range | IO_L4P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K1 | DDR_addr[14] | | PS_DDR_A14_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| K2 | DDR_addr[13] | | PS_DDR_A13_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| K3 | DDR_odt | | PS_DDR_ODT_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| K6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K8 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | +| K9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| K10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K11 | gpio_1_tri_io[20] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K12 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| K13 | gpio_1_tri_io[21] | High Range | IO_L10P_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K15 | gpio_1_tri_io[0] | High Range | IO_L4N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L2 | DDR_addr[11] | | PS_DDR_A11_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| L3 | DDR_cke | | PS_DDR_CKE_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| L4 | DDR_reset_n | | PS_DDR_DRST_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| L7 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | +| L8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | +| L9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L12 | gpio_1_tri_io[22] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L13 | gpio_1_tri_io[12] | High Range | IO_L10N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L14 | gpio_1_tri_io[5] | High Range | IO_L9P_T1_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L15 | gpio_1_tri_io[6] | High Range | IO_L8P_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M1 | DDR_addr[2] | | PS_DDR_A2_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M2 | DDR_addr[12] | | PS_DDR_A12_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| M4 | DDR_addr[3] | | PS_DDR_A3_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M5 | DDR_addr[7] | | PS_DDR_A7_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M6 | DDR_ba[0] | | PS_DDR_BA0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | +| M8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M9 | csi_d_lp_n[0] | High Range | IO_L19P_T3_34 | INPUT | HSUL_12 | 34 | | | | NONE | | FIXED | PULLDOWN | | Internal | NONE | +| M10 | csi_d_p[0] | High Range | IO_L21P_T3_DQS_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| M11 | csi_d_n[0] | High Range | IO_L21N_T3_DQS_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| M12 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| M13 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| M14 | gpio_1_tri_io[16] | High Range | IO_L9N_T1_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M15 | gpio_1_tri_io[10] | High Range | IO_L8N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N1 | DDR_addr[1] | | PS_DDR_A1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N2 | DDR_ck_n | | PS_DDR_CKN_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N3 | DDR_ck_p | | PS_DDR_CKP_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N4 | DDR_addr[9] | | PS_DDR_A9_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N6 | DDR_ba[2] | | PS_DDR_BA2_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N7 | PWM_L | High Range | IO_L22P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N8 | PWM_R | High Range | IO_L22N_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N9 | csi_d_lp_p[0] | High Range | IO_L19N_T3_VREF_34 | INPUT | HSUL_12 | 34 | | | | NONE | | FIXED | PULLDOWN | | Internal | NONE | +| N10 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| N11 | csi_c_clk_p | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| N12 | csi_c_clk_n | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| N13 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | +| N14 | gpio_1_tri_io[3] | High Range | IO_L7N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P1 | DDR_addr[0] | | PS_DDR_A0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P3 | DDR_addr[4] | | PS_DDR_A4_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P4 | DDR_addr[5] | | PS_DDR_A5_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P5 | DDR_addr[6] | | PS_DDR_A6_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P6 | DDR_addr[8] | | PS_DDR_A8_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| P8 | hdmi_data_p[0] | High Range | IO_L23P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P9 | hdmi_data_n[0] | High Range | IO_L23N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P10 | hdmi_data_p[1] | High Range | IO_L24P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P11 | hdmi_data_p[2] | High Range | IO_L16P_T2_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P13 | csi_d_p[1] | High Range | IO_L18P_T2_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| P14 | csi_d_n[1] | High Range | IO_L18N_T2_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| P15 | gpio_1_tri_io[17] | High Range | IO_L15P_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R1 | DDR_ba[1] | | PS_DDR_BA1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R2 | DDR_cs_n | | PS_DDR_CS_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R3 | DDR_we_n | | PS_DDR_WE_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| R5 | DDR_cas_n | | PS_DDR_CAS_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R6 | DDR_ras_n | | PS_DDR_RAS_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R7 | hdmi_clk_p | High Range | IO_L20P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R8 | hdmi_clk_n | High Range | IO_L20N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R10 | hdmi_data_n[1] | High Range | IO_L24N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R11 | hdmi_data_n[2] | High Range | IO_L16N_T2_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R12 | gpio_1_tri_io[15] | High Range | IO_L17P_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R13 | gpio_1_tri_io[11] | High Range | IO_L17N_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| R15 | gpio_1_tri_io[4] | High Range | IO_L15N_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | ++------------+-------------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_io_report.xdc b/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_io_report.xdc new file mode 100644 index 0000000..1bc805c --- /dev/null +++ b/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_io_report.xdc @@ -0,0 +1,535 @@ +set_property DIRECTION IN [get_ports {csi_d_lp_p[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}] +set_property DIRECTION IN [get_ports {csi_d_n[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_n[1]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_n[1]}] +set_property DIRECTION IN [get_ports {csi_d_n[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_n[0]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_n[0]}] +set_property DIRECTION IN [get_ports {csi_d_p[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_p[1]}] +set_property DIRECTION IN [get_ports {csi_d_p[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_p[0]}] +set_property DIRECTION IN [get_ports {csi_d_lp_n[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[2]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[1]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[0]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[2]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[1]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[0]}] +set_property DIRECTION OUT [get_ports hdmi_clk_p] +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p] +set_property DIRECTION OUT [get_ports hdmi_clk_n] +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_n] +set_property DIRECTION IN [get_ports csi_c_clk_p] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p] +set_property DIFF_TERM FALSE [get_ports csi_c_clk_p] +set_property DIRECTION IN [get_ports csi_c_clk_n] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_n] +set_property DIFF_TERM FALSE [get_ports csi_c_clk_n] +set_property DIRECTION IN [get_ports Vp_Vn_v_p] +set_property DIRECTION IN [get_ports Vp_Vn_v_n] +set_property DIRECTION OUT [get_ports PWM_R] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_R] +set_property DRIVE 12 [get_ports PWM_R] +set_property SLEW SLOW [get_ports PWM_R] +set_property DIRECTION OUT [get_ports PWM_L] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_L] +set_property DRIVE 12 [get_ports PWM_L] +set_property SLEW SLOW [get_ports PWM_L] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[23]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[23]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[23]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[23]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[22]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[22]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[22]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[21]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[21]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[21]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[21]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[20]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[20]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[20]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[19]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[19]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[19]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[19]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[18]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[18]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[18]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[17]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[17]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[17]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[17]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[16]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[16]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[16]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[15]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[15]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[15]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[14]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[14]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[14]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[13]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[13]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[13]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[12]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[12]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[12]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[11]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[11]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[11]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[10]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[10]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[10]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[9]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[9]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[9]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[8]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[8]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[8]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[7]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[7]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[7]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[6]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[6]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[6]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[5]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[5]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[5]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[4]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[4]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[4]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[3]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[3]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[3]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[2]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[2]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[2]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[1]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[1]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[1]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[0]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[0]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[0]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[31]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[31]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[31]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[31]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[30]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[30]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[30]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[30]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[29]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[29]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[29]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[29]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[28]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[28]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[28]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[28]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[27]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[27]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[27]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[27]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[26]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[26]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[26]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[26]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[25]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[25]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[25]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[25]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[24]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[24]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[24]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[24]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[23]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[23]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[23]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[23]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[22]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[22]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[22]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[22]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[21]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[21]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[21]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[21]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[20]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[20]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[20]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[20]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[19]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[19]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[19]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[19]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[18]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[18]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[18]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[18]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[17]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[17]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[17]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[17]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[16]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[16]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[16]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[16]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[15]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[15]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[15]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[15]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[14]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[14]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[14]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[13]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[13]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[13]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[12]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[12]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[12]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[11]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[11]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[11]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[10]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[10]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[10]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[9]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[9]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[9]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[8]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[8]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[8]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[7]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[7]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[7]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[6]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[6]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[6]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[5]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[5]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[5]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[4]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[4]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[4]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[3]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[3]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[3]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[2]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[2]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[2]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[1]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[1]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[1]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[0]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[0]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[0]}] +set_property DIRECTION INOUT [get_ports FIXED_IO_ddr_vrn] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ddr_vrn] +set_property DRIVE 12 [get_ports FIXED_IO_ddr_vrn] +set_property SLEW SLOW [get_ports FIXED_IO_ddr_vrn] +set_property DIRECTION INOUT [get_ports FIXED_IO_ddr_vrp] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ddr_vrp] +set_property DRIVE 12 [get_ports FIXED_IO_ddr_vrp] +set_property SLEW SLOW [get_ports FIXED_IO_ddr_vrp] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_clk] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ps_clk] +set_property DRIVE 12 [get_ports FIXED_IO_ps_clk] +set_property SLEW SLOW [get_ports FIXED_IO_ps_clk] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_porb] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ps_porb] +set_property DRIVE 12 [get_ports FIXED_IO_ps_porb] +set_property SLEW SLOW [get_ports FIXED_IO_ps_porb] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_srstb] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ps_srstb] +set_property DRIVE 12 [get_ports FIXED_IO_ps_srstb] +set_property SLEW SLOW [get_ports FIXED_IO_ps_srstb] +set_property DIRECTION INOUT [get_ports {DDR_dqs_p[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dqs_p[1]}] +set_property DRIVE 12 [get_ports {DDR_dqs_p[1]}] +set_property SLEW SLOW [get_ports {DDR_dqs_p[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_p[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dqs_p[0]}] +set_property DRIVE 12 [get_ports {DDR_dqs_p[0]}] +set_property SLEW SLOW [get_ports {DDR_dqs_p[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_n[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dqs_n[1]}] +set_property DRIVE 12 [get_ports {DDR_dqs_n[1]}] +set_property SLEW SLOW [get_ports {DDR_dqs_n[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_n[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dqs_n[0]}] +set_property DRIVE 12 [get_ports {DDR_dqs_n[0]}] +set_property SLEW SLOW [get_ports {DDR_dqs_n[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[15]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[15]}] +set_property DRIVE 12 [get_ports {DDR_dq[15]}] +set_property SLEW SLOW [get_ports {DDR_dq[15]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[14]}] +set_property DRIVE 12 [get_ports {DDR_dq[14]}] +set_property SLEW SLOW [get_ports {DDR_dq[14]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[13]}] +set_property DRIVE 12 [get_ports {DDR_dq[13]}] +set_property SLEW SLOW [get_ports {DDR_dq[13]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[12]}] +set_property DRIVE 12 [get_ports {DDR_dq[12]}] +set_property SLEW SLOW [get_ports {DDR_dq[12]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[11]}] +set_property DRIVE 12 [get_ports {DDR_dq[11]}] +set_property SLEW SLOW [get_ports {DDR_dq[11]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[10]}] +set_property DRIVE 12 [get_ports {DDR_dq[10]}] +set_property SLEW SLOW [get_ports {DDR_dq[10]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[9]}] +set_property DRIVE 12 [get_ports {DDR_dq[9]}] +set_property SLEW SLOW [get_ports {DDR_dq[9]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[8]}] +set_property DRIVE 12 [get_ports {DDR_dq[8]}] +set_property SLEW SLOW [get_ports {DDR_dq[8]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[7]}] +set_property DRIVE 12 [get_ports {DDR_dq[7]}] +set_property SLEW SLOW [get_ports {DDR_dq[7]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[6]}] +set_property DRIVE 12 [get_ports {DDR_dq[6]}] +set_property SLEW SLOW [get_ports {DDR_dq[6]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[5]}] +set_property DRIVE 12 [get_ports {DDR_dq[5]}] +set_property SLEW SLOW [get_ports {DDR_dq[5]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[4]}] +set_property DRIVE 12 [get_ports {DDR_dq[4]}] +set_property SLEW SLOW [get_ports {DDR_dq[4]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[3]}] +set_property DRIVE 12 [get_ports {DDR_dq[3]}] +set_property SLEW SLOW [get_ports {DDR_dq[3]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[2]}] +set_property DRIVE 12 [get_ports {DDR_dq[2]}] +set_property SLEW SLOW [get_ports {DDR_dq[2]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[1]}] +set_property DRIVE 12 [get_ports {DDR_dq[1]}] +set_property SLEW SLOW [get_ports {DDR_dq[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[0]}] +set_property DRIVE 12 [get_ports {DDR_dq[0]}] +set_property SLEW SLOW [get_ports {DDR_dq[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dm[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dm[1]}] +set_property DRIVE 12 [get_ports {DDR_dm[1]}] +set_property SLEW SLOW [get_ports {DDR_dm[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dm[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dm[0]}] +set_property DRIVE 12 [get_ports {DDR_dm[0]}] +set_property SLEW SLOW [get_ports {DDR_dm[0]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_ba[2]}] +set_property DRIVE 12 [get_ports {DDR_ba[2]}] +set_property SLEW SLOW [get_ports {DDR_ba[2]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_ba[1]}] +set_property DRIVE 12 [get_ports {DDR_ba[1]}] +set_property SLEW SLOW [get_ports {DDR_ba[1]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_ba[0]}] +set_property DRIVE 12 [get_ports {DDR_ba[0]}] +set_property SLEW SLOW [get_ports {DDR_ba[0]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[14]}] +set_property DRIVE 12 [get_ports {DDR_addr[14]}] +set_property SLEW SLOW [get_ports {DDR_addr[14]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[13]}] +set_property DRIVE 12 [get_ports {DDR_addr[13]}] +set_property SLEW SLOW [get_ports {DDR_addr[13]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[12]}] +set_property DRIVE 12 [get_ports {DDR_addr[12]}] +set_property SLEW SLOW [get_ports {DDR_addr[12]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[11]}] +set_property DRIVE 12 [get_ports {DDR_addr[11]}] +set_property SLEW SLOW [get_ports {DDR_addr[11]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[10]}] +set_property DRIVE 12 [get_ports {DDR_addr[10]}] +set_property SLEW SLOW [get_ports {DDR_addr[10]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[9]}] +set_property DRIVE 12 [get_ports {DDR_addr[9]}] +set_property SLEW SLOW [get_ports {DDR_addr[9]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[8]}] +set_property DRIVE 12 [get_ports {DDR_addr[8]}] +set_property SLEW SLOW [get_ports {DDR_addr[8]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[7]}] +set_property DRIVE 12 [get_ports {DDR_addr[7]}] +set_property SLEW SLOW [get_ports {DDR_addr[7]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[6]}] +set_property DRIVE 12 [get_ports {DDR_addr[6]}] +set_property SLEW SLOW [get_ports {DDR_addr[6]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[5]}] +set_property DRIVE 12 [get_ports {DDR_addr[5]}] +set_property SLEW SLOW [get_ports {DDR_addr[5]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[4]}] +set_property DRIVE 12 [get_ports {DDR_addr[4]}] +set_property SLEW SLOW [get_ports {DDR_addr[4]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[3]}] +set_property DRIVE 12 [get_ports {DDR_addr[3]}] +set_property SLEW SLOW [get_ports {DDR_addr[3]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[2]}] +set_property DRIVE 12 [get_ports {DDR_addr[2]}] +set_property SLEW SLOW [get_ports {DDR_addr[2]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[1]}] +set_property DRIVE 12 [get_ports {DDR_addr[1]}] +set_property SLEW SLOW [get_ports {DDR_addr[1]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[0]}] +set_property DRIVE 12 [get_ports {DDR_addr[0]}] +set_property SLEW SLOW [get_ports {DDR_addr[0]}] +set_property DIRECTION INOUT [get_ports DDR_cas_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_cas_n] +set_property DRIVE 12 [get_ports DDR_cas_n] +set_property SLEW SLOW [get_ports DDR_cas_n] +set_property DIRECTION INOUT [get_ports DDR_ck_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_ck_n] +set_property DRIVE 12 [get_ports DDR_ck_n] +set_property SLEW SLOW [get_ports DDR_ck_n] +set_property DIRECTION INOUT [get_ports DDR_ck_p] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_ck_p] +set_property DRIVE 12 [get_ports DDR_ck_p] +set_property SLEW SLOW [get_ports DDR_ck_p] +set_property DIRECTION INOUT [get_ports DDR_cke] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_cke] +set_property DRIVE 12 [get_ports DDR_cke] +set_property SLEW SLOW [get_ports DDR_cke] +set_property DIRECTION INOUT [get_ports DDR_cs_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_cs_n] +set_property DRIVE 12 [get_ports DDR_cs_n] +set_property SLEW SLOW [get_ports DDR_cs_n] +set_property DIRECTION INOUT [get_ports DDR_odt] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_odt] +set_property DRIVE 12 [get_ports DDR_odt] +set_property SLEW SLOW [get_ports DDR_odt] +set_property DIRECTION INOUT [get_ports DDR_ras_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_ras_n] +set_property DRIVE 12 [get_ports DDR_ras_n] +set_property SLEW SLOW [get_ports DDR_ras_n] +set_property DIRECTION INOUT [get_ports DDR_reset_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_reset_n] +set_property DRIVE 12 [get_ports DDR_reset_n] +set_property SLEW SLOW [get_ports DDR_reset_n] +set_property DIRECTION INOUT [get_ports DDR_we_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_we_n] +set_property DRIVE 12 [get_ports DDR_we_n] +set_property SLEW SLOW [get_ports DDR_we_n] +set_property PACKAGE_PIN N12 [get_ports csi_c_clk_n] +set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p] +set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}] +set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}] +set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}] +set_property PACKAGE_PIN M11 [get_ports {csi_d_n[0]}] +set_property PACKAGE_PIN P14 [get_ports {csi_d_n[1]}] +set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}] +set_property INTERNAL_VREF 0.6 [get_iobanks 34] +set_property PACKAGE_PIN R8 [get_ports hdmi_clk_n] +set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p] +set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}] +set_property PACKAGE_PIN P9 [get_ports {hdmi_data_n[0]}] +set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}] +set_property PACKAGE_PIN R10 [get_ports {hdmi_data_n[1]}] +set_property PACKAGE_PIN R11 [get_ports {hdmi_data_n[2]}] +set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}] +set_property PACKAGE_PIN K15 [get_ports {gpio_1_tri_io[0]}] +set_property PACKAGE_PIN J14 [get_ports {gpio_1_tri_io[1]}] +set_property PACKAGE_PIN H12 [get_ports {gpio_1_tri_io[2]}] +set_property PACKAGE_PIN N14 [get_ports {gpio_1_tri_io[3]}] +set_property PACKAGE_PIN R15 [get_ports {gpio_1_tri_io[4]}] +set_property PACKAGE_PIN L14 [get_ports {gpio_1_tri_io[5]}] +set_property PACKAGE_PIN L15 [get_ports {gpio_1_tri_io[6]}] +set_property PACKAGE_PIN J13 [get_ports {gpio_1_tri_io[7]}] +set_property PACKAGE_PIN H14 [get_ports {gpio_1_tri_io[8]}] +set_property PACKAGE_PIN J15 [get_ports {gpio_1_tri_io[9]}] +set_property PACKAGE_PIN M15 [get_ports {gpio_1_tri_io[10]}] +set_property PACKAGE_PIN R13 [get_ports {gpio_1_tri_io[11]}] +set_property PACKAGE_PIN L13 [get_ports {gpio_1_tri_io[12]}] +set_property PACKAGE_PIN G11 [get_ports {gpio_1_tri_io[13]}] +set_property PACKAGE_PIN H11 [get_ports {gpio_1_tri_io[14]}] +set_property PACKAGE_PIN R12 [get_ports {gpio_1_tri_io[15]}] +set_property PACKAGE_PIN M14 [get_ports {gpio_1_tri_io[16]}] +set_property PACKAGE_PIN P15 [get_ports {gpio_1_tri_io[17]}] +set_property PACKAGE_PIN H13 [get_ports {gpio_1_tri_io[18]}] +set_property PACKAGE_PIN J11 [get_ports {gpio_1_tri_io[19]}] +set_property PACKAGE_PIN K11 [get_ports {gpio_1_tri_io[20]}] +set_property PACKAGE_PIN K13 [get_ports {gpio_1_tri_io[21]}] +set_property PACKAGE_PIN L12 [get_ports {gpio_1_tri_io[22]}] +set_property PACKAGE_PIN G12 [get_ports {gpio_1_tri_io[23]}] +set_property PACKAGE_PIN N8 [get_ports PWM_R] +set_property PACKAGE_PIN N7 [get_ports PWM_L] +#revert back to original instance +current_instance -quiet diff --git a/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_ip_status_report.txt b/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_ip_status_report.txt new file mode 100644 index 0000000..8278b7d --- /dev/null +++ b/zynqberrydemo1/prebuilt/hardware/te0726_7s/reports/zynqberrydemo1_ip_status_report.txt @@ -0,0 +1,152 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Mon Jun 12 14:19:13 2017 +| Host : W8-64-02 running 64-bit major release (build 9200) +| Command : report_ip_status +------------------------------------------------------------------------------------ + +IP Status Summary + +1. Project IP Status +-------------------- +Your project uses 29 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. + +More information on the Xilinx versioning policy is available at www.xilinx.com. + +Project IP Instances ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | +| | | | Log | | Version | | License | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_Video_IO_2_HDMI_TMDS_0_0 | Up-to-date | No changes required | Change | Video IO to HDMI | 1.0 | 1.0 (Rev. 26) | Included | xc7z007sclg225-1 | +| | | | Log not | TMDS Interface | (Rev. | | | | +| | | | available | v1.0 | 26) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_i2s_adi_0_0 | Up-to-date | No changes required | Change | AXI I2S Audio | 1.2 | 1.2 (Rev. 1) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_interconnect_0_0 | Up-to-date | No changes required | *(1) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_mem_intercon_0 | Up-to-date | No changes required | *(2) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_reg32_0_0 | Up-to-date | No changes required | Change | AXI Register Bank | 1.0 | 1.0 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | Log not | 16/16 v1.0 | (Rev. | | | | +| | | | available | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_vdma_0_0 | Up-to-date | No changes required | *(3) | AXI Video Direct | 6.3 | 6.3 | Included | xc7z007sclg225-1 | +| | | | | Memory Access | | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_vdma_0_1 | Up-to-date | No changes required | *(4) | AXI Video Direct | 6.3 | 6.3 | Included | xc7z007sclg225-1 | +| | | | | Memory Access | | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_0_0 | Up-to-date | No changes required | *(5) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_3_0 | Up-to-date | No changes required | *(6) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_4_0 | Up-to-date | No changes required | *(7) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_fb_conv_0_0 | Up-to-date | No changes required | Change | axis_fb_conv_v1.0 | 1.0 | 1.0 (Rev. 5) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 5) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_raw_demosaic_0_0 | Up-to-date | No changes required | Change | RAW Demosaic v1.0 | 1.0 | 1.0 (Rev. 20) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 20) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_raw_unpack_0_0 | Up-to-date | No changes required | Change | RAW10 Unpack v1.0 | 1.0 | 1.0 (Rev. 17) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 17) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_to_i2s_0_0 | Up-to-date | No changes required | Change | AXI4-Stream to I2S | 1.0 | 1.0 (Rev. 4) | Included | xc7z007sclg225-1 | +| | | | Log not | v1.0 | (Rev. | | | | +| | | | available | | 4) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_clk_wiz_1_0 | Up-to-date | No changes required | *(8) | Clocking Wizard | 5.4 | 5.4 | Included | xc7z007sclg225-1 | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_csi2_d_phy_rx_0_0 | Up-to-date | No changes required | Change | CSI-2 D-PHY RX | 1.0 | 1.0 (Rev. 35) | Included | xc7z007sclg225-1 | +| | | | Log not | v1_0 | (Rev. | | | | +| | | | available | | 35) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_csi_to_axis_0_0 | Up-to-date | No changes required | Change | CSI-2 to | 1.0 | 1.0 (Rev. 46) | Included | xc7z007sclg225-1 | +| | | | Log not | AXI4-Stream v1.0 | (Rev. | | | | +| | | | available | | 46) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_i2s_to_pwm_0_0 | Up-to-date | No changes required | Change | I2S to PWM v1.0 | 1.0 | 1.0 (Rev. 7) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 7) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_proc_sys_reset_0_0 | Up-to-date | No changes required | *(9) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z007sclg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_proc_sys_reset_1_0 | Up-to-date | No changes required | *(10) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z007sclg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_processing_system7_0_0 | Up-to-date | No changes required | *(11) | ZYNQ7 Processing | 5.5 | 5.5 (Rev. 5) | Included | xc7z007sclg225-1 | +| | | | | System | (Rev. | | | | +| | | | | | 5) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_processing_system7_0_axi_periph_0 | Up-to-date | No changes required | *(12) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_rst_processing_system7_0_50M_0 | Up-to-date | No changes required | *(13) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z007sclg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_v_axi4s_vid_out_0_0 | Up-to-date | No changes required | *(14) | AXI4-Stream to | 4.0 | 4.0 (Rev. 6) | Included | xc7z007sclg225-1 | +| | | | | Video Out | (Rev. | | | | +| | | | | | 6) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_v_tc_0_0 | Up-to-date | No changes required | *(15) | Video Timing | 6.1 | 6.1 (Rev. 10) | Included | xc7z007sclg225-1 | +| | | | | Controller | (Rev. | | | | +| | | | | | 10) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xadc_wiz_0_0 | Up-to-date | No changes required | *(16) | XADC Wizard | 3.3 | 3.3 (Rev. 3) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 3) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlconcat_0_0 | Up-to-date | No changes required | *(17) | Concat | 2.1 | 2.1 (Rev. 1) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlslice_0_0 | Up-to-date | No changes required | Change | Slice | 1.0 | 1.0 (Rev. 1) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlslice_1_0 | Up-to-date | No changes required | Change | Slice | 1.0 | 1.0 (Rev. 1) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +*(1) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(2) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(3) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt +*(4) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt +*(5) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(6) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(7) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(8) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/clk_wiz_v5_4/doc/clk_wiz_v5_4_changelog.txt +*(9) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(10) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(11) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/processing_system7_v5_5/doc/processing_system7_v5_5_changelog.txt +*(12) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(13) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(14) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/v_axi4s_vid_out_v4_0/doc/v_axi4s_vid_out_v4_0_changelog.txt +*(15) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/v_tc_v6_1/doc/v_tc_v6_1_changelog.txt +*(16) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/xadc_wiz_v3_3/doc/xadc_wiz_v3_3_changelog.txt +*(17) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt + + diff --git a/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_io_report.txt b/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_io_report.txt new file mode 100644 index 0000000..40d7498 --- /dev/null +++ b/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_io_report.txt @@ -0,0 +1,267 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Mon Jun 12 13:57:38 2017 +| Host : W8-64-02 running 64-bit major release (build 9200) +| Command : report_io -force -file B:/Design/cores/2017.1/design/TE0726/zynqberrydemo1/vivado/zynqberrydemo1.runs/impl_1/zynqberrydemo1_io_report.txt -format text +| Design : zsys_wrapper +| Device : xc7z010 +| Speed File : -1 +| Package : clg225 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 130 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A2 | DDR_dq[1] | | PS_DDR_DQ1_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A3 | DDR_dq[7] | | PS_DDR_DQ7_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A4 | DDR_dq[5] | | PS_DDR_DQ5_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A5 | FIXED_IO_mio[1] | | PS_MIO1_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| A7 | FIXED_IO_mio[3] | | PS_MIO3_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A8 | FIXED_IO_mio[2] | | PS_MIO2_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A9 | FIXED_IO_mio[5] | | PS_MIO5_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A10 | FIXED_IO_mio[6] | | PS_MIO6_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A12 | FIXED_IO_mio[30] | | PS_MIO52_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A13 | FIXED_IO_mio[26] | | PS_MIO38_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A14 | FIXED_IO_mio[23] | | PS_MIO35_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A15 | FIXED_IO_mio[16] | | PS_MIO28_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B1 | DDR_dm[0] | | PS_DDR_DM0_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | BIDIR | DIFF_SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| B3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| B4 | DDR_dq[4] | | PS_DDR_DQ4_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B6 | FIXED_IO_mio[8] | | PS_MIO8_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B7 | FIXED_IO_mio[12] | | PS_MIO12_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B9 | FIXED_IO_mio[14] | | PS_MIO14_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B10 | FIXED_IO_mio[11] | | PS_MIO11_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B11 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| B12 | FIXED_IO_mio[28] | | PS_MIO48_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| B14 | FIXED_IO_mio[24] | | PS_MIO36_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B15 | FIXED_IO_mio[18] | | PS_MIO30_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C1 | DDR_dq[3] | | PS_DDR_DQ3_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | BIDIR | DIFF_SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C3 | DDR_dq[6] | | PS_DDR_DQ6_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C4 | DDR_dq[2] | | PS_DDR_DQ2_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C6 | FIXED_IO_mio[13] | | PS_MIO13_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| C7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| C8 | FIXED_IO_mio[4] | | PS_MIO4_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| C9 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| C10 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| C11 | FIXED_IO_mio[21] | | PS_MIO33_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C12 | FIXED_IO_mio[19] | | PS_MIO31_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C13 | FIXED_IO_mio[31] | | PS_MIO53_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C14 | FIXED_IO_mio[25] | | PS_MIO37_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D1 | DDR_dq[9] | | PS_DDR_DQ9_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| D2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D3 | DDR_dm[1] | | PS_DDR_DM1_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| D4 | DDR_dq[0] | | PS_DDR_DQ0_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| D5 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | +| D6 | FIXED_IO_mio[10] | | PS_MIO10_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| D8 | FIXED_IO_mio[0] | | PS_MIO0_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D9 | FIXED_IO_mio[7] | | PS_MIO7_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D10 | FIXED_IO_mio[15] | | PS_MIO15_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D11 | FIXED_IO_mio[17] | | PS_MIO29_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D13 | FIXED_IO_mio[29] | | PS_MIO49_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D14 | FIXED_IO_mio[27] | | PS_MIO39_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D15 | FIXED_IO_mio[22] | | PS_MIO34_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| E1 | DDR_dq[8] | | PS_DDR_DQ8_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E2 | DDR_dq[10] | | PS_DDR_DQ10_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E3 | DDR_dq[11] | | PS_DDR_DQ11_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E6 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E8 | | | RSVDGND | GND | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| E11 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | +| E12 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | +| E13 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | +| E14 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| E15 | FIXED_IO_mio[20] | | PS_MIO32_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| F1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| F2 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | BIDIR | DIFF_SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| F3 | DDR_dq[12] | | PS_DDR_DQ12_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| F4 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | +| F5 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | +| F6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | +| F7 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | +| F8 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | +| F9 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| F10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F11 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | +| F12 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | +| F13 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | +| F14 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | +| F15 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | +| G1 | DDR_dq[13] | | PS_DDR_DQ13_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| G2 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | BIDIR | DIFF_SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| G3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G4 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G6 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| G7 | Vp_Vn_v_p | Dedicated | VP_0 | INPUT | LVCMOS18* | 0 | | | | NONE | | UNFIXED | | | | NONE | +| G8 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | +| G9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| G11 | gpio_1_tri_io[13] | High Range | IO_L1P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G12 | gpio_1_tri_io[23] | High Range | IO_L2P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G14 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | +| G15 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | +| H1 | DDR_dq[14] | | PS_DDR_DQ14_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H2 | DDR_dq[15] | | PS_DDR_DQ15_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H3 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H4 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | +| H5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| H6 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H7 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | +| H8 | Vp_Vn_v_n | Dedicated | VN_0 | INPUT | LVCMOS18* | 0 | | | | NONE | | UNFIXED | | | | NONE | +| H9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| H10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H11 | gpio_1_tri_io[14] | High Range | IO_L6P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H12 | gpio_1_tri_io[2] | High Range | IO_L1N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H13 | gpio_1_tri_io[18] | High Range | IO_L2N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H14 | gpio_1_tri_io[8] | High Range | IO_L3N_T0_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H15 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | +| J1 | DDR_addr[10] | | PS_DDR_A10_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| J3 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| J4 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | +| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| J7 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | +| J8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| J11 | gpio_1_tri_io[19] | High Range | IO_L6N_T0_VREF_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J12 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| J13 | gpio_1_tri_io[7] | High Range | IO_L5P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J14 | gpio_1_tri_io[1] | High Range | IO_L5N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J15 | gpio_1_tri_io[9] | High Range | IO_L4P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K1 | DDR_addr[14] | | PS_DDR_A14_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K2 | DDR_addr[13] | | PS_DDR_A13_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K3 | DDR_odt | | PS_DDR_ODT_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| K6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K8 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | +| K9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| K10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K11 | gpio_1_tri_io[20] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K12 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| K13 | gpio_1_tri_io[21] | High Range | IO_L10P_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K15 | gpio_1_tri_io[0] | High Range | IO_L4N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L2 | DDR_addr[11] | | PS_DDR_A11_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L3 | DDR_cke | | PS_DDR_CKE_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L4 | DDR_reset_n | | PS_DDR_DRST_B_502 | BIDIR | SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| L7 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | +| L8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | +| L9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L12 | gpio_1_tri_io[22] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L13 | gpio_1_tri_io[12] | High Range | IO_L10N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L14 | gpio_1_tri_io[5] | High Range | IO_L9P_T1_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L15 | gpio_1_tri_io[6] | High Range | IO_L8P_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M1 | DDR_addr[2] | | PS_DDR_A2_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M2 | DDR_addr[12] | | PS_DDR_A12_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| M4 | DDR_addr[3] | | PS_DDR_A3_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M5 | DDR_addr[7] | | PS_DDR_A7_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M6 | DDR_ba[0] | | PS_DDR_BA0_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | +| M8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M9 | csi_d_lp_n[0] | High Range | IO_L19P_T3_34 | INPUT | HSUL_12 | 34 | | | | NONE | | FIXED | PULLDOWN | | Internal | NONE | +| M10 | csi_d_p[0] | High Range | IO_L21P_T3_DQS_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| M11 | csi_d_n[0] | High Range | IO_L21N_T3_DQS_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| M12 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| M13 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| M14 | gpio_1_tri_io[16] | High Range | IO_L9N_T1_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M15 | gpio_1_tri_io[10] | High Range | IO_L8N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N1 | DDR_addr[1] | | PS_DDR_A1_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N2 | DDR_ck_n | | PS_DDR_CKN_502 | BIDIR | DIFF_SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| N3 | DDR_ck_p | | PS_DDR_CKP_502 | BIDIR | DIFF_SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| N4 | DDR_addr[9] | | PS_DDR_A9_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N6 | DDR_ba[2] | | PS_DDR_BA2_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N7 | PWM_L | High Range | IO_L22P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N8 | PWM_R | High Range | IO_L22N_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N9 | csi_d_lp_p[0] | High Range | IO_L19N_T3_VREF_34 | INPUT | HSUL_12 | 34 | | | | NONE | | FIXED | PULLDOWN | | Internal | NONE | +| N10 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| N11 | csi_c_clk_p | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| N12 | csi_c_clk_n | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| N13 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | +| N14 | gpio_1_tri_io[3] | High Range | IO_L7N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P1 | DDR_addr[0] | | PS_DDR_A0_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P3 | DDR_addr[4] | | PS_DDR_A4_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P4 | DDR_addr[5] | | PS_DDR_A5_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P5 | DDR_addr[6] | | PS_DDR_A6_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P6 | DDR_addr[8] | | PS_DDR_A8_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| P8 | hdmi_data_p[0] | High Range | IO_L23P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P9 | hdmi_data_n[0] | High Range | IO_L23N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P10 | hdmi_data_p[1] | High Range | IO_L24P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P11 | hdmi_data_p[2] | High Range | IO_L16P_T2_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P13 | csi_d_p[1] | High Range | IO_L18P_T2_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| P14 | csi_d_n[1] | High Range | IO_L18N_T2_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| P15 | gpio_1_tri_io[17] | High Range | IO_L15P_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R1 | DDR_ba[1] | | PS_DDR_BA1_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R2 | DDR_cs_n | | PS_DDR_CS_B_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R3 | DDR_we_n | | PS_DDR_WE_B_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| R5 | DDR_cas_n | | PS_DDR_CAS_B_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R6 | DDR_ras_n | | PS_DDR_RAS_B_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R7 | hdmi_clk_p | High Range | IO_L20P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R8 | hdmi_clk_n | High Range | IO_L20N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R10 | hdmi_data_n[1] | High Range | IO_L24N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R11 | hdmi_data_n[2] | High Range | IO_L16N_T2_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R12 | gpio_1_tri_io[15] | High Range | IO_L17P_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R13 | gpio_1_tri_io[11] | High Range | IO_L17N_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| R15 | gpio_1_tri_io[4] | High Range | IO_L15N_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_io_report.xdc b/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_io_report.xdc new file mode 100644 index 0000000..bf8968b --- /dev/null +++ b/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_io_report.xdc @@ -0,0 +1,589 @@ +set_property PACKAGE_PIN C9 [get_ports FIXED_IO_ps_porb] +set_property PACKAGE_PIN K3 [get_ports DDR_odt] +set_property PACKAGE_PIN C7 [get_ports FIXED_IO_ps_clk] +set_property PACKAGE_PIN G2 [get_ports {DDR_dqs_p[1]}] +set_property PACKAGE_PIN A12 [get_ports {FIXED_IO_mio[30]}] +set_property PACKAGE_PIN A8 [get_ports {FIXED_IO_mio[2]}] +set_property PACKAGE_PIN B12 [get_ports {FIXED_IO_mio[28]}] +set_property PACKAGE_PIN D14 [get_ports {FIXED_IO_mio[27]}] +set_property PACKAGE_PIN A13 [get_ports {FIXED_IO_mio[26]}] +set_property PACKAGE_PIN C14 [get_ports {FIXED_IO_mio[25]}] +set_property PACKAGE_PIN B14 [get_ports {FIXED_IO_mio[24]}] +set_property PACKAGE_PIN A14 [get_ports {FIXED_IO_mio[23]}] +set_property PACKAGE_PIN D15 [get_ports {FIXED_IO_mio[22]}] +set_property PACKAGE_PIN C11 [get_ports {FIXED_IO_mio[21]}] +set_property PACKAGE_PIN E15 [get_ports {FIXED_IO_mio[20]}] +set_property PACKAGE_PIN A5 [get_ports {FIXED_IO_mio[1]}] +set_property PACKAGE_PIN B15 [get_ports {FIXED_IO_mio[18]}] +set_property PACKAGE_PIN D11 [get_ports {FIXED_IO_mio[17]}] +set_property PACKAGE_PIN A15 [get_ports {FIXED_IO_mio[16]}] +set_property PACKAGE_PIN D10 [get_ports {FIXED_IO_mio[15]}] +set_property PACKAGE_PIN B9 [get_ports {FIXED_IO_mio[14]}] +set_property PACKAGE_PIN C6 [get_ports {FIXED_IO_mio[13]}] +set_property PACKAGE_PIN B7 [get_ports {FIXED_IO_mio[12]}] +set_property PACKAGE_PIN B10 [get_ports {FIXED_IO_mio[11]}] +set_property PACKAGE_PIN D6 [get_ports {FIXED_IO_mio[10]}] +set_property PACKAGE_PIN D8 [get_ports {FIXED_IO_mio[0]}] +set_property PACKAGE_PIN B6 [get_ports {FIXED_IO_mio[8]}] +set_property PACKAGE_PIN D9 [get_ports {FIXED_IO_mio[7]}] +set_property PACKAGE_PIN A10 [get_ports {FIXED_IO_mio[6]}] +set_property PACKAGE_PIN A9 [get_ports {FIXED_IO_mio[5]}] +set_property PACKAGE_PIN C8 [get_ports {FIXED_IO_mio[4]}] +set_property PACKAGE_PIN A7 [get_ports {FIXED_IO_mio[3]}] +set_property PACKAGE_PIN C13 [get_ports {FIXED_IO_mio[31]}] +set_property PACKAGE_PIN D13 [get_ports {FIXED_IO_mio[29]}] +set_property PACKAGE_PIN C12 [get_ports {FIXED_IO_mio[19]}] +set_property PACKAGE_PIN H3 [get_ports FIXED_IO_ddr_vrp] +set_property PACKAGE_PIN R6 [get_ports DDR_ras_n] +set_property PACKAGE_PIN L4 [get_ports DDR_reset_n] +set_property PACKAGE_PIN R3 [get_ports DDR_we_n] +set_property PACKAGE_PIN J3 [get_ports FIXED_IO_ddr_vrn] +set_property PACKAGE_PIN B11 [get_ports FIXED_IO_ps_srstb] +set_property PACKAGE_PIN K1 [get_ports {DDR_addr[14]}] +set_property PACKAGE_PIN N1 [get_ports {DDR_addr[1]}] +set_property PACKAGE_PIN M1 [get_ports {DDR_addr[2]}] +set_property PACKAGE_PIN M4 [get_ports {DDR_addr[3]}] +set_property PACKAGE_PIN P3 [get_ports {DDR_addr[4]}] +set_property PACKAGE_PIN P4 [get_ports {DDR_addr[5]}] +set_property PACKAGE_PIN P5 [get_ports {DDR_addr[6]}] +set_property PACKAGE_PIN M5 [get_ports {DDR_addr[7]}] +set_property PACKAGE_PIN P6 [get_ports {DDR_addr[8]}] +set_property PACKAGE_PIN P1 [get_ports {DDR_addr[0]}] +set_property PACKAGE_PIN J1 [get_ports {DDR_addr[10]}] +set_property PACKAGE_PIN L2 [get_ports {DDR_addr[11]}] +set_property PACKAGE_PIN K2 [get_ports {DDR_addr[13]}] +set_property PACKAGE_PIN M2 [get_ports {DDR_addr[12]}] +set_property PACKAGE_PIN N4 [get_ports {DDR_addr[9]}] +set_property PACKAGE_PIN M6 [get_ports {DDR_ba[0]}] +set_property PACKAGE_PIN R1 [get_ports {DDR_ba[1]}] +set_property PACKAGE_PIN N6 [get_ports {DDR_ba[2]}] +set_property PACKAGE_PIN N3 [get_ports DDR_ck_p] +set_property PACKAGE_PIN R5 [get_ports DDR_cas_n] +set_property PACKAGE_PIN N2 [get_ports DDR_ck_n] +set_property PACKAGE_PIN B5 [get_ports {FIXED_IO_mio[9]}] +set_property PACKAGE_PIN L3 [get_ports DDR_cke] +set_property PACKAGE_PIN R2 [get_ports DDR_cs_n] +set_property PACKAGE_PIN B1 [get_ports {DDR_dm[0]}] +set_property PACKAGE_PIN D3 [get_ports {DDR_dm[1]}] +set_property PACKAGE_PIN H2 [get_ports {DDR_dq[15]}] +set_property PACKAGE_PIN A2 [get_ports {DDR_dq[1]}] +set_property PACKAGE_PIN C4 [get_ports {DDR_dq[2]}] +set_property PACKAGE_PIN C1 [get_ports {DDR_dq[3]}] +set_property PACKAGE_PIN B4 [get_ports {DDR_dq[4]}] +set_property PACKAGE_PIN A4 [get_ports {DDR_dq[5]}] +set_property PACKAGE_PIN C3 [get_ports {DDR_dq[6]}] +set_property PACKAGE_PIN A3 [get_ports {DDR_dq[7]}] +set_property PACKAGE_PIN E1 [get_ports {DDR_dq[8]}] +set_property PACKAGE_PIN D4 [get_ports {DDR_dq[0]}] +set_property PACKAGE_PIN E2 [get_ports {DDR_dq[10]}] +set_property PACKAGE_PIN E3 [get_ports {DDR_dq[11]}] +set_property PACKAGE_PIN F3 [get_ports {DDR_dq[12]}] +set_property PACKAGE_PIN G1 [get_ports {DDR_dq[13]}] +set_property PACKAGE_PIN H1 [get_ports {DDR_dq[14]}] +set_property PACKAGE_PIN D1 [get_ports {DDR_dq[9]}] +set_property PACKAGE_PIN B2 [get_ports {DDR_dqs_n[0]}] +set_property PACKAGE_PIN F2 [get_ports {DDR_dqs_n[1]}] +set_property PACKAGE_PIN C2 [get_ports {DDR_dqs_p[0]}] +set_property PACKAGE_PIN N12 [get_ports csi_c_clk_n] +set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p] +set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}] +set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}] +set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}] +set_property PACKAGE_PIN M11 [get_ports {csi_d_n[0]}] +set_property PACKAGE_PIN P14 [get_ports {csi_d_n[1]}] +set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}] +set_property INTERNAL_VREF 0.6 [get_iobanks 34] +set_property PACKAGE_PIN R8 [get_ports hdmi_clk_n] +set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p] +set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}] +set_property PACKAGE_PIN P9 [get_ports {hdmi_data_n[0]}] +set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}] +set_property PACKAGE_PIN R10 [get_ports {hdmi_data_n[1]}] +set_property PACKAGE_PIN R11 [get_ports {hdmi_data_n[2]}] +set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}] +set_property PACKAGE_PIN K15 [get_ports {gpio_1_tri_io[0]}] +set_property PACKAGE_PIN J14 [get_ports {gpio_1_tri_io[1]}] +set_property PACKAGE_PIN H12 [get_ports {gpio_1_tri_io[2]}] +set_property PACKAGE_PIN N14 [get_ports {gpio_1_tri_io[3]}] +set_property PACKAGE_PIN R15 [get_ports {gpio_1_tri_io[4]}] +set_property PACKAGE_PIN L14 [get_ports {gpio_1_tri_io[5]}] +set_property PACKAGE_PIN L15 [get_ports {gpio_1_tri_io[6]}] +set_property PACKAGE_PIN J13 [get_ports {gpio_1_tri_io[7]}] +set_property PACKAGE_PIN H14 [get_ports {gpio_1_tri_io[8]}] +set_property PACKAGE_PIN J15 [get_ports {gpio_1_tri_io[9]}] +set_property PACKAGE_PIN M15 [get_ports {gpio_1_tri_io[10]}] +set_property PACKAGE_PIN R13 [get_ports {gpio_1_tri_io[11]}] +set_property PACKAGE_PIN L13 [get_ports {gpio_1_tri_io[12]}] +set_property PACKAGE_PIN G11 [get_ports {gpio_1_tri_io[13]}] +set_property PACKAGE_PIN H11 [get_ports {gpio_1_tri_io[14]}] +set_property PACKAGE_PIN R12 [get_ports {gpio_1_tri_io[15]}] +set_property PACKAGE_PIN M14 [get_ports {gpio_1_tri_io[16]}] +set_property PACKAGE_PIN P15 [get_ports {gpio_1_tri_io[17]}] +set_property PACKAGE_PIN H13 [get_ports {gpio_1_tri_io[18]}] +set_property PACKAGE_PIN J11 [get_ports {gpio_1_tri_io[19]}] +set_property PACKAGE_PIN K11 [get_ports {gpio_1_tri_io[20]}] +set_property PACKAGE_PIN K13 [get_ports {gpio_1_tri_io[21]}] +set_property PACKAGE_PIN L12 [get_ports {gpio_1_tri_io[22]}] +set_property PACKAGE_PIN G12 [get_ports {gpio_1_tri_io[23]}] +set_property PACKAGE_PIN N8 [get_ports PWM_R] +set_property PACKAGE_PIN N7 [get_ports PWM_L] +set_property DIRECTION IN [get_ports {csi_d_lp_p[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}] +set_property DIRECTION IN [get_ports {csi_d_n[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_n[1]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_n[1]}] +set_property DIRECTION IN [get_ports {csi_d_n[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_n[0]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_n[0]}] +set_property DIRECTION IN [get_ports {csi_d_p[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_p[1]}] +set_property DIRECTION IN [get_ports {csi_d_p[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_p[0]}] +set_property DIRECTION IN [get_ports {csi_d_lp_n[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[2]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[1]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[0]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[2]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[1]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[0]}] +set_property DIRECTION OUT [get_ports hdmi_clk_p] +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p] +set_property DIRECTION OUT [get_ports hdmi_clk_n] +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_n] +set_property DIRECTION IN [get_ports csi_c_clk_p] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p] +set_property DIFF_TERM FALSE [get_ports csi_c_clk_p] +set_property DIRECTION IN [get_ports csi_c_clk_n] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_n] +set_property DIFF_TERM FALSE [get_ports csi_c_clk_n] +set_property DIRECTION IN [get_ports Vp_Vn_v_p] +set_property DIRECTION IN [get_ports Vp_Vn_v_n] +set_property DIRECTION OUT [get_ports PWM_R] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_R] +set_property DRIVE 12 [get_ports PWM_R] +set_property SLEW SLOW [get_ports PWM_R] +set_property DIRECTION OUT [get_ports PWM_L] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_L] +set_property DRIVE 12 [get_ports PWM_L] +set_property SLEW SLOW [get_ports PWM_L] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[23]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[23]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[23]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[23]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[22]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[22]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[22]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[21]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[21]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[21]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[21]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[20]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[20]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[20]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[19]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[19]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[19]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[19]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[18]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[18]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[18]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[17]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[17]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[17]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[17]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[16]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[16]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[16]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[15]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[15]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[15]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[14]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[14]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[14]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[13]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[13]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[13]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[12]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[12]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[12]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[11]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[11]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[11]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[10]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[10]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[10]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[9]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[9]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[9]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[8]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[8]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[8]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[7]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[7]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[7]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[6]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[6]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[6]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[5]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[5]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[5]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[4]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[4]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[4]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[3]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[3]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[3]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[2]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[2]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[2]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[1]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[1]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[1]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[0]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[0]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[0]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[31]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[31]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[31]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[31]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[31]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[30]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[30]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[30]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[30]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[30]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[29]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[29]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[29]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[29]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[29]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[28]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[28]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[28]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[28]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[28]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[27]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[27]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[27]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[27]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[27]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[26]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[26]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[26]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[26]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[26]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[25]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[25]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[25]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[25]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[25]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[24]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[24]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[24]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[24]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[24]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[23]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[23]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[23]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[23]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[23]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[22]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[22]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[22]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[22]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[21]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[21]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[21]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[21]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[21]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[20]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[20]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[20]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[20]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[19]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[19]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[19]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[19]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[19]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[18]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[18]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[18]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[18]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[17]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[17]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[17]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[17]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[17]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[16]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[16]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[16]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[16]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[15]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[15]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[15]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[14]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[14]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[14]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[13]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[13]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[13]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[12]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[12]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[12]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[11]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[11]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[11]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[10]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[10]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[10]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[9]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[9]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[9]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[9]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[8]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[8]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[8]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[7]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[7]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[7]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[6]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[6]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[6]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[5]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[5]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[5]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[4]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[4]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[4]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[3]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[3]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[3]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[2]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[2]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[2]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[1]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[1]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[1]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[1]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[0]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[0]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[0]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[0]}] +set_property DIRECTION INOUT [get_ports FIXED_IO_ddr_vrn] +set_property IOSTANDARD SSTL135_T_DCI [get_ports FIXED_IO_ddr_vrn] +set_property SLEW FAST [get_ports FIXED_IO_ddr_vrn] +set_property DIRECTION INOUT [get_ports FIXED_IO_ddr_vrp] +set_property IOSTANDARD SSTL135_T_DCI [get_ports FIXED_IO_ddr_vrp] +set_property SLEW FAST [get_ports FIXED_IO_ddr_vrp] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_clk] +set_property IOSTANDARD LVCMOS33 [get_ports FIXED_IO_ps_clk] +set_property DRIVE 12 [get_ports FIXED_IO_ps_clk] +set_property SLEW FAST [get_ports FIXED_IO_ps_clk] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_porb] +set_property IOSTANDARD LVCMOS33 [get_ports FIXED_IO_ps_porb] +set_property DRIVE 12 [get_ports FIXED_IO_ps_porb] +set_property SLEW FAST [get_ports FIXED_IO_ps_porb] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_srstb] +set_property IOSTANDARD LVCMOS33 [get_ports FIXED_IO_ps_srstb] +set_property DRIVE 12 [get_ports FIXED_IO_ps_srstb] +set_property SLEW FAST [get_ports FIXED_IO_ps_srstb] +set_property DIRECTION INOUT [get_ports {DDR_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL135_T_DCI [get_ports {DDR_dqs_p[1]}] +set_property SLEW FAST [get_ports {DDR_dqs_p[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL135_T_DCI [get_ports {DDR_dqs_p[0]}] +set_property SLEW FAST [get_ports {DDR_dqs_p[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL135_T_DCI [get_ports {DDR_dqs_n[1]}] +set_property SLEW FAST [get_ports {DDR_dqs_n[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL135_T_DCI [get_ports {DDR_dqs_n[0]}] +set_property SLEW FAST [get_ports {DDR_dqs_n[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[15]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[15]}] +set_property SLEW FAST [get_ports {DDR_dq[15]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[14]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[14]}] +set_property SLEW FAST [get_ports {DDR_dq[14]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[13]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[13]}] +set_property SLEW FAST [get_ports {DDR_dq[13]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[12]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[12]}] +set_property SLEW FAST [get_ports {DDR_dq[12]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[11]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[11]}] +set_property SLEW FAST [get_ports {DDR_dq[11]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[10]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[10]}] +set_property SLEW FAST [get_ports {DDR_dq[10]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[9]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[9]}] +set_property SLEW FAST [get_ports {DDR_dq[9]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[8]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[8]}] +set_property SLEW FAST [get_ports {DDR_dq[8]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[7]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[7]}] +set_property SLEW FAST [get_ports {DDR_dq[7]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[6]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[6]}] +set_property SLEW FAST [get_ports {DDR_dq[6]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[5]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[5]}] +set_property SLEW FAST [get_ports {DDR_dq[5]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[4]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[4]}] +set_property SLEW FAST [get_ports {DDR_dq[4]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[3]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[3]}] +set_property SLEW FAST [get_ports {DDR_dq[3]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[2]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[2]}] +set_property SLEW FAST [get_ports {DDR_dq[2]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[1]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[1]}] +set_property SLEW FAST [get_ports {DDR_dq[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[0]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[0]}] +set_property SLEW FAST [get_ports {DDR_dq[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dm[1]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dm[1]}] +set_property SLEW FAST [get_ports {DDR_dm[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dm[0]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dm[0]}] +set_property SLEW FAST [get_ports {DDR_dm[0]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[2]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_ba[2]}] +set_property SLEW SLOW [get_ports {DDR_ba[2]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[1]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_ba[1]}] +set_property SLEW SLOW [get_ports {DDR_ba[1]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[0]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_ba[0]}] +set_property SLEW SLOW [get_ports {DDR_ba[0]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[14]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[14]}] +set_property SLEW SLOW [get_ports {DDR_addr[14]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[13]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[13]}] +set_property SLEW SLOW [get_ports {DDR_addr[13]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[12]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[12]}] +set_property SLEW SLOW [get_ports {DDR_addr[12]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[11]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[11]}] +set_property SLEW SLOW [get_ports {DDR_addr[11]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[10]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[10]}] +set_property SLEW SLOW [get_ports {DDR_addr[10]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[9]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[9]}] +set_property SLEW SLOW [get_ports {DDR_addr[9]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[8]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[8]}] +set_property SLEW SLOW [get_ports {DDR_addr[8]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[7]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[7]}] +set_property SLEW SLOW [get_ports {DDR_addr[7]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[6]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[6]}] +set_property SLEW SLOW [get_ports {DDR_addr[6]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[5]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[5]}] +set_property SLEW SLOW [get_ports {DDR_addr[5]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[4]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[4]}] +set_property SLEW SLOW [get_ports {DDR_addr[4]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[3]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[3]}] +set_property SLEW SLOW [get_ports {DDR_addr[3]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[2]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[2]}] +set_property SLEW SLOW [get_ports {DDR_addr[2]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[1]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[1]}] +set_property SLEW SLOW [get_ports {DDR_addr[1]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[0]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[0]}] +set_property SLEW SLOW [get_ports {DDR_addr[0]}] +set_property DIRECTION INOUT [get_ports DDR_cas_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_cas_n] +set_property SLEW SLOW [get_ports DDR_cas_n] +set_property DIRECTION INOUT [get_ports DDR_ck_n] +set_property IOSTANDARD DIFF_SSTL135 [get_ports DDR_ck_n] +set_property SLEW FAST [get_ports DDR_ck_n] +set_property DIRECTION INOUT [get_ports DDR_ck_p] +set_property IOSTANDARD DIFF_SSTL135 [get_ports DDR_ck_p] +set_property SLEW FAST [get_ports DDR_ck_p] +set_property DIRECTION INOUT [get_ports DDR_cke] +set_property IOSTANDARD SSTL135 [get_ports DDR_cke] +set_property SLEW SLOW [get_ports DDR_cke] +set_property DIRECTION INOUT [get_ports DDR_cs_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_cs_n] +set_property SLEW SLOW [get_ports DDR_cs_n] +set_property DIRECTION INOUT [get_ports DDR_odt] +set_property IOSTANDARD SSTL135 [get_ports DDR_odt] +set_property SLEW SLOW [get_ports DDR_odt] +set_property DIRECTION INOUT [get_ports DDR_ras_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_ras_n] +set_property SLEW SLOW [get_ports DDR_ras_n] +set_property DIRECTION INOUT [get_ports DDR_reset_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_reset_n] +set_property SLEW FAST [get_ports DDR_reset_n] +set_property DIRECTION INOUT [get_ports DDR_we_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_we_n] +set_property SLEW SLOW [get_ports DDR_we_n] +#revert back to original instance +current_instance -quiet diff --git a/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_ip_status_report.txt b/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_ip_status_report.txt new file mode 100644 index 0000000..d728eff --- /dev/null +++ b/zynqberrydemo1/prebuilt/hardware/te0726_m/reports/zynqberrydemo1_ip_status_report.txt @@ -0,0 +1,152 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Mon Jun 12 13:57:38 2017 +| Host : W8-64-02 running 64-bit major release (build 9200) +| Command : report_ip_status +------------------------------------------------------------------------------------ + +IP Status Summary + +1. Project IP Status +-------------------- +Your project uses 29 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. + +More information on the Xilinx versioning policy is available at www.xilinx.com. + +Project IP Instances ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | +| | | | Log | | Version | | License | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_Video_IO_2_HDMI_TMDS_0_0 | Up-to-date | No changes required | Change | Video IO to HDMI | 1.0 | 1.0 (Rev. 26) | Included | xc7z010clg225-1 | +| | | | Log not | TMDS Interface | (Rev. | | | | +| | | | available | v1.0 | 26) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_i2s_adi_0_0 | Up-to-date | No changes required | Change | AXI I2S Audio | 1.2 | 1.2 (Rev. 1) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_interconnect_0_0 | Up-to-date | No changes required | *(1) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_mem_intercon_0 | Up-to-date | No changes required | *(2) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_reg32_0_0 | Up-to-date | No changes required | Change | AXI Register Bank | 1.0 | 1.0 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | Log not | 16/16 v1.0 | (Rev. | | | | +| | | | available | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_vdma_0_0 | Up-to-date | No changes required | *(3) | AXI Video Direct | 6.3 | 6.3 | Included | xc7z010clg225-1 | +| | | | | Memory Access | | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_vdma_0_1 | Up-to-date | No changes required | *(4) | AXI Video Direct | 6.3 | 6.3 | Included | xc7z010clg225-1 | +| | | | | Memory Access | | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_0_0 | Up-to-date | No changes required | *(5) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_3_0 | Up-to-date | No changes required | *(6) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_4_0 | Up-to-date | No changes required | *(7) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_fb_conv_0_0 | Up-to-date | No changes required | Change | axis_fb_conv_v1.0 | 1.0 | 1.0 (Rev. 5) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 5) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_raw_demosaic_0_0 | Up-to-date | No changes required | Change | RAW Demosaic v1.0 | 1.0 | 1.0 (Rev. 20) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 20) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_raw_unpack_0_0 | Up-to-date | No changes required | Change | RAW10 Unpack v1.0 | 1.0 | 1.0 (Rev. 17) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 17) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_to_i2s_0_0 | Up-to-date | No changes required | Change | AXI4-Stream to I2S | 1.0 | 1.0 (Rev. 4) | Included | xc7z010clg225-1 | +| | | | Log not | v1.0 | (Rev. | | | | +| | | | available | | 4) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_clk_wiz_1_0 | Up-to-date | No changes required | *(8) | Clocking Wizard | 5.4 | 5.4 | Included | xc7z010clg225-1 | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_csi2_d_phy_rx_0_0 | Up-to-date | No changes required | Change | CSI-2 D-PHY RX | 1.0 | 1.0 (Rev. 35) | Included | xc7z010clg225-1 | +| | | | Log not | v1_0 | (Rev. | | | | +| | | | available | | 35) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_csi_to_axis_0_0 | Up-to-date | No changes required | Change | CSI-2 to | 1.0 | 1.0 (Rev. 46) | Included | xc7z010clg225-1 | +| | | | Log not | AXI4-Stream v1.0 | (Rev. | | | | +| | | | available | | 46) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_i2s_to_pwm_0_0 | Up-to-date | No changes required | Change | I2S to PWM v1.0 | 1.0 | 1.0 (Rev. 7) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 7) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_proc_sys_reset_0_0 | Up-to-date | No changes required | *(9) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z010clg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_proc_sys_reset_1_0 | Up-to-date | No changes required | *(10) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z010clg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_processing_system7_0_0 | Up-to-date | No changes required | *(11) | ZYNQ7 Processing | 5.5 | 5.5 (Rev. 5) | Included | xc7z010clg225-1 | +| | | | | System | (Rev. | | | | +| | | | | | 5) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_processing_system7_0_axi_periph_0 | Up-to-date | No changes required | *(12) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_rst_processing_system7_0_50M_0 | Up-to-date | No changes required | *(13) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z010clg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_v_axi4s_vid_out_0_0 | Up-to-date | No changes required | *(14) | AXI4-Stream to | 4.0 | 4.0 (Rev. 6) | Included | xc7z010clg225-1 | +| | | | | Video Out | (Rev. | | | | +| | | | | | 6) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_v_tc_0_0 | Up-to-date | No changes required | *(15) | Video Timing | 6.1 | 6.1 (Rev. 10) | Included | xc7z010clg225-1 | +| | | | | Controller | (Rev. | | | | +| | | | | | 10) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xadc_wiz_0_0 | Up-to-date | No changes required | *(16) | XADC Wizard | 3.3 | 3.3 (Rev. 3) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 3) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlconcat_0_0 | Up-to-date | No changes required | *(17) | Concat | 2.1 | 2.1 (Rev. 1) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlslice_0_0 | Up-to-date | No changes required | Change | Slice | 1.0 | 1.0 (Rev. 1) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlslice_1_0 | Up-to-date | No changes required | Change | Slice | 1.0 | 1.0 (Rev. 1) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +*(1) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(2) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(3) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt +*(4) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt +*(5) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(6) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(7) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(8) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/clk_wiz_v5_4/doc/clk_wiz_v5_4_changelog.txt +*(9) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(10) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(11) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/processing_system7_v5_5/doc/processing_system7_v5_5_changelog.txt +*(12) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(13) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(14) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/v_axi4s_vid_out_v4_0/doc/v_axi4s_vid_out_v4_0_changelog.txt +*(15) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/v_tc_v6_1/doc/v_tc_v6_1_changelog.txt +*(16) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/xadc_wiz_v3_3/doc/xadc_wiz_v3_3_changelog.txt +*(17) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt + + diff 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    + *        NumBd = 2,
+ *        Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ *        if (Status != XST_SUCCESS)
+ *        {
+ *            *Not enough BDs available for the request*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * 
    + *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ * 
    
+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ *     parameter.
+ *   - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ *       parameter. Doing so will lead to data corruption and system
+ *       instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr)
+{
+	LONG Status;
+	/* Enough free BDs available for the request? */
+	if (RingPtr->FreeCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead forward */
+	*BdSetPtr = RingPtr->FreeHead;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt -= NumBd;
+	RingPtr->PreCnt += NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * 
    + *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *        ...
+ *    if (Error)
+ *    {
+ *        Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ *    }
+ * 
    
+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * 
    + *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *    BdsLeft = 10,
+ *    CurBdPtr = BdPtr,
+ *
+ *    while (BdsLeft)
+ *    {
+ *       if (Error)
+ *       {
+ *          Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
+ *       }
+ *
+ *       CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
+ *       BdsLeft--,
+ *    }
+ * 
    
+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the BDs were unallocated.
+ *   - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ *     the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	(void) BdSetPtr;
+	Xil_AssertNonvoid(RingPtr != NULL);
+	Xil_AssertNonvoid(BdSetPtr != NULL);
+
+	/* Enough BDs in the free state for the request? */
+	if (RingPtr->PreCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead backward */
+		XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PreCnt -= NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ *   - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ *     did not have its "last" bit set.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 i;
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	CurBdPtr = BdSetPtr;
+			for (i = 0U; i < NumBd; i++) {
+				CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+	}
+	/* Adjust ring pointers & counters */
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+	RingPtr->PreCnt -= NumBd;
+	RingPtr->HwTail = CurBdPtr;
+	RingPtr->HwCnt += NumBd;
+
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
    + *        NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ *        if (NumBd == 0)
+ *        {
+ *           * hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
    + *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * 
    
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Sop = 0U;
+	u32 Status;
+	u32 BdLimitLoc = BdLimit;
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+		if (BdLimitLoc > RingPtr->HwCnt){
+			BdLimitLoc = RingPtr->HwCnt;
+	}
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has not completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+		while (BdCount < BdLimitLoc) {
+		/* Read the status */
+			if(CurBdPtr != NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+
+			if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+				Sop = 1U;
+			}
+			if (Sop == 0x00000001U) {
+			BdCount++;
+			BdPartialCount++;
+		}
+
+		/* hardware has processed this BD so check the "last" bit.
+		 * If it is clear, then there are more BDs for the current
+		 * packet. Keep a count of these partial packet BDs.
+		 */
+			if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+				Sop = 0U;
+				BdPartialCount = 0U;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+        BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+		} else {
+			*BdSetPtr = NULL;
+			Status = 0U;
+	}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
    + *        NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           *hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
    + *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * 
    
+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Status;
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+	while (BdCount < BdLimit) {
+
+		/* Read the status */
+			if(CurBdPtr!=NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+			if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+			break;
+		}
+
+		BdCount++;
+
+		/* hardware has processed this BD so check the "last" bit. If
+                 * it is clear, then there are more BDs for the current packet.
+                 * Keep a count of these partial packet BDs.
+		 */
+			if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+				BdPartialCount = 0U;
+			} else {
+			BdPartialCount++;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+	BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+	}
+	else {
+		*BdSetPtr = NULL;
+			Status = 0U;
+	}
+}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0x00000000U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	/* Update pointers and counters */
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PostCnt -= NumBd;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ *   - Is the BD ring linked correctly in physical address space.
+ *   - Do the internal pointers point to BDs in the ring.
+ *   - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_NO_LIST if the list has not been created.
+ *   - XST_IS_STARTED if the channel is not stopped.
+ *   - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ *     structures. If this value is returned, the channel should be reset to
+ *     avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+	UINTPTR AddrV, AddrP;
+	u32 i;
+
+	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Is the list created */
+	if (RingPtr->AllCnt == 0x00000000U) {
+		return (LONG)(XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't check if channel is running */
+	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+		return (LONG)(XST_IS_STARTED);
+	}
+
+	/* RunState doesn't make sense */
+	if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal pointers point to correct memory space */
+	AddrV = (UINTPTR) RingPtr->FreeHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PreHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwTail;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PostHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal counters add up */
+	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+	     RingPtr->PostCnt) != RingPtr->AllCnt) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify BDs are linked correctly */
+	AddrV = RingPtr->BaseBdAddr;
+	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+	for (i = 1U; i < RingPtr->AllCnt; i++) {
+		/* Check BDA for this BD. It should point to next physical addr */
+		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+
+		/* Move on to next BD */
+		AddrV += RingPtr->Separation;
+		AddrP += RingPtr->Separation;
+	}
+
+	/* Last BD should have wrap bit set */
+	if (XEMACPS_SEND == Direction) {
+		if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+	else {			/* XEMACPS_RECV */
+		if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+
+	/* No problems found */
+	return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueRx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueRx = *TempPtr;
+		DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+		*TempPtr = DataValueRx;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueTx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueTx = *TempPtr;
+		DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+		*TempPtr = DataValueTx;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * Reset BD ring head and tail pointers.
+ *
+ * @param RingPtr is the instance to be worked on.
+ * @param VirtAddr is the virtual base address of the user memory region.
+ *
+ * @note
+ * Should be called after XEmacPs_Stop()
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+ *
+ *****************************************************************************/
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc)
+{
+	RingPtr->FreeHead = virtaddrloc;
+	RingPtr->PreHead = virtaddrloc;
+	RingPtr->HwHead = virtaddrloc;
+	RingPtr->HwTail = virtaddrloc;
+	RingPtr->PostHead = virtaddrloc;
+}
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
new file mode 100644
index 0000000..b89e898
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h
@@ -0,0 +1,241 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_7
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6   rb   09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+*		      changed to volatile.
+*
+* 
    
+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
+#define XEMACPS_BDRING_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
+	u32 Length;	 /**< Total size of ring in bytes */
+	u32 RunState;	 /**< Flag to indicate DMA is started */
+	u32 Separation;	 /**< Number of bytes between the starting address
+                                  of adjacent BDs */
+	XEmacPs_Bd *FreeHead;
+			     /**< First BD in the free group */
+	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+	XEmacPs_Bd *HwHead; /**< First BD in the work group */
+	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+	XEmacPs_Bd *PostHead;
+			     /**< First BD in the post-work group */
+	XEmacPs_Bd *BdaRestart;
+			     /**< BDA to load when channel is started */
+
+	volatile u32 HwCnt;    /**< Number of BDs in work group */
+	u32 PreCnt;     /**< Number of BDs in pre-work group */
+	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
+	u32 PostCnt;    /**< Number of BDs in post-work group */
+	u32 AllCnt;     /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
+    (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+*        parameter must be a power of 2 to get an accurate calculation (32, 64,
+*        128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+*         given memory constraints.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
+    (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
+    (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
+    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
+    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
+    (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
+    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
new file mode 100644
index 0000000..8217a45
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c
@@ -0,0 +1,1174 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_7
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *					   register. Added a new API for setting the BURST length
+ *					   in DMACR register.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 
    
+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device.  The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	}
+	else{
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the MAC bits [31:0] in BOT */
+		MacAddr = *(Aptr);
+		MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+		MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+		MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+	/* There are reserved bits in TOP so don't affect them */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+		MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+	/* Set MAC bits [47:32] in TOP */
+		MacAddr |= (u32)(*(Aptr+4));
+		MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Aptr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	IndexLoc--;
+
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*Aptr = (u8) MacAddr;
+	*(Aptr+1) = (u8) (MacAddr >> 8U);
+	*(Aptr+2) = (u8) (MacAddr >> 16U);
+	*(Aptr+3) = (u8) (MacAddr >> 24U);
+
+	/* Read MAC bits [47:32] in TOP */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*(Aptr+4) = (u8) MacAddr;
+	*(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * 
    + * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
+ * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
+ * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
+ * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
+ * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
+ * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
+ * 
    
+ *
+ * da[0] represents the least significant bit of the first byte received,
+ * that is, the multicast/unicast indicator, and da[47] represents the most
+ * significant bit of the last byte received.
+ *
+ * If the hash index points to a bit that is set in the hash register then
+ * the frame will be matched according to whether the frame is multicast
+ * or unicast.
+ *
+ * A multicast match will be signaled if the multicast hash enable bit is
+ * set, da[0] is logic 1 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * A unicast match will be signaled if the unicast hash enable bit is set,
+ * da[0] is logic 0 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * To receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the network
+ * configuration register.
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+				(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
+			Status = (LONG)(XST_INVALID_PARAM);
+		} else {
+
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr |= (u32)(0x00000001U << Result);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Delete 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was deleted successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+					(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
+			Status =  (LONG)(XST_INVALID_PARAM);
+		} else {
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << Result));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+/*****************************************************************************/
+/**
+ * Clear the Hash registers for the mac address pointed by AddressPtr.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ *****************************************************************************/
+void XEmacPs_ClearHash(XEmacPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET, 0x0U);
+
+	/* write bits [63:32] in TOP */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET, 0x0U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the Hash address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current HASH MAC address will be copied.
+ *
+ *****************************************************************************/
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 *Aptr = (u32 *)(void *)AddressPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(AddressPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	*(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET);
+
+	/* Read Hash bits [63:32] in TOP */
+	*(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the Type ID match for this driver/device.  The register is a 32-bit
+ * value. The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Id_Check is type ID to be configured.
+ * @param Index is a index to which Type ID (1-4).
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
+{
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the ID bits in MATCHx register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Set options for the driver/device. The driver should be stopped with
+ * XEmacPs_Stop() before changing options.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to set. Multiple options can be set by OR'ing
+ *        XTE_*_OPTIONS constants together. Options not specified are not
+ *        affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic register contents */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/*
+	 * It is configured to max 1536.
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn on VLAN packet only, only VLAN tagged will be accepted */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
+	}
+
+	/* Turn on FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
+	}
+
+	/* Turn on length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
+	}
+
+	/* Turn on flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
+	}
+
+	/* Turn on promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
+	}
+
+	/* Allow broadcast address reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
+	}
+
+	/* Allow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
+	}
+
+	/* enable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+	}
+
+	/* Enable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK);
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Enable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+		Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Enable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_TXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Enable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_RXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * the option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options |= Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear options for the driver/device
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to clear. Multiple options can be cleared by
+ *        OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
+ *        are not affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/* There is only RX configuration!?
+	 * It is configured in two different length, upto 1536 and 10240 bytes
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn off VLAN packet only */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
+	}
+
+	/* Turn off FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
+	}
+
+	/* Turn off length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
+	}
+
+	/* Turn off flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
+	}
+
+	/* Turn off promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
+	}
+
+	/* Disallow broadcast address filtering => broadcast reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
+	}
+
+	/* Disallow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
+	}
+
+	/* Disable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
+	}
+
+	/* Disable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~(XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK));
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Disable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+			Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Disable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Disable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options &= ~Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get current option settings
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
+ * as a set opion.
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	return (InstancePtr->Options);
+}
+
+
+/*****************************************************************************/
+/**
+ * Send a pause packet
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * - XST_SUCCESS if pause frame transmission was initiated
+ * - XST_DEVICE_IS_STOPPED if the device has not been started.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Make sure device is ready for this operation */
+	if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STOPPED);
+	} else {
+	/* Send flow control frame */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
+ * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ *
+ * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
+ *         megabits per second.
+ *
+ * @note
+ *
+ *****************************************************************************/
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	u16 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+
+	if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
+		Status = (u16)(1000);
+	} else {
+		if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
+			Status = (u16)(100);
+		} else {
+			Status = (u16)(10);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
+ * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
+ * link speed.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
+ *        or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
+ *
+ * @note
+ *
+ *****************************************************************************/
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
+{
+        u32 Reg;
+	u16 Status;
+        Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
+
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
+
+	switch (Speed) {
+		case (u16)10:
+				Status = 0U;
+                break;
+
+        case (u16)100:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_100_MASK;
+                break;
+
+        case (u16)1000:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_1000_MASK;
+                break;
+
+        default:
+			Status = 1U;
+                break;
+    }
+	if(Status == (u16)1){
+                return;
+        }
+
+        /* Set register and return */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the MDIO clock divisor.
+ *
+ * Calculating the divisor:
+ *
+ * 
    + *              f[HOSTCLK]
+ *   f[MDC] = -----------------
+ *            (1 + Divisor) * 2
+ * 
    
+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ * 
    + * 000 : divide pclk by   8 (pclk up to  20 MHz)
+ * 001 : divide pclk by  16 (pclk up to  40 MHz)
+ * 010 : divide pclk by  32 (pclk up to  80 MHz)
+ * 011 : divide pclk by  48 (pclk up to 120 MHz)
+ * 100 : divide pclk by  64 (pclk up to 160 MHz)
+ * 101 : divide pclk by  96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ * 
    
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+	u32 Reg;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCFG_OFFSET);
+	/* clear these three bits, could be done with mask */
+	Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+	Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+*        which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpReadTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+			IpReadTemp = Ipisr;
+		} while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+	/* Read data */
+		*PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_PHYMNTNC_OFFSET);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY.  Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+*   status from the MAC on a write, the user should read the PHY to verify the
+*   write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpWriteTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+				IpWriteTemp = Ipisr;
+		} while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+	u32 Reg;
+	u32 RegUpdateVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+					(BLength == XEMACPS_4BYTE_BURST) ||
+					(BLength == XEMACPS_8BYTE_BURST) ||
+					(BLength == XEMACPS_16BYTE_BURST));
+
+	switch (BLength) {
+		case XEMACPS_SINGLE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+			break;
+
+		case XEMACPS_4BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+			break;
+
+		case XEMACPS_8BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+			break;
+
+		case XEMACPS_16BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+			break;
+
+		default:
+			RegUpdateVal = 0x00000000U;
+			break;
+	}
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_DMACR_OFFSET);
+
+	Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+	Reg |= RegUpdateVal;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+																	Reg);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
new file mode 100644
index 0000000..2554f27
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_ETHERNET_0_DEVICE_ID,
+		XPAR_PS7_ETHERNET_0_BASEADDR,
+		XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
new file mode 100644
index 0000000..00e79a5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_7
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc  28/06/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status registers
+*	Disable Rx and Tx engines
+*	Update the Tx and Rx descriptor queue registers with reset values
+*	Update the other relevant control registers with reset value
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+	u32 RegVal;
+
+	/* Disable the interrupts  */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+	/* Stop transmission,disable loopback and Stop tx and Rx engines */
+	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+	RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+				(u32)XEMACPS_NWCTRL_RXEN_MASK|
+				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
+				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+	/* Clear the statistic registers, flush the packets in DPRAM*/
+	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+	/* Clear the interrupt status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+	/* Clear the tx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
+									(u32)XEMACPS_TXSR_TXGO_MASK));
+	/* Clear the rx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+								XEMACPS_RXSR_FRAMERX_MASK);
+	/* Clear the tx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+	/* Clear the rx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+	/* Update the network config register with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+	/* Update the hash address registers with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
new file mode 100644
index 0000000..e535470
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_7
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 
    
+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
+#define XEMACPS_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR     4U   /**< Maxmum number of mac address
+                                           supported */
+#define XEMACPS_MAX_TYPE_ID      4U   /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT     64U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT     4U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U   /**< Minimum buffer alignment when using
+                                           options that impose alignment
+                                           restrictions on the buffer data on
+                                           the local bus */
+
+/** @name Direction identifiers
+ *
+ *  These are used by several functions and callbacks that need
+ *  to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND        1U	      /**< send direction */
+#define XEMACPS_RECV        2U	      /**< receive direction */
+/*@}*/
+
+/**  @name MDC clock division
+ *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+                                       bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT   64U /**< Number of receive buffer bytes as a
+                                       unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD     128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD     128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET        0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET         0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET          0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET         0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET          0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET       0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET       0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET          0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET           0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET           0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET           0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET           0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET      0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET       0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET       0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET   0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET         0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET         0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET       0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET       0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET       0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET       0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET       0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET       0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET       0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET       0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET        0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET        0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET        0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET        0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET       0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET        0x00000100U /**< Octects transmitted Low
+                                                      reg */
+#define XEMACPS_OCTTXH_OFFSET        0x00000104U /**< Octects transmitted High
+                                                      reg */
+
+#define XEMACPS_TXCNT_OFFSET         0x00000108U /**< Error-free Frmaes
+                                                      transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET       0x0000010CU /**< Error-free Broadcast
+                                                      Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET       0x00000110U /**< Error-free Multicast
+                                                      Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114U /**< Pause Frames Transmitted
+                                                      Counter */
+#define XEMACPS_TX64CNT_OFFSET       0x00000118U /**< Error-free 64 byte Frames
+                                                      Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET       0x0000011CU /**< Error-free 65-127 byte
+                                                      Frames Transmitted
+                                                      counter */
+#define XEMACPS_TX128CNT_OFFSET      0x00000120U /**< Error-free 128-255 byte
+                                                      Frames Transmitted
+                                                      counter*/
+#define XEMACPS_TX256CNT_OFFSET      0x00000124U /**< Error-free 256-511 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX512CNT_OFFSET      0x00000128U /**< Error-free 512-1023 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1024CNT_OFFSET     0x0000012CU /**< Error-free 1024-1518 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1519CNT_OFFSET     0x00000130U /**< Error-free larger than
+                                                      1519 byte Frames
+                                                      transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET     0x00000134U /**< TX under run error
+                                                      counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138U /**< Single Collision Frame
+                                                      Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013CU /**< Multiple Collision Frame
+                                                      Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+                                                      Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144U /**< Late Collision Frame
+                                                      Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148U /**< Deferred Transmission
+                                                      Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014CU /**< Transmit Carrier Sense
+                                                      Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET        0x00000150U /**< Octects Received register
+                                                      Low */
+#define XEMACPS_OCTRXH_OFFSET        0x00000154U /**< Octects Received register
+                                                      High */
+
+#define XEMACPS_RXCNT_OFFSET         0x00000158U /**< Error-free Frames
+                                                      Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET    0x0000015CU /**< Error-free Broadcast
+                                                      Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET    0x00000160U /**< Error-free Multicast
+                                                      Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164U /**< Pause Frames
+                                                      Received Counter */
+#define XEMACPS_RX64CNT_OFFSET       0x00000168U /**< Error-free 64 byte Frames
+                                                      Received Counter */
+#define XEMACPS_RX65CNT_OFFSET       0x0000016CU /**< Error-free 65-127 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET      0x00000170U /**< Error-free 128-255 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET      0x00000174U /**< Error-free 256-512 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET      0x00000178U /**< Error-free 512-1023 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET     0x0000017CU /**< Error-free 1024-1518 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET     0x00000180U /**< Error-free 1519-max byte
+                                                      Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184U /**< Undersize Frames Received
+                                                      Counter */
+#define XEMACPS_RXOVRCNT_OFFSET      0x00000188U /**< Oversize Frames Received
+                                                      Counter */
+#define XEMACPS_RXJABCNT_OFFSET      0x0000018CU /**< Jabbers Received
+                                                      Counter */
+#define XEMACPS_RXFCSCNT_OFFSET      0x00000190U /**< Frame Check Sequence
+                                                      Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194U /**< Length Field Error
+                                                      Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0U /**< Receive Resource Error
+                                                      Counter */
+#define XEMACPS_RXORCNT_OFFSET       0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8U /**< IP header Checksum Error
+                                                      Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET     0x000001ACU /**< TCP Checksum Error
+                                                      Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
+                                                      Counter */
+#define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
+						      offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
+						      adjustment counter */
+#define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
+						      increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
+						      counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+						      nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
+						      counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+						      nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
+						      second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+						      nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
+						      second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+						      nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
+							reg */
+#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
+							reg */
+#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
+							reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
+							reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
+							reg */
+#define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
+							reg */
+#define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
+							reg */
+#define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
+							reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
+							Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+                                                         pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400U /**< Halt transmission
+                                                         after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080U /**< Enable writing to
+                                                         stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040U /**< Increment statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020U /**< Clear statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+                                                        non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK     0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000U /**< disable rejection of
+                                                        FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000U /**< enable RX checksum
+                                                        offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+                                                        Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
+                                                        received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK      0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK        0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100U /**< Enable 1536 byte
+                                                        frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020U /**< Do not receive
+                                                        broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004U /**< Receive only VLAN
+                                                        frames */
+#define XEMACPS_NWCFG_FDEN_MASK        0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK         0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK       0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK         0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK        0x0000FFFFU /**< Address bits[47:32]
+                                                      bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
+													size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
+												size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
+													    checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK        0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010U /**< Transmit buffs exhausted
+                                                       mid frame */
+#define XEMACPS_TXSR_TXGO_MASK        0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK       0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK      ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_TXSR_URUN_MASK | \
+                                       (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+                                       (u32)XEMACPS_TXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+                                       (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK       0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK      ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_RXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000U /**< PTP Pdelay_req
+						     transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK     0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000U /**< PTP Delay_req transmitted
+						*/
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK     0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
+                                                     zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
+                                                     no buffers*/
+#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
+                                     (u32)XEMACPS_IXR_RETRY_MASK |         \
+                                     (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK    ((u32)XEMACPS_IXR_HRESPNOK_MASK |      \
+                                     (u32)XEMACPS_IXR_RXUSED_MASK |        \
+                                     (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET  0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET  0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET  0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process.  After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK  0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK  0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK  0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK   0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK   0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK  0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK   0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK     0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK       0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000U /**< Specific address
+                                                      matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK      0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK       0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK       0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK       0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK       0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK       0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK      0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK       0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32  Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+    XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+*         u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+    XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
new file mode 100644
index 0000000..9c355a1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c
@@ -0,0 +1,268 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_7
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
+*		      Rx errors. Under heavy Rx traffic, there will be a large
+*		      number of errors related to receive buffer not available.
+*		      Because of a HW bug (SI #692601), under such heavy errors,
+*		      the Rx data path can become unresponsive. To reduce the
+*		      probabilities for hitting this HW bug, the SW writes to
+*		      bit 18 to flush a packet from Rx DPRAM immediately. The
+*		      changes for it are done in the function
+*		      XEmacPs_IntrHandler.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+*		       and 64-bit changes.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+*                     there is no error. CR# 869403
+* 
    
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ *        XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ *        when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef)
+{
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FuncPointer != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	switch (HandlerType) {
+	case XEMACPS_HANDLER_DMASEND:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->SendRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_DMARECV:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->RecvRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_ERROR:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+		InstancePtr->ErrorRef = CallBackRef;
+		break;
+	default:
+		Status = (LONG)(XST_INVALID_PARAM);
+		break;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+*        interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+	u32 RegISR;
+	u32 RegSR;
+	u32 RegCtrl;
+	u32 RegQ1ISR = 0U;
+	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* This ISR will try to handle as many interrupts as it can in a single
+	 * call. However, in most of the places where the user's error handler
+         * is called, this ISR exits because it is expected that the user will
+         * reset the device in nearly all instances.
+	 */
+	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_ISR_OFFSET);
+
+	/* Read Transmit Q1 ISR */
+
+	if (InstancePtr->Version > 2)
+		RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET);
+
+	/* Clear the interrupt status register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   RegISR);
+
+	/* Receive complete interrupt */
+	if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+		/* Clear RX status register RX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET,
+				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
+		InstancePtr->RecvHandler(InstancePtr->RecvRef);
+	}
+
+	/* Transmit Q1 complete interrupt */
+	if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET,
+				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Transmit complete interrupt */
+	if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Receive error conditions interrupt */
+	if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+		/* Clear RX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_RXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET, RegSR);
+
+		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
+		 * register to flush a packet out of Rx SRAM upon
+		 * an error for receive buffer not available. */
+		if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+			RegCtrl =
+			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_NWCTRL_OFFSET);
+			RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET, RegCtrl);
+		}
+
+		if(RegSR != 0) {
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+						XEMACPS_RECV, RegSR);
+		}
+	}
+
+        /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+         * will be asserted the same time.
+         * Have to distinguish this bit to handle the real error condition.
+         */
+	/* Transmit Q1 error conditions interrupt */
+        if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+            ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+			/* Clear Interrupt Q1 status register */
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegQ1ISR);
+	   }
+
+	/* Transmit error conditions interrupt */
+        if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+            (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_TXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET, RegSR);
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegSR);
+	}
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
new file mode 100644
index 0000000..e2d2078
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_7
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 New
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+	XEmacPs_Config *CfgPtr = NULL;
+	u32 i;
+
+	for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmacPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
new file mode 100644
index 0000000..7b6fe2e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c
@@ -0,0 +1,628 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device. The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	ConfigPtr points to the XGpioPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address should be passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status = XST_SUCCESS;
+	u8 i;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0U;
+	InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Handler = StubHandler;
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	/* Initialize the Bank data based on platform */
+	if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/*
+		 *	Max pins in the ZynqMP GPIO device
+		 *	0 - 25,  Bank 0
+		 *	26 - 51, Bank 1
+		 *	52 - 77, Bank 2
+		 *	78 - 109, Bank 3
+		 *	110 - 141, Bank 4
+		 *	142 - 173, Bank 5
+		 */
+		InstancePtr->MaxPinNum = (u32)174;
+		InstancePtr->MaxBanks = (u8)6;
+	} else {
+		/*
+		 *	Max pins in the GPIO device
+		 *	0 - 31,  Bank 0
+		 *	32 - 53, Bank 1
+		 *	54 - 85, Bank 2
+		 *	86 - 117, Bank 3
+		 */
+		InstancePtr->MaxPinNum = (u32)118;
+		InstancePtr->MaxBanks = (u8)4;
+	}
+
+	/*
+	 * By default, interrupts are not masked in GPIO. Disable
+	 * interrupts for all pins in all the 4 banks.
+	 */
+	for (i=0;iMaxBanks;i++) {
+		XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+					  ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+					  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+	}
+
+	/* Indicate the component is now ready to use. */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	Current value of the Data register.
+*
+* @note		This function is used for reading the state of all the GPIO pins
+*		of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the data has to be read.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*		See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return	Current value of the Pin (0 or 1).
+*
+* @note		This function is used for reading the state of the specified
+*		GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Data is the value to be written to the Data register.
+*
+* @return	None.
+*
+* @note		This function is used for writing to all the GPIO pins of
+*		the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+			  XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	Data is the data to be written to the specified pin (0 or 1).
+*
+* @return	None.
+*
+* @note		This function does a masked write to the specified pin of
+*		the specified GPIO bank. The previous state of other pins
+*		is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+	u32 RegOffset;
+	u32 Value;
+	u8 Bank;
+	u8 PinNumber;
+	u32 DataVar = Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	if (PinNumber > 15U) {
+		/* There are only 16 data bits in bit maskable register. */
+		PinNumber -= (u8)16;
+		RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+	} else {
+		RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+	}
+
+	/*
+	 * Get the 32 bit value to be written to the Mask/Data register where
+	 * the upper 16 bits is the mask and lower 16 bits is the data.
+	 */
+	DataVar &= (u32)0x01;
+	Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+			  RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Direction is the 32 bit mask of the Pin direction to be set for
+*		all the pins in the Bank. Bits with 0 are set to Input mode,
+*		bits with 1 are	set to Output Mode.
+*
+* @return	None.
+*
+* @note		This function is used for setting the direction of all the pins
+*		in the specified bank. The previous state of the pins is
+*		not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	Direction is the direction to be set for the specified pin.
+*		Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return	None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 DirModeReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(Direction <= (u32)1);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_DIRM_OFFSET);
+
+	if (Direction!=(u32)0) { /*  Output Direction */
+		DirModeReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Input Direction */
+		DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			 XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return	Returns a 32 bit mask of the Direction register. Bits with 0 are
+*		in Input mode, bits with 1 are in Output Mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Direction is to be
+*		retrieved.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	Direction of the specified pin.
+*		- 0 for Input Direction
+*		- 1 for Output Direction
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	OpEnable is the 32 bit mask of the Output Enables to be set for
+*		all the pins in the Bank. The Output Enable of bits with 0 are
+*		disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return	None.
+*
+* @note		This function is used for setting the Output Enables of all the
+*		pins in the specified bank. The previous state of the Output
+*		Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	OpEnable specifies whether the Output Enable for the specified
+*		pin should be enabled.
+*		Valid values are 0 for Disabling Output Enable,
+*		1 for Enabling Output Enable.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 OpEnableReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(OpEnable <= (u32)1);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_OUTEN_OFFSET);
+
+	if (OpEnable != (u32)0) { /*  Enable Output Enable */
+		OpEnableReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Disable Output Enable */
+		OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return	Returns a a 32 bit mask of the Output Enable register.
+*		Bits with 0 are in Disabled state, bits with 1 are in
+*		Enabled State.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Output Enable status is to
+*		be retrieved.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	Output Enable of the specified pin.
+*		- 0 if Output Enable is disabled for this pin
+*		- 1 if Output Enable is enabled for this pin
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param	PinNumber is the Pin number in the GPIO device.
+* @param	BankNumber returns the Bank in which this GPIO pin is present.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+{
+	u32 XGpioPsPinTable[6] = {0};
+	u32 Platform = XGetPlatform_Info();
+
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/*
+		 * This structure defines the mapping of the pin numbers to the banks when
+		 * the driver APIs are used for working on the individual pins.
+		 */
+
+		XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+		XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+		XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+		XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+		XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+		XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+		*BankNumber = 0U;
+		while (*BankNumber < 6U) {
+			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+				break;
+			}
+			(*BankNumber)++;
+		}
+	} else {
+		XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+		XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+		XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+		XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+		*BankNumber = 0U;
+		while (*BankNumber < 4U) {
+			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+				break;
+			}
+			(*BankNumber)++;
+		}
+	}
+	if (*BankNumber == (u8)0) {
+		*PinNumberInBank = PinNumber;
+	} else {
+		*PinNumberInBank = (u8)((u32)PinNumber %
+					(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+	}
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
new file mode 100644
index 0000000..fda562d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h
@@ -0,0 +1,277 @@
+
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_3
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+*	- 4 banks
+*	- Masked writes (There are no masked reads)
+*	- Bypass mode
+*	- Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* 

    
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+*       ms   04/05/17 Added tabspace for return statements in functions of
+*                     gpiops examples for proper documentation while
+*                     generating doxygen.
+* 3.3   ms   04/17/17 Added notes about gpio input and output pin description
+*                     for zcu102 and zc702 boards in polled and interrupt
+*                     example, configured Interrupt pin to input pin for
+*                     proper functioning of interrupt example.
+* 
    
+*
+******************************************************************************/
+#ifndef XGPIOPS_H		/* prevent circular inclusions */
+#define XGPIOPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ *  @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4			0x04U  /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5			0x05U  /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP		0x06U  /**< Max banks in a
+										*	Zynq Ultrascale+ MP GPIO device
+										*/
+#define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP	(u32)174 /**< Max pins in the
+						  *	Zynq Ultrascale+ MP GPIO device
+					      * 0 - 25,  Bank 0
+					      * 26 - 51, Bank 1
+					      *	52 - 77, Bank 2
+					      *	78 - 109, Bank 3
+					      *	110 - 141, Bank 4
+					      *	142 - 173, Bank 5
+					      */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /**< Max pins in the Zynq GPIO device
+					      * 0 - 31,  Bank 0
+					      * 32 - 53, Bank 1
+					      *	54 - 85, Bank 2
+					      *	86 - 117, Bank 3
+					      */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions for a GPIO bank. It is
+ *		passed back to the upper layer when the callback is invoked. Its
+ *		type is not important to the driver component, so it is a void
+ *		pointer.
+ * @param	Bank is the bank for which the interrupt status has changed.
+ * @param	Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XGpioPs_Config GpioConfig;	/**< Device configuration */
+	u32 IsReady;			/**< Device is initialized and ready */
+	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
+	void *CallBackRef; 		/**< Callback ref for bank handlers */
+	u32 Platform;			/**< Platform data */
+	u32 MaxPinNum;			/**< Max pins in the GPIO device */
+	u8 MaxBanks;			/**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+			   u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber,	u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+			     XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
new file mode 100644
index 0000000..76e6947
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_GPIO_0_DEVICE_ID,
+		XPAR_PS7_GPIO_0_BASEADDR
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
new file mode 100644
index 0000000..8961c42
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains low level GPIO functions.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk   08/22/13 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param	Base address of GPIO module
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+	u32 BankCount;
+	u32 Platform,MaxBanks;
+
+	Platform = XGetPlatform_Info();
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		MaxBanks = (u32)6;
+	} else {
+		MaxBanks = (u32)4;
+	}
+	/* Write reset values to all mask data registers */
+	for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+	}
+	/* Write reset values to all output data registers */
+	for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_OFFSET), 0x0U);
+	}
+
+	/* Reset all registers of all GPIO banks */
+	for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTMASK_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTDIS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTSTS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTPOL_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTANY_OFFSET), 0x0U);
+	}
+
+	/* Bank 0 Int type */
+	XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+			XGPIOPS_INTTYPE_BANK0_RESET);
+	/* Bank 1 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK1_RESET);
+	/* Bank 2 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK2_RESET);
+	/* Bank 3 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK3_RESET);
+
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/* Bank 4 Int type */
+		XGpioPs_WriteReg(BaseAddress,
+				(((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+				XGPIOPS_INTTYPE_BANK4_RESET);
+		/* Bank 5 Int type */
+		XGpioPs_WriteReg(BaseAddress,
+				(((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+				XGPIOPS_INTTYPE_BANK5_RESET);
+	}
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
new file mode 100644
index 0000000..ff01906
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h
@@ -0,0 +1,164 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+* 
    
+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
+#define XGPIOPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ *  @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ *  @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET  0x00000040U  /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ *  @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET  0x03FFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU  /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU  /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET  0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET  0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
new file mode 100644
index 0000000..a8b0a56
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c
@@ -0,0 +1,731 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to API's. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the bit mask of the pins for which interrupts are to
+*		be enabled. Bit positions of 1 will be enabled. Bit positions
+*		of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be enabled.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the bit mask of the pins for which interrupts are
+*		to be disabled. Bit positions of 1 will be disabled. Bit
+*		positions of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be disabled.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg =  ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+*		indicate that the interrupt for that pin is enabled, bit
+*		positions with 0 indicate that the interrupt for that pin is
+*		disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+	u32 IntrMask;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+	return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+*		- TRUE if the interrupt is enabled.
+*		- FALSE if the interrupt is disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	The value read from Interrupt Status Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+*		- TRUE if the interrupt has occurred.
+*		- FALSE if the interrupt has not occurred.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the mask of the interrupts to be cleared. Bit positions
+*		of 1 will be cleared. Bit positions of 0 will not change the
+*		previous interrupt status.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	/* Clear the currently pending interrupts. */
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt status is to be
+*		cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	/* Clear the specified pending interrupts. */
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	IntrReg &= ((u32)1 << PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	IntrType is the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity is the 32 bit mask of the interrupt polarity.
+*		0 means Active Low or Falling Edge and 1 means Active High or
+*		Rising Edge.
+* @param	IntrOnAny is the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means  trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		This function is used for setting the interrupt related
+*		properties of all the pins in the specified bank. The previous
+*		state of the pins is not maintained.
+*		To change the Interrupt properties of a single GPIO pin, use the
+*		function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	IntrType returns the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity returns the 32 bit mask of the interrupt
+*		polarity. 0 means Active Low or Falling Edge and 1 means
+*		Active High or Rising Edge.
+* @param	IntrOnAny returns the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTTYPE_OFFSET);
+
+	*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					 XGPIOPS_INTPOL_OFFSET);
+
+	*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be set.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+*		defined in xgpiops.h to specify the IRQ type.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+	u32 IntrTypeReg;
+	u32 IntrPolReg;
+	u32 IntrOnAnyReg;
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_INTTYPE_OFFSET);
+
+	IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTPOL_OFFSET);
+
+	IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					XGPIOPS_INTANY_OFFSET);
+
+	switch (IrqType) {
+		case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		default:
+			/**< Default statement is added for MISRA C compliance. */
+			break;
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be obtained.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+*		returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u32 IntrType;
+	u32 IntrPol;
+	u32 IntrOnAny;
+	u8 Bank;
+	u8 PinNumber;
+	u8 IrqType;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+	if (IntrType == ((u32)1 << PinNumber)) {
+
+		IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+		if (IntrOnAny == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+		} else if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+		}
+	} else {
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+		if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+		}
+	}
+
+	return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the  XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+*
+* @return	None.
+*
+* @note		The handler is called within interrupt context, so it should do
+*		its work quickly and queue potentially time-consuming work to a
+*		task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+				 XGpioPs_Handler FuncPointer)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPointer != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPointer;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return	None.
+*
+* @note		This function does not save and restore the processor context
+*		such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+	u8 Bank;
+	u32 IntrStatus;
+	u32 IntrEnabled;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+		IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+		if (IntrStatus != (u32)0) {
+			IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+							      Bank);
+			XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
+							(IntrStatus & IntrEnabled));
+			InstancePtr->Handler(InstancePtr->
+					     CallBackRef, Bank,
+					     (IntrStatus & IntrEnabled));
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	Bank is the GPIO Bank in which an interrupt occurred.
+* @param	Status is the Interrupt status of the GPIO bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
+{
+	(void) CallBackRef;
+	(void) Bank;
+	(void) Status;
+
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
new file mode 100644
index 0000000..378524c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed.
+* 		- XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrEnabled;
+	u32 CurrentIntrType = 0U;
+	u32 CurrentIntrPolarity = 0U;
+	u32 CurrentIntrOnAny = 0U;
+	u32 IntrType = 0U;
+	u32 IntrPolarity = 0U;
+	u32 IntrOnAny = 0U;
+	u32 IntrTestValue = 0x22U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable the Interrupts for Bank 0 . */
+	IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+	XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	/*
+	 * Get the Current Interrupt properties for Bank 0.
+	 * Set them to a known value, read it back and compare.
+	 */
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+			     &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+			     IntrTestValue, IntrTestValue);
+
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+			     &IntrPolarity, &IntrOnAny);
+
+	if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+	    (IntrOnAny != IntrTestValue)) {
+
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Restore the contents of all the interrupt registers modified in this
+	 * test.
+	 */
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+			     CurrentIntrPolarity, CurrentIntrOnAny);
+
+	XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
new file mode 100644
index 0000000..4cc0c39
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_3
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+	XGpioPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+		if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XGpioPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
new file mode 100644
index 0000000..9546b54
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.c
@@ -0,0 +1,333 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Contains implementation of required functions for the XIicPs driver.
+* See xiicps.h for detailed description of the device and driver.
+*
+* 
     MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.00a sdm     09/21/11 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* 2.1   hk      04/25/14 Explicitly reset CR and clear FIFO in Abort function
+*                        and state the same in the comments. CR# 784254.
+*                        Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk		10/07/14 Repeated start feature removed.
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+* 						 in XIicPs_Reset.
+*				12/06/14 Implemented Repeated start feature.
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn		05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef, u32 StatusEvent);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XIicPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Device is disabled
+*   - Slave mode
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific IIC device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return	The return value is XST_SUCCESS if successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
+				  u32 EffectiveAddr)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->StatusHandler = StubHandler;
+	InstancePtr->CallBackRef = NULL;
+
+	InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the IIC device to get it into its initial state. It is expected
+	 * that device configuration will take place after this initialization
+	 * is done, but before the device is started.
+	 */
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	/* Initialize repeated start flag to 0 */
+	InstancePtr->IsRepeatedStart = 0;
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Check whether the I2C bus is busy
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+* 		- TRUE if the bus is busy.
+*		- FALSE if the bus is not busy.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	s32	Status;
+
+	StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_SR_OFFSET);
+	if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
+		Status = (s32)TRUE;
+	}else {
+		Status = (s32)FALSE;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference.
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef, u32 StatusEvent)
+{
+	(void) ((void *)CallBackRef);
+	(void) StatusEvent;
+	Xil_AssertVoidAlways();
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
+* cleared.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Abort(XIicPs *InstancePtr)
+{
+	u32 IntrMaskReg;
+	u32 IntrStatusReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enter a critical section, so disable the interrupts while we clear
+	 * the FIFO and the status register.
+	 */
+	IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_IMR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+
+	/*
+	 * Reset the settings in config register and clear the FIFOs.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK);
+
+	/*
+	 * Read, then write the interrupt status to make sure there are no
+	 * pending interrupts.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Restore the interrupt state.
+	 */
+	IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IER_OFFSET, IntrMaskReg);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the IIC device. Reset must only be called after the driver has been
+* initialized. The configuration of the device after reset is the same as its
+* configuration after initialization.  Any data transfer that is in progress is
+* aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and reenabling interrupts for the IIC device after the reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Reset(XIicPs *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress.
+	 */
+	XIicPs_Abort(InstancePtr);
+
+	/*
+	 * Reset any values so the software state matches the hardware device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
+			  XIICPS_IXR_ALL_INTR_MASK);
+
+}
+/*****************************************************************************/
+/**
+* Put more data into the transmit FIFO, number of bytes is ether expected
+* number of bytes for this transfer or available space in FIFO, which ever
+* is less.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes left for this instance.
+*
+* @note		This is function is shared by master and slave.
+*
+******************************************************************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr)
+{
+	u8 AvailBytes;
+	s32 LoopCnt;
+	s32 NumBytesToSend;
+
+	/*
+	 * Determine number of bytes to write to FIFO.
+	 */
+	AvailBytes = (u8)XIICPS_FIFO_DEPTH -
+		(u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_TRANS_SIZE_OFFSET);
+
+	if (InstancePtr->SendByteCount > (s32)AvailBytes) {
+		NumBytesToSend = (s32)AvailBytes;
+	} else {
+		NumBytesToSend = InstancePtr->SendByteCount;
+	}
+
+	/*
+	 * Fill FIFO with amount determined above.
+	 */
+	for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
+		XIicPs_SendByte(InstancePtr);
+	}
+
+	return InstancePtr->SendByteCount;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
new file mode 100644
index 0000000..d3713de
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps.h
@@ -0,0 +1,425 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+* @addtogroup iicps_v3_7
+* @{
+* @details
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface.  The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* Initialization & Configuration
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*    - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+*      the static configuration structure defined in xiicps_g.c. This is
+*      setup by the tools. For some operating systems the config structure
+*      will be initialized by the software and this call is not needed.
+*
+*   - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a
+*     system with address translation, the provided virtual memory base
+*     address replaces the physical address in the configuration
+*     structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* Multiple Slaves
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* Addressing
+*
+* The IIC hardware can use 7 or 10 bit addresses.  The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* FIFO Size 
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* Data Rates
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* Polled Mode Operation
+*
+* This driver supports polled mode transfers.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* Bus Busy
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+*Repeated Start
+*
+* The I2C controller does not indicate completion of a receive transfer if HOLD
+* bit is set. Due to this errata, repeated start cannot be used if a receive
+* transfer is followed by any other transfer.
+*
+* 
     MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                    read mode and clear transfer size register.
+*                    Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	10/07/14 Repeated start feature deleted.
+* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
+* 					 in XIicPs_Reset.
+* 			12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* 3.7   ask  04/17/18 Updated the Eeprom scanning mechanism
+*                     as per the other examples (CR#997545)
+*
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIICPS_H       /* prevent circular inclusions */
+#define XIICPS_H       /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC.  Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION	0x01U  /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION	0x02U  /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION		0x04U  /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION		0x08U  /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver.  These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND	0x0001U  /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV	0x0002U  /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT		0x0004U  /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR			0x0008U  /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST		0x0010U  /**< Arbitration lost */
+#define XIICPS_EVENT_NACK			0x0020U  /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY		0x0040U  /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR			0x0080U  /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR			0x0100U  /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF			0x0200U  /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE		1  /**< Transfer direction is sending */
+#define RECVING_ROLE		0  /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE	(u32)(255U - 3U)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		not important to the driver, so it is a void pointer.
+* @param	StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;     /**< Unique ID  of device */
+	u32 BaseAddress;  /**< Base address of the device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIicPs_Config Config;	/* Configuration structure */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Options set in the device */
+
+	u8 *SendBufferPtr;	/* Pointer to send buffer */
+	u8 *RecvBufferPtr;	/* Pointer to recv buffer */
+	s32 SendByteCount;	/* Number of bytes still expected to send */
+	s32 RecvByteCount;	/* Number of bytes still expected to receive */
+	s32 CurrByteCount;	/* No. of bytes expected in current transfer */
+
+	s32 UpdateTxSize;	/* If tx size register has to be updated */
+	s32 IsSend;		/* Whether master is sending or receiving */
+	s32 IsRepeatedStart;	/* Indicates if user set repeated start */
+
+	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr)					\
+{									\
+	u8 Data;							\
+	Data = *((InstancePtr)->SendBufferPtr);				\
+	 XIicPs_Out32((InstancePtr)->Config.BaseAddress			\
+			 + (u32)(XIICPS_DATA_OFFSET), 			\
+					(u32)(Data));			\
+	(InstancePtr)->SendBufferPtr += 1;				\
+	(InstancePtr)->SendByteCount -= 1;\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr)					\
+{									\
+	u8 *Data, Value;						\
+	Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress	\
+		  + (u32)XIICPS_DATA_OFFSET));  			\
+	Data = &Value;							\
+	*(InstancePtr)->RecvBufferPtr = *Data;				\
+	(InstancePtr)->RecvBufferPtr += 1;				\
+	 (InstancePtr)->RecvByteCount --; 				\
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
+				  u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+s32 XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
new file mode 100644
index 0000000..64ac648
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xiicps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_I2C_0_DEVICE_ID,
+		XPAR_PS7_I2C_0_BASEADDR,
+		XPAR_PS7_I2C_0_I2C_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
new file mode 100644
index 0000000..ce81d92
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Contains implementation of required functions for providing the reset sequence
+* to the i2c interface
+*
+* 
     MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.04a kpc     11/07/13 First release
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given I2c interface by
+* configuring the appropriate control bits in the I2c specifc registers
+* the i2cps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status
+*	Clear FIFO's and disable hold bit
+*	Clear the line status
+*	Update relevant config registers with reset values
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* I2c controller
+******************************************************************************/
+void XIicPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+
+	/* Disable all the interrupts */
+	XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+	/* Clear the interrupt status */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
+	/* Clear the hold bit,master enable bit and ack bit */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
+	RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
+	/* Clear the fifos */
+	RegVal |= XIICPS_CR_CLR_FIFO_MASK;
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
+	/* Clear the timeout register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	/* Clear the transfer size register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+	/* Clear the status register */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
+	/* Update the configuraqtion register with reset value */
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
new file mode 100644
index 0000000..e9d63ec
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_hw.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+* @addtogroup iicps_v3_7
+* @{
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype.
+* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 
    
+*
+******************************************************************************/
+#ifndef XIICPS_HW_H		/* prevent circular inclusions */
+#define XIICPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET			0x00U  /**< 32-bit Control */
+#define XIICPS_SR_OFFSET			0x04U  /**< Status */
+#define XIICPS_ADDR_OFFSET			0x08U  /**< IIC Address */
+#define XIICPS_DATA_OFFSET			0x0CU  /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET			0x10U  /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET	0x14U  /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET		0x18U  /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET		0x1CU  /**< Time Out */
+#define XIICPS_IMR_OFFSET			0x20U  /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET			0x24U  /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET			0x28U  /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK	0x0000C000U /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT			14U /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX				 4U /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK	0x00003F00U /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT			 8U /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK	0x00000040U /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK	0x00000020U /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK		0x00000010U /**<  Hold bus 1=Hold scl,
+												0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK	0x00000008U /**< Enable TX of ACK when
+												Master receiver*/
+#define XIICPS_CR_NEA_MASK		0x00000004U /**< Addressing Mode 1=7 bit,
+												0=10 bit */
+#define XIICPS_CR_MS_MASK		0x00000002U /**< Master mode bit 1=Master,
+												0=Slave */
+#define XIICPS_CR_RD_WR_MASK	0x00000001U /**< Read or Write Master
+												transfer  0=Transmitter,
+												1=Receiver*/
+#define XIICPS_CR_RESET_VALUE			 0U /**< Reset value of the Control
+												register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK		0x00000100U  /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK	0x00000080U  /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK		0x00000040U  /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK		0x00000020U  /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK		0x00000008U  /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK	0x000003FF  /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK	0x000000FF  /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * IIC Interrupt Status Register
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists.  Other flags are
+ *   edge triggered, which means they are set one the interrupt condition occurs
+ *   then remain set until they are cleared by software.
+ *   The interrupts are cleared by writing a one to the interrupt bit position
+ *   in the Interrupt Status Register. Read/Write.
+ *
+ * IIC Interrupt Enable Register
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register.  Write only.
+ *
+ * IIC Interrupt Disable Register 
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * IIC Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK  0x00000200U	 /**< Arbitration Lost Interrupt
+													mask */
+#define XIICPS_IXR_RX_UNF_MASK    0x00000080U	 /**< FIFO Recieve Underflow
+													Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK    0x00000040U	 /**< Transmit Overflow
+													Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK    0x00000020U	 /**< Receive Overflow Interrupt
+													mask */
+#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U	 /**< Monitored Slave Ready
+													Interrupt mask */
+#define XIICPS_IXR_TO_MASK        0x00000008U	 /**< Transfer Time Out
+													Interrupt mask */
+#define XIICPS_IXR_NACK_MASK      0x00000004U	 /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK      0x00000002U	 /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK      0x00000001U	 /**< Transfer Complete
+													Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU	 /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK  0x000002FFU	 /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+*   - Master transmitter mode: number of data bytes still not transmitted minus
+*     one
+*   - Master receiver mode: number of data bytes that are still expected to be
+*     received
+*   - Slave transmitter mode: number of bytes remaining in the FIFO after the
+*     master terminates the transfer
+*   - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK  0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH          16	  /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH     14    /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK    0x0000000F  /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK    0x000000FFU    /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE   0x000000FFU    /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+	XIicPs_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	Current bit mask that represents currently enabled interrupts.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+	XIicPs_ReadReg((BaseAddress),  XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be enabled.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be disabled.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		(IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddress);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
new file mode 100644
index 0000000..6dccff4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_intr.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_intr.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Contains functions of the XIicPs driver for interrupt-driven transfers.
+* See xiicps.h for a detailed description of the device and driver.
+*
+* 
     MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 3.00	sk		01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function, the status handler, which the
+* driver calls when it encounters conditions that should be reported to the
+* higher layer software. The handler executes in an interrupt context, so
+* the amount of processing should be minimized
+*
+* Refer to the xiicps.h file for a list of the Callback events. The events are
+* defined to start with XIICPS_EVENT_*.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FunctionPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should finish its
+* work quickly.
+*
+******************************************************************************/
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FunctionPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FunctionPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
new file mode 100644
index 0000000..5554209
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_master.c
@@ -0,0 +1,999 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_master.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Handles master mode transfers.
+*
+* 
     MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---  -------- ---------------------------------------------
+* 1.00a jz   01/30/10 First release
+* 1.00a sdm  09/21/11 Updated the XIicPs_SetupMaster to not check for
+*		      Bus Busy condition when the Hold Bit is set.
+* 1.01a sg   03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*		      check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 2.0   hk   03/07/14 Added check for error status in the while loop that
+*                     checks for completion. CR# 762244, 764875.
+* 2.1   hk   04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                     Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk   08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                     read mode and clear transfer size register.
+*                     Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	 10/06/14 Fill transmit fifo before address register when sending.
+* 					  Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
+* 					  Repeated start feature removed.
+* 3.0	sk	 12/06/14 Implemented Repeated start feature.
+*			 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			 02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+* 3.6   ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register
+* 		     before slave address. Fix for CR996440.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
+static void MasterSendData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven send in master mode.
+*
+* It tries to send the first FIFO-full of data, then lets the interrupt
+* handler to handle the rest of the data if there is any.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+ ****************************************************************************/
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+	u32 Platform = XGetPlatform_Info();
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->IsSend = 1;
+
+	/*
+	 * Set repeated start if sending more than FIFO of data.
+	 */
+	if (((InstancePtr->IsRepeatedStart) != 0)||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+				(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Setup as a master sending role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+	/*
+	 * Do the address transfer to notify the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	/* Clear the Hold bit in ZYNQ if receive byte count is less than
+	 * the FIFO depth to get the completion interrupt properly.
+	 */
+	if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) &
+				(u32)(~XIICPS_CR_HOLD_MASK));
+	}
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven receive in master mode.
+*
+* It sets the transfer size register so the slave can send data to us.
+* The rest of the work is managed by interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note		This receive routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->IsSend = 0;
+
+	if ((ByteCount > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Initialize for a master receiving role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+	/*
+	 * Setup the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		InstancePtr->UpdateTxSize = 1;
+	}else {
+		InstancePtr->CurrByteCount = ByteCount;
+		XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
+			 (u32)ByteCount);
+		InstancePtr->UpdateTxSize = 0;
+	}
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+	/*
+	 * Do the address transfer to signal the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode send in master mode.
+*
+* It sends data to the FIFO and waits for the slave to pick them up.
+* If slave fails to remove data from FIFO, the send fails with
+* time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+		 s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	u32 Intrs;
+	_Bool Value;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	if (((InstancePtr->IsRepeatedStart) != 0) ||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
+		(u32)XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Transmit first FIFO full of data.
+	 */
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Continue sending as long as there is more data and
+	 * there are no errors.
+	 */
+	Value = ((InstancePtr->SendByteCount > (s32)0) &&
+		((IntrStatusReg & Intrs) == (u32)0U));
+	while (Value != FALSE) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * Wait until transmit FIFO is empty.
+		 */
+		if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+				((IntrStatusReg & Intrs) == (u32)0U));
+			continue;
+		}
+
+		/*
+		 * Send more data out through transmit FIFO.
+		 */
+		(void)TransmitFifoFill(InstancePtr);
+		Value = ((InstancePtr->SendByteCount > (s32)0) &&
+			((IntrStatusReg & Intrs) == (u32)0U));
+	}
+
+	/*
+	 * Check for completion of transfer.
+	 */
+	while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		/*
+		 * If there is an error, tell the caller.
+		 */
+		if ((IntrStatusReg & Intrs) != 0U) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode receive in master mode.
+*
+* It repeatedly sets the transfer size register so the slave can
+* send data to us. It polls the data register for data to come in.
+* If slave fails to send us data, it fails with time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+				s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 Intrs;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Result;
+	s32 IsHold;
+	s32 UpdateTxSize = 0;
+	s32 ByteCountVar = ByteCount;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCountVar;
+
+	Platform = XGetPlatform_Info();
+
+	if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+		IsHold = 1;
+	} else {
+		IsHold = 0;
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+
+	/*
+	 * Set up the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 ByteCountVar);
+	}
+
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
+			(u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
+	/*
+	 * Poll the interrupt status register to find the errors.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	while ((InstancePtr->RecvByteCount > 0) &&
+			((IntrStatusReg & Intrs) == 0U)) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	    while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
+		    if (((InstancePtr->RecvByteCount <
+			    XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
+			    ((!InstancePtr->IsRepeatedStart) != 0) &&
+			    (UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+		    ByteCountVar --;
+
+			if (Platform == (u32)XPLAT_ZYNQ) {
+			    if ((UpdateTxSize != 0) &&
+				    (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
+				    break;
+				}
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		}
+		if (Platform == (u32)XPLAT_ZYNQ) {
+			if ((UpdateTxSize != 0) &&
+				(ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) {
+			    /*  wait while fifo is full */
+			    while (XIicPs_ReadReg(BaseAddr,
+				    XIICPS_TRANS_SIZE_OFFSET) !=
+				    (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+		    if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		}
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+	if ((IntrStatusReg & Intrs) != 0x0U) {
+		Result = (s32)XST_FAILURE;
+	}
+	else {
+		Result =  (s32)XST_SUCCESS;
+	}
+
+	return Result;
+}
+
+/*****************************************************************************/
+/**
+* This function enables the slave monitor mode.
+*
+* It enables slave monitor in the control register and enables
+* slave ready interrupt. It then does an address transfer to slave.
+* Interrupt handler will signal the caller if slave responds to
+* the address transfer.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we want to contact.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 BaseAddr;
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/* Clear transfer size register */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+
+	/*
+	 * Enable slave monitor mode in control register.
+	 */
+	ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
+	ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
+			(u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
+	ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Set up interrupt flag for slave monitor interrupt.
+	 * Dont enable NACK.
+	 */
+	XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
+
+	/*
+	 * Initialize the slave monitor register.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
+
+	/*
+	 * Set the slave address to start the slave address transmission.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function disables slave monitor mode.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
+{
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Clear slave monitor control bit.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+		XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+			& (~XIICPS_CR_SLVMON_MASK));
+
+	/*
+	 * wait for slv monitor control bit to be clear
+	 */
+	while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+				& XIICPS_CR_SLVMON_MASK);
+	/*
+	 * Clear interrupt flag for slave monitor interrupt.
+	 */
+	XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the master mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper handling.
+*
+* 
    +* The interrupts that are handled are:
+* - DATA
+*	This case is handled only for master receive data.
+*	The master has to request for more data (if there is more data to
+*	receive) and read the data from the FIFO .
+*
+* - COMP
+*	If the Master is transmitting data and there is more data to be
+*	sent then the data is written to the FIFO. If there is no more data to
+*	be transmitted then a completion event is signalled to the upper layer
+*	by calling the callback handler.
+*
+*	If the Master is receiving data then the data is read from the FIFO and
+*	the Master has to request for more data (if there is more data to
+*	receive). If all the data has been received then a completion event
+*	is signalled to the upper layer by calling the callback handler.
+*	It is an error if the amount of received data is more than expected.
+*
+* - NAK and SLAVE_RDY
+*	This is signalled to the upper layer by calling the callback handler.
+*
+* - All Other interrupts
+*	These interrupts are marked as error. This is signalled to the upper
+*	layer by calling the callback handler.
+*
+* 
    
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 StatusEvent = 0U;
+	u32 BaseAddr;
+	u16 SlaveAddr;
+	s32 ByteCnt;
+	s32 IsHold;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	Platform = XGetPlatform_Info();
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					 (u32)XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are
+	 * missed while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
+
+	ByteCnt = InstancePtr->CurrByteCount;
+
+	IsHold = 0;
+	if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
+		IsHold = 1;
+	}
+
+	/*
+	 * Send
+	 */
+	if (((InstancePtr->IsSend) != 0) &&
+		((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
+		if (InstancePtr->SendByteCount > 0) {
+			MasterSendData(InstancePtr);
+		} else {
+			StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+		}
+	}
+
+
+	/*
+	 * Receive
+	 */
+	if (((!(InstancePtr->IsSend))!= 0) &&
+		((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
+		(0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
+
+		while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
+				XIICPS_SR_RXDV_MASK) != 0U) {
+			if (((InstancePtr->RecvByteCount <
+				XIICPS_DATA_INTR_DEPTH)!= 0U)  && (IsHold != 0)  &&
+				((!InstancePtr->IsRepeatedStart)!= 0) &&
+				(InstancePtr->UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+			ByteCnt--;
+
+			if (Platform == (u32)XPLAT_ZYNQ) {
+			    if ((InstancePtr->UpdateTxSize != 0) &&
+				    (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
+				    break;
+				}
+			}
+		}
+
+		if (Platform == (u32)XPLAT_ZYNQ) {
+			if ((InstancePtr->UpdateTxSize != 0) &&
+				(ByteCnt == (XIICPS_FIFO_DEPTH + 1))) {
+				/* wait while fifo is full */
+				while (XIicPs_ReadReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET) !=
+					(u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+			if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					(s32)XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+				XIicPs_EnableInterrupts(BaseAddr,
+					(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+					(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+					(u32)XIICPS_IXR_ARB_LOST_MASK);
+			}
+		}
+		InstancePtr->CurrByteCount = ByteCnt;
+	}
+
+	if (((!(InstancePtr->IsSend)) != 0) &&
+		(0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
+		/*
+		 * If all done, tell the application.
+		 */
+		if (InstancePtr->RecvByteCount == 0){
+			if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+		}
+	}
+
+
+	/*
+	 * Slave ready interrupt, it is only meaningful for master mode.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
+		StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
+	}
+
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * Arbitration lost interrupt
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
+		StatusEvent |= XIICPS_EVENT_ARB_LOST;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
+			XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
+			XIICPS_IXR_RX_OVR_MASK))) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (StatusEvent != 0U) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+
+}
+
+/*****************************************************************************/
+/*
+* This function prepares a device to transfers as a master.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @param	Role specifies whether the device is sending or receiving.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if bus is busy.
+*
+* @note		Interrupts are always disabled, device which needs to use
+*		interrupts needs to setup interrupts after this call.
+*
+****************************************************************************/
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
+
+
+	/*
+	 * Only check if bus is busy when repeated start option is not set.
+	 */
+	if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
+		if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
+			(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
+
+	if (Role == RECVING_ROLE) {
+		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
+	}else {
+		ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+	}
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+* This function handles continuation of sending data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+static void MasterSendData(XIicPs *InstancePtr)
+{
+	(void)TransmitFifoFill(InstancePtr);
+
+	/*
+	 * Clear hold bit if done, so stop can be sent out.
+	 */
+	if (InstancePtr->SendByteCount == 0) {
+
+		/*
+		 * If user has enabled repeated start as an option,
+		 * do not disable it.
+		 */
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+
+			XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
+		}
+	}
+
+	return;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
new file mode 100644
index 0000000..4ef69a1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_options.c
@@ -0,0 +1,497 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_options.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Contains functions for the configuration of the XIccPs driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error.
+*			 This is a fix for CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk	10/07/14 Repeated start feature removed.
+* 3.0	sk	12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+		u32 Option;
+		u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+		{XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
+		{XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
+};
+
+#define XIICPS_NUM_OPTIONS      (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the IIC device driver. The options control
+* how the device behaves relative to the IIC bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is requested, set the flag.
+	 * The hold bit in CR will be written by driver when the next transfer
+	 * is initiated.
+	 */
+	if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) {
+		InstancePtr->IsRepeatedStart = 1;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table, turning the option on.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so turning it on means
+			 * turning 7-bit option off.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			} else {
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+	/*
+	 * Now write to the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears the options for the IIC device driver. The options
+* control how the device behaves relative to the IIC bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be cleared. This is a
+*		bit mask where a 1 means to turn the option off. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is cleared, set the flag.
+	 * The hold bit in CR will be cleared by driver when the
+	 * following transfer ends.
+	 */
+	if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
+		InstancePtr->IsRepeatedStart = 0;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table and clear the specified options.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so clearing it means turning
+			 * 7-bit option on.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			} else {
+
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the IIC device. The options control how
+* the device behaves relative to the IIC bus.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	32 bit mask of the options, where a 1 means the option is on,
+*		and a 0 means to the option is off. One or more bit values may
+*		be contained in the mask. See the bit definitions named
+* 		XIICPS_*_OPTION in the file xiicps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetOptions(XIicPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 ControlReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read control register to find which options are currently set.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to determine which options are set.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+		if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
+			OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
+		}
+	}
+
+	if (InstancePtr->IsRepeatedStart != 0 ) {
+		OptionsFlag |= XIICPS_REP_START_OPTION;
+	}
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+* See the hardware data sheet for a full explanation of setting the serial
+* clock rate.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	FsclHz is the clock frequency in Hz. The two most common clock
+*		rates are 100KHz and 400KHz.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*		- XST_FAILURE if the Fscl frequency can not be set.
+*
+* @note		The clock can not be faster than the input clock divide by 22.
+*
+******************************************************************************/
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
+{
+	u32 Div_a;
+	u32 Div_b;
+	u32 ActualFscl;
+	u32 Temp;
+	u32 TempLimit;
+	u32 LastError;
+	u32 BestError;
+	u32 CurrentError;
+	u32 ControlReg;
+	u32 CalcDivA;
+	u32 CalcDivB;
+	u32 BestDivA;
+	u32 BestDivB;
+	u32 FsclHzVar = FsclHz;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FsclHzVar > 0U);
+
+	if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
+					XIICPS_TRANS_SIZE_OFFSET)) {
+		return (s32)XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
+	 */
+	Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
+
+	/*
+	 * If the answer is negative or 0, the Fscl input is out of range.
+	 */
+	if ((u32)(0U) == Temp) {
+		return (s32)XST_FAILURE;
+	}
+
+	/*
+	 * If frequency 400KHz is selected, 384.6KHz should be set.
+	 * If frequency 100KHz is selected, 90KHz should be set.
+	 * This is due to a hardware limitation.
+	 */
+	if(FsclHzVar > (u32)384600U) {
+		FsclHzVar = (u32)384600U;
+	}
+
+	if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) {
+		FsclHzVar = (u32)90000U;
+	}
+
+	/*
+	 * TempLimit helps in iterating over the consecutive value of Temp to
+	 * find the closest clock rate achievable with divisors.
+	 * Iterate over the next value only if fractional part is involved.
+	 */
+	TempLimit = (((InstancePtr->Config.InputClockHz) %
+			((u32)22 * FsclHzVar)) != 	(u32)0x0U) ?
+						Temp + (u32)1U : Temp;
+	BestError = FsclHzVar;
+
+	BestDivA = 0U;
+	BestDivB = 0U;
+	for ( ; Temp <= TempLimit ; Temp++)
+	{
+		LastError = FsclHzVar;
+		CalcDivA = 0U;
+		CalcDivB = 0U;
+
+		for (Div_b = 0U; Div_b < 64U; Div_b++) {
+
+			Div_a = Temp / (Div_b + 1U);
+
+			if (Div_a != 0U){
+				Div_a = Div_a - (u32)1U;
+			}
+			if (Div_a > 3U){
+				continue;
+			}
+			ActualFscl = (InstancePtr->Config.InputClockHz) /
+						(22U * (Div_a + 1U) * (Div_b + 1U));
+
+			if (ActualFscl > FsclHzVar){
+				CurrentError = (ActualFscl - FsclHzVar);}
+			else{
+				CurrentError = (FsclHzVar - ActualFscl);}
+
+			if (LastError > CurrentError) {
+				CalcDivA = Div_a;
+				CalcDivB = Div_b;
+				LastError = CurrentError;
+			}
+		}
+
+		/*
+		 * Used to capture the best divisors.
+		 */
+		if (LastError < BestError) {
+			BestError = LastError;
+			BestDivA = CalcDivA;
+			BestDivB = CalcDivB;
+		}
+	}
+
+
+	/*
+	 * Read the control register and mask the Divisors.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  (u32)XIICPS_CR_OFFSET);
+	ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
+	ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
+		(BestDivB << XIICPS_CR_DIV_B_SHIFT);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	The value of the IIC clock to the nearest Hz based on the
+*		control register settings. The actual value may not be exact to
+*		to integer math rounding errors.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetSClk(XIicPs *InstancePtr)
+{
+	u32 ControlReg;
+	u32 ActualFscl;
+	u32 Div_a;
+	u32 Div_b;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XIICPS_CR_OFFSET);
+
+	Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
+	Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
+
+	ActualFscl = (InstancePtr->Config.InputClockHz) /
+		(22U * (Div_a + 1U) * (Div_b + 1U));
+
+	return ActualFscl;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
new file mode 100644
index 0000000..3e68cb6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_selftest.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* This component contains the implementation of selftest functions for the
+* XIicPs driver component.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.00a sdm    09/22/11 Removed unused code
+* 3.0	sk	   11/03/14 Removed TimeOut Register value check
+*			   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+#define REG_TEST_VALUE    0x00000005U
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SelfTest(XIicPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the IIC registers should be in their default state right now.
+	 */
+	if ((XIICPS_CR_RESET_VALUE !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_CR_OFFSET)) ||
+		(XIICPS_IXR_ALL_INTR_MASK !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_IMR_OFFSET))) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Write, Read then write a register
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
+
+	if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XIICPS_SLV_PAUSE_OFFSET)) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, 0U);
+
+	XIicPs_Reset(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
new file mode 100644
index 0000000..a5724c2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_sinit.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_sinit.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* The implementation of the XIicPs component's static initialization
+* functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 3.00	sk	   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*		device ID was not found. See xiicps.h for the definition of
+*		XIicPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
+{
+	XIicPs_Config *CfgPtr = NULL;
+	s32 Index;
+
+	for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
+		if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIicPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XIicPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
new file mode 100644
index 0000000..fb89192
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/iicps_v3_7/src/xiicps_slave.c
@@ -0,0 +1,595 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xiicps_slave.c
+* @addtogroup iicps_v3_7
+* @{
+*
+* Handles slave transfers
+*
+* 
     MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --  -------- ---------------------------------------------
+* 1.00a jz  01/30/10 First release
+* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
+* 3.00	sk	01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 3.3   kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 SlaveRecvData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function sets up the device to be a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note
+*	Interrupt is always enabled no matter the tranfer is interrupt-
+*	driven or polled mode. Whether device will be interrupted or not
+*	depends on whether the device is connected to an interrupt
+*	controller and interrupt for the device is enabled.
+*
+****************************************************************************/
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
+	ControlReg |= (u32)XIICPS_CR_NEA_MASK;
+	ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven send. It set the repeated
+* start for the device is the tranfer size is larger than FIFO depth.
+* Data processing for the send is initiated by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(BaseAddr,
+			(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+			(u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
+			(u32)XIICPS_IXR_TX_OVR_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven receive.
+* Data processing for the receive is handled by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return	None.
+*
+* @note		This routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
+		(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+* This function sends  a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if master sends us data or master terminates the
+*		transfer before all data has sent out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Tmp;
+	s32 BytesToSend;
+	s32 Error = 0;
+	s32 Status = (s32)XST_SUCCESS;
+	_Bool Value;
+	_Bool Result;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	/*
+	 * Use RXRW bit in status register to wait master to start a read.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+			(Error == 0));
+	while (Result != FALSE) {
+
+		/*
+		 * If master tries to send us data, it is an error.
+		 */
+		if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
+			Error = 1;
+		}
+
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) &&
+				(Error == 0));
+	}
+
+	if (Error != 0) {
+		Status = (s32)XST_FAILURE;
+	} else {
+
+		/*
+		 * Clear the interrupt status register.
+		 */
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+		/*
+		 * Send data as long as there is more data to send and
+		 * there are no errors.
+		 */
+		Value = (InstancePtr->SendByteCount > (s32)0) &&
+						((Error == 0));
+		while (Value != FALSE) {
+
+			/*
+			 * Find out how many can be sent.
+			 */
+			BytesToSend = InstancePtr->SendByteCount;
+			if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
+				BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
+			}
+
+			for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
+				XIicPs_SendByte(InstancePtr);
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * Wait for master to read the data out of fifo.
+			 */
+			while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
+							(Error == 0)) {
+
+				/*
+				 * If master terminates the transfer before all data is
+				 * sent, it is an error.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_ISR_OFFSET);
+				if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
+					Error = 1;
+				}
+
+				/* Clear ISR.
+				 */
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+							IntrStatusReg);
+
+				StatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_SR_OFFSET);
+			}
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+							(Error == 0));
+		}
+	}
+	if (Error != 0) {
+		Status = (s32)XST_FAILURE;
+	}
+
+	return Status;
+}
+/*****************************************************************************/
+/**
+* This function receives a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Count;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	/*
+	 * Clear the interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Clear the status register.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	Count = InstancePtr->RecvByteCount;
+	while (Count > (s32)0) {
+
+		/* Wait for master to put data */
+		while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
+		    StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * If master terminates the transfer before we get all
+			 * the data or the master tries to read from us,
+			 * it is an error.
+			 */
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_ISR_OFFSET);
+			if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
+					XIICPS_IXR_COMP_MASK))!=0x0U) &&
+				((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
+				((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+
+				return (s32)XST_FAILURE;
+			}
+
+			/*
+			 * Clear the interrupt status register.
+			 */
+			XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+			IntrStatusReg);
+		}
+
+		/*
+		 * Read all data from FIFO.
+		 */
+		while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			 ((InstancePtr->RecvByteCount > 0) != 0x0U)){
+
+			XIicPs_RecvByte(InstancePtr);
+
+			StatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_SR_OFFSET);
+		}
+		Count = InstancePtr->RecvByteCount;
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for slave mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper
+* handling.
+*
+* 
    +*
+* The interrupts that are handled are:
+* - DATA
+*	If the instance is sending, it means that the master wants to read more
+*	data from us. Send more data, and check whether we are done with this
+*	send.
+*
+*	If the instance is receiving, it means that the master has writen
+* 	more data to us. Receive more data, and check whether we are done with
+*	with this receive.
+*
+* - COMP
+*	This marks that stop sequence has been sent from the master, transfer
+*	is about to terminate. However, for receiving, the master may have
+*	written us some data, so receive that first.
+*
+*	It is an error if the amount of transfered data is less than expected.
+*
+* - NAK
+*	This marks that master does not want our data. It is for send only.
+*
+* - Other interrupts
+*	These interrupts are marked as error.
+*
+* 
    
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 IsSend = 0U;
+	u32 StatusEvent = 0U;
+	s32 LeftOver;
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are missed
+	 * while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
+
+	/*
+	 * Determine whether the device is sending.
+	 */
+	if (InstancePtr->RecvBufferPtr == NULL) {
+		IsSend = 1U;
+	}
+
+	/* Data interrupt
+	 *
+	 * This means master wants to do more data transfers.
+	 * Also check for completion of transfer, signal upper layer if done.
+	 */
+	if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
+		if (IsSend != 0x0U) {
+			LeftOver = TransmitFifoFill(InstancePtr);
+				/*
+				 * We may finish send here
+				 */
+				if (LeftOver == 0) {
+					StatusEvent |=
+						XIICPS_EVENT_COMPLETE_SEND;
+				}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+
+			/* We may finish the receive here */
+			if (LeftOver == 0) {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Complete interrupt.
+	 *
+	 * In slave mode, it means the master has done with this transfer, so
+	 * we signal the application using completion event.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
+		if (IsSend != 0x0U) {
+			if (InstancePtr->SendByteCount > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			}else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+			}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+			if (LeftOver > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			} else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Nack interrupt, pass this information to application.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
+				XIICPS_IXR_RX_UNF_MASK |
+				XIICPS_IXR_TX_OVR_MASK |
+				XIICPS_IXR_RX_OVR_MASK))){
+
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if ((u32)0U != StatusEvent) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function handles continuation of receiving data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes still expected by the instance.
+*
+* @note		None.
+*
+****************************************************************************/
+static s32 SlaveRecvData(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	u32 BaseAddr;
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+		XIicPs_RecvByte(InstancePtr);
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	return InstancePtr->RecvByteCount;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
new file mode 100644
index 0000000..c33322c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c
@@ -0,0 +1,1571 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains implements the interface functions of the XQspiPs driver.
+* See xqspips.h for a detailed description of the device and driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed XQspiPs_GetWriteData API.
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added logic to XQspiPs_GetReadData to handle data
+*		     shift for normal data reads and instruction/status
+*		     reads differently based on the ShiftReadData flag.
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+*		     This version of the driver fixes CRs 670197/663787.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*
+* 2.02a hk  05/14/13 Added enable and disable to the XQspiPs_LqspiRead()
+*			 function
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141
+*
+* 2.03a hk  09/05/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef defines qspi flash instruction format
+ */
+typedef struct {
+	u8 OpCode;	/**< Operational code of the instruction */
+	u8 InstSize;	/**< Size of the instruction including address bytes */
+	u8 TxOffset;	/**< Register address where instruction has to be
+			     written */
+} XQspiPsInstFormat;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define ARRAY_SIZE(Array)		(sizeof(Array) / sizeof((Array)[0]))
+
+/************************** Function Prototypes ******************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size);
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount);
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * List of all the QSPI instructions and its format
+ */
+static XQspiPsInstFormat FlashInst[] = {
+	{ XQSPIPS_FLASH_OPCODE_WREN, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_WRDS, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDSR1, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDSR2, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_WRSR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_PP, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_SE, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE_32K, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE_4K, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BE, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_ERASE_SUS, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_ERASE_RES, 1, XQSPIPS_TXD_01_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_RDID, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_NORM_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_FAST_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DUAL_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_QUAD_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DUAL_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_QUAD_IO_READ, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BRWR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_BRRD, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_EARWR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_EARRD, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_DIE_ERASE, 4, XQSPIPS_TXD_00_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_READ_FLAG_SR, 2, XQSPIPS_TXD_10_OFFSET },
+	{ XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR, 1, XQSPIPS_TXD_01_OFFSET },
+	/* Add all the instructions supported by the flash device */
+};
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Master mode
+*   - Active high clock polarity
+*   - Clock phase 0
+*   - Baud rate divisor 2
+*   - Transfer width 32
+*   - Master reference clock = pclk
+*   - No chip select active
+*   - Manual CS and Manual Start disabled
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific QSPI device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is busy, disallow the initialize and return a status
+	 * indicating it is already started. This allows the user to stop the
+	 * device and re-initialize, but prevents a user from inadvertently
+	 * initializing. This assumes the busy flag is cleared at startup.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		return XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->IsBusy = FALSE;
+
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->StatusHandler = StubStatusHandler;
+
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->RequestedBytes = 0;
+	InstancePtr->RemainingBytes = 0;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+
+	/*
+	 * Reset the QSPI device to get it into its initial state. It is
+	 * expected that device configuration will take place after this
+	 * initialization is done, but before the device is started.
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPI device. Reset must only be called after the driver has been
+* initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPI device after the reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_Reset(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress
+	 */
+	XQspiPs_Abort(InstancePtr);
+
+	/*
+	 * Write default value to configuration register.
+	 * Do not modify reserved bits.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET);
+	ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+	ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+			  ConfigReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by disabling the device and flush the RxFIFO.
+* The byte counts are cleared, the busy flag is cleared.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* This function does a read/modify/write of the config register. The user of
+* this function needs to take care of critical sections.
+*
+******************************************************************************/
+void XQspiPs_Abort(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+	u32 IsLock;
+
+	XQspiPs_Disable(InstancePtr);
+
+	/*
+	 * De-assert slave select lines.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			 XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * QSPI Software Reset
+	 */
+	IsLock = XQspiPs_ReadReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCKSTA);
+	if (IsLock) {
+		XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_UNLOCK,
+				SLCR_UNLOCK_MASK);
+	}
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL,
+			LQSPI_RST_CTRL_MASK);
+	XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, LQSPI_RST_CTRL, 0x0);
+	if (IsLock) {
+		XQspiPs_WriteReg(XPAR_XSLCR_0_BASEADDR, SLCR_LOCK,
+				SLCR_LOCK_MASK);
+	}
+
+	/*
+	 * Set the RX and TX FIFO threshold to reset value (one)
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_TXWR_OFFSET, XQSPIPS_TXWR_RESET_VALUE);
+
+	InstancePtr->RemainingBytes = 0;
+	InstancePtr->RequestedBytes = 0;
+	InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* Transfers specified data on the QSPI bus. Initiates bus communication and
+* sends/receives data to/from the selected QSPI slave. For every byte sent,
+* a byte is received.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* 
    +*   XQspiPs_Transfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XQspiPs_Transfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XQspiPs_Transfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XQspiPs_Transfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+* 
    
+* Although this function takes entire buffers as arguments, the driver can only
+* transfer a limited number of bytes at a time, limited by the size of the
+* FIFO. A call to this function only starts the transfer, then subsequent
+* transfers of the data is performed by the interrupt service routine until
+* the entire buffer has been transferred. The status callback function is
+* called when the entire buffer has been sent/received.
+*
+* This function is non-blocking. The SetSlaveSelect function must be called
+* prior to this function.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	SendBufPtr is a pointer to a data buffer that needs to be
+*		transmitted. This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+*
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		  device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		  progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+			u32 ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u8 Instruction;
+	u32 Data;
+	unsigned int Index;
+	u8 TransCount = 0;
+	XQspiPsInstFormat *CurrInst;
+	XQspiPsInstFormat NewInst[2];
+	u8 SwitchFlag  = 0;
+
+	CurrInst = &NewInst[0];
+
+	/*
+	 * The RecvBufPtr argument can be null
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared in the ISR when the
+	 * transfer is entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	/*
+	 * Set up buffer pointers.
+	 */
+	InstancePtr->SendBufferPtr = SendBufPtr;
+	InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+	InstancePtr->RequestedBytes = ByteCount;
+	InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * The first byte with every chip-select assertion is always
+	 * expected to be an instruction for flash interface mode
+	 */
+	Instruction = *InstancePtr->SendBufferPtr;
+
+	for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+		if (Instruction == FlashInst[Index].OpCode) {
+			break;
+		}
+	}
+
+	/*
+	 * Set the RX FIFO threshold
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+	/*
+	 * If the slave select is "Forced" or under manual control,
+	 * set the slave select now, before beginning the transfer.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET,
+				  ConfigReg);
+	}
+
+	/*
+	 * Enable the device.
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	/*
+	 * Clear all the interrrupts.
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+			XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+	if (Index < ARRAY_SIZE(FlashInst)) {
+		CurrInst = &FlashInst[Index];
+		/*
+		 * Check for WRSR instruction which has different size for
+		 * Spansion (3 bytes) and Micron (2 bytes)
+		 */
+		if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+			(ByteCount == 3) ) {
+			CurrInst->InstSize = 3;
+			CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+		}
+	}
+
+	/*
+	 * If instruction not present in table
+	 */
+	if (Index == ARRAY_SIZE(FlashInst)) {
+		/*
+		 * Assign current instruction, size and TXD register to be used
+		 * The InstSize mentioned in case of instructions greater than
+		 * 4 bytes is not the actual size, but is indicative of
+		 * the TXD register used.
+		 * The remaining bytes of the instruction will be transmitted
+		 * through TXD0 below.
+		 */
+		switch(ByteCount%4)
+		{
+			case XQSPIPS_SIZE_ONE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+				CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_TWO:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+				CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_THREE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+				CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			default:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+				CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+				break;
+		}
+	}
+
+	/*
+	 * If the instruction size in not 4 bytes then the data received needs
+	 * to be shifted
+	 */
+	if( CurrInst->InstSize != 4 ) {
+		InstancePtr->ShiftReadData = 1;
+	} else {
+		InstancePtr->ShiftReadData = 0;
+	}
+
+	/* Get the complete command (flash inst + address/data) */
+	Data = *((u32 *)InstancePtr->SendBufferPtr);
+	InstancePtr->SendBufferPtr += CurrInst->InstSize;
+	InstancePtr->RemainingBytes -= CurrInst->InstSize;
+	if (InstancePtr->RemainingBytes < 0) {
+		InstancePtr->RemainingBytes = 0;
+	}
+
+	/* Write the command to the FIFO */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			 CurrInst->TxOffset, Data);
+	TransCount++;
+
+	/*
+	 * If switching from TXD1/2/3 to TXD0, then start transfer and
+	 * check for FIFO empty
+	 */
+	if(SwitchFlag == 1) {
+		SwitchFlag = 0;
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (XQspiPs_IsManualStart(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+		/*
+		 * Wait for the transfer to finish by polling Tx fifo status.
+		 */
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+	}
+
+	/*
+	 * Fill the Tx FIFO with as many bytes as it takes (or as many as
+	 * we have to send).
+	 */
+	while ((InstancePtr->RemainingBytes > 0) &&
+		(TransCount < XQSPIPS_FIFO_DEPTH)) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_TXD_00_OFFSET,
+				  *((u32 *)InstancePtr->SendBufferPtr));
+		InstancePtr->SendBufferPtr += 4;
+		InstancePtr->RemainingBytes -= 4;
+		if (InstancePtr->RemainingBytes < 0) {
+			InstancePtr->RemainingBytes = 0;
+		}
+		TransCount++;
+	}
+
+	/*
+	 * Enable QSPI interrupts (connecting to the interrupt controller and
+	 * enabling interrupts should have been done by the caller).
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_IER_OFFSET, XQSPIPS_IXR_RXNEMPTY_MASK |
+			  XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXOVR_MASK |
+			  XQSPIPS_IXR_TXUF_MASK);
+
+	/*
+	 * If, in Manual Start mode, Start the transfer.
+	 */
+	if (XQspiPs_IsManualStart(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPS_CR_OFFSET);
+		ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Transfers specified data on the QSPI bus in polled mode.
+*
+* The caller has the option of providing two different buffers for send and
+* receive, or one buffer for both send and receive, or no buffer for receive.
+* The receive buffer must be at least as big as the send buffer to prevent
+* unwanted memory writes. This implies that the byte count passed in as an
+* argument must be the smaller of the two buffers if they differ in size.
+* Here are some sample usages:
+* 
    +*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, RecvBuf, ByteCount)
+*	The caller wishes to send and receive, and provides two different
+*	buffers for send and receive.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, NULL, ByteCount)
+*	The caller wishes only to send and does not care about the received
+*	data. The driver ignores the received data in this case.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, SendBuf, SendBuf, ByteCount)
+*	The caller wishes to send and receive, but provides the same buffer
+*	for doing both. The driver sends the data and overwrites the send
+*	buffer with received data as it transfers the data.
+*
+*   XQspiPs_PolledTransfer(InstancePtr, RecvBuf, RecvBuf, ByteCount)
+*	The caller wishes to only receive and does not care about sending
+*	data.  In this case, the caller must still provide a send buffer, but
+*	it can be the same as the receive buffer if the caller does not care
+*	what it sends.  The device must send N bytes of data if it wishes to
+*	receive N bytes of data.
+*
+* 
    
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	SendBufPtr is a pointer to a data buffer that needs to be
+*		transmitted. This buffer must not be NULL.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+*		This argument can be NULL if do not care about receiving.
+* @param	ByteCount contains the number of bytes to send/receive.
+*		The number of bytes received always equals the number of bytes
+*		sent.
+* @return
+*		- XST_SUCCESS if the buffers are successfully handed off to the
+*		  device for transfer.
+*		- XST_DEVICE_BUSY indicates that a data transfer is already in
+*		  progress. This is determined by the driver.
+*
+* @note
+*
+* This function is not thread-safe.  The higher layer software must ensure that
+* no two threads are transferring data on the QSPI bus at the same time.
+*
+******************************************************************************/
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, u32 ByteCount)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	u8 Instruction;
+	u32 Data;
+	u8 TransCount;
+	unsigned int Index;
+	XQspiPsInstFormat *CurrInst;
+	XQspiPsInstFormat NewInst[2];
+	u8 SwitchFlag  = 0;
+	u8 IsManualStart = FALSE;
+	u32 RxCount = 0;
+
+	CurrInst = &NewInst[0];
+	/*
+	 * The RecvBufPtr argument can be NULL.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(SendBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check whether there is another transfer in progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	/*
+	 * Set up buffer pointers.
+	 */
+	InstancePtr->SendBufferPtr = SendBufPtr;
+	InstancePtr->RecvBufferPtr = RecvBufPtr;
+
+	InstancePtr->RequestedBytes = ByteCount;
+	InstancePtr->RemainingBytes = ByteCount;
+
+	/*
+	 * The first byte with every chip-select assertion is always
+	 * expected to be an instruction for flash interface mode
+	 */
+	Instruction = *InstancePtr->SendBufferPtr;
+
+	for (Index = 0 ; Index < ARRAY_SIZE(FlashInst); Index++) {
+		if (Instruction == FlashInst[Index].OpCode) {
+			break;
+		}
+	}
+
+	/*
+	 * Set the RX FIFO threshold
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXFIFO_THRESHOLD_OPT);
+
+	/*
+	 * If the slave select is "Forced" or under manual control,
+	 * set the slave select now, before beginning the transfer.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET,
+				  ConfigReg);
+	}
+
+	/*
+	 * Enable the device.
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	if (Index < ARRAY_SIZE(FlashInst)) {
+
+		CurrInst = &FlashInst[Index];
+		/*
+		 * Check for WRSR instruction which has different size for
+		 * Spansion (3 bytes) and Micron (2 bytes)
+		 */
+		if( (CurrInst->OpCode == XQSPIPS_FLASH_OPCODE_WRSR) &&
+			(ByteCount == 3) ) {
+			CurrInst->InstSize = 3;
+			CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+		}
+	}
+
+	/*
+	 * If instruction not present in table
+	 */
+	if (Index == ARRAY_SIZE(FlashInst)) {
+		/*
+		 * Assign current instruction, size and TXD register to be used.
+		 * The InstSize mentioned in case of instructions greater than 4 bytes
+		 * is not the actual size, but is indicative of the TXD register used.
+		 * The remaining bytes of the instruction will be transmitted
+		 * through TXD0 below.
+		 */
+		switch(ByteCount%4)
+		{
+			case XQSPIPS_SIZE_ONE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_ONE;
+				CurrInst->TxOffset = XQSPIPS_TXD_01_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_TWO:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_TWO;
+				CurrInst->TxOffset = XQSPIPS_TXD_10_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			case XQSPIPS_SIZE_THREE:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_THREE;
+				CurrInst->TxOffset = XQSPIPS_TXD_11_OFFSET;
+				if(ByteCount > 4) {
+					SwitchFlag = 1;
+				}
+				break;
+			default:
+				CurrInst->OpCode = Instruction;
+				CurrInst->InstSize = XQSPIPS_SIZE_FOUR;
+				CurrInst->TxOffset = XQSPIPS_TXD_00_OFFSET;
+				break;
+		}
+	}
+
+	/*
+	 * If the instruction size in not 4 bytes then the data received needs
+	 * to be shifted
+	 */
+	if( CurrInst->InstSize != 4 ) {
+		InstancePtr->ShiftReadData = 1;
+	} else {
+		InstancePtr->ShiftReadData = 0;
+	}
+	TransCount = 0;
+	/* Get the complete command (flash inst + address/data) */
+	Data = *((u32 *)InstancePtr->SendBufferPtr);
+	InstancePtr->SendBufferPtr += CurrInst->InstSize;
+	InstancePtr->RemainingBytes -= CurrInst->InstSize;
+	if (InstancePtr->RemainingBytes < 0) {
+		InstancePtr->RemainingBytes = 0;
+	}
+
+	/* Write the command to the FIFO */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					CurrInst->TxOffset, Data);
+	++TransCount;
+
+	/*
+	 * If switching from TXD1/2/3 to TXD0, then start transfer and
+	 * check for FIFO empty
+	 */
+	if(SwitchFlag == 1) {
+		SwitchFlag = 0;
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (XQspiPs_IsManualStart(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+		/*
+		 * Wait for the transfer to finish by polling Tx fifo status.
+		 */
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0);
+
+	}
+
+	/*
+	 * Check if manual start is selected and store it in a
+	 * local varibale for reference. This is to avoid reading
+	 * the config register everytime.
+	 */
+	IsManualStart = XQspiPs_IsManualStart(InstancePtr);
+
+	/*
+	 * Fill the DTR/FIFO with as many bytes as it will take (or as
+	 * many as we have to send).
+	 */
+	while ((InstancePtr->RemainingBytes > 0) &&
+		(TransCount < XQSPIPS_FIFO_DEPTH)) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_TXD_00_OFFSET,
+				 *((u32 *)InstancePtr->SendBufferPtr));
+		InstancePtr->SendBufferPtr += 4;
+		InstancePtr->RemainingBytes -= 4;
+		if (InstancePtr->RemainingBytes < 0) {
+			InstancePtr->RemainingBytes = 0;
+		}
+		++TransCount;
+	}
+
+	while((InstancePtr->RemainingBytes > 0) ||
+	      (InstancePtr->RequestedBytes > 0)) {
+
+		/*
+		 * Fill the TX FIFO with RX threshold no. of entries (or as
+		 * many as we have to send, in case that's less).
+		 */
+		while ((InstancePtr->RemainingBytes > 0) &&
+			(TransCount < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_TXD_00_OFFSET,
+					 *((u32 *)InstancePtr->SendBufferPtr));
+			InstancePtr->SendBufferPtr += 4;
+			InstancePtr->RemainingBytes -= 4;
+			if (InstancePtr->RemainingBytes < 0) {
+				InstancePtr->RemainingBytes = 0;
+			}
+			++TransCount;
+		}
+
+		/*
+		 * If, in Manual Start mode, start the transfer.
+		 */
+		if (IsManualStart == TRUE) {
+			ConfigReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+			XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Reset TransCount - this is only used to fill TX FIFO
+		 * in the above loop;
+		 * RxCount is used to keep track of data received
+		 */
+		TransCount = 0;
+
+		/*
+		 * Wait for RX FIFO to reach threshold (or)
+		 * TX FIFO to become empty.
+		 * The latter check is required for
+		 * small transfers (<32 words) and
+		 * when the last chunk in a large data transfer is < 32 words.
+		 */
+
+		do {
+			StatusReg = XQspiPs_ReadReg(
+					InstancePtr->Config.BaseAddress,
+					XQSPIPS_SR_OFFSET);
+		} while ( ((StatusReg & XQSPIPS_IXR_TXOW_MASK) == 0) &&
+			((StatusReg & XQSPIPS_IXR_RXNEMPTY_MASK) == 0) );
+
+		/*
+		 * A transmit has just completed. Process received data
+		 * and check for more data to transmit.
+		 * First get the data received as a result of the
+		 * transmit that just completed. Receive data based on the
+		 * count obtained while filling tx fifo. Always get
+		 * the received data, but only fill the receive
+		 * buffer if it points to something (the upper layer
+		 * software may not care to receive data).
+		 */
+		while ((InstancePtr->RequestedBytes > 0) &&
+			(RxCount < XQSPIPS_RXFIFO_THRESHOLD_OPT )) {
+			u32 Data;
+
+			RxCount++;
+
+			if (InstancePtr->RecvBufferPtr != NULL) {
+				if (InstancePtr->RequestedBytes < 4) {
+					Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					XQspiPs_GetReadData(InstancePtr, Data,
+						InstancePtr->RequestedBytes);
+				} else {
+					(*(u32 *)InstancePtr->RecvBufferPtr) =
+						XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					InstancePtr->RecvBufferPtr += 4;
+					InstancePtr->RequestedBytes -= 4;
+					if (InstancePtr->RequestedBytes < 0) {
+						InstancePtr->RequestedBytes = 0;
+					}
+				}
+			} else {
+				Data = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+				InstancePtr->RequestedBytes -= 4;
+			}
+		}
+		RxCount = 0;
+	}
+
+	/*
+	 * If the Slave select lines are being manually controlled, disable
+	 * them because the transfer is complete.
+	 */
+	if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+		ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XQSPIPS_CR_OFFSET);
+		ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_CR_OFFSET, ConfigReg);
+	}
+
+	/*
+	 * Clear the busy flag.
+	 */
+	InstancePtr->IsBusy = FALSE;
+
+	/*
+	 * Disable the device.
+	 */
+	XQspiPs_Disable(InstancePtr);
+
+	/*
+	 * Reset the RX FIFO threshold to one
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the flash in Linear QSPI mode.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RecvBufPtr is a pointer to a buffer for received data.
+* @param	Address is the starting address within the flash from
+*		from where data needs to be read.
+* @param	ByteCount contains the number of bytes to receive.
+*
+* @return
+*		- XST_SUCCESS if read is performed
+*		- XST_FAILURE if Linear mode is not set
+*
+* @note		None.
+*
+*
+******************************************************************************/
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(RecvBufPtr != NULL);
+	Xil_AssertNonvoid(ByteCount > 0);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR
+#define	XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
+#endif
+	/*
+	 * Enable the controller
+	 */
+	XQspiPs_Enable(InstancePtr);
+
+	if (XQspiPs_GetLqspiConfigReg(InstancePtr) &
+		XQSPIPS_LQSPI_CR_LINEAR_MASK) {
+		memcpy((void*)RecvBufPtr,
+		      (const void*)(XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +
+		       Address),
+		      (size_t)ByteCount);
+		return XST_SUCCESS;
+	} else {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Disable the controller
+	 */
+	XQspiPs_Disable(InstancePtr);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects the slave with which the master communicates.
+*
+* The user is not allowed to select the slave while a transfer is in progress.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- XST_SUCCESS if the slave is selected or deselected
+*		  successfully.
+*		- XST_DEVICE_BUSY if a transfer is in progress, slave cannot be
+*		  changed.
+*
+* @note
+*
+* This function only sets the slave which will be selected when a transfer
+* occurs. The slave is not selected when the QSPI is idle.
+*
+******************************************************************************/
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Select the slave
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+	ConfigReg &= ~XQSPIPS_CR_SSCTRL_MASK;
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_CR_OFFSET, ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* 
    +*
+* XST_SPI_TRANSFER_DONE		The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
+*				but there were none available in the transmit
+*				register/FIFO. This typically means the slave
+*				application did not issue a transfer request
+*				fast enough, or the processor/driver could not
+*				fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN	The QSPI device lost data. Data was received
+*				but the receive data register/FIFO was full.
+*
+* 
    
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPtr;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				unsigned ByteCount)
+{
+	(void) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* The interrupt handler for QSPI interrupts. This function must be connected
+* by the user to an interrupt controller.
+*
+* The interrupts that are handled are:
+*
+*
+* - Data Transmit Register (FIFO) Empty. This interrupt is generated when the
+*   transmit register or FIFO is empty. The driver uses this interrupt during a
+*   transmission to continually send/receive data until the transfer is done.
+*
+* - Data Transmit Register (FIFO) Underflow. This interrupt is generated when
+*   the QSPI device, when configured as a slave, attempts to read an empty
+*   DTR/FIFO.  An empty DTR/FIFO usually means that software is not giving the
+*   device data in a timely manner. No action is taken by the driver other than
+*   to inform the upper layer software of the error.
+*
+* - Data Receive Register (FIFO) Overflow. This interrupt is generated when the
+*   QSPI device attempts to write a received byte to an already full DRR/FIFO.
+*   A full DRR/FIFO usually means software is not emptying the data in a timely
+*   manner.  No action is taken by the driver other than to inform the upper
+*   layer software of the error.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note
+*
+* The slave select register is being set to deselect the slave when a transfer
+* is complete.
+*
+******************************************************************************/
+void XQspiPs_InterruptHandler(void *InstancePtr)
+{
+	XQspiPs *QspiPtr = (XQspiPs *)InstancePtr;
+	u32 IntrStatus;
+	u32 ConfigReg;
+	u32 Data;
+	u32 TransCount;
+	u32 Count = 0;
+	unsigned BytesDone; /* Number of bytes done so far. */
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(QspiPtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Immediately clear the interrupts in case the ISR causes another
+	 * interrupt to be generated. If we clear at the end of the ISR,
+	 * we may miss newly generated interrupts. This occurs because we
+	 * transmit from within the ISR, which could potentially cause another
+	 * TX_EMPTY interrupt.
+	 */
+	IntrStatus = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+				      XQSPIPS_SR_OFFSET);
+	XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_SR_OFFSET,
+			  (IntrStatus & XQSPIPS_IXR_WR_TO_CLR_MASK));
+	XQspiPs_WriteReg(QspiPtr->Config.BaseAddress, XQSPIPS_IDR_OFFSET,
+			XQSPIPS_IXR_TXOW_MASK | XQSPIPS_IXR_RXNEMPTY_MASK |
+			XQSPIPS_IXR_RXOVR_MASK | XQSPIPS_IXR_TXUF_MASK);
+
+	if ((IntrStatus & XQSPIPS_IXR_TXOW_MASK) ||
+		(IntrStatus & XQSPIPS_IXR_RXNEMPTY_MASK)) {
+
+		/*
+		 * Rx FIFO has just reached threshold no. of entries.
+		 * Read threshold no. of entries from RX FIFO
+		 * Another possiblity of entering this loop is when
+		 * the last byte has been transmitted and TX FIFO is empty,
+		 * in which case, read all the data from RX FIFO.
+		 * Always get the received data, but only fill the
+		 * receive buffer if it is not null (it can be null when
+		 * the device does not care to receive data).
+		 */
+		TransCount = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+		if (TransCount % 4) {
+			TransCount = TransCount/4 + 1;
+		} else {
+			TransCount = TransCount/4;
+		}
+
+		while ((Count < TransCount) &&
+			(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+
+			if (QspiPtr->RecvBufferPtr != NULL) {
+				if (QspiPtr->RequestedBytes < 4) {
+					Data = XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					XQspiPs_GetReadData(QspiPtr, Data,
+						QspiPtr->RequestedBytes);
+				} else {
+					(*(u32 *)QspiPtr->RecvBufferPtr) =
+						XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+					QspiPtr->RecvBufferPtr += 4;
+					QspiPtr->RequestedBytes -= 4;
+					if (QspiPtr->RequestedBytes < 0) {
+						QspiPtr->RequestedBytes = 0;
+					}
+				}
+			} else {
+				XQspiPs_ReadReg(QspiPtr->Config.BaseAddress,
+						XQSPIPS_RXD_OFFSET);
+				QspiPtr->RequestedBytes -= 4;
+				if (QspiPtr->RequestedBytes < 0) {
+					QspiPtr->RequestedBytes = 0;
+				}
+
+			}
+			Count++;
+		}
+		Count = 0;
+		/*
+		 * Interrupt asserted as TX_OW got asserted
+		 * See if there is more data to send.
+		 * Fill TX FIFO with RX threshold no. of entries or
+		 * remaining entries (in case that is less than threshold)
+		 */
+		while ((QspiPtr->RemainingBytes > 0) &&
+			(Count < XQSPIPS_RXFIFO_THRESHOLD_OPT)) {
+			/*
+			 * Send more data.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_TXD_00_OFFSET,
+				*((u32 *)QspiPtr->SendBufferPtr));
+			QspiPtr->SendBufferPtr += 4;
+			QspiPtr->RemainingBytes -= 4;
+			if (QspiPtr->RemainingBytes < 0) {
+				QspiPtr->RemainingBytes = 0;
+			}
+
+			Count++;
+		}
+
+		if ((QspiPtr->RemainingBytes == 0) &&
+			(QspiPtr->RequestedBytes == 0)) {
+			/*
+			 * No more data to send.  Disable the interrupt
+			 * and inform the upper layer software that the
+			 * transfer is done. The interrupt will be re-enabled
+			 * when another transfer is initiated.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					  XQSPIPS_IDR_OFFSET,
+					  XQSPIPS_IXR_RXNEMPTY_MASK |
+					  XQSPIPS_IXR_TXOW_MASK |
+					  XQSPIPS_IXR_RXOVR_MASK |
+					  XQSPIPS_IXR_TXUF_MASK);
+
+			/*
+			 * If the Slave select is being manually controlled,
+			 * disable it because the transfer is complete.
+			 */
+			if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+				ConfigReg = XQspiPs_ReadReg(
+						QspiPtr->Config.BaseAddress,
+						XQSPIPS_CR_OFFSET);
+				ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+				XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+						  XQSPIPS_CR_OFFSET,
+						   ConfigReg);
+			}
+
+			/*
+			 * Clear the busy flag.
+			 */
+			QspiPtr->IsBusy = FALSE;
+
+			/*
+			 * Disable the device.
+			 */
+			XQspiPs_Disable(QspiPtr);
+
+			/*
+			 * Reset the RX FIFO threshold to one
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+			QspiPtr->StatusHandler(QspiPtr->StatusRef,
+						XST_SPI_TRANSFER_DONE,
+						QspiPtr->RequestedBytes);
+		} else {
+			/*
+			 * Enable the TXOW interrupt.
+			 */
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					 XQSPIPS_IER_OFFSET,
+					 XQSPIPS_IXR_RXNEMPTY_MASK |
+					 XQSPIPS_IXR_TXOW_MASK |
+					 XQSPIPS_IXR_RXOVR_MASK |
+					 XQSPIPS_IXR_TXUF_MASK);
+			/*
+			 * If, in Manual Start mode, start the transfer.
+			 */
+			if (XQspiPs_IsManualStart(QspiPtr)) {
+				ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET);
+				ConfigReg |= XQSPIPS_CR_MANSTRT_MASK;
+				XQspiPs_WriteReg(
+					QspiPtr->Config.BaseAddress,
+					 XQSPIPS_CR_OFFSET, ConfigReg);
+			}
+		}
+	}
+
+	/*
+	 * Check for overflow and underflow errors.
+	 */
+	if (IntrStatus & XQSPIPS_IXR_RXOVR_MASK) {
+		BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+		QspiPtr->IsBusy = FALSE;
+
+		/*
+		 * If the Slave select lines is being manually controlled,
+		 * disable it because the transfer is complete.
+		 */
+		if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+				XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Disable the device.
+		 */
+		XQspiPs_Disable(QspiPtr);
+
+		/*
+		 * Reset the RX FIFO threshold to one
+		 */
+		XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+		QspiPtr->StatusHandler(QspiPtr->StatusRef,
+			XST_SPI_RECEIVE_OVERRUN, BytesDone);
+	}
+
+	if (IntrStatus & XQSPIPS_IXR_TXUF_MASK) {
+		BytesDone = QspiPtr->RequestedBytes - QspiPtr->RemainingBytes;
+
+		QspiPtr->IsBusy = FALSE;
+		/*
+		 * If the Slave select lines is being manually controlled,
+		 * disable it because the transfer is complete.
+		 */
+		if (XQspiPs_IsManualChipSelect(InstancePtr)) {
+			ConfigReg = XQspiPs_ReadReg(
+					QspiPtr->Config.BaseAddress,
+					XQSPIPS_CR_OFFSET);
+			ConfigReg |= XQSPIPS_CR_SSCTRL_MASK;
+			XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+					  XQSPIPS_CR_OFFSET, ConfigReg);
+		}
+
+		/*
+		 * Disable the device.
+		 */
+		XQspiPs_Disable(QspiPtr);
+
+		/*
+		 * Reset the RX FIFO threshold to one
+		 */
+		XQspiPs_WriteReg(QspiPtr->Config.BaseAddress,
+			XQSPIPS_RXWR_OFFSET, XQSPIPS_RXWR_RESET_VALUE);
+
+		QspiPtr->StatusHandler(QspiPtr->StatusRef,
+				      XST_SPI_TRANSMIT_UNDERRUN, BytesDone);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Copies data from Data to the Receive buffer.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Data is the data which needs to be copied to the Rx buffer.
+* @param	Size is the number of bytes to be copied to the Receive buffer.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XQspiPs_GetReadData(XQspiPs *InstancePtr, u32 Data, u8 Size)
+{
+	u8 DataByte3;
+
+	if (InstancePtr->RecvBufferPtr) {
+		switch (Size) {
+		case 1:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u8 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0xFF000000) >> 24);
+			} else {
+				*((u8 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFF);
+			}
+			InstancePtr->RecvBufferPtr += 1;
+			break;
+		case 2:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0xFFFF0000) >> 16);
+			} else 	{
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFFFF);
+			}
+			InstancePtr->RecvBufferPtr += 2;
+			break;
+		case 3:
+			if (InstancePtr->ShiftReadData == 1) {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					((Data & 0x00FFFF00) >> 8);
+				InstancePtr->RecvBufferPtr += 2;
+				DataByte3 = ((Data & 0xFF000000) >> 24);
+				*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+			} else {
+				*((u16 *)InstancePtr->RecvBufferPtr) =
+					(Data & 0xFFFF);
+				InstancePtr->RecvBufferPtr += 2;
+				DataByte3 = ((Data & 0x00FF0000) >> 16);
+				*((u8 *)InstancePtr->RecvBufferPtr) = DataByte3;
+			}
+			InstancePtr->RecvBufferPtr += 1;
+			break;
+		default:
+			/* This will never execute */
+			break;
+		}
+	}
+	InstancePtr->ShiftReadData  = 0;
+	InstancePtr->RequestedBytes -= Size;
+	if (InstancePtr->RequestedBytes < 0) {
+		InstancePtr->RequestedBytes = 0;
+	}
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
new file mode 100644
index 0000000..139ce4d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h
@@ -0,0 +1,799 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips.h
+* @addtogroup qspips_v3_4
+* @{
+* @details
+*
+* This file contains the implementation of the XQspiPs driver. It supports only
+* master mode. User documentation for the driver functions is contained in this
+* file in the form of comment blocks at the front of each function.
+*
+* A QSPI device connects to an QSPI bus through a 4-wire serial interface.
+* The QSPI bus is a full-duplex, synchronous bus that facilitates communication
+* between one master and one slave. The device is always full-duplex,
+* which means that for every byte sent, one is received, and vice-versa.
+* The master controls the clock, so it can regulate when it wants to
+* send or receive data. The slave is under control of the master, it must
+* respond quickly since it has no control of the clock and must send/receive
+* data as fast or as slow as the master does.
+*
+*  Linear Mode 
+* The Linear Quad-SPI Controller extends the existing Quad-SPI Controller�s
+* functionality by adding a linear addressing scheme that allows the SPI flash
+* memory subsystem to behave like a typical ROM device.  The new feature hides
+* the normal SPI protocol from a master reading from the SPI flash memory. The
+* feature improves both the user friendliness and the overall read memory
+* throughput over that of the current Quad-SPI Controller by lessening the
+* amount of software overheads required and by the use of the faster AXI
+* interface.
+*
+* Initialization & Configuration
+*
+* The XQspiPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*	- XQspiPs_LookupConfig(DeviceId) - Use the device identifier to find
+*	  static configuration structure defined in xqspips_g.c. This is setup
+*	  by the tools. For some operating systems the config structure will be
+*	  initialized by the software and this call is not needed.
+*	- XQspiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	  configuration structure provided by the caller. If running in a system
+*	  with address translation, the provided virtual memory base address
+*	  replaces the physical address present in the configuration structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, but arbitration is the responsibility of
+* the higher layer software. The device driver does not perform any type of
+* arbitration.
+*
+* Modes of Operation
+*
+* There are four modes to perform a data transfer and the selection of a mode
+* is based on Chip Select(CS) and Start. These two options individually, can
+* be controlled either by software(Manual) or hardware(Auto).
+* - Auto CS: Chip select is automatically asserted as soon as the first word
+*	     is written into the TXFIFO and de asserted when the TXFIFO becomes
+*	     empty
+* - Manual CS: Software must assert and de assert CS.
+* - Auto Start: Data transmission starts as soon as there is data in the
+*		TXFIFO and stalls when the TXFIFO is empty
+* - Manual Start: Software must start data transmission at the beginning of
+*		  the transaction or whenever the TXFIFO has become empty
+*
+* The preferred combination is Manual CS and Auto Start.
+* In this combination, the software asserts CS before loading any data into
+* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
+* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
+* data is available. If no further data, software disables CS.
+*
+* Risks/challenges of other combinations:
+* - Manual CS and Manual Start: Manual Start bit should be set after each
+*   TXFIFO write otherwise there could be a race condition where the TXFIFO
+*   becomes empty before the new word is written. In that case the
+*   transmission stops.
+* - Auto CS with Manual or Auto Start: It is very difficult for software to
+*   keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is de asserted.
+*   This results in a single transaction to be split into multiple pieces each
+*   with its own chip select. This will result in garbage data to be sent.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XQspiPs_InterruptHandler, to an interrupt system such that it will be
+* called when an interrupt occurs. This function does not save and restore
+* the processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Data Transmit Register/FIFO Underflow
+* - Data Receive Register/FIFO Not Empty
+* - Data Transmit Register/FIFO Overwater
+* - Data Receive Register/FIFO Overrun
+*
+* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
+* QSPI device has transmitted the data available to transmit, and now its data
+* register and FIFO is ready to accept more data. The driver uses this
+* interrupt to indicate progress while sending data.  The driver may have
+* more data to send, in which case the data transmit register and FIFO is
+* filled for subsequent transmission. When this interrupt arrives and all
+* the data has been sent, the driver invokes the status callback with a
+* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
+* all data has been sent.
+*
+* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
+* as slave, the QSPI device was required to transmit but there was no data
+* available to transmit in the transmit register (or FIFO). This may not
+* be an error if the master is not expecting data. But in the case where
+* the master is expecting data, this serves as a notification of such a
+* condition. The driver reports this condition to the upper layer
+* software through the status handler.
+*
+* The Data Receive Register/FIFO Overrun interrupt -- indicates that the QSPI
+* device received data and subsequently dropped the data because the data
+* receive register and FIFO was full. The driver reports this condition to the
+* upper layer software through the status handler. This likely indicates a
+* problem with the higher layer protocol, or a problem with the slave
+* performance.
+*
+*
+* Polled Operation
+*
+* Transfer in polled mode is supported through a separate interface function
+* XQspiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
+* this function blocks until all data has been sent/received.
+*
+* Device Busy
+*
+* Some operations are disallowed when the device is busy. The driver tracks
+* whether a device is busy. The device is considered busy when a data transfer
+* request is outstanding, and is considered not busy only when that transfer
+* completes (or is aborted with a mode fault error).
+*
+* Device Configuration
+*
+* The device can be configured in various ways during the FPGA implementation
+* process. Configuration parameters are stored in the xqspips_g.c file or
+* passed in via XQspiPs_CfgInitialize(). A table is defined where each entry
+* contains configuration information for an QSPI device, including the base
+* address for the device.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied
+* by the layer above this driver.
+*
+* NOTE: This driver was always tested with endianess set to little-endian.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00a sdm 11/25/10 First release, based on the PS SPI driver...
+* 1.01a sdm 11/22/11 Added TCL file for generating QSPI parameters
+*		     in xparameters.h
+* 2.00a kka 07/25/12 Added a few register defines for CR 670297
+* 		     Removed code related to mode fault for CR 671468
+*		     The XQspiPs_SetSlaveSelect has been modified to remove
+*		     the argument of the slave select as the QSPI controller
+*		     only supports one slave.
+* 		     XQspiPs_GetSlaveSelect API has been removed
+* 		     Added a flag ShiftReadData to the instance structure
+*.		     and is used in the XQspiPs_GetReadData API.
+*		     The ShiftReadData Flag indicates whether the data
+*		     read from the Rx FIFO needs to be shifted
+*		     in cases where the data is less than 4  bytes
+* 		     Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode and doesnot support
+*		     Slave mode or the legacy mode.
+*		     Modified the XQspiPs_PolledTransfer and XQspiPs_Transfer
+*		     APIs so that the last argument (IsInst) specifying whether
+*		     it is instruction or data has been removed. The first byte
+*		     in the SendBufPtr argument of these APIs specify the
+*		     instruction to be sent to the Flash Device.
+*		     This version of the driver fixes CRs 670197/663787/
+*		     670297/671468.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+*		     The XQspiPs_PolledTransfer function has been updated
+*		     to fill the data to fifo depth.
+* 2.01a sg  02/03/13 Added flash opcodes for DUAL_IO_READ,QUAD_IO_READ.
+*		     Added macros for Set/Get Rx Watermark. Changed QSPI
+*		     Enable/Disable macro argument from BaseAddress to
+*		     Instance Pointer. Added DelayNss argument to SetDelays
+*		     and GetDelays API's.
+*		     Created macros XQspiPs_IsManualStart and
+*		     XQspiPs_IsManualChipSelect.
+*		     Changed QSPI transfer logic for polled and interrupt
+*		     modes to be based on filled tx fifo count and receive
+*		     based on it. RXNEMPTY interrupt is not used.
+*		     Added assertions to XQspiPs_LqspiRead function.
+*		     SetDelays and GetDelays API's include DelayNss parameter.
+*		     Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register. Renamed Fixed burst error to
+*		     data FSM error in  LQSPI Status register.
+*
+* 2.02a hk  05/07/13 Added ConnectionMode to config structure.
+*			 Corresponds to C_QSPI_MODE - 0:Single, 1:Stacked, 2:Parallel
+*			 Added enable and disable to the XQspiPs_LqspiRead() function
+*			 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set.
+*            Added instructions for bank selection, die erase and
+*            flag status register to the flash instruction table
+*            Handling for instructions not in flash instruction
+*			 table added. Checking for Tx FIFO empty when switching from
+*			 TXD1/2/3 to TXD0 added. If WRSR instruction is sent with
+*            byte count 3 (spansion), instruction size and TXD register
+*			 changed accordingly. CR# 712502 and 703869.
+*            Added prefix to constant definitions for ConnectionMode
+*            Added (#ifdef linear base address) in the Linear read function.
+*            Changed  XPAR_XQSPIPS_0_LINEAR_BASEADDR to
+*            XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR in
+*            XQspiPs_LqspiRead function. Fix for CR#718141.
+*
+* 2.03a hk  09/17/13 Modified polled and interrupt transfers to make use of
+*                    thresholds. This is to improve performance.
+*                    Added API's for QSPI reset and
+*                    linear mode initialization for boot.
+*                    Added RX and TX threshold reset to one in XQspiPs_Abort.
+*                    Added RX threshold reset(1) after transfer in polled and
+*                    interrupt transfers. Made changes to make sure threshold
+*                    change is done only when no transfer is in progress.
+*                    Updated linear init API for parallel and stacked modes.
+*                    CR#737760.
+* 3.1   hk  08/13/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+*       ms  04/05/17 Modified Comment lines in functions of qspips
+*                    examples to recognize it as documentation block
+*                    and modified filename tag in
+*                    xqspips_dual_flash_stack_lqspi_example.c to include it in
+*                    doxygen examples.
+* 3.4   nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file
+*
+* 
    
+*
+******************************************************************************/
+#ifndef XQSPIPS_H		/* prevent circular inclusions */
+#define XQSPIPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips_hw.h"
+#include 
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options are supported to enable/disable certain features of
+ * an QSPI device.  Each of the options is a bit mask, so more than one may be
+ * specified.
+ *
+ *
+ * The Active Low Clock option configures the device's clock polarity.
+ * Setting this option means the clock is active low and the SCK signal idles
+ * high. By default, the clock is active high and SCK idles low.
+ *
+ * The Clock Phase option configures the QSPI device for one of two
+ * transfer formats.  A clock phase of 0, the default, means data is valid on
+ * the first SCK edge (rising or falling) after the slave select (SS) signal
+ * has been asserted. A clock phase of 1 means data is valid on the second SCK
+ * edge (rising or falling) after SS has been asserted.
+ *
+ *
+ * The QSPI Force Slave Select option is used to enable manual control of
+ * the slave select signal.
+ * 0: The SPI_SS signal is controlled by the QSPI controller during
+ * transfers. (Default)
+ * 1: The SPI_SS signal is forced active (driven low) regardless of any
+ * transfers in progress.
+ *
+ * NOTE: The driver will handle setting and clearing the Slave Select when
+ * the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
+ * QSPI clock to be set to a faster speed. If the QSPI clock is too fast, the
+ * processor cannot empty and refill the FIFOs before the TX FIFO is empty
+ * When the QSPI hardware is controlling the Slave Select signals, this
+ * will cause slave to be de-selected and terminate the transfer.
+ *
+ * The Manual Start option is used to enable manual control of
+ * the Start command to perform data transfer.
+ * 0: The Start command is controlled by the QSPI controller during
+ * transfers(Default). Data transmission starts as soon as there is data in
+ * the TXFIFO and stalls when the TXFIFO is empty
+ * 1: The Start command must be issued by software to perform data transfer.
+ * Bit 15 of Configuration register is used to issue Start command. This bit
+ * must be set whenever TXFIFO is filled with new data.
+ *
+ * NOTE: The driver will set the Manual Start Enable bit in Configuration
+ * Register, if Manual Start option is selected. Software will issue
+ * Manual Start command whenever TXFIFO is filled with data. When there is
+ * no further data, driver will clear the Manual Start Enable bit.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_ACTIVE_LOW_OPTION	0x2  /**< Active Low Clock option */
+#define XQSPIPS_CLK_PHASE_1_OPTION	0x4  /**< Clock Phase one option */
+#define XQSPIPS_FORCE_SSELECT_OPTION	0x10 /**< Force Slave Select */
+#define XQSPIPS_MANUAL_START_OPTION	0x20 /**< Manual Start enable */
+#define XQSPIPS_LQSPI_MODE_OPTION	0x80 /**< Linear QPSI mode */
+#define XQSPIPS_HOLD_B_DRIVE_OPTION	0x100 /**< Drive HOLD_B Pin */
+/*@}*/
+
+
+/** @name QSPI Clock Prescaler options
+ * The QSPI Clock Prescaler Configuration bits are used to program master mode
+ * bit rate. The bit rate can be programmed in divide-by-two decrements from
+ * pclk/2 to pclk/256.
+ *
+ * @{
+ */
+#define XQSPIPS_CLK_PRESCALE_2		0x00 /**< PCLK/2 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_4		0x01 /**< PCLK/4 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_8		0x02 /**< PCLK/8 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_16		0x03 /**< PCLK/16 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_32		0x04 /**< PCLK/32 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_64		0x05 /**< PCLK/64 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_128	0x06 /**< PCLK/128 Prescaler */
+#define XQSPIPS_CLK_PRESCALE_256	0x07 /**< PCLK/256 Prescaler */
+
+/*@}*/
+
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to
+ * a handler from the driver.  These constants are not bit masks such that
+ * only one will be passed at a time to the handler.
+ *
+ * @{
+ */
+#define XQSPIPS_EVENT_TRANSFER_DONE	2 /**< Transfer done */
+#define XQSPIPS_EVENT_TRANSMIT_UNDERRUN 3 /**< TX FIFO empty */
+#define XQSPIPS_EVENT_RECEIVE_OVERRUN	4 /**< Receive data loss because
+						RX FIFO full */
+/*@}*/
+
+/** @name Flash commands
+ *
+ * The following constants define most of the commands supported by flash
+ * devices. Users can add more commands supported by the flash devices
+ *
+ * @{
+ */
+#define	XQSPIPS_FLASH_OPCODE_WRSR	0x01 /* Write status register */
+#define	XQSPIPS_FLASH_OPCODE_PP		0x02 /* Page program */
+#define	XQSPIPS_FLASH_OPCODE_NORM_READ	0x03 /* Normal read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_WRDS	0x04 /* Write disable */
+#define	XQSPIPS_FLASH_OPCODE_RDSR1	0x05 /* Read status register 1 */
+#define	XQSPIPS_FLASH_OPCODE_WREN	0x06 /* Write enable */
+#define	XQSPIPS_FLASH_OPCODE_FAST_READ	0x0B /* Fast read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_4K	0x20 /* Erase 4KiB block */
+#define	XQSPIPS_FLASH_OPCODE_RDSR2	0x35 /* Read status register 2 */
+#define	XQSPIPS_FLASH_OPCODE_DUAL_READ	0x3B /* Dual read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_BE_32K	0x52 /* Erase 32KiB block */
+#define	XQSPIPS_FLASH_OPCODE_QUAD_READ	0x6B /* Quad read data bytes */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_SUS	0x75 /* Erase suspend */
+#define	XQSPIPS_FLASH_OPCODE_ERASE_RES	0x7A /* Erase resume */
+#define	XQSPIPS_FLASH_OPCODE_RDID	0x9F /* Read JEDEC ID */
+#define	XQSPIPS_FLASH_OPCODE_BE		0xC7 /* Erase whole flash block */
+#define	XQSPIPS_FLASH_OPCODE_SE		0xD8 /* Sector erase (usually 64KB)*/
+#define XQSPIPS_FLASH_OPCODE_DUAL_IO_READ 0xBB /* Read data using Dual I/O */
+#define XQSPIPS_FLASH_OPCODE_QUAD_IO_READ 0xEB /* Read data using Quad I/O */
+#define XQSPIPS_FLASH_OPCODE_BRWR	0x17 /* Bank Register Write */
+#define XQSPIPS_FLASH_OPCODE_BRRD	0x16 /* Bank Register Read */
+/* Extende Address Register Write - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARWR	0xC5
+/* Extende Address Register Read - Micron's equivalent of Bank Register */
+#define XQSPIPS_FLASH_OPCODE_EARRD	0xC8
+#define XQSPIPS_FLASH_OPCODE_DIE_ERASE	0xC4
+#define XQSPIPS_FLASH_OPCODE_READ_FLAG_SR	0x70
+#define XQSPIPS_FLASH_OPCODE_CLEAR_FLAG_SR	0x50
+#define XQSPIPS_FLASH_OPCODE_READ_LOCK_REG	0xE8	/* Lock register Read */
+#define XQSPIPS_FLASH_OPCODE_WRITE_LOCK_REG	0xE5	/* Lock Register Write */
+
+/*@}*/
+
+/** @name Instruction size
+ *
+ * The following constants define numbers 1 to 4.
+ * Used to identify whether TXD0,1,2 or 3 is to be used.
+ *
+ * @{
+ */
+#define XQSPIPS_SIZE_ONE 	1
+#define XQSPIPS_SIZE_TWO 	2
+#define XQSPIPS_SIZE_THREE 	3
+#define XQSPIPS_SIZE_FOUR 	4
+
+/*@}*/
+
+/** @name ConnectionMode
+ *
+ * The following constants are the possible values of ConnectionMode in
+ * Config structure.
+ *
+ * @{
+ */
+#define XQSPIPS_CONNECTION_MODE_SINGLE		0
+#define XQSPIPS_CONNECTION_MODE_STACKED		1
+#define XQSPIPS_CONNECTION_MODE_PARALLEL	2
+
+/*@}*/
+
+/** @name FIFO threshold value
+ *
+ * This is the Rx FIFO threshold (in words) that was found to be most
+ * optimal in terms of performance
+ *
+ * @{
+ */
+#define XQSPIPS_RXFIFO_THRESHOLD_OPT		32
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPI device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPs_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPs_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					unsigned ByteCount);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
+} XQspiPs_Config;
+
+/**
+ * The XQspiPs driver instance data. The user is required to allocate a
+ * variable of this type for every QSPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPs_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	int RequestedBytes;	 /**< Number of bytes to transfer (state) */
+	int RemainingBytes;	 /**< Number of bytes left to transfer(state) */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	XQspiPs_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+	u32 ShiftReadData;	 /**<  Flag to indicate whether the data
+				   *   read from the Rx FIFO needs to be shifted
+				   *   in cases where the data is less than 4
+				   *   bytes
+				   */
+} XQspiPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Start Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualStart(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualStart(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_MANUAL_START_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/*
+*
+* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
+*
+* @param	InstancePtr is a pointer to the XSpiPs instance.
+*
+* @return
+*		- TRUE if option is set
+*		- FALSE if option is not set
+*
+* @note		C-Style signature:
+*		u8 XQspiPs_IsManualChipSelect(XQspiPs *InstancePtr);
+*
+*****************************************************************************/
+#define XQspiPs_IsManualChipSelect(InstancePtr) \
+	((XQspiPs_GetOptions(InstancePtr) & \
+	  XQSPIPS_FORCE_SSELECT_OPTION) ? TRUE : FALSE)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the slave idle count register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are
+*		0-255.
+*
+* @return	None
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetSlaveIdle(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetSlaveIdle(InstancePtr, RegisterValue)	\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 	\
+			XQSPIPS_SICR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the slave idle count register. Use the XQSPIPS_SICR_*
+* constants defined in xqspips_hw.h to interpret the bit-mask returned.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	An 8-bit value representing Slave Idle Count.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetSlaveIdle(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetSlaveIdle(InstancePtr)				\
+	XQspiPs_In32(((InstancePtr)->Config.BaseAddress) + 		\
+	XQSPIPS_SICR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the transmit FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetTXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetTXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_TXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the transmit FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Tx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetTXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetTXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_TXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the receive FIFO watermark register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written, valid values are 1-63.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetRXWatermark(XQspiPs *InstancePtr, u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetRXWatermark(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) + 		\
+			XQSPIPS_RXWR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the receive FIFO watermark register.
+* Valid values are in the range 1-63.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 6-bit value representing Rx Watermark level.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetRXWatermark(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetRXWatermark(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) + XQSPIPS_RXWR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable the device and uninhibit master transactions.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Enable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Enable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, \
+			XQSPIPS_ER_ENABLE_MASK)
+
+/****************************************************************************/
+/**
+*
+* Disable the device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_Disable(XQspiPs *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_Disable(InstancePtr)					\
+	XQspiPs_Out32((InstancePtr->Config.BaseAddress) + XQSPIPS_ER_OFFSET, 0)
+
+/****************************************************************************/
+/**
+*
+* Set the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	RegisterValue is the value to be written to the Linear QSPI
+*		configuration register.
+*
+* @return	None.
+*
+* @note
+* C-Style signature:
+*	void XQspiPs_SetLqspiConfigReg(XQspiPs *InstancePtr,
+*					u32 RegisterValue)
+*
+*****************************************************************************/
+#define XQspiPs_SetLqspiConfigReg(InstancePtr, RegisterValue)		\
+	XQspiPs_Out32(((InstancePtr)->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET, (RegisterValue))
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the Linear QSPI Configuration register.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	A 32-bit value representing the contents of the LQSPI Config
+*		register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_GetLqspiConfigReg(u32 *InstancePtr)
+*
+*****************************************************************************/
+#define XQspiPs_GetLqspiConfigReg(InstancePtr)				\
+	XQspiPs_In32((InstancePtr->Config.BaseAddress) +		\
+			XQSPIPS_LQSPI_CR_OFFSET)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization function, implemented in xqspips_sinit.c
+ */
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions implemented in xqspips.c
+ */
+int XQspiPs_CfgInitialize(XQspiPs *InstancePtr, XQspiPs_Config * Config,
+			   u32 EffectiveAddr);
+void XQspiPs_Reset(XQspiPs *InstancePtr);
+void XQspiPs_Abort(XQspiPs *InstancePtr);
+
+s32 XQspiPs_Transfer(XQspiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
+		      u32 ByteCount);
+s32 XQspiPs_PolledTransfer(XQspiPs *InstancePtr, u8 *SendBufPtr,
+			    u8 *RecvBufPtr, u32 ByteCount);
+int XQspiPs_LqspiRead(XQspiPs *InstancePtr, u8 *RecvBufPtr,
+			u32 Address, unsigned ByteCount);
+
+int XQspiPs_SetSlaveSelect(XQspiPs *InstancePtr);
+
+void XQspiPs_SetStatusHandler(XQspiPs *InstancePtr, void *CallBackRef,
+				XQspiPs_StatusHandler FuncPtr);
+void XQspiPs_InterruptHandler(void *InstancePtr);
+
+/*
+ * Functions for selftest, in xqspips_selftest.c
+ */
+int XQspiPs_SelfTest(XQspiPs *InstancePtr);
+
+/*
+ * Functions for options, in xqspips_options.c
+ */
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options);
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr);
+
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler);
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr);
+
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit);
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
new file mode 100644
index 0000000..d739e62
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspips.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_QSPI_0_DEVICE_ID,
+		XPAR_PS7_QSPI_0_BASEADDR,
+		XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ,
+		XPAR_PS7_QSPI_0_QSPI_MODE
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
new file mode 100644
index 0000000..1817b07
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c
@@ -0,0 +1,224 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains low level functions, primarily reset related.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 2.03a hk  09/17/13 First release
+* 3.1   hk  06/19/14 When writing to the configuration register, set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips_hw.h"
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Pre-scaler value for divided by 4
+ *
+ * Pre-scaler value for divided by 4
+ *
+ * @{
+ */
+#define XQSPIPS_CR_PRESC_DIV_BY_4	0x01
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Resets QSPI by disabling the device and bringing it to reset state through
+* register writes.
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_ResetHw(u32 BaseAddress)
+{
+	u32 ConfigReg;
+
+	/*
+	 * Disable interrupts
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_IDR_OFFSET,
+				XQSPIPS_IXR_DISABLE_ALL);
+
+	/*
+	 * Disable device
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+				0);
+
+	/*
+	 * De-assert slave select lines.
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_SSCTRL_MASK | XQSPIPS_CR_SSFORCE_MASK);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Write default value to RX and TX threshold registers
+	 * RX threshold should be set to 1 here because the corresponding
+	 * status bit is used next to clear the RXFIFO
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_TXWR_OFFSET,
+			(XQSPIPS_TXWR_RESET_VALUE & XQSPIPS_TXWR_MASK));
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_RXWR_OFFSET,
+			(XQSPIPS_RXWR_RESET_VALUE & XQSPIPS_RXWR_MASK));
+
+	/*
+	 * Clear RXFIFO
+	 */
+	while ((XQspiPs_ReadReg(BaseAddress,XQSPIPS_SR_OFFSET) &
+		XQSPIPS_IXR_RXNEMPTY_MASK) != 0) {
+		XQspiPs_ReadReg(BaseAddress, XQSPIPS_RXD_OFFSET);
+	}
+
+	/*
+	 * Clear status register by reading register and
+	 * writing 1 to clear the write to clear bits
+	 */
+	XQspiPs_ReadReg(BaseAddress, XQSPIPS_SR_OFFSET);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_SR_OFFSET,
+				XQSPIPS_IXR_WR_TO_CLR_MASK);
+
+	/*
+	 * Write default value to configuration register
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
+	ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * De-select linear mode
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+				0x0);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initializes QSPI to Linear mode with default QSPI boot settings.
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_LinearInit(u32 BaseAddress)
+{
+	u32 BaudRateDiv;
+	u32 LinearCfg;
+	u32 ConfigReg;
+
+	/*
+	 * Baud rate divisor for dividing by 4. Value of CR bits [5:3]
+	 * should be set to 0x001; hence shift the value and use the mask.
+	 */
+	BaudRateDiv = ( (XQSPIPS_CR_PRESC_DIV_BY_4) <<
+			XQSPIPS_CR_PRESC_SHIFT) & XQSPIPS_CR_PRESC_MASK;
+	/*
+	 * Write configuration register with default values, slave selected &
+	 * pre-scaler value for divide by 4
+	 */
+	ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
+	ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
+	ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Write linear configuration register with default value -
+	 * enable linear mode and use fast read.
+	 */
+
+	if(XPAR_XQSPIPS_0_QSPI_MODE == XQSPIPS_CONNECTION_MODE_SINGLE){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE;
+
+	}else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+			XQSPIPS_CONNECTION_MODE_STACKED){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+				XQSPIPS_LQSPI_CR_TWO_MEM_MASK;
+
+	}else if(XPAR_XQSPIPS_0_QSPI_MODE ==
+			XQSPIPS_CONNECTION_MODE_PARALLEL){
+
+		LinearCfg = XQSPIPS_LQSPI_CR_RST_STATE |
+				XQSPIPS_LQSPI_CR_TWO_MEM_MASK |
+				XQSPIPS_LQSPI_CR_SEP_BUS_MASK;
+
+	}
+
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_LQSPI_CR_OFFSET,
+				LinearCfg);
+
+	/*
+	 * Enable device
+	 */
+	XQspiPs_WriteReg(BaseAddress, XQSPIPS_ER_OFFSET,
+				XQSPIPS_ER_ENABLE_MASK);
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
new file mode 100644
index 0000000..96c867a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h
@@ -0,0 +1,423 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_hw.h
+* @addtogroup qspips_v3_4
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xqspips.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a ka  07/25/12 Added a few register defines for CR 670297
+*		     and removed some defines of reserved fields for
+*		     CR 671468
+*		     Added define XQSPIPS_CR_HOLD_B_MASK for Holdb_dr
+*		     bit in Configuration register.
+* 2.01a sg  02/03/13 Added defines for DelayNss,Rx Watermark,Interrupts
+*		     which need write to clear. Removed Read zeros mask from
+*		     LQSPI Config register.
+* 2.03a hk  08/22/13 Added prototypes of API's for QSPI reset and
+*                    linear mode initialization for boot. Added related
+*                    constant definitions.
+* 3.1   hk  08/13/14 Changed definition of CR reset value masks to set/reset
+*                    required bits leaving reserved bits untouched. CR# 796813.
+* 3.2	sk	02/05/15 Add SLCR reset in abort function as a workaround because
+* 					 controller does not update FIFO status flags as expected
+* 					 when thresholds are used.
+*
+* 
    
+*
+******************************************************************************/
+#ifndef XQSPIPS_HW_H		/* prevent circular inclusions */
+#define XQSPIPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an QSPI device.
+ * @{
+ */
+#define XQSPIPS_CR_OFFSET	 	0x00 /**< Configuration Register */
+#define XQSPIPS_SR_OFFSET	 	0x04 /**< Interrupt Status */
+#define XQSPIPS_IER_OFFSET	 	0x08 /**< Interrupt Enable */
+#define XQSPIPS_IDR_OFFSET	 	0x0c /**< Interrupt Disable */
+#define XQSPIPS_IMR_OFFSET	 	0x10 /**< Interrupt Enabled Mask */
+#define XQSPIPS_ER_OFFSET	 	0x14 /**< Enable/Disable Register */
+#define XQSPIPS_DR_OFFSET	 	0x18 /**< Delay Register */
+#define XQSPIPS_TXD_00_OFFSET	 	0x1C /**< Transmit 4-byte inst/data */
+#define XQSPIPS_RXD_OFFSET	 	0x20 /**< Data Receive Register */
+#define XQSPIPS_SICR_OFFSET	 	0x24 /**< Slave Idle Count */
+#define XQSPIPS_TXWR_OFFSET	 	0x28 /**< Transmit FIFO Watermark */
+#define XQSPIPS_RXWR_OFFSET	 	0x2C /**< Receive FIFO Watermark */
+#define XQSPIPS_GPIO_OFFSET	 	0x30 /**< GPIO Register */
+#define XQSPIPS_LPBK_DLY_ADJ_OFFSET	0x38 /**< Loopback Delay Adjust Reg */
+#define XQSPIPS_TXD_01_OFFSET	 	0x80 /**< Transmit 1-byte inst */
+#define XQSPIPS_TXD_10_OFFSET	 	0x84 /**< Transmit 2-byte inst */
+#define XQSPIPS_TXD_11_OFFSET	 	0x88 /**< Transmit 3-byte inst */
+#define XQSPIPS_LQSPI_CR_OFFSET  	0xA0 /**< Linear QSPI config register */
+#define XQSPIPS_LQSPI_SR_OFFSET  	0xA4 /**< Linear QSPI status register */
+#define XQSPIPS_MOD_ID_OFFSET  		0xFC /**< Module ID register */
+
+/* @} */
+
+/** @name Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the QSPI device. Read/Write.
+ * @{
+ */
+
+#define XQSPIPS_CR_IFMODE_MASK    0x80000000 /**< Flash mem interface mode */
+#define XQSPIPS_CR_ENDIAN_MASK    0x04000000 /**< Tx/Rx FIFO endianness */
+#define XQSPIPS_CR_MANSTRT_MASK   0x00010000 /**< Manual Transmission Start */
+#define XQSPIPS_CR_MANSTRTEN_MASK 0x00008000 /**< Manual Transmission Start
+						   Enable */
+#define XQSPIPS_CR_SSFORCE_MASK   0x00004000 /**< Force Slave Select */
+#define XQSPIPS_CR_SSCTRL_MASK    0x00000400 /**< Slave Select Decode */
+#define XQSPIPS_CR_SSCTRL_SHIFT   10	      /**< Slave Select Decode shift */
+#define XQSPIPS_CR_DATA_SZ_MASK   0x000000C0 /**< Size of word to be
+						   transferred */
+#define XQSPIPS_CR_PRESC_MASK     0x00000038 /**< Prescaler Setting */
+#define XQSPIPS_CR_PRESC_SHIFT    3	      /**< Prescaler shift */
+#define XQSPIPS_CR_PRESC_MAXIMUM  0x07	      /**< Prescaler maximum value */
+
+#define XQSPIPS_CR_CPHA_MASK      0x00000004 /**< Phase Configuration */
+#define XQSPIPS_CR_CPOL_MASK      0x00000002 /**< Polarity Configuration */
+
+#define XQSPIPS_CR_MSTREN_MASK    0x00000001 /**< Master Mode Enable */
+
+#define XQSPIPS_CR_HOLD_B_MASK    0x00080000 /**< HOLD_B Pin Drive Enable */
+
+#define XQSPIPS_CR_REF_CLK_MASK   0x00000100 /**< Ref clk bit - should be 0 */
+
+/* Deselect the Slave select line and set the transfer size to 32 at reset */
+#define XQSPIPS_CR_RESET_MASK_SET  XQSPIPS_CR_IFMODE_MASK | \
+				   XQSPIPS_CR_SSCTRL_MASK | \
+				   XQSPIPS_CR_DATA_SZ_MASK | \
+				   XQSPIPS_CR_MSTREN_MASK | \
+				   XQSPIPS_CR_SSFORCE_MASK | \
+				   XQSPIPS_CR_HOLD_B_MASK
+#define XQSPIPS_CR_RESET_MASK_CLR  XQSPIPS_CR_CPOL_MASK | \
+				   XQSPIPS_CR_CPHA_MASK | \
+				   XQSPIPS_CR_PRESC_MASK | \
+				   XQSPIPS_CR_MANSTRTEN_MASK | \
+				   XQSPIPS_CR_MANSTRT_MASK | \
+				   XQSPIPS_CR_ENDIAN_MASK | \
+				   XQSPIPS_CR_REF_CLK_MASK
+/* @} */
+
+
+/** @name QSPI Interrupt Registers
+ *
+ * QSPI Status Register
+ *
+ * This register holds the interrupt status flags for an QSPI device. Some
+ * of the flags are level triggered, which means that they are set as long
+ * as the interrupt condition exists. Other flags are edge triggered,
+ * which means they are set once the interrupt condition occurs and remain
+ * set until they are cleared by software. The interrupts are cleared by
+ * writing a '1' to the interrupt bit position in the Status Register.
+ * Read/Write.
+ *
+ * QSPI Interrupt Enable Register
+ *
+ * This register is used to enable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * QSPI Interrupt Mask register.  Write only.
+ *
+ * QSPI Interrupt Disable Register 
+ *
+ * This register is used to disable chosen interrupts for an QSPI device.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * QSPI Interrupt Mask register. Write only.
+ *
+ * QSPI Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled interrupts of an QSPI device.
+ * Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Channel Interrupt Status Register
+ * @{
+ */
+
+#define XQSPIPS_IXR_TXUF_MASK	   0x00000040  /**< QSPI Tx FIFO Underflow */
+#define XQSPIPS_IXR_RXFULL_MASK    0x00000020  /**< QSPI Rx FIFO Full */
+#define XQSPIPS_IXR_RXNEMPTY_MASK  0x00000010  /**< QSPI Rx FIFO Not Empty */
+#define XQSPIPS_IXR_TXFULL_MASK    0x00000008  /**< QSPI Tx FIFO Full */
+#define XQSPIPS_IXR_TXOW_MASK	   0x00000004  /**< QSPI Tx FIFO Overwater */
+#define XQSPIPS_IXR_RXOVR_MASK	   0x00000001  /**< QSPI Rx FIFO Overrun */
+#define XQSPIPS_IXR_DFLT_MASK	   0x00000025  /**< QSPI default interrupts
+						    mask */
+#define XQSPIPS_IXR_WR_TO_CLR_MASK 0x00000041  /**< Interrupts which
+						    need write to clear */
+#define XQSPIPS_ISR_RESET_STATE    0x00000004  /**< Default to tx/rx empty */
+#define XQSPIPS_IXR_DISABLE_ALL    0x0000007D  /**< Disable all interrupts */
+/* @} */
+
+
+/** @name Enable Register
+ *
+ * This register is used to enable or disable an QSPI device.
+ * Read/Write
+ * @{
+ */
+#define XQSPIPS_ER_ENABLE_MASK    0x00000001 /**< QSPI Enable Bit Mask */
+/* @} */
+
+
+/** @name Delay Register
+ *
+ * This register is used to program timing delays in
+ * slave mode. Read/Write
+ * @{
+ */
+#define XQSPIPS_DR_NSS_MASK	0xFF000000 /**< Delay to de-assert slave select
+						between two words mask */
+#define XQSPIPS_DR_NSS_SHIFT	24	   /**< Delay to de-assert slave select
+						between two words shift */
+#define XQSPIPS_DR_BTWN_MASK	0x00FF0000 /**< Delay Between Transfers
+						mask */
+#define XQSPIPS_DR_BTWN_SHIFT	16	   /**< Delay Between Transfers shift */
+#define XQSPIPS_DR_AFTER_MASK	0x0000FF00 /**< Delay After Transfers mask */
+#define XQSPIPS_DR_AFTER_SHIFT	8 	   /**< Delay After Transfers shift */
+#define XQSPIPS_DR_INIT_MASK	0x000000FF /**< Delay Initially mask */
+/* @} */
+
+/** @name Slave Idle Count Registers
+ *
+ * This register defines the number of pclk cycles the slave waits for a the
+ * QSPI clock to become stable in quiescent state before it can detect the start
+ * of the next transfer in CPHA = 1 mode.
+ * Read/Write
+ *
+ * @{
+ */
+#define XQSPIPS_SICR_MASK	0x000000FF /**< Slave Idle Count Mask */
+/* @} */
+
+
+/** @name Transmit FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Transmit FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_TXWR_MASK           0x0000003F /**< Transmit Watermark Mask */
+#define XQSPIPS_TXWR_RESET_VALUE    0x00000001 /**< Transmit Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name Receive FIFO Watermark Register
+ *
+ * This register defines the watermark setting for the Receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_RXWR_MASK	    0x0000003F /**< Receive Watermark Mask */
+#define XQSPIPS_RXWR_RESET_VALUE    0x00000001 /**< Receive Watermark
+						  * register reset value */
+
+/* @} */
+
+/** @name FIFO Depth
+ *
+ * This macro provides the depth of transmit FIFO and receive FIFO.
+ *
+ * @{
+ */
+#define XQSPIPS_FIFO_DEPTH	63	/**< FIFO depth (words) */
+/* @} */
+
+
+/** @name Linear QSPI Configuration Register
+ *
+ * This register contains various control bits that
+ * affect the operation of the Linear QSPI controller. Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_CR_LINEAR_MASK	 0x80000000 /**< LQSPI mode enable */
+#define XQSPIPS_LQSPI_CR_TWO_MEM_MASK	 0x40000000 /**< Both memories or one */
+#define XQSPIPS_LQSPI_CR_SEP_BUS_MASK	 0x20000000 /**< Seperate memory bus */
+#define XQSPIPS_LQSPI_CR_U_PAGE_MASK	 0x10000000 /**< Upper memory page */
+#define XQSPIPS_LQSPI_CR_MODE_EN_MASK	 0x02000000 /**< Enable mode bits */
+#define XQSPIPS_LQSPI_CR_MODE_ON_MASK	 0x01000000 /**< Mode on */
+#define XQSPIPS_LQSPI_CR_MODE_BITS_MASK  0x00FF0000 /**< Mode value for dual I/O
+							 or quad I/O */
+#define XQSPIPS_LQSPI_CR_DUMMY_MASK	 0x00000700 /**< Number of dummy bytes
+							 between addr and return
+							 read data */
+#define XQSPIPS_LQSPI_CR_INST_MASK	 0x000000FF /**< Read instr code */
+#define XQSPIPS_LQSPI_CR_RST_STATE	 0x8000016B /**< Default CR value */
+/* @} */
+
+/** @name Linear QSPI Status Register
+ *
+ * This register contains various status bits of the Linear QSPI controller.
+ * Read/Write.
+ *
+ * @{
+ */
+#define XQSPIPS_LQSPI_SR_D_FSM_ERR_MASK	  0x00000004 /**< AXI Data FSM Error
+							  received */
+#define XQSPIPS_LQSPI_SR_WR_RECVD_MASK	  0x00000002 /**< AXI write command
+							  received */
+/* @} */
+
+
+/** @name Loopback Delay Adjust Register
+ *
+ * This register contains various bit masks of Loopback Delay Adjust Register.
+ *
+ * @{
+ */
+
+#define XQSPIPS_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 /**< Loopback Bit */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Register offsets from SLCR base address.
+ *
+ * @{
+ */
+
+#define SLCR_LOCK 0x00000004 /**< SLCR Write Protection Lock */
+#define SLCR_UNLOCK 0x00000008 /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL 0x00000230 /**< Quad SPI Software Reset Control */
+#define SLCR_LOCKSTA 0x0000000C /**< SLCR Write Protection status */
+
+/* @} */
+
+
+/** @name SLCR Register
+ *
+ * Bit Masks of above SLCR Registers .
+ *
+ * @{
+ */
+
+#ifndef XPAR_XSLCR_0_BASEADDR
+#define XPAR_XSLCR_0_BASEADDR 0xF8000000
+#endif
+#define SLCR_LOCK_MASK 0x767B /**< Write Protection Lock mask*/
+#define SLCR_UNLOCK_MASK 0xDF0D /**< SLCR Write Protection Unlock */
+#define LQSPI_RST_CTRL_MASK 0x3 /**< Quad SPI Software Reset Control */
+
+/* @} */
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPs_In32 Xil_In32
+#define XQspiPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XQspiPs_ReadReg(BaseAddress, RegOffset) \
+	XQspiPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XQspiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Functions implemented in xqspips_hw.c
+ */
+void XQspiPs_ResetHw(u32 BaseAddress);
+void XQspiPs_LinearInit(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
new file mode 100644
index 0000000..1cd43f4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c
@@ -0,0 +1,430 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_options.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* Contains functions for the configuration of the XQspiPs driver component.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.00a kka 07/25/12 Removed the selection for the following options:
+*		     Master mode (XQSPIPS_MASTER_OPTION) and
+*		     Flash interface mode (XQSPIPS_FLASH_MODE_OPTION) option
+*		     as the QSPI driver supports the Master mode
+*		     and Flash Interface mode. The driver doesnot support
+*		     Slave mode or the legacy mode.
+* 		     Added the option for setting the Holdb_dr bit in the
+*		     configuration options, XQSPIPS_HOLD_B_DRIVE_OPTION
+*		     is the option to be used for setting this bit in the
+*		     configuration register.
+* 2.01a sg  02/03/13 SetDelays and GetDelays API's include DelayNss parameter.
+*
+* 2.02a hk  26/03/13 Removed XQspi_Reset() in Set_Options() function when
+*			 LQSPI_MODE_OPTION is set. Moved Enable() to XQpsiPs_LqspiRead().
+* 3.3   sk  11/07/15 Modified the API prototypes according to MISRAC standards
+*                    to remove compilation warnings. CR# 868893.
+*
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+	{XQSPIPS_CLK_ACTIVE_LOW_OPTION, XQSPIPS_CR_CPOL_MASK},
+	{XQSPIPS_CLK_PHASE_1_OPTION, XQSPIPS_CR_CPHA_MASK},
+	{XQSPIPS_FORCE_SSELECT_OPTION, XQSPIPS_CR_SSFORCE_MASK},
+	{XQSPIPS_MANUAL_START_OPTION, XQSPIPS_CR_MANSTRTEN_MASK},
+	{XQSPIPS_HOLD_B_DRIVE_OPTION, XQSPIPS_CR_HOLD_B_MASK},
+};
+
+#define XQSPIPS_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPI device driver. The options control
+* how the device behaves relative to the QSPI bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained in
+*		the mask. See the bit definitions named XQSPIPS_*_OPTIONS in
+*		the file xqspips.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetOptions(XQspiPs *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	unsigned int Index;
+	u32 QspiOptions;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	QspiOptions = Options & XQSPIPS_LQSPI_MODE_OPTION;
+	Options &= ~XQSPIPS_LQSPI_MODE_OPTION;
+
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+		if (Options & OptionsTable[Index].Option) {
+			/* Turn it on */
+			ConfigReg |= OptionsTable[Index].Mask;
+		} else {
+			/* Turn it off */
+			ConfigReg &= ~(OptionsTable[Index].Mask);
+		}
+	}
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
+			 ConfigReg);
+
+	/*
+	 * Check for the LQSPI configuration options.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_LQSPI_CR_OFFSET);
+
+
+	if (QspiOptions & XQSPIPS_LQSPI_MODE_OPTION) {
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_LQSPI_CR_OFFSET,
+				  XQSPIPS_LQSPI_CR_RST_STATE);
+		XQspiPs_SetSlaveSelect(InstancePtr);
+	} else {
+		ConfigReg &= ~XQSPIPS_LQSPI_CR_LINEAR_MASK;
+		XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPS_LQSPI_CR_OFFSET, ConfigReg);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPI device. The options control how
+* the device behaves relative to the QSPI bus.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPS_*_OPTIONS in file xqspips.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XQspiPs_GetOptions(XQspiPs *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ConfigReg;
+	unsigned int Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the current options from QSPI configuration register.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to grab options
+	 */
+	for (Index = 0; Index < XQSPIPS_NUM_OPTIONS; Index++) {
+		if (ConfigReg & OptionsTable[Index].Mask) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	/*
+	 * Check for the LQSPI configuration options.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_LQSPI_CR_OFFSET);
+
+	if ((ConfigReg & XQSPIPS_LQSPI_CR_LINEAR_MASK) != 0) {
+		OptionsFlag |= XQSPIPS_LQSPI_MODE_OPTION;
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the clock prescaler for an QSPI device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	Prescaler is the value that determine how much the clock should
+*		be divided by. Use the XQSPIPS_CLK_PRESCALE_* constants defined
+*		in xqspips.h for this setting.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPs_SetClkPrescaler(XQspiPs *InstancePtr, u8 Prescaler)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Prescaler <= XQSPIPS_CR_PRESC_MAXIMUM);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/*
+	 * Read the configuration register, mask out the interesting bits, and set
+	 * them with the shifted value passed into the function. Write the
+	 * results back to the configuration register.
+	 */
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	ConfigReg &= ~XQSPIPS_CR_PRESC_MASK;
+	ConfigReg |= (u32) (Prescaler & XQSPIPS_CR_PRESC_MAXIMUM) <<
+			    XQSPIPS_CR_PRESC_SHIFT;
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_CR_OFFSET,
+			  ConfigReg);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the clock prescaler of an QSPI device.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+*
+******************************************************************************/
+u8 XQspiPs_GetClkPrescaler(XQspiPs *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPS_CR_OFFSET);
+
+	ConfigReg &= XQSPIPS_CR_PRESC_MASK;
+
+	return (u8)(ConfigReg >> XQSPIPS_CR_PRESC_SHIFT);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the delay register for the QSPI device driver.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0. The range of
+* each delay value is 0-255.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	DelayNss is the delay to de-assert slave select between
+*		two word transfers.
+* @param	DelayBtwn is the delay between one Slave Select being
+*		de-activated and the activation of another slave. The delay is
+*		the number of master clock periods given by DelayBtwn + 2.
+* @param	DelayAfter define the delay between the last bit of the current
+*		byte transfer and the first bit of the next byte transfer.
+*		The delay in number of master clock periods is given as:
+*		CHPA=0:DelayInit+DelayAfter+3
+*		CHPA=1:DelayAfter+1
+* @param	DelayInit is the delay between asserting the slave select signal
+*		and the first bit transfer. The delay int number of master clock
+*		periods is DelayInit+1.
+*
+* @return
+*		- XST_SUCCESS if delays are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_SetDelays(XQspiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
+			 u8 DelayAfter, u8 DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow the delays to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy) {
+		return XST_DEVICE_BUSY;
+	}
+
+	/* Shift, Mask and OR the values to build the register settings */
+	DelayRegister = (u32) DelayNss << XQSPIPS_DR_NSS_SHIFT;
+	DelayRegister |= (u32) DelayBtwn << XQSPIPS_DR_BTWN_SHIFT;
+	DelayRegister |= (u32) DelayAfter << XQSPIPS_DR_AFTER_SHIFT;
+	DelayRegister |= (u32) DelayInit;
+
+	XQspiPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XQSPIPS_DR_OFFSET, DelayRegister);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the delay settings for an QSPI device.
+* The delay register controls the Delay Between Transfers, Delay After
+* Transfers, and the Delay Initially. The default value is 0x0.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+* @param	DelayNss is a pointer to the Delay to de-assert slave select
+*		between two word transfers.
+* @param	DelayBtwn is a pointer to the Delay Between transfers value.
+*		This is a return parameter.
+* @param	DelayAfter is a pointer to the Delay After transfer value.
+*		This is a return parameter.
+* @param	DelayInit is a pointer to the Delay Initially value. This is
+*		a return parameter.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPs_GetDelays(XQspiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
+			 u8 *DelayAfter, u8 *DelayInit)
+{
+	u32 DelayRegister;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	DelayRegister = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XQSPIPS_DR_OFFSET);
+
+	*DelayInit = (u8)(DelayRegister & XQSPIPS_DR_INIT_MASK);
+
+	*DelayAfter = (u8)((DelayRegister & XQSPIPS_DR_AFTER_MASK) >>
+			   XQSPIPS_DR_AFTER_SHIFT);
+
+	*DelayBtwn = (u8)((DelayRegister & XQSPIPS_DR_BTWN_MASK) >>
+			  XQSPIPS_DR_BTWN_SHIFT);
+
+	*DelayNss = (u8)((DelayRegister & XQSPIPS_DR_NSS_MASK) >>
+			  XQSPIPS_DR_NSS_SHIFT);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
new file mode 100644
index 0000000..4c44cdf
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_selftest.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* This file contains the implementation of selftest function for the QSPI
+* device.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 2.01a sg  02/03/13 Delay Register test is added with DelayNss parameter.
+* 3.1   hk  06/19/14 Remove checks for CR and ISR register values as they are
+*                    reset in the previous step.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspips.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPs instance.
+*
+* @return
+* 		- XST_SUCCESS if successful
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly.
+*
+* @note		None.
+*
+******************************************************************************/
+int XQspiPs_SelfTest(XQspiPs *InstancePtr)
+{
+	int Status;
+	u8 DelayTestNss;
+	u8 DelayTestBtwn;
+	u8 DelayTestAfter;
+	u8 DelayTestInit;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Reset the QSPI device to leave it in a known good state
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	DelayTestNss = 0x5A;
+	DelayTestBtwn = 0xA5;
+	DelayTestAfter = 0xAA;
+	DelayTestInit = 0x55;
+
+	/*
+	 * Write and read the delay register, just to be sure there is some
+	 * hardware out there.
+	 */
+	Status = XQspiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
+				DelayTestAfter, DelayTestInit);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	XQspiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
+				&DelayTestAfter, &DelayTestInit);
+	if ((0x5A != DelayTestNss) || (0xA5 != DelayTestBtwn) ||
+		(0xAA != DelayTestAfter) || (0x55 != DelayTestInit)) {
+		return XST_REGISTER_ERROR;
+	}
+
+	Status = XQspiPs_SetDelays(InstancePtr, 0, 0, 0, 0);
+	if (Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	/*
+	 * Reset the QSPI device to leave it in a known good state
+	 */
+	XQspiPs_Reset(InstancePtr);
+
+	return XST_SUCCESS;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
new file mode 100644
index 0000000..929ecd8
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspips_sinit.c
+* @addtogroup qspips_v3_4
+* @{
+*
+* The implementation of the XQspiPs component's static initialization
+* functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.00  sdm 11/25/10 First release
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspips.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPs_Config XQspiPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspips.h for the definition of XQspiPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XQspiPs_Config *XQspiPs_LookupConfig(u16 DeviceId)
+{
+	XQspiPs_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XQSPIPS_NUM_INSTANCES; Index++) {
+		if (XQspiPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XQspiPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
new file mode 100644
index 0000000..f6afc0e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c
@@ -0,0 +1,1020 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+*		      		  "Config" entry is now made as pointer in the XScuGic
+*		      		  structure, necessary changes are made.
+*		      		  The HandlerTable can now be populated through the low
+*		      		  level routine XScuGic_RegisterHandler added in this
+*		      		  release. Hence necessary checks are added not to
+*		      		  overwrite the HandlerTable entriesin function
+*		      		  XScuGic_CfgInitialize.
+* 1.03a srt  02/27/13 Added APIs
+*					  - XScuGic_SetPriTrigTypeByDistAddr()
+*					  - XScuGic_GetPriTrigTypeByDistAddr()
+* 		    		  Removed Offset calculation macros, defined in _hw.h
+*		      		  (CR 702687)
+*			  		  Added support to direct interrupts to the appropriate CPU. Earlier
+*			  		  interrupts were directed to CPU1 (hard coded). Now depending
+*			  		  upon the CPU selected by the user (xparameters.h), interrupts
+*			  		  will be directed to the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  		  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  		  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             		  XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  		  This is fix for CR#705621.
+* 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+*			  		  in function XScuGic_CfgInitialize is removed as it was
+*		      		  a bug.
+* 3.00  kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+*			  		  target CPU mapping
+* 3.02	pkp	 11/09/15 Modified DistributorInit function for AMP case to add
+*					  the current cpu to interrupt processor targets registers
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  		  distributor is left uninitialized for Zynq AMP. It is assumed
+*             		  that the distributor will be initialized by Linux master. However
+*             		  for CortexR5 case, the earlier code is left unchanged where the
+*             		  the interrupt processor target registers in the distributor is
+*             		  initialized with the corresponding CPU ID on which the application
+*             		  built over the scugic driver runs.
+*             		  These changes fix CR#937243.
+* 3.3	pkp  05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value
+*					  to interrupt target register to fix CR#951848
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*                     the flow and avoid code duplication. Changes are made for
+*                     USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*                     one R5 is operating with A53 in open amp config and other
+*                     R5 running baremetal app, the existing code
+*                     had the potential to stop the whole AMP solution to work (if
+*                     for some reason the R5 running the baremetal app tasked to
+*                     initialize the Distributor hangs or crashes before initializing).
+*                     Changes are made so that the R5 under AMP first checks if
+*                     the distributor is enabled or not and if not, it does the
+*                     standard Distributor initialization.
+*                     This fixes the CR#952962.
+* 3.4   mus  09/08/16 Added assert to avoid invalid access of GIC from CPUID 1
+*                     for single core zynq-7000s
+* 3.5   mus  10/05/16 Modified DistributorInit function to avoid re-initialization of
+*                     distributor,If it is already initialized by other CPU.
+* 3.5	pkp	 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value
+*					  and properly mask interrupt target processor value to modify
+*					  interrupt target processor register for a given interrupt ID
+*					  and cpu ID
+* 3.6	pkp	 20/01/17 Added new API XScuGic_Stop to Disable distributor and
+*					  interrupts in case they are being used only by current cpu.
+*					  It also removes current cpu from interrupt target registers
+*					  for all interrupts.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+* 3.9   mus  02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+*                     XScuGic_InterruptUnmapFromCpu, These API's can be used
+*                     by applications to unmap specific/all interrupts from
+*                     target CPU. It fixes CR#992490.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DoDistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for
+	 * non-secure interrupts
+	 * All are secure, so leave at the default. Set to 1 for non-secure
+	 * interrupts.
+	 */
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+16U) {
+		/*
+		 * Each INT_ID uses two bits, or 16 INT_ID per register
+		 * Set them all to be level sensitive, active HIGH.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+					0U);
+	}
+
+
+#define DEFAULT_PRIORITY    0xa0a0a0a0U
+	for (Int_Id = 0U; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id=Int_Id+4U) {
+		/*
+		 * 2. The priority using int the priority_level register
+		 * The priority_level and spi_target registers use one byte per
+		 * INT_ID.
+		 * Write a default value that can be changed elsewhere.
+		 */
+		XScuGic_DistWriteReg(InstancePtr,
+					XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_IdBaseAddress for this parameters, passing the physical
+*		address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr,
+				XScuGic_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 Int_Id;
+	u32 Cpu_Id = CpuId + (u32)1;
+	(void) EffectiveAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	/*
+     * Detect Zynq-7000 base silicon configuration,Dual or Single CPU.
+     * If it is single CPU cnfiguration then invoke assert for CPU ID=1
+	 */
+#ifdef ARMA9
+	if ( XPAR_CPU_ID == 0x01 )
+	{
+		Xil_AssertNonvoid((Xil_In32(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)
+		 & EFUSE_STATUS_CPU_MASK ) == 0);
+	}
+#endif
+
+	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+		InstancePtr->IsReady = 0U;
+		InstancePtr->Config = ConfigPtr;
+
+
+		for (Int_Id = 0U; Int_IdConfig->HandlerTable[Int_Id].Handler == NULL)) {
+				InstancePtr->Config->HandlerTable[Int_Id].Handler =
+									StubHandler;
+			}
+			InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+								InstancePtr;
+		}
+		XScuGic_Stop(InstancePtr);
+		DistributorInit(InstancePtr, Cpu_Id);
+		CPUInitialize(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return
+*
+*		- XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+                      Xil_InterruptHandler Handler, void *CallBackRef)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used as an index into the table to select the proper
+	 * handler
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param	Int_Id contains the ID of the interrupt source and should
+*		be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the interrupt such that it won't occur while disconnecting
+	 * the handler, only disable the specified interrupt id without modifying
+	 * the other interrupt ids
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+
+	/*
+	 * Disconnect the handler and connect a stub, the callback reference
+	 * must be set to this instance to allow unhandled interrupts to be
+	 * tracked
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Enable the selected interrupt source by setting the
+	 * corresponding bit in the Enable Set register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the selected interrupt source by setting the
+	 * corresponding bit in the IDR.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller.  This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode.  A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id is the software interrupt ID to simulate an interrupt.
+* @param	Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Int_Id <= 15U) ;
+	Xil_AssertNonvoid(Cpu_Id <= 255U) ;
+
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired interrupt. Int_Id currently limited to 0 - 15
+	 * Use the target list for the Cpu ID.
+	 */
+	Mask = ((Cpu_Id << 16U) | Int_Id) &
+		(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+	/*
+	 * Write to the Software interrupt trigger register. Use the appropriate
+	 * CPU Int_Id.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+	/* Indicate the interrupt was successfully simulated */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef) {
+	/*
+	 * verify that the inputs are valid
+	 */
+	Xil_AssertVoid(CallBackRef != NULL);
+
+	/*
+	 * Indicate another unhandled interrupt for stats
+	 */
+	((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority;
+	LocalPriority = Priority;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				RegValue);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cpu_Id is a CPU number for which the interrupt has to be targeted
+* @param	Int_Id is the IRQ source number to modify
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+	u32 RegValue, Offset;
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+	Offset = (Int_Id & 0x3U);
+	Cpu_Id = (0x1U << Cpu_Id);
+
+	RegValue = (RegValue & (~(0xFFU << (Offset*8U))) );
+	RegValue |= ((Cpu_Id) << (Offset*8U));
+
+	XScuGic_DistWriteReg(InstancePtr,
+						 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+						 RegValue);
+}
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cpu_Id is a CPU number from which the interrupt has to be
+*			unmapped
+* @param	Int_Id is the IRQ source number to modify
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+	u32 RegValue;
+	u8 BitPos;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Identify bit position corresponding to  Int_Id and Cpu_Id,
+	 * in interrupt target register and clear it
+	 */
+	BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
+	RegValue &= (~ ( 1U << BitPos ));
+	XScuGic_DistWriteReg(InstancePtr,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+				RegValue);
+}
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cpu_Id is a CPU number from which the interrupts has to be
+*			unmapped
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id)
+{
+	u32 Int_Id;
+	u32 Target_Cpu;
+	u32 LocalCpuID = (1U << Cpu_Id);
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	LocalCpuID |= LocalCpuID << 8U;
+	LocalCpuID |= LocalCpuID << 16U;
+
+	for (Int_Id = 32U; Int_IdInterrupt Vector Tables    
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs.  The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+* 3.4   asa  04/07/16 Created a new static function DoDistributorInit to simplify
+*            the flow and avoid code duplication. Changes are made for
+*            USE_AMP use case for R5. In a scenario (in R5 split mode) when
+*            one R5 is operating with A53 in open amp config and other
+*            R5 running baremetal app, the existing code
+*            had the potential to stop the whole AMP solution to work (if
+*            for some reason the R5 running the baremetal app tasked to
+*            initialize the Distributor hangs or crashes before initializing).
+*            Changes are made so that the R5 under AMP first checks if
+*            the distributor is enabled or not and if not, it does the
+*            standard Distributor initialization.
+*            This fixes the CR#952962.
+* 3.6   ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* 3.7   ms   04/11/17 Modified tcl file to add suffix U for all macro
+*                     definitions of scugic in xparameters.h
+* 3.8   mus  07/05/17 Updated scugic.tcl to add support for intrrupts connected
+*                     through util_reduced_vector IP(OR gate)
+*       mus  07/05/17 Updated xdefine_zynq_canonical_xpars proc to initialize
+*                     the HandlerTable in XScuGic_ConfigTable to 0, it removes
+*                     the compilation warning in xscugic_g.c. Fix for CR#978736.
+*       mus  07/25/17 Updated xdefine_gic_params proc to export correct canonical
+*                     definitions for pl to ps interrupts.Fix for CR#980534
+* 3.9   mus  02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and
+*                     XScuGic_InterruptUnmapFromCpu, These API's can be used
+*                     by applications to unmap specific/all interrupts from
+*                     target CPU.
+*
+* 
    
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+#define EFUSE_STATUS_OFFSET   0x10
+#define EFUSE_STATUS_CPU_MASK 0x80
+
+#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+#define ARMA9
+#endif
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+	Xil_InterruptHandler Handler;
+	void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
+	u32 DistBaseAddress;	/**< Distributor Register base address */
+	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+				 Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+	XScuGic_Config *Config;  /**< Configuration table entry */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+			Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+							u32 EffectiveAddr);
+
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id);
+void XScuGic_Stop(XScuGic *InstancePtr);
+void XScuGic_SetCpuID(u32 CpuCoreId);
+u32 XScuGic_GetCpuID(void);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32  XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
new file mode 100644
index 0000000..6765fd5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUGIC_0_DEVICE_ID,
+		XPAR_PS7_SCUGIC_0_BASEADDR,
+		XPAR_PS7_SCUGIC_0_DIST_BASEADDR,
+		{{0}}		/**< Initialize the HandlerTable to 0 */
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
new file mode 100644
index 0000000..6604e3a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c
@@ -0,0 +1,649 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm  07/18/11 First release
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+*					  Added support to direct interrupts to the appropriate CPU.
+*			  Earlier interrupts were directed to CPU1 (hard coded). Now
+*			  depending upon the CPU selected by the user (xparameters.h),
+*			  interrupts will be directed to the relevant CPU.
+*			  This fixes CR 699688.
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved functions
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6   kvn  02/17/17 Add support for changing GIC CPU master at run time.
+*       kvn  02/28/17 Make the CpuId as static variable and Added new
+*                     XScugiC_GetCpuId to access CpuId.
+* 3.9   mus  02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+*					  and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+*					  API's can be used by applications to unmap specific/all
+*					  interrupts from target CPU. It fixes CR#992490.
+*
+* 
    
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+extern u32 CpuId;
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for non-secure
+	 * interrupts. All are secure, so leave at the default. Set to 1 for
+	 * non-secure interrupts.
+	 */
+
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_IdDistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+	}
+
+
+#define DEFAULT_PRIORITY	0xa0a0a0a0U
+	for (Int_Id = 0U; Int_IdDistBaseAddress,
+				XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_IdDistBaseAddress,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+	}
+
+	for (Int_Id = 0U; Int_IdDistBaseAddress,
+		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+		Int_Id),
+		0xFFFFFFFFU);
+
+	}
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+						XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask
+	 * register
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+									0xF0U);
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+	 * interrupts Only enable the IRQ output unless secure interrupts
+	 * are needed.
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param ConfigPtr is a pointer to a config table for the particular device
+*        this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory address
+*        space. The caller is responsible for keeping the address mapping
+*        from EffectiveAddr to the device physical base address unchanged
+*        once this function is invoked. Unexpected errors may occur if the
+*        address mapping changes after this function is called. If address
+*        translation is not used, use Config->BaseAddress for this parameters,
+*        passing the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+	XScuGic_Config *Config;
+	u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1;
+
+	Config = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+	DistInit(Config, Cpu_Id);
+
+	CPUInit(Config);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param	DeviceId is the unique identifier for the ScuGic device.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+	u32 InterruptID;
+	u32 IntIDFull;
+	XScuGic_VectorTableEntry *TablePtr;
+	XScuGic_Config *CfgPtr;
+
+	CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
+
+	/*
+	 * Read the int_ack register to identify the highest priority
+	 * interrupt ID and make sure it is valid. Reading Int_Ack will
+	 * clear the interrupt in the GIC.
+	 */
+	IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
+	InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+	if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	}
+
+	/*
+	 * If the interrupt is shared, do some locking here if there are
+	 * multiple processors.
+	 */
+	/*
+	 * If pre-eption is required:
+	 * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	 * interrupts or the F bit for secure interrupts
+	 */
+
+	/*
+	 * If we need to change security domains, issue a SMC instruction here.
+	 */
+
+	/*
+	 * Execute the ISR. Jump into the Interrupt service routine based on
+	 * the IRQSource. A software trigger is cleared by the ACK.
+	 */
+	TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+	if(TablePtr != NULL) {
+		TablePtr->Handler(TablePtr->CallBackRef);
+	}
+
+IntrExit:
+	/*
+	 * Write to the EOI register, we are all done here.
+	 * Let this function return, the boot code will restore the stack.
+	 */
+	XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	/*
+	 * Return from the interrupt. Change security domains could happen
+	 * here.
+	 */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID.  The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param	BaseAddress is the CPU Interface Register base address of the
+*		interrupt controller whose vector table will be modified.
+* @param	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param	Handler is the function pointer that will be added to
+*		the vector table for the given interrupt ID.
+* @param	CallBackRef is the argument that will be passed to the new
+*		handler function when it is called. This is user-specific.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+	XScuGic_Config *CfgPtr;
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+	if(CfgPtr != NULL) {
+		if( IntrHandler != NULL) {
+			CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
+		}
+		if( CallBackRef != NULL) {
+			CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param	CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return 	A pointer to the configuration structure for the specified
+*		device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+				CpuBaseAddress) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_SetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority = Priority;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					RegValue);
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_GetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+
+/****************************************************************************/
+/**
+* Unmaps specific SPI interrupt from the target CPU
+*
+* @param	DistBaseAddress is the device base address
+* @param	Cpu_Id is a CPU number from which the interrupt has to be
+*			unmapped
+* @param	Int_Id is the IRQ source number to modify
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+											 u8 Cpu_Id, u32 Int_Id)
+{
+	u32 RegValue;
+	u8 BitPos;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Identify bit position corresponding to  Int_Id and Cpu_Id,
+	 * in interrupt target register and clear it
+	 */
+	BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id;
+	RegValue &= (~ ( 1U << BitPos ));
+	XScuGic_WriteReg(DistBaseAddress,
+			XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue);
+}
+
+/****************************************************************************/
+/**
+* Unmaps all SPI interrupts from the target CPU
+*
+* @param	DistBaseAddress is the device base address
+* @param	Cpu_Id is a CPU number from which the interrupts has to be
+*			unmapped
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+												 u8 Cpu_Id)
+{
+	u32 Int_Id;
+	u32 Target_Cpu;
+	u32 LocalCpuID = (1U << Cpu_Id);
+
+	LocalCpuID |= LocalCpuID << 8U;
+	LocalCpuID |= LocalCpuID << 16U;
+
+	for (Int_Id = 32U; Int_Id
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
+*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 3.9   mus  02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr
+*					  and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These
+*					  API's can be used by applications to unmap specific/all
+*					  interrupts from target CPU. It fixes CR#992490.
+* 
    
+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
+#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
+							Register */
+#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
+							Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
+							Register */
+#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
+							Register */
+#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
+							Register */
+#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
+							Register */
+#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
+							Register */
+#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
+							Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
+							Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
+							0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
+							Register */
+#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
+							Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name  Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name  Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
+						Shared Peripheral
+						Interrupts*/
+#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name  Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name  Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080.  A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
+					      INT_ID */
+/* @} */
+
+/** @name  Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
+						INT_ID */
+#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
+						actually the lowest priority*/
+/* @} */
+
+/** @name  SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK	0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name  Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI    Read Only    b10 always
+ * PPI    Read Only    depending on how the PPIs are configured.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive
+ * SPI                LSB is read only.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
+/* @} */
+
+/** @name  PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
+/* @} */
+
+/** @name  SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
+					     input */
+/* @} */
+
+/** @name  AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
+                                                  1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
+                                                  1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name  Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
+                                                            b00-Use the target List
+                                                            b01-All CPUs except requester
+                                                            b10-To Requester
+                                                            b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
+                                                        signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
+							Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
+							Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
+						        Binary Point Register */
+
+/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
+                                                 0=separate registers,
+                                                 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
+                                                  interrupts,
+                                                  0= use IRQ for both,
+                                                  1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
+						Value  Secure  Non-secure
+						b000    0xFE    0xFF
+						b001    0xFC    0xFE
+						b010    0xF8    0xFC
+						b011    0xF0    0xF8
+						b100    0xE0    0xF0
+						b101    0xC0    0xE0
+						b110    0x80    0xC0
+						b111    0x00    0x80
+						*/
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param	Register is the register offset for the clear/enable bank.
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+		((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32  XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+                                        u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress,
+											u8 Cpu_Id, u32 Int_Id);
+void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress,
+												u8 Cpu_Id);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
new file mode 100644
index 0000000..d82a60b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller.  The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing.  This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported.  This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system.  The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 XScuGic_InterruptHandler has changed correspondingly
+*		      since the HandlerTable has now moved to XScuGic_Config.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 
    
+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+	u32 InterruptID;
+	    u32 IntIDFull;
+	    XScuGic_VectorTableEntry *TablePtr;
+
+	    /* Assert that the pointer to the instance is valid
+	     */
+	    Xil_AssertVoid(InstancePtr != NULL);
+
+	    /*
+	     * Read the int_ack register to identify the highest priority interrupt ID
+	     * and make sure it is valid. Reading Int_Ack will clear the interrupt
+	     * in the GIC.
+	     */
+	    IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+	    InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+	    if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	    }
+
+	    /*
+	     * If the interrupt is shared, do some locking here if there are multiple
+	     * processors.
+	     */
+	    /*
+	     * If pre-eption is required:
+	     * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	     * interrupts or the F bit for secure interrupts
+	     */
+
+	    /*
+	     * If we need to change security domains, issue a SMC instruction here.
+	     */
+
+	    /*
+	     * Execute the ISR. Jump into the Interrupt service routine based on the
+	     * IRQSource. A software trigger is cleared by the ACK.
+	     */
+	    TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+		if(TablePtr != NULL) {
+	        TablePtr->Handler(TablePtr->CallBackRef);
+		}
+
+	IntrExit:
+	    /*
+	     * Write to the EOI register, we are all done here.
+	     * Let this function return, the boot code will restore the stack.
+	     */
+	    XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	    /*
+	     * Return from the interrupt. Change security domains could happen here.
+     */
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
new file mode 100644
index 0000000..7b1028f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define	XSCUGIC_PCELL_ID	0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* 		- XST_SUCCESS if self-test is successful.
+* 		- XST_FAILURE if the self-test is not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+	u32 RegValue1 = 0U;
+	u32 Index;
+	s32 Status;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ID registers.
+	 */
+	for(Index=0U; Index<=3U; Index++) {
+		RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+			((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
+	}
+
+	if(XSCUGIC_PCELL_ID != RegValue1){
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
new file mode 100644
index 0000000..842f318
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v3_8
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique identifier for a device.
+*
+* @return	A pointer to the XScuGic configuration structure for the
+*		specified device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
new file mode 100644
index 0000000..9d477d9
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.c
@@ -0,0 +1,286 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the SCU Timer driver.
+* See xscutimer.h for a description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific timer instance/driver. This function  must be called
+* before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	ConfigPtr points to the XScuTimer configuration structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			 XScuTimer_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) {
+		/*
+		 * Copy configuration into the instance structure.
+		 */
+		InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+		/*
+		 * Save the base address pointer such that the registers of the block
+		 * can be accessed and indicate it has not been started yet.
+		 */
+		InstancePtr->Config.BaseAddr = EffectiveAddress;
+
+		InstancePtr->IsStarted = (u32)0;
+
+		/*
+		 * Indicate the instance is ready to use, successfully initialized.
+		 */
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		Status =(s32)XST_SUCCESS;
+	}
+	else {
+		Status = (s32)XST_DEVICE_IS_STARTED;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the timer.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuTimer_Start(XScuTimer *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Set the 'timer enable' bit in the register.
+	 */
+	Register |= XSCUTIMER_CONTROL_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the timer.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuTimer_Stop(XScuTimer *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Clear the 'timer enable' bit in the register.
+	 */
+	Register &= (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is stopped.
+	 */
+	InstancePtr->IsStarted = (u32)0;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler bits in the timer control register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	PrescalerValue is a 8 bit value that sets the prescaler to use.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue)
+{
+	u32 ControlReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	/*
+	 * Read the Timer control register.
+	 */
+	ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+					XSCUTIMER_CONTROL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register.
+	 */
+	ControlReg &= (u32)(~XSCUTIMER_CONTROL_PRESCALER_MASK);
+
+	/*
+	 * Set the prescaler value.
+	 */
+	ControlReg |= (((u32)PrescalerValue) << XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			  XSCUTIMER_CONTROL_OFFSET, ControlReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current prescaler value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	The prescaler value.
+*
+* @note		None.
+*
+****************************************************************************/
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr)
+{
+	u32 ControlReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Timer control register.
+	 */
+	ControlReg = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				    XSCUTIMER_CONTROL_OFFSET);
+	ControlReg &= XSCUTIMER_CONTROL_PRESCALER_MASK;
+
+	return (u8)(ControlReg >> XSCUTIMER_CONTROL_PRESCALER_SHIFT);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
new file mode 100644
index 0000000..ea4ba79
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer.h
+* @addtogroup scutimer_v2_1
+* @{
+* @details
+*
+* The timer driver supports the Cortex A9 private timer.
+*
+* The timer driver supports the following features:
+* - Normal mode and Auto reload mode
+* - Interrupts (Interrupt handler is not provided in this driver. Application
+* 		has to register it's own handler)
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Timer.
+*
+* XScuTimer_CfgInitialize() API is used to initialize the Timer. The
+* user needs to first call the XScuTimer_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuTimer_CfgInitialize() API.
+*
+*  Interrupts 
+*
+* The Timer hardware supports interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*  Building the driver 
+*
+* The XScuTimer driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* 

    
+*
+* NOTE:
+* The timer is not a part of the snoop control unit as indicated by the
+* prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.02a sg  07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* 
    
+*
+******************************************************************************/
+#ifndef XSCUTIMER_H		/* prevent circular inclusions */
+#define XSCUTIMER_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscutimer_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	/**< Unique ID of device */
+	u32 BaseAddr;	/**< Base address of the device */
+} XScuTimer_Config;
+
+/**
+ * The XScuTimer driver instance data. The user is required to allocate a
+ * variable of this type for every timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuTimer_Config Config; /**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device timer is running */
+} XScuTimer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Check if the timer has expired.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- TRUE if the timer has expired.
+*		- FALSE if the timer has not expired.
+*
+* @note		C-style signature:
+*		int XScuTimer_IsExpired(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_IsExpired(InstancePtr) \
+	((XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_ISR_OFFSET) & \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK) == \
+				XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the timer. This macro will read the timer load register
+* and writes the same value to load register to update the counter register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_RestartTimer(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_RestartTimer(InstancePtr)				\
+	XScuTimer_LoadTimer((InstancePtr),				\
+		XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_LOAD_OFFSET))
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_LoadTimer(XScuTimer *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_LoadTimer(InstancePtr, Value)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value. It can be called at any
+* time.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterValue(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterValue(InstancePtr)				\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+				XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableAutoReload(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) |		 \
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableAutoReload(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableAutoReload(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_AUTO_RELOAD_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Enable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_EnableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_EnableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+					XSCUTIMER_CONTROL_OFFSET) |	\
+					XSCUTIMER_CONTROL_IRQ_ENABLE_MASK))
+
+/****************************************************************************/
+/**
+*
+* Disable the Timer interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_DisableInterrupt(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_DisableInterrupt(InstancePtr)				\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_CONTROL_OFFSET,			\
+			(XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr, \
+				XSCUTIMER_CONTROL_OFFSET) &		\
+				~(XSCUTIMER_CONTROL_IRQ_ENABLE_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_GetInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_GetInterruptStatus(InstancePtr)			\
+	XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUTIMER_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_ClearInterruptStatus(XScuTimer *InstancePtr)
+*
+******************************************************************************/
+#define XScuTimer_ClearInterruptStatus(InstancePtr)			\
+	XScuTimer_WriteReg((InstancePtr)->Config.BaseAddr,		\
+		XSCUTIMER_ISR_OFFSET, XSCUTIMER_ISR_EVENT_FLAG_MASK)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscutimer_sinit.c
+ */
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscutimer_selftest.c
+ */
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr);
+
+/*
+ * Interface functions in xscutimer.c
+ */
+s32 XScuTimer_CfgInitialize(XScuTimer *InstancePtr,
+			    XScuTimer_Config *ConfigPtr, u32 EffectiveAddress);
+void XScuTimer_Start(XScuTimer *InstancePtr);
+void XScuTimer_Stop(XScuTimer *InstancePtr);
+void XScuTimer_SetPrescaler(XScuTimer *InstancePtr, u8 PrescalerValue);
+u8 XScuTimer_GetPrescaler(XScuTimer *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
new file mode 100644
index 0000000..6ccfa91
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscutimer.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUTIMER_0_DEVICE_ID,
+		XPAR_PS7_SCUTIMER_0_BASEADDR
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
new file mode 100644
index 0000000..ac7b429
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_hw.h
@@ -0,0 +1,287 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_hw.h
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains the hardware interface to the Timer.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 1.01a sdm 02/02/12 Added low level macros to read/write load, counter, control
+*		     and interrupt registers
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+#ifndef XSCUTIMER_HW_H		/* prevent circular inclusions */
+#define XSCUTIMER_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XSCUTIMER_LOAD_OFFSET		0x00U /**< Timer Load Register */
+#define XSCUTIMER_COUNTER_OFFSET	0x04U /**< Timer Counter Register */
+#define XSCUTIMER_CONTROL_OFFSET	0x08U /**< Timer Control Register */
+#define XSCUTIMER_ISR_OFFSET		0x0CU /**< Timer Interrupt
+						  Status Register */
+/* @} */
+
+/** @name Timer Control register
+ * This register bits control the prescaler, Intr enable,
+ * auto-reload and timer enable.
+ * @{
+ */
+
+#define XSCUTIMER_CONTROL_PRESCALER_MASK	0x0000FF00U /**< Prescaler */
+#define XSCUTIMER_CONTROL_PRESCALER_SHIFT	8U
+#define XSCUTIMER_CONTROL_IRQ_ENABLE_MASK	0x00000004U /**< Intr enable */
+#define XSCUTIMER_CONTROL_AUTO_RELOAD_MASK	0x00000002U /**< Auto-reload */
+#define XSCUTIMER_CONTROL_ENABLE_MASK		0x00000001U /**< Timer enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Timer counter register has reached zero.
+ * @{
+ */
+
+#define XSCUTIMER_ISR_EVENT_FLAG_MASK		0x00000001U /**< Event flag */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetLoadReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetLoadReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+*		u32 XScuTimer_GetLoadReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetLoadReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_LOAD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetCounterReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetCounterReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetCounterReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetCounterReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_COUNTER_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer load register. This will also update the
+* timer counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetControlReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetControlReg(BaseAddr, Value)			\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer load register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer load register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetControlReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetControlReg(BaseAddr)				\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the timer counter register.
+*
+* @param	BaseAddr is the base address of the scu timer.
+* @param	Value is the count to be loaded in to the counter register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_SetIntrReg(u32 BaseAddr, u32 Value)
+*
+******************************************************************************/
+#define XScuTimer_SetIntrReg(BaseAddr, Value)				\
+	XScuTimer_WriteReg(BaseAddr, XSCUTIMER_ISR_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Returns the current timer counter register value.
+*
+* @param	BaseAddr is the base address of the scu timer.
+*
+* @return	Contents of the timer counter register.
+*
+* @note		C-style signature:
+		u32 XScuTimer_GetIntrReg(u32 BaseAddr)
+*
+******************************************************************************/
+#define XScuTimer_GetIntrReg(BaseAddr)					\
+	XScuTimer_ReadReg(BaseAddr, XSCUTIMER_ISR_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Read from the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuTimer_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuTimer_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write to the given Timer register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuTimer_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuTimer_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + (RegOffset), (Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
new file mode 100644
index 0000000..6e37fef
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_selftest.c
@@ -0,0 +1,139 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscutimer_selftest.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuTimer driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XSCUTIMER_SELFTEST_VALUE	0xA55AF00FU
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timer. This test clears the timer enable bit in
+* the control register, writes to the timer load register and verifies the
+* value read back matches the value written and restores the control register
+* and the timer load register.
+*
+* @param	InstancePtr is a pointer to the XScuTimer instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if self test was not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuTimer_SelfTest(XScuTimer *InstancePtr)
+{
+	u32 Register;
+	u32 CtrlOrig;
+	u32 LoadOrig;
+	s32 Status;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Save the contents of the Control Register and stop the timer.
+	 */
+	CtrlOrig = XScuTimer_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUTIMER_CONTROL_OFFSET);
+	Register = CtrlOrig & (u32)(~XSCUTIMER_CONTROL_ENABLE_MASK);
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, Register);
+
+	/*
+	 * Save the contents of the Load Register.
+	 * Load a new test value in the Load Register, read it back and
+	 * compare it with the written value.
+	 */
+	LoadOrig = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+				  XSCUTIMER_LOAD_OFFSET);
+	XScuTimer_LoadTimer(InstancePtr, XSCUTIMER_SELFTEST_VALUE);
+	Register = XScuTimer_ReadReg((InstancePtr)->Config.BaseAddr,
+				  XSCUTIMER_LOAD_OFFSET);
+
+	/*
+	 * Restore the contents of the Load Register and Control Register.
+	 */
+	XScuTimer_LoadTimer(InstancePtr, LoadOrig);
+	XScuTimer_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUTIMER_CONTROL_OFFSET, CtrlOrig);
+
+	/*
+	 * Return a Failure if the contents of the Load Register do not
+	 * match with the value written to it.
+	 */
+	if (Register != XSCUTIMER_SELFTEST_VALUE) {
+		Status = (s32)XST_FAILURE;
+	}
+	else {
+		Status = (s32)XST_SUCCESS;
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
new file mode 100644
index 0000000..3bcc57e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscutimer_sinit.c
+* @addtogroup scutimer_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a nm  03/10/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscutimer.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions ****************************/
+extern XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuTimer_Config *XScuTimer_LookupConfig(u16 DeviceId)
+{
+	XScuTimer_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_XSCUTIMER_NUM_INSTANCES; Index++) {
+		if (XScuTimer_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuTimer_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuTimer_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
new file mode 100644
index 0000000..cd9e15d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c
@@ -0,0 +1,217 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains the implementation of interface functions of the XScuWdt driver.
+* See xscuwdt.h for a description of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ConfigPtr is the config structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		This function enables the watchdog mode.
+*
+******************************************************************************/
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			 XScuWdt_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	s32 CfgStatus;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddress != 0x00U);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		CfgStatus = (s32)XST_DEVICE_IS_STARTED;
+	}
+	else {
+		/*
+		 * Copy configuration into instance.
+		 */
+		InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+		/*
+		 * Save the base address pointer such that the registers of the block
+		 * can be accessed and indicate it has not been started yet.
+		 */
+		InstancePtr->Config.BaseAddr = EffectiveAddress;
+		InstancePtr->IsStarted = 0U;
+
+		/*
+		 * Put the watchdog timer in Watchdog mode.
+		 */
+		XScuWdt_SetWdMode(InstancePtr);
+
+		/*
+		 * Indicate the instance is ready to use, successfully initialized.
+		 */
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		CfgStatus =(s32)XST_SUCCESS;
+	}
+	return CfgStatus;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog counter of the device.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		User needs to select the appropriate mode (watchdog/timer)
+*		before using this API.
+*		See XScuWdt_SetWdMode/XScuWdt_SetTimerMode macros in
+*		xscuwdt.h.
+*
+******************************************************************************/
+void XScuWdt_Start(XScuWdt *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUWDT_CONTROL_OFFSET);
+
+	/*
+	 * Set the 'watchdog enable' bit in the register.
+	 */
+	Register |= XSCUWDT_CONTROL_WD_ENABLE_MASK;
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUWDT_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+}
+
+/****************************************************************************/
+/**
+*
+* Stop the watchdog timer.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuWdt_Stop(XScuWdt *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the Control register.
+	 */
+	Register = XScuWdt_ReadReg(InstancePtr->Config.BaseAddr,
+				  XSCUWDT_CONTROL_OFFSET);
+
+	/*
+	 * Clear the 'watchdog enable' bit in the register.
+	 */
+	Register &= (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+	/*
+	 * Update the Control register with the new value.
+	 */
+	XScuWdt_WriteReg(InstancePtr->Config.BaseAddr,
+			XSCUWDT_CONTROL_OFFSET, Register);
+
+	/*
+	 * Indicate that the device is stopped.
+	 */
+	InstancePtr->IsStarted = 0U;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
new file mode 100644
index 0000000..372bbc3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt.h
+* @addtogroup scuwdt_v2_1
+* @{
+* @details
+*
+* The Xilinx SCU watchdog timer driver (XScuWdt) supports the Xilinx SCU private
+* watchdog timer hardware.
+*
+* The XScuWdt driver supports the following features:
+* - Watchdog mode
+* - Timer mode
+* - Auto reload (timer mode only)
+*
+* The watchdog counter register is a down counter and starts decrementing when
+* the watchdog is started.
+* In watchdog mode, when the counter reaches 0, the Reset flag is set in the
+* Reset status register and the WDRESETREQ pin is asserted, causing a system
+* reset. The Reset flag is not reset by normal processor reset and is cleared
+* when written with a value of 1. This enables the user to differentiate a
+* normal reset and a reset caused by watchdog time-out. The user needs to call
+* XScuWdt_RestartWdt() periodically, to avoid the watchdog from being timed-out.
+*
+* The IsWdtExpired function can be used to check if the watchdog was the cause
+* of the last reset. In this situation, call Initialize then call IsWdtExpired.
+* If the result is true, watchdog timeout caused the last system reset. The
+* application then needs to clear the Reset flag.
+*
+* In timer mode, when the counter reaches 0, the Event flag is set in the
+* Interrupt status register and if interrupts are enabled, interrupt ID 30 is
+* set as pending in the interrupt distributor. The IsTimerExpired function
+* is used to check if the watchdog counter has decremented to 0 in timer mode.
+* If auto-reload mode is enabled, the Counter register is automatically reloaded
+* from the Load register.
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate with the Watchdog Timer.
+*
+* XScuWdt_CfgInitialize() API is used to initialize the Watchdog Timer. The
+* user needs to first call the XScuWdt_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to
+* the XScuWdt_CfgInitialize() API.
+*
+* Interrupts
+*
+* The SCU Watchdog Timer supports interrupts in Timer mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* Timer in interrupt mode.
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*  Building the driver 
+*
+* The XScuWdt driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* 

    
+*
+* NOTE:
+* The watchdog timer is not a part of the snoop control unit as indicated
+* by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* 
    
+*
+******************************************************************************/
+#ifndef XSCUWDT_H		/* prevent circular inclusions */
+#define XSCUWDT_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xscuwdt_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Base address of the device */
+} XScuWdt_Config;
+
+/**
+ * The XScuWdt driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XScuWdt_Config Config;/**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device watchdog timer is running */
+} XScuWdt;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog has timed-out and the last
+* reset was caused by the watchdog reset.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsWdtExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsWdtExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_RST_STS_OFFSET) &			\
+	 XSCUWDT_RST_STS_RESET_FLAG_MASK) == XSCUWDT_RST_STS_RESET_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* This function is used to check if the watchdog counter has reached 0 in timer
+* mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XScuWdt_IsTimerExpired(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_IsTimerExpired(InstancePtr)				\
+	((XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,		\
+			  XSCUWDT_ISR_OFFSET) &				\
+	 XSCUWDT_ISR_EVENT_FLAG_MASK) == XSCUWDT_ISR_EVENT_FLAG_MASK)
+
+/****************************************************************************/
+/**
+*
+* Re-start the watchdog timer. This macro will read the watchdog load register
+* and write the same value to load register to update the counter register.
+* An application needs to call this function periodically to keep the watchdog
+* from asserting the WDRESETREQ reset request output pin.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_RestartWdt(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_RestartWdt(InstancePtr)					 \
+	XScuWdt_LoadWdt((InstancePtr),					 \
+			(XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+					 XSCUWDT_LOAD_OFFSET)))
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog timer load register. This will also update the
+* watchdog counter register with the new value. This macro can be used to
+* change the time-out value.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	Value is the value to be written to the Watchdog Load register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_LoadWdt(XScuWdt *InstancePtr, u32 Value)
+*
+******************************************************************************/
+#define XScuWdt_LoadWdt(InstancePtr, Value)				\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_LOAD_OFFSET, (Value))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Watchdog mode by setting the WD mode bit of the
+* Watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetWdMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetWdMode(InstancePtr)					  \
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		  \
+			 XSCUWDT_CONTROL_OFFSET,			  \
+			 (XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr, \
+			  XSCUWDT_CONTROL_OFFSET) |			  \
+			  (XSCUWDT_CONTROL_WD_MODE_MASK)))
+
+/****************************************************************************/
+/**
+*
+* Put the watchdog timer in Timer mode by writing 0x12345678 and 0x87654321
+* successively to the Watchdog Disable Register.
+* The software must write 0x12345678 and 0x87654321 successively to the
+* Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+* Control Register is set to zero.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_SetTimerMode(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_SetTimerMode(InstancePtr)				\
+{									\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE1);			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			XSCUWDT_DISABLE_OFFSET,				\
+			XSCUWDT_DISABLE_VALUE2);			\
+}
+
+/****************************************************************************/
+/**
+*
+* Get the contents of the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	Contents of the watchdog control register.
+*
+* @note		C-style signature:
+		u32 XScuWdt_GetControlReg(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_GetControlReg(InstancePtr)				\
+	XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,			\
+			XSCUWDT_CONTROL_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* Write to the watchdog control register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+* @param	ControlReg is the value to be written to the watchdog control
+*		register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+		void XScuWdt_SetControlReg(XScuWdt *InstancePtr, u32 ControlReg)
+*
+******************************************************************************/
+#define XScuWdt_SetControlReg(InstancePtr, ControlReg)			\
+	XScuWdt_WriteReg((InstancePtr)->Config.BaseAddr,		\
+			 XSCUWDT_CONTROL_OFFSET, (ControlReg))
+
+/****************************************************************************/
+/**
+*
+* Enable auto-reload mode.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_EnableAutoReload(XScuWdt *InstancePtr)
+*
+******************************************************************************/
+#define XScuWdt_EnableAutoReload(InstancePtr)				\
+	XScuWdt_SetControlReg((InstancePtr),				\
+			      (XScuWdt_GetControlReg(InstancePtr) |	\
+			      XSCUWDT_CONTROL_AUTO_RELOAD_MASK))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xscuwdt_sinit.c.
+ */
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId);
+
+/*
+ * Selftest function in xscuwdt_selftest.c
+ */
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr);
+
+/*
+ * Interface functions in xscuwdt.c
+ */
+s32 XScuWdt_CfgInitialize(XScuWdt *InstancePtr,
+			  XScuWdt_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XScuWdt_Start(XScuWdt *InstancePtr);
+
+void XScuWdt_Stop(XScuWdt *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
new file mode 100644
index 0000000..5d6307d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscuwdt.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SCUWDT_0_DEVICE_ID,
+		XPAR_PS7_SCUWDT_0_BASEADDR
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
new file mode 100644
index 0000000..2067d3a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_hw.h
@@ -0,0 +1,182 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_hw.h
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains the hardware interface to the Xilinx SCU private Watch Dog
+* Timer (XSCUWDT).
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 1.01a bss 02/27/12 Updated the register offsets to start at 0x0 instead
+*                    of 0x20 as the base address obtained from the tools
+*		     starts at 0x20.
+* 1.02a  sg 07/17/12 Included xil_assert.h for CR 667947. This is an issue
+*		     when the xstatus.h in the common driver overwrites
+*		     the xstatus.h of the standalone BSP during the
+*		     libgen.
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+#ifndef XSCUWDT_HW_H		/* prevent circular inclusions */
+#define XSCUWDT_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device. The WDT registers start at
+ * an offset 0x20
+ * @{
+ */
+
+#define XSCUWDT_LOAD_OFFSET	0x00U /**< Watchdog Load Register */
+#define XSCUWDT_COUNTER_OFFSET	0x04U /**< Watchdog Counter Register */
+#define XSCUWDT_CONTROL_OFFSET	0x08U /**< Watchdog Control Register */
+#define XSCUWDT_ISR_OFFSET	0x0CU /**< Watchdog Interrupt Status Register */
+#define XSCUWDT_RST_STS_OFFSET	0x10U /**< Watchdog Reset Status Register */
+#define XSCUWDT_DISABLE_OFFSET	0x14U /**< Watchdog Disable Register */
+/* @} */
+
+/** @name Watchdog Control register
+ * This register bits control the prescaler, WD/Timer mode, Intr enable,
+ * auto-reload, watchdog enable.
+ * @{
+ */
+
+#define XSCUWDT_CONTROL_PRESCALER_MASK	 0x0000FF00U /**< Prescaler */
+#define XSCUWDT_CONTROL_PRESCALER_SHIFT	 8U
+#define XSCUWDT_CONTROL_WD_MODE_MASK	 0x00000008U /**< Watchdog/Timer mode */
+#define XSCUWDT_CONTROL_IT_ENABLE_MASK	 0x00000004U /**< Intr enable (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_AUTO_RELOAD_MASK 0x00000002U /**< Auto-reload (in
+							 timer mode) */
+#define XSCUWDT_CONTROL_WD_ENABLE_MASK	 0x00000001U /**< Watchdog enable */
+/* @} */
+
+/** @name Interrupt Status register
+ * This register indicates the Counter register has reached zero in Counter
+ * mode.
+ * @{
+ */
+
+#define XSCUWDT_ISR_EVENT_FLAG_MASK	0x00000001U /**< Event flag */
+/*@}*/
+
+/** @name Reset Status register
+ * This register indicates the Counter register has reached zero in Watchdog
+ * mode and a reset request is sent.
+ * @{
+ */
+
+#define XSCUWDT_RST_STS_RESET_FLAG_MASK	0x00000001U /**< Time out occured */
+/*@}*/
+
+/** @name Disable register
+ * This register is used to switch from watchdog mode to timer mode.
+ * The software must write 0x12345678 and 0x87654321 successively to the
+ * Watchdog Disable Register so that the watchdog mode bit in the Watchdog
+ * Control Register is set to zero.
+ * @{
+ */
+#define XSCUWDT_DISABLE_VALUE1		0x12345678U /**< Watchdog mode disable
+							value 1 */
+#define XSCUWDT_DISABLE_VALUE2		0x87654321U /**< Watchdog mode disable
+							value 2 */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XScuWdt_ReadReg(u32 BaseAddr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuWdt_ReadReg(BaseAddr, RegOffset)		\
+	Xil_In32((BaseAddr) + ((u32)RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddr is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuWdt_WriteReg(u32 BaseAddr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuWdt_WriteReg(BaseAddr, RegOffset, Data)	\
+	Xil_Out32((BaseAddr) + ((u32)RegOffset), ((u32)Data))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
new file mode 100644
index 0000000..95d5065
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_selftest.c
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xscuwdt_selftest.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuWdt driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the WDT. This test stops the watchdog, writes a value to
+* the watchdog load register, starts the watchdog and verifies that the value
+* read from the counter register is less that the value written to the load
+* register. It then restores the control register and the watchdog load
+* register.
+*
+* @param	InstancePtr is a pointer to the XScuWdt instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if the WDT is not decrementing.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XScuWdt_SelfTest(XScuWdt *InstancePtr)
+{
+	s32 SelfTestStatus;
+	u32 Register;
+	u32 CtrlOrig;
+	u32 LoadOrig;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Stop the watchdog timer.
+	 */
+	CtrlOrig = XScuWdt_GetControlReg(InstancePtr);
+	XScuWdt_SetControlReg(InstancePtr,
+			      CtrlOrig & (u32)(~XSCUWDT_CONTROL_WD_ENABLE_MASK));
+
+	LoadOrig = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+				   XSCUWDT_LOAD_OFFSET);
+	XScuWdt_LoadWdt(InstancePtr, 0xFFFFFFFFU);
+
+	/*
+	 * Start the watchdog timer and check if the watchdog counter is
+	 * decrementing.
+	 */
+	XScuWdt_SetControlReg(InstancePtr,
+			      CtrlOrig | (u32)XSCUWDT_CONTROL_WD_ENABLE_MASK);
+
+	Register = XScuWdt_ReadReg((InstancePtr)->Config.BaseAddr,
+				   XSCUWDT_COUNTER_OFFSET);
+
+	XScuWdt_LoadWdt(InstancePtr, LoadOrig);
+	XScuWdt_SetControlReg(InstancePtr, CtrlOrig);
+
+	if (Register == 0xFFFFFFFFU) {
+		SelfTestStatus = (s32)XST_FAILURE;
+	}
+	else {
+		SelfTestStatus = (s32)XST_SUCCESS;
+	}
+
+	return SelfTestStatus;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
new file mode 100644
index 0000000..c63eb9a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscuwdt_sinit.c
+* @addtogroup scuwdt_v2_1
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- ---------------------------------------------
+* 1.00a sdm 01/15/10 First release
+* 2.1 	sk  02/26/15 Modified the code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xscuwdt.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuWdt_Config *XScuWdt_LookupConfig(u16 DeviceId)
+{
+	XScuWdt_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_XSCUWDT_NUM_INSTANCES; Index++) {
+		if (XScuWdt_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuWdt_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuWdt_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
new file mode 100644
index 0000000..8b1f113
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.c
@@ -0,0 +1,1763 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+* @addtogroup sdps_v3_5
+* @{
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     05/17/17 Add support for 64bit DMA addressing
+*       mn     07/17/17 Add support for running SD at 200MHz
+*       mn     07/26/17 Fixed compilation warnings
+*       mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*       mn     08/17/17 Added CCI support for A53 and disabled data cache
+*                       operations when it is enabled.
+*       mn     08/22/17 Updated for Word Access System support
+*       mn     09/06/17 Resolved compilation errors with IAR toolchain
+*       mn     09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode
+* 3.4   mn     10/17/17 Use different commands for single and multi block
+*                       transfers
+*       mn     03/02/18 Move UHS macro check to SD card initialization routine
+* 3.5   mn     04/18/18 Resolve compilation warnings for sdps driver
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN	0x1AAU
+#define XSDPS_RESPOCR_READY	0x80000000U
+#define XSDPS_ACMD41_HCS	0x40000000U
+#define XSDPS_ACMD41_3V3	0x00300000U
+#define XSDPS_CMD1_HIGH_VOL	0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL	0x00FF8010U
+#define HIGH_SPEED_SUPPORT	0x2U
+#define UHS_SDR50_SUPPORT	0x4U
+#define WIDTH_4_BIT_SUPPORT	0x4U
+#define SD_CLK_25_MHZ		25000000U
+#define SD_CLK_19_MHZ		19000000U
+#define SD_CLK_26_MHZ		26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE	196U
+#define EXT_CSD_SEC_COUNT_BYTE1		212U
+#define EXT_CSD_SEC_COUNT_BYTE2		213U
+#define EXT_CSD_SEC_COUNT_BYTE3		214U
+#define EXT_CSD_SEC_COUNT_BYTE4		215U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED			0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED	0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED	0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200		0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200		0x20U
+#define CSD_SPEC_VER_3		0x3U
+#define SCR_SPEC_VER_3		0x80U
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+
+u16 TransferMode;
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific SD device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		This function initializes the host controller.
+*		Initial clock of 400KHz is set.
+*		Voltage of 3.3V is selected as that is supported by host.
+*		Interrupts status is enabled and signal disabled by default.
+*		Default data direction is card to host and
+*		32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	u8 PowerLevel;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/* Set some default values. */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
+	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
+	InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+	InstancePtr->Config.BankNumber = ConfigPtr->BankNumber;
+	InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO;
+	InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent;
+	InstancePtr->SectorCount = 0;
+	InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+	InstancePtr->Config_TapDelay = NULL;
+
+	/* Disable bus power and issue emmc hw reset */
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) ==
+			XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET, 0x0);
+
+	/* Delay to poweroff card */
+    (void)usleep(1000U);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_ALL_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	}
+	/* Host Controller version is read. */
+	 InstancePtr->HC_Version =
+			(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+
+	/*
+	 * Read capabilities register and update it in Instance pointer.
+	 * It is sufficient to read this once on power on.
+	 */
+	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_CAPS_OFFSET);
+
+	/* Select voltage and enable bus power. */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				(XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) &
+				~XSDPS_PC_EMMC_HW_RST_MASK);
+	else
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_POWER_CTRL_OFFSET,
+				XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+	/* Delay before issuing the command after emmc reset */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+		if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) ==
+				XSDPS_CAPS_EMB_SLOT)
+			usleep(200);
+
+	/* Change the clock frequency to 400 KHz */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH ;
+	}
+
+    if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
+	} else {
+		PowerLevel = 0U;
+	}
+
+	/* Select voltage based on capability and enable bus power. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET,
+			PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+
+#ifdef __aarch64__
+	/* Enable ADMA2 in 64bit mode. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_64_MASK);
+#else
+	/* Enable ADMA2 in 32bit mode. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_32_MASK);
+#endif
+
+	/* Enable all interrupt status except card interrupt initially */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_EN_OFFSET,
+			XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_EN_OFFSET,
+			XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* Disable all interrupt signals by default. */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
+
+	/*
+	 * Transfer mode register - default value
+	 * DMA enabled, block count enabled, data direction card to host(read)
+	 */
+	TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_DAT_DIR_SEL_MASK;
+
+	/* Set block size to 512 by default */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+			   initialization cycle failed
+*
+* @note		This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD8 and ACDM41 are sent to identify voltage and
+*		high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 Arg;
+	u8 ReadReg;
+	u32 BlkLen, DeviceSize, Mult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+#ifndef UHS_MODE_ENABLE
+	InstancePtr->Config.BusWidth = XSDPS_WIDTH_4;
+#endif
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * CMD8; response expected
+	 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+			XSDPS_CMD8_VOL_PATTERN, 0U);
+	if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (Status == XSDPS_CT_ERROR) {
+		 /* "Software reset for all" is initiated */
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+				XSDPS_SWRST_CMD_LINE_MASK);
+
+		/* Proceed with initialization only after reset is complete */
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+			ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		}
+	}
+
+	RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_RESP0_OFFSET);
+	if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+		InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
+	}
+	else {
+		InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
+	}
+
+	RespOCR = 0U;
+	/* Send ACMD41 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+		/*
+		 * There is no support to switch to 1.8V and use UHS mode on
+		 * 1.0 silicon
+		 */
+		if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+			(XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+			(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+			Arg |= XSDPS_OCR_S18;
+		}
+
+		/* 0x40300000 - Host High Capacity support & 3.3V window */
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+				Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	if ((RespOCR & XSDPS_OCR_S18) != 0U) {
+		InstancePtr->Switch1v8 = 1U;
+		Status = XSdPs_Switch_Voltage(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+	do {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Relative card address is stored as the upper 16 bits
+		 * This is to avoid shifting when sending commands
+		 */
+		InstancePtr->RelCardAddr =
+				XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
+	} while (InstancePtr->RelCardAddr == 0U);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) {
+		BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+		Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+		DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+		DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+		DeviceSize = (DeviceSize + 1U) * Mult;
+		DeviceSize =  DeviceSize * BlkLen;
+		InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+	} else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) {
+		InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) +
+										1U) * 1024U;
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize Card with Identification mode sequence
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+*			   initialization cycle failed
+*
+*
+******************************************************************************/
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr)
+{
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	static u8 ExtCsd[512];
+	u8 SCR[8] = { 0U };
+#pragma data_alignment = 4
+#else
+	static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+	u8 SCR[8] __attribute__ ((aligned(32))) = { 0U };
+#endif
+	u8 ReadBuff[64] = { 0U };
+	s32 Status;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Default settings */
+	InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+	InstancePtr->CardType = XSDPS_CARD_SD;
+	InstancePtr->Switch1v8 = 0U;
+	InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+
+	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+			((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+			== XSDPS_CAPS_EMB_SLOT)) {
+		InstancePtr->CardType = XSDPS_CHIP_EMMC;
+	} else {
+		Status = XSdPs_IdentifyCard(InstancePtr);
+		if (Status == XST_FAILURE) {
+			goto RETURN_PATH;
+		}
+	}
+
+	if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
+		(InstancePtr->CardType != XSDPS_CARD_MMC) &&
+		(InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		Status = XSdPs_SdCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Change clock to default clock 25MHz */
+		/*
+		 * SD default speed mode timing should be closed at 19 MHz.
+		 * The reason for this is SD requires a voltage level shifter.
+		 * This limitation applies to ZynqMPSoC.
+		 */
+		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+			InstancePtr->BusSpeed = SD_CLK_19_MHZ;
+		else
+			InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	} else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
+			|| (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+		Status = XSdPs_MmcCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+		/* Change clock to default clock 26MHz */
+		InstancePtr->BusSpeed = SD_CLK_26_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_Select_Card(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		/* Pull-up disconnected during data transfer */
+		Status = XSdPs_Pullup(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
+			Status = XSdPs_Change_BusWidth(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+
+		/* Get speed supported by device */
+		Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+		if (Status != XST_SUCCESS) {
+			goto RETURN_PATH;
+		}
+
+		if (((SCR[2] & SCR_SPEC_VER_3) != 0U) &&
+			(ReadBuff[13] >= UHS_SDR50_SUPPORT) &&
+			(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) &&
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+			(XGetPSVersion_Info() > XPS_VERSION_1) &&
+#endif
+			(InstancePtr->Switch1v8 == 0U)) {
+			u16 CtrlReg, ClockReg;
+
+			/* Stop the clock */
+			CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+			CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+					CtrlReg);
+
+			/* Enabling 1.8V in controller */
+			CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL2_OFFSET);
+			CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+					CtrlReg);
+
+			/* Wait minimum 5mSec */
+			(void)usleep(5000U);
+
+			/* Check for 1.8V signal enable bit is cleared by Host */
+			CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_HOST_CTRL2_OFFSET);
+			if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			/* Wait for internal clock to stabilize */
+			ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_CLK_CTRL_OFFSET);
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_CLK_CTRL_OFFSET,
+						ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+			ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+								XSDPS_CLK_CTRL_OFFSET);
+			while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+				ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+							XSDPS_CLK_CTRL_OFFSET);
+			}
+
+			/* Enable SD clock */
+			ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET,
+					ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+			/* Wait for 1mSec */
+			(void)usleep(1000U);
+
+			InstancePtr->Switch1v8 = 1U;
+		}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+		if (InstancePtr->Switch1v8 != 0U) {
+
+			/* Identify the UHS mode supported by card */
+			XSdPs_Identify_UhsMode(InstancePtr, ReadBuff);
+
+			/* Set UHS-I SDR104 mode */
+			Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode);
+			if (Status != XST_SUCCESS) {
+				goto RETURN_PATH;
+			}
+
+		} else {
+#endif
+			/*
+			 * card supports CMD6 when SD_SPEC field in SCR register
+			 * indicates that the Physical Layer Specification Version
+			 * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
+			 */
+			if (SCR[0] != 0U) {
+				/* Check for high speed support */
+				if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) &&
+						(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+					InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+					InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+					Status = XSdPs_Change_BusSpeed(InstancePtr);
+					if (Status != XST_SUCCESS) {
+						Status = XST_FAILURE;
+						goto RETURN_PATH;
+					}
+				}
+			}
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+		}
+#endif
+
+	} else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
+				(InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
+				(InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
+
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+		if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	} else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
+		/* Change bus width to 8-bit */
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Get Extended CSD */
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8;
+		InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1];
+
+		/* Check for card supported speed */
+		if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				(EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
+				EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HS200_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+#endif
+		} else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				(EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED |
+				EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_DDR52_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+#endif
+		} else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) &&
+				(InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) {
+			InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE;
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+#endif
+		} else
+			InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE;
+
+		if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) {
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+				if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
+					Status = XST_FAILURE;
+					goto RETURN_PATH;
+				}
+			}
+
+			if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) ||
+					InstancePtr->Mode == XSDPS_DDR52_MODE) {
+				if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+					Status = XST_FAILURE;
+					goto RETURN_PATH;
+				}
+
+				if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+					Status = XSdPs_Change_BusWidth(InstancePtr);
+					if (Status != XST_SUCCESS) {
+						Status = XST_FAILURE;
+						goto RETURN_PATH;
+					}
+				}
+			}
+		}
+
+		/* Enable Rst_n_Fun bit if it is disabled */
+		if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) {
+			Arg = XSDPS_MMC_RST_FUN_EN_ARG;
+			Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+	if ((InstancePtr->Mode != XSDPS_DDR52_MODE) ||
+			(InstancePtr->CardType == XSDPS_CARD_SD)) {
+		Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Identify type of card using CMD0 + CMD1 sequence
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* 74 CLK delay after card is powered up, before the first command. */
+	usleep(XSDPS_INIT_DELAY);
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Host High Capacity support & High voltage window */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+			XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+	if (Status != XST_SUCCESS) {
+		InstancePtr->CardType = XSDPS_CARD_SD;
+	} else {
+		InstancePtr->CardType = XSDPS_CARD_MMC;
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_CMD_LINE_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Switches the SD card voltage from 3v3 to 1v8
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 CtrlReg;
+	u32 ReadReg, ClockReg;
+
+	/* Send switch voltage command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+	}
+
+	/* Wait for CMD and DATA line to go low */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
+					XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+	/* Stop the clock */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+			CtrlReg);
+
+	/* Enabling 1.8V in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+			CtrlReg);
+
+	/* Wait minimum 5mSec */
+	(void)usleep(5000U);
+
+	/* Check for 1.8V signal enable bit is cleared by Host */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for internal clock to stabilize */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET,
+				ClockReg | XSDPS_CC_INT_CLK_EN_MASK);
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_CLK_CTRL_OFFSET);
+	while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	/* Wait for 1mSec */
+	(void)usleep(1000U);
+
+	/* Wait for CMD and DATA line to go high */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
+			!= (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+
+* This function does SD command generation.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cmd is the command to be sent.
+* @param	Arg is the argument to be sent along with the command.
+* 		This could be address or any other information
+* @param	BlkCnt - Block count passed by the user.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 			is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+	u32 PresentStateReg;
+	u32 CommandReg;
+	u32 StatusReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the command inhibit to make sure no other
+	 * command transfer is in progress
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Write block count register */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
+
+	/* Write argument register */
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XSDPS_ARGMT_OFFSET, Arg);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+	/* Command register is set to trigger transfer of command */
+	CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
+
+	/*
+	 * Mask to avoid writing to reserved bits 31-30
+	 * This is necessary because 0x80000000 is used  by this software to
+	 * distinguish between ACMD and CMD of same number
+	 */
+	CommandReg = CommandReg & 0x3FFFU;
+
+	/*
+	 * Check for data inhibit in case of command using DAT lines.
+	 * For Tuning Commands DAT lines check can be ignored.
+	 */
+	if ((Cmd != CMD21) && (Cmd != CMD19)) {
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
+									XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
+				((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+			(CommandReg << 16) | TransferMode);
+
+	/* Polling for response for now */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((Cmd == CMD21) || (Cmd == CMD19)) {
+			if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
+				break;
+			}
+		}
+
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+									XSDPS_ERR_INTR_STS_OFFSET);
+			if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
+				Status = XSDPS_CT_ERROR;
+			}
+			 /* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET,
+			XSDPS_INTR_CC_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param	Command to be sent.
+*
+* @return	Command register value complete with response type and
+* 		data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
+{
+		u32 RetVal;
+
+		RetVal = Cmd;
+
+		switch(Cmd) {
+		case CMD0:
+			RetVal |= RESP_NONE;
+		break;
+		case CMD1:
+			RetVal |= RESP_R3;
+		break;
+		case CMD2:
+			RetVal |= RESP_R2;
+		break;
+		case CMD3:
+			RetVal |= RESP_R6;
+		break;
+		case CMD4:
+			RetVal |= RESP_NONE;
+			break;
+		case CMD5:
+			RetVal |= RESP_R1B;
+		break;
+		case CMD6:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			} else {
+				RetVal |= RESP_R1B;
+			}
+			break;
+		case ACMD6:
+			RetVal |= RESP_R1;
+		break;
+		case CMD7:
+			RetVal |= RESP_R1;
+		break;
+		case CMD8:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1;
+			} else {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			}
+			break;
+		case CMD9:
+			RetVal |= RESP_R2;
+		break;
+		case CMD11:
+		case CMD10:
+		case CMD12:
+		case ACMD13:
+		case CMD16:
+			RetVal |= RESP_R1;
+		break;
+		case CMD17:
+		case CMD18:
+		case CMD19:
+		case CMD21:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD23:
+		case ACMD23:
+		case CMD24:
+		case CMD25:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case ACMD41:
+			RetVal |= RESP_R3;
+		break;
+		case ACMD42:
+			RetVal |= RESP_R1;
+		break;
+		case ACMD51:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD52:
+		case CMD55:
+			RetVal |= RESP_R1;
+		break;
+		case CMD58:
+		break;
+		default :
+			RetVal |= Cmd;
+		break;
+		}
+
+		return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheInvalidateRange((INTPTR)Buff,
+			BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+	}
+
+	if (BlkCnt == 1U) {
+		TransferMode = XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+		/* Send single block read command */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK;
+
+		/* Send multiple blocks read command */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/* Check for transfer complete */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheFlushRange((INTPTR)Buff,
+			BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+	}
+
+	if (BlkCnt == 1U) {
+		TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK;
+
+		/* Send single block write command */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+		/* Send multiple blocks write command */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+	s32 Status = 0;
+
+	/* Send CMD7 - Select card */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	BlkCnt - block count.
+* @param	Buff pointer to data buffer.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+	u32 TotalDescLines = 0U;
+	u32 DescNum = 0U;
+	u32 BlkSize = 0U;
+
+	/* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+	BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_BLK_SIZE_OFFSET);
+	BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
+
+	if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+		TotalDescLines = 1U;
+
+	}else {
+
+		TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+		if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+			TotalDescLines += 1U;
+		}
+
+	}
+
+	for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+#ifdef __aarch64__
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
+		InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+				XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+		/* This will write '0' to length field which indicates 65536 */
+		InstancePtr->Adma2_DescrTbl[DescNum].Length =
+				(u16)XSDPS_DESC_MAX_LENGTH;
+	}
+
+#ifdef __aarch64__
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#else
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+#endif
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+			XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+			(u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+#ifdef __aarch64__
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET,
+			(u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32));
+#endif
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+			(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+			sizeof(XSdPs_Adma2Descriptor) * 32U);
+	}
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) MMC is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the initialization
+*			   cycle failed
+* @note 	This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD1 sent to identify voltage and high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 BlkLen, DeviceSize, Mult;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = 0U;
+	/* Send CMD1 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+
+		/* Host High Capacity support & High volage window */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+				XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	/* Set relative card address */
+	InstancePtr->RelCardAddr = 0x12340000U;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	InstancePtr->Card_Version =  (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
+
+	/* Calculating the memory capacity */
+	BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U);
+	Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U);
+	DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U;
+	DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U;
+	DeviceSize = (DeviceSize + 1U) * Mult;
+	DeviceSize =  DeviceSize * BlkLen;
+
+	InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
new file mode 100644
index 0000000..b8d979d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps.h
@@ -0,0 +1,280 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v3_5
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+*              05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+*       sk     08/13/16 Removed sleep.h from xsdps.h as a temporary fix for
+*                       CR#956899.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     10/13/16 Reduced the delay during power cycle to 1ms as per spec
+*       sk     10/19/16 Used emmc_hwreset pin to reset eMMC.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     11/30/16 Modified the voltage switching sequence as per spec.
+*       sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     05/17/17 Add support for 64bit DMA addressing
+* 	mn     08/07/17 Modify driver to support 64-bit DMA in arm64 only
+*       mn     08/17/17 Enabled CCI support for A53 by adding cache coherency
+*                       information.
+*       mn     09/06/17 Resolved compilation errors with IAR toolchain
+*
+* 
    
+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include "xplatform_info.h"
+#include 
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR	0x2U	/**< Command timeout flag */
+#define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+
+typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID  of device */
+	u32 BaseAddress;		/**< Base address of the device */
+	u32 InputClockHz;		/**< Input clock frequency */
+	u32 CardDetect;			/**< Card Detect */
+	u32 WriteProtect;			/**< Write Protect */
+	u32 BusWidth;			/**< Bus Width */
+	u32 BankNumber;			/**< MIO Bank selection for SD */
+	u32 HasEMIO;			/**< If SD is connected to EMIO */
+	u8 IsCacheCoherent; 		/**< If SD is Cache Coherent or not */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+	u16 Attribute;		/**< Attributes of descriptor */
+	u16 Length;		/**< Length of current dma transfer */
+#ifdef __aarch64__
+	u64 Address;		/**< Address of current dma transfer */
+#else
+	u32 Address;		/**< Address of current dma transfer */
+#endif
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+} XSdPs_Adma2Descriptor;
+#pragma data_alignment = 4
+#else
+}  __attribute__((__packed__))XSdPs_Adma2Descriptor;
+#endif
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSdPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 Host_Caps;		/**< Capabilities of host controller */
+	u32 Host_CapsExt;	/**< Extended Capabilities */
+	u32 HCS;		/**< High capacity support in card */
+	u8  CardType;		/**< Type of card - SD/MMC/eMMC */
+	u8  Card_Version;	/**< Card version */
+	u8  HC_Version;		/**< Host controller version */
+	u8  BusWidth;		/**< Current operating bus width */
+	u32 BusSpeed;		/**< Current operating bus speed */
+	u8  Switch1v8;		/**< 1.8V Switch support */
+	u32 CardID[4];		/**< Card ID Register */
+	u32 RelCardAddr;	/**< Relative Card Address */
+	u32 CardSpecData[4];	/**< Card Specific Data Register */
+	u32 SectorCount;		/**< Sector Count */
+	u32 SdCardConfig;	/**< Sd Card Configuration Register */
+	u32 Mode;			/**< Bus Speed Mode */
+	XSdPs_ConfigTap Config_TapDelay;	/**< Configuring the tap delays */
+	/**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff);
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
new file mode 100644
index 0000000..c427bed
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_g.c
@@ -0,0 +1,62 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_SD_0_DEVICE_ID,
+		XPAR_PS7_SD_0_BASEADDR,
+		XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ,
+		XPAR_PS7_SD_0_HAS_CD,
+		XPAR_PS7_SD_0_HAS_WP,
+		XPAR_PS7_SD_0_BUS_WIDTH,
+		XPAR_PS7_SD_0_MIO_BANK,
+		XPAR_PS7_SD_0_HAS_EMIO,
+		XPAR_PS7_SD_0_IS_CACHE_COHERENT
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
new file mode 100644
index 0000000..c63d8f6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_hw.h
@@ -0,0 +1,1301 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v3_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     06/09/16 Added support for mkfs to calculate sector count.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+* 3.2   sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     08/22/17 Updated for Word Access System support
+*       mn     09/06/17 Added support for ARMCC toolchain
+* 3.4   mn     01/22/18 Separated out SDR104 and HS200 clock defines
+*
+* 
    
+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00U	/**< SDMA System Address
+							Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET	XSDPS_SDMA_SYS_ADDR_OFFSET
+						/**< SDMA System Address
+							Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET		0x00U	/**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET	0x02U	/**< SDMA System Address
+							High Register */
+#define XSDPS_ARGMT2_HI_OFFSET		0x02U	/**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET		0x04U	/**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET		0x06U	/**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET		0x08U	/**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET		XSDPS_ARGMT_OFFSET
+						/**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET		0x0AU	/**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET		0x0CU	/**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET		0x0EU	/**< Command Register */
+#define XSDPS_RESP0_OFFSET		0x10U	/**< Response0 Register */
+#define XSDPS_RESP1_OFFSET		0x14U	/**< Response1 Register */
+#define XSDPS_RESP2_OFFSET		0x18U	/**< Response2 Register */
+#define XSDPS_RESP3_OFFSET		0x1CU	/**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET	0x20U	/**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET		0x24U	/**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET		0x28U	/**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET		0x29U	/**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2AU	/**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2BU	/**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET		0x2CU	/**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2EU	/**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET		0x2FU	/**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 	0x30U	/**< Normal Interrupt
+							Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 	0x32U	/**< Error Interrupt
+							Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34U	/**< Normal Interrupt
+						Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36U	/**< Error Interrupt
+						Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38U	/**< Normal Interrupt
+						Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3AU	/**< Error Interrupt
+						Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3CU	/**< Auto CMD12 Error Status
+							Register */
+#define XSDPS_HOST_CTRL2_OFFSET		0x3EU	/**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 		0x40U	/**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 		0x44U	/**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48U	/**< Maximum Current
+						Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4CU	/**< Maximum Current
+						Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52U	/**< Force Event for
+						Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50U	/**< Auto CM12 Error Interrupt
+							Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET	0x54U	/**< ADMA Error Status
+							Register */
+#define XSDPS_ADMA_SAR_OFFSET		0x58U	/**< ADMA System Address
+							Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5CU	/**< ADMA System Address
+							Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET		0x60U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET		0x64U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET		0x68U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET		0x6CU	/**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET	0x70U	/**< Boot timeout control
+							register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0U	/**< Shared Bus Control
+							Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET	0xFCU	/**< Slot Interrupt Status
+							Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET	0xFEU	/**< Host Controller Version
+							Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * 			Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK		0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK		0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4		0x00000002U
+#define XSDPS_HC_SPEED_MASK		0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK		0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK		0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK		0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK		0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK	0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK		0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK		0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK		0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK		0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK		0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK		0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT			256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT		2046U
+#define XSDPS_CC_EXT_DIV_SHIFT			6U
+
+#define XSDPS_TC_CNTR_VAL_MASK			0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK			0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV		9U
+#define XSDPS_CC_DIV_SHIFT		8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ *  Normal and Error Interrupt Status Register 
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ *  Normal and Error Interrupt Status Enable Register 
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ *  Normal and Error Interrupt Signal Enable Register 
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK		0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK		0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK		0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK		0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK		0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK		0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK	0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK		0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK		0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK		0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK		0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK	0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00002000U /**< Boot Ack Recv
+							Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK	0x00004000U /**< Boot Terminate
+							Interrupt */
+#define XSDPS_INTR_ERR_MASK		0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK		0x00000001U /**< Command Timeout
+							Error */
+#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK		0x00000004U /**< Command End Bit
+							Error */
+#define XSDPS_INTR_ERR_CI_MASK		0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK		0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK		0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK	0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK		0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000U /**< Vendor Specific
+							Error */
+#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK		0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024		0x400U
+#define XSDPS_BLK_SIZE_2048		0x800U
+#define XSDPS_BLK_CNT_MASK		0x0000FFFFU /**< Block Count for
+								Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK		0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010U /**< Data Transfer
+							Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020U /**< Multi/Single
+							Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK		0x00000003U /**< Response Type
+							Select */
+#define XSDPS_CMD_RESP_NONE_MASK	0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK	0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK		0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003U /**< Response length 48 &
+							check busy after
+							response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008U /**< Command CRC Check
+							Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010U /**< Command Index Check
+							Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK		0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK			0x00003F00U /**< Command Index Mask -
+							Set to CMD0-63,
+							AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_AUTO_CMD_CRC_MASK		0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK		0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_AUTO_CMD_IND_MASK		0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK		0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK	0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK	0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK	0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK	0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK	0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK		0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK	0x0030U /**< Driver Strength
+							Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK	0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK	0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK	0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK	0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK		0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK	0x0080U /**< Sampling Clock
+							Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK	0x4000U /**< Asynchronous Interrupt
+							Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK	0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003FU /**< Timeout clock freq
+							select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080U /**< Timeout clock unit -
+							MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK	0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK	0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK	0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK		0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK		0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000U /**< Suspend/Resume
+							support */
+#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000U /**< 64 bit system bus
+							support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK	0x08000000U /**< Interrupt mode
+							support */
+#define XSDPS_CAP_SPI_MODE_MASK		0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK	0x20000000U /**< Async Interrupt
+							support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK	0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD			0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT			0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS			0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK		0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK		0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK		0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK	0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK	0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK	0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK	0x00000F00U /**< Timer Count for
+							Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK	0x00002000U /**< SDR50 Mode needs
+							tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK	0x0000C000U /**< Re-tuning modes
+							support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK	0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK	0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK	0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK	0x00FF0000U /**< Clock Multiplier value
+							for Programmable clock
+							mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK	0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK	0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK	0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK		0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK		0x00080000U /**< Write protect switch
+								pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK	0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK	0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK	0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK	0x00000F00U /**< Maximum Current
+							Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK	0x000000F0U /**< Maximum Current
+							Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK	0x0000000FU /**< Maximum Current
+							Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK	0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK	0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK	0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK	0x0001U /**< Command Timeout
+							Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK	0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK	0x0004U /**< Command End Bit
+							Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK	0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK	0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK	0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK	0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK	0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK	0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK	0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK	0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK	0xE000U /**< Vendor Specific
+							Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK	0x04U /**< ADMA Length Mismatch
+							Error */
+#define XSDPS_ADMA_ERR_STATE_MASK	0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK	0x00U /**< ADMA Error State
+							STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK	0x01U /**< ADMA Error State
+							FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK	0x03U /**< ADMA Error State
+							TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK	0x03FFU /**< SDCLK Frequency
+							Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK	0x0400U /**< Clock Generator
+							Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK	0xC000U /**< Driver Strength
+							Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK	0x0007U /**< Interrupt Signal
+							mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER		0xFF00U /**< Vendor
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_VER_MASK		0x00FFU /**< Host
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_V3		0x0002U
+#define XSDPS_HC_SPEC_V2		0x0001U
+#define XSDPS_HC_SPEC_V1		0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK	0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX	 0x8000U
+#define CMD0	 0x0000U
+#define CMD1	 0x0100U
+#define CMD2	 0x0200U
+#define CMD3	 0x0300U
+#define CMD4	 0x0400U
+#define CMD5	 0x0500U
+#define CMD6	 0x0600U
+#define ACMD6	(XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7	 0x0700U
+#define CMD8	 0x0800U
+#define CMD9	 0x0900U
+#define CMD10	 0x0A00U
+#define CMD11	 0x0B00U
+#define CMD12	 0x0C00U
+#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16	 0x1000U
+#define CMD17	 0x1100U
+#define CMD18	 0x1200U
+#define CMD19	 0x1300U
+#define CMD21	 0x1500U
+#define CMD23	 0x1700U
+#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24	 0x1800U
+#define CMD25	 0x1900U
+#define CMD41	 0x2900U
+#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52	 0x3400U
+#define CMD55	 0x3700U
+#define CMD58	 0x3A00U
+
+#define RESP_NONE	(u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1		(u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+			(u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B	(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2		(u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3		(u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6		(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN	0xAAU
+#define XSDPS_CIC_VOLT_MASK	(0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6	(1U<<8)
+#define XSDPS_CIC_VOLT_LOW	(1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS	(1U<<31)
+#define XSDPS_OCR_CC_STS	(1U<<30)
+#define XSDPS_OCR_S18		(1U<<24)
+#define XSDPS_OCR_3V5_3V6	(1U<<23)
+#define XSDPS_OCR_3V4_3V5	(1U<<22)
+#define XSDPS_OCR_3V3_3V4	(1U<<21)
+#define XSDPS_OCR_3V2_3V3	(1U<<20)
+#define XSDPS_OCR_3V1_3V2	(1U<<19)
+#define XSDPS_OCR_3V0_3V1	(1U<<18)
+#define XSDPS_OCR_2V9_3V0	(1U<<17)
+#define XSDPS_OCR_2V8_2V9	(1U<<16)
+#define XSDPS_OCR_2V7_2V8	(1U<<15)
+#define XSDPS_OCR_1V7_1V95	(1U<<7)
+#define XSDPS_OCR_HIGH_VOL	0x00FF8000U
+#define XSDPS_OCR_LOW_VOL	0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN		8U
+#define XSDPS_SCR_STRUCT_MASK		(0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK		(0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0		0U
+#define XSDPS_SCR_SPEC_1V1		(1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0		(2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE	(1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK		(7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE		0U
+#define XSDPS_SCR_SEC_SUPP_1V1		(2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0		(3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0		(4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK	(0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1		(1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4		(4U<<16)
+#define XSDPS_SCR_SPEC3_MASK		(1U<<12)
+#define XSDPS_SCR_SPEC3_2V0		0U
+#define XSDPS_SCR_SPEC3_3V0		(1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK		0x3U
+#define XSDPS_SCR_CMD23_SUPP		(1U<<1)
+#define XSDPS_SCR_CMD20_SUPP		(1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE	(1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR		(1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR	(1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR		(1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR		(1U<<27)
+#define XSDPS_CD_STS_WP_VIO		(1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED		(1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL	(1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR	(1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD		(1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL	(1U<<21)
+#define XSDPS_CD_STS_CC_ERR		(1U<<20)
+#define XSDPS_CD_STS_ERR		(1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR		(1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP		(1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS	(1U<<14)
+#define XSDPS_CD_STS_ER_RST		(1U<<13)
+#define XSDPS_CD_STS_CUR_STATE		(0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA	(1U<<8)
+#define XSDPS_CD_STS_APP_CMD		(1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR	(1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN	64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH	(1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK		0U
+
+#define XSDPS_MODE_FUNC_GRP1		1U
+#define XSDPS_MODE_FUNC_GRP2		2U
+#define XSDPS_MODE_FUNC_GRP3		3U
+#define XSDPS_MODE_FUNC_GRP4		4U
+#define XSDPS_MODE_FUNC_GRP5		5U
+#define XSDPS_MODE_FUNC_GRP6		6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL		0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL	0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12	0U
+#define XSDPS_ACC_MODE_HS_SDR25		1U
+#define XSDPS_ACC_MODE_SDR50		2U
+#define XSDPS_ACC_MODE_SDR104		3U
+#define XSDPS_ACC_MODE_DDR50		4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT		4U
+#define XSDPS_CMD_SYS_DEF		0U
+#define XSDPS_CMD_SYS_eC		1U
+#define XSDPS_CMD_SYS_OTP		3U
+#define XSDPS_CMD_SYS_ASSD		4U
+#define XSDPS_CMD_SYS_VEND		5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT	8U
+#define XSDPS_DRV_TYPE_B		0U
+#define XSDPS_DRV_TYPE_A		1U
+#define XSDPS_DRV_TYPE_C		2U
+#define XSDPS_DRV_TYPE_D		3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT		12U
+#define XSDPS_CUR_LIM_200		0U
+#define XSDPS_CUR_LIM_400		1U
+#define XSDPS_CUR_LIM_600		2U
+#define XSDPS_CUR_LIM_800		3U
+
+#define CSD_SPEC_VER_MASK		0x3C0000U
+#define READ_BLK_LEN_MASK		0x00000F00U
+#define C_SIZE_MULT_MASK		0x00000380U
+#define C_SIZE_LOWER_MASK		0xFFC00000U
+#define C_SIZE_UPPER_MASK		0x00000003U
+#define CSD_STRUCT_MASK			0x00C00000U
+#define CSD_V2_C_SIZE_MASK		0x3FFFFF00U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE		512U
+
+#define EXT_CSD_WR_REL_PARAM_EN		(1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN     (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0     (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL          (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE          (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE        (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26    	(1U<<0)  /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52    	(1U<<1)  /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK  	0x3FU    /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1U<<2)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1U<<3)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V  \
+                                        | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V      (1U<<4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V      (1U<<5)  /* Card can run at 200MHz */
+                                                /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE			183U
+#define EXT_CSD_BUS_WIDTH_1_BIT			0U	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT			1U	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT			2U	/* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT		5U	/* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT		6U	/* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE		185U
+#define EXT_CSD_HS_TIMING_DEF		0U
+#define EXT_CSD_HS_TIMING_HIGH		1U	/* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200		2U	/* Card is in HS200 mode */
+
+#define EXT_CSD_RST_N_FUN_BYTE		162U
+#define EXT_CSD_RST_N_FUN_TEMP_DIS	0U	/* RST_n signal is temporarily disabled */
+#define EXT_CSD_RST_N_FUN_PERM_EN	1U	/* RST_n signal is permanently enabled */
+#define EXT_CSD_RST_N_FUN_PERM_DIS	2U	/* RST_n signal is permanently disabled */
+
+#define XSDPS_EXT_CSD_CMD_SET		0U
+#define XSDPS_EXT_CSD_SET_BITS		1U
+#define XSDPS_EXT_CSD_CLR_BITS		2U
+#define XSDPS_EXT_CSD_WRITE_BYTE	3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG	(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_RST_FUN_EN_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \
+					 | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH	1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY	2960U
+#define XSDPS_100CLK_DELAY	4000U
+#define XSDPS_INIT_DELAY	10000U
+
+#define XSDPS_DEF_VOLT_LVL	XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR	0x1234U
+
+#define XSDPS_CARD_SD		1U
+#define XSDPS_CARD_MMC		2U
+#define XSDPS_CARD_SDIO		3U
+#define XSDPS_CARD_SDCOMBO	4U
+#define XSDPS_CHIP_EMMC		5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID     	(0x1U << 0)
+#define XSDPS_DESC_END       	(0x1U << 1)
+#define XSDPS_DESC_INT       	(0x1U << 2)
+#define XSDPS_DESC_TRAN  	(0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ		400000U		/**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ		50000000U	/**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ		52000000U	/**< 52 MHZ */
+#define XSDPS_SD_VER_1_0		0x1U		/**< SD ver 1 */
+#define XSDPS_SD_VER_2_0		0x2U		/**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT	1U
+#define XSDPS_SCR_BLKSIZE	8U
+#define XSDPS_1_BIT_WIDTH	0x1U
+#define XSDPS_4_BIT_WIDTH	0x2U
+#define XSDPS_8_BIT_WIDTH	0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12	0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25	0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50	0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104	0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50	0x4U
+#define XSDPS_HIGH_SPEED_MODE		0x5U
+#define XSDPS_DEFAULT_SPEED_MODE	0x6U
+#define XSDPS_HS200_MODE			0x7U
+#define XSDPS_DDR52_MODE			0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT		1U
+#define XSDPS_SWITCH_CMD_BLKSIZE	64U
+#define XSDPS_SWITCH_CMD_HS_GET		0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET		0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET		0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET		0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET		0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT	1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE	512U
+#define XSDPS_TUNING_CMD_BLKCNT		1U
+#define XSDPS_TUNING_CMD_BLKSIZE	64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK	50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK	208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK		100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK		25000000U
+
+#define SD_DRIVER_TYPE_B	0x01U
+#define SD_DRIVER_TYPE_A	0x02U
+#define SD_DRIVER_TYPE_C	0x04U
+#define SD_DRIVER_TYPE_D	0x08U
+#define SD_SET_CURRENT_LIMIT_200	0U
+#define SD_SET_CURRENT_LIMIT_400	1U
+#define SD_SET_CURRENT_LIMIT_600	2U
+#define SD_SET_CURRENT_LIMIT_800	3U
+
+#define SD_MAX_CURRENT_200	(1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400	(1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600	(1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800	(1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK	25000000U
+#define XSDPS_SD_SDR25_MAX_CLK	50000000U
+#define XSDPS_SD_SDR50_MAX_CLK	100000000U
+#define XSDPS_SD_DDR50_MAX_CLK	50000000U
+#define XSDPS_SD_SDR104_MAX_CLK	208000000U
+/*
+ * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller
+ * than the clock value coming from the core. This value is kept to safely
+ * switch to SDR104 mode if the SD card supports it.
+ */
+#define XSDPS_SD_INPUT_MAX_CLK	175000000U
+
+#define XSDPS_MMC_HS200_MAX_CLK	200000000U
+#define XSDPS_MMC_HSD_MAX_CLK	52000000U
+#define XSDPS_MMC_DDR_MAX_CLK	52000000U
+
+#define XSDPS_CARD_STATE_IDLE		0U
+#define XSDPS_CARD_STATE_RDY		1U
+#define XSDPS_CARD_STATE_IDEN		2U
+#define XSDPS_CARD_STATE_STBY		3U
+#define XSDPS_CARD_STATE_TRAN		4U
+#define XSDPS_CARD_STATE_DATA		5U
+#define XSDPS_CARD_STATE_RCV		6U
+#define XSDPS_CARD_STATE_PROG		7U
+#define XSDPS_CARD_STATE_DIS		8U
+#define XSDPS_CARD_STATE_BTST		9U
+#define XSDPS_CARD_STATE_SLP		10U
+
+#define XSDPS_SLOT_REM			0U
+#define XSDPS_SLOT_EMB			1U
+
+#define XSDPS_WIDTH_8		8U
+#define XSDPS_WIDTH_4		4U
+
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+#define SD0_ITAPDLY_SEL_MASK		0x000000FFU
+#define SD0_OTAPDLY_SEL_MASK		0x0000003FU
+#define SD1_ITAPDLY_SEL_MASK		0x00FF0000U
+#define SD1_OTAPDLY_SEL_MASK		0x003F0000U
+#define SD_DLL_CTRL 				0x00000358U
+#define SD_ITAPDLY					0x00000314U
+#define SD_OTAPDLY					0x00000318U
+#define SD0_DLL_RST					0x00000004U
+#define SD1_DLL_RST					0x00040000U
+#define SD0_ITAPCHGWIN				0x00000200U
+#define SD0_ITAPDLYENA				0x00000100U
+#define SD0_OTAPDLYENA				0x00000040U
+#define SD1_ITAPCHGWIN				0x02000000U
+#define SD1_ITAPDLYENA				0x01000000U
+#define SD1_OTAPDLYENA				0x00400000U
+
+#define SD0_OTAPDLYSEL_HS200_B0		0x00000003U
+#define SD0_OTAPDLYSEL_HS200_B2		0x00000002U
+#define SD0_ITAPDLYSEL_SD50			0x00000014U
+#define SD0_OTAPDLYSEL_SD50			0x00000003U
+#define SD0_ITAPDLYSEL_SD_DDR50		0x0000003DU
+#define SD0_ITAPDLYSEL_EMMC_DDR50	0x00000012U
+#define SD0_OTAPDLYSEL_SD_DDR50		0x00000004U
+#define SD0_OTAPDLYSEL_EMMC_DDR50	0x00000006U
+#define SD0_ITAPDLYSEL_HSD			0x00000015U
+#define SD0_OTAPDLYSEL_SD_HSD		0x00000005U
+#define SD0_OTAPDLYSEL_EMMC_HSD		0x00000006U
+
+#define SD1_OTAPDLYSEL_HS200_B0		0x00030000U
+#define SD1_OTAPDLYSEL_HS200_B2		0x00020000U
+#define SD1_ITAPDLYSEL_SD50			0x00140000U
+#define SD1_OTAPDLYSEL_SD50			0x00030000U
+#define SD1_ITAPDLYSEL_SD_DDR50		0x003D0000U
+#define SD1_ITAPDLYSEL_EMMC_DDR50	0x00120000U
+#define SD1_OTAPDLYSEL_SD_DDR50		0x00040000U
+#define SD1_OTAPDLYSEL_EMMC_DDR50	0x00060000U
+#define SD1_ITAPDLYSEL_HSD			0x00150000U
+#define SD1_OTAPDLYSEL_SD_HSD		0x00050000U
+#define SD1_OTAPDLYSEL_EMMC_HSD		0x00060000U
+
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+	XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+*		u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+	XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+		(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+	XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+	u32 Reg;
+	BaseAddress += RegOffset & 0xFC;
+	Reg = XSdPs_In32(BaseAddress);
+	Reg >>= ((RegOffset & 0x3)*8);
+	return (u16)Reg;
+#else
+	return XSdPs_In16((BaseAddress) + (RegOffset));
+#endif
+}
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u16 RegisterValue)
+*
+******************************************************************************/
+
+static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+	u32 Reg;
+	BaseAddress += RegOffset & 0xFC;
+	Reg = XSdPs_In32(BaseAddress);
+	Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8));
+	Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+	XSdPs_Out32(BaseAddress, Reg);
+#else
+	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset)
+{
+#if defined (__MICROBLAZE__)
+	u32 Reg;
+	BaseAddress += RegOffset & 0xFC;
+	Reg = XSdPs_In32(BaseAddress);
+	Reg >>= ((RegOffset & 0x3)*8);
+	return (u8)Reg;
+#else
+	return XSdPs_In8((BaseAddress) + (RegOffset));
+#endif
+}
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue)
+{
+#if defined (__MICROBLAZE__)
+	u32 Reg;
+	BaseAddress += RegOffset & 0xFC;
+	Reg = XSdPs_In32(BaseAddress);
+	Reg &= ~(0xFF<<((RegOffset & 0x3)*8));
+	Reg |= RegisterValue <<((RegOffset & 0x3)*8);
+	XSdPs_Out32(BaseAddress, Reg);
+#else
+	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue));
+#endif
+}
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
new file mode 100644
index 0000000..4894754
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_options.c
@@ -0,0 +1,1760 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+* @addtogroup sdps_v3_5
+* @{
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 2.8   sk     04/20/16 Added new workaround for auto tuning.
+* 3.0   sk     07/07/16 Used usleep API for both arm and microblaze.
+*       sk     07/16/16 Added support for UHS modes.
+*       sk     07/16/16 Added Tap delays accordingly to different SD/eMMC
+*                       operating modes.
+* 3.1   mi     09/07/16 Removed compilation warnings with extra compiler flags.
+*       sk     11/07/16 Enable Rst_n bit in ext_csd reg if not enabled.
+*       sk     11/16/16 Issue DLL reset at 31 iteration to load new zero value.
+* 3.2   sk     02/01/17 Added HSD and DDR mode support for eMMC.
+*       sk     02/01/17 Consider bus width parameter from design for switching
+*       vns    02/09/17 Added ARMA53_32 support for ZynqMP CR#968397
+*       vns    03/13/17 Fixed MISRAC mandatory violation
+*       sk     03/20/17 Add support for EL1 non-secure mode.
+* 3.3   mn     07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits
+*       mn     08/07/17	Properly set OTAPDLY value by clearing previous bit
+* 			settings
+*       mn     08/17/17 Added CCI support for A53 and disabled data cache
+*                       operations when it is enabled.
+*       mn     08/22/17 Updated for Word Access System support
+* 3.4   mn     01/22/18 Separated out SDR104 and HS200 clock defines
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+#include "sleep.h"
+#if defined (__aarch64__)
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+#define UHS_SDR12_SUPPORT	0x1U
+#define UHS_SDR25_SUPPORT	0x2U
+#define UHS_SDR50_SUPPORT	0x4U
+#define UHS_SDR104_SUPPORT	0x8U
+#define UHS_DDR50_SUPPORT	0x10U
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType);
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+static void XSdPs_DllReset(XSdPs *InstancePtr);
+#endif
+
+extern u16 TransferMode;
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	BlkSize - Block size passed by the user.
+*
+* @return	None
+*
+******************************************************************************/
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+	s32 Status;
+	u32 PresentStateReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+
+	if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
+			(u32)XSDPS_PSR_INHIBIT_DAT_MASK |
+			(u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/* Set block size to the value passed */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			 BlkSize & XSDPS_BLK_SIZE_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SCR - buffer to store SCR register returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+	s32 Status;
+	u32 StatusReg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+		SCR[LoopCnt] = 0U;
+	}
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	BlkCnt = XSDPS_SCR_BLKCNT;
+	BlkSize = XSDPS_SCR_BLKSIZE;
+
+	/* Set block size to the value passed */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * check for bus width for 3.0 controller and return if
+	 * bus width is <4
+	 */
+	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+			(InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) {
+		Status = XST_SUCCESS;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+				0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+
+		Arg = ((u32)InstancePtr->BusWidth);
+
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+
+		if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+				&& (InstancePtr->CardType == XSDPS_CHIP_EMMC) &&
+				(InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) {
+			/* in case of eMMC data width 8-bit */
+			InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
+		} else {
+			InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+		}
+
+		if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+			if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+				Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG;
+			else
+				Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+		} else {
+			if (InstancePtr->Mode == XSDPS_DDR52_MODE)
+				Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG;
+			else
+				Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+		}
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Check for transfer complete */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	}
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+
+	/* Width setting in controller */
+	if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+		StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+	} else {
+		StatusReg |= XSDPS_HC_WIDTH_MASK;
+	}
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			(u8)StatusReg);
+
+	if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL2_OFFSET);
+		StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+		StatusReg |= InstancePtr->Mode;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET, StatusReg);
+	}
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store function group support data
+*		returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64] = {0U};
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+		BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+		BlkSize &= XSDPS_BLK_SIZE_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+		XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+		if (InstancePtr->Config.IsCacheCoherent == 0) {
+			Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+		}
+
+		TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+		Arg = XSDPS_SWITCH_CMD_HS_SET;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 * Polling for response for now
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 50 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+
+	} else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
+		Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 52 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+			Arg = XSDPS_MMC_HS200_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
+		} else if (InstancePtr->Mode == XSDPS_DDR52_MODE) {
+			Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK;
+		} else {
+			Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+			InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK;
+		}
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if (InstancePtr->Mode == XSDPS_HS200_MODE) {
+			Status = XSdPs_Execute_Tuning(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+	StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SelFreq - Clock frequency in Hz.
+*
+* @return	None
+*
+* @note		This API will change clock frequency to the value less than
+*		or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+	u16 ClockReg;
+	u16 DivCnt;
+	u16 Divisor = 0U;
+	u16 ExtDivisor;
+	s32 Status;
+	u16 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) &&
+			(InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12))
+		/* Program the Tap delays */
+		XSdPs_SetTapDelay(InstancePtr);
+#endif
+		/* Calculate divisor */
+		for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt >> 1;
+				break;
+			}
+		}
+
+		if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		/* Calculate divisor */
+		DivCnt = 0x1U;
+		while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt / 2U;
+				break;
+			}
+			DivCnt = DivCnt << 1U;
+		}
+
+		if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/* Set clock divisor */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
+		XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
+
+		ExtDivisor = Divisor >> 8;
+		ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
+		ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	} else {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	}
+
+	/* Wait for internal clock to stabilize */
+	ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);;
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Pullup(XSdPs *InstancePtr)
+{
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store EXT_CSD
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg = 0U;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+	}
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	/* Send SEND_EXT_CSD command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to write EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Arg is the argument to be sent along with the command
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg)
+{
+	s32 Status;
+	u32 StatusReg;
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/*
+			 * Write to clear error bits
+			 */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to Identify the supported UHS mode. This API will assign the
+* corresponding tap delay API to the Config_TapDelay pointer based on the
+* supported bus speed.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff contains the response for CMD6
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104;
+		InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50;
+		InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50;
+		InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay;
+	}
+	else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) &&
+		(InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) {
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25;
+		InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay;
+	}
+	else
+		InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12;
+}
+
+/*****************************************************************************/
+/**
+*
+* API to UHS-I mode initialization
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Mode UHS-I mode
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
+{
+	s32 Status;
+	u16 StatusReg;
+	u16 CtrlReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64] = {0U};
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Drive strength */
+
+	/* Bus speed mode selection */
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	if (InstancePtr->Config.IsCacheCoherent == 0) {
+		Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+	}
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK;
+
+	switch (Mode) {
+	case 0U:
+		Arg = XSDPS_SWITCH_CMD_SDR12_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
+		break;
+	case 1U:
+		Arg = XSDPS_SWITCH_CMD_SDR25_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
+		break;
+	case 2U:
+		Arg = XSDPS_SWITCH_CMD_SDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
+		break;
+	case 3U:
+		Arg = XSDPS_SWITCH_CMD_SDR104_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
+		break;
+	case 4U:
+		Arg = XSDPS_SWITCH_CMD_DDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
+		break;
+	default:
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+		break;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+
+	/* Current limit */
+
+	/* Set UHS mode in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+	CtrlReg |= Mode;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/* Change the clock frequency */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+	if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+	}
+
+	if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+			(Mode == XSDPS_UHS_SPEED_MODE_SDR50)) {
+		/* Send tuning pattern */
+		Status = XSdPs_Execute_Tuning(InstancePtr);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+#endif
+
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 BlkSize;
+	u16 CtrlReg;
+	u8 TuningCount;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
+	if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
+	{
+		BlkSize = BlkSize*2U;
+	}
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	TransferMode = 	XSDPS_TM_DAT_DIR_SEL_MASK;
+
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/*
+	 * workaround which can work for 1.0/2.0 silicon for auto tuning.
+	 * This can be revisited for 3.0 silicon if necessary.
+	 */
+	/* Wait for ~60 clock cycles to reset the tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
+	for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
+
+		if (InstancePtr->CardType == XSDPS_CARD_SD) {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
+		} else {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
+		}
+
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
+			break;
+		}
+
+		if (TuningCount == 31) {
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+			/* Issue DLL Reset to load new SDHC tuned tap values */
+			XSdPs_DllReset(InstancePtr);
+#endif
+		}
+	}
+
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for ~12 clock cycles to synchronize the new tap values */
+	(void)usleep(1U);
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+	/* Issue DLL Reset to load new SDHC tuned tap values */
+	XSdPs_DllReset(InstancePtr);
+#endif
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH: return Status;
+
+}
+
+#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32)
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR104 and HS200 modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		if (Bank == 2)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+		if (Bank == 2)
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		if (Bank == 2)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+		if (Bank == 2)
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B2;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_HS200_B0;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for SDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+	(void) CardType;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50,
+				0, 0, 0, 0, 0);
+#else
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+		TapDelay |= SD0_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) |
+				((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50,
+				0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+		TapDelay |= SD1_OTAPDLYSEL_SD50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for DDR50 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType== XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+					(u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32),
+					(u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType== XSDPS_CARD_SD)
+			TapDelay |= SD0_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		if (CardType== XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+					(u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32),
+					(u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_ITAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_DDR50;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay for HSD and SDR25 mode
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType)
+{
+	u32 TapDelay;
+	(void) Bank;
+
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32),
+					(u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD0_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD0_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD0_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD0_OTAPDLY_SEL_MASK;
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD0_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+	} else {
+#endif
+		(void) DeviceId;
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)TapDelay;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD,
+				0, 0, 0, 0, 0);
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) |
+				((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0);
+		if (CardType == XSDPS_CARD_SD)
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0);
+		else
+			Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+					SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32),
+					(u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0);
+#else
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+		TapDelay |= SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the ITAPDLY */
+		TapDelay |= SD1_ITAPDLYENA;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay |= SD1_ITAPDLYSEL_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		TapDelay &= ~SD1_ITAPCHGWIN;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+		/* Program the OTAPDLY */
+		TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY);
+		TapDelay &= ~SD1_OTAPDLY_SEL_MASK;
+		if (CardType == XSDPS_CARD_SD)
+			TapDelay |= SD1_OTAPDLYSEL_SD_HSD;
+		else
+			TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay w.r.t speed modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetTapDelay(XSdPs *InstancePtr)
+{
+	u32 DllCtrl, BankNum, DeviceId, CardType;
+
+	BankNum = InstancePtr->Config.BankNumber;
+	DeviceId = InstancePtr->Config.DeviceId ;
+	CardType = InstancePtr->CardType ;
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	if (DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#endif
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+		InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType);
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+#ifdef XPAR_PSU_SD_0_DEVICE_ID
+	}
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* API to reset the DLL
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XSdPs_DllReset(XSdPs *InstancePtr)
+{
+	u32 ClockReg, DllCtrl;
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	/* Issue DLL Reset to load zero tap values */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)SD0_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl |= SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)SD1_DLL_RST, 0, 0, 0, 0, 0);
+#else
+		DllCtrl |= SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	}
+
+	/* Wait for 2 micro seconds */
+	(void)usleep(2U);
+
+	/* Release the DLL out of reset */
+	DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+	if (InstancePtr->Config.DeviceId == 0U) {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	} else {
+#if EL1_NONSECURE && defined (__aarch64__)
+		(void)DllCtrl;
+		Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR +
+				SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32),
+				(u64)0x0, 0, 0, 0, 0, 0);
+#else
+		DllCtrl &= ~SD1_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+#endif
+	}
+
+	/* Wait for internal clock to stabilize */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+}
+#endif
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
new file mode 100644
index 0000000..62bbfc0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/sdps_v3_5/src/xsdps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v3_5
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+	XSdPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSdPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c
new file mode 100644
index 0000000..cf59888
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_exit.c
@@ -0,0 +1,44 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/* _exit - Simple implementation. Does not return.
+*/
+__attribute__((weak)) void _exit (sint32 status)
+{
+  (void)status;
+  while (1) {
+	;
+  }
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c
new file mode 100644
index 0000000..a108b77
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_open.c
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+  (void)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
new file mode 100644
index 0000000..967bdfc
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/_sbrk.c
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+  static u8 *heap = NULL;
+  u8 *prev_heap;
+  static u8 *HeapEndPtr = (u8 *)&_heap_end;
+  caddr_t Status;
+
+  if (heap == NULL) {
+    heap = (u8 *)&_heap_start;
+  }
+  prev_heap = heap;
+
+  	if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) {
+  heap += incr;
+	  Status = (caddr_t) ((void *)prev_heap);
+  	} else {
+	  Status = (caddr_t) -1;
+  }
+
+  return Status;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c
new file mode 100644
index 0000000..e8988c0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/abort.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include 
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+  _exit(1);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
new file mode 100644
index 0000000..9427ad0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/bspconfig.h
@@ -0,0 +1,45 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
new file mode 100644
index 0000000..0dab3e9
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/changelog.txt
@@ -0,0 +1,549 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ---------------------------------------------------
+  * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ *                     cacheable regions
+ *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ *                     generated by the cpu driver, for enabling caches
+ * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
+ *                     write-thru caches
+ * 3.03a sdm  08/20/11 Updated the tag/data RAM latency values for L2CC
+ *		       Updated the MMU table to mark OCM in high address space
+ *		       as inner cacheable and reserved space as Invalid
+ * 3.03a sdm  08/20/11 Changes to support FreeRTOS
+ *		       Updated the MMU table to mark upper half of the DDR as
+ *		       non-cacheable
+ *		       Setup supervisor and abort mode stacks
+ *		       Do not initialize/enable L2CC in case of AMP
+ *		       Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm  08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ *		       in case of AMP
+ * 3.03a sdm  09/14/11 Added code for performance monitor and L2CC event
+ *		       counters
+ * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include
+ *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
+ *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ *		       for MicroBlaze will invalidate data in the cache instead
+ *		       of flushing it for writeback caches
+ * 3.04a sdm  11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm  01/02/12 Updated to clear cp15 regs with unknown reset values
+ *		       Remove redundant dsb/dmb instructions in cache maintenance
+ *		       APIs
+ *		       Remove redundant dsb in mcr instruction
+ * 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm  02/02/12 Removed some of the defines as they are being generated through
+ *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
+ *                     for the QSPI complete address range - DT644567
+ *                     Removed profile directory for armcc compiler and changed
+ *                     profiling setting to false in standalone_v2_1_0.tcl file
+ *                     Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ *		       invalidate the caches before enabling back the MMU and
+ *		       D cache.
+ * 3.05a asa  04/15/12 Updated the function Xil_SetTlbAttributes in file
+ *		       xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ *		       array, flush the D-cache before changing the attributes
+ *		       in translation table. The user need not call Xil_DisableMMU
+ *		       before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ *	 sgd	       initialization is present. Changes for this were done in
+ *		       uart.c and xil-crt0.s.
+ *		       Made changes in xil_io.c to use volatile pointers.
+ *		       Made changes in xil_mmu.c to correct the function
+ *		       Xil_SetTlbAttributes.
+ *		       Changes are made xil-crt0.s to initialize the static
+ *		       C++ constructors.
+ *		       Changes are made in boot.s, to fix the TTBR settings,
+ *		       correct the L2 Cache Auxiliary register settings, L2 cache
+ *		       latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ *	 sgd	       usleep.c to use global timer intstead of CP15.
+ *		       Made changes in cortexa9/gcc/translation_table.s to map
+ *		       the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/boot.S to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/translation_table.s to
+ *		       map the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/boot.S to optimize the
+ *		       L2 cache settings. Changes the section properties for
+ *		       ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ *			and cortexa9/gcc/translation_table.S.
+ *		       Made changes in cortexa9/xil_cache.c to change the
+ *		       cache invalidation order.
+ * 3.07a asa  08/17/12 Made changes across files for Cortexa9 to remove
+ *		       compilation/linking issues for C++ compiler.
+ *		       Made changes in mb_interface.h to remove compilation/
+ *		       linking issues for C++ compiler.
+ *		       Added macros for swapb and swaph microblaze instructions
+ *		       mb_interface.h
+ *		       Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ *		       for CortexA9.
+ * 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa  08/31/12 Added xil_printf.h include
+ * 3.07a sgd  09/18/12 Corrected the L2 cache enable settings
+ *				Corrected L2 cache sequence disable sequence
+ * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa  01/25/13 Updated to push and pop neon registers into stack for
+ *		       irq/fiq handling.
+ *		       Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ *		       fixes the CR #692094.
+ * 3.09a sgd  02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt  04/18/13 Implemented ARM Erratas.
+ *		       Cortex A9 Errata - 742230, 743622, 775420, 794073
+ *		       L2Cache PL310 Errata - 588369, 727915, 759370
+ *		       Please refer to file 'xil_errata.h' for errata
+ *		       description.
+ * 3.10a asa  05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ *		       cache APIs were corresponding to only Layer 1 cache
+ *		       memories. New APIs were now added and the existing cache
+ *		       related APIs were changed to provide a uniform interface
+ *		       to flush/invalidate/enable/disable the complete cache
+ *		       system which includes both L1 and L2 caches. The changes
+ *		       for these were done in:
+ *		       src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ *		       files.
+ *		       Four new files were added for supporting L2 cache. They are:
+ *		       microblaze_flush_cache_ext.S-> Flushes L2 cache
+ *		       microblaze_flush_cache_ext_range.S -> Flushes a range of
+ *		       memory in L2 cache.
+ *		       microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ *		       microblaze_invalidate_cache_ext_range -> Invalidates a
+ *		       range of memory in L2 cache.
+ *		       These changes are done to implement PR #697214.
+ * 3.10a  asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ *		       fix the CR #706464. L2 cache disabling happens independent
+ *		       of L1 data cache disable operation. Changes are done in the
+ *		       same file in cache handling APIs to do a L2 cache sync
+ *		       (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa  05/20/13 Added API/Macros for enabling and disabling nested
+ *		       interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt  05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ *		       sync operation. This fixes the CR# 716781.
+ * 3.11a asa  09/07/13 Updated armcc specific BSP files to have proper support
+ *		       for armcc toolchain.
+ *		       Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ *		       fix issues related to NEON context saving. The assembly
+ *		       routines for IRQ and FIQ handling are modified.
+ *		       Deprecated the older BSP (3.10a).
+ * 3.11a asa  09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ *		       various potential issues. Made changes in the function
+ *		       Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa  09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ *		       in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa  09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ *		       L2 cache sync operation and to fix issues around complete
+ *		       L2 cache flush/invalidation by ways.
+ * 3.12a asa  10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ *		       to fix linking issues with armcc/DS-5. Modified the armcc
+ *		       makefile to fix issues.
+ * 3.12a asa  11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0   hk   12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 	 pkp  22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ *		       and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ *		       src\cortexa9\armcc\) to fix CR#767251
+ * 4.0	 pkp  24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ *		       Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ *		       Few cache lines were missed to invalidate when unaligned address
+ *		       invalidation was accommodated in Xil_DCacheInvalidateRange.
+ *		       In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ *		       stack memory (which contains return address) was invalidated. So
+ *		       stack memory is flushed first and then L1D cache is invalidated.
+ *		       This is done to fix CR #763829
+ * 4.0 adk   22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ *			mblaze_nt_types.h file and replace uint32_t with u32 in the
+ *			profile_hist.c to fix the above CR.
+ * 4.1 bss   04/14/14  Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * 		       instead of libxil.a and added prototypes for
+ *		       microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ *		       mb_interface.h
+ * 4.1 hk    04/18/14  Add sleep function.
+ * 4.1 asa   04/21/14  Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ *		       some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa   04/28/14  Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss   04/29/14  Modified driver tcl to use libxil.a if libgloss.a does not exist
+ *			CR#794205
+ * 4.1 asa   05/09/14  Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ *		       common/xil_testcache.c
+ *	               Fix for CR#764881.
+ * 4.1 srt   06/27/14  Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ *                     output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp   06/27/14  Added support for IAR compiler in src/cortexa9/iccarm.
+ *		       Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp   06/19/14  Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ *		       cortexa9/armcc/boot.s. Added default exception handlers for data
+ *		       abort and prefetch abort using handlers called
+ *		       DataAbortHandler and PrefetchAbortHandler respectively in
+ *		       cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp   06/30/14  MakeFile for cortexa9/armcc has been changed to fixes the
+ *		       issue of improper linking of translation_table.s
+ * 4.2 pkp   07/04/14  added weak attribute for the function in BSP which are also present
+ *		       in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp   07/21/14  Corrected reset value of event counter in function
+ *		       Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp   07/21/14  Included xil_types.h file in xil_mmu.h which had contained a function
+ * 		       containing type def u32 defined in xil_types.g to resolve issue of
+ *		       CR#805869
+ * 4.2 pkp   08/04/14  Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ *		       it is not possible to generate timer in nanosecond due to limited
+ *		       cpu frequency
+ * 4.2 pkp   08/04/14  Removed PEEP board related code which contained initialization of
+ *		       uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ *		       and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ *		       removed function definition of XSmc_NorInit and XSmc_NorInit from
+ *		       cortexa9/smc.h
+ * 4.2 bss   08/11/14  Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ *		       cache_ext_range declarations in mb_interface.h CR#783821.
+ *		       Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp   08/21/14  modified makefile of iccarm for proper linking of objectfiles in
+ *		       cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp   09/02/14  modified translation table entries in cortexa9/gcc/translation_table.s,
+ *		       armcc/translation_table.s and iccarm/translation_table.s
+ *		       to properly defined reserved entries according to address map for
+ *		       fixing CR#820146
+ * 4.2 pkp   09/11/14  modified translation table entries in cortexa9/iccarm/translation_table.s
+ *		       and  cortexa9/armcc/translation_table.s to resolve compilation
+ *		       error for solving CR#822897
+ * 5.0 kvn   12/9/14   Support for Zync Ultrascale Mp.Also modified code for
+ *                     MISRA-C:2012 compliance.
+ * 5.0 pkp   12/15/14  Added APIs to get information about the platforms running the code by
+ *		       adding src/common/xplatform_info.*s
+ * 5.0 pkp   16/12/14  Modified boot code to enable scu after MMU is enabled and
+ *		       removed incorrect initialization of TLB lockdown register to fix
+ *		       CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ *		       and iccarm/boot.s
+ * 5.0 pkp   25/02/15  Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ *		       for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp   05/13/15  Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ *		       and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ *		       caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ *		       of L2Cache is done later.
+ * 5.1 pkp   12/05/15  Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ *		       Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ *		       taking long time to fix CR#853097. L2CacheSync is added into
+ *		       Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ *		       Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ *		       instead of just System Stack
+ * 5.1 pkp   14/05/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS and also take the compiler and archiver as specified
+ *		       in settings instead of hardcoding it.
+ * 5.2 pkp   06/08/15  Modified cortexa9/gcc/translation_table.S to put a check for
+ *		       XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ *		       accordingly generate the	translation table
+ * 5.2 pkp   23/07/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS to fix a bug introduced during new version creation
+ *		       of BSP.
+ * 5.3 pkp   10/07/15  Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ *		       functionalities are avoided for the OpenAMP slave application(when
+ *		       USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ *		       cache for its operation. Also file operations such as read, write,
+ *		       close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ *		       defined for BSP) because XilOpenAMP library contains own file operation.
+ *		       The xil-crt0.S file is modified for not initializing global timer for
+ *		       OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp   10/09/15  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ *		       definition for dsb, isb and dmb to fix the compilation error when used
+ *     kvn   16/10/15  Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp   09/11/15  Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ *		       R5 deadlock for errata 780125
+ * 5.4 pkp   09/11/15  Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ *		       32 bit BSP in the initialization
+ * 5.4 pkp   09/11/15  Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ * 5.4 pkp   16/11/15  Modified microblaze/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ *     kvn   21/11/15  Added volatile keyword for ADDR varibles in Xil_Out API
+ *     kvn   21/11/15  Changed ADDR variable type from u32 to UINTPTR. This is
+ *                     required for MISRA-C:2012 Compliance.
+ * 5.4 pkp   23/11/15  Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ *		       in cortexa9/xil_mmu.h
+ * 5.4 pkp   23/11/15  Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp   11/12/15  Modified common/xplatform_info.h to add #defines for silicon for
+ *		       checking the current executing platform
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ *		       to initialize global constructor for C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ *		       C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ *		       translation_table.S to update the translation table according to proper
+ *		       address map
+ * 5.4 pkp   18/12/15  Modified cortexar5/mpu.c to initialize the MPU according to proper
+ *		       address map
+ * 5.4	pkp  05/01/16  Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ *		       equivalent to vector table base address
+ * 5.4 pkp   08/01/16  Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ *		       as per the toolchain update
+ * 5.4 pkp   12/01/16  Changed common/xplatform_info.* to add platform information support
+ *		       for Cortex-A53 32bit mode
+ * 5.4 pkp   28/01/16  Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ *		       and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ *		       instead take it from xparameters.h to properly configure the timestamp
+ *		       clock frequency
+ * 5.4 asa   29/01/16  Modified microblaze/mb_interface.h to add macros that support the
+ *		       new instructions for MB address extension feature
+ * 5.4 kvn   30/01/16  Modified xparameters_ps.h file to add interrupt ID number for
+ *		       system monitor.
+ * 5.4 pkp   04/02/16  Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp   19/02/16  Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ *		       cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ *		       cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ *		       use set of assembly instructions to provide required delay to fix
+ *		       CR#913249.
+ * 5.4 asa   25/02/16  Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ *		       _exit with exit. We should not be directly calling _exit and should
+ *		       always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp   25/02/16  Made change to cortexr5/gcc/boot.S to initialize the floating point
+ *		       registers, banked registers for various modes and enabled
+ *		       the cache ECC check before enabling the fault log for lock step mode
+ *		       Also modified the cortexr5/gcc/Makefile to support floating point
+ *		       registers initialization in boot code.
+ * 5.4 pkp   03/01/16  Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ *		       logic in case of lock-step mode when fault log is enabled to fix
+ *		       CR#938281
+ * 5.4 pkp   03/02/16  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ *		       header file instrinsics.h which contains assembly instructions
+ *		       definitions which can be used by C
+ * 5.4 asa   03/02/16  Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ *                     proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp   03/09/16  Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ *		       interrupts when sleep/usleep is being executed using assembly
+ *		       instructions to fix CR#913249.
+ * 5.4 pkp   03/11/16  Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ *		       instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ *		       value and compare it with previous value to detect the overflow
+ *		       to fix CR#940209.
+ * 5.4 pkp   03/24/16  Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ *		       the fault log to avoid intervention for lock-step mode and cortexr5/
+ *		       _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ *		       to fix CR#947335
+ * 5.5 pkp   04/11/16  Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode
+ *		       in lock-step to avoid resetting the debug logic which restricts the
+ *		       access for debugger and removed enabling back of debug modules in
+ *		       cortexr5/_exit.c
+ * 5.5 pkp   04/13/16  Modified cortexa9/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c
+ *		       to return correct number of bytes when read buffer is filled and
+ *		       removed the redundant NULL checking for buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexr5/gcc/read.c to return correct number of bytes when
+ *		       read buffer is filled and removed the redundant NULL checking for
+ *		       buffer to simplify the code
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm
+ *		       instruction macros to disable certain optimizations which may move
+ *		       code out of loops if optimizers believe that the code will always
+ *		       return the same result or discard asm statements if optimizers
+ *		       determine there is no need for the output variables
+ * 5.5 pkp   04/13/16  Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/64bit/
+ *		       sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which
+ *		       starts the timer if it is disabled and modified XTime_GetTime to
+ *		       enable the timer if it is not enabled. Also modified cortexa53/32bit/
+ *		       sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is
+ *		       disabled and read the counter value directly from register instead
+ *		       of using XTime_GetTime for optimization
+ * 5.5 pkp   04/13/16  Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c
+ *		       to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and
+ * 		       Xil_DCacheInvalidateRange functions description for proper
+ *		       explaination to fix CR#949801
+ * 5.5 asa   04/20/16  Added missing macros for hibernate and suspend in Microblaze BSP
+ *                     file mb_interface.h. This fixes the CR#949503.
+ * 5.5 asa   04/29/16  Fix for CR#951080. Updated cache APIs for HW designs where cache
+ *                     memory is not included for MicroBlaze.
+ * 5.5 pkp   05/06/16  Modified the cortexa9/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 5.5 pkp   05/06/16  Modified the cortexr5/xil_exception.h to update the macros
+ *		       Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing
+ *		       the issue of lr being corrupted to resolve CR#950468
+ * 6.0 kvn   05/31/16  Make Xil_AsserWait a global variable
+ * 6.0 pkp   06/27/16  Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot
+ *		       section since it is part of boot process to fix CR#949555
+ *     hk    07/12/16  Correct masks for IOU SLCR GEM registers
+ * 6.0 pkp   07/25/16  Program the counter frequency in boot code for CortexA53
+ * 6.0 asa   08/03/16  Updated sleep_common function in microblaze_sleep.c to improve the
+ *                     the accuracy of MB sleep functionality. This fixes the CR#954191.
+ * 6.0 mus   08/03/16  Restructured the BSP to avoid code duplication across all BSPs.
+ *                     Source code directories specific to ARM processor's are moved to src/arm
+ *                     directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53,
+ *                     src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h,
+ *                     print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and
+ *                     consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h,
+ *                     xil_exception.c and xil_exception.h are consolidated across all ARM BSPs
+ *                     into common file each and consolidated files are kept at src/arm/common directory.
+ *                     GCC source files related to file  operations are consolidated and kept
+ *                     at src/arm/common/gcc directory.
+ *                     All io interfacing functions (i.e. All variants of xil_out, xil_in )
+ *                     are made as static inline and implementation is kept in consolidated common/xil_io.h,
+ *                     xil_io.h must be included as a header file to access io interfacing functions.
+ *                     Added undefined exception handler for A53 32 bit and R5 processor
+ * 6.0 mus   08/11/16  Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since
+ *                     TTC counter value register is read only.
+ * 6.0 asa   08/15/16  Modified the signatures for functions sleep and usleep. This fixes
+ *                     the CR#956899.
+ * 6.0 mus   08/18/16  Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag
+ *                     in cortexr5/xparameters_ps.h
+ * 6.0 mus   08/18/16  Added support for the the Zynq 7000s devices
+ * 6.0 mus   08/18/16  Removed unused variables from xil_printf.c and xplatform_info.c
+ * 6.0 mus   08/19/16  Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors
+ * 6.1 mus   11/03/16  Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl.
+ *                     ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
+ *                     these APIs and modifications are done on top of it to handle stdout/stdin
+ *                     parameters for design which doesnt have UART.It fixes CR#953681
+ * 6.1 nsk   11/07/16  Added two new files xil_mem.c and xil_mem.h for xil_memcpy
+ * 6.2 pkp   12/14/16  Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
+ *		       0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
+ *		       and rest of the memory in that 32GB region is marked as reserved to avoid
+ *		       any speculative access
+ * 6.2 pkp   12/23/16  Added support for floating point operation to Cortex-A53 64bit mode. It modified
+ *		       asm_vectors.S to implement lazy floating point context saving i.e. floating point
+ *		       access is enabled if there is any floating point operation, it is disabled by
+ *		       default. Also FPU is initally disabled for IRQ and none of the floating point
+ *		       registers are saved during normal context saving. If IRQ handler does not require
+ *		       floating point operation, the floating point registers are untouched and no need
+ *		       for saving/restoring. If IRQ handler uses any floating point operation, then floating
+ *		       point registers are saved and FPU is enabled for IRQ handler. Then floating point
+ *		       registers are restored back after servicing IRQ during normal context restoring.
+ * 6.2 mus   01/01/17  Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
+ *                     target.It fixes the CR#966900
+ * 6.2 pkp   01/22/17  Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
+ *		       64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
+ *		       for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
+ *		       as false i.e. default bsp is EL3.
+ * 6.2 pkp   01/24/17  Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
+ *		       contains initial status of FPU i.e. disabled. In case of a warm restart execution
+ *		       when bss sections are not cleared, it may contain previously updated value which
+ *		       does not hold true once processor resumes. This fixes CR#966826.
+ * 6.2 asa   01/31/17  The existing Xil_DCacheDisable API first flushes the
+ *		       D caches and then disables it. The problem with that is,
+ *		       potentially there will be a small window after the cache
+ *		       flush operation and before the we disable D caches where
+ *		       we might have valid data in cache lines. In such a
+ *		       scenario disabling the D cache can lead to unknown behavior.
+ *		       The ideal solution to this is to use assembly code for
+ *		       the complete API and avoid any memory accesses. But with
+ *		       that we will end up having a huge amount on assembly code
+ *		       which is not maintainable. Changes are done to use a mix
+ *		       of assembly and C code. All local variables are put in
+ *		       registers. Also function calls are avoided in the API to
+ *		       avoid using stack memory.
+ * 6.2 mus   02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
+ *                    scenarios when an invalidated cache line can get pre fetched to cache.
+ *                    If that happens, the coherency between cache and memory is lost
+ *                    resulting in lost data. To avoid this kind of issue either
+ *                    user has to use dsb() or disable pre-fetching for L1 cache
+ *                    or else reduce maximum number of outstanding data prefetches allowed.
+ *                    Using dsb() while comparing data costing more performance compared to
+ *                    disabling pre-fetching/reducing maximum number of outstanding data
+ *                    prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
+ *                    to disable pre-fetching/configure maximum number of outstanding data
+ *                    prefetches allowed in L1 cache system.This fixes CR#967864.
+ * 6.2 pkp   02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
+ *		      used by cortex-A53 64bit EL1 Non-secure application.
+ * 6.2 kvn   03/03/17 Added support thumb mode
+ * 6.2 mus   03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
+ *                    It fixes CR#970543
+ * 6.2 asa   03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
+ *                    profiling we see a crash. That is because the the tcl uses invalid
+ *                    HSI command. This change fixes it.
+ * 6.2 mus   03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
+ *                    any FPD peripheral is configured to use CCI.It fixes CR#972638
+ * 6.3 mus   03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
+ * 6.3 mus   04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
+ *                    the HW coherency enablement. It fixes the CR#973287
+ * 6.3 mus   04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
+ *                    L2CTLR_EL1 register. It fixes the CR#974698
+ * 6.4 mus   06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
+ *                    of ARM 32 bit processor's.
+ * 6.4 mus   06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in  IRQInterruptHandler code
+ *                    snippet, which checks for the FPEN bit of CPACR_EL1 register.
+ * 6.4 ms    05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
+ *                    XGetPSVersion_Info function for PMUFW.
+ *     ms    06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
+ *                    function for PMUFW.
+ * 6.4 mus   07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
+ * 6.4 mus   07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
+ *                    operations.Now,VFP is being enabled in FPEXC register, through boot code
+ *                    and FPU registers are being saved/restored when irq/fiq vector is invoked.
+ * 6.4 adk   08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
+ * 		      if h/w design configured with HPC port.
+ * 6.4 mus   08/10/17 Updated a53 64 bit translation table to mark  memory as a outer shareable for
+ *                    EL1 NS execution. This change has been done to support CCI enabled IP's.
+ * 6.4 mus   08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
+ *                    CR#982209.
+ * 6.4 asa   08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
+ *                    make RPU MPU handling user-friendly. This also fixes the CR-981028.
+ * 6.4 mus   08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
+ *                    version register through SMC call, over EL1 NS mode. This change has been done to
+ *                    support these APIs over EL1 NS mode.
+ * 6.5 mus   10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
+ *                    it fixes CR#987464.
+ * 6.6 mus   12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
+ *                    It fixes CR#989132.
+ *     srm   10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
+ *		      will use the timer specified by the user to provide delay. A9 and A53 can use
+ *                    Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
+ *                    machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
+ *		      to support the sleep configuration Added new API's for the Axi timer in
+ *		      microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
+ *		      xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
+ *		      xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
+ * 6.6 hk    12/15/17 Export platform macros to bspconfig.h based on the processor.
+ * 6.6 asa   1/16/18  Ensure C stack information for A9 are flushed out from L1 D cache
+ *                    or L2 cache only when the respective caches are enabled. This fixes CR-922023.
+ * 6.6 mus   01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
+ *                    after writing to cpacr_el1/cptr_el3 registers. It would ensure
+ *                    disabling/enabling of floating-point unit, before any subsequent
+ *                    instruction.
+ * 6.6 mus   01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
+ *                    support. Now, xil_printf would use PV console instead of UART in case of
+ *                    hypervisor enabled BSP.
+ * 6.6 mus   02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port 
+ *                    configured with smart interconnect.It fixes CR#990318.
+ * 6.6 srm   02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
+ * 6.6 asa   02/12/18 Fix for heap handling for ARM platforms. CR#993932.
+ * 6.6 mus   02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
+ *                    CR#995014.
+ * 6.6 mus   02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
+*		      non-JTAG boot mode, when processor is in lockstep configuration.
+*		      This behavior is restricting application debugging in non-JTAG boot
+*		      mode.  To get rid of this restriction, added new mld parameter 
+*		      "lockstep_mode_debug", to enable/disable debug logic from BSP 
+*		      settings. Now, debug logic can be enabled through BSP settings, 
+*		      by modifying value of parameter "lockstep_mode_debug" as "true".
+*		      It fixes CR#993896.
+ * 6.6.mus   02/27/18  Updated Xil_DCacheInvalidateRange and
+*		       Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix  bug
+*		       in handling upper DDR addresses.It fixes CR#995581.
+* 6.6 mus    03/12/18  Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
+*		       in the list of include paths. This change allows applications/BSP
+*		       files to include .h files in include_ps directory.
+* 6.6 mus    03/16/18  By default CPUACTLR_EL1 is accessible only from EL3, it
+*		       results into abort if accessed from EL1 non secure privilege
+*		       level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
+*		       to avoid CPUACTLR_EL1 access from privile levels other than EL3.
+* 6.6 mus    03/16/18  Updated hypervisor enabled BSP to use PV console, based on the
+*		       XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would
+*		       use UART console, PV console can be enabled by appending
+		       "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
+ *
+* 6.7 mus    04/27/18  Removed __ARM_NEON__ flag definition. Now, saving/restoring of of HW
+*		       floating point register would be done through newly introduced flag
+*		       FPU_HARD_FLOAT_ABI_ENABLED. This new flag will be configured based on
+*		       the -mfpu-abi option in extra compiler flags.. This change has
+*		       been done to avoid saving/restoring of HW floating point registers,
+*		       when BSP is not compiled with HW floating point configuration.
+* 6.7 asa    04/26/18  Added API Xil_GetExceptionRegisterHandler for obtaining information
+*                      on an already registered exception vector.
+* 6.7 asa    05/18/18  Fixed bugss in the API Xil_GetExceptionRegisterHandler.
+*
+ *****************************************************************************************/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c
new file mode 100644
index 0000000..dbbe0d4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/close.c
@@ -0,0 +1,49 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+  (void)fd;
+  return (0);
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c
new file mode 100644
index 0000000..df0218e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/errno.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+  return &_REENT->_errno;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c
new file mode 100644
index 0000000..e58221a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fcntl.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) sint32 fcntl (sint32 fd, sint32 cmd, long arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c
new file mode 100644
index 0000000..c5a31f3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/fstat.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c
new file mode 100644
index 0000000..d02df5c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/getpid.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+  return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+  return 1;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c
new file mode 100644
index 0000000..a5a6448
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif 
+
+char inbyte(void) {
+	 return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c
new file mode 100644
index 0000000..f142515
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/isatty.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ *           returns 0 if not. Since we're hooked up to a
+ *           serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c
new file mode 100644
index 0000000..fc2f89d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/kill.c
@@ -0,0 +1,60 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) int _kill(pid_t pid, int sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) int kill(pid_t pid, int sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
+
+__attribute__((weak)) int _kill(pid_t pid, int sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c
new file mode 100644
index 0000000..106c45c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/lseek.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek --  Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c
new file mode 100644
index 0000000..85e9ce4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/open.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef UNDEFINE_FILE_OPS
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
+{
+  (void)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c
new file mode 100644
index 0000000..3c64308
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c); 
+
+#ifdef __cplusplus
+}
+#endif 
+
+void outbyte(char c) {
+	 XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
new file mode 100644
index 0000000..da7e768
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/print.c
@@ -0,0 +1,36 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+	XPVXenConsole_Write(ptr);
+#else
+#ifdef STDOUT_BASEADDRESS
+  while (*ptr != (char8)0) {
+    outbyte (*ptr);
+	ptr++;
+  }
+#else
+(void)ptr;
+#endif
+#endif
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c
new file mode 100644
index 0000000..1d8aada
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_clean.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#include "xil_exception.h"
+
+void _profile_clean( void );
+
+/*
+ * This function is the exit routine and is called by the crtinit, when the
+ * program terminates. The name needs to be changed later..
+ */
+void _profile_clean( void )
+{
+	Xil_ExceptionDisable();
+	disable_timer();
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c
new file mode 100644
index 0000000..0ac51b1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_init.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_init.c:
+*	Initialize the Profiling Structures.
+*
+******************************************************************************/
+
+#include "profile.h"
+
+/* XMD Initializes the following Global Variables Value during Program
+ *  Download with appropriate values. */
+
+#ifdef PROC_MICROBLAZE
+
+extern s32 microblaze_init(void);
+
+#elif defined PROC_PPC
+
+extern s32 powerpc405_init(void);
+
+#else
+
+extern s32 cortexa9_init(void);
+
+#endif
+
+s32 profile_version = 1;	/* Version of S/W Intrusive Profiling library */
+
+u32 binsize = (u32)BINSIZE;    			/* Histogram Bin Size */
+u32 cpu_clk_freq = (u32)CPU_FREQ_HZ ;	/* CPU Clock Frequency */
+u32 sample_freq_hz = (u32)SAMPLE_FREQ_HZ ;	/* Histogram Sampling Frequency */
+u32 timer_clk_ticks = (u32)TIMER_CLK_TICKS ;/* Timer Clock Ticks for the Timer */
+
+/* Structure for Storing the Profiling Data */
+struct gmonparam *_gmonparam = (struct gmonparam *)(0xffffffffU);
+s32 n_gmon_sections = 1;
+
+/* This is the initialization code, which is called from the crtinit. */
+
+void _profile_init( void )
+{
+/* 	print("Gmon Init called....\r\n")  */
+/* 	putnum(n_gmon_sections) , print("\r\n")   */
+/* 	if( _gmonparam == 0xffffffff ) */
+/* 		printf("Gmonparam is NULL !!\r\n")  */
+/* 	for( i = 0, i < n_gmon_sections, i++ )[ */
+/* 		putnum( _gmonparam[i].lowpc) , print("\t")   */
+/* 		putnum( _gmonparam[i].highpc) , print("\r\n")  */
+/* 		putnum( _gmonparam[i].textsize ), print("\r\n")  */
+/* 		putnum( _gmonparam[i].kcountsize * sizeof(unsigned short)), print("\r\n")  */
+/* 	] */
+
+#ifdef PROC_MICROBLAZE
+	(void)microblaze_init();
+#elif defined PROC_PPC
+	powerpc405_init();
+#else
+	(void)cortexa9_init();
+#endif
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c
new file mode 100644
index 0000000..e85fb5c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.c
@@ -0,0 +1,387 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+*  _program_timer_hw.c:
+*	Timer related functions
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#include "xil_exception.h"
+
+#ifdef PROC_PPC
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+/* extern u32 timer_clk_ticks, */
+
+#ifdef PROC_PPC405
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_pit_init( void );
+#endif
+s32 powerpc405_init()
+#endif	/* PROC_CORTEXA9 */
+
+#ifdef PROC_PPC440
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void );
+#endif
+s32 powerpc405_init(void);
+#endif	/* PROC_PPC440 */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void );
+#endif
+
+#ifdef PROC_MICROBLAZE
+s32 microblaze_init(void);
+#endif	/* PROC_MICROBLAZE */
+
+#ifdef PROC_CORTEXA9
+s32 scu_timer_init( void );
+s32 cortexa9_init(void);
+#endif	/* PROC_CORTEXA9 */
+
+
+/*--------------------------------------------------------------------
+  * PowerPC Target - Timer related functions
+  *-------------------------------------------------------------------- */
+#ifdef PROC_PPC405
+
+
+/*--------------------------------------------------------------------
+* PowerPC PIT Timer Init.
+*	Defined only if PIT Timer is used for Profiling
+*
+*-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+int ppc_pit_init( void )
+{
+	/* 1. Register Profile_intr_handler as Interrupt handler */
+	/* 2. Set PIT Timer Interrupt and Enable it. */
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_PIT_INT,
+			    (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	XTime_PITSetInterval( timer_clk_ticks ) ;
+	XTime_PITEnableAutoReload() ;
+	return 0;
+}
+#endif
+
+
+/* --------------------------------------------------------------------
+* PowerPC Timer Initialization functions.
+*	For PowerPC, PIT and opb_timer can be used for Profiling. This
+*	is selected by the user in standalone BSP
+*
+*-------------------------------------------------------------------- */
+s32 powerpc405_init()
+{
+	Xil_ExceptionInit() ;
+	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+	/* Initialize the Timer.
+	  * 1. If PowerPC PIT Timer has to be used, initialize PIT timer.
+	  * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+	ppc_pit_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+	/* Initialize the timer with Timer Ticks */
+	opb_timer_init() ;
+#endif
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	  * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+	XTime_PITEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+	Xil_ExceptionEnableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+#endif
+	return 0;
+}
+
+#endif	/* PROC_PPC */
+
+
+
+/*--------------------------------------------------------------------
+  * PowerPC440 Target - Timer related functions
+  * -------------------------------------------------------------------- */
+#ifdef PROC_PPC440
+
+
+/*--------------------------------------------------------------------
+ * PowerPC DEC Timer Init.
+ *	Defined only if DEC Timer is used for Profiling
+ *
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+s32 ppc_dec_init( void )
+{
+	/* 1. Register Profile_intr_handler as Interrupt handler */
+	/* 2. Set DEC Timer Interrupt and Enable it. */
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_DEC_INT,
+			    (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	XTime_DECSetInterval( timer_clk_ticks ) ;
+	XTime_DECEnableAutoReload() ;
+	return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * PowerPC Timer Initialization functions.
+ *	For PowerPC, DEC and opb_timer can be used for Profiling. This
+ *	is selected by the user in standalone BSP
+ *
+ *-------------------------------------------------------------------- */
+s32 powerpc405_init(void)
+{
+	Xil_ExceptionInit();
+	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;
+
+	/* Initialize the Timer.
+	 * 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
+	 * 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC */
+#ifdef PPC_PIT_INTERRUPT
+	ppc_dec_init();
+#else
+#ifdef TIMER_CONNECT_INTC
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
+			      (Xil_ExceptionHandler)profile_intr_handler,NULL);
+#endif
+	/* Initialize the timer with Timer Ticks */
+	opb_timer_init() ;
+#endif
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	 * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef PPC_PIT_INTERRUPT
+	XTime_DECEnableInterrupt() ;
+#elif TIMER_CONNECT_INTC
+	XIntc_MasterEnable( INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+#endif
+	Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
+#endif
+	return 0;
+}
+
+#endif	/* PROC_PPC440 */
+
+/* --------------------------------------------------------------------
+ * opb_timer Initialization for PowerPC and MicroBlaze. This function
+ * is not needed if DEC timer is used in PowerPC
+ *
+ *-------------------------------------------------------------------- */
+/* #ifndef PPC_PIT_INTERRUPT */
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+s32 opb_timer_init( void )
+{
+	/* set the number of cycles the timer counts before interrupting */
+	XTmrCtr_SetLoadReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)timer_clk_ticks);
+
+	/* reset the timers, and clear interrupts */
+	XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0,
+				     (u32)XTC_CSR_INT_OCCURED_MASK | (u32)XTC_CSR_LOAD_MASK );
+
+	/* start the timers */
+	XTmrCtr_SetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)XTC_CSR_ENABLE_TMR_MASK
+			     | (u32)XTC_CSR_ENABLE_INT_MASK | (u32)XTC_CSR_AUTO_RELOAD_MASK | (u32)XTC_CSR_DOWN_COUNT_MASK);
+	return 0;
+}
+#endif
+
+
+/*--------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for MicroBlaze Target.
+ *	For MicroBlaze, opb_timer is used. The opb_timer can be directly
+ *	connected to MicroBlaze or connected through Interrupt Controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 microblaze_init(void)
+{
+	/* Register profile_intr_handler
+	 * 1. If timer is connected to Interrupt Controller, register the handler
+	 *    to Interrupt Controllers vector table.
+	 * 2. If timer is directly connected to MicroBlaze, register the handler
+	 *    as Interrupt handler */
+	Xil_ExceptionInit();
+
+#ifdef TIMER_CONNECT_INTC
+	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
+			     (XInterruptHandler)profile_intr_handler,NULL);
+#else
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				     (Xil_ExceptionHandler)profile_intr_handler,
+				     NULL) ;
+#endif
+
+	/* Initialize the timer with Timer Ticks */
+	(void)opb_timer_init() ;
+
+	/* Enable Interrupts in the System, if Profile Timer is the only Interrupt
+	 * in the System. */
+#ifdef ENABLE_SYS_INTR
+#ifdef TIMER_CONNECT_INTC
+	XIntc_MasterEnable((u32)INTC_BASEADDR );
+	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
+	XIntc_EnableIntr( (u32)INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,NULL);
+#endif
+
+#endif
+
+	Xil_ExceptionEnable();
+
+	return 0;
+
+}
+
+#endif	/* PROC_MICROBLAZE */
+
+
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Initialize the Profile Timer for Cortex A9 Target.
+ *	The scu private timer is connected to the Scu GIC controller.
+ *
+ *-------------------------------------------------------------------- */
+s32 scu_timer_init( void )
+{
+	/* set the number of cycles the timer counts before interrupting
+	 * scu timer runs at half the cpu clock */
+	XScuTimer_SetLoadReg(PROFILE_TIMER_BASEADDR, timer_clk_ticks/2U);
+
+	/* clear any pending interrupts */
+	XScuTimer_SetIntrReg(PROFILE_TIMER_BASEADDR, 1U);
+
+	/* enable interrupts, auto-reload mode and start the timer */
+	XScuTimer_SetControlReg(PROFILE_TIMER_BASEADDR, XSCUTIMER_CONTROL_IRQ_ENABLE_MASK |
+				XSCUTIMER_CONTROL_AUTO_RELOAD_MASK | XSCUTIMER_CONTROL_ENABLE_MASK);
+
+	return 0;
+}
+
+s32 cortexa9_init(void)
+{
+
+	Xil_ExceptionInit();
+
+	XScuGic_DeviceInitialize(0);
+
+	/*
+	 * Connect the interrupt controller interrupt handler to the hardware
+	 * interrupt handling logic in the processor.
+	 */
+	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
+				(Xil_ExceptionHandler)XScuGic_DeviceInterruptHandler,
+				NULL);
+
+	/*
+	 * Connect the device driver handler that will be called when an
+	 * interrupt for the device occurs, the handler defined above performs
+	 * the specific interrupt processing for the device.
+	 */
+	XScuGic_RegisterHandler(SCUGIC_CPU_BASEADDR,
+				PROFILE_TIMER_INTR_ID,
+				(Xil_ExceptionHandler)profile_intr_handler,
+				NULL);
+
+	/*
+	 * Enable the interrupt for scu timer.
+	 */
+	XScuGic_EnableIntr(SCUGIC_DIST_BASEADDR, PROFILE_TIMER_INTR_ID);
+
+	/*
+	 * Enable interrupts in the Processor.
+	 */
+	Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
+
+	/*
+	 * Initialize the timer with Timer Ticks
+	 */
+	(void)scu_timer_init() ;
+
+	Xil_ExceptionEnable();
+
+	return 0;
+}
+
+#endif	/* PROC_CORTEXA9 */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h
new file mode 100644
index 0000000..2cee66b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/_profile_timer_hw.h
@@ -0,0 +1,312 @@
+/******************************************************************************
+*
+* Copyright (C) 2004 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************
+*
+* _program_timer_hw.h:
+*	Timer related functions
+*
+******************************************************************************/
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+#  define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+#  define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ;	/* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ *	1. XTime_PITDisableInterrupt() ;
+ *	2. Store the remaining timer clk tick
+ *	3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() 		\
+	{				\
+		u32 val;	\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE));	\
+		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
+		mtspr(XREG_SPR_PIT, 0);	\
+	}
+#else
+#define disable_timer() 	\
+   { \
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+   }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ *	1. Load the remaining timer clk ticks
+ *	2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer()				\
+	{					\
+		u32 val;		\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
+		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+	}
+#else
+#define enable_timer()						\
+	{							\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 	1. Load the timer clk ticks
+ *	2. Enable AutoReload and Interrupt
+ *	3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack()							\
+	{								\
+		u32 val;					\
+		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
+		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
+		val=mfspr(XREG_SPR_TCR);				\
+		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+	}
+#else
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(Addr); \
+      tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+      u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+      OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+      OutAddr += (u32)XTC_TCSR_OFFSET; \
+      ProfIo_Out32(OutAddr, (u32)tmp_v); \
+    }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = (u32)ProfIo_In32(Addr); \
+      tmp_v = tmp_v |  (u32)XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+	}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0);	\
+		ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr);	\
+	}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()						\
+{							\
+	Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+		(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h
new file mode 100644
index 0000000..7096a92
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/mblaze_nt_types.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char            byte;
+typedef short           half;
+typedef int             word;
+typedef unsigned char   ubyte;
+typedef unsigned short  uhalf;
+typedef unsigned int    uword;
+typedef ubyte           boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h
new file mode 100644
index 0000000..4cb07a7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile.h
@@ -0,0 +1,131 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#ifndef	PROFILE_H
+#define	PROFILE_H	1
+
+#include 
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define	HISTCOUNTER	u16
+
+struct tostruct {
+	u32  selfpc;
+	s32	 count;
+	s16  link;
+	u16	 pad;
+};
+
+struct fromstruct {
+	u32 frompc ;
+	s16 link ;
+	u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
+#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+	s32		state;
+
+	/* Histogram Information */
+	u16		*kcount;	/* No. of bins in histogram */
+	u32		kcountsize;	/* Histogram samples */
+
+	/* Call-graph Information */
+	struct fromstruct	*froms;
+	u32		fromssize;
+	struct tostruct		*tos;
+	u32		tossize;
+
+	/* Initialization I/Ps */
+	u32    	lowpc;
+	u32		highpc;
+	u32		textsize;
+	/* u32 		cg_froms, */
+	/* u32 		cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define	GMON_PROF_ON	0
+#define	GMON_PROF_BUSY	1
+#define	GMON_PROF_ERROR	2
+#define	GMON_PROF_OFF	3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define	GPROF_STATE	0	/* int: profiling enabling variable */
+#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
+#define	GPROF_FROMS	2	/* struct: from location hash bucket */
+#define	GPROF_TOS	3	/* struct: destination/count structure */
+#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 		/* PROFILE_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c
new file mode 100644
index 0000000..2539ce6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_cg.c
@@ -0,0 +1,171 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+/*
+ * The mcount fucntion is excluded from the library, if the user defines
+ * PROFILE_NO_GRAPH.
+ */
+#ifndef PROFILE_NO_GRAPH
+
+#include 
+#include 
+#include 
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc );
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc );
+#endif
+
+/*extern struct gmonparam *_gmonparam, */
+
+#ifdef PROFILE_NO_FUNCPTR
+s32 searchpc(const struct fromto_struct *cgtable, s32 cgtable_size, u32 frompc )
+{
+	s32 index = 0 ;
+
+	while( (index < cgtable_size) && (cgtable[index].frompc != frompc) ){
+		index++ ;
+	}
+	if( index == cgtable_size ) {
+		return -1 ;
+	} else {
+		return index ;
+	}
+}
+#else
+s32 searchpc(const struct fromstruct *froms, s32 fromssize, u32 frompc )
+{
+	s32 index = 0 ;
+	s32 Status;
+
+	while( (index < fromssize) && (froms[index].frompc != frompc) ){
+		index++ ;
+	}
+	if( index == fromssize ) {
+		Status = -1 ;
+	} else {
+		Status = index ;
+	}
+	return Status;
+}
+#endif		/* PROFILE_NO_FUNCPTR */
+
+
+void mcount( u32 frompc, u32 selfpc )
+{
+	register struct gmonparam *p = NULL;
+	register s32 toindex, fromindex;
+	s32 j;
+
+	disable_timer();
+
+	/*print("CG: "), putnum(frompc), print("->"), putnum(selfpc), print("\r\n") ,
+	 * check that frompcindex is a reasonable pc value.
+	 * for example:	signal catchers get called from the stack,
+	 *		not from text space.  too bad.
+	*/
+	for(j = 0; j < n_gmon_sections; j++ ){
+		if((frompc >= _gmonparam[j].lowpc) && (frompc < _gmonparam[j].highpc)) {
+			p = &_gmonparam[j];
+			break;
+		}
+	}
+	if( j == n_gmon_sections ) {
+		goto done;
+	}
+
+#ifdef PROFILE_NO_FUNCPTR
+	fromindex = searchpc( p->cgtable, p->cgtable_size, frompc ) ;
+	if( fromindex == -1 ) {
+		fromindex = p->cgtable_size ;
+		p->cgtable_size++ ;
+		p->cgtable[fromindex].frompc = frompc ;
+		p->cgtable[fromindex].selfpc = selfpc ;
+		p->cgtable[fromindex].count = 1 ;
+		goto done ;
+	}
+	p->cgtable[fromindex].count++ ;
+#else
+	fromindex = (s32)searchpc( p->froms, ((s32)p->fromssize), frompc ) ;
+	if( fromindex == -1 ) {
+		fromindex = (s32)p->fromssize ;
+		p->fromssize++ ;
+		/*if( fromindex >= N_FROMS ) {
+		* print("Error : From PC table overflow\r\n")
+		* goto overflow
+		*}*/
+		p->froms[fromindex].frompc = frompc ;
+		p->froms[fromindex].link = -1 ;
+	}else {
+		toindex = ((s32)(p->froms[fromindex].link));
+		while(toindex != -1) {
+			toindex = (((s32)p->tossize) - toindex)-1 ;
+			if( p->tos[toindex].selfpc == selfpc ) {
+				p->tos[toindex].count++ ;
+				goto done ;
+			}
+			toindex = ((s32)(p->tos[toindex].link)) ;
+		}
+	}
+
+	/*if( toindex == -1 ) { */
+	p->tos-- ;
+	p->tossize++ ;
+	/* if( toindex >= N_TOS ) {
+	* print("Error : To PC table overflow\r\n")
+	* goto overflow
+	*} */
+	p->tos[0].selfpc = selfpc ;
+	p->tos[0].count = 1 ;
+	p->tos[0].link = p->froms[fromindex].link ;
+	p->froms[fromindex].link = ((s32)(p->tossize))-((s32)1);
+#endif
+
+ done:
+	p->state = GMON_PROF_ON;
+	goto enable_timer_label ;
+ /* overflow: */
+	/*p->state = GMON_PROF_ERROR */
+ enable_timer_label:
+	enable_timer();
+	return ;
+}
+
+
+#endif		/* PROFILE_NO_GRAPH */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h
new file mode 100644
index 0000000..550c60b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_config.h
@@ -0,0 +1,48 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+
+#ifndef _PROFILE_CONFIG_H
+#define _PROFILE_CONFIG_H
+
+#define BINSIZE 4U
+#define SAMPLE_FREQ_HZ 100000U
+#define TIMER_CLK_TICKS 1000U
+
+#define PROFILE_NO_FUNCPTR_FLAG 0
+
+#define PROFILE_TIMER_BASEADDR 0x00608000U
+#define PROFILE_TIMER_INTR_ID 0U
+
+#define TIMER_CONNECT_INTC
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c
new file mode 100644
index 0000000..c8ee9ce
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/profile/profile_hist.c
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2014 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "profile.h"
+#include "_profile_timer_hw.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef PROC_PPC
+#include "xpseudo_asm.h"
+#define SPR_SRR0 0x01A
+#endif
+
+#include "xil_types.h"
+
+extern u32 binsize ;
+u32 prof_pc ;
+
+void profile_intr_handler( void )
+{
+
+	s32 j;
+
+#ifdef PROC_MICROBLAZE
+	asm( "swi r14, r0, prof_pc" ) ;
+#elif defined PROC_PPC
+	prof_pc = mfspr(SPR_SRR0);
+#else
+	/* for cortexa9, lr is saved in asm interrupt handler */
+#endif
+	/* print("PC: "), putnum(prof_pc), print("\r\n"), */
+	for(j = 0; j < n_gmon_sections; j++ ){
+		if((prof_pc >= ((u32)_gmonparam[j].lowpc)) && (prof_pc < ((u32)_gmonparam[j].highpc))) {
+			_gmonparam[j].kcount[(prof_pc-_gmonparam[j].lowpc)/((u32)4 * binsize)]++;
+			break;
+		}
+	}
+	/* Ack the Timer Interrupt */
+	timer_ack();
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c
new file mode 100644
index 0000000..aaf9ede
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+  char8  buf[9];
+  s32  cnt;
+  s32 i;
+  char8  *ptr;
+  u32  digit;
+  for(i = 0; i<9; i++) {
+	buf[i] = '0';
+  }
+
+  ptr = buf;
+  for (cnt = 7 ; cnt >= 0 ; cnt--) {
+    digit = (num >> (cnt * 4U)) & 0x0000000fU;
+
+    if ((digit <= 9U) && (ptr != NULL)) {
+		digit += (u32)'0';
+		*ptr = ((char8) digit);
+		ptr += 1;
+	} else if (ptr != NULL) {
+		digit += ((u32)'a' - (u32)10);
+		*ptr = ((char8)digit);
+		ptr += 1;
+	} else {
+		/*Made for MisraC Compliance*/;
+	}
+  }
+
+  if(ptr != NULL) {
+	  *ptr = (char8) 0;
+  }
+  print (buf);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c
new file mode 100644
index 0000000..7f7b7d2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/read.c
@@ -0,0 +1,104 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* read.c -- read bytes from a input device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read  -- read bytes from the serial port. Ignore fd, since
+ *          we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  s32 numbytes = 0;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
+		}
+	}
+  }
+
+  return numbytes;
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  s32 numbytes = 0;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  if(LocalBuf != NULL) {
+	for (i = 0; i < nbytes; i++) {
+		numbytes++;
+		*(LocalBuf + i) = inbyte();
+		if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) {
+			break;
+		}
+	}
+  }
+
+  return numbytes;
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
new file mode 100644
index 0000000..87a753d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sbrk.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+  char8 *base;
+  static char8 *heap_ptr = HeapBase;
+
+  base = heap_ptr;
+	if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
+	heap_ptr += nbytes;
+    return base;
+  }	else {
+    errno = ENOMEM;
+    return ((char8 *)-1);
+  }
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
new file mode 100644
index 0000000..f85743b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.c
@@ -0,0 +1,92 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Updated sleep function to make use Global
+* 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 6.6	srm      10/18/17 Updated sleep routines to support user configurable
+*			  implementation. Now sleep routines will use Timer
+*                         specified by the user (i.e. Global timer/TTC timer)
+*
+* 
    
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds
+*
+* @param	seconds requested
+*
+* @return	0 always
+*
+* @note		None.
+*
+****************************************************************************/
+unsigned sleep_A9(unsigned int seconds)
+{
+#if defined (SLEEP_TIMER_BASEADDR)
+	Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND);
+#else
+	XTime tEnd, tCur;
+
+	XTime_GetTime(&tCur);
+	tEnd  = tCur + (((XTime) seconds) * COUNTS_PER_SECOND);
+	do
+    {
+		XTime_GetTime(&tCur);
+    } while (tCur < tEnd);
+#endif
+
+  return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
new file mode 100644
index 0000000..f53b2d8
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/sleep.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+*  This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+*  related APIs.
+*
+* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6   srm  11/02/17 Added processor specific sleep rountines
+*								 function prototypes.
+*
+* 
    
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param            IO_func - accessor function to read the register contents.
+*                   Depends on the register width.
+* @param            ADDR - Address to be polled
+* @param            VALUE - variable to read the value
+* @param            COND - Condition to checked (usually involves VALUE)
+* @param            TIMEOUT_US - timeout in micro seconds
+*
+* @return           0 - when the condition is met
+*                   -1 - when the condition is not met till the timeout period
+*
+* @note             none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( {	  \
+	u64 timeout = TIMEOUT_US/100;    \
+	if(TIMEOUT_US%100!=0)	\
+		timeout++;   \
+	for(;;) { \
+		VALUE = IO_func(ADDR); \
+		if(COND) \
+			break; \
+		else {    \
+			usleep(100);  \
+			timeout--; \
+			if(timeout==0) \
+			break;  \
+		}  \
+	}    \
+	(timeout>0) ? 0 : -1;  \
+ }  )
+
+void usleep(unsigned long useconds);
+void sleep(unsigned int seconds);
+int usleep_R5(unsigned long useconds);
+unsigned sleep_R5(unsigned int seconds);
+int usleep_MB(unsigned long useconds);
+unsigned sleep_MB(unsigned int seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h
new file mode 100644
index 0000000..5a4d336
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/smc.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file smc.h
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  11/03/09 Initial release.
+* 4.2	pkp	 08/04/14 Removed function definition of XSmc_NorInit and XSmc_NorInit
+*					  as smc.c is removed
+* 
    
+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef SMC_H /* prevent circular inclusions */
+#define SMC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xparameters.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory controller configuration register offset */
+#define XSMCPSS_MC_STATUS		0x000U	/* Controller status reg, RO */
+#define XSMCPSS_MC_INTERFACE_CONFIG	0x004U	/* Interface config reg, RO */
+#define XSMCPSS_MC_SET_CONFIG		0x008U	/* Set configuration reg, WO */
+#define XSMCPSS_MC_CLR_CONFIG		0x00CU	/* Clear config reg, WO */
+#define XSMCPSS_MC_DIRECT_CMD		0x010U	/* Direct command reg, WO */
+#define XSMCPSS_MC_SET_CYCLES		0x014U	/* Set cycles register, WO */
+#define XSMCPSS_MC_SET_OPMODE		0x018U	/* Set opmode register, WO */
+#define XSMCPSS_MC_REFRESH_PERIOD_0	0x020U	/* Refresh period_0 reg, RW */
+#define XSMCPSS_MC_REFRESH_PERIOD_1	0x024U	/* Refresh period_1 reg, RW */
+
+/* Chip select configuration register offset */
+#define XSMCPSS_CS_IF0_CHIP_0_OFFSET	0x100U	/* Interface 0 chip 0 config */
+#define XSMCPSS_CS_IF0_CHIP_1_OFFSET	0x120U	/* Interface 0 chip 1 config */
+#define XSMCPSS_CS_IF0_CHIP_2_OFFSET	0x140U	/* Interface 0 chip 2 config */
+#define XSMCPSS_CS_IF0_CHIP_3_OFFSET	0x160U	/* Interface 0 chip 3 config */
+#define XSMCPSS_CS_IF1_CHIP_0_OFFSET	0x180U	/* Interface 1 chip 0 config */
+#define XSMCPSS_CS_IF1_CHIP_1_OFFSET	0x1A0U	/* Interface 1 chip 1 config */
+#define XSMCPSS_CS_IF1_CHIP_2_OFFSET	0x1C0U	/* Interface 1 chip 2 config */
+#define XSMCPSS_CS_IF1_CHIP_3_OFFSET	0x1E0U	/* Interface 1 chip 3 config */
+
+/* User configuration register offset */
+#define XSMCPSS_UC_STATUS_OFFSET	0x200U	/* User status reg, RO */
+#define XSMCPSS_UC_CONFIG_OFFSET	0x204U	/* User config reg, WO */
+
+/* Integration test register offset */
+#define XSMCPSS_IT_OFFSET		0xE00U
+
+/* ID configuration register offset */
+#define XSMCPSS_ID_PERIP_0_OFFSET	0xFE0U
+#define XSMCPSS_ID_PERIP_1_OFFSET	0xFE4U
+#define XSMCPSS_ID_PERIP_2_OFFSET	0xFE8U
+#define XSMCPSS_ID_PERIP_3_OFFSET	0xFECU
+#define XSMCPSS_ID_PCELL_0_OFFSET	0xFF0U
+#define XSMCPSS_ID_PCELL_1_OFFSET	0xFF4U
+#define XSMCPSS_ID_PCELL_2_OFFSET	0xFF8U
+#define XSMCPSS_ID_PCELL_3_OFFSET	0xFFCU
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* SMC_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c
new file mode 100644
index 0000000..d0cc680
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/unlink.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+__attribute__((weak)) sint32 unlink(char8 *path)
+{
+  (void) path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
new file mode 100644
index 0000000..65eea28
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/usleep.c
@@ -0,0 +1,107 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex A9 MP core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  11/11/09 First release
+* 3.07a sgd      07/05/12 Upadted micro sleep function to make use Global Timer
+* 4.2	pkp		 08/04/14 Removed unimplemented nanosleep routine as it is not
+*						  possible to generate timer in nanosecond due to
+*						  limited cpu frequency
+* 6.0   asa      08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 6.6	srm	 10/18/17 Updated sleep routines to support user configurable
+*			  implementation. Now sleep routines will use Timer
+*                         specified by the user (i.e. Global timer/TTC timer)
+* 
    
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexa9.h"
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#include "xil_sleeptimer.h"
+#endif
+
+/****************************  Constant Definitions  ************************/
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_USECOND  (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U))
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param	useconds requested
+*
+* @return	0 if the delay can be achieved, -1 if the requested delay
+*		is out of range
+*
+* @note		None.
+*
+****************************************************************************/
+int usleep_A9(unsigned long useconds)
+{
+#if defined (SLEEP_TIMER_BASEADDR)
+	Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND);
+#else
+	XTime tEnd, tCur;
+
+	XTime_GetTime(&tCur);
+	tEnd = tCur + (((XTime) useconds) * COUNTS_PER_USECOND);
+	do
+	{
+		XTime_GetTime(&tCur);
+	} while (tCur < tEnd);
+#endif
+
+	return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c
new file mode 100644
index 0000000..0a36163
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.c
@@ -0,0 +1,231 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex A9 core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/09 Initial version, moved over from bsp area
+* 6.0   mus  27/07/16 Consolidated vectors for a53,a9 and r5 processor
+*                     and added UndefinedException for a53 32 bit and r5
+*                     processor
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+#if !defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Undefined exception called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void UndefinedException(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_UNDEFINED_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
+#else
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SynchronousInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SYNC_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SError Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SErrorInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data);
+}
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h
new file mode 100644
index 0000000..bb599b5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/vectors.h
@@ -0,0 +1,88 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex A9 core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a ecm  10/20/10 Initial version, moved over from bsp area
+* 6.0   mus  07/27/16 Consolidated vectors for a9,a53 and r5 processors
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _VECTORS_H_
+#define _VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+#if !defined (__aarch64__)
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+void UndefinedException(void);
+#else
+void SynchronousInterrupt(void);
+void SErrorInterrupt(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
new file mode 100644
index 0000000..9389f61
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/write.c
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* write.c -- write bytes to an output device.
+ */
+#ifndef UNDEFINE_FILE_OPS
+#include "xil_printf.h"
+#include "xparameters.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+__attribute__((weak)) sint32
+write (sint32 fd, char8* buf, sint32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) sint32
+_write (sint32 fd, char8* buf, sint32 nbytes)
+{
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+	sint32 length;
+
+	(void)fd;
+	(void)nbytes;
+	length = XPVXenConsole_Write(buf);
+	return length;
+#else
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+#endif
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h
new file mode 100644
index 0000000..787212c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xbasic_types.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* 
    
+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include 
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+
+#endif	/* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h
new file mode 100644
index 0000000..650946b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG  /* prevent circular inclusions */
+#define XDEBUG  /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x)  x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h
new file mode 100644
index 0000000..3d97beb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h
new file mode 100644
index 0000000..f186018
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* 
    
+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include 
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * 

    
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c
new file mode 100644
index 0000000..59b3c1c
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.c
@@ -0,0 +1,147 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 Initial release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+s32 Xil_AssertWait = 1;
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief    Implement assert. Currently, it calls a user-defined callback
+*           function if one has been set.  Then, it potentially enters an
+*           infinite loop depending on the value of the Xil_AssertWait
+*           variable.
+*
+* @param    file: filename of the source
+* @param    line: linenumber within File
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+	/* if the callback has been set then invoke it */
+	if (Xil_AssertCallbackRoutine != 0) {
+		(*Xil_AssertCallbackRoutine)(File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (Xil_AssertWait != 0) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Set up a callback function to be invoked when an assert occurs.
+*           If a callback is already installed, then it will be replaced.
+*
+* @param    routine: callback to be invoked when an assert is taken
+*
+* @return   None.
+*
+* @note     This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+	Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Null handler function. This follows the XInterruptHandler
+*           signature for interrupt handlers. It can be used to assign a null
+*           handler (a stub) to an interrupt controller vector table.
+*
+* @param    NullParameter: arbitrary void pointer and not used.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+	(void) NullParameter;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h
new file mode 100644
index 0000000..add4124
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_assert.h
@@ -0,0 +1,195 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for void functions. This in
+*           conjunction with the Xil_AssertWait boolean can be used to
+*           accomodate tests so that asserts which fail allow execution to
+*           continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for functions that do return a
+*           value. This in conjunction with the Xil_AssertWait boolean can be
+*           used to accomodate tests so that asserts which fail allow execution
+*           to continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	        case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief     Always assert. This assert macro is to be used for void functions.
+*            Use for instances where an assert should always occur.
+*
+* @return    Returns void unless the Xil_AssertWait variable is true, in which
+*	         case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* @brief   Always assert. This assert macro is to be used for functions that
+*          do return a value. Use for instances where an assert should always
+*          occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	      case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
new file mode 100644
index 0000000..259c3b1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.c
@@ -0,0 +1,1641 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a  ecm 01/29/10 First release
+* 1.00a  ecm 06/24/10 Moved the L1 and L2 specific function prototypes
+*		      		  to xil_cache_mach.h to give access to sophisticated users
+* 3.02a  sdm 04/07/11 Updated Flush/InvalidateRange APIs to flush/invalidate
+*		      		  L1 and L2 caches in a single loop and used dsb, L2 sync
+*		      		  at the end of the loop.
+* 3.04a  sdm 01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      		  APIs.
+* 3.07a  asa 07/16/12 Corrected the L1 and L2 cache invalidation order.
+* 3.07a  sgd 09/18/12 Corrected the L2 cache enable and disable sequence.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      		  'xil_errata.h' for errata description
+* 3.10a  asa 05/13/13 Modified cache disable APIs. The L2 cache disable
+*			  		  operation was being done with L1 Data cache disabled. This is
+*			  		  fixed so that L2 cache disable operation happens independent of
+*			  		  L1 cache disable operation. This fixes CR #706464.
+*			  		  Changes are done to do a L2 cache sync (poll reg7_?cache_?sync).
+*			  		  This is done to fix the CR #700542.
+* 3.11a  asa 09/23/13 Modified the Xil_DCacheFlushRange and
+*			 		  Xil_DCacheInvalidateRange to fix potential issues. Fixed other
+*			 		  relevant cache APIs to disable and enable back the interrupts.
+*			 		  This fixes CR #663885.
+* 3.11a  asa 09/28/13 Made changes for L2 cache sync operation. It is found
+*			 		  out that for L2 cache flush/clean/invalidation by cache lines
+*			 		  does not need a cache sync as these are atomic nature. Similarly
+*			 		  figured out that for complete L2 cache flush/invalidation by way
+*			 		  we need to wait for some more time in a loop till the status
+*			 		  shows that the cache operation is completed.
+* 4.00	 pkp 24/01/14 Modified Xil_DCacheInvalidateRange to fix the bug. Few
+*			 		  cache lines were missed to invalidate when unaligned address
+*			 		  invalidation was accommodated. That fixes CR #766768.
+*			 		  Also in Xil_L1DCacheInvalidate, while invalidating all L1D cache
+*			 		  stack memory which contains return address was invalidated. So
+*			 		  stack memory was flushed first and then L1D cache is invalidated.
+*			 		  This is done to fix CR #763829
+* 4.01   asa 05/09/14 Made changes in cortexa9/xil_cache.c to fix CR# 798230.
+* 4.02	 pkp 06/27/14 Added notes to Xil_L1DCacheInvalidateRange function for
+*					  explanation of CR#785243
+* 5.00   kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
+*					  has stack memory which has return address. Before invalidating
+*					  cache, stack memory was flushed first and L2 Cache is invalidated.
+* 5.01	 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
+*					  to remove unnecessary dsb in the APIs. Instead of using dsb
+*					  for L2 Cache, L2CacheSync has been used for each L2 cache line
+*					  and single dsb has been used for L1 cache. Also L2CacheSync is
+*					  added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
+*					  and Xil_L2CacheInvalidate APIs are modified to flush the complete
+*					  stack instead of just System Stack
+* 5.03	 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
+*					  application(when USE_AMP flag is defined for BSP) as master CPU
+*					  would be utilizing L2 cache for its operation
+* 6.6    mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+*                     version r0p2, which is present in zynq. So,removed the handling
+*                     related to same.It fixes CR#989132.
+* 6.6    asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+*					  routines to ensure the stack data flushed only when the respective
+*					  caches are enabled. This fixes CR-992023.
+*
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_cache_l.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexa9.h"
+#include "xl2cc.h"
+#include "xil_errata.h"
+#include "xil_exception.h"
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0U	/* Mask IRQ and FIQ interrupts in cpsr */
+
+#ifdef __GNUC__
+	extern s32  _stack_end;
+	extern s32  __undef_stack;
+#endif
+
+#ifndef USE_AMP
+/****************************************************************************
+*
+* Access L2 Debug Control Register.
+*
+* @param	Value, value to be written to Debug Control Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2WriteDebugCtrl(u32 Value)
+#else
+static void Xil_L2WriteDebugCtrl(u32 Value)
+#endif
+{
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DEBUG_CTRL_OFFSET, Value);
+#else
+	(void)(Value);
+#endif
+}
+
+/****************************************************************************
+*
+* Perform L2 Cache Sync Operation.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+#ifdef __GNUC__
+static inline void Xil_L2CacheSync(void)
+#else
+static void Xil_L2CacheSync(void)
+#endif
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U);
+}
+#endif
+/****************************************************************************/
+/**
+* @brief	Enable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+	Xil_L1DCacheEnable();
+#ifndef USE_AMP
+	Xil_L2CacheEnable();
+#endif
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+#ifndef USE_AMP
+	Xil_L2CacheDisable();
+#endif
+	Xil_L1DCacheDisable();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidate();
+#endif
+	Xil_L1DCacheInvalidate();
+
+	mtcpsr(currmask);
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate a Data cache line. If the byte specified by the address
+* 			(adr) is cached by the Data cache, the cacheline containing that
+* 			byte is invalidated. If the cacheline is modified (dirty), the
+* 			modified contents are lost and are NOT written to the system memory
+* 			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidateLine(adr);
+#endif
+	Xil_L1DCacheInvalidateLine(adr);
+
+	mtcpsr(currmask);
+}
+
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate the Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+*			cache, the cachelines containing those bytes are invalidated. If
+*			the cachelines are modified (dirty), the modified contents are lost
+*			and NOT written to the system memory before the lines are
+*			invalidated.
+*
+* 			In this function, if start address or end address is not aligned to
+* 			cache-line, particular cache-line containing unaligned start or end
+* 			address is flush first and then invalidated the others as
+* 			invalidating the same unaligned cache line may result into loss of
+*			data. This issue raises few possibilities.
+*
+* 			If the address to be invalidated is not cache-line aligned, the
+* 			following choices are available:
+* 			1. Invalidate the cache line when required and do not bother much
+* 			for the side effects. Though it sounds good, it can result in
+* 			hard-to-debug issues. The problem is, if some other variable are
+* 			allocated in the same cache line and had been recently updated
+* 			(in cache), the invalidation would result in loss of data.
+* 			2. Flush the cache line first. This will ensure that if any other
+* 			variable present in the same cache line and updated recently are
+* 			flushed out to memory. Then it can safely be invalidated. Again it
+* 			sounds good, but this can result in issues. For example, when the
+* 			invalidation happens in a typical ISR (after a DMA transfer has
+* 			updated the memory), then flushing the cache line means, loosing
+* 			data that were updated recently before the ISR got invoked.
+*
+* 			Linux prefers the second one. To have uniform implementation
+* 			(across standalone and Linux), the second option is implemented.
+* 			This being the case, follwoing needs to be taken care of:
+* 			1. Whenever possible, the addresses must be cache line aligned.
+* 			Please nore that, not just start address, even the end address must
+* 			be cache line aligned. If that is taken care of, this will always
+*			work.
+* 			2. Avoid situations where invalidation has to be done after the
+* 			data is updated by peripheral/DMA directly into the memory. It is
+* 			not tough to achieve (may be a bit risky). The common use case to
+* 			do invalidation is when a DMA happens. Generally for such use
+*			cases, buffers can be allocated first and then start the DMA. The
+* 			practice that needs to be followed here is, immediately after
+* 			buffer allocation and before starting the DMA, do the invalidation.
+* 			With this approach, invalidation need not to be done after the DMA
+*			transfer is over.
+*
+* 			This is going to always work if done carefully.
+* 			However, the concern is, there is no guarantee that invalidate has
+* 			not needed to be done after DMA is complete. For example, because
+* 			of some reasons if the first cache line or last cache line
+* 			(assuming the buffer in question comprises of multiple cache lines)
+*			are brought into cache (between the time it is invalidated and DMA
+* 			completes) because of some speculative prefetching or reading data
+* 			for a variable present in the same cache line, then we will have to
+*			invalidate the cache after DMA is complete.
+*
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 tempadr = adr;
+	u32 tempend;
+	u32 currmask;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		end = tempadr + len;
+		tempend = end;
+		/* Select L1 Data cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		if ((tempadr & (cacheline-1U)) != 0U) {
+			tempadr &= (~(cacheline - 1U));
+
+			Xil_L1DCacheFlushLine(tempadr);
+#ifndef USE_AMP
+			/* Disable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x3U);
+			Xil_L2CacheFlushLine(tempadr);
+			/* Enable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x0U);
+			Xil_L2CacheSync();
+#endif
+			tempadr += cacheline;
+		}
+		if ((tempend & (cacheline-1U)) != 0U) {
+			tempend &= (~(cacheline - 1U));
+
+			Xil_L1DCacheFlushLine(tempend);
+#ifndef USE_AMP
+			/* Disable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x3U);
+			Xil_L2CacheFlushLine(tempend);
+			/* Enable Write-back and line fills */
+			Xil_L2WriteDebugCtrl(0x0U);
+			Xil_L2CacheSync();
+#endif
+		}
+
+		while (tempadr < tempend) {
+#ifndef USE_AMP
+			/* Invalidate L2 cache line */
+			*L2CCOffset = tempadr;
+			Xil_L2CacheSync();
+#endif
+
+	/* Invalidate L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_mva_poc(tempadr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+			  Reg = tempadr; }
+#endif
+			tempadr += cacheline;
+		}
+	}
+
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L1DCacheFlush();
+#ifndef USE_AMP
+	Xil_L2CacheFlush();
+#endif
+	mtcpsr(currmask);
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Flush a Data cache line. If the byte specified by the address (adr)
+* 			is cached by the Data cache, the cacheline containing that byte is
+* 			invalidated. If the cacheline is modified (dirty), the entire
+* 			contents of the cacheline are written to system memory before the
+* 			line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	Xil_L1DCacheFlushLine(adr);
+#ifndef USE_AMP
+	/* Disable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x3U);
+
+	Xil_L2CacheFlushLine(adr);
+
+	/* Enable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x0U);
+	Xil_L2CacheSync();
+#endif
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the
+* 			data cache, the cachelines containing those bytes are invalidated.
+* 			If the cachelines are modified (dirty), they are written to the
+* 			system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr &= ~(cacheline - 1U);
+
+		while (LocalAddr < end) {
+
+	/* Flush L1 Data cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+#ifndef USE_AMP
+			/* Flush L2 cache line */
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+	dsb();
+	mtcpsr(currmask);
+}
+/****************************************************************************/
+/**
+* @brief	Store a Data cache line. If the byte specified by the address (adr)
+* 			is cached by the Data cache and the cacheline is modified (dirty),
+* 			the entire contents of the cacheline are written to system memory.
+* 			After the store completes, the cacheline is marked as unmodified
+* 			(not dirty).
+*
+* @param	adr: 32bit address of the data to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	Xil_L1DCacheStoreLine(adr);
+#ifndef USE_AMP
+	Xil_L2CacheStoreLine(adr);
+#endif
+	mtcpsr(currmask);
+}
+
+/***************************************************************************/
+/**
+* @brief	Enable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+	Xil_L1ICacheEnable();
+#ifndef USE_AMP
+	Xil_L2CacheEnable();
+#endif
+}
+
+/***************************************************************************/
+/**
+* @brief	Disable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+#ifndef USE_AMP
+	Xil_L2CacheDisable();
+#endif
+	Xil_L1ICacheDisable();
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidate();
+#endif
+	Xil_L1ICacheInvalidate();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate an instruction cache line. If the instruction specified
+*			by the address is cached by the instruction cache, the cacheline
+*			containing that instruction is invalidated.
+*
+* @param	adr: 32bit address of the instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(u32 adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+#ifndef USE_AMP
+	Xil_L2CacheInvalidateLine(adr);
+#endif
+	Xil_L1ICacheInvalidateLine(adr);
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the instruction cache for the given address range.
+* 			If the instructions specified by the address range are cached by
+* 			the instrunction cache, the cachelines containing those
+*			instructions are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+#ifndef USE_AMP
+		/* Invalidate L2 cache line */
+		*L2CCOffset = LocalAddr;
+		dsb();
+#endif
+
+		/* Invalidate L1 I-cache line */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+			  Reg = LocalAddr; }
+#endif
+
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 and L2 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Enable the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+		return;
+	}
+
+	/* clean and invalidate the Data cache */
+	Xil_L1DCacheInvalidate();
+
+	/* enable the Data cache */
+	CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/***************************************************************************/
+/**
+* @brief	Disable the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	/* clean and invalidate the Data cache */
+	Xil_L1DCacheFlush();
+
+#ifdef __GNUC__
+	/* disable the Data cache */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+
+	CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In Cortex A9, there is no cp instruction for invalidating
+*			the whole D-cache. This function invalidates each line by
+*			set/way.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidate(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 CacheSize, LineSize, NumWays;
+	u32 Way, WayIndex, Set, SetIndex, NumSet;
+	u32 currmask;
+
+#ifdef __GNUC__
+	u32 stack_start,stack_end,stack_size;
+	register u32 CtrlReg;
+#endif
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+#ifdef __GNUC__
+	stack_end = (u32)&_stack_end;
+	stack_start = (u32)&__undef_stack;
+	stack_size=stack_start-stack_end;
+
+	/* Check for the cache status. If cache is enabled, then only
+	 * flush stack memory to save return address. If cache is disabled,
+	 * dont flush anything as it might result in flushing stale date into
+	 * memory which is undesirable.
+	 * */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+	if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) {
+		Xil_DCacheFlushRange(stack_end, stack_size);
+	}
+#endif
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+#ifdef __GNUC__
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+	  CsidReg = Reg; }
+#endif
+	/* Determine Cache Size */
+	CacheSize = (CsidReg >> 13U) & 0x1FFU;
+	CacheSize +=1U;
+	CacheSize *=128U;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x3ffU) >> 3U;
+	NumWays += 1U;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x07U) + 4U;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (0x00000001U << LineSize);
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+
+		/* Invalidate by Set/Way */
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_sw(C7Reg);
+#else
+			/*mtcp(XREG_CP15_INVAL_DC_LINE_SW, C7Reg), */
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_SW);
+			  Reg = C7Reg; }
+#endif
+			Set += (0x00000001U << LineSize);
+		}
+		Set=0U;
+		Way += 0x40000000U;
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate a level 1 Data cache line. If the byte specified by the
+* 			address (Addr) is cached by the Data cache, the cacheline
+* 			containing that byte is invalidated. If the cacheline is modified
+* 			(dirty), the modified contents are lost and are NOT written to
+*			system memory before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+* 			cache, the cachelines containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), the modified contents are lost and
+* 			NOT written to the system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 D-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 1 Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In Cortex A9, there is no cp instruction for flushing
+*			the whole D-cache. Need to flush each line.
+*
+****************************************************************************/
+void Xil_L1DCacheFlush(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 CacheSize, LineSize, NumWays;
+	u32 Way;
+	u32 WayIndex, Set, SetIndex, NumSet;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+#ifdef __GNUC__
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_CACHE_SIZE_ID, CsidReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_CACHE_SIZE_ID);
+	  CsidReg = Reg; }
+#endif
+
+	/* Determine Cache Size */
+
+	CacheSize = (CsidReg >> 13U) & 0x1FFU;
+	CacheSize +=1U;
+	CacheSize *=128U;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x3ffU) >> 3U;
+	NumWays += 1U;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x07U) + 4U;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (0x00000001U << LineSize);
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+			/* Flush by Set/Way */
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_sw(C7Reg);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_SW);
+			  Reg = C7Reg; }
+#endif
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += 0x40000000U;
+	}
+
+	/* Wait for L1 flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush a level 1 Data cache line. If the byte specified by the
+*			address (adr) is cached by the Data cache, the cacheline containing
+*			that byte is invalidated. If the cacheline is modified (dirty), the
+* 			entire contents of the cacheline are written to system memory
+*			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 flush to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 1  Data cache for the given address range.
+* 			If the bytes specified by the address range are cached by the Data
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), they are written to system memory
+* 			before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1DCacheFlushRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 D-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_clean_inval_dc_line_mva_poc(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Store a level 1  Data cache line. If the byte specified by the
+* 			address (adr) is cached by the Data cache and the cacheline is
+* 			modified (dirty), the entire contents of the cacheline are written
+* 			to system memory. After the store completes, the cacheline is
+*			marked as unmodified (not dirty).
+*
+* @param	Address to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1DCacheStoreLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+	mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1FU)));
+
+	/* Wait for L1 store to complete */
+	dsb();
+}
+
+
+/****************************************************************************/
+/**
+* @brief	Enable the level 1 instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	if ((CtrlReg & (XREG_CP15_CONTROL_I_BIT)) != 0U) {
+		return;
+	}
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* enable the instruction cache */
+	CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable level 1 the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	dsb();
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* disable the instruction cache */
+#ifdef __GNUC__
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+#else
+	{ volatile register u32 Reg __asm(XREG_CP15_SYS_CONTROL);
+	  CtrlReg = Reg; }
+#endif
+	CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the entire level 1 instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidate(void)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0U);
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate a level 1  instruction cache line. If the instruction
+*			specified by the address is cached by the instruction cache, the
+*			cacheline containing that instruction is invalidated.
+*
+* @param	adr: 32bit address of the instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 5 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateLine(u32 adr)
+{
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1FU)));
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 1 instruction cache for the given address
+* 			range. If the instrucions specified by the address range are cached
+*			by the instruction cache, the cacheline containing those bytes are
+*			invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+			asm_cp15_inval_ic_line_mva_pou(LocalAddr);
+#else
+			{ volatile register u32 Reg
+				__asm(XREG_CP15_INVAL_IC_LINE_MVA_POU);
+			  Reg = LocalAddr; }
+#endif
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for L1 invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+#ifndef USE_AMP
+/****************************************************************************/
+/**
+* @brief	Enable the L2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheEnable(void)
+{
+	register u32 L2CCReg;
+
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+	/* only enable if L2CC is currently disabled */
+	if ((L2CCReg & 0x01U) == 0U) {
+		/* set up the way size and latencies */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_AUX_CNTRL_OFFSET);
+		L2CCReg &= XPS_L2CC_AUX_REG_ZERO_MASK;
+		L2CCReg |= XPS_L2CC_AUX_REG_DEFAULT_MASK;
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_AUX_CNTRL_OFFSET,
+			  L2CCReg);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_TAG_RAM_CNTRL_OFFSET,
+			  XPS_L2CC_TAG_RAM_DEFAULT_MASK);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DATA_RAM_CNTRL_OFFSET,
+			  XPS_L2CC_DATA_RAM_DEFAULT_MASK);
+
+		/* Clear the pending interrupts */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_ISR_OFFSET);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_IAR_OFFSET, L2CCReg);
+
+		Xil_L2CacheInvalidate();
+		/* Enable the L2CC */
+		L2CCReg = Xil_In32(XPS_L2CC_BASEADDR +
+				   XPS_L2CC_CNTRL_OFFSET);
+		Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+			  (L2CCReg | (0x01U)));
+
+        Xil_L2CacheSync();
+        /* synchronize the processor */
+	    dsb();
+
+    }
+}
+
+/****************************************************************************/
+/**
+* @brief	Disable the L2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheDisable(void)
+{
+    register u32 L2CCReg;
+
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+
+    if((L2CCReg & 0x1U) != 0U) {
+
+        /* Clean and Invalidate L2 Cache */
+        Xil_L2CacheFlush();
+
+	    /* Disable the L2CC */
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+	    Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET,
+		      (L2CCReg & (~0x01U)));
+		/* Wait for the cache operations to complete */
+
+		dsb();
+    }
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate the entire level 2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidate(void)
+{
+	#ifdef __GNUC__
+	u32 stack_start,stack_end,stack_size;
+	register u32 L2CCReg;
+	stack_end = (u32)&_stack_end;
+	stack_start = (u32)&__undef_stack;
+	stack_size=stack_start-stack_end;
+
+	/* Check for the cache status. If cache is enabled, then only
+	 * flush stack memory to save return address. If cache is disabled,
+     * dont flush anything as it might result in flushing stale date into
+	 * memory which is undesirable.
+	 */
+	L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET);
+	if ((L2CCReg & 0x01U) != 0U) {
+	/*Flush stack memory to save return address*/
+		Xil_DCacheFlushRange(stack_end, stack_size);
+	}
+
+	#endif
+	u32 ResultDCache;
+	/* Invalidate the caches */
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET,
+		  0x0000FFFFU);
+	ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+							& 0x0000FFFFU;
+	while(ResultDCache != (u32)0U) {
+		ResultDCache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_WAY_OFFSET)
+							& 0x0000FFFFU;
+	}
+
+	/* Wait for the invalidate to complete */
+	Xil_L2CacheSync();
+
+	/* synchronize the processor */
+	dsb();
+}
+
+/*****************************************************************************/
+/**
+* @brief	Invalidate a level 2 cache line. If the byte specified by the
+*			address (adr) is cached by the Data cache, the cacheline containing
+*			that byte is invalidated. If the cacheline is modified (dirty),
+*			the modified contents are lost and are NOT written to system memory
+*			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data/instruction to be invalidated.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateLine(u32 adr)
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, (u32)adr);
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Invalidate the level 2 cache for the given address range.
+* 			If the bytes specified by the address range are cached by the L2
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), the modified contents are lost and
+* 			are NOT written to system memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be invalidated.
+* @param	len: Length of the range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INVLD_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Disable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x3U);
+
+		while (LocalAddr < end) {
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+			LocalAddr += cacheline;
+		}
+
+		/* Enable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x0U);
+	}
+
+	/* synchronize the processor */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the entire level 2 cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheFlush(void)
+{
+	u32 ResultL2Cache;
+
+	/* Flush the caches */
+
+	/* Disable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x3U);
+
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET,
+		  0x0000FFFFU);
+	ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+							& 0x0000FFFFU;
+
+	while(ResultL2Cache != (u32)0U) {
+		ResultL2Cache = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET)
+									& 0x0000FFFFU;
+	}
+
+	Xil_L2CacheSync();
+	/* Enable Write-back and line fills */
+	Xil_L2WriteDebugCtrl(0x0U);
+
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush a level 2 cache line. If the byte specified by the address
+* 			(adr) is cached by the L2 cache, the cacheline containing that
+* 			byte is invalidated. If the cacheline is modified (dirty), the
+* 			entire contents of the cacheline are written to system memory
+* 			before the line is invalidated.
+*
+* @param	adr: 32bit address of the data/instruction to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheFlushLine(u32 adr)
+{
+#ifdef CONFIG_PL310_ERRATA_588369
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INVLD_PA_OFFSET, adr);
+#else
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_INV_CLN_PA_OFFSET, adr);
+#endif
+	/* synchronize the processor */
+	dsb();
+}
+
+/****************************************************************************/
+/**
+* @brief	Flush the level 2 cache for the given address range.
+* 			If the bytes specified by the address range are cached by the L2
+* 			cache, the cacheline containing those bytes are invalidated. If the
+* 			cachelines are modified (dirty), they are written to the system
+* 			memory before the lines are invalidated.
+*
+* @param	adr: 32bit start address of the range to be flushed.
+* @param	len: Length of the range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_L2CacheFlushRange(u32 adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	volatile u32 *L2CCOffset = (volatile u32 *)(XPS_L2CC_BASEADDR +
+				    XPS_L2CC_CACHE_INV_CLN_PA_OFFSET);
+
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Disable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x3U);
+
+		while (LocalAddr < end) {
+			*L2CCOffset = LocalAddr;
+			Xil_L2CacheSync();
+			LocalAddr += cacheline;
+		}
+
+		/* Enable Write-back and line fills */
+		Xil_L2WriteDebugCtrl(0x0U);
+	}
+	/* synchronize the processor */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************/
+/**
+* @brief	Store a level 2 cache line. If the byte specified by the address
+* 			(adr) is cached by the L2 cache and the cacheline is modified
+* 			(dirty), the entire contents of the cacheline are written to
+*			system memory. After the store completes, the cacheline is marked
+*			as unmodified (not dirty).
+*
+* @param	adr: 32bit address of the data/instruction to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_L2CacheStoreLine(u32 adr)
+{
+	Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_CLEAN_PA_OFFSET, adr);
+	/* synchronize the processor */
+	dsb();
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h
new file mode 100644
index 0000000..b6614d5
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache.h
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions
+*
+* Cache functions provide access to cache related operations such as flush
+* and invalidate for instruction and data caches. It gives option to perform
+* the cache operations on a single cacheline, a range of memory and an entire
+* cache.
+*
+* @{
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/29/10 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb/dmb instructions in cache maintenance
+*		      APIs.
+* 
    
+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __GNUC__
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#elif defined (__ICCARM__)
+
+#define asm_cp15_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_mva_poc(param) __asm volatile ("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param));
+
+#define asm_cp15_inval_ic_line_mva_pou(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param));
+
+#define asm_cp15_inval_dc_line_sw(param) __asm volatile ("mcr " \
+			XREG_CP15_INVAL_DC_LINE_SW :: "r" (param));
+
+#define asm_cp15_clean_inval_dc_line_sw(param) __asm volatile ("mcr " \
+			XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param));
+
+#endif
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h
new file mode 100644
index 0000000..fa92c6b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_l.h
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_l.h
+*
+* Contains L1 and L2 specific functions for the ARM cache functionality
+* used by xcache.c. This functionality is being made available here for
+* more sophisticated users.
+*
+* @addtogroup a9_cache_apis
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  01/24/10 First release
+* 
    
+*
+******************************************************************************/
+#ifndef XIL_CACHE_MACH_H
+#define XIL_CACHE_MACH_H
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_DCacheInvalidateLine(u32 adr);
+void Xil_DCacheFlushLine(u32 adr);
+void Xil_DCacheStoreLine(u32 adr);
+void Xil_ICacheInvalidateLine(u32 adr);
+
+void Xil_L1DCacheEnable(void);
+void Xil_L1DCacheDisable(void);
+void Xil_L1DCacheInvalidate(void);
+void Xil_L1DCacheInvalidateLine(u32 adr);
+void Xil_L1DCacheInvalidateRange(u32 adr, u32 len);
+void Xil_L1DCacheFlush(void);
+void Xil_L1DCacheFlushLine(u32 adr);
+void Xil_L1DCacheFlushRange(u32 adr, u32 len);
+void Xil_L1DCacheStoreLine(u32 adr);
+
+void Xil_L1ICacheEnable(void);
+void Xil_L1ICacheDisable(void);
+void Xil_L1ICacheInvalidate(void);
+void Xil_L1ICacheInvalidateLine(u32 adr);
+void Xil_L1ICacheInvalidateRange(u32 adr, u32 len);
+
+void Xil_L2CacheEnable(void);
+void Xil_L2CacheDisable(void);
+void Xil_L2CacheInvalidate(void);
+void Xil_L2CacheInvalidateLine(u32 adr);
+void Xil_L2CacheInvalidateRange(u32 adr, u32 len);
+void Xil_L2CacheFlush(void);
+void Xil_L2CacheFlushLine(u32 adr);
+void Xil_L2CacheFlushRange(u32 adr, u32 len);
+void Xil_L2CacheStoreLine(u32 adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h
new file mode 100644
index 0000000..6e8cfa7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* 
    
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
new file mode 100644
index 0000000..490aebe
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_errata.h
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_errata.h
+*
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a srt  04/18/13 First release
+* 6.6   mus  12/07/17 Removed errata 753970, It fixes CR#989132.
+* 
    
+*
+******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
+
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
+#define ENABLE_ARM_ERRATA 1
+
+#ifdef ENABLE_ARM_ERRATA
+
+/**
+ *  Errata No: 	 742230
+ *  Description: DMB operation may be faulty
+ */
+#define CONFIG_ARM_ERRATA_742230 1
+
+/**
+ *  Errata No: 	 743622
+ *  Description: Faulty hazard checking in the Store Buffer may lead
+ *	         	 to data corruption.
+ */
+#define CONFIG_ARM_ERRATA_743622 1
+
+/**
+ *  Errata No: 	 775420
+ *  Description: A data cache maintenance operation which aborts,
+ *		 		 might lead to deadlock
+ */
+#define CONFIG_ARM_ERRATA_775420 1
+
+/**
+ *  Errata No: 	 794073
+ *  Description: Speculative instruction fetches with MMU disabled
+ *               might not comply with architectural requirements
+ */
+#define CONFIG_ARM_ERRATA_794073 1
+
+
+/** PL310 L2 Cache Errata */
+
+/**
+ *  Errata No: 	 588369
+ *  Description: Clean & Invalidate maintenance operations do not
+ *	   	 		 invalidate clean lines
+ */
+#define CONFIG_PL310_ERRATA_588369 1
+
+/**
+ *  Errata No: 	 727915
+ *  Description: Background Clean and Invalidate by Way operation
+ *		 can cause data corruption
+ */
+#define CONFIG_PL310_ERRATA_727915 1
+
+/*@}*/
+#endif  /* ENABLE_ARM_ERRATA */
+
+#endif  /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
new file mode 100644
index 0000000..d34fd21
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.c
@@ -0,0 +1,363 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex A53,A9,R5 exception
+* Handler.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
+*                         processors and added Xil_UndefinedExceptionHandler
+*                         for a53 32 bit and r5 as well.
+* 6.4   mus      08/06/17 Updated debug prints to replace %x with the %lx, to
+*                         fix the warnings.
+* 6.7   mna      26/04/18 Add an API to obtain a corresponding
+*                         Xil_ExceptionHandler entry from XExc_VectorTable.
+* 6.7  asa       18/05/18 Fix bugs in the API Xil_GetExceptionRegisterHandler.
+*
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+#if defined (__aarch64__)
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SyncAbortHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_ExceptionNullHandler, NULL},
+        {Xil_SErrorAbortHandler, NULL},
+
+};
+#else
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_UndefinedExceptionHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_PrefetchAbortHandler, NULL},
+	{Xil_DataAbortHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+};
+#endif
+#if !defined (__aarch64__)
+u32 DataAbortAddr;       /* Address of instruction causing data abort */
+u32 PrefetchAbortAddr;   /* Address of instruction causing prefetch abort */
+u32 UndefinedExceptionAddr;   /* Address of instruction causing Undefined
+							     exception */
+#endif
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific  exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param	Data is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+	(void) Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* @brief	The function is a common API used to initialize exception handlers
+*			across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
+*			and Cortex-A9, the exception handlers are being initialized
+*			statically and this function does not do anything.
+* 			However, it is still present to take care of backward compatibility
+*			issues (in earlier versions of BSPs, this API was being used to
+*			initialize exception handlers).
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+	return;
+}
+
+/*****************************************************************************/
+/**
+* @brief	Register a handler for a specific exception. This handler is being
+*			called when the processor encounters the specified exception.
+*
+* @param	exception_id contains the ID of the exception source and should
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*			Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+				    Xil_ExceptionHandler Handler,
+				    void *Data)
+{
+	XExc_VectorTable[Exception_id].Handler = Handler;
+	XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+* @brief	Get a handler for a specific exception. This handler is being
+*			called when the processor encounters the specified exception.
+*
+* @param	exception_id contains the ID of the exception source and should
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*			Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+					Xil_ExceptionHandler *Handler,
+					void **Data)
+{
+	*Handler = XExc_VectorTable[Exception_id].Handler;
+	*Data = XExc_VectorTable[Exception_id].Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief	Removes the Handler for a specific exception Id. The stub Handler
+*			is then registered for this exception Id.
+*
+* @param	exception_id contains the ID of the exception source and should
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+	Xil_ExceptionRegisterHandler(Exception_id,
+				       Xil_ExceptionNullHandler,
+				       NULL);
+}
+
+#if defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* Default Synchronous abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+
+void Xil_SyncAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Default SError abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param        None
+*
+* @return       None.
+*
+* @note         None.
+*
+****************************************************************************/
+void Xil_SErrorAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
+	while(1) {
+		;
+	}
+}
+#else
+/*****************************************************************************/
+/*
+*
+* Default Data abort handler which prints data fault status register through
+* which information about data fault can be acquired
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+#ifdef DEBUG
+	u32 FaultStatus;
+
+        xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+	        mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus);
+	    #else
+	        { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
+	        FaultStatus = Reg; }
+	    #endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register  %lx\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* Default Prefetch abort handler which prints prefetch fault status register through
+* which information about instruction prefetch fault can be acquired
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
+#ifdef DEBUG
+	u32 FaultStatus;
+
+    xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+        #ifdef __GNUC__
+	FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS);
+	    #elif defined (__ICCARM__)
+			mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus);
+	    #else
+			{ volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
+			FaultStatus = Reg; }
+		#endif
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register  %lx\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
+#endif
+	while(1) {
+		;
+	}
+}
+/*****************************************************************************/
+/*
+*
+* Default undefined exception handler which prints address of the undefined
+* instruction if debug prints are enabled
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_UndefinedExceptionHandler(void *CallBackRef){
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
+	while(1) {
+		;
+	}
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
new file mode 100644
index 0000000..8330387
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_exception.h
@@ -0,0 +1,260 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
+* 6.7   mna      26/04/18 Add API Xil_GetExceptionRegisterHandler.
+* 6.7   asa      18/05/18 Update signature of API Xil_GetExceptionRegisterHandler.
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0U
+#if defined (__aarch64__)
+#define XIL_EXCEPTION_ID_SYNC_INT		1U
+#define XIL_EXCEPTION_ID_IRQ_INT		2U
+#define XIL_EXCEPTION_ID_FIQ_INT		3U
+#define XIL_EXCEPTION_ID_SERROR_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_LAST			5U
+#else
+#define XIL_EXCEPTION_ID_RESET			0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
+#define XIL_EXCEPTION_ID_SWI_INT		2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_IRQ_INT		5U
+#define XIL_EXCEPTION_ID_FIQ_INT		6U
+#define XIL_EXCEPTION_ID_LAST			6U
+#endif
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* @brief	Enable Exceptions.
+*
+* @param	Mask: Value for enabling the exceptions.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*			C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionEnableMask(Mask)	\
+		{								\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \
+		}
+#endif
+/****************************************************************************/
+/**
+* @brief	Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* @brief	Disable Exceptions.
+*
+* @param	Mask: Value for disabling the exceptions.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*			C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#if defined (__GNUC__) || defined (__ICCARM__)
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+#else
+#define Xil_ExceptionDisableMask(Mask)	\
+		{									\
+		  register u32 Reg __asm("cpsr"); \
+		  mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \
+		}
+#endif
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+#if !defined (__aarch64__) && !defined (ARMA53_32)
+/****************************************************************************/
+/**
+* @brief	Enable nested interrupts by clearing the I and F bits in CPSR. This
+* 			API is defined for cortex-a9 and cortex-r5.
+*
+* @return   None.
+*
+* @note     This macro is supposed to be used from interrupt handlers. In the
+*			interrupt handler the interrupts are disabled by default (I and F
+*			are 1). To allow nesting of interrupts, this macro should be
+*			used. It clears the I and F bits by changing the ARM mode to
+*			system mode. Once these bits are cleared and provided the
+*			preemption of interrupt conditions are met in the GIC, nesting of
+*			interrupts will start happening.
+*			Caution: This macro must be used with caution. Before calling this
+*			macro, the user must ensure that the source of the current IRQ
+*			is appropriately cleared. Otherwise, as soon as we clear the I and
+*			F bits, there can be an infinite loop of interrupts with an
+*			eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("mrs     lr, spsr");  \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}");
+
+/****************************************************************************/
+/**
+* @brief	Disable the nested interrupts by setting the I and F bits. This API
+*			is defined for cortex-a9 and cortex-r5.
+*
+* @return   None.
+*
+* @note     This macro is meant to be called in the interrupt service routines.
+*			This macro cannot be used independently. It can only be used when
+*			nesting of interrupts have been enabled by using the macro
+*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
+*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+*			point. The user then must call this macro before exiting the interrupt
+*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
+*			hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     spsr_cxsf, lr"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+
+#endif
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+extern void Xil_GetExceptionRegisterHandler(u32 Exception_id,
+					Xil_ExceptionHandler *Handler, void **Data);
+
+extern void Xil_ExceptionInit(void);
+#if defined (__aarch64__)
+void Xil_SyncAbortHandler(void *CallBackRef);
+void Xil_SErrorAbortHandler(void *CallBackRef);
+#else
+extern void Xil_DataAbortHandler(void *CallBackRef);
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h
new file mode 100644
index 0000000..d4434d0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* 
    
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c
new file mode 100644
index 0000000..90bfc81
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 
    
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a 16-bit endian converion.
+*
+* @param	Data: 16 bit value to be converted
+*
+* @return	16 bit Data with converted endianess
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a 32-bit endian converion.
+*
+* @param	Data: 32 bit value to be converted
+*
+* @return	32 bit data with converted endianess
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
new file mode 100644
index 0000000..9c5aa43
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_io.h
@@ -0,0 +1,345 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+* 
    
+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+#  define INST_SYNC		mbar(0)
+#  define DATA_SYNC		mbar(1)
+# else
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+# endif
+#else
+# define SYNCHRONIZE_IO
+# define INST_SYNC
+# define DATA_SYNC
+# define INST_SYNC
+# define DATA_SYNC
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline
+#else
+#define INLINE __inline
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading
+*           from the specified address and returning the 8 bit Value read from
+*            that address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading from
+*           the specified address and returning the 16 bit Value read from that
+*           address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by
+*           reading from the specified address and returning the 32 bit Value
+*           read  from that address.
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief     Performs an input operation for a memory location by reading the
+*            64 bit Value read  from that address.
+*
+*
+* @param	Addr: contains the address to perform the input operation
+*
+* @return	The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for an memory location by
+*           writing the 8 bit Value to the the specified address.
+*
+* @param	Addr: contains the address to perform the output operation
+* @param	Value: contains the 8 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+	volatile u8 *LocalAddr = (volatile u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*            16 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+	volatile u16 *LocalAddr = (volatile u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           32 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the 32 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+#ifndef ENABLE_SAFETY
+	volatile u32 *LocalAddr = (volatile u32 *)Addr;
+	*LocalAddr = Value;
+#else
+	XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           64 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains 64 bit Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+	volatile u64 *LocalAddr = (volatile u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+# else
+# define Xil_In16BE	Xil_In16
+# define Xil_In32BE	Xil_In32
+# define Xil_Out16BE	Xil_Out16
+# define Xil_Out32BE	Xil_Out32
+# define Xil_Htons(Data) (Data)
+# define Xil_Htonl(Data) (Data)
+# define Xil_Ntohs(Data) (Data)
+# define Xil_Ntohl(Data) (Data)
+#endif
+#else
+# define Xil_In16LE	Xil_In16
+# define Xil_In32LE	Xil_In32
+# define Xil_Out16LE	Xil_Out16
+# define Xil_Out32LE	Xil_Out32
+# define Xil_Htons	Xil_EndianSwap16
+# define Xil_Htonl	Xil_EndianSwap32
+# define Xil_Ntohs	Xil_EndianSwap16
+# define Xil_Ntohl	Xil_EndianSwap32
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In16(Addr);
+	return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr)
+#endif
+#else
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+	u32 value = Xil_In32(Addr);
+	return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value)
+#endif
+#else
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+	Value = Xil_EndianSwap16(Value);
+	Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value)
+#endif
+#else
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+	Value = Xil_EndianSwap32(Value);
+	Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h
new file mode 100644
index 0000000..ebafde8
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ *   XGpio_mSetDataDirection
+ *   XGpio_mGetDataReg
+ *   XGpio_mSetDataReg
+ *   XIIC_RESET
+ *   XIIC_CLEAR_STATS
+ *   XSpi_mReset
+ *   XSysAce_mSetCfgAddr
+ *   XSysAce_mIsCfgDone
+ *   XTft_mSetPixel
+ *   XTft_mGetPixel
+ *   XWdtTb_mEnableWdt
+ *   XWdtTb_mDisbleWdt
+ *   XWdtTb_mRestartWdt
+ *   XWdtTb_mGetTimebaseReg
+ *   XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c
new file mode 100644
index 0000000..0929a68
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.c
@@ -0,0 +1,83 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.c
+*
+* This file contains xil mem copy function to use in case of word aligned
+* data copies.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/***************** Inline Functions Definitions ********************/
+/*****************************************************************************/
+/**
+* @brief       This  function copies memory from once location to other.
+*
+* @param       dst: pointer pointing to destination memory
+*
+* @param       src: pointer pointing to source memory
+*
+* @param       cnt: 32 bit length of bytes to be copied
+*
+*****************************************************************************/
+void Xil_MemCpy(void* dst, const void* src, u32 cnt)
+{
+	char *d = (char*)(void *)dst;
+	const char *s = src;
+
+	while (cnt >= sizeof (int)) {
+		*(int*)d = *(int*)s;
+		d += sizeof (int);
+		s += sizeof (int);
+		cnt -= sizeof (int);
+	}
+	while ((cnt) > 0U){
+		*d = *s;
+		d += 1U;
+		s += 1U;
+		cnt -= 1U;
+	}
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h
new file mode 100644
index 0000000..a2d5e66
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mem.h
@@ -0,0 +1,59 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* 
    
+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c
new file mode 100644
index 0000000..e114d14
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.c
@@ -0,0 +1,524 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_misc_reset.c
+*
+* This file contains the implementation of the reset sequence for various
+* zynq ps devices like DDR,OCM,Slcr,Ethernet,Usb.. controllers. The reset
+* sequence provided to the interfaces is based on the provision in
+* slcr reset functional blcok.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release
+* 5.4	pkp	  09/11/15 Change the description for XOcm_Remap function
+* 
    
+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_misc_psreset_api.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for ddr reset.
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XDdr_ResetHw(void)
+{
+	u32 RegVal;
+
+	/* Unlock the slcr register access lock */
+	 Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert and deassert the ddr softreset bit */
+     RegVal = 	Xil_In32(XDDRC_CTRL_BASEADDR);
+	 RegVal &= (u32)(~XDDRPS_CTRL_RESET_MASK);
+	 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+	 RegVal |= ((u32)XDDRPS_CTRL_RESET_MASK);
+	 Xil_Out32(XDDRC_CTRL_BASEADDR,RegVal);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for remapping the ocm memory region
+* to postbootrom state.
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XOcm_Remap(void)
+{
+	u32 RegVal;
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Map the ocm region to postbootrom state */
+	RegVal = Xil_In32(XSLCR_OCM_CFG_ADDR);
+	RegVal = (RegVal & (u32)(~XSLCR_OCM_CFG_HIADDR_MASK)) | (u32)XSLCR_OCM_CFG_RESETVAL;
+	Xil_Out32(XSLCR_OCM_CFG_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC reset sequence
+*
+* @param   BaseAddress of the interface
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSmc_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+
+	/* Clear the interuupts */
+	RegVal = Xil_In32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET);
+	RegVal = RegVal | (u32)XSMC_MEMC_CLR_CONFIG_MASK;
+	Xil_Out32(BaseAddress + XSMC_MEMC_CLR_CONFIG_OFFSET, RegVal);
+	/* Clear the idle counter registers */
+	Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_0_OFFSET, 0x0U);
+	Xil_Out32(BaseAddress + XSMC_REFRESH_PERIOD_1_OFFSET, 0x0U);
+	/* Update the ecc registers with reset values */
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCFG1_OFFSET,
+							XSMC_ECC_MEMCFG1_RESET_VAL);
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD1_OFFSET,
+							XSMC_ECC_MEMCMD1_RESET_VAL);
+	Xil_Out32(BaseAddress + XSMC_ECC_MEMCMD2_OFFSET,
+							XSMC_ECC_MEMCMD2_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr mio registers
+* with reset values
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_MioWriteResetValues(void)
+{
+	u32 i;
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Update all the MIO registers with reset values */
+    for (i=0U; i<=1U;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_00_RESET_VAL);
+	}
+	for (; i<=8U;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_02_RESET_VAL);
+	}
+	for (; i<=53U ;i++)
+	{
+		Xil_Out32((XSLCR_MIO_PIN_00_ADDR + (i * 4U)),
+								XSLCR_MIO_PIN_00_RESET_VAL);
+	}
+
+
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for updating the slcr pll registers
+* with reset values
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_PllWriteResetValues(void)
+{
+
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+
+	/* update the pll control registers with reset values */
+	Xil_Out32(XSLCR_IO_PLL_CTRL_ADDR, XSLCR_IO_PLL_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_ARM_PLL_CTRL_ADDR, XSLCR_ARM_PLL_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_PLL_CTRL_ADDR, XSLCR_DDR_PLL_CTRL_RESET_VAL);
+	/* update the pll config registers with reset values */
+	Xil_Out32(XSLCR_IO_PLL_CFG_ADDR, XSLCR_IO_PLL_CFG_RESET_VAL);
+	Xil_Out32(XSLCR_ARM_PLL_CFG_ADDR, XSLCR_ARM_PLL_CFG_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_PLL_CFG_ADDR, XSLCR_DDR_PLL_CFG_RESET_VAL);
+	/* update the clock control registers with reset values */
+	Xil_Out32(XSLCR_ARM_CLK_CTRL_ADDR, XSLCR_ARM_CLK_CTRL_RESET_VAL);
+	Xil_Out32(XSLCR_DDR_CLK_CTRL_ADDR, XSLCR_DDR_CLK_CTRL_RESET_VAL);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for disabling the level shifters
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_DisableLevelShifters(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Disable the level shifters */
+	RegVal = Xil_In32(XSLCR_LVL_SHFTR_EN_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_LVL_SHFTR_EN_MASK);
+	Xil_Out32(XSLCR_LVL_SHFTR_EN_ADDR, RegVal);
+
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for OCM software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_OcmReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_OCM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_OCM_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_OCM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_OCM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for Ethernet software reset from
+* the slcr
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_EmacPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_GEM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_GEM_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_GEM_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GEM_RST_CTRL_ADDR, RegVal);
+}
+
+/*****************************************************************************/
+/**
+* This function contains the implementation for USB software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_UsbPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_USB_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_USB_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_USB_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_USB_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for QSPI software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_QspiPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_QSPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_LQSPI_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_QSPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_LQSPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SPI software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_SpiPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_SPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_SPI_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_SPI_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SPI_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for i2c software reset from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_I2cPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_I2C_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_I2C_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_I2C_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_I2C_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for UART software reset from the
+* slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_UartPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_UART_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_UART_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_UART_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_UART_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for CAN software reset from slcr
+* registers
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_CanPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_CAN_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_CAN_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_CAN_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_CAN_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for SMC software reset from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_SmcPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_SMC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_SMC_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_SMC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_SMC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for DMA controller software reset
+* from the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_DmaPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_DMAC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_DMAC_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_DMAC_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_DMAC_RST_CTRL_ADDR, RegVal);
+}
+/*****************************************************************************/
+/**
+* This function contains the implementation for Gpio AMBA software reset from
+* the slcr
+*
+* @param   N/A.
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XSlcr_GpioPsReset(void)
+{
+	u32 RegVal;
+	/* Unlock the slcr register access lock */
+	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
+	/* Assert the reset */
+	RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+	RegVal = RegVal | ((u32)XSLCR_GPIO_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+	/* Release the reset */
+	RegVal = Xil_In32(XSLCR_GPIO_RST_CTRL_ADDR);
+	RegVal = RegVal & (u32)(~XSLCR_GPIO_RST_CTRL_VAL);
+	Xil_Out32(XSLCR_GPIO_RST_CTRL_ADDR, RegVal);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h
new file mode 100644
index 0000000..c228c98
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_misc_psreset_api.h
@@ -0,0 +1,277 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_misc_psreset_api.h
+*
+* This file contains the various register defintions and function prototypes for
+* implementing the reset functionality of zynq ps devices
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00b kpc   03/07/13 First release.
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_MISC_RESET_H		/* prevent circular inclusions */
+#define XIL_MISC_RESET_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+#define XDDRC_CTRL_BASEADDR				0xF8006000U
+#define XSLCR_BASEADDR					0xF8000000U
+/**< OCM configuration register */
+#define XSLCR_OCM_CFG_ADDR				(XSLCR_BASEADDR + 0x00000910U)
+/**< SLCR unlock register */
+#define XSLCR_UNLOCK_ADDR				(XSLCR_BASEADDR + 0x00000008U)
+/**< SLCR GEM0 rx clock control register */
+#define XSLCR_GEM0_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000138U)
+/**< SLCR GEM1 rx clock control register */
+#define XSLCR_GEM1_RCLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x0000013CU)
+/**< SLCR GEM0 clock control register */
+#define XSLCR_GEM0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000140U)
+/**< SLCR GEM1 clock control register */
+#define XSLCR_GEM1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000144U)
+/**< SLCR SMC clock control register */
+#define XSLCR_SMC_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000148U)
+/**< SLCR GEM reset control register */
+#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)
+/**< SLCR USB0 clock control register */
+#define XSLCR_USB0_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000130U)
+/**< SLCR USB1 clock control register */
+#define XSLCR_USB1_CLK_CTRL_ADDR		(XSLCR_BASEADDR + 0x00000134U)
+/**< SLCR USB1 reset control register */
+#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)
+/**< SLCR SMC reset control register */
+#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)
+/**< SLCR Level shifter enable register */
+#define XSLCR_LVL_SHFTR_EN_ADDR			(XSLCR_BASEADDR + 0x00000900U)
+/**< SLCR ARM pll control register */
+#define XSLCR_ARM_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000100U)
+/**< SLCR DDR pll control register */
+#define XSLCR_DDR_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000104U)
+/**< SLCR IO pll control register */
+#define XSLCR_IO_PLL_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000108U)
+/**< SLCR ARM pll configuration register */
+#define XSLCR_ARM_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000110U)
+/**< SLCR DDR pll configuration register */
+#define XSLCR_DDR_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000114U)
+/**< SLCR IO pll configuration register */
+#define XSLCR_IO_PLL_CFG_ADDR			(XSLCR_BASEADDR + 0x00000118U)
+/**< SLCR ARM clock control register */
+#define XSLCR_ARM_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000120U)
+/**< SLCR DDR clock control register */
+#define XSLCR_DDR_CLK_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000124U)
+/**< SLCR MIO pin address register */
+#define XSLCR_MIO_PIN_00_ADDR			(XSLCR_BASEADDR + 0x00000700U)
+/**< SLCR DMAC reset control address register */
+#define XSLCR_DMAC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000020CU)
+/**< SLCR USB reset control address register */
+/*#define XSLCR_USB_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000210U)*/
+/**< SLCR GEM reset control address register */
+/*#define XSLCR_GEM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000214U)*/
+/**< SLCR SDIO reset control address register */
+#define XSLCR_SDIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000218U)
+/**< SLCR SPI reset control address register */
+#define XSLCR_SPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000021CU)
+/**< SLCR CAN reset control address register */
+#define XSLCR_CAN_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000220U)
+/**< SLCR I2C reset control address register */
+#define XSLCR_I2C_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000224U)
+/**< SLCR UART reset control address register */
+#define XSLCR_UART_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000228U)
+/**< SLCR GPIO reset control address register */
+#define XSLCR_GPIO_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x0000022CU)
+/**< SLCR LQSPI reset control address register */
+#define XSLCR_LQSPI_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000230U)
+/**< SLCR SMC reset control address register */
+/*#define XSLCR_SMC_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000234U)*/
+/**< SLCR OCM reset control address register */
+#define XSLCR_OCM_RST_CTRL_ADDR			(XSLCR_BASEADDR + 0x00000238U)
+
+/**< SMC mem controller clear config register */
+#define XSMC_MEMC_CLR_CONFIG_OFFSET			0x0000000CU
+/**< SMC idlecount configuration register */
+#define XSMC_REFRESH_PERIOD_0_OFFSET		0x00000020U
+#define XSMC_REFRESH_PERIOD_1_OFFSET		0x00000024U
+/**< SMC ECC configuration register */
+#define XSMC_ECC_MEMCFG1_OFFSET				0x00000404U
+/**< SMC ECC command 1 register */
+#define XSMC_ECC_MEMCMD1_OFFSET				0x00000404U
+/**< SMC ECC command 2 register */
+#define XSMC_ECC_MEMCMD2_OFFSET				0x00000404U
+
+/**< SLCR unlock code */
+#define XSLCR_UNLOCK_CODE		0x0000DF0DU
+
+/**< SMC mem clear configuration mask */
+#define XSMC_MEMC_CLR_CONFIG_MASK 	0x000005FU
+/**< SMC ECC memconfig 1 reset value */
+#define XSMC_ECC_MEMCFG1_RESET_VAL 	0x0000043U
+/**< SMC ECC memcommand 1 reset value */
+#define XSMC_ECC_MEMCMD1_RESET_VAL 	0x01300080U
+/**< SMC ECC memcommand 2 reset value */
+#define XSMC_ECC_MEMCMD2_RESET_VAL 	0x01E00585U
+
+/**< DDR controller reset bit mask */
+#define XDDRPS_CTRL_RESET_MASK 		0x00000001U
+/**< SLCR OCM configuration reset value*/
+#define XSLCR_OCM_CFG_RESETVAL		0x00000008U
+/**< SLCR OCM bank selection mask*/
+#define XSLCR_OCM_CFG_HIADDR_MASK	0x0000000FU
+/**< SLCR level shifter enable mask*/
+#define XSLCR_LVL_SHFTR_EN_MASK		0x0000000FU
+
+/**< SLCR PLL register reset values */
+#define XSLCR_ARM_PLL_CTRL_RESET_VAL	0x0001A008U
+#define XSLCR_DDR_PLL_CTRL_RESET_VAL	0x0001A008U
+#define XSLCR_IO_PLL_CTRL_RESET_VAL		0x0001A008U
+#define XSLCR_ARM_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_DDR_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_IO_PLL_CFG_RESET_VAL		0x00177EA0U
+#define XSLCR_ARM_CLK_CTRL_RESET_VAL	0x1F000400U
+#define XSLCR_DDR_CLK_CTRL_RESET_VAL	0x18400003U
+
+/**< SLCR MIO register default values */
+#define XSLCR_MIO_PIN_00_RESET_VAL		0x00001601U
+#define XSLCR_MIO_PIN_02_RESET_VAL		0x00000601U
+
+/**< SLCR Reset control registers default values */
+#define XSLCR_DMAC_RST_CTRL_VAL			0x00000001U
+#define XSLCR_GEM_RST_CTRL_VAL			0x000000F3U
+#define XSLCR_USB_RST_CTRL_VAL			0x00000003U
+#define XSLCR_I2C_RST_CTRL_VAL			0x00000003U
+#define XSLCR_SPI_RST_CTRL_VAL			0x0000000FU
+#define XSLCR_UART_RST_CTRL_VAL			0x0000000FU
+#define XSLCR_QSPI_RST_CTRL_VAL			0x00000003U
+#define XSLCR_GPIO_RST_CTRL_VAL			0x00000001U
+#define XSLCR_SMC_RST_CTRL_VAL			0x00000003U
+#define XSLCR_OCM_RST_CTRL_VAL			0x00000001U
+#define XSLCR_SDIO_RST_CTRL_VAL			0x00000033U
+#define XSLCR_CAN_RST_CTRL_VAL			0x00000003U
+/**************************** Type Definitions *******************************/
+
+/* the following data type is used to hold a null terminated version string
+ * consisting of the following format, "X.YYX"
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Performs reset operation to the ddr interface
+ */
+void XDdr_ResetHw(void);
+/*
+ * Map the ocm region to post bootrom state
+ */
+void XOcm_Remap(void);
+/*
+ * Performs the smc interface reset
+ */
+void XSmc_ResetHw(u32 BaseAddress);
+/*
+ * updates the MIO registers with reset values
+ */
+void XSlcr_MioWriteResetValues(void);
+/*
+ * updates the PLL and clock registers with reset values
+ */
+void XSlcr_PllWriteResetValues(void);
+/*
+ * Disables the level shifters
+ */
+void XSlcr_DisableLevelShifters(void);
+/*
+ * provides softreset to the GPIO interface
+ */
+void XSlcr_GpioPsReset(void);
+/*
+ * provides softreset to the DMA interface
+ */
+void XSlcr_DmaPsReset(void);
+/*
+ * provides softreset to the SMC interface
+ */
+void XSlcr_SmcPsReset(void);
+/*
+ * provides softreset to the CAN interface
+ */
+void XSlcr_CanPsReset(void);
+/*
+ * provides softreset to the Uart interface
+ */
+void XSlcr_UartPsReset(void);
+/*
+ * provides softreset to the I2C interface
+ */
+void XSlcr_I2cPsReset(void);
+/*
+ * provides softreset to the SPI interface
+ */
+void XSlcr_SpiPsReset(void);
+/*
+ * provides softreset to the QSPI interface
+ */
+void XSlcr_QspiPsReset(void);
+/*
+ * provides softreset to the USB interface
+ */
+void XSlcr_UsbPsReset(void);
+/*
+ * provides softreset to the GEM interface
+ */
+void XSlcr_EmacPsReset(void);
+/*
+ * provides softreset to the OCM interface
+ */
+void XSlcr_OcmReset(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_MISC_RESET_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c
new file mode 100644
index 0000000..1f58d90
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.c
@@ -0,0 +1,190 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.c
+*
+* This file provides APIs for enabling/disabling MMU and setting the memory
+* attributes for sections, in the MMU translation table.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 3.05a asa  03/10/12 Modified the Xil_EnableMMU to invalidate the caches
+*		      before enabling back.
+* 3.05a asa  04/15/12 Modified the Xil_SetTlbAttributes routine so that
+*		      translation table and branch predictor arrays are
+*		      invalidated, D-cache flushed before the attribute
+*		      change is applied. This is done so that the user
+*		      need not call Xil_DisableMMU before calling
+*		      Xil_SetTlbAttributes.
+* 3.10a  srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 3.11a  asa 09/23/13 Modified Xil_SetTlbAttributes to flush the complete
+*			 D cache after the translation table update. Removed the
+*			 redundant TLB invalidation in the same API at the beginning.
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mmu.h"
+#include "xil_errata.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+extern u32 MMUTable;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* @brief	This function sets the memory attributes for a section covering 1MB
+*			of memory in the translation table.
+*
+* @param	Addr: 32-bit address for which memory attributes need to be set.
+* @param	attrib: Attribute for the given memory region. xil_mmu.h contains
+*			definitions of commonly used memory attributes which can be
+*			utilized for this function.
+*
+*
+* @return	None.
+*
+* @note		The MMU or D-cache does not need to be disabled before changing a
+*			translation table entry.
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
+{
+	u32 *ptr;
+	u32 section;
+
+	section = Addr / 0x100000U;
+	ptr = &MMUTable;
+	ptr += section;
+	if(ptr != NULL) {
+		*ptr = (Addr & 0xFFF00000U) | attrib;
+	}
+
+	Xil_DCacheFlush();
+
+	mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+	/* Invalidate all branch predictors */
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+
+	dsb(); /* ensure completion of the BP and TLB invalidation */
+    isb(); /* synchronize context on this processor */
+}
+
+/*****************************************************************************/
+/**
+* @brief	Enable MMU for cortex A9 processor. This function invalidates the
+*			instruction and data caches, and then enables MMU.
+*
+* @param	None.
+* @return	None.
+*
+******************************************************************************/
+void Xil_EnableMMU(void)
+{
+	u32 Reg;
+	Xil_DCacheInvalidate();
+	Xil_ICacheInvalidate();
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+	{ volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+	  Reg = Cp15Reg; }
+#endif
+	Reg |= (u32)0x05U;
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+
+	dsb();
+	isb();
+}
+
+/*****************************************************************************/
+/**
+* @brief	Disable MMU for Cortex A9 processors. This function invalidates
+*			the TLBs, Branch Predictor Array and flushed the D Caches before
+*			disabling the MMU.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		When the MMU is disabled, all the memory accesses are treated as
+*			strongly ordered.
+******************************************************************************/
+void Xil_DisableMMU(void)
+{
+	u32 Reg;
+
+	mtcp(XREG_CP15_INVAL_UTLB_UNLOCKED, 0U);
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0U);
+	Xil_DCacheFlush();
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_SYS_CONTROL, Reg);
+#else
+	{ volatile register u32 Cp15Reg __asm(XREG_CP15_SYS_CONTROL);
+	  Reg = Cp15Reg; }
+#endif
+	Reg &= (u32)(~0x05U);
+#ifdef CONFIG_ARM_ERRATA_794073
+	/* Disable Branch Prediction */
+	Reg &= (u32)(~0x800U);
+#endif
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h
new file mode 100644
index 0000000..dd14b63
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_mmu.h
@@ -0,0 +1,108 @@
+/******************************************************************************
+*
+* Copyright (C) 2012 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
+*
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  01/12/12 Initial version
+* 4.2	pkp	 07/21/14 Included xil_types.h file which contains definition for
+*					  u32 which resolves issue of CR#805869
+* 5.4	pkp	 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
+* 
    
+*
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/* Memory type */
+#define NORM_NONCACHE 0x11DE2 	/* Normal Non-cacheable */
+#define STRONG_ORDERED 0xC02	/* Strongly ordered */
+#define DEVICE_MEMORY 0xC06		/* Device memory */
+#define RESERVED 0x0			/* reserved memory */
+
+/* Normal write-through cacheable shareable */
+#define NORM_WT_CACHE 0x16DEA
+
+/* Normal write back cacheable shareable */
+#define NORM_WB_CACHE 0x15DE6
+
+/* shareability attribute */
+#define SHAREABLE (0x1 << 16)
+#define NON_SHAREABLE	(~(0x1 << 16))
+
+/* Execution type */
+#define EXECUTE_NEVER ((0x1 << 4) | (0x1 << 0))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMMU(void);
+void Xil_DisableMMU(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
new file mode 100644
index 0000000..dc0897f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.c
@@ -0,0 +1,443 @@
+/*---------------------------------------------------*/
+/* Modified from :                                   */
+/* Public Domain version of printf                   */
+/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
+/* For Embedded Systems Programming, 1991            */
+/*                                                   */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include 
+#include 
+#include 
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+    s32 len;
+    s32 num1;
+    s32 num2;
+    char8 pad_character;
+    s32 do_padding;
+    s32 left_flag;
+    s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine puts pad characters into the output  */
+/* buffer.                                           */
+/*                                                   */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+    s32 i;
+
+    if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+		i=(par->len);
+        for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+            outbyte( par->pad_character);
+#endif
+		}
+    }
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a string to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+static void outs(const charptr lp, struct params_s *par)
+{
+    charptr LocalPtr;
+	LocalPtr = lp;
+    /* pad on left if needed                         */
+	if(LocalPtr != NULL) {
+		par->len = (s32)strlen( LocalPtr);
+	}
+    padding( !(par->left_flag), par);
+
+    /* Move string to the buffer                     */
+    while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+		(par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+        outbyte(*LocalPtr);
+#endif
+		LocalPtr += 1;
+}
+
+    /* Pad on right if needed                        */
+    /* CR 439175 - elided next stmt. Seemed bogus.   */
+    /* par->len = strlen( lp)                      */
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a number to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[32];
+    const char8 digits[] = "0123456789ABCDEF";
+    u32 num;
+    for(i = 0; i<32; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = n;
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+	outbyte( outbuf[i] );
+#endif
+		i--;
+}
+    padding( par->left_flag, par);
+}
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a 64-bit number to the output  */
+/* buffer as directed by the padding and positioning */
+/* flags. 											 */
+/*                                                   */
+#if defined (__aarch64__)
+static void outnum1( const s64 n, const s32 base, params_t *par)
+{
+    s32 negative;
+	s32 i;
+    char8 outbuf[64];
+    const char8 digits[] = "0123456789ABCDEF";
+    u64 num;
+    for(i = 0; i<64; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = (n);
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+	outbyte( outbuf[i] );
+		i--;
+}
+    padding( par->left_flag, par);
+}
+#endif
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine gets a number from the format        */
+/* string.                                           */
+/*                                                   */
+static s32 getnum( charptr* linep)
+{
+    s32 n;
+    s32 ResultIsDigit = 0;
+    charptr cptr;
+    n = 0;
+    cptr = *linep;
+	if(cptr != NULL){
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    while (ResultIsDigit != 0) {
+		if(cptr != NULL){
+			n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+			cptr += 1;
+			if(cptr != NULL){
+				ResultIsDigit = isdigit(((s32)*cptr));
+			}
+		}
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    *linep = ((charptr )(cptr));
+    return(n);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine operates just like a printf/sprintf  */
+/* routine. It outputs a set of data under the       */
+/* control of a formatting string. Not all of the    */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded  */
+/* systems work. Primarily the floating point        */
+/* routines are omitted. Other formats could be      */
+/* added easily by following the examples shown for  */
+/* the supported formats.                            */
+/*                                                   */
+
+/* void esp_printf( const func_ptr f_ptr,
+   const charptr ctrl1, ...) */
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+void xil_printf( const char8 *ctrl1, ...){
+	XPVXenConsole_Printf(ctrl1);
+}
+#else
+void xil_printf( const char8 *ctrl1, ...)
+{
+	s32 Check;
+#if defined (__aarch64__)
+    s32 long_flag;
+#endif
+    s32 dot_flag;
+
+    params_t par;
+
+    char8 ch;
+    va_list argp;
+    char8 *ctrl = (char8 *)ctrl1;
+
+    va_start( argp, ctrl1);
+
+    while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+        /* move format string chars to buffer until a  */
+        /* format control is found.                    */
+        if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+            outbyte(*ctrl);
+#endif
+			ctrl += 1;
+            continue;
+        }
+
+        /* initialize all the flags for this format.   */
+        dot_flag = 0;
+#if defined (__aarch64__)
+		long_flag = 0;
+#endif
+        par.unsigned_flag = 0;
+		par.left_flag = 0;
+		par.do_padding = 0;
+        par.pad_character = ' ';
+        par.num2=32767;
+		par.num1=0;
+		par.len=0;
+
+ try_next:
+		if(ctrl != NULL) {
+			ctrl += 1;
+		}
+		if(ctrl != NULL) {
+			ch = *ctrl;
+		}
+		else {
+			ch = *ctrl;
+		}
+
+        if (isdigit((s32)ch) != 0) {
+            if (dot_flag != 0) {
+                par.num2 = getnum(&ctrl);
+			}
+            else {
+                if (ch == '0') {
+                    par.pad_character = '0';
+				}
+				if(ctrl != NULL) {
+			par.num1 = getnum(&ctrl);
+				}
+                par.do_padding = 1;
+            }
+            if(ctrl != NULL) {
+			ctrl -= 1;
+			}
+            goto try_next;
+        }
+
+        switch (tolower((s32)ch)) {
+            case '%':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( '%');
+#endif
+                Check = 1;
+                break;
+
+            case '-':
+                par.left_flag = 1;
+                Check = 0;
+                break;
+
+            case '.':
+                dot_flag = 1;
+                Check = 0;
+                break;
+
+            case 'l':
+            #if defined (__aarch64__)
+                long_flag = 1;
+            #endif
+                Check = 0;
+                break;
+
+            case 'u':
+                par.unsigned_flag = 1;
+                /* fall through */
+            case 'i':
+            case 'd':
+                #if defined (__aarch64__)
+                if (long_flag != 0){
+			        outnum1((s64)va_arg(argp, s64), 10L, &par);
+                }
+                else {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+                #else
+                    outnum( va_arg(argp, s32), 10L, &par);
+                #endif
+				Check = 1;
+                break;
+            case 'p':
+                #if defined (__aarch64__)
+                par.unsigned_flag = 1;
+			    outnum1((s64)va_arg(argp, s64), 16L, &par);
+			    Check = 1;
+                break;
+                #endif
+            case 'X':
+            case 'x':
+                par.unsigned_flag = 1;
+                #if defined (__aarch64__)
+                if (long_flag != 0) {
+				    outnum1((s64)va_arg(argp, s64), 16L, &par);
+				}
+				else {
+				    outnum((s32)va_arg(argp, s32), 16L, &par);
+                }
+                #else
+                outnum((s32)va_arg(argp, s32), 16L, &par);
+                #endif
+                Check = 1;
+                break;
+
+            case 's':
+                outs( va_arg( argp, char *), &par);
+                Check = 1;
+                break;
+
+            case 'c':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( va_arg( argp, s32));
+#endif
+                Check = 1;
+                break;
+
+            case '\\':
+                switch (*ctrl) {
+                    case 'a':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x07));
+#endif
+                        break;
+                    case 'h':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x08));
+#endif
+                        break;
+                    case 'r':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+#endif
+                        break;
+                    case 'n':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+                        outbyte( ((char8)0x0A));
+#endif
+                        break;
+                    default:
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( *ctrl);
+#endif
+                        break;
+                }
+                ctrl += 1;
+                Check = 0;
+                break;
+
+            default:
+		Check = 1;
+		break;
+        }
+        if(Check == 1) {
+			if(ctrl != NULL) {
+				ctrl += 1;
+			}
+                continue;
+        }
+        goto try_next;
+    }
+    va_end( argp);
+}
+#endif
+/*---------------------------------------------------*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
new file mode 100644
index 0000000..016ae3b
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_printf.h
@@ -0,0 +1,48 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+#include "xil_types.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/*                                                   */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
new file mode 100644
index 0000000..972a310
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleepcommon.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+*@file xil_sleepcommon.c
+*
+* This file contains the sleep API's
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 	srm  	 11/02/17 First release
+* 
    
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "sleep.h"
+
+/****************************  Constant Definitions  *************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This API gives delay in sec
+*
+* @param            seconds - delay time in seconds
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+ void sleep(unsigned int seconds)
+ {
+#if defined (ARMR5)
+	sleep_R5(seconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+	sleep_A53(seconds);
+#elif defined (__MICROBLAZE__)
+	sleep_MB(seconds);
+#else
+	sleep_A9(seconds);
+#endif
+
+ }
+
+/****************************************************************************/
+/**
+*
+* This API gives delay in usec
+*
+* @param            useconds - delay time in useconds
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+ void usleep(unsigned long useconds)
+ {
+#if defined (ARMR5)
+	usleep_R5(useconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+	usleep_A53(useconds);
+#elif defined (__MICROBLAZE__)
+	usleep_MB(useconds);
+#else
+	usleep_A9(useconds);
+#endif
+
+ }
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
new file mode 100644
index 0000000..5bf30cc
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.c
@@ -0,0 +1,162 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.c
+*
+* This file provides the common helper routines for the sleep API's
+*
+* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+* 6.6   srm  04/20/18 Fixed compilation warning in Xil_SleepTTCCommon API
+*
+* 
    
+*****************************************************************************/
+
+/****************************  Include Files  ********************************/
+
+#include "xil_io.h"
+#include "xil_sleeptimer.h"
+#include "xtime_l.h"
+
+/****************************  Constant Definitions  *************************/
+
+
+/* Function definitions are applicable only when TTC3 is present*/
+#if defined (SLEEP_TIMER_BASEADDR)
+/****************************************************************************/
+/**
+*
+* This is a helper function used by sleep/usleep APIs to
+* have delay in sec/usec
+*
+* @param            delay - delay time in seconds/micro seconds
+*
+* @param            frequency - Number of counts per second/micro second
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+void Xil_SleepTTCCommon(u32 delay, u64 frequency)
+{
+	u64 tEnd = 0U;
+	u64 tCur = 0U;
+	XCntrVal TimeHighVal = 0U;
+	XCntrVal TimeLowVal1 = 0U;
+	XCntrVal TimeLowVal2 = 0U;
+
+	TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+			XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+	tEnd = (u64)TimeLowVal1 + ((u64)(delay) * frequency);
+	do
+	{
+		TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+				                  XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+		if (TimeLowVal2 < TimeLowVal1) {
+			TimeHighVal++;
+		}
+		TimeLowVal1 = TimeLowVal2;
+		tCur = (((u64) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
+								(u64)TimeLowVal2;
+	}while (tCur < tEnd);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This API starts the Triple Timer Counter
+*
+* @param            none
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+void XTime_StartTTCTimer()
+{
+	u32 TimerPrescalar;
+	u32 TimerCntrl;
+
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+	u32 LpdRst;
+
+	LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2);
+
+	/* check if the timer is reset */
+	if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+					       XSLEEP_TTC_INSTANCE)) != 0 )) {
+		LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+							XSLEEP_TTC_INSTANCE));
+		Xil_Out32(RST_LPD_IOU2, LpdRst);
+	} else {
+#endif
+		TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+		/* check if Timer is disabled */
+		if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
+		    TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					       XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+		/* check if Timer is configured with proper functionalty for sleep */
+		   if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
+						return;
+		}
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+	}
+#endif
+	/* Disable the timer to configure */
+	TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+	TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+			                 TimerCntrl);
+	/* Disable the prescalar */
+	TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+			XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+	TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
+								TimerPrescalar);
+	/* Enable the Timer */
+	TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+								TimerCntrl);
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
new file mode 100644
index 0000000..4bfac0a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_sleeptimer.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+* 
    +* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+*
+* 
    
+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H		/* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H		/* by using protection macros */
+/****************************  Include Files  ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT  32U
+#define XSleep_ReadCounterVal   Xil_In32
+#define XCntrVal 			    u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT  16U
+#define XSleep_ReadCounterVal   Xil_In16
+#define XCntrVal 			    u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 					    0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 	0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET		0x00000000U
+					     /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET		0x0000000CU
+	                                     /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET	0x00000018U
+					     /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK		0x00000001U
+						   /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK		0x00000001U
+						/**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK		0x00000010U
+						  /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c
new file mode 100644
index 0000000..157ad08
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.c
@@ -0,0 +1,371 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+* 
    
+*
+* @note
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform DCache range related API test such as Xil_DCacheFlushRange
+*           and Xil_DCacheInvalidateRange. This test function writes a constant
+*           value to the Data array, flushes the range, writes a new value, then
+*           invalidates the corresponding range.
+* @param	None
+*
+* @return
+*      - -1 is returned for a failure
+*      - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestDCacheRange(void)
+{
+	s32 Index;
+	s32 Status = 0;
+	u32 CtrlReg;
+	INTPTR Value;
+
+	xil_printf("-- Cache Range Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A00505;
+
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    flush range done\r\n");
+
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A00505) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("	Flush worked\r\n");
+	}
+	else {
+		xil_printf("Error: flush dcache range not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+		#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+		#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0C505;
+
+
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    invalidate dcache range done\r\n");
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0A05;
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A0A05) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+
+	if (!Status) {
+		xil_printf("    Invalidate worked\r\n");
+	}
+	else {
+		xil_printf("Error: Invalidate dcache range not working\r\n");
+	}
+	xil_printf("-- Cache Range Test Complete --\r\n");
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* @brief    Perform DCache all related API test such as Xil_DCacheFlush and
+*           Xil_DCacheInvalidate. This test function writes a constant value
+*           to the Data array, flushes the DCache, writes a new value,
+*           then invalidates the DCache.
+*
+* @return
+*          - 0 is returned for a pass
+*          - -1 is returned for a failure
+*****************************************************************************/
+s32 Xil_TestDCacheAll(void)
+{
+	s32 Index;
+	s32 Status;
+	INTPTR Value;
+	u32 CtrlReg;
+
+	xil_printf("-- Cache All Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50500A0A;
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlush();
+	xil_printf("    flush all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+
+		if (Value != 0x50500A0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Flush all worked\r\n");
+	}
+	else {
+		xil_printf("Error: Flush dcache all not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x505FFA0A;
+
+	Xil_DCacheFlush();
+
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidate();
+
+	xil_printf("    invalidate all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50CFA0A;
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0x50CFA0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Invalidate all worked\r\n");
+	}
+	else {
+			xil_printf("Error: Invalidate dcache all not working\r\n");
+	}
+
+	xil_printf("-- DCache all Test Complete --\n\r");
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* @brief   Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+*     - 0 is returned for a pass
+* @note
+*     The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheRange(void)
+{
+
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+	xil_printf("-- Invalidate icache range done --\r\n");
+
+	return 0;
+}
+
+/*****************************************************************************/
+/**
+* @brief     Perform Xil_ICacheInvalidate() on a few function pointers.
+*
+* @return
+*           - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
+s32 Xil_TestICacheAll(void)
+{
+	Xil_ICacheInvalidate();
+	xil_printf("-- Invalidate icache all done --\r\n");
+	return 0;
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h
new file mode 100644
index 0000000..c35e9a4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testcache.h
@@ -0,0 +1,71 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* @addtogroup common_test_utils
+* 
    Cache test 
    
+* The xil_testcache.h file contains utility functions to test cache.
+*
+* @{
+* 
    +* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
+#define XIL_TESTCACHE_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c
new file mode 100644
index 0000000..e6a3680
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.c
@@ -0,0 +1,299 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.c
+*
+* Contains the memory test utility functions.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param	Data is the 16-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+	return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param	Data is the 32-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+	u16 Lo16;
+	u16 Hi16;
+
+	u16 Swap16Lo;
+	u16 Swap16Hi;
+
+	Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+	Lo16 = (u16)(Data & 0x0000FFFFU);
+
+	Swap16Lo = Swap16(Lo16);
+	Swap16Hi = Swap16(Hi16);
+
+	return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 8-bit wide register IO test where the
+*           register is accessed using Xil_Out8 and Xil_In8, and comparing
+*           the written values by reading them back.
+*
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+	u8 ValueIn;
+	s32 Index;
+	s32 Status = 0;
+
+	for (Index = 0; Index < Length; Index++) {
+		Xil_Out8((INTPTR)Addr, Value);
+
+		ValueIn = Xil_In8((INTPTR)Addr);
+
+		if ((Value != ValueIn) && (Status == 0)) {
+			Status = -1;
+			break;
+		}
+	}
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief   Perform a destructive 16-bit wide register IO test. Each location
+*          is tested by sequentially writing a 16-bit wide register, reading
+*          the register, and comparing value. This function tests three kinds
+*          of register IO functions, normal register IO, little-endian register
+*          IO, and big-endian register IO. When testing little/big-endian IO,
+*          the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
+*          Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
+*          Compare In-Out values. Whether to swap the read-in value before
+*          comparing is controlled by the 5th argument.
+*
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: Type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+	u16 *TempAddr16;
+	u16 ValueIn = 0U;
+	s32 Index;
+	TempAddr16 = Addr;
+	Xil_AssertNonvoid(TempAddr16 != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out16LE((INTPTR)TempAddr16, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out16BE((INTPTR)TempAddr16, Value);
+			break;
+		default:
+			Xil_Out16((INTPTR)TempAddr16, Value);
+			break;
+		}
+
+		ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out16((INTPTR)TempAddr16, Value);
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+			break;
+		default:
+			ValueIn = Xil_In16((INTPTR)TempAddr16);
+			break;
+		}
+
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr16 += sizeof(u16);
+	}
+	return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 32-bit wide register IO test. Each location
+*           is tested by sequentially writing a 32-bit wide regsiter, reading
+*           the register, and comparing value. This function tests three kinds
+*           of register IO functions, normal register IO, little-endian register IO,
+*           and big-endian register IO. When testing little/big-endian IO,
+*           the function perform the following sequence, Xil_Out32LE/
+*           Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
+*           Whether to swap the read-in value *before comparing is controlled
+*           by the 5th argument.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+	u32 *TempAddr;
+	u32 ValueIn = 0U;
+	s32 Index;
+	TempAddr = Addr;
+	Xil_AssertNonvoid(TempAddr != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out32LE((INTPTR)TempAddr, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out32BE((INTPTR)TempAddr, Value);
+			break;
+		default:
+			Xil_Out32((INTPTR)TempAddr, Value);
+			break;
+		}
+
+		ValueIn = Xil_In32((INTPTR)TempAddr);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out32((INTPTR)TempAddr, Value);
+
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In32LE((INTPTR)TempAddr);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In32BE((INTPTR)TempAddr);
+			break;
+		default:
+			ValueIn = Xil_In32((INTPTR)TempAddr);
+			break;
+		}
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr += sizeof(u32);
+	}
+	return 0;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h
new file mode 100644
index 0000000..ad68ead
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testio.h
@@ -0,0 +1,94 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testio.h
+*
+* @addtogroup common_test_utils Test Utilities
+* 
    I/O test 
    
+* The xil_testio.h file contains utility functions to test endian related memory
+* IO functions.
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
+#define XIL_TESTIO_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 	0
+#define XIL_TESTIO_LE		1
+#define XIL_TESTIO_BE		2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c
new file mode 100644
index 0000000..87426d1
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.c
@@ -0,0 +1,868 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 32-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: test type selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*           - 0 is returned for a pass
+*           - 1 is returned for a failure
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u32 Val;
+	u32 FirtVal;
+	u32 WordMem32;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			*(Addr+I) = Val;
+			Val++;
+		}
+
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			WordMem32 = *(Addr+I);
+
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (1U << j);
+
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u32) RotateLeft(Val, 32U);
+			}
+
+			/*
+			 * Restore the reference 'val' to the
+			 * initial value
+			 */
+			Val = 1U << j;
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+
+				WordMem32 = *(Addr+I);
+
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = (u32)RotateLeft(Val, 32U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible
+		 * initial test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = ~(1U << j);
+
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = ~(1U << j);
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+				WordMem32 = *(Addr+I);
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* Read the location */
+			WordMem32 = *(Addr+I);
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+
+			if ((WordMem32 ^ Val) != 0x00000000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u32)0) {
+			Val = 0xDEADBEEFU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+
+			/* read memory location */
+
+			WordMem32 = *(Addr+I);
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 16-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant Pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u16 Val;
+	u16 FirtVal;
+	u16 WordMem16;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * selectthe proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (u16)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u16)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones
+			 * test to test for bad
+			 * data bits
+			 */
+
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u16) (~((INTPTR)(&Addr[I])));
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			Val = (u16) (~((INTPTR) (&Addr[I])));
+			if ((WordMem16 ^ Val) != 0x0000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+		if (Pattern == (u16)0) {
+			Val = 0xDEADU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a destructive 8-bit wide memory test.
+*
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
+*
+* @return
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u8 Val;
+	u8 FirtVal;
+	u8 WordMem8;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * select the proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			Val = (u8)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u8)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test to test
+			 * for bad data bits
+			 */
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			if ((WordMem8 ^ Val) != 0x00U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u8)0) {
+			Val = 0xA5U;
+		}
+		else {
+			Val = Pattern;
+		}
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* @brief   Rotates the provided value to the left one bit position
+*
+* @param    Input is value to be rotated to the left
+* @param    Width is the number of bits in the input data
+*
+* @return
+*           The resulting unsigned long value of the rotate left
+*
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+	u32 Msb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+	/*
+	 * set the Width of the Input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	Msb = LocalInput & MsbMask;
+
+	ReturnVal = LocalInput << 1U;
+
+	if (Msb != 0x00000000U) {
+		ReturnVal = ReturnVal | (u32)0x00000001;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* @brief    Rotates the provided value to the right one bit position
+*
+* @param    Input: value to be rotated to the right
+* @param    Width: number of bits in the input data
+*
+* @return
+*           The resulting u32 value of the rotate right
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+	u32 Lsb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << 1U) - 1U;
+
+	/*
+	 * set the width of the input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	ReturnVal = LocalInput >> 1U;
+
+	Lsb = LocalInput & 0x00000001U;
+
+	if (Lsb != 0x00000000U) {
+		ReturnVal = ReturnVal | MsbMask;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h
new file mode 100644
index 0000000..c204728
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_testmem.h
@@ -0,0 +1,158 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+* @addtogroup common_test_utils
+*
+* 
    Memory test
    
+*
+* The xil_testmem.h file contains utility functions to test memory.
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+* Following list describes the supported memory tests:
+*
+*  - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
+*
+*  - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
+*
+*  - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+*          location 1 = 0x00000001
+*          location 2 = 0x00000002
+*          ...
+* @endcode
+*
+*  - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*@endcode
+*
+*  - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
+*
+*  - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
+*
+* @warning
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
+#define XIL_TESTMEM_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE	1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS     0x00U
+#define XIL_TESTMEM_INCREMENT       0x01U
+#define XIL_TESTMEM_WALKONES        0x02U
+#define XIL_TESTMEM_WALKZEROS       0x03U
+#define XIL_TESTMEM_INVERSEADDR     0x04U
+#define XIL_TESTMEM_FIXEDPATTERN    0x05U
+#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h
new file mode 100644
index 0000000..8143aff
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xil_types.h
@@ -0,0 +1,209 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
+*
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* 
    
+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include 
+#include 
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
+
+/* @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/*
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+/** @}*/
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* @brief    Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* @brief    Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/*
+ * xbasic_types.h does not typedef s* or u64
+ */
+/** @{ */
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+/** @}*/
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include 
+#endif
+
+/** @{ */
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * @brief  Returns 32-63 bits of a number.
+ * @param  n : Number being accessed.
+ * @return Bits 32-63 of number.
+ *
+ * @note    A basic shift-right of a 64- or 32-bit quantity.
+ *          Use this to suppress the "right shift count >= width of type"
+ *          warning when that quantity is 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * @brief  Returns 0-31 bits of a number
+ * @param  n : Number being accessed.
+ * @return Bits 0-31 of number
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h
new file mode 100644
index 0000000..735e26d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc.h
@@ -0,0 +1,172 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xl2cc.h
+*
+* This file contains the address definitions for the PL310 Level-2 Cache
+* Controller.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 1.00a sdm  02/01/10 Initial version
+* 3.10a srt 04/18/13 Implemented ARM Erratas. Please refer to file
+*		      'xil_errata.h' for errata description
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XL2CC_H_
+#define _XL2CC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+/* L2CC Register Offsets */
+#define XPS_L2CC_ID_OFFSET		0x0000U
+#define XPS_L2CC_TYPE_OFFSET		0x0004U
+#define XPS_L2CC_CNTRL_OFFSET		0x0100U
+#define XPS_L2CC_AUX_CNTRL_OFFSET	0x0104U
+#define XPS_L2CC_TAG_RAM_CNTRL_OFFSET	0x0108U
+#define XPS_L2CC_DATA_RAM_CNTRL_OFFSET	0x010CU
+
+#define XPS_L2CC_EVNT_CNTRL_OFFSET	0x0200U
+#define XPS_L2CC_EVNT_CNT1_CTRL_OFFSET	0x0204U
+#define XPS_L2CC_EVNT_CNT0_CTRL_OFFSET	0x0208U
+#define XPS_L2CC_EVNT_CNT1_VAL_OFFSET	0x020CU
+#define XPS_L2CC_EVNT_CNT0_VAL_OFFSET	0x0210U
+
+#define XPS_L2CC_IER_OFFSET		0x0214U		/* Interrupt Mask */
+#define XPS_L2CC_IPR_OFFSET		0x0218U		/* Masked interrupt status */
+#define XPS_L2CC_ISR_OFFSET		0x021CU		/* Raw Interrupt Status */
+#define XPS_L2CC_IAR_OFFSET		0x0220U		/* Interrupt Clear */
+
+#define XPS_L2CC_CACHE_SYNC_OFFSET		0x0730U		/* Cache Sync */
+#define XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET	0x0740U		/* Dummy Register for Cache Sync */
+#define XPS_L2CC_CACHE_INVLD_PA_OFFSET		0x0770U		/* Cache Invalid by PA */
+#define XPS_L2CC_CACHE_INVLD_WAY_OFFSET		0x077CU		/* Cache Invalid by Way */
+#define XPS_L2CC_CACHE_CLEAN_PA_OFFSET		0x07B0U		/* Cache Clean by PA */
+#define XPS_L2CC_CACHE_CLEAN_INDX_OFFSET	0x07B8U		/* Cache Clean by Index */
+#define XPS_L2CC_CACHE_CLEAN_WAY_OFFSET		0x07BCU		/* Cache Clean by Way */
+#define XPS_L2CC_CACHE_INV_CLN_PA_OFFSET	0x07F0U		/* Cache Invalidate and Clean by PA */
+#define XPS_L2CC_CACHE_INV_CLN_INDX_OFFSET	0x07F8U		/* Cache Invalidate and Clean by Index */
+#define XPS_L2CC_CACHE_INV_CLN_WAY_OFFSET	0x07FCU		/* Cache Invalidate and Clean by Way */
+
+#define XPS_L2CC_CACHE_DLCKDWN_0_WAY_OFFSET	0x0900U		/* Cache Data Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_0_WAY_OFFSET	0x0904U		/* Cache Instruction Lockdown 0 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_1_WAY_OFFSET	0x0908U		/* Cache Data Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_1_WAY_OFFSET	0x090CU		/* Cache Instruction Lockdown 1 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_2_WAY_OFFSET	0x0910U		/* Cache Data Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_2_WAY_OFFSET	0x0914U		/* Cache Instruction Lockdown 2 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_3_WAY_OFFSET	0x0918U		/* Cache Data Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_3_WAY_OFFSET	0x091CU		/* Cache Instruction Lockdown 3 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_4_WAY_OFFSET	0x0920U		/* Cache Data Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_4_WAY_OFFSET	0x0924U		/* Cache Instruction Lockdown 4 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_5_WAY_OFFSET	0x0928U		/* Cache Data Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_5_WAY_OFFSET	0x092CU		/* Cache Instruction Lockdown 5 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_6_WAY_OFFSET	0x0930U		/* Cache Data Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_6_WAY_OFFSET	0x0934U		/* Cache Instruction Lockdown 6 by Way */
+#define XPS_L2CC_CACHE_DLCKDWN_7_WAY_OFFSET	0x0938U		/* Cache Data Lockdown 7 by Way */
+#define XPS_L2CC_CACHE_ILCKDWN_7_WAY_OFFSET	0x093CU		/* Cache Instruction Lockdown 7 by Way */
+
+#define XPS_L2CC_CACHE_LCKDWN_LINE_ENABLE_OFFSET 0x0950U		/* Cache Lockdown Line Enable */
+#define XPS_L2CC_CACHE_UUNLOCK_ALL_WAY_OFFSET	0x0954U		/* Cache Unlock All Lines by Way */
+
+#define XPS_L2CC_ADDR_FILTER_START_OFFSET	0x0C00U		/* Start of address filtering */
+#define XPS_L2CC_ADDR_FILTER_END_OFFSET		0x0C04U		/* Start of address filtering */
+
+#define XPS_L2CC_DEBUG_CTRL_OFFSET		0x0F40U		/* Debug Control Register */
+
+/* XPS_L2CC_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_ENABLE_MASK		0x00000001U	/* enables the L2CC */
+
+/* XPS_L2CC_AUX_CNTRL_OFFSET bit masks */
+#define XPS_L2CC_AUX_EBRESPE_MASK	0x40000000U	/* Early BRESP Enable */
+#define XPS_L2CC_AUX_IPFE_MASK		0x20000000U	/* Instruction Prefetch Enable */
+#define XPS_L2CC_AUX_DPFE_MASK		0x10000000U	/* Data Prefetch Enable */
+#define XPS_L2CC_AUX_NSIC_MASK		0x08000000U	/* Non-secure interrupt access control */
+#define XPS_L2CC_AUX_NSLE_MASK		0x04000000U	/* Non-secure lockdown enable */
+#define XPS_L2CC_AUX_CRP_MASK		0x02000000U	/* Cache replacement policy */
+#define XPS_L2CC_AUX_FWE_MASK		0x01800000U	/* Force write allocate */
+#define XPS_L2CC_AUX_SAOE_MASK		0x00400000U	/* Shared attribute override enable */
+#define XPS_L2CC_AUX_PE_MASK		0x00200000U	/* Parity enable */
+#define XPS_L2CC_AUX_EMBE_MASK		0x00100000U	/* Event monitor bus enable */
+#define XPS_L2CC_AUX_WAY_SIZE_MASK	0x000E0000U	/* Way-size */
+#define XPS_L2CC_AUX_ASSOC_MASK		0x00010000U	/* Associativity */
+#define XPS_L2CC_AUX_SAIE_MASK		0x00002000U	/* Shared attribute invalidate enable */
+#define XPS_L2CC_AUX_EXCL_CACHE_MASK	0x00001000U	/* Exclusive cache configuration */
+#define XPS_L2CC_AUX_SBDLE_MASK		0x00000800U	/* Store buffer device limitation Enable */
+#define XPS_L2CC_AUX_HPSODRE_MASK	0x00000400U	/* High Priority for SO and Dev Reads Enable */
+#define XPS_L2CC_AUX_FLZE_MASK		0x00000001U	/* Full line of zero enable */
+
+#define XPS_L2CC_AUX_REG_DEFAULT_MASK	0x72360000U	/* Enable all prefetching, */
+                                                    /* Cache replacement policy, Parity enable, */
+                                                    /* Event monitor bus enable and Way Size (64 KB) */
+#define XPS_L2CC_AUX_REG_ZERO_MASK	0xFFF1FFFFU	/* */
+
+#define XPS_L2CC_TAG_RAM_DEFAULT_MASK	0x00000111U	/* latency for TAG RAM */
+#define XPS_L2CC_DATA_RAM_DEFAULT_MASK	0x00000121U	/* latency for DATA RAM */
+
+/* Interrupt bit masks */
+#define XPS_L2CC_IXR_DECERR_MASK	0x00000100U	/* DECERR from L3 */
+#define XPS_L2CC_IXR_SLVERR_MASK	0x00000080U	/* SLVERR from L3 */
+#define XPS_L2CC_IXR_ERRRD_MASK		0x00000040U	/* Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_ERRRT_MASK		0x00000020U	/* Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ERRWD_MASK		0x00000010U	/* Error on L2 data RAM (Write) */
+#define XPS_L2CC_IXR_ERRWT_MASK		0x00000008U	/* Error on L2 tag RAM (Write) */
+#define XPS_L2CC_IXR_PARRD_MASK		0x00000004U	/* Parity Error on L2 data RAM (Read) */
+#define XPS_L2CC_IXR_PARRT_MASK		0x00000002U	/* Parity Error on L2 tag RAM (Read) */
+#define XPS_L2CC_IXR_ECNTR_MASK		0x00000001U	/* Event Counter1/0 Overflow Increment */
+
+/* Address filtering mask and enable bit */
+#define XPS_L2CC_ADDR_FILTER_VALID_MASK	0xFFF00000U	/* Address filtering valid bits*/
+#define XPS_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001U	/* Address filtering enable bit*/
+
+/* Debug control bits */
+#define XPS_L2CC_DEBUG_SPIDEN_MASK	0x00000004U	/* Debug SPIDEN bit */
+#define XPS_L2CC_DEBUG_DWB_MASK		0x00000002U	/* Debug DWB bit, forces write through */
+#define XPS_L2CC_DEBUG_DCL_MASK		0x00000002U	/* Debug DCL bit, disables cache line fill */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c
new file mode 100644
index 0000000..d6b88cb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.c
+*
+* This file contains APIs for configuring and controlling the event counters
+* in PL310 L2 cache controller. For more information about the event counters,
+* see xl2cc_counter.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include 
+#include "xparameters_ps.h"
+#include "xl2cc_counter.h"
+#include "xl2cc.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XL2cc_EventCtrReset(void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief	This function initializes the event counters in L2 Cache controller
+*			with a set of event codes specified by the user.
+*
+* @param	Event0: Event code for counter 0.
+* @param	Event1: Event code for counter 1.
+*
+* @return	None.
+*
+* @note		The definitions for event codes XL2CC_* can be found in
+*			xl2cc_counter.h.
+*
+*****************************************************************************/
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
+{
+
+	/* Write event code into cnt1 cfg reg */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_CTRL_OFFSET)) = (((u32)Event1) << 2);
+
+	/* Write event code into cnt0 cfg reg */
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_CTRL_OFFSET)) = (((u32)Event0) << 2);
+
+	/* Reset counters */
+	XL2cc_EventCtrReset();
+}
+
+
+/****************************************************************************/
+/**
+*
+* @brief	This function starts the event counters in L2 Cache controller.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStart(void)
+{
+	u32 *LocalPtr;
+	LocalPtr = (u32 *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET);
+	XL2cc_EventCtrReset();
+
+	/* Enable counter */
+	/* *((volatile u32*)((void *)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET))) = 1 */
+	*LocalPtr = (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the event counters in L2 Cache controller,
+*			saves the counter values and resets the counters.
+*
+* @param	EveCtr0: Output parameter which is used to return the value
+*			in event counter 0.
+*			EveCtr1: Output parameter which is used to return the value
+*			in event counter 1.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
+{
+	/* Disable counter */
+	*((volatile u32*) (XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0U;
+
+	/* Save counter values */
+	*EveCtr1 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT1_VAL_OFFSET));
+	*EveCtr0 = *((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNT0_VAL_OFFSET));
+
+	XL2cc_EventCtrReset();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function resets the event counters in L2 Cache controller.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XL2cc_EventCtrReset(void)
+{
+	*((volatile u32*)(XPS_L2CC_BASEADDR + XPS_L2CC_EVNT_CNTRL_OFFSET)) = 0x6U;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h
new file mode 100644
index 0000000..8d0a61f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xl2cc_counter.h
@@ -0,0 +1,113 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xl2cc_counter.h
+*
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
+*
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+*		      inside the APIs
+* 
    
+*
+******************************************************************************/
+
+#ifndef L2CCCOUNTER_H /* prevent circular inclusions */
+#define L2CCCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants define the event codes for the event counters.
+ */
+#define XL2CC_CO		0x1
+#define XL2CC_DRHIT		0x2
+#define XL2CC_DRREQ		0x3
+#define XL2CC_DWHIT		0x4
+#define XL2CC_DWREQ		0x5
+#define XL2CC_DWTREQ		0x6
+#define XL2CC_IRHIT		0x7
+#define XL2CC_IRREQ		0x8
+#define XL2CC_WA		0x9
+#define XL2CC_IPFALLOC		0xa
+#define XL2CC_EPFHIT		0xb
+#define XL2CC_EPFALLOC		0xc
+#define XL2CC_SRRCVD		0xd
+#define XL2CC_SRCONF		0xe
+#define XL2CC_EPFRCVD		0xf
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+void XL2cc_EventCtrInit(s32 Event0, s32 Event1);
+void XL2cc_EventCtrStart(void);
+void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
new file mode 100644
index 0000000..0fa7771
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xparameters_ps.h
@@ -0,0 +1,338 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex A9 core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 1.00a ecm/sdm 02/01/10 Initial version
+* 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
+*                        driver tcl
+* 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6   srm     10/18/17 Added ARMA9 macro to identify CortexA9
+*
+* 
    
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef _XPARAMETERS_PS_H_
+#define _XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************  Include Files  *******************************/
+
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB0_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+
+
+#define XPAR_XQSPIPS_0_LINEAR_BASEADDR	XPS_QSPI_LINEAR_BASEADDR
+#define XPAR_XPARPORTPS_CTRL_BASEADDR	XPS_PARPORT_CRTL_BASEADDR
+
+
+
+/* Canonical definitions for DMAC */
+
+
+/* Canonical definitions for WDT */
+
+/* Canonical definitions for SLCR */
+#define XPAR_XSLCR_NUM_INSTANCES	1U
+#define XPAR_XSLCR_0_DEVICE_ID		0U
+#define XPAR_XSLCR_0_BASEADDR		XPS_SYS_CTRL_BASEADDR
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000100U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+/* Canonical definitions for Global Timer */
+#define XPAR_GLOBAL_TMR_NUM_INSTANCES	1U
+#define XPAR_GLOBAL_TMR_DEVICE_ID	0U
+#define XPAR_GLOBAL_TMR_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00000200U)
+#define XPAR_GLOBAL_TMR_INTR		XPS_GLOBAL_TMR_INT_ID
+
+
+/* Xilinx Parallel Flash Library (XilFlash) User Settings */
+#define XPAR_AXI_EMC
+
+
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_PERIPHERAL_BASEADDR		0xE0000000U
+#define XPS_UART0_BASEADDR		0xE0000000U
+#define XPS_UART1_BASEADDR		0xE0001000U
+#define XPS_USB0_BASEADDR		0xE0002000U
+#define XPS_USB1_BASEADDR		0xE0003000U
+#define XPS_I2C0_BASEADDR		0xE0004000U
+#define XPS_I2C1_BASEADDR		0xE0005000U
+#define XPS_SPI0_BASEADDR		0xE0006000U
+#define XPS_SPI1_BASEADDR		0xE0007000U
+#define XPS_CAN0_BASEADDR		0xE0008000U
+#define XPS_CAN1_BASEADDR		0xE0009000U
+#define XPS_GPIO_BASEADDR		0xE000A000U
+#define XPS_GEM0_BASEADDR		0xE000B000U
+#define XPS_GEM1_BASEADDR		0xE000C000U
+#define XPS_QSPI_BASEADDR		0xE000D000U
+#define XPS_PARPORT_CRTL_BASEADDR	0xE000E000U
+#define XPS_SDIO0_BASEADDR		0xE0100000U
+#define XPS_SDIO1_BASEADDR		0xE0101000U
+#define XPS_IOU_BUS_CFG_BASEADDR	0xE0200000U
+#define XPS_NAND_BASEADDR		0xE1000000U
+#define XPS_PARPORT0_BASEADDR		0xE2000000U
+#define XPS_PARPORT1_BASEADDR		0xE4000000U
+#define XPS_QSPI_LINEAR_BASEADDR	0xFC000000U
+#define XPS_SYS_CTRL_BASEADDR		0xF8000000U	/* AKA SLCR */
+#define XPS_TTC0_BASEADDR		0xF8001000U
+#define XPS_TTC1_BASEADDR		0xF8002000U
+#define XPS_DMAC0_SEC_BASEADDR		0xF8003000U
+#define XPS_DMAC0_NON_SEC_BASEADDR	0xF8004000U
+#define XPS_WDT_BASEADDR		0xF8005000U
+#define XPS_DDR_CTRL_BASEADDR		0xF8006000U
+#define XPS_DEV_CFG_APB_BASEADDR	0xF8007000U
+#define XPS_AFI0_BASEADDR		0xF8008000U
+#define XPS_AFI1_BASEADDR		0xF8009000U
+#define XPS_AFI2_BASEADDR		0xF800A000U
+#define XPS_AFI3_BASEADDR		0xF800B000U
+#define XPS_OCM_BASEADDR		0xF800C000U
+#define XPS_EFUSE_BASEADDR		0xF800D000U
+#define XPS_CORESIGHT_BASEADDR		0xF8800000U
+#define XPS_TOP_BUS_CFG_BASEADDR	0xF8900000U
+#define XPS_SCU_PERIPH_BASE		0xF8F00000U
+#define XPS_L2CC_BASEADDR		0xF8F02000U
+#define XPS_SAM_RAM_BASEADDR		0xFFFC0000U
+#define XPS_FPGA_AXI_S0_BASEADDR	0x40000000U
+#define XPS_FPGA_AXI_S1_BASEADDR	0x80000000U
+#define XPS_IOU_S_SWITCH_BASEADDR	0xE0000000U
+#define XPS_PERIPH_APB_BASEADDR		0xF8000000U
+
+/* Shared Peripheral Interrupts (SPI) */
+#define XPS_CORE_PARITY0_INT_ID		32U
+#define XPS_CORE_PARITY1_INT_ID		33U
+#define XPS_L2CC_INT_ID			34U
+#define XPS_OCMINTR_INT_ID		35U
+#define XPS_ECC_INT_ID			36U
+#define XPS_PMU0_INT_ID			37U
+#define XPS_PMU1_INT_ID			38U
+#define XPS_SYSMON_INT_ID		39U
+#define XPS_DVC_INT_ID			40U
+#define XPS_WDT_INT_ID			41U
+#define XPS_TTC0_0_INT_ID		42U
+#define XPS_TTC0_1_INT_ID		43U
+#define XPS_TTC0_2_INT_ID 		44U
+#define XPS_DMA0_ABORT_INT_ID		45U
+#define XPS_DMA0_INT_ID			46U
+#define XPS_DMA1_INT_ID			47U
+#define XPS_DMA2_INT_ID			48U
+#define XPS_DMA3_INT_ID			49U
+#define XPS_SMC_INT_ID			50U
+#define XPS_QSPI_INT_ID			51U
+#define XPS_GPIO_INT_ID			52U
+#define XPS_USB0_INT_ID			53U
+#define XPS_GEM0_INT_ID			54U
+#define XPS_GEM0_WAKE_INT_ID		55U
+#define XPS_SDIO0_INT_ID		56U
+#define XPS_I2C0_INT_ID			57U
+#define XPS_SPI0_INT_ID			58U
+#define XPS_UART0_INT_ID		59U
+#define XPS_CAN0_INT_ID			60U
+#define XPS_FPGA0_INT_ID		61U
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_TTC1_0_INT_ID		69U
+#define XPS_TTC1_1_INT_ID		70U
+#define XPS_TTC1_2_INT_ID		71U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_USB1_INT_ID			76U
+#define XPS_GEM1_INT_ID			77U
+#define XPS_GEM1_WAKE_INT_ID		78U
+#define XPS_SDIO1_INT_ID		79U
+#define XPS_I2C1_INT_ID			80U
+#define XPS_SPI1_INT_ID			81U
+#define XPS_UART1_INT_ID		82U
+#define XPS_CAN1_INT_ID			83U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Private Peripheral Interrupts (PPI) */
+#define XPS_GLOBAL_TMR_INT_ID		27U	/* SCU Global Timer interrupt */
+#define XPS_FIQ_INT_ID			28U	/* FIQ from FPGA fabric */
+#define XPS_SCU_TMR_INT_ID		29U	/* SCU Private Timer interrupt */
+#define XPS_SCU_WDT_INT_ID		30U	/* SCU Private WDT interrupt */
+#define XPS_IRQ_INT_ID			31U	/* IRQ from FPGA fabric */
+
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+#define XPAR_PS7_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PS7_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PS7_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PS7_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PS7_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PS7_TTC_5_INTR         XPS_TTC1_2_INT_ID
+
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXA9_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUTIMER_DEVICE_ID		0U
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
new file mode 100644
index 0000000..2c08e5f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.c
@@ -0,0 +1,161 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
+*					  mode
+* 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4   ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                     function for PMUFW.
+*       ms   06/13/17 Added PSU_PMU macro to provide support of
+*                     XGetPlatform_Info function for PMUFW.
+*       mus  08/17/17 Add EL1 NS mode support for
+*                     XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+*                     APIs.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_io.h"
+#include "xplatform_info.h"
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about platform
+*
+* @param    None.
+*
+* @return   The information about platform defined in xplatform_info.h
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+	return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+	return XPLAT_MICROBLAZE;
+#else
+	return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about zynq ultrascale MP platform
+*
+* @param    None.
+*
+* @return   The information about zynq ultrascale MP platform defined in
+*			xplatform_info.h
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+#if EL1_NONSECURE
+	XSmc_OutVar reg;
+    /*
+	 * This SMC call will return,
+     *  idcode - upper 32 bits of reg.Arg0
+     *  version - lower 32 bits of reg.Arg1
+	 */
+	reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+	return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
+	u32 reg;
+	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+	return reg;
+#endif
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief    This API is used to provide information about PS Silicon version
+*
+* @param    None.
+*
+* @return   The information about PS Silicon version.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info()
+{
+#if EL1_NONSECURE
+        /*
+         * This SMC call will return,
+         *  idcode - upper 32 bits of reg.Arg0
+         *  version - lower 32 bits of reg.Arg1
+         */
+        XSmc_OutVar reg;
+        reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+        return (u32)(reg.Arg1 &  XPS_VERSION_INFO_MASK);
+#else
+	u32 reg;
+	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
+			& XPS_VERSION_INFO_MASK);
+	return reg;
+#endif
+}
+#endif
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
new file mode 100644
index 0000000..0582222
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xplatform_info.h
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date    Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4    ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                      function for PMUFW.
+* 
    
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
+#define XPLATFORM_INFO_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define	XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c
new file mode 100644
index 0000000..d0765b6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.c
@@ -0,0 +1,297 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-A9
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 4.2	pkp	 07/21/14 Corrected reset value of event counter in function
+*					  Xpm_ResetEventCounters to fix CR#796275
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+	/* Disable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function enables the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+	/* Enable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function resets the Cortex A9 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+	u32 Reg;
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#elif defined (__ICCARM__)
+	mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+#else
+	{ register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+	  Reg = C15Reg; }
+#endif
+	Reg |= (1U << 1U); /* reset event counters */
+	mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+
+}
+
+/****************************************************************************/
+/**
+* @brief	This function configures the Cortex A9 event counters controller,
+*			with the event codes, in a configuration selected by the user and
+*			enables the counters.
+*
+* @param	PmcrCfg: Configuration value based on which the event counters
+*			are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
+*			be utilized for setting configuration.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(s32 PmcrCfg)
+{
+	u32 Counter;
+	static PmcrEventCfg32 PmcrEvents[] = {
+	{
+		XPM_EVENT_SOFTINCR,
+		XPM_EVENT_INSRFETCH_CACHEREFILL,
+		XPM_EVENT_INSTRFECT_TLBREFILL,
+		XPM_EVENT_DATA_CACHEREFILL,
+		XPM_EVENT_DATA_CACHEACCESS,
+		XPM_EVENT_DATA_TLBREFILL
+	},
+	{
+		XPM_EVENT_DATA_READS,
+		XPM_EVENT_DATA_WRITE,
+		XPM_EVENT_EXCEPTION,
+		XPM_EVENT_EXCEPRETURN,
+		XPM_EVENT_CHANGECONTEXT,
+		XPM_EVENT_SW_CHANGEPC
+	},
+	{
+		XPM_EVENT_IMMEDBRANCH,
+		XPM_EVENT_UNALIGNEDACCESS,
+		XPM_EVENT_BRANCHMISS,
+		XPM_EVENT_CLOCKCYCLES,
+		XPM_EVENT_BRANCHPREDICT,
+		XPM_EVENT_JAVABYTECODE
+	},
+	{
+		XPM_EVENT_SWJAVABYTECODE,
+		XPM_EVENT_JAVABACKBRANCH,
+		XPM_EVENT_COHERLINEMISS,
+		XPM_EVENT_COHERLINEHIT,
+		XPM_EVENT_INSTRSTALL,
+		XPM_EVENT_DATASTALL
+	},
+	{
+		XPM_EVENT_MAINTLBSTALL,
+		XPM_EVENT_STREXPASS,
+		XPM_EVENT_STREXFAIL,
+		XPM_EVENT_DATAEVICT,
+		XPM_EVENT_NODISPATCH,
+		XPM_EVENT_ISSUEEMPTY
+	},
+	{
+		XPM_EVENT_INSTRRENAME,
+		XPM_EVENT_PREDICTFUNCRET,
+		XPM_EVENT_MAINEXEC,
+		XPM_EVENT_SECEXEC,
+		XPM_EVENT_LDRSTR,
+		XPM_EVENT_FLOATRENAME
+	},
+	{
+		XPM_EVENT_NEONRENAME,
+		XPM_EVENT_PLDSTALL,
+		XPM_EVENT_WRITESTALL,
+		XPM_EVENT_INSTRTLBSTALL,
+		XPM_EVENT_DATATLBSTALL,
+		XPM_EVENT_INSTR_uTLBSTALL
+	},
+	{
+		XPM_EVENT_DATA_uTLBSTALL,
+		XPM_EVENT_DMB_STALL,
+		XPM_EVENT_INT_CLKEN,
+		XPM_EVENT_DE_CLKEN,
+		XPM_EVENT_INSTRISB,
+		XPM_EVENT_INSTRDSB
+	},
+	{
+		XPM_EVENT_INSTRDMB,
+		XPM_EVENT_EXTINT,
+		XPM_EVENT_PLE_LRC,
+		XPM_EVENT_PLE_LRS,
+		XPM_EVENT_PLE_FLUSH,
+		XPM_EVENT_PLE_CMPL
+	},
+	{
+		XPM_EVENT_PLE_OVFL,
+		XPM_EVENT_PLE_PROG,
+		XPM_EVENT_PLE_LRC,
+		XPM_EVENT_PLE_LRS,
+		XPM_EVENT_PLE_FLUSH,
+		XPM_EVENT_PLE_CMPL
+	},
+	{
+		XPM_EVENT_DATASTALL,
+		XPM_EVENT_INSRFETCH_CACHEREFILL,
+		XPM_EVENT_INSTRFECT_TLBREFILL,
+		XPM_EVENT_DATA_CACHEREFILL,
+		XPM_EVENT_DATA_CACHEACCESS,
+		XPM_EVENT_DATA_TLBREFILL
+	},
+	};
+	const u32 *ptr = PmcrEvents[PmcrCfg];
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		/* Selecet event counter */
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+		/* Set the event */
+		mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
+	}
+
+	Xpm_ResetEventCounters();
+	Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* @brief	This function disables the event counters and returns the counter
+*			values.
+*
+* @param	PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
+*			It is an output parameter which is used to return the PM
+*			counter values.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+	u32 Counter;
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+		PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#elif defined (__ICCARM__)
+		mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]);
+#else
+		{ register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+		  PmCtrValue[Counter] = Cp15Reg; }
+#endif
+	}
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h
new file mode 100644
index 0000000..45f0919
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpm_counter.h
@@ -0,0 +1,575 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
+*
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
+*
+* @note
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* @{
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sdm  07/11/11 First release
+* 
    
+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include 
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-A9 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-A9 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which also miss in all the other
+ * Cortex-A9 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-A9 processor which hit in another Cortex-A9
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-A9 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ *    - b00 no instructions renamed
+ *    - b01 one instruction renamed
+ *    - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-A9 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config		PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
+ *			  XPM_EVENT_DATA_WRITE,
+ *			  XPM_EVENT_EXCEPTION,
+ *			  XPM_EVENT_EXCEPRETURN,
+ *			  XPM_EVENT_CHANGECONTEXT,
+ *			  XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
+ *			  XPM_EVENT_UNALIGNEDACCESS,
+ *			  XPM_EVENT_BRANCHMISS,
+ *			  XPM_EVENT_CLOCKCYCLES,
+ *			  XPM_EVENT_BRANCHPREDICT,
+ *			  XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
+ *			  XPM_EVENT_JAVABACKBRANCH,
+ *			  XPM_EVENT_COHERLINEMISS,
+ *			  XPM_EVENT_COHERLINEHIT,
+ *			  XPM_EVENT_INSTRSTALL,
+ *			  XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
+ *			  XPM_EVENT_STREXPASS,
+ *			  XPM_EVENT_STREXFAIL,
+ *			  XPM_EVENT_DATAEVICT,
+ *			  XPM_EVENT_NODISPATCH,
+ *			  XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
+ *			  XPM_EVENT_PREDICTFUNCRET,
+ *			  XPM_EVENT_MAINEXEC,
+ *			  XPM_EVENT_SECEXEC,
+ *			  XPM_EVENT_LDRSTR,
+ *			  XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
+ *			  XPM_EVENT_PLDSTALL,
+ *			  XPM_EVENT_WRITESTALL,
+ *			  XPM_EVENT_INSTRTLBSTALL,
+ *			  XPM_EVENT_DATATLBSTALL,
+ *			  XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
+ *			  XPM_EVENT_DMB_STALL,
+ *			  XPM_EVENT_INT_CLKEN,
+ *			  XPM_EVENT_DE_CLKEN,
+ *			  XPM_EVENT_INSTRISB,
+ *			  XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
+ *			  XPM_EVENT_EXTINT,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
+ *			  XPM_EVENT_PLE_PROG,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1	0
+#define XPM_CNTRCFG2	1
+#define XPM_CNTRCFG3	2
+#define XPM_CNTRCFG4	3
+#define XPM_CNTRCFG5	4
+#define XPM_CNTRCFG6	5
+#define XPM_CNTRCFG7	6
+#define XPM_CNTRCFG8	7
+#define XPM_CNTRCFG9	8
+#define XPM_CNTRCFG10	9
+#define XPM_CNTRCFG11	10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h
new file mode 100644
index 0000000..4ad9e5d
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm.h
@@ -0,0 +1,77 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a ecm  10/18/09 First release
+* 3.04a sdm  01/02/12 Remove redundant dsb in mcr instruction.
+* 
    
+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H
+#define XPSEUDO_ASM_H
+
+#include "xreg_cortexa9.h"
+#ifdef __GNUC__
+ #include "xpseudo_asm_gcc.h"
+#elif defined (__ICCARM__)
+ #include "xpseudo_asm_iccarm.h"
+#else
+ #include "xpseudo_asm_rvct.h"
+#endif
+
+#endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
new file mode 100644
index 0000000..37971bc
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xpseudo_asm_gcc.h
@@ -0,0 +1,256 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
+* 
    
+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+#if defined (__aarch64__)
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval = 0U; \
+			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
+			  rval;\
+			 })
+
+#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v))
+
+#define cpsiei()	//__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	//__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	//__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	//__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	/*__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)*/
+
+#define mfgpr(rn)	/*({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })*/
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb sy")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__("dsb sy")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__("dmb sy")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u64 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define mfelrel3() ({u64 rval = 0U; \
+                   asm volatile("mrs %0,  ELR_EL3" : "=r" (rval));\
+                  rval;\
+                 })
+
+#define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v))
+
+#else
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval = 0U; \
+			  __asm__ __volatile__(\
+			    "mrs	%0, cpsr\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+#define mtcpsr(v)	__asm__ __volatile__(\
+			  "msr	cpsr,%0\n"\
+			  : : "r" (v)\
+			)
+
+#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)
+
+#define mfgpr(rn)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#endif
+
+#define ldrb(adr)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+
+#if defined (__aarch64__)
+#define mtcpdc(reg,val)	__asm__ __volatile__("dc " #reg ",%0"  : : "r" (val))
+#define mtcpic(reg,val)	__asm__ __volatile__("ic " #reg ",%0"  : : "r" (val))
+
+#define mtcpicall(reg)	__asm__ __volatile__("ic " #reg)
+#define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
+#define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
+/* CP15 operations */
+#define mfcp(reg)	({u64 rval = 0U;\
+			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
+			rval;\
+			})
+
+#define mtcp(reg,val)	__asm__ __volatile__("msr " #reg ",%0"  : : "r" (val))
+
+#else
+/* CP15 operations */
+#define mtcp(rn, v)	__asm__ __volatile__(\
+			 "mcr " rn "\n"\
+			 : : "r" (v)\
+			);
+
+#define mfcp(rn)	({u32 rval = 0U; \
+			 __asm__ __volatile__(\
+			   "mrc " rn "\n"\
+			   : "=r" (rval)\
+			 );\
+			 rval;\
+			 })
+#endif
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h
new file mode 100644
index 0000000..dc9a4eb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xreg_cortexa9.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexa9.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, ARMCC compiler.
+*
+* All of the ARM Cortex A9 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 1.00a ecm/sdm  10/20/09 First release
+* 
    
+*
+******************************************************************************/
+#ifndef XREG_CORTEXA9_H
+#define XREG_CORTEXA9_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0				r0
+#define XREG_GPR1				r1
+#define XREG_GPR2				r2
+#define XREG_GPR3				r3
+#define XREG_GPR4				r4
+#define XREG_GPR5				r5
+#define XREG_GPR6				r6
+#define XREG_GPR7				r7
+#define XREG_GPR8				r8
+#define XREG_GPR9				r9
+#define XREG_GPR10				r10
+#define XREG_GPR11				r11
+#define XREG_GPR12				r12
+#define XREG_GPR13				r13
+#define XREG_GPR14				r14
+#define XREG_GPR15				r15
+#define XREG_CPSR				cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0				0
+#define XREG_CP1				1
+#define XREG_CP2				2
+#define XREG_CP3				3
+#define XREG_CP4				4
+#define XREG_CP5				5
+#define XREG_CP6				6
+#define XREG_CP7				7
+#define XREG_CP8				8
+#define XREG_CP9				9
+#define XREG_CP10				10
+#define XREG_CP11				11
+#define XREG_CP12				12
+#define XREG_CP13				13
+#define XREG_CP14				14
+#define XREG_CP15				15
+
+/* Coprocessor control register defines */
+#define XREG_CR0				cr0
+#define XREG_CR1				cr1
+#define XREG_CR2				cr2
+#define XREG_CR3				cr3
+#define XREG_CR4				cr4
+#define XREG_CR5				cr5
+#define XREG_CR6				cr6
+#define XREG_CR7				cr7
+#define XREG_CR8				cr8
+#define XREG_CR9				cr9
+#define XREG_CR10				cr10
+#define XREG_CR11				cr11
+#define XREG_CR12				cr12
+#define XREG_CR13				cr13
+#define XREG_CR14				cr14
+#define XREG_CR15				cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE			0x20
+#define XREG_CPSR_MODE_BITS			0x1F
+#define XREG_CPSR_SYSTEM_MODE			0x1F
+#define XREG_CPSR_UNDEFINED_MODE		0x1B
+#define XREG_CPSR_DATA_ABORT_MODE		0x17
+#define XREG_CPSR_SVC_MODE			0x13
+#define XREG_CPSR_IRQ_MODE			0x12
+#define XREG_CPSR_FIQ_MODE			0x11
+#define XREG_CPSR_USER_MODE			0x10
+
+#define XREG_CPSR_IRQ_ENABLE			0x80
+#define XREG_CPSR_FIQ_ENABLE			0x40
+
+#define XREG_CPSR_N_BIT				0x80000000
+#define XREG_CPSR_Z_BIT				0x40000000
+#define XREG_CPSR_C_BIT				0x20000000
+#define XREG_CPSR_V_BIT				0x10000000
+
+
+/* CP15 defines */
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
+#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
+#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
+#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
+#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
+#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
+#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
+#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
+#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
+#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
+
+#define XREG_CP15_SECURE_CONFIG			"p15, 0, %0,  c1,  c1, 0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"p15, 0, %0,  c1,  c1, 1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"p15, 0, %0,  c1,  c1, 2"
+#define XREG_CP15_VIRTUAL_CONTROL		"p15, 0, %0,  c1,  c1, 3"
+
+#else /* RVCT */
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"cp15:0:c0:c0:0"
+#define XREG_CP15_CACHE_TYPE			"cp15:0:c0:c0:1"
+#define XREG_CP15_TCM_TYPE			"cp15:0:c0:c0:2"
+#define XREG_CP15_TLB_TYPE			"cp15:0:c0:c0:3"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"cp15:0:c0:c0:5"
+
+#define XREG_CP15_PROC_FEATURE_0		"cp15:0:c0:c1:0"
+#define XREG_CP15_PROC_FEATURE_1		"cp15:0:c0:c1:1"
+#define XREG_CP15_DEBUG_FEATURE_0		"cp15:0:c0:c1:2"
+#define XREG_CP15_MEMORY_FEATURE_0		"cp15:0:c0:c1:4"
+#define XREG_CP15_MEMORY_FEATURE_1		"cp15:0:c0:c1:5"
+#define XREG_CP15_MEMORY_FEATURE_2		"cp15:0:c0:c1:6"
+#define XREG_CP15_MEMORY_FEATURE_3		"cp15:0:c0:c1:7"
+
+#define XREG_CP15_INST_FEATURE_0		"cp15:0:c0:c2:0"
+#define XREG_CP15_INST_FEATURE_1		"cp15:0:c0:c2:1"
+#define XREG_CP15_INST_FEATURE_2		"cp15:0:c0:c2:2"
+#define XREG_CP15_INST_FEATURE_3		"cp15:0:c0:c2:3"
+#define XREG_CP15_INST_FEATURE_4		"cp15:0:c0:c2:4"
+
+#define XREG_CP15_CACHE_SIZE_ID			"cp15:1:c0:c0:0"
+#define XREG_CP15_CACHE_LEVEL_ID		"cp15:1:c0:c0:1"
+#define XREG_CP15_AUXILARY_ID			"cp15:1:c0:c0:7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"cp15:2:c0:c0:0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"cp15:0:c1:c0:0"
+#define XREG_CP15_AUX_CONTROL			"cp15:0:c1:c0:1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"cp15:0:c1:c0:2"
+
+#define XREG_CP15_SECURE_CONFIG			"cp15:0:c1:c1:0"
+#define XREG_CP15_SECURE_DEBUG_ENABLE		"cp15:0:c1:c1:1"
+#define XREG_CP15_NS_ACCESS_CONTROL		"cp15:0:c1:c1:2"
+#define XREG_CP15_VIRTUAL_CONTROL		"cp15:0:c1:c1:3"
+#endif
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
+#define XREG_CP15_CONTROL_V_BIT			0x00002000U
+#define XREG_CP15_CONTROL_I_BIT			0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
+#define XREG_CP15_CONTROL_B_BIT			0x00000080U
+#define XREG_CP15_CONTROL_C_BIT			0x00000004U
+#define XREG_CP15_CONTROL_A_BIT			0x00000002U
+#define XREG_CP15_CONTROL_M_BIT			0x00000001U
+
+#if defined (__GNUC__) || defined (__ICCARM__)
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"p15, 0, %0,  c2,  c0, 0"
+#define XREG_CP15_TTBR1				"p15, 0, %0,  c2,  c0, 1"
+#define XREG_CP15_TTB_CONTROL			"p15, 0, %0,  c2,  c0, 2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"p15, 0, %0,  c3,  c0, 0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"p15, 0, %0,  c7,  c1, 0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"p15, 0, %0,  c7,  c1, 6"
+
+#define XREG_CP15_PHYS_ADDR			"p15, 0, %0,  c7,  c4, 0"
+
+#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"p15, 0, %0,  c7,  c8, 0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"p15, 0, %0,  c7,  c8, 1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"p15, 0, %0,  c7,  c8, 2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"p15, 0, %0,  c7,  c8, 3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"p15, 0, %0,  c7,  c8, 4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"p15, 0, %0,  c7,  c8, 5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"p15, 0, %0,  c7,  c8, 6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"p15, 0, %0,  c7,  c8, 7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
+
+#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"p15, 0, %0,  c8,  c3, 0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"p15, 0, %0,  c8,  c3, 1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"p15, 0, %0,  c8,  c3, 2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"p15, 0, %0,  c8,  c3, 3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"p15, 0, %0,  c8,  c5, 0"
+#define XREG_CP15_INVAL_ITLB_MVA		"p15, 0, %0,  c8,  c5, 1"
+#define XREG_CP15_INVAL_ITLB_ASID		"p15, 0, %0,  c8,  c5, 2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"p15, 0, %0,  c8,  c6, 0"
+#define XREG_CP15_INVAL_DTLB_MVA		"p15, 0, %0,  c8,  c6, 1"
+#define XREG_CP15_INVAL_DTLB_ASID		"p15, 0, %0,  c8,  c6, 2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"p15, 0, %0,  c8,  c7, 0"
+#define XREG_CP15_INVAL_UTLB_MVA		"p15, 0, %0,  c8,  c7, 1"
+#define XREG_CP15_INVAL_UTLB_ASID		"p15, 0, %0,  c8,  c7, 2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"p15, 0, %0,  c8,  c7, 3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
+#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"p15, 0, %0, c10,  c0, 0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"p15, 0, %0, c10,  c2, 0"
+#define XREG_CP15_NORM_MEM_REMAP		"p15, 0, %0, c10,  c2, 1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"p15, 0, %0, c12,  c0, 0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"p15, 0, %0, c12,  c0, 1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"p15, 0, %0, c12,  c1, 0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"p15, 0, %0, c12,  c1, 1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
+#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
+#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
+#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"p15, 0, %0, c15,  c0, 0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"p15, 4, %0, c15,  c0, 0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"p15, 5, %0, c15,  c4, 2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"p15, 5, %0, c15,  c4, 4"
+
+#define XREG_CP15_MAIN_TLB_VA			"p15, 5, %0, c15,  c5, 2"
+
+#define XREG_CP15_MAIN_TLB_PA			"p15, 5, %0, c15,  c6, 2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"p15, 5, %0, c15,  c7, 2"
+
+#else
+/* C2 Register Defines */
+#define XREG_CP15_TTBR0				"cp15:0:c2:c0:0"
+#define XREG_CP15_TTBR1				"cp15:0:c2:c0:1"
+#define XREG_CP15_TTB_CONTROL			"cp15:0:c2:c0:2"
+
+/* C3 Register Defines */
+#define XREG_CP15_DOMAIN_ACCESS_CTRL		"cp15:0:c3:c0:0"
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"cp15:0:c5:c0:0"
+#define XREG_CP15_INST_FAULT_STATUS		"cp15:0:c5:c0:1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"cp15:0:c5:c1:0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"cp15:0:c5:c1:1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"cp15:0:c6:c0:0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"cp15:0:c6:c0:2"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"cp15:0:c7:c0:4"
+
+#define XREG_CP15_INVAL_IC_POU_IS		"cp15:0:c7:c1:0"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_IS		"cp15:0:c7:c1:6"
+
+#define XREG_CP15_PHYS_ADDR			"cp15:0:c7:c4:0"
+
+#define XREG_CP15_INVAL_IC_POU			"cp15:0:c7:c5:0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"cp15:0:c7:c5:1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex A9.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"cp15:0:c7:c5:4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"cp15:0:c7:c5:6"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"cp15:0:c7:c6:1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"cp15:0:c7:c6:2"
+
+#define XREG_CP15_VA_TO_PA_CURRENT_0		"cp15:0:c7:c8:0"
+#define XREG_CP15_VA_TO_PA_CURRENT_1		"cp15:0:c7:c8:1"
+#define XREG_CP15_VA_TO_PA_CURRENT_2		"cp15:0:c7:c8:2"
+#define XREG_CP15_VA_TO_PA_CURRENT_3		"cp15:0:c7:c8:3"
+
+#define XREG_CP15_VA_TO_PA_OTHER_0		"cp15:0:c7:c8:4"
+#define XREG_CP15_VA_TO_PA_OTHER_1		"cp15:0:c7:c8:5"
+#define XREG_CP15_VA_TO_PA_OTHER_2		"cp15:0:c7:c8:6"
+#define XREG_CP15_VA_TO_PA_OTHER_3		"cp15:0:c7:c8:7"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"cp15:0:c7:c10:1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"cp15:0:c7:c10:2"
+
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex A9.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"cp15:0:c7:c10:4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"cp15:0:c7:c10:5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"cp15:0:c7:c11:1"
+
+#define XREG_CP15_NOP2				"cp15:0:c7:c13:1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"cp15:0:c7:c14:1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"cp15:0:c7:c14:2"
+
+/* C8 Register Defines */
+#define XREG_CP15_INVAL_TLB_IS			"cp15:0:c8:c3:0"
+#define XREG_CP15_INVAL_TLB_MVA_IS		"cp15:0:c8:c3:1"
+#define XREG_CP15_INVAL_TLB_ASID_IS		"cp15:0:c8:c3:2"
+#define XREG_CP15_INVAL_TLB_MVA_ASID_IS		"cp15:0:c8:c3:3"
+
+#define XREG_CP15_INVAL_ITLB_UNLOCKED		"cp15:0:c8:c5:0"
+#define XREG_CP15_INVAL_ITLB_MVA		"cp15:0:c8:c5:1"
+#define XREG_CP15_INVAL_ITLB_ASID		"cp15:0:c8:c5:2"
+
+#define XREG_CP15_INVAL_DTLB_UNLOCKED		"cp15:0:c8:c6:0"
+#define XREG_CP15_INVAL_DTLB_MVA		"cp15:0:c8:c6:1"
+#define XREG_CP15_INVAL_DTLB_ASID		"cp15:0:c8:c6:2"
+
+#define XREG_CP15_INVAL_UTLB_UNLOCKED		"cp15:0:c8:c7:0"
+#define XREG_CP15_INVAL_UTLB_MVA		"cp15:0:c8:c7:1"
+#define XREG_CP15_INVAL_UTLB_ASID		"cp15:0:c8:c7:2"
+#define XREG_CP15_INVAL_UTLB_MVA_ASID		"cp15:0:c8:c7:3"
+
+/* C9 Register Defines */
+#define XREG_CP15_PERF_MONITOR_CTRL		"cp15:0:c9:c12:0"
+#define XREG_CP15_COUNT_ENABLE_SET		"cp15:0:c9:c12:1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"cp15:0:c9:c12:2"
+#define XREG_CP15_V_FLAG_STATUS			"cp15:0:c9:c12:3"
+#define XREG_CP15_SW_INC			"cp15:0:c9:c12:4"
+#define XREG_CP15_EVENT_CNTR_SEL		"cp15:0:c9:c12:5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"cp15:0:c9:c13:0"
+#define XREG_CP15_EVENT_TYPE_SEL		"cp15:0:c9:c13:1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"cp15:0:c9:c13:2"
+
+#define XREG_CP15_USER_ENABLE			"cp15:0:c9:c14:0"
+#define XREG_CP15_INTR_ENABLE_SET		"cp15:0:c9:c14:1"
+#define XREG_CP15_INTR_ENABLE_CLR		"cp15:0:c9:c14:2"
+
+/* C10 Register Defines */
+#define XREG_CP15_TLB_LOCKDWN			"cp15:0:c10:c0:0"
+
+#define XREG_CP15_PRI_MEM_REMAP			"cp15:0:c10:c2:0"
+#define XREG_CP15_NORM_MEM_REMAP		"cp15:0:c10:c2:1"
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+#define XREG_CP15_VEC_BASE_ADDR			"cp15:0:c12:c0:0"
+#define XREG_CP15_MONITOR_VEC_BASE_ADDR		"cp15:0:c12:c0:1"
+
+#define XREG_CP15_INTERRUPT_STATUS		"cp15:0:c12:c1:0"
+#define XREG_CP15_VIRTUALIZATION_INTR		"cp15:0:c12:c1:1"
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"cp15:0:c13:c0:1"
+#define USER_RW_THREAD_PID			"cp15:0:c13:c0:2"
+#define USER_RO_THREAD_PID			"cp15:0:c13:c0:3"
+#define USER_PRIV_THREAD_PID			"cp15:0:c13:c0:4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_POWER_CTRL			"cp15:0:c15:c0:0"
+#define XREG_CP15_CONFIG_BASE_ADDR		"cp15:4:c15:c0:0"
+
+#define XREG_CP15_READ_TLB_ENTRY		"cp15:5:c15:c4:2"
+#define XREG_CP15_WRITE_TLB_ENTRY		"cp15:5:c15:c4:4"
+
+#define XREG_CP15_MAIN_TLB_VA			"cp15:5:c15:c5:2"
+
+#define XREG_CP15_MAIN_TLB_PA			"cp15:5:c15:c6:2"
+
+#define XREG_CP15_MAIN_TLB_ATTR			"cp15:5:c15:c7:2"
+#endif
+
+
+/* MPE register definitions */
+#define XREG_FPSID				c0
+#define XREG_FPSCR				c1
+#define XREG_MVFR1				c6
+#define XREG_MVFR0				c7
+#define XREG_FPEXC				c8
+#define XREG_FPINST				c9
+#define XREG_FPINST2				c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0xFF << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(1<<23)
+#define XREG_FPSID_ARCH_BIT		(16)
+#define XREG_FPSID_ARCH_MASK		(0xF  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8)
+#define XREG_FPSID_PART_MASK		(0xFF << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4)
+#define XREG_FPSID_VARIANT_MASK		(0xF  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0)
+#define XREG_FPSID_REV_MASK		(0xF  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(1 << 31)
+#define XREG_FPSCR_Z_BIT		(1 << 30)
+#define XREG_FPSCR_C_BIT		(1 << 29)
+#define XREG_FPSCR_V_BIT		(1 << 28)
+#define XREG_FPSCR_QC			(1 << 27)
+#define XREG_FPSCR_AHP			(1 << 26)
+#define XREG_FPSCR_DEFAULT_NAN		(1 << 25)
+#define XREG_FPSCR_FLUSHTOZERO		(1 << 24)
+#define XREG_FPSCR_ROUND_NEAREST	(0 << 22)
+#define XREG_FPSCR_ROUND_PLUSINF	(1 << 22)
+#define XREG_FPSCR_ROUND_MINUSINF	(2 << 22)
+#define XREG_FPSCR_ROUND_TOZERO		(3 << 22)
+#define XREG_FPSCR_RMODE_BIT		(22)
+#define XREG_FPSCR_RMODE_MASK		(3 << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20)
+#define XREG_FPSCR_STRIDE_MASK		(3 << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16)
+#define XREG_FPSCR_LENGTH_MASK		(7 << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(1 << 7)
+#define XREG_FPSCR_IXC			(1 << 4)
+#define XREG_FPSCR_UFC			(1 << 3)
+#define XREG_FPSCR_OFC			(1 << 2)
+#define XREG_FPSCR_DZC			(1 << 1)
+#define XREG_FPSCR_IOC			(1 << 0)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28)
+#define XREG_MVFR0_RMODE_MASK		(0xF << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0xF << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20)
+#define XREG_MVFR0_SQRT_MASK		(0xF << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16)
+#define XREG_MVFR0_DIVIDE_MASK		(0xF << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(12)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0xF << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8)
+#define XREG_MVFR0_DP_MASK		(0xF << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4)
+#define XREG_MVFR0_SP_MASK		(0xF << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0)
+#define XREG_MVFR0_A_SIMD_MASK		(0xF << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(1 << 31)
+#define XREG_FPEXC_EN			(1 << 30)
+#define XREG_FPEXC_DEX			(1 << 29)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXA9_H */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h
new file mode 100644
index 0000000..9937475
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xstatus.h
@@ -0,0 +1,535 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/*!< An error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/*!< An error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/*!< A DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/*!< The device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/*!< A FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/*!< The buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/*!< There was no data available */
+#define XST_REGISTER_ERROR              14L	/*!< A register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/*!< An invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/*!< The device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/*!< A loopback test failed */
+#define XST_NO_CALLBACK                 18L	/*!< A callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/*!< Device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/*!< Device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/*!< Device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/*!< The error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/*!< Used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/*!< Used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/*!< Driver defined error */
+#define XST_RECV_ERROR                  27L	/*!< Generic receive error */
+#define XST_SEND_ERROR                  28L	/*!< Generic transmit error */
+#define XST_NOT_ENABLED                 29L	/*!< A requested service is not
+						   available because it has not
+						   been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500  *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED              401L	/*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/*!< Not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/*!< Not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/*!< Packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/*!< Self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/*!< Scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/*!< All the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/*!< The scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/*!< No buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/*!< The packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/*!< The scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/*!< No scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/*!< The buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/*!< The buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/*!< General purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/*!< General buffer descriptor
+						   error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/*!< An invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/*!< The value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/*!< A write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/*!< The device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/*!< The device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/*!< A write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/*!< The IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/*!< IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/*!< The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/*!< The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/*!< Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/*!< MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/*!< Excess deferral or late
+						 * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/*!< self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/*!< bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/*!< mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/*!< A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/*!< Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/*!< Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/*!< 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/*!< Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/*!< Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/*!< the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/*!< Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/*!< Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/*!< Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/*!< Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/*!< Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/*!< Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/*!< Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/*!< Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/*!< Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/*!< more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/*!< device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE           1163        /*!< controller completed polling the
+						   device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/*!< the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/*!< an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/*!< bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/*!< the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/*!< self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/*!< Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/*!< Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/*!< Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/*!< Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/*!< Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/*!< Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/*!< Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/*!< Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/*!< Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/*!< Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/*!< Flash is write protected
+						 */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c
new file mode 100644
index 0000000..e81643f
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex A9 MP core.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 
    
+*
+* @note		None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************/
+/**
+* @brief	Set the time in the Global Timer Counter Register.
+*
+* @param	Xtime_Global: 64-bit Value to be written to the Global Timer
+*			Counter Register.
+*
+* @return	None.
+*
+* @note		When this function is called by any one processor in a multi-
+*			processor environment, reference time will reset/lost for all
+*			processors.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+	/* Disable Global Timer */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x0);
+
+	/* Updating Global Timer Counter Register */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_LOWER_OFFSET, (u32)Xtime_Global);
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_COUNTER_UPPER_OFFSET,
+		(u32)((u32)(Xtime_Global>>32U)));
+
+	/* Enable Global Timer */
+	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
+}
+
+/****************************************************************************/
+/**
+* @brief	Get the time from the Global Timer Counter Register.
+*
+* @param	Xtime_Global: Pointer to the 64-bit location which will be
+*			updated with the current timer value.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+	u32 low;
+	u32 high;
+
+	/* Reading Global Timer Counter Register */
+	do
+	{
+		high = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET);
+		low = Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_LOWER_OFFSET);
+	} while(Xil_In32(GLOBAL_TMR_BASEADDR + GTIMER_COUNTER_UPPER_OFFSET) != high);
+
+	*Xtime_Global = (((XTime) high) << 32U) | (XTime) low;
+}
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
new file mode 100644
index 0000000..9b872b6
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/standalone_v6_7/src/xtime_l.h
@@ -0,0 +1,105 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
+*
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 1.00a rp/sdm 11/03/09 Initial release.
+* 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
+* 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
+* 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
+*						implementation
+* 
    
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+typedef u64 XTime;
+
+/************************** Constant Definitions *****************************/
+#define GLOBAL_TMR_BASEADDR               XPAR_GLOBAL_TMR_BASEADDR
+#define GTIMER_COUNTER_LOWER_OFFSET       0x00U
+#define GTIMER_COUNTER_UPPER_OFFSET       0x04U
+#define GTIMER_CONTROL_OFFSET             0x08U
+
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND          (SLEEP_TIMER_FREQUENCY)
+#else
+/* Global Timer is always clocked at half of the CPU frequency */
+#define COUNTS_PER_SECOND          (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
\ No newline at end of file
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.c
new file mode 100644
index 0000000..88f96d7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.c
@@ -0,0 +1,448 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2018 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.c
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file contains the implementation of the XTtcPs driver. This driver
+* controls the operation of one timer counter in the Triple Timer Counter (TTC)
+* module in the Ps block. Refer to xttcps.h for more detailed description
+* of the driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	   01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
+*						to stop the timer before configuring
+* 3.2   mus    10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
+*                       32 bit interval count for zynq ultrascale+mpsoc
+* 3.5   srm    10/06/17 Updated XTtcPs_GetMatchValue and XTtcPs_SetMatchValue
+*                       APIs to use correct match register width for zynq
+*                       (i.e. 16 bit) and zynq ultrascale+mpsoc (i.e. 32 bit).
+*                       It fixes CR# 986617
+* 3.6   srm    04/25/18 Corrected the Match register initialization in
+						XTtcPs_CfgInitialize API.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XTtcPs instance such that the driver is ready to use.
+* This function initializes a single timer counter in the triple timer counter
+* function block.
+*
+* The state of the device after initialization is:
+*  - Overflow Mode
+*  - Internal (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific TTC device.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, then use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return
+*
+* 		- XST_SUCCESS if the initialization is successful.
+*		- XST_DEVICE_IS_STARTED if the device is started. It must be
+*		  stopped to re-initialize.
+*
+* @note		Device has to be stopped first to call this function to
+*		initialize it.
+*
+******************************************************************************/
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
+			      u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 IsStartResult;
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+
+	IsStartResult = XTtcPs_IsStarted(InstancePtr);
+	/*
+	 * If the timer counter has already started, return an error
+	 * Device should be stopped first.
+	 */
+	if(IsStartResult == (u32)TRUE) {
+		Status = XST_DEVICE_IS_STARTED;
+	} else {
+
+		/*
+		 * stop the timer before configuring
+		 */
+		XTtcPs_Stop(InstancePtr);
+		/*
+		 * Reset the count control register to it's default value.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET,
+				  XTTCPS_CNT_CNTRL_RESET_VALUE);
+
+		/*
+		 * Reset the rest of the registers to the default values.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_0_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_1_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_IER_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		/*
+		 * Reset the counter value
+		 */
+		XTtcPs_ResetCounterValue(InstancePtr);
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set the match registers. There are three match
+* registers.
+*
+* The match 0 register is special. If the waveform output mode is enabled, the
+* waveform will change polarity when the count matches the value in the match 0
+* register. The polarity of the waveform output can also be set using the
+* XTtcPs_SetOptions() function.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+* @param	Value is the 16-bit value to be set in the match register.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value)
+{
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
+
+	/*
+	 * Write the value to the correct match register with MatchIndex
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTtcPs_Match_N_Offset(MatchIndex), Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to get the value of the match registers. There are
+* three match registers.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+*
+* @return	The match register value
+*
+* @note		None
+*
+****************************************************************************/
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+{
+	u32 MatchReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+	MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XTtcPs_Match_N_Offset(MatchIndex));
+
+	return (XMatchRegValue) MatchReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler enable bit and if needed sets the prescaler
+* bits in the control register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	PrescalerValue is a number from 0-16 that sets the prescaler
+*		to use.
+*		If the parameter is 0 - 15, use a prescaler on the clock of
+*		2^(PrescalerValue+1), or 2-65536.
+*		If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
+*		prescaler.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
+{
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			   XTTCPS_CLK_CNTRL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register
+	 */
+	ClockReg &=
+		~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
+
+	if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
+		/*
+		 * Set the prescaler value and enable prescaler
+		 */
+		ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
+		ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
+	}
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the input clock prescaler
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* 
    +* @return	The value(n) from which the prescalar value is calculated
+*		as 2^(n+1). Some example values are given below :
+*
+* 	Value		Prescaler
+* 	0		2
+* 	1		4
+* 	N		2^(n+1)
+* 	15		65536
+* 	16		1
+* 
    
+*
+* @note		None.
+*
+****************************************************************************/
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
+{
+	u8 Status;
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+
+	if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
+		/*
+		 * Prescaler is disabled. Return the correct flag value
+		 */
+		Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
+	}
+	else {
+
+		Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the interval value as well as the prescaler value
+* for a given frequency.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Freq is the requested output frequency for the device.
+* @param	Interval is the interval value for the given frequency,
+*		it is the output value for this function.
+* @param	Prescaler is the prescaler value for the given frequency,
+*		it is the output value for this function.
+*
+* @return	None.
+*
+* @note
+*  Upon successful calculation for the given frequency, Interval and Prescaler
+*  carry the settings for the timer counter; Upon unsuccessful calculation,
+*  Interval and Prescaler are set to 0xFF(FF) for their maximum values to
+*  signal the caller of failure. Therefore, caller needs to check the return
+*  interval or prescaler values for whether the function has succeeded.
+*
+****************************************************************************/
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        XInterval *Interval, u8 *Prescaler)
+{
+	u8 TmpPrescaler;
+	u32 TempValue;
+	u32 InputClock;
+
+	InputClock = InstancePtr->Config.InputClockHz;
+	/*
+	 * Find the smallest prescaler that will work for a given frequency. The
+	 * smaller the prescaler, the larger the count and the more accurate the
+	 *  PWM setting.
+	 */
+	TempValue = InputClock/ Freq;
+
+	if (TempValue < 4U) {
+		/*
+		 * The frequency is too high, it is too close to the input
+		 * clock value. Use maximum values to signal caller.
+		 */
+		*Interval = XTTCPS_MAX_INTERVAL_COUNT;
+		*Prescaler = 0xFFU;
+		return;
+	}
+
+	/*
+	 * First, do we need a prescaler or not?
+	 */
+	if (((u32)65536U) > TempValue) {
+		/*
+		 * We do not need a prescaler, so set the values appropriately
+		 */
+		*Interval = (XInterval)TempValue;
+		*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
+		return;
+	}
+
+
+	for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
+	     TmpPrescaler++) {
+		TempValue =	InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
+
+		/*
+		 * The first value less than 2^16 is the best bet
+		 */
+		if (((u32)65536U) > TempValue) {
+			/*
+			 * Set the values appropriately
+			 */
+			*Interval = (XInterval)TempValue;
+			*Prescaler = TmpPrescaler;
+			return;
+		}
+	}
+
+	/* Can not find interval values that work for the given frequency.
+	 * Return maximum values to signal caller.
+	 */
+	*Interval = XTTCPS_MAX_INTERVAL_COUNT;
+	*Prescaler = 0XFFU;
+	return;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.h
new file mode 100644
index 0000000..b7b4e19
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps.h
@@ -0,0 +1,467 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_5
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+*	. At a regular, predefined period, that is on a timed interval
+*	. When the counter registers overflow
+* 	. When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* Initialization & Configuration
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* Interrupts
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+*  - Overflow Mode
+*  - Internal clock (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.2   mus    10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
+*                       macros to return 32 bit values for zynq ultrascale+mpsoc
+*       ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* 3.4   ms   04/18/17 Modified tcl file to add suffix U for all macros
+*                     definitions of ttcps in xparameters.h
+* 3.5   srm  10/06/17 Added new typedef XMatchRegValue for match register width
+*
+* 
    
+*
+******************************************************************************/
+
+#ifndef XTTCPS_H		/* prevent circular inclusions */
+#define XTTCPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/*
+ * Maximum Value for interval counter
+ */
+ #if defined(ARMA9)
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU
+ #else
+ #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU
+ #endif
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK	0x00000001U 	/**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG	0x00000002U	/**< Clock on trailing edge for
+						     external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE	0x00000004U	/**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT		0x00000008U	/**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE	0x00000010U	/**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE	0x00000020U 	/**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY	0x00000040U	/**< Waveform polarity */
+/*@}*/
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	  /**< Unique ID for device */
+	u32 BaseAddress;  /**< Base address for device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+	XTtcPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+} XTtcPs;
+
+/**
+ * This typedef contains interval count and Match register value
+ */
+#if defined(ARMA9)
+typedef u16 XInterval;
+typedef u16 XMatchRegValue;
+#else
+typedef u32 XInterval;
+typedef u32 XMatchRegValue;
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+    (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+    (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr)	\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &	\
+		 ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr)		\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |	\
+		 XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance
+*
+* @return	Non-zero if the device has started, '0' otherwise.
+*
+* @note		C-style signature:
+*		int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+     ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+       XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	zynq:16 bit counter value.
+*           zynq ultrascale+mpsoc:32 bit counter value.
+*
+* @note		C-style signature:
+*		zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit counter for zynq
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#else
+/*
+ * ttc supports 32 bit counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetCounterValue(InstancePtr) \
+               InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Value is the 16-bit value to be set in the interval register.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value)	\
+		InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	zynq:16 bit interval value.
+*           zynq ultrascale+mpsoc:32 bit interval value.
+*
+* @note		C-style signature:
+*		zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*       zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#if defined(ARMA9)
+/*
+ * ttc supports 16 bit interval counter for zynq
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#else
+/*
+ * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc
+ */
+#define XTtcPs_GetInterval(InstancePtr) \
+		InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+#endif
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+		 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be enabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be enabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)		\
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,		\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |	\
+		 (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be disabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be disabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &	\
+		 ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr)	 \
+		InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be cleared.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be cleared, cleared bits
+*		will not be cleared.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+		 (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+         XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value);
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        XInterval *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_g.c
new file mode 100644
index 0000000..f88e5ef
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_g.c
@@ -0,0 +1,66 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XTtcPs_Config XTtcPs_ConfigTable[] =
+{
+	{
+		XPAR_PS7_TTC_0_DEVICE_ID,
+		XPAR_PS7_TTC_0_BASEADDR,
+		XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PS7_TTC_1_DEVICE_ID,
+		XPAR_PS7_TTC_1_BASEADDR,
+		XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PS7_TTC_2_DEVICE_ID,
+		XPAR_PS7_TTC_2_BASEADDR,
+		XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_hw.h
new file mode 100644
index 0000000..b1fa545
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_hw.h
@@ -0,0 +1,233 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.5   srm    10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+*                       XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+*                       mask 16 bit values for zynq and 32 bit values for
+*                       zynq ultrascale+mpsoc "
+* 
    
+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H		/* prevent circular inclusions */
+#define XTTCPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET		0x00000000U  /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET		0x0000000CU  /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET	0x00000018U  /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET	0x00000024U  /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET		0x00000030U  /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET		0x0000003CU  /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET		0x00000048U  /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET			0x00000054U  /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET			0x00000060U  /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK		0x00000001U  /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK	0x0000001EU  /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT			 1U  /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE				16U  /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK		0x00000020U  /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK	0x00000040U  /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK		0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK		0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK		0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK		0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK		0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK	0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK	0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE	0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_COUNT_VALUE_MASK		0x0000FFFFU /**< 16-bit counter value */
+#else
+#define XTTCPS_COUNT_VALUE_MASK		0xFFFFFFFFU /**< 32-bit counter value */
+#endif
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFFU /**< 16-bit Interval value*/
+#else
+#define XTTCPS_INTERVAL_VAL_MASK	0xFFFFFFFFU /**< 32-bit Interval value*/
+#endif
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#if defined(ARMA9)
+#define XTTCPS_MATCH_MASK		0x0000FFFFU /**< 16-bit Match value */
+#else
+#define XTTCPS_MATCH_MASK		0xFFFFFFFFU /**< 32-bit Match value */
+#endif
+#define XTTCPS_NUM_MATCH_REG			 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK	0x00000001U  /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK		0x00000002U  /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK		0x00000004U  /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK		0x00000008U  /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK		0x00000010U  /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK			0x0000001FU  /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param	MatchIndex is the 0-2 value of the match register
+*
+* @return	MATCH_N_OFFSET.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+		((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_options.c
new file mode 100644
index 0000000..01dd9ef
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_options.c
@@ -0,0 +1,243 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_options.c
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file contains functions to get or set option features for the device.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 1.01a nm     03/05/2012 Removed break statement after return to remove
+*                         compilation warnings.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+	u32 Register;
+} OptionsMap;
+
+static OptionsMap TmrCtrOptionsTable[] = {
+	{XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+};
+
+#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
+				sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained
+*		in the mask. See the bit definitions named XTTCPS_*_OPTION in
+*		the file xttcps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_FAILURE if any of the options are unknown.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
+{
+	u32 CountReg;
+	u32 ClockReg;
+	u32 Index;
+	s32 Status = XST_SUCCESS;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+	CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CNT_CNTRL_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		if(Status != (s32)XST_FAILURE) {
+			if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
+
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Add option */
+				ClockReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Add option */
+				CountReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+			}
+		}
+		else {
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Remove option*/
+				ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Remove option*/
+				CountReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Now write the registers. Leave it to the upper layers to restart the
+	 * device.
+	 */
+	if (Status != (s32)XST_FAILURE ) {
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET, CountReg);
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the settings for the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* The return u32 contains the specified options that are set. This is a bit
+* mask where a '1' means the option is on, and a'0' means the option is off.
+* One or more bit values may be contained in the mask. See the bit definitions
+* named XTTCPS_*_OPTION in the file xttcps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 Register;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Loop through the options table to determine which options are set
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		/*
+		 * Get the control register to determine which options are
+		 * currently set.
+		 */
+		Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+					      TmrCtrOptionsTable[Index].
+					      Register);
+
+		if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
+			OptionsFlag |= TmrCtrOptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_selftest.c
new file mode 100644
index 0000000..b1dd7d0
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_selftest.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_selftest.c
+* @addtogroup ttcps_v3_5
+* @{
+*
+* This file contains the implementation of self test function for the
+* XTtcPs driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device.
+*
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+*	- XST_SUCCESS if successful
+*	- XST_FAILURE indicates a register did not read or write correctly
+*
+* @note		This test fails if it is not called right after initialization.
+*
+******************************************************************************/
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
+{
+	s32 Status;
+	u32 TempReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the TTC registers should be in their default state right now.
+	 */
+	TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XTTCPS_CNT_CNTRL_OFFSET);
+	if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
+		Status = XST_FAILURE;
+	}
+	else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_sinit.c
new file mode 100644
index 0000000..4684c8a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_6/src/xttcps_sinit.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_sinit.c
+* @addtogroup ttcps_v3_5
+* @{
+*
+* The implementation of the XTtcPs driver's static initialization functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the unique ID of the device
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xttcps.h for the definition of XTtcPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
+{
+	XTtcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
+		if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XTtcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XTtcPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
new file mode 100644
index 0000000..c33ec54
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
@@ -0,0 +1,645 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	 Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 3.5	NK     09/26/17 Fix the RX Buffer Overflow issue.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE		 3U	/* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount);
+
+u32  XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32  XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Config is a reference to a structure containing information
+*		about a specific XUartPs driver.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, pass in the physical
+*		address instead.
+*
+* @return
+*
+*		- XST_SUCCESS if initialization was successful
+*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
+*		  the inputclock frequency is not divisible with an acceptable
+*		  amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*   All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				   XUartPs_Config * Config, u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 ModeRegister;
+	u32 BaudRate;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Config != NULL);
+
+	/* Setup the driver instance using passed in parameters */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = Config->InputClockHz;
+	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+	/* Initialize other instance data to default values */
+	InstancePtr->Handler = XUartPs_StubHandler;
+
+	InstancePtr->SendBuffer.NextBytePtr = NULL;
+	InstancePtr->SendBuffer.RemainingBytes = 0U;
+	InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+	/* Initialize the platform data */
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	InstancePtr->is_rxbs_error = 0U;
+
+	/* Flag that the driver instance is ready to use */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Set the default baud rate here, can be changed prior to
+	 * starting the device
+	 */
+	BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+	Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+	if (Status != (s32)XST_SUCCESS) {
+		InstancePtr->IsReady = 0U;
+	} else {
+
+		/*
+		 * Set up the default data format: 8 bit data, 1 stop bit, no
+		 * parity
+		 */
+		ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XUARTPS_MR_OFFSET);
+
+		/* Mask off what's already there */
+		ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+						 (u32)XUARTPS_MR_STOPMODE_MASK |
+						 (u32)XUARTPS_MR_PARITY_MASK));
+
+		/* Set the register value to the desired data format */
+		ModeRegister |=	((u32)XUARTPS_MR_CHARLEN_8_BIT |
+						 (u32)XUARTPS_MR_STOPMODE_1_BIT |
+						 (u32)XUARTPS_MR_PARITY_NONE);
+
+		/* Write the mode register out */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+				   ModeRegister);
+
+		/* Set the RX FIFO trigger at 8 data bytes. */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXWM_OFFSET, 0x08U);
+
+		/* Set the RX timeout to 1, which will be 4 character time */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+		/* Disable all interrupts, polled mode is the default */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+				   XUARTPS_IXR_MASK);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	BufferPtr is pointer to a buffer of data to be sent.
+* @param  	NumBytes contains the number of bytes to be sent. A value of
+*		zero will stop a previous send operation that is in progress
+*		in interrupt mode. Any data that was already put into the
+*		transmit FIFO will be sent.
+*
+* @return	The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+* 

    
+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+			   u32 NumBytes)
+{
+	u32 BytesSent;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the UART transmit interrupts to allow this call to stop a
+	 * previous operation that may be interrupt driven.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+					  (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+	/* Setup the buffer parameters */
+	InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+	InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+	InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+	 * filling the TX FIFO.
+	 */
+	BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+	return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BufferPtr is pointer to buffer for data to be received into
+* @param	NumBytes is the number of bytes to be received. A value of zero
+*		will stop a previous receive operation that is in progress in
+*		interrupt mode.
+*
+* @return	The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+			  u8 *BufferPtr, u32 NumBytes)
+{
+	u32 ReceivedCount;
+	u32 ImrRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all the interrupts.
+	 * This stops a previous operation that may be interrupt driven
+	 */
+	ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup the buffer parameters */
+	InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+	/* Receive the data from the device */
+	ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+	/* Restore the interrupt state */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+		ImrRegister);
+
+	return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes actually sent
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+	u32 SentCount = 0U;
+	u32 ImrRegister;
+
+	/*
+	 * If the TX FIFO is full, send nothing.
+	 * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+	 * data has been put into the FIFO.
+	 */
+	while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+		   (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+		/* Fill the FIFO from the buffer */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_FIFO_OFFSET,
+				   ((u32)InstancePtr->SendBuffer.
+				   NextBytePtr[SentCount]));
+
+		/* Increment the send count. */
+		SentCount++;
+	}
+
+	/* Update the buffer to reflect the bytes that were sent from it */
+	InstancePtr->SendBuffer.NextBytePtr += SentCount;
+	InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+	/*
+	 * If interrupts are enabled as indicated by the receive interrupt, then
+	 * enable the TX FIFO empty interrupt, so further action can be taken
+	 * for this sending.
+	 */
+	ImrRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+		((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+		((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XUARTPS_IER_OFFSET,
+					   ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+	}
+
+	return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+	u32 CsrRegister;
+	u32 ReceivedCount = 0U;
+	u32 ByteStatusValue, EventData;
+	u32 Event;
+
+	/*
+	 * Read the Channel Status Register to determine if there is any data in
+	 * the RX FIFO
+	 */
+	CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_SR_OFFSET);
+
+	/*
+	 * Loop until there is no more data in RX FIFO or the specified
+	 * number of bytes has been received
+	 */
+	while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
+		(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+		if (InstancePtr->is_rxbs_error) {
+			ByteStatusValue = XUartPs_ReadReg(
+						InstancePtr->Config.BaseAddress,
+						XUARTPS_RXBS_OFFSET);
+			if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
+				EventData = ByteStatusValue;
+				Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
+				/*
+				 * Call the application handler to indicate that there is a receive
+				 * error or a break interrupt, if the application cares about the
+				 * error it call a function to get the last errors.
+				 */
+				InstancePtr->Handler(InstancePtr->CallBackRef,
+							Event, EventData);
+			}
+		}
+
+		InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+			XUartPs_ReadReg(InstancePtr->Config.
+				  BaseAddress,
+				  XUARTPS_FIFO_OFFSET);
+
+		ReceivedCount++;
+
+		CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+								XUARTPS_SR_OFFSET);
+	}
+	InstancePtr->is_rxbs_error = 0;
+	/*
+	 * Update the receive buffer to reflect the number of bytes just
+	 * received
+	 */
+	if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+		InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+	}
+	InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+	return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BaudRate to be set
+*
+* @return
+*		- XST_SUCCESS if everything configured as expected
+*		- XST_UART_BAUD_ERROR if the requested rate is not available
+*		  because there was too much error
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+	u32 IterBAUDDIV;	/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 ModeReg;
+	u32 InputClk;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+	Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+	/*
+	 * Make sure the baud rate is not impossilby large.
+	 * Fastest possible baud rate is Input Clock / 2.
+	 */
+	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+		return XST_UART_BAUD_ERROR;
+	}
+	/* Check whether the input clock is divided by 8 */
+	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+				 XUARTPS_MR_OFFSET);
+
+	InputClk = InstancePtr->Config.InputClockHz;
+	if(ModeReg & XUARTPS_MR_CLKSEL) {
+		InputClk = InstancePtr->Config.InputClockHz / 8;
+	}
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/* Calculate the value for BRGR register */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/* Calculate the baud rate from the BRGR value */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/* Avoid unsigned integer underflow */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		}
+		else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/* Find the calculated baud rate closest to requested baud rate. */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/* Make sure the best error is not too large. */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+		return XST_UART_BAUD_ERROR;
+	}
+
+	/* Disable TX and RX to avoid glitches when setting the baud rate. */
+	XUartPs_DisableUart(InstancePtr);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/* RX and TX SW reset */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+	/* Enable device */
+	XUartPs_EnableUart(InstancePtr);
+
+	InstancePtr->BaudRate = BaudRate;
+
+	return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+* @param	ByteCount is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount)
+{
+	(void) CallBackRef;
+	(void) Event;
+	(void) ByteCount;
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
new file mode 100644
index 0000000..33758c2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
@@ -0,0 +1,520 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_5
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* 
    +*	baud_rate = input_clock / (bgen * (bdiv + 1)
+* 
    
+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
+*						platform variable in driver instance structure.
+* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
+*			uart is connected to a valid interrupt controller CR#946803.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+* 3.4   ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+* 3.6   ms     02/16/18 Updates the flow control mode offset value in modem
+*                       control register.
+*
+* 
    
+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H		/* prevent circular inclusions */
+#define XUARTPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE	 921600U
+#define XUARTPS_MIN_RATE	 110U
+
+#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified.  These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA			1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT			2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA			3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR		4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM				5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE	6U /**< A receive parity, frame, break
+											 *	error detected */
+#define XUARTPS_EVENT_RECV_ORERR		7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+	u32 InputClockHz;/**< Input clock frequency */
+	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+				 *  to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+	u8 *NextBytePtr;
+	u32 RequestedBytes;
+	u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+	u32 BaudRate;	/**< In bps, ie 1200 */
+	u32 DataBits;	/**< Number of data bits */
+	u32 Parity;		/**< Parity */
+	u8 StopBits;	/**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+				  u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XUartPs_Config Config;	/* Configuration data structure */
+	u32 InputClockHz;	/* Input clock frequency */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 BaudRate;		/* Current baud rate */
+
+	XUartPsBuffer SendBuffer;
+	XUartPsBuffer ReceiveBuffer;
+
+	XUartPs_Handler Handler;
+	void *CallBackRef;	/* Callback reference for event handler */
+	u32 Platform;
+	u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr)   \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr)  \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if a byte can be sent
+*		- FALSE if the Transmitter Fifo is not empty
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr)				\
+	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				  XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+			 void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
new file mode 100644
index 0000000..2956620
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c
@@ -0,0 +1,57 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_UART_1_DEVICE_ID,
+		XPAR_PS7_UART_1_BASEADDR,
+		XPAR_PS7_UART_1_UART_CLK_FREQ_HZ,
+		XPAR_PS7_UART_1_HAS_MODEM
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
new file mode 100644
index 0000000..724c3cb
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c
@@ -0,0 +1,180 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_5
+* @{
+*
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.05a hk     08/22/13 Added reset function
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	Data contains the byte to be sent.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+	/* Wait until there is space in TX FIFO */
+	while (XUartPs_IsTransmitFull(BaseAddress)) {
+		;
+	}
+
+	/* Write the byte into the TX FIFO */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	The data byte received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+	u32 RecievedByte;
+	/* Wait until there is data */
+	while (!XUartPs_IsReceiveData(BaseAddress)) {
+		;
+	}
+	RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+	/* Return the byte received */
+	return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+	/* Disable interrupts */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+	/* Disable receive and transmit */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+	/*
+	 * Software reset of receive and transmit
+	 * This clears the FIFO.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+	/* Clear status flags - SW reset wont clear sticky flags. */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Mode register reset value : All zeroes
+	 * Normal mode, even parity, 1 stop bit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+				XUARTPS_MR_CHMODE_NORM);
+
+	/* Rx and TX trigger register reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+				XUARTPS_RXWM_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+				XUARTPS_TXWM_RESET_VAL);
+
+	/* Rx timeout disabled by default */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+				XUARTPS_RXTOUT_DISABLE);
+
+	/* Baud rate generator and dividor reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+				XUARTPS_BAUDGEN_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+				XUARTPS_BAUDDIV_RESET_VAL);
+
+	/*
+	 * Control register reset value -
+	 * RX and TX are disable by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+						(u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
new file mode 100644
index 0000000..9a2bc43
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h
@@ -0,0 +1,451 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_5
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 3.6   ms     02/16/18 Updates flow control mode offset value in
+*			modem control register.
+*
+* 
    
+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
+#define XUARTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET		0x0000U  /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET		0x0004U  /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET		0x0008U  /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET		0x000CU  /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET		0x0010U  /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET		0x0014U  /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET		0x0020U  /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET		0x002CU  /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET		0x0030U  /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET		0x0044U  /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET		0x0048U  /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
+#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
+#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
+#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
+#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
+#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK				0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT				8U  /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT			6U  /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT				3U  /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT			1U  /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL			0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK	0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 	0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER	0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 	0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 	0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR  	0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK	0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE		0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK		0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK        0x000000FFU	/**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000FU	/**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE		0x00000000U  /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK			0x000000FFU  /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE	0x00000000U  /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM	0x00000020U  /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS	0x00000002U  /**< Request to send */
+#define XUARTPS_MODEMCR_DTR	0x00000001U  /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS	0x00000100U  /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD		0x00000080U  /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI		0x00000040U  /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR		0x00000020U  /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS		0x00000010U  /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD	0x00000008U  /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI  0x00000004U  /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR	0x00000002U  /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS	0x00000001U  /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR	0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE		0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME		0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE		0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE		0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME		0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE		0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE		0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME		0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE		0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE		0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME		0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE		0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK		0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
+#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+*						   u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if there is receive data, FALSE otherwise.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress)			 \
+	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*		FIFO.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress)			 \
+	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	 (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
new file mode 100644
index 0000000..dff02fd
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c
@@ -0,0 +1,450 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the functions for interrupt handling
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		The current interrupt mask. The mask indicates which interupts
+*		are enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+	/* Assert validates the input argument */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Read the Interrupt Mask register */
+	return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	Mask contains the interrupts to be enabled or disabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+	u32 TempMask = Mask;
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	TempMask &= (u32)XUARTPS_IXR_MASK;
+
+	/* Write the mask to the IER Register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IER_OFFSET, TempMask);
+
+	/* Write the inverse of the Mask to the IDR register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active
+	 */
+	IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+
+	IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_ISR_OFFSET);
+
+	/* Dispatch an appropriate handler. */
+	if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+			(u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+		/* Received data interrupt */
+		ReceiveDataHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+									 != (u32)0) {
+		/* Transmit data interrupt */
+		SendDataHandler(InstancePtr, IsrStatus);
+	}
+
+	/* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
+	if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+			(u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
+		/* Received Error Status interrupt */
+		ReceiveErrorHandler(InstancePtr, IsrStatus);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+		/* Received Timeout interrupt */
+		ReceiveTimeoutHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+		/* Modem status interrupt */
+		ModemHandler(InstancePtr);
+	}
+
+	/* Clear the interrupt status. */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+		IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+	u32 EventData;
+	u32 Event;
+
+	InstancePtr->is_rxbs_error = 0;
+
+	if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
+		(IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
+					| (u32)XUARTPS_IXR_FRAMING))) {
+		InstancePtr->is_rxbs_error = 1;
+	}
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+
+	(void)XUartPs_ReceiveBuffer(InstancePtr);
+
+	if (!(InstancePtr->is_rxbs_error)) {
+		Event = XUARTPS_EVENT_RECV_ERROR;
+		EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
+			InstancePtr->ReceiveBuffer.RemainingBytes;
+
+		/*
+		 * Call the application handler to indicate that there is a receive
+		 * error or a break interrupt, if the application cares about the
+		 * error it call a function to get the last errors.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					Event,
+					EventData);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+	u32 Event;
+
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * If there are no more bytes to receive then indicate that this is
+	 * not a receive timeout but the end of the buffer reached, a timeout
+	 * normally occurs if # of bytes is not divisible by FIFO threshold,
+	 * don't rely on previous test of remaining bytes since receive
+	 * function updates it
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		Event = XUARTPS_EVENT_RECV_TOUT;
+	} else {
+		Event = XUARTPS_EVENT_RECV_DATA;
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * timeout or data event
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+				 InstancePtr->ReceiveBuffer.RequestedBytes -
+				 InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	 if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	 /* If the last byte of a message was received then call the application
+	 * handler, this code should not use an else from the previous check of
+	 * the number of bytes to receive because the call to receive the buffer
+	 * updates the bytes ramained
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_DATA,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	IsrStatus is the register value for channel status register
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+	/*
+	 * If there are not bytes to be sent from the specified buffer then disable
+	 * the transmit interrupt so it will stop interrupting as it interrupts
+	 * any time the FIFO is empty
+	 */
+	if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_IDR_OFFSET,
+				((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+		/* Call the application handler to indicate the sending is done */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XUARTPS_EVENT_SENT_DATA,
+					InstancePtr->SendBuffer.RequestedBytes -
+					InstancePtr->SendBuffer.RemainingBytes);
+	}
+
+	/* If TX FIFO is empty, send more. */
+	else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+		(void)XUartPs_SendBuffer(InstancePtr);
+	}
+	else {
+		/* Else with dummy entry for MISRA-C Compliance.*/
+		;
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts.  It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+	u32 MsrRegister;
+
+	/*
+	 * Read the modem status register so that the interrupt is acknowledged
+	 * and it can be passed to the callback handler with the event
+	 */
+	MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			  XUARTPS_MODEMSR_OFFSET);
+
+	/*
+	 * Call the application handler to indicate the modem status changed,
+	 * passing the modem status and the event data in the call
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				  XUARTPS_EVENT_MODEM,
+				  MsrRegister);
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
new file mode 100644
index 0000000..5d8d301
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c
@@ -0,0 +1,764 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+*			value was not being written to the register.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+*
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+	u16 Option;
+	u16 RegisterOffset;
+	u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+	{XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+	{XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+	{XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+	{XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+	{XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+	{XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_RTS},
+	{XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_DTR},
+	{XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS	  (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+	u16 Options = 0U;
+	u32 Register;
+	u32 Index;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the physical options in the
+	 * registers of the UART to the logical options to be returned
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the bit in the register which correlates to the option
+		 * is set, then set the corresponding bit in the options,
+		 * ignoring any bits which are zero since the options variable
+		 * is initialized to zero
+		 */
+		if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+			Options |= OptionsTable[Index].Option;
+		}
+	}
+
+	return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Options contains the options to be set which are bit masks
+*		contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+	u32 Index;
+	u32 Register;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the logical options to the
+	 * physical options in the registers of the UART.
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+		/*
+		 * Read the register which contains option so that the register
+		 * can be changed without destoying any other bits of the
+		 * register.
+		 */
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the option is set in the input, then set the corresponding
+		 * bit in the specified register, otherwise clear the bit in
+		 * the register.
+		 */
+		if ((Options & OptionsTable[Index].Option) != (u16)0) {
+			if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK)
+				Register &= ~XUARTPS_CR_STOPBRK;
+			Register |= OptionsTable[Index].Mask;
+		}
+		else {
+			Register &= ~OptionsTable[Index].Mask;
+		}
+
+		/* Write the new value to the register to set the option */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   OptionsTable[Index].RegisterOffset,
+				   Register);
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current receive FIFO trigger level. This is a value
+*		from 0-31.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+	u8 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the value of the FIFO control register so that the threshold
+	 * can be retrieved, this read takes special register processing
+	 */
+	RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XUARTPS_RXWM_OFFSET);
+
+	/* Return only the trigger level from the register value */
+
+	RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+	return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	TriggerLevel contains the trigger level to set.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+	u32 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+	/*
+	 * Write the new value for the FIFO control register to it such that the
+	 * threshold is changed
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+	u32 ModemStatusRegister;
+	u16 TmpRegister;
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the modem status register to return
+	 */
+	ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUARTPS_MODEMSR_OFFSET);
+	TmpRegister = (u16)ModemStatusRegister;
+	return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if the UART is sending data
+*		- FALSE if UART is not sending data
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+	u32 ChanStatRegister;
+	u32 ChanTmpSRegister;
+	u32 ActiveResult;
+	u32 EmptyResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel status register to determine if the transmitter is
+	 * active
+	 */
+	ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 XUARTPS_SR_OFFSET);
+
+	/*
+	 * If the transmitter is active, or the TX FIFO is not empty, then indicate
+	 * that the UART is still sending some data
+	 */
+	ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+	EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+	ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+		(((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+	return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+	u32 ModeRegister;
+	u8 OperMode;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+	/* Return the constant */
+	switch (ModeRegister) {
+	case XUARTPS_MR_CHMODE_NORM:
+		OperMode = XUARTPS_OPER_MODE_NORMAL;
+		break;
+	case XUARTPS_MR_CHMODE_ECHO:
+		OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+		break;
+	case XUARTPS_MR_CHMODE_L_LOOP:
+		OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+		break;
+	case XUARTPS_MR_CHMODE_R_LOOP:
+		OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+		break;
+	default:
+		OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+			XUARTPS_MR_CHMODE_SHIFT);
+		break;
+	}
+
+	return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	OperationMode is the mode of the UART.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+	u32 ModeRegister;
+
+	/* Assert validates the input arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Set the correct value by masking the bits, then ORing the const. */
+	ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+	switch (OperationMode) {
+		case XUARTPS_OPER_MODE_NORMAL:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+			break;
+		case XUARTPS_OPER_MODE_AUTO_ECHO:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+			break;
+		case XUARTPS_OPER_MODE_LOCAL_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+			break;
+		case XUARTPS_OPER_MODE_REMOTE_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+			break;
+		default:
+			/* Default case made for MISRA-C Compliance. */
+			break;
+	}
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+	u32 FdelTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XUARTPS_FLOWDEL_OFFSET);
+
+	/* Return the contents of the flow delay register */
+	FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+	return  FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FlowDelayValue is the Setting for the flow delay.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+	u32 FdelRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by shifting the input constant, then masking
+	 * the bits
+	 */
+	FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current setting for receive time out.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+	u32 RtoRegister;
+	u8 RtoRTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Receive Timeout register. */
+	RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUARTPS_RXTOUT_OFFSET);
+
+	/* Return the contents of the mode register shifted appropriately */
+	RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+	return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RecvTimeout setting allows the UART to detect an idle connection
+*		on the reciever data line.
+*		Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+*		timeout function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+	u32 RtoRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Set the correct value by masking the bits */
+	RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+	/* Configure CR to restart the receiver timeout counter */
+	RtoRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_CR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+			   (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure containing the data
+*		format to be set.
+*
+* @return
+*		- XST_SUCCESS if the data format was successfully set.
+*		- XST_UART_BAUD_ERROR indicates the baud rate could not be
+*		set because of the amount of error with the baud rate and
+*		the input clock frequency.
+*		- XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+* 

    
+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+			XUartPsFormat * FormatPtr)
+{
+	s32 Status;
+	u32 ModeRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FormatPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Verify the inputs specified are valid */
+	if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+		(FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+		(FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+		Status = XST_INVALID_PARAM;
+	} else {
+
+		/*
+		 * Try to set the baud rate and if it's not successful then don't
+		 * continue altering the data format, this is done first to avoid the
+		 * format from being altered when an error occurs
+		 */
+		Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+		if (Status != (s32)XST_SUCCESS) {
+			;
+		} else {
+
+			ModeRegister =
+				XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						  XUARTPS_MR_OFFSET);
+
+			/*
+			 * Set the length of data (8,7,6) by first clearing out the bits
+			 * that control it in the register, then set the length in the register
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+			ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+			/*
+			 * Set the number of stop bits in the mode register by first clearing
+			 * out the bits that control it in the register, then set the number
+			 * of stop bits in the register.
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+			ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+			/*
+			 * Set the parity by first clearing out the bits that control it in the
+			 * register, then set the bits in the register, the default is no parity
+			 * after clearing the register bits
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+			ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+			/* Update the mode register */
+			XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+					   ModeRegister);
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure that will contain
+*		the data format after this call completes.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+	u32 ModeRegister;
+
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FormatPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the baud rate from the instance, this is not retrieved from the
+	 * hardware because it is only kept as a divisor such that it is more
+	 * difficult to get back to the baud rate
+	 */
+	FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Get the length of data (8,7,6,5) */
+	FormatPtr->DataBits =
+		((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+		XUARTPS_MR_CHARLEN_SHIFT);
+
+	/* Get the number of stop bits */
+	FormatPtr->StopBits =
+		(u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+		XUARTPS_MR_STOPMODE_SHIFT);
+
+	/* Determine what parity is */
+	FormatPtr->Parity =
+		(u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+		XUARTPS_MR_PARITY_SHIFT);
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
new file mode 100644
index 0000000..de58201
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*		- XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrRegister;
+	u32 ModeRegister;
+	u8 Index;
+	u32 ReceiveDataResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable all interrupts in the interrupt disable register */
+	IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup for local loopback */
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_MR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+				(u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+	/* Send a number of bytes and receive them, one at a time. */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		/*
+		 * Send out the byte and if it was not sent then the failure
+		 * will be caught in the comparison at the end
+		 */
+		(void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+		/*
+		 * Wait until the byte is received. This can hang if the HW
+		 * is broken. Watch for the FIFO empty flag to be false.
+		 */
+		ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+				XUARTPS_SR_RXEMPTY;
+		while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+			ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+					XUARTPS_SR_RXEMPTY;
+		}
+
+		/* Receive the byte */
+		(void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+	}
+
+	/*
+	 * Compare the bytes received to the bytes sent to verify the exact data
+	 * was received
+	 */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		if (TestString[Index] != ReturnString[Index]) {
+			Status = XST_UART_TEST_FAIL;
+		}
+	}
+
+	/*
+	 * Restore the registers which were altered to put into polling and
+	 * loopback modes so that this test is not destructive
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+			   IntrRegister);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	return Status;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
new file mode 100644
index 0000000..22e2f7a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+* @addtogroup uartps_v3_5
+* @{
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device
+*
+* @return	A pointer to the configuration structure or NULL if the
+*		specified device is not in the system.
+*
+* @note		None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+	XUartPs_Config *CfgPtr = NULL;
+
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+		if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XUartPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XUartPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
new file mode 100644
index 0000000..b76c94a
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c
@@ -0,0 +1,364 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The XUsbPs driver. Functions in this file are the minimum required
+ * functions for this driver. See xusbps.h for a detailed description of the
+ * driver.
+ *
+ * @note	None.
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 2.1   kpc 04/28/14 Removed ununsed functions
+ * 
    
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+#include 
+#include "xusbps.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a XUsbPs instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XUsbPs structure.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	ConfigPtr is a pointer to a XUsbPs_Config configuration
+*		structure. This structure will contain the requested
+*		configuration for the device. Typically, this is a local
+*		structure and the content of which will be copied into the
+*		configuration structure within XUsbPs.
+* @param	VirtBaseAddress is the base address of the device. For systems
+*		with virtual memory, this address must be the virtual address
+*		of the device.
+* 		For systems that do not support virtual memory this address
+* 		should be the physical address of the device. For backwards
+* 		compatibilty NULL may be passed in systems that do not support
+* 		virtual memory (deprecated).
+*
+* @return
+*		- XST_SUCCESS no errors occured.
+*		- XST_FAILURE an error occured during initialization.
+*
+* @note
+*		After calling XUsbPs_CfgInitialize() the controller
+*		IS NOT READY for use. Before the controller can be used its
+*		DEVICE parameters must be configured. See xusbps.h
+*		for details.
+*
+******************************************************************************/
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+			  const XUsbPs_Config *ConfigPtr, u32 VirtBaseAddress)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr   != NULL);
+
+	/* Copy the config structure. */
+	InstancePtr->Config = *ConfigPtr;
+
+	/* Check if the user provided a non-NULL base address. If so, we have
+	 * to overwrite the base address in the configuration structure.
+	 */
+	if (0 != VirtBaseAddress) {
+		InstancePtr->Config.BaseAddress = VirtBaseAddress;
+	}
+
+	/* Initialize the XUsbPs structure to default values. */
+	InstancePtr->CurrentAltSetting	= XUSBPS_DEFAULT_ALT_SETTING;
+
+	InstancePtr->HandlerFunc	= NULL;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function performs device reset, device is stopped at the end.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return	None.
+*
+* @note 	None.
+*
+******************************************************************************/
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr)
+{
+	int Timeout;
+
+	/* Clear all setup token semaphores by reading the
+	 * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+	 * itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPSTAT_OFFSET));
+
+	/* Clear all the endpoint complete status bits by reading the
+	 * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+	 * to itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPCOMPL_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPCOMPL_OFFSET));
+
+	/* Cancel all endpoint prime status by waiting until all bits
+	 * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+	 * to XUSBPS_EPFLUSH_OFFSET.
+	 *
+	 * Avoid hanging here by using a Timeout counter...
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPPRIME_OFFSET) &
+				XUSBPS_EP_ALL_MASK) && --Timeout) {
+		/* NOP */
+	}
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+	XUsbPs_Stop(InstancePtr);
+
+	/* Write to CR register for controller reset */
+ 	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) | XUSBPS_CMD_RST_MASK);
+
+	/* Wait for reset to finish, hardware clears the reset bit once done  */
+	Timeout = 1000000;
+	while((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_RST_MASK) && --Timeout) {
+		/* NOP */
+	}
+}
+/*****************************************************************************/
+/**
+*
+* This function resets the USB device. All the configuration registers are
+* reset to their default values. The function waits until the reset operation
+* is complete or for a certain duration within which the reset operation is
+* expected to be completed.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS Reset operation completed successfully.
+*		- XST_FAILURE Reset operation timed out.
+*
+* @note 	None.
+*
+******************************************************************************/
+int XUsbPs_Reset(XUsbPs *InstancePtr)
+{
+	int Timeout;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Write a 1 to the RESET bit. The RESET bit is cleared by HW once the
+	 * RESET is complete.
+	 *
+	 * We are going to wait for the RESET bit to clear before we return
+	 * from this function. Unfortunately we do not have timers available at
+	 * this point to determine when we should report a Timeout.
+	 *
+	 * However, by using a large number for the poll loop we can assume
+	 * that the polling operation will take longer than the expected time
+	 * the HW needs to RESET. If the poll loop expires we can assume a
+	 * Timeout. The drawback is that on a slow system (and even on a fast
+	 * system) this can lead to _very_ long Timeout periods.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET, XUSBPS_CMD_RST_MASK);
+
+
+	/* Wait for the RESET bit to be cleared by HW. */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_RST_MASK) && --Timeout) {
+		/* NOP */
+	}
+
+	if (0 == Timeout) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+ * USB Suspend
+ *
+ * In order to conserve power, USB devices automatically enter the suspended
+ * state when the device has observed no bus traffic for a specified period.
+ * When suspended, the USB device maintains any internal status, including its
+ * address and configuration. Attached devices must be prepared to suspend at
+ * any time they are powered, regardless of if they have been assigned a
+ * non-default address, are configured, or neither. Bus activity may cease due
+ * to the host entering a suspend mode of its own. In addition, a USB device
+ * shall also enter the suspended state when the hub port it is attached to is
+ * disabled.
+ *
+ * A USB device exits suspend mode when there is bus activity. A USB device may
+ * also request the host to exit suspend mode or selective suspend by using
+ * electrical signaling to indicate remote wakeup. The ability of a device to
+ * signal remote wakeup is optional. If the USB device is capable of remote
+ * wakeup signaling, the device must support the ability of the host to enable
+ * and disable this capability. When the device is reset, remote wakeup
+ * signaling must be disabled.
+ *
+ * @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+ *
+ * @return
+ *		- XST_SUCCESS if the USB device has entered Suspend mode
+ *		successfully
+ *		- XST_FAILURE on any error
+ *
+ * @note 	None.
+ *
+ ******************************************************************************/
+int XUsbPs_Suspend(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Resume
+*
+ If the USB controller is suspended, its operation is resumed when any
+* non-idle signaling is received on its upstream facing port.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS if the USB device has Resumed successfully
+*		- XST_FAILURE on any error
+*
+* @note 	None.
+*
+******************************************************************************/
+int XUsbPs_Resume(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* USB Assert Resume
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+*		- XST_SUCCESS if the USB device has Resumed successfully
+*		- XST_FAILURE on any error
+*
+* @note 	None.
+*
+******************************************************************************/
+
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr)
+{
+	(void) InstancePtr;
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+* This functions sets the controller's DEVICE address. It also sets the
+* advance bit so the controller will wait for the next IN-ACK before the new
+* address takes effect.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	Address is the Address of the device.
+*
+* @return
+*		- XST_SUCCESS: Address set successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_INVALID_PARAM: Invalid parameter passed, e.g. address
+*		value too big.
+*
+* @note 	None.
+*
+*****************************************************************************/
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Check address range validity. */
+	if (Address > XUSBPS_DEVICEADDR_MAX) {
+		return XST_INVALID_PARAM;
+	}
+
+	/* Set the address register with the Address value provided. Also set
+	 * the Address Advance Bit. This will cause the address to be set only
+	 * after an IN occured and has been ACKed on the endpoint.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_DEVICEADDR_OFFSET,
+			 	(Address << XUSBPS_DEVICEADDR_ADDR_SHIFT) |
+			 	XUSBPS_DEVICEADDR_DEVICEAADV_MASK);
+
+	return XST_SUCCESS;
+}
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
new file mode 100644
index 0000000..b5c472e
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h
@@ -0,0 +1,1098 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps.h
+* @addtogroup usbps_v2_4
+* @{
+* @details
+ *
+ * This file contains the implementation of the XUsbPs driver. It is the
+ * driver for an USB controller in DEVICE or HOST mode.
+ *
+ * 
    Introduction
    
+ *
+ * The Spartan-3AF Embedded Peripheral Block contains a USB controller for
+ * communication with serial peripherals or hosts. The USB controller supports
+ * Host, Device and On the Go (OTG) applications.
+ *
+ * 
    USB Controller Features
    
+ *
+ * - Supports Low Speed USB 1.1 (1.5Mbps), Full Speed USB 1.1 (12Mbps), and
+ *   High Speed USB 2.0 (480Mbps) data speeds
+ * - Supports Device, Host and OTG operational modes
+ * - ULPI transceiver interface for USB 2.0 operation
+ * - Integrated USB Full and Low speed serial transceiver interfaces for lowest
+ *   cost connections
+ *
+ * 
    Initialization & Configuration
    
+ *
+ * The configuration of the USB driver happens in multiple stages:
+ *
+ * - (a) Configuration of the basic parameters:
+ *   In this stage the basic parameters for the driver are configured,
+ *   including the base address and the controller ID.
+ *
+ * - (b) Configuration of the DEVICE endpoints (if applicable):
+ *   If DEVICE mode is desired, the endpoints of the controller need to be
+ *   configured using the XUsbPs_DeviceConfig data structure. Once the
+ *   endpoint configuration is set up in the data structure, The user then
+ *   needs to allocate the required amount of DMAable memory and
+ *   finalize the configuration of the XUsbPs_DeviceConfig data structure,
+ *   e.g. setting the DMAMemVirt and DMAMemPhys members.
+ *
+ * - (c) Configuration of the DEVICE modes:
+ *   In the second stage the parameters for DEVICE are configured.
+ *   The caller only needs to configure the modes that are
+ *   actually used. Configuration is done with the:
+ *   	XUsbPs_ConfigureDevice()
+ * Configuration parameters are defined and passed
+ *   into these functions using the:
+ *      XUsbPs_DeviceConfig data structures.
+ *
+ *
+ * 
    USB Device Endpoints
    
+ *
+ * The USB core supports up to 4 endpoints. Each endpoint has two directions,
+ * an OUT (RX) and an IN (TX) direction. Note that the direction is viewed from
+ * the host's perspective. Endpoint 0 defaults to be the control endpoint and
+ * does not need to be set up. Other endpoints need to be configured and set up
+ * depending on the application. Only endpoints that are actuelly used by the
+ * application need to be initialized.
+ * See the example code (xusbps_intr_example.c) for more information.
+ *
+ *
+ * 
    Interrupt Handling
    
+ *
+ * The USB core uses one interrupt line to report interrupts to the CPU.
+ * Interrupts are handled by the driver's interrupt handler function
+ * XUsbPs_IntrHandler().
+ * It has to be registered with the OS's interrupt subsystem. The driver's
+ * interrupt handler divides incoming interrupts into two categories:
+ *
+ *  - General device interrupts
+ *  - Endopint related interrupts
+ *
+ * The user (typically the adapter layer) can register general interrupt
+ * handler fucntions and endpoint specific interrupt handler functions with the
+ * driver to receive those interrupts by calling the
+ *    XUsbPs_IntrSetHandler()
+ * and
+ *    XUsbPs_EpSetHandler()
+ * functions respectively. Calling these functions with a NULL pointer as the
+ * argument for the function pointer will "clear" the handler function.
+ *
+ * The user can register one handler function for the generic interrupts and
+ * two handler functions for each endpoint, one for the RX (OUT) and one for
+ * the TX (IN) direction. For some applications it may be useful to register a
+ * single endpoint handler function for muliple endpoints/directions.
+ *
+ * When a callback function is called by the driver, parameters identifying the
+ * type of the interrupt will be passed into the handler functions. For general
+ * interrupts the interrupt mask will be passed into the handler function. For
+ * endpoint interrupts the parameters include the number of the endpoint, the
+ * direction (OUT/IN) and the type of the interrupt.
+ *
+ *
+ * 
    Data buffer handling
    
+ *
+ * Data buffers are sent to and received from endpoint using the
+ *    XUsbPs_EpBufferSend(), XUsbPs_EpBufferSendWithZLT()
+ * and
+ *    XUsbPs_EpBufferReceive()
+ * functions.
+ *
+ * User data buffer size is limited to 16 Kbytes. If the user wants to send a
+ * data buffer that is bigger than this limit it needs to break down the data
+ * buffer into multiple fragments and send the fragments individually.
+ *
+ * From the controller perspective Data buffers can be aligned at any boundary.
+ * if the buffers are from cache region then the buffer and buffer size should
+ * be aligned to cache line aligned
+ *
+ *
+ * 
    Zero copy
    
+ *
+ * The driver uses a zero copy mechanism which imposes certain restrictions to
+ * the way the user can handle the data buffers.
+ *
+ * One restriction is that the user needs to release a buffer after it is done
+ * processing the data in the buffer.
+ *
+ * Similarly, when the user sends a data buffer it MUST not re-use the buffer
+ * until it is notified by the driver that the buffer has been transmitted. The
+ * driver will notify the user via the registered endpoint interrupt handling
+ * function by sending a XUSBPS_EP_EVENT_DATA_TX event.
+ *
+ *
+ * 
    DMA
    
+ *
+ * The driver uses DMA internally to move data from/to memory. This behaviour
+ * is transparent to the user. Keeping the DMA handling hidden from the user
+ * has the advantage that the same API can be used with USB cores that do not
+ * support DMA.
+ *
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.02a wgr  05/16/12 Removed comments as they are showing up in SDK
+ *		       Tabs for CR 657898
+ * 1.03a nm   09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ *	      11/02/12 Fixed CR# 683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Corrected the setup tripwire macro val.
+ * 2.1   kpc 04/28/14 Removed unused function prototypes
+ * 2.2   kpc 08/23/14 Exported XUsbPs_DeviceReset API as global for calling in
+ *                    code coverage tests.
+ * 2.3   kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper
+ *                    moving of dTD Head/Tail Pointers. Invalidate the cache
+ *                    after buffer receive in Endpoint Buffer Handler.
+ * 2.4   sg  04/26/16 Fixed CR#949693, Corrected the logic for EP flush
+ *       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+ *                    generation.
+ *       ms  04/10/17 Modified filename tag to include the file in doxygen
+ *                    examples.
+ * 
    
+ *
+ ******************************************************************************/
+
+#ifndef XUSBPS_H
+#define XUSBPS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xusbps_hw.h"
+#include "xil_types.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name System hang prevention Timeout counter value.
+ *
+ * This value is used throughout the code to initialize a Timeout counter that
+ * is used when hard polling a register. The ides is to initialize the Timeout
+ * counter to a value that is longer than any expected Timeout but short enough
+ * so the system will continue to work and report an error while the user is
+ * still paying attention. A reasonable Timeout time would be about 10 seconds.
+ * The XUSBPS_TIMEOUT_COUNTER value should be chosen so a polling loop would
+ * run about 10 seconds before a Timeout is detected. For example:
+ *
+ * 	int Timeout = XUSBPS_TIMEOUT_COUNTER;
+ *	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+ *				XUSBPS_CMD_OFFSET) &
+ *				XUSBPS_CMD_RST_MASK) && --Timeout) {
+ *		;
+ *	}
+ *	if (0 == Timeout) {
+ *		return XST_FAILURE;
+ *	}
+ *
+ */
+#define XUSBPS_TIMEOUT_COUNTER		1000000
+
+
+/**
+ * @name Endpoint Direction (bitmask)
+ * Definitions to be used with Endpoint related function that require a
+ * 'Direction' parameter.
+ *
+ * NOTE:
+ *   The direction is always defined from the perspective of the HOST! This
+ *   means that an IN endpoint on the controller is used for sending data while
+ *   the OUT endpoint on the controller is used for receiving data.
+ * @{
+ */
+#define XUSBPS_EP_DIRECTION_IN		0x01 /**< Endpoint direction IN. */
+#define XUSBPS_EP_DIRECTION_OUT		0x02 /**< Endpoint direction OUT. */
+/* @} */
+
+
+/**
+ * @name Endpoint Type
+ * Definitions to be used with Endpoint related functions that require a 'Type'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_TYPE_NONE		0 /**< Endpoint is not used. */
+#define XUSBPS_EP_TYPE_CONTROL		1 /**< Endpoint for Control Transfers */
+#define XUSBPS_EP_TYPE_ISOCHRONOUS 	2 /**< Endpoint for isochronous data */
+#define XUSBPS_EP_TYPE_BULK		3 /**< Endpoint for BULK Transfers. */
+#define XUSBPS_EP_TYPE_INTERRUPT	4 /**< Endpoint for interrupt Transfers */
+/* @} */
+
+/**
+ * Endpoint Max Packet Length in DeviceConfig is a coded value, ch9.6.6.
+ *
+ * @{
+ */
+#define ENDPOINT_MAXP_LENGTH		0x400
+#define ENDPOINT_MAXP_MULT_MASK		0xC00
+#define ENDPOINT_MAXP_MULT_SHIFT	10
+/* @} */
+
+/**
+ * @name Field names for status retrieval
+ * Definitions for the XUsbPs_GetStatus() function call 'StatusType'
+ * parameter.
+ * @{
+ */
+#define XUSBPS_EP_STS_ADDRESS		1 /**< Address of controller. */
+#define XUSBPS_EP_STS_CONTROLLER_STATE	2 /**< Current controller state. */
+/* @} */
+
+
+
+/**
+ * @name USB Default alternate setting
+ *
+ * @{
+ */
+#define XUSBPS_DEFAULT_ALT_SETTING	0 /**< The default alternate setting is 0 */
+/* @} */
+
+/**
+ * @name Endpoint event types
+ * Definitions that are used to identify events that occur on endpoints. Passed
+ * to the endpoint event handler functions registered with
+ * XUsbPs_EpSetHandler().
+ * @{
+ */
+#define XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED	0x01
+			/**< Setup data has been received on the enpoint. */
+#define XUSBPS_EP_EVENT_DATA_RX		0x02
+			/**< Data frame has been received on the endpoint. */
+#define XUSBPS_EP_EVENT_DATA_TX		0x03
+			/**< Data frame has been sent on the endpoint. */
+/* @} */
+
+
+/*
+ * Maximum packet size for endpoint, 1024
+ * @{
+ */
+#define XUSBPS_MAX_PACKET_SIZE		1024
+				/**< Maximum value can be put into the queue head */
+/* @} */
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************
+ * This data type defines the callback function to be used for Endpoint
+ * handlers.
+ *
+ * @param	CallBackRef is the Callback reference passed in by the upper
+ *		layer when setting the handler, and is passed back to the upper
+ *		layer when the handler is called.
+ * @param	EpNum is the Number of the endpoint that caused the event.
+ * @param	EventType is the type of the event that occured on the endpoint.
+ * @param	Data is a pointer to user data pointer specified when callback
+ *		was registered.
+ */
+typedef void (*XUsbPs_EpHandlerFunc)(void *CallBackRef,
+				      u8 EpNum, u8 EventType, void *Data);
+
+
+/******************************************************************************
+ * This data type defines the callback function to be used for the general
+ * interrupt handler.
+ *
+ * @param	CallBackRef is the Callback reference passed in by the upper
+ *		layer when setting the handler, and is passed back to the upper
+ *		layer when the handler is called.
+ * @param	IrqMask is the Content of the interrupt status register. This
+ *		value can be used by the callback function to distinguish the
+ *		individual interrupt types.
+ */
+typedef void (*XUsbPs_IntrHandlerFunc)(void *CallBackRef, u32 IrqMask);
+
+
+/******************************************************************************/
+
+/* The following type definitions are used for referencing Queue Heads and
+ * Transfer Descriptors. The structures themselves are not used, however, the
+ * types are used in the API to avoid using (void *) pointers.
+ */
+typedef u8	XUsbPs_dQH[XUSBPS_dQH_ALIGN];
+typedef u8	XUsbPs_dTD[XUSBPS_dTD_ALIGN];
+
+
+/**
+ * The following data structures are used internally by the L0/L1 driver.
+ * Their contents MUST NOT be changed by the upper layers.
+ */
+
+/**
+ * The following data structure represents OUT endpoint.
+ */
+typedef struct {
+	XUsbPs_dQH	*dQH;
+		/**< Pointer to the Queue Head structure of the endpoint. */
+
+	XUsbPs_dTD	*dTDs;
+		/**< Pointer to the first dTD of the dTD list for this
+		 * endpoint. */
+
+	XUsbPs_dTD	*dTDCurr;
+		/**< Buffer to the currently processed descriptor. */
+
+	u8	*dTDBufs;
+		/**< Pointer to the first buffer of the buffer list for this
+		 * endpoint. */
+
+	XUsbPs_EpHandlerFunc	HandlerFunc;
+		/**< Handler function for this endpoint. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+} XUsbPs_EpOut;
+
+
+/**
+ * The following data structure represents IN endpoint.
+ */
+typedef struct {
+	XUsbPs_dQH	*dQH;
+		/**< Pointer to the Queue Head structure of the endpoint. */
+
+	XUsbPs_dTD	*dTDs;
+		/**< List of pointers to the Transfer Descriptors of the
+		 * endpoint. */
+
+	XUsbPs_dTD	*dTDHead;
+		/**< Buffer to the next available descriptor in the list. */
+
+	XUsbPs_dTD	*dTDTail;
+		/**< Buffer to the last unsent descriptor in the list*/
+
+	XUsbPs_EpHandlerFunc	HandlerFunc;
+		/**< Handler function for this endpoint. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+} XUsbPs_EpIn;
+
+
+/**
+ * The following data structure represents an endpoint used internally
+ * by the L0/L1 driver.
+ */
+typedef struct {
+	/* Each endpoint has an OUT and an IN component.
+	 */
+	XUsbPs_EpOut	Out;	/**< OUT endpoint structure */
+	XUsbPs_EpIn	In;	/**< IN endpoint structure */
+} XUsbPs_Endpoint;
+
+
+
+/**
+ * The following structure is used by the user to receive Setup Data from an
+ * endpoint. Using this structure simplifies the process of interpreting the
+ * setup data in the core's data fields.
+ *
+ * The naming scheme for the members of this structure is different from the
+ * naming scheme found elsewhere in the code. The members of this structure are
+ * defined in the Chapter 9 USB reference guide. Using this naming scheme makes
+ * it easier for people familiar with the standard to read the code.
+ */
+typedef struct {
+	u8  bmRequestType;	/**< bmRequestType in setup data */
+	u8  bRequest;		/**< bRequest in setup data */
+	u16 wValue;		/**< wValue in setup data */
+	u16 wIndex;		/**< wIndex in setup data */
+	u16 wLength;		/**< wLength in setup data */
+}
+XUsbPs_SetupData;
+
+
+/**
+ * Data structures used to configure endpoints.
+ */
+typedef struct {
+	u32	Type;
+		/**< Endpoint type:
+			- XUSBPS_EP_TYPE_CONTROL
+			- XUSBPS_EP_TYPE_ISOCHRONOUS
+			- XUSBPS_EP_TYPE_BULK
+			- XUSBPS_EP_TYPE_INTERRUPT */
+
+	u32	NumBufs;
+		/**< Number of buffers to be handled by this endpoint. */
+	u32	BufSize;
+		/**< Buffer size. Only relevant for OUT (receive) Endpoints. */
+
+	u16	MaxPacketSize;
+		/**< Maximum packet size for this endpoint. This number will
+		 * define the maximum number of bytes sent on the wire per
+		 * transaction. Range: 0..1024 */
+} XUsbPs_EpSetup;
+
+
+/**
+ * Endpoint configuration structure.
+ */
+typedef struct {
+	XUsbPs_EpSetup		Out; /**< OUT component of endpoint. */
+	XUsbPs_EpSetup		In;  /**< IN component of endpoint. */
+} XUsbPs_EpConfig;
+
+
+/**
+ * The XUsbPs_DeviceConfig structure contains the configuration information to
+ * configure the USB controller for DEVICE mode. This data structure is used
+ * with the XUsbPs_ConfigureDevice() function call.
+ */
+typedef struct {
+	u8  NumEndpoints;	/**< Number of Endpoints for the controller.
+				  This number depends on the runtime
+				  configuration of driver. The driver may
+				  configure fewer endpoints than are available
+				  in the core. */
+
+	XUsbPs_EpConfig	EpCfg[XUSBPS_MAX_ENDPOINTS];
+				/**< List of endpoint configurations. */
+
+
+	u32 DMAMemPhys;		/**< Physical base address of DMAable memory
+				  allocated for the driver. */
+
+	/* The following members are used internally by the L0/L1 driver.  They
+	 * MUST NOT be accesses and/or modified in any way by the upper layers.
+	 *
+	 * The reason for having these members is that we generally try to
+	 * avoid allocating memory in the L0/L1 driver as we want to be OS
+	 * independent. In order to avoid allocating memory for this data
+	 * structure wihin L0/L1 we put it into the XUsbPs_DeviceConfig
+	 * structure which is allocated by the caller.
+	 */
+	XUsbPs_Endpoint	Ep[XUSBPS_MAX_ENDPOINTS];
+				/**< List of endpoint metadata structures. */
+
+	u32 PhysAligned;	/**< 64 byte aligned base address of the DMA
+				   memory block. Will be computed and set by
+				   the L0/L1 driver. */
+} XUsbPs_DeviceConfig;
+
+
+/**
+ * The XUsbPs_Config structure contains configuration information for the USB
+ * controller.
+ *
+ * This structure only contains the basic configuration for the controller. The
+ * caller also needs to initialize the controller for the DEVICE mode
+ * using the XUsbPs_DeviceConfig data structures with the
+ * XUsbPs_ConfigureDevice() function call
+ */
+typedef struct {
+	u16 DeviceID;		/**< Unique ID of controller. */
+	u32 BaseAddress;	/**< Core register base address. */
+} XUsbPs_Config;
+
+
+/**
+ * The XUsbPs driver instance data. The user is required to allocate a
+ * variable of this type for every USB controller in the system. A pointer to a
+ * variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XUsbPs_Config Config;	/**< Configuration structure */
+
+	int CurrentAltSetting;	/**< Current alternative setting of interface */
+
+	void *UserDataPtr;	/**< Data pointer to be used by upper layers to
+				  store application dependent data structures.
+				  The upper layers are responsible to allocated
+				  and free the memory. The driver will not
+				  mofidy this data pointer. */
+
+	/**
+	 * The following structures hold the configuration for DEVICE mode
+	 * of the controller. They are initialized using the
+	 * XUsbPs_ConfigureDevice() function call.
+	 */
+	XUsbPs_DeviceConfig	DeviceConfig;
+				/**< Configuration for the DEVICE mode. */
+
+	XUsbPs_IntrHandlerFunc	HandlerFunc;
+		/**< Handler function for the controller. */
+	void			*HandlerRef;
+		/**< User data reference for the handler. */
+	u32			HandlerMask;
+		/**< User interrupt mask. Defines which interrupts will cause
+		 * the callback to be called. */
+} XUsbPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/******************************************************************************
+ *
+ * USB CONTROLLER RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ * This macro returns the current frame number.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @return	The current frame number.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_GetFrameNum(const XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_GetFrameNum(InstancePtr) \
+	XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, XUSBPS_FRAME_OFFSET)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB engine.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_Start(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Start(InstancePtr) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro stops the USB engine.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_Stop(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_Stop(InstancePtr) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET, XUSBPS_CMD_RS_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro forces the USB engine to be in Full Speed (FS) mode.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ *
+ * @note	C-style signature:
+ * 		void XUsbPs_ForceFS(XUsbPs *InstancePtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_ForceFS(InstancePtr)					\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET,		\
+ 		XUSBPS_PORTSCR_PFSC_MASK)
+
+
+/*****************************************************************************/
+/**
+ * This macro starts the USB Timer 0, with repeat option for period of
+ * one second.
+ *
+ * @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+ * @param	Interval is the interval for Timer0 to generate an interrupt
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_StartTimer0(XUsbPs *InstancePtr, u32 Interval)
+ *
+ ******************************************************************************/
+#define XUsbPs_StartTimer0(InstancePtr, Interval) 			\
+{									\
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, 		\
+			XUSBPS_TIMER0_LD_OFFSET, (Interval));		\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET,		\
+			XUSBPS_TIMER_RUN_MASK |			\
+			XUSBPS_TIMER_RESET_MASK |			\
+			XUSBPS_TIMER_REPEAT_MASK);			\
+}									\
+
+
+/*****************************************************************************/
+/**
+* This macro stops Timer 0.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_StopTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_StopTimer0(InstancePtr) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_TIMER0_CTL_OFFSET,		\
+		XUSBPS_TIMER_RUN_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro reads Timer 0.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_ReadTimer0(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ReadTimer0(InstancePtr) 				\
+	XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress,		\
+			XUSBPS_TIMER0_CTL_OFFSET) & 			\
+					XUSBPS_TIMER_COUNTER_MASK
+
+
+/*****************************************************************************/
+/**
+* This macro force remote wakeup on host
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*  		void XUsbPs_RemoteWakeup(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_RemoteWakeup(InstancePtr) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_PORTSCR1_OFFSET,		 \
+			XUSBPS_PORTSCR_FPR_MASK)
+
+
+/******************************************************************************
+ *
+ * ENDPOINT RELATED MACROS
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+* This macro enables the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is number of the endpoint to enable.
+* @param	Dir is direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpEnable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpEnable(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro disables the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to disable.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 		- XUSBPS_EP_DIRECTION_OUT
+* 		- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpDisable(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpDisable(InstancePtr, EpNum, Dir) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),		 \
+		((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXE_MASK : 0) | \
+		((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXE_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro stalls the given endpoint for the given direction, and flush
+* the buffers.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is number of the endpoint to stall.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+*		void XUsbPs_EpStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpStall(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro unstalls the given endpoint for the given direction.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the Number of the endpoint to unstall.
+* @param	Dir is the Direction of the endpoint (bitfield):
+* 		- XUSBPS_EP_DIRECTION_OUT
+* 		- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+* 		void XUsbPs_EpUnStall(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpUnStall(InstancePtr, EpNum, Dir) \
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPCRn_OFFSET(EpNum),	 \
+	((Dir) & XUSBPS_EP_DIRECTION_OUT ? XUSBPS_EPCR_RXS_MASK : 0) | \
+	((Dir) & XUSBPS_EP_DIRECTION_IN  ? XUSBPS_EPCR_TXS_MASK : 0))
+
+
+/*****************************************************************************/
+/**
+* This macro flush an endpoint upon interface disable
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to flush.
+* @param	Dir is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @note		C-style signature:
+*		void XUsbPs_EpFlush(XUsbPs *InstancePtr, u8 EpNum, u8 Dir)
+*
+******************************************************************************/
+#define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET,	\
+		1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ?		\
+			XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \
+
+/*****************************************************************************/
+/**
+* This macro enables the interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	IntrMask is the Bit mask of interrupts to be enabled.
+*
+* @note		C-style signature:
+*		void XUsbPs_IntrEnable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrEnable(InstancePtr, IntrMask)	\
+		XUsbPs_SetBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function disables the interrupts defined by the bit mask.
+*
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	IntrMask is a Bit mask of interrupts to be disabled.
+*
+* @note		C-style signature:
+* 		void XUsbPs_IntrDisable(XUsbPs *InstancePtr, u32 IntrMask)
+*
+******************************************************************************/
+#define XUsbPs_IntrDisable(InstancePtr, IntrMask)	\
+		XUsbPs_ClrBits(InstancePtr, XUSBPS_IER_OFFSET, IntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro enables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is the Bit mask of endpoint NAK interrupts to be
+*		enabled.
+* @note		C-style signature:
+* 		void XUsbPs_NakIntrEnable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrEnable(InstancePtr, NakIntrMask)	\
+	XUsbPs_SetBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This macro disables the endpoint NAK interrupts defined by the bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is a Bit mask of endpoint NAK interrupts to be
+*		disabled.
+*
+* @note
+* 	C-style signature:
+* 	void XUsbPs_NakIntrDisable(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrDisable(InstancePtr, NakIntrMask)	\
+	XUsbPs_ClrBits(InstancePtr, XUSBPS_EPNAKIER_OFFSET, NakIntrMask)
+
+
+/*****************************************************************************/
+/**
+* This function clears the endpoint NAK interrupts status defined by the
+* bit mask.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	NakIntrMask is the Bit mask of endpoint NAK interrupts to be cleared.
+*
+* @note		C-style signature:
+* 		void XUsbPs_NakIntrClear(XUsbPs *InstancePtr, u32 NakIntrMask)
+*
+******************************************************************************/
+#define XUsbPs_NakIntrClear(InstancePtr, NakIntrMask)			\
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+				XUSBPS_EPNAKISR_OFFSET, NakIntrMask)
+
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Interrupt Threshold value in the control register
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	Threshold is the Interrupt threshold to be set.
+* 		Allowed values:
+*			- XUSBPS_CMD_ITHRESHOLD_0 - Immediate interrupt
+*			- XUSBPS_CMD_ITHRESHOLD_1 - 1 Frame
+*			- XUSBPS_CMD_ITHRESHOLD_2 - 2 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_4 - 4 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_8 - 8 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_16 - 16 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_32 - 32 Frames
+*			- XUSBPS_CMD_ITHRESHOLD_64 - 64 Frames
+*
+* @note
+* 	C-style signature:
+*	void XUsbPs_SetIntrThreshold(XUsbPs *InstancePtr, u8 Threshold)
+*
+******************************************************************************/
+#define XUsbPs_SetIntrThreshold(InstancePtr, Threshold)		\
+		XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress,	\
+					XUSBPS_CMD_OFFSET, (Threshold))\
+
+
+/*****************************************************************************/
+/**
+* This macro sets the Tripwire bit in the USB command register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_SetTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetSetupTripwire(InstancePtr)				\
+		XUsbPs_SetBits(InstancePtr, XUSBPS_CMD_OFFSET,	\
+				XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro clears the Tripwire bit in the USB command register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @note		C-style signature:
+*		void XUsbPs_ClrTripwire(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_ClrSetupTripwire(InstancePtr)				\
+		XUsbPs_ClrBits(InstancePtr, XUSBPS_CMD_OFFSET,	\
+				XUSBPS_CMD_SUTW_MASK)
+
+
+/*****************************************************************************/
+/**
+* This macro checks if the Tripwire bit in the USB command register is set.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+*
+* @return
+* 		- TRUE: The tripwire bit is still set.
+* 		- FALSE: The tripwire bit has been cleared.
+*
+* @note		C-style signature:
+*		int XUsbPs_TripwireIsSet(XUsbPs *InstancePtr)
+*
+******************************************************************************/
+#define XUsbPs_SetupTripwireIsSet(InstancePtr)				\
+		(XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+				XUSBPS_CMD_OFFSET) &			\
+				XUSBPS_CMD_SUTW_MASK ? TRUE : FALSE)
+
+
+/******************************************************************************
+*
+* GENERAL REGISTER / BIT MANIPULATION MACROS
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* This macro sets the given bit mask in the register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	RegOffset is the register offset to be written.
+* @param	Bits is the Bits to be set in the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XUsbPs_SetBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_SetBits(InstancePtr, RegOffset, Bits) \
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset,	\
+		XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+					RegOffset) | (Bits));
+
+
+/****************************************************************************/
+/**
+*
+* This macro clears the given bits in the register.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	RegOffset is the register offset to be written.
+* @param	Bits are the bits to be cleared in the register
+*
+* @return	None.
+*
+* @note
+* 	C-style signature:
+*	void XUsbPs_ClrBits(u32 BaseAddress, u32 RegOffset, u32 Bits)
+*
+*****************************************************************************/
+#define XUsbPs_ClrBits(InstancePtr, RegOffset, Bits) \
+	XUsbPs_WriteReg((InstancePtr)->Config.BaseAddress, RegOffset,	\
+		XUsbPs_ReadReg((InstancePtr)->Config.BaseAddress, 	\
+				RegOffset) & ~(Bits));
+
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * Setup / Initialize functions.
+ *
+ * Implemented in file xusbps.c
+ */
+int XUsbPs_CfgInitialize(XUsbPs *InstancePtr,
+			  const XUsbPs_Config *ConfigPtr, u32 BaseAddress);
+
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+				const XUsbPs_DeviceConfig *CfgPtr);
+
+/**
+ * Common functions used for DEVICE/HOST mode.
+ */
+int XUsbPs_Reset(XUsbPs *InstancePtr);
+
+void XUsbPs_DeviceReset(XUsbPs *InstancePtr);
+
+/**
+ * DEVICE mode specific functions.
+ */
+int XUsbPs_BusReset(XUsbPs *InstancePtr);
+int XUsbPs_SetDeviceAddress(XUsbPs *InstancePtr, u8 Address);
+
+
+/**
+ * Handling Suspend and Resume.
+ *
+ * Implemented in xusbps.c
+ */
+int XUsbPs_Suspend(const XUsbPs *InstancePtr);
+int XUsbPs_Resume(const XUsbPs *InstancePtr);
+int XUsbPs_RequestHostResume(const XUsbPs *InstancePtr);
+
+
+/*
+ * Functions for managing Endpoints / Transfers
+ *
+ * Implemented in file xusbps_endpoint.c
+ */
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+			const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+			const u8 *BufferPtr, u32 BufferLen);
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+			u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle);
+void XUsbPs_EpBufferRelease(u32 Handle);
+
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+			XUsbPs_EpHandlerFunc CallBackFunc,
+			void *CallBackRef);
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+			XUsbPs_SetupData *SetupDataPtr);
+
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction);
+
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+			int EpNum, unsigned short NewDirection, int DirectionChanged);
+
+/*
+ * Interrupt handling functions
+ *
+ * Implemented in file xusbps_intr.c
+ */
+void XUsbPs_IntrHandler(void *InstancePtr);
+
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+			   XUsbPs_IntrHandlerFunc CallBackFunc,
+			   void *CallBackRef, u32 Mask);
+/*
+ * Helper functions for static configuration.
+ * Implemented in xusbps_sinit.c
+ */
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
new file mode 100644
index 0000000..7b16d22
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c
@@ -0,0 +1,1454 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_endpoint.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * Endpoint specific function implementations.
+ *
+ * @note     None.
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 1.03a nm  09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 1.04a nm  11/02/12 Fixed CR#683931. Mult bits are set properly in dQH.
+ * 2.00a kpc 04/03/14 Fixed CR#777763. Updated the macro names 
+ * 2.1   kpc 04/28/14 Added XUsbPs_EpBufferSendWithZLT api and merged common
+ *		      code to XUsbPs_EpQueueRequest.
+ * 2.3   bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
+ *            (moving of dTD Head/Tail Pointers)and CR#873974(invalidate
+ *            Caches After Buffer Receive in Endpoint Buffer Handler...)
+ * 
    
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include  /* for bzero() */
+#include 
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes ******************************/
+
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int  XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr);
+static int  XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+					const u8 *BufferPtr, u32 BufferLen);
+
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len);
+
+/* Functions to reconfigure endpoint upon host's set alternate interface
+ * request.
+ */
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+					int EpNum, unsigned short NewDirection);
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+					int EpNum, unsigned short NewDirection);
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen, u8 ReqZero);
+
+/******************************* Functions ************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * This function configures the DEVICE side of the controller. The caller needs
+ * to pass in the desired configuration (e.g. number of endpoints) and a
+ * DMAable buffer that will hold the Queue Head List and the Transfer
+ * Descriptors. The required size for this buffer can be obtained by the caller
+ * using the: XUsbPs_DeviceMemRequired() macro.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	CfgPtr is a pointer to the configuration structure that contains
+ *		the desired DEVICE side configuration.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ * @note
+ * 		The caller may configure the controller for both, DEVICE and
+ * 		HOST side.
+ *
+ ******************************************************************************/
+int XUsbPs_ConfigureDevice(XUsbPs *InstancePtr,
+			    const XUsbPs_DeviceConfig *CfgPtr)
+{
+	int	Status;
+	u32 ModeValue = 0x0;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr      != NULL);
+
+	/* Copy the configuration data over into the local instance structure */
+	InstancePtr->DeviceConfig = *CfgPtr;
+
+
+	/* Align the buffer to a 2048 byte (XUSBPS_dQH_BASE_ALIGN) boundary.*/
+	InstancePtr->DeviceConfig.PhysAligned =
+		(InstancePtr->DeviceConfig.DMAMemPhys +
+					 XUSBPS_dQH_BASE_ALIGN) &
+						~(XUSBPS_dQH_BASE_ALIGN -1);
+
+	/* Initialize the endpoint pointer list data structure. */
+	XUsbPs_EpListInit(&InstancePtr->DeviceConfig);
+
+
+	/* Initialize the Queue Head structures in DMA memory. */
+	XUsbPs_dQHInit(&InstancePtr->DeviceConfig);
+
+
+	/* Initialize the Transfer Descriptors in DMA memory.*/
+	Status = XUsbPs_dTDInit(&InstancePtr->DeviceConfig);
+	if (XST_SUCCESS != Status) {
+		return XST_FAILURE;
+	}
+
+	/* Changing the DEVICE mode requires a controller RESET. */
+	if (XST_SUCCESS != XUsbPs_Reset(InstancePtr)) {
+		return XST_FAILURE;
+	}
+
+	/* Set the Queue Head List address. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPLISTADDR_OFFSET,
+				InstancePtr->DeviceConfig.PhysAligned);
+
+	/* Set the USB mode register to configure DEVICE mode.
+	 *
+	 * XUSBPS_MODE_SLOM_MASK note:
+	 *   Disable Setup Lockout. Setup Lockout is not required as we
+	 *   will be using the tripwire mechanism when handling setup
+	 *   packets.
+	 */
+	ModeValue = XUSBPS_MODE_CM_DEVICE_MASK | XUSBPS_MODE_SLOM_MASK;
+
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_MODE_OFFSET, ModeValue);
+
+	XUsbPs_SetBits(InstancePtr, XUSBPS_OTGCSR_OFFSET,
+				XUSBPS_OTGSC_OT_MASK);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSend(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen)
+{
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+					BufferLen, FALSE);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also zero length packet if the
+* Bufferlen is in multiples of endpoint max packet size.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+int XUsbPs_EpBufferSendWithZLT(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen)
+{
+	u8 ReqZero = FALSE;
+	XUsbPs_EpSetup *Ep;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.EpCfg[EpNum].In;
+
+	if ((BufferLen >= Ep->MaxPacketSize) &&
+		(BufferLen % Ep->MaxPacketSize == 0)) {
+		ReqZero = TRUE;
+	}
+
+	return XUsbPs_EpQueueRequest(InstancePtr, EpNum, BufferPtr,
+						BufferLen, ReqZero);
+}
+
+/*****************************************************************************/
+/**
+* This function sends a given data buffer and also sends ZLT packet if it is
+* requested.
+*
+* @param	InstancePtr is a pointer to XUsbPs instance of the controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	BufferPtr is a pointer to the buffer to send.
+* @param	BufferLen is the Buffer length.
+* @param	ReqZero is the
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_USB_BUF_TOO_BIG: Provided buffer is too big (>16kB).
+*		- XST_USB_NO_DESC_AVAILABLE: No TX descriptor is available.
+*
+******************************************************************************/
+static int XUsbPs_EpQueueRequest(XUsbPs *InstancePtr, u8 EpNum,
+				const u8 *BufferPtr, u32 BufferLen, u8 ReqZero)
+{
+	int		Status;
+	u32		Token;
+	XUsbPs_EpIn	*Ep;
+	XUsbPs_dTD	*DescPtr;
+	u32 		Length;
+	u32		PipeEmpty = 1;
+	u32		Mask = 0x00010000;
+	u32		BitMask = Mask << EpNum;
+	u32		RegValue;
+	u32		Temp;
+	u32 exit = 1;
+
+
+	/* Locate the next available buffer in the ring. A buffer is available
+	 * if its descriptor is not active.
+	 */
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].In;
+
+	Xil_DCacheFlushRange((unsigned int)BufferPtr, BufferLen);
+
+	if(Ep->dTDTail != Ep->dTDHead) {
+		PipeEmpty = 0;
+	}
+	XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+	/* Tell the caller if we do not have any descriptors available. */
+	if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+		return XST_USB_NO_DESC_AVAILABLE;
+	}
+
+	/* Remember the current head. */
+	DescPtr = Ep->dTDHead;
+
+	do {
+
+		/* Tell the caller if we do not have any descriptors available. */
+		if (XUsbPs_dTDIsActive(Ep->dTDHead)) {
+			return XST_USB_NO_DESC_AVAILABLE;
+		}
+
+		Length = (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) ? XUSBPS_dTD_BUF_MAX_SIZE : BufferLen;
+		/* Attach the provided buffer to the current descriptor.*/
+		Status = XUsbPs_dTDAttachBuffer(Ep->dTDHead, BufferPtr, Length);
+		if (XST_SUCCESS != Status) {
+			return XST_FAILURE;
+		}
+		BufferLen -= Length;
+		BufferPtr += Length;
+
+		XUsbPs_dTDSetActive(Ep->dTDHead);
+		if (BufferLen == 0 && (ReqZero == FALSE)) {
+			XUsbPs_dTDSetIOC(Ep->dTDHead);
+			exit = 0;
+		}
+		XUsbPs_dTDClrTerminate(Ep->dTDHead);
+		XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+		/* Advance the head descriptor pointer to the next descriptor. */
+		Ep->dTDHead = XUsbPs_dTDGetNLP(Ep->dTDHead);
+		/* Terminate the next descriptor and flush the cache.*/
+		XUsbPs_dTDInvalidateCache(Ep->dTDHead);
+
+		if (ReqZero && BufferLen == 0) {
+			ReqZero = FALSE;
+		}
+
+	} while(BufferLen || exit);
+
+	XUsbPs_dTDSetTerminate(Ep->dTDHead);
+	XUsbPs_dTDFlushCache(Ep->dTDHead);
+
+	if(!PipeEmpty) {
+		/* Read the endpoint prime register. */
+		RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPPRIME_OFFSET);
+		if(RegValue & BitMask) {
+			return XST_SUCCESS;
+		}
+
+		do {
+			RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+			XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+						RegValue | XUSBPS_CMD_ATDTW_MASK);
+			Temp = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_EPRDY_OFFSET)
+						& BitMask;
+		} while(!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET) &
+				XUSBPS_CMD_ATDTW_MASK));
+
+		RegValue = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET);
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_CMD_OFFSET,
+					RegValue & ~XUSBPS_CMD_ATDTW_MASK);
+
+		if(Temp) {
+			return XST_SUCCESS;
+		}
+	}
+
+	/* Check, if the DMA engine is still running. If it is running, we do
+	 * not clear Queue Head fields.
+	 *
+	 * Same cache rule as for the Transfer Descriptor applies for the Queue
+	 * Head.
+	 */
+	XUsbPs_dQHInvalidateCache(Ep->dQH);
+	/* Add the dTD to the dQH */
+	XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDNLP, DescPtr);
+	Token = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHdTDTOKEN);
+	Token &= ~(XUSBPS_dTDTOKEN_ACTIVE_MASK | XUSBPS_dTDTOKEN_HALT_MASK);
+	XUsbPs_WritedQH(Ep->dQH, XUSBPS_dQHdTDTOKEN, Token);
+
+	XUsbPs_dQHFlushCache(Ep->dQH);
+
+	Status = XUsbPs_EpPrime(InstancePtr, EpNum, XUSBPS_EP_DIRECTION_IN);
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * This function receives a data buffer from the endpoint of the given endpoint
+ * number.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	EpNum is the number of the endpoint to receive data from.
+ * @param	BufferPtr (OUT param) is a pointer to the buffer pointer to hold
+ *		the reference of the data buffer.
+ * @param	BufferLenPtr (OUT param) is a pointer to the integer that will
+ *		hold the buffer length.
+ * @param	Handle is the opaque handle to be used when the buffer is
+ *		released.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_USB_NO_BUF: No buffer available.
+ *
+ * @note
+ * 		After handling the data in the buffer, the user MUST release
+ * 		the buffer using the Handle by calling the
+ * 		XUsbPs_EpBufferRelease() function.
+ *
+ ******************************************************************************/
+int XUsbPs_EpBufferReceive(XUsbPs *InstancePtr, u8 EpNum,
+				u8 **BufferPtr, u32 *BufferLenPtr, u32 *Handle)
+{
+	XUsbPs_EpOut	*Ep;
+	XUsbPs_EpSetup	*EpSetup;
+	u32 length = 0;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(BufferPtr    != NULL);
+	Xil_AssertNonvoid(BufferLenPtr != NULL);
+	Xil_AssertNonvoid(Handle       != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	/* Locate the next available buffer in the ring. A buffer is available
+	 * if its descriptor is not active.
+	 */
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+	XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+	if (XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+		return XST_USB_NO_BUF;
+	}
+
+	/* The buffer is not active which means that it has been processed by
+	 * the DMA engine and contains valid data.
+	 */
+	EpSetup = &InstancePtr->DeviceConfig.EpCfg[EpNum].Out;
+
+
+	/* Use the buffer pointer stored in the "user data" field of the
+	 * Transfer Descriptor.
+	 */
+	*BufferPtr = (u8 *) XUsbPs_ReaddTD(Ep->dTDCurr,
+						XUSBPS_dTDUSERDATA);
+
+	length = EpSetup->BufSize -
+			XUsbPs_dTDGetTransferLen(Ep->dTDCurr);
+
+	if(length > 0) {
+		*BufferLenPtr = length;
+	}else {
+		*BufferLenPtr = 0;
+	}
+
+	*Handle	= (u32) Ep->dTDCurr;
+
+
+	/* Reset the descriptor's BufferPointer0 and Transfer Length fields to
+	 * their original value. Note that we can not yet re-activate the
+	 * descriptor as the caller will be using the attached buffer. Once the
+	 * caller releases the buffer by calling XUsbPs_EpBufferRelease(), we
+	 * can re-activate the descriptor.
+	 */
+	XUsbPs_WritedTD(Ep->dTDCurr, XUSBPS_dTDBPTR0, *BufferPtr);
+	XUsbPs_dTDSetTransferLen(Ep->dTDCurr, EpSetup->BufSize);
+
+	XUsbPs_dTDFlushCache(Ep->dTDCurr);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function returns a previously received data buffer to the driver.
+*
+* @param	Handle is a pointer to the buffer that is returned.
+*
+* @return	None.
+*
+******************************************************************************/
+void XUsbPs_EpBufferRelease(u32 Handle)
+{
+	XUsbPs_dTD		*dTDPtr;
+
+	/* Perform sanity check on Handle.*/
+	Xil_AssertVoid((0 != Handle) && (0 == (Handle % XUSBPS_dTD_ALIGN)));
+
+	/* Activate the descriptor and clear the Terminate bit. Make sure to do
+	 * the proper cache handling.
+	 */
+	dTDPtr = (XUsbPs_dTD *) Handle;
+
+	XUsbPs_dTDInvalidateCache(dTDPtr);
+
+	XUsbPs_dTDClrTerminate(dTDPtr);
+	XUsbPs_dTDSetActive(dTDPtr);
+	XUsbPs_dTDSetIOC(dTDPtr);
+
+	XUsbPs_dTDFlushCache(dTDPtr);
+
+}
+
+
+/*****************************************************************************/
+/**
+ * This function sets the handler for endpoint events.
+ *
+ * @param	InstancePtr is a pointer to the XUsbPs instance of the
+ *		controller.
+ * @param	EpNum is the number of the endpoint to receive data from.
+ * @param	Direction is the direction of the endpoint (bitfield):
+ * 			- XUSBPS_EP_DIRECTION_OUT
+ * 			- XUSBPS_EP_DIRECTION_IN
+ * @param	CallBackFunc is the Handler callback function.
+ *		Can be NULL if the user wants to disable the handler entry.
+ * @param	CallBackRef is the user definable data pointer that will be
+ *		passed back if the handler is called. May be NULL.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_INVALID_PARAM: Invalid parameter passed.
+ *
+ * @note
+ * 		The user can disable a handler by setting the callback function
+ * 		pointer to NULL.
+ *
+ ******************************************************************************/
+int XUsbPs_EpSetHandler(XUsbPs *InstancePtr, u8 EpNum, u8 Direction,
+			 XUsbPs_EpHandlerFunc CallBackFunc,
+			 void *CallBackRef)
+{
+	XUsbPs_Endpoint	*Ep;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(CallBackFunc != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum];
+
+	if(Direction & XUSBPS_EP_DIRECTION_OUT) {
+		Ep->Out.HandlerFunc	= CallBackFunc;
+		Ep->Out.HandlerRef	= CallBackRef;
+	}
+
+	if(Direction & XUSBPS_EP_DIRECTION_IN) {
+		Ep->In.HandlerFunc	= CallBackFunc;
+		Ep->In.HandlerRef	= CallBackRef;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function primes an endpoint.
+*
+* @param	InstancePtr is pointer to the XUsbPs instance.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	Direction is the direction of the endpoint (bitfield):
+* 			- XUSBPS_EP_DIRECTION_OUT
+* 			- XUSBPS_EP_DIRECTION_IN
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*		- XST_INVALID_PARAM: Invalid parameter passed.
+*
+* @note		None.
+*
+******************************************************************************/
+int XUsbPs_EpPrime(XUsbPs *InstancePtr, u8 EpNum, u8 Direction)
+{
+	u32	Mask;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	/* Get the right bit mask for the endpoint direction. */
+	switch (Direction) {
+
+	case XUSBPS_EP_DIRECTION_OUT:
+		Mask = 0x00000001;
+		break;
+
+	case XUSBPS_EP_DIRECTION_IN:
+		Mask = 0x00010000;
+		break;
+
+	default:
+		return XST_INVALID_PARAM;
+	}
+
+	/* Write the endpoint prime register. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPPRIME_OFFSET, Mask << EpNum);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function extracts the Setup Data from a given endpoint.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpNum is the number of the endpoint to receive data from.
+* @param	SetupDataPtr is a pointer to the setup data structure to be
+*		filled.
+*
+* @return
+*		- XST_SUCCESS: The operation completed successfully.
+*		- XST_FAILURE: An error occured.
+*
+* @note		None.
+******************************************************************************/
+int XUsbPs_EpGetSetupData(XUsbPs *InstancePtr, int EpNum,
+				XUsbPs_SetupData *SetupDataPtr)
+{
+	XUsbPs_EpOut	*Ep;
+
+	u32	Data[2];
+	u8	*p;
+
+	int Timeout;
+
+	Xil_AssertNonvoid(InstancePtr  != NULL);
+	Xil_AssertNonvoid(SetupDataPtr != NULL);
+	Xil_AssertNonvoid(EpNum < InstancePtr->DeviceConfig.NumEndpoints);
+
+	Ep = &InstancePtr->DeviceConfig.Ep[EpNum].Out;
+
+
+	/* Get the data from the Queue Heads Setup buffer into local variables
+	 * so we can extract the setup data values.
+	 */
+	do {
+		/* Arm the tripwire. The tripwire will tell us if a new setup
+		 * packet arrived (in which case the tripwire bit will be
+		 * cleared) while we were reading the buffer. If a new setup
+		 * packet arrived the buffer is corrupted and we continue
+		 * reading.
+		 */
+		XUsbPs_SetSetupTripwire(InstancePtr);
+
+		XUsbPs_dQHInvalidateCache(Ep->dQH);
+
+		Data[0] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB0);
+		Data[1] = XUsbPs_ReaddQH(Ep->dQH, XUSBPS_dQHSUB1);
+	} while (FALSE == XUsbPs_SetupTripwireIsSet(InstancePtr));
+
+	/* Clear the pending endpoint setup stat bit.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET, 1 << EpNum);
+
+	/* Clear the Tripwire bit and continue.
+	 */
+	XUsbPs_ClrSetupTripwire(InstancePtr);
+
+
+	/* Data in the setup buffer is being converted by the core to big
+	 * endian format. We have to take care of proper byte swapping when
+	 * reading the setup data values.
+	 *
+	 * Need to check if there is a smarter way to do this and take the
+	 * processor/memory-controller endianess into account?
+	 */
+	p = (u8 *) Data;
+
+	SetupDataPtr->bmRequestType	= p[0];
+	SetupDataPtr->bRequest		= p[1];
+	SetupDataPtr->wValue		= (p[3] << 8) | p[2];
+	SetupDataPtr->wIndex		= (p[5] << 8) | p[4];
+	SetupDataPtr->wLength		= (p[7] << 8) | p[6];
+
+	/* Before we leave we need to make sure that the endpoint setup bit has
+	 * cleared. It needs to be 0 before the endpoint can be re-primed.
+	 *
+	 * Note: According to the documentation this endpoint setup bit should
+	 * clear within 1-2us after it has been written above. This means that
+	 * we should never catch it being 1 here. However, we still need to
+	 * poll it to make sure. Just in case, we use a counter 'Timeout' so we
+	 * won't hang here if the bit is stuck for some reason.
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET) &
+				(1 << EpNum)) && --Timeout) {
+		/* NOP */
+	}
+	if (0 == Timeout) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the endpoint pointer data structure.
+*
+* The function sets up the local data structure with the aligned addresses for
+* the Queue Head and Transfer Descriptors.
+*
+* @param	DevCfgPtr is pointer to the XUsbPs DEVICE configuration
+*		structure.
+*
+* @return	none
+*
+* @note
+* 		Endpoints of type XUSBPS_EP_TYPE_NONE are not used in the
+* 		system. Therefore no memory is reserved for them.
+*
+******************************************************************************/
+static void XUsbPs_EpListInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+	u8	*p;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Set up the XUsbPs_Endpoint array. This array is used to define the
+	 * location of the Queue Head list and the Transfer Descriptors in the
+	 * block of DMA memory that has been passed into the driver.
+	 *
+	 * 'p' is used to set the pointers in the local data structure.
+	 * Initially 'p' is pointed to the beginning of the DMAable memory
+	 * block. As pointers are assigned, 'p' is incremented by the size of
+	 * the respective object.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+	/* Start off with 'p' pointing to the (aligned) beginning of the DMA
+	 * buffer.
+	 */
+	p = (u8 *) DevCfgPtr->PhysAligned;
+
+
+	/* Initialize the Queue Head pointer list.
+	 *
+	 * Each endpoint has two Queue Heads. One for the OUT direction and one
+	 * for the IN direction. An OUT Queue Head is always followed by an IN
+	 * Queue Head.
+	 *
+	 * Queue Head alignment is XUSBPS_dQH_ALIGN.
+	 *
+	 * Note that we have to reserve space here for unused endpoints.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		/* OUT Queue Head */
+		Ep[EpNum].Out.dQH = (XUsbPs_dQH *) p;
+		p += XUSBPS_dQH_ALIGN;
+
+		/* IN Queue Head */
+		Ep[EpNum].In.dQH = (XUsbPs_dQH *) p;
+		p += XUSBPS_dQH_ALIGN;
+	}
+
+
+	/* 'p' now points to the first address after the Queue Head list. The
+	 * Transfer Descriptors start here.
+	 *
+	 * Each endpoint has a variable number of Transfer Descriptors
+	 * depending on user configuration.
+	 *
+	 * Transfer Descriptor alignment is XUSBPS_dTD_ALIGN.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		/* OUT Descriptors.
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			Ep[EpNum].Out.dTDs		= (XUsbPs_dTD *) p;
+			Ep[EpNum].Out.dTDCurr	= (XUsbPs_dTD *) p;
+			p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs;
+		}
+
+		/* IN Descriptors.
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			Ep[EpNum].In.dTDs		= (XUsbPs_dTD *) p;
+			Ep[EpNum].In.dTDHead	= (XUsbPs_dTD *) p;
+			Ep[EpNum].In.dTDTail	= (XUsbPs_dTD *) p;
+			p += XUSBPS_dTD_ALIGN * EpCfg[EpNum].In.NumBufs;
+		}
+	}
+
+
+	/* 'p' now points to the first address after the Transfer Descriptors.
+	 * The data buffers for the OUT Transfer Desciptors start here.
+	 *
+	 * Note that IN (TX) Transfer Descriptors are not assigned buffers at
+	 * this point. Buffers will be assigned when the user calls the send()
+	 * function.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			/* If BufSize for this endpoint is set to 0 it means
+			 * that we do not need to attach a buffer to this
+			 * descriptor. We also initialize it's buffer pointer
+			 * to NULL.
+			 */
+			if (0 == EpCfg[EpNum].Out.BufSize) {
+				Ep[EpNum].Out.dTDBufs = NULL;
+				continue;
+			}
+
+			Ep[EpNum].Out.dTDBufs = p;
+			p += EpCfg[EpNum].Out.BufSize * EpCfg[EpNum].Out.NumBufs;
+		}
+	}
+
+
+	/* Initialize the endpoint event handlers to NULL.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		Ep[EpNum].Out.HandlerFunc = NULL;
+		Ep[EpNum].In.HandlerFunc  = NULL;
+	}
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes the Queue Head List in memory.
+*
+* @param	DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+*		structure.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XUsbPs_dQHInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access. */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Go through the list of Queue Head entries and:
+	 *
+	 * - Set Transfer Descriptor addresses
+	 * - Set Maximum Packet Size
+	 * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+	 * - Enable Interrupt On Setup (IOS)
+	 *
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+
+		/* OUT Queue Heads.*/
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+					XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+			/* For isochronous, ep max packet size translates to different
+			 * values in queue head than other types.
+			 * Also	enable ZLT for isochronous.
+			 */
+			if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+				XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+                        EpCfg[EpNum].Out.MaxPacketSize);
+				XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+			}else {
+				XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+					    EpCfg[EpNum].Out.MaxPacketSize);
+				XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+			}
+
+			/* Only control OUT needs this */
+			if(XUSBPS_EP_TYPE_CONTROL == EpCfg[EpNum].Out.Type) {
+				XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+			}
+
+			/* Set up the overlay next dTD pointer. */
+			XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+					XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+			XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+		}
+
+
+		/* IN Queue Heads. */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+				  XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+
+			/* Isochronous ep packet size can be larger than 1024.*/
+			if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+				XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+						EpCfg[EpNum].In.MaxPacketSize);
+				XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+			}else {
+				XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+					    EpCfg[EpNum].In.MaxPacketSize);
+				XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+			}
+
+			XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function initializes the Transfer Descriptors lists in memory.
+ *
+ * @param	DevCfgPtr is a pointer to the XUsbPs DEVICE configuration
+ *		structure.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDInit(XUsbPs_DeviceConfig *DevCfgPtr)
+{
+	int	EpNum;
+
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access. */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Walk through the list of endpoints and initialize their Transfer
+	 * Descriptors.
+	 */
+	for (EpNum = 0; EpNum < DevCfgPtr->NumEndpoints; ++EpNum) {
+		int	Td;
+		int	NumdTD;
+
+		XUsbPs_EpOut	*Out = &Ep[EpNum].Out;
+		XUsbPs_EpIn	*In  = &Ep[EpNum].In;
+
+
+		/* OUT Descriptors
+		 * ===============
+		 *
+		 * + Set the next link pointer
+		 * + Set the interrupt complete and the active bit
+		 * + Attach the buffer to the dTD
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].Out.Type) {
+			NumdTD = EpCfg[EpNum].Out.NumBufs;
+		}
+		else {
+			NumdTD = 0;
+		}
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int	Status;
+
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+			/* Set NEXT link pointer. */
+			XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+					  &Out->dTDs[NextTd]);
+
+			/* Set the OUT descriptor ACTIVE and enable the
+			 * interrupt on complete.
+			 */
+			XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+			XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+
+			/* Set up the data buffer with the descriptor. If the
+			 * buffer pointer is NULL it means that we do not need
+			 * to attach a buffer to this descriptor.
+			 */
+			if (NULL == Out->dTDBufs) {
+				XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+				continue;
+			}
+
+			Status = XUsbPs_dTDAttachBuffer(
+					&Out->dTDs[Td],
+					Out->dTDBufs +
+						(Td * EpCfg[EpNum].Out.BufSize),
+					EpCfg[EpNum].Out.BufSize);
+			if (XST_SUCCESS != Status) {
+				return XST_FAILURE;
+			}
+
+			XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+		}
+
+
+		/* IN Descriptors
+		 * ==============
+		 *
+		 * + Set the next link pointer
+		 * + Set the Terminate bit to mark it available
+		 */
+		if (XUSBPS_EP_TYPE_NONE != EpCfg[EpNum].In.Type) {
+			NumdTD = EpCfg[EpNum].In.NumBufs;
+		}
+		else {
+			NumdTD = 0;
+		}
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+			/* Set NEXT link pointer. */
+			XUsbPs_WritedTD(In->dTDs[Td], XUSBPS_dTDNLP,
+					  In->dTDs[NextTd]);
+
+			/* Set the IN descriptor's TERMINATE bits. */
+			XUsbPs_dTDSetTerminate(In->dTDs[Td]);
+
+			XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ *
+ * This function associates a buffer with a Transfer Descriptor. The function
+ * will take care of splitting the buffer into multiple 4kB aligned segments if
+ * the buffer happens to span one or more 4kB pages.
+ *
+ * @param	dTDIndex is a pointer to the Transfer Descriptor
+ * @param	BufferPtr is pointer to the buffer to link to the descriptor.
+ * @param	BufferLen is the length of the buffer.
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *		- XST_USB_BUF_TOO_BIG: The provided buffer is bigger than tha
+ *		maximum allowed buffer size (16k).
+ *
+ * @note
+ * 		Cache invalidation and flushing needs to be handler by the
+ * 		caller of this function.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDAttachBuffer(XUsbPs_dTD *dTDPtr,
+					const u8 *BufferPtr, u32 BufferLen)
+{
+	u32	BufAddr;
+	u32	BufEnd;
+	u32	PtrNum;
+
+	Xil_AssertNonvoid(dTDPtr    != NULL);
+
+	/* Check if the buffer is smaller than 16kB. */
+	if (BufferLen > XUSBPS_dTD_BUF_MAX_SIZE) {
+		return XST_USB_BUF_TOO_BIG;
+	}
+
+	/* Get a u32 of the buffer pointer to avoid casting in the following
+	 * logic operations.
+	 */
+	BufAddr = (u32) BufferPtr;
+
+
+	/* Set the buffer pointer 0. Buffer pointer 0 can point to any location
+	 * in memory. It does not need to be 4kB aligned. However, if the
+	 * provided buffer spans one or more 4kB boundaries, we need to set up
+	 * the subsequent buffer pointers which must be 4kB aligned.
+	 */
+	XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(0), BufAddr);
+
+	/* Check if the buffer spans a 4kB boundary.
+	 *
+	 * Only do this check, if we are not sending a 0-length buffer.
+	 */
+	if (BufferLen > 0) {
+		BufEnd = BufAddr + BufferLen -1;
+		PtrNum = 1;
+
+		while ((BufAddr & 0xFFFFF000) != (BufEnd & 0xFFFFF000)) {
+			/* The buffer spans at least one boundary, let's set
+			 * the next buffer pointer and repeat the procedure
+			 * until the end of the buffer and the pointer written
+			 * are in the same 4kB page.
+			 */
+			BufAddr = (BufAddr + 0x1000) & 0xFFFFF000;
+			XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDBPTR(PtrNum),
+								BufAddr);
+			PtrNum++;
+		}
+	}
+
+	/* Set the length of the buffer. */
+	XUsbPs_dTDSetTransferLen(dTDPtr, BufferLen);
+
+
+	/* We remember the buffer pointer in the user data field (reserved
+	 * field in the dTD). This makes it easier to reset the buffer pointer
+	 * after a buffer has been received on the endpoint. The buffer pointer
+	 * needs to be reset because the DMA engine modifies the buffer pointer
+	 * while receiving.
+	 */
+	XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDUSERDATA, BufferPtr);
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function set the Max PacketLen for the queue head for isochronous EP.
+ *
+ * If the max packet length is greater than XUSBPS_MAX_PACKET_SIZE, then
+ * Mult bits are set to reflect that.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Len is the Length to be set.
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHSetMaxPacketLenISO(XUsbPs_dQH *dQHPtr, u32 Len)
+{
+	u32 Mult = (Len & ENDPOINT_MAXP_MULT_MASK) >> ENDPOINT_MAXP_MULT_SHIFT;
+	u32 MaxPktSize = (Mult > 1) ? ENDPOINT_MAXP_LENGTH : Len;
+
+	if (MaxPktSize > XUSBPS_MAX_PACKET_SIZE) {
+		return;
+	}
+
+	if (Mult > 3) {
+		return;
+	}
+
+	/* Set Max packet size */
+	XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+		(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+			~XUSBPS_dQHCFG_MPL_MASK) |
+			(MaxPktSize << XUSBPS_dQHCFG_MPL_SHIFT));
+
+	/* Set Mult to tell hardware how many transactions in each microframe */
+	XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG,
+		(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &
+			~XUSBPS_dQHCFG_MULT_MASK) |
+			(Mult << XUSBPS_dQHCFG_MULT_SHIFT));
+
+}
+
+/*****************************************************************************/
+/**
+* This function reconfigures one Ep corresponding to host's request of setting
+* alternate interface. The endpoint has been disabled before this call.
+*
+* Both QH and dTDs are updated for the new configuration.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	CfgPtr
+* 		Pointer to the updated XUsbPs DEVICE configuration structure.
+*
+* @param	EpNum
+*		The endpoint to be reconfigured.
+*
+* @param NewDirection
+*		The new transfer direction the endpoint.
+*
+* @param DirectionChanged
+*		A boolean value indicate whether the transfer direction has changed.
+*
+* @return
+*	XST_SUCCESS upon success, XST_FAILURE otherwise.
+*
+******************************************************************************/
+int XUsbPs_ReconfigureEp(XUsbPs *InstancePtr, XUsbPs_DeviceConfig *CfgPtr,
+				int EpNum, unsigned short NewDirection,
+				int DirectionChanged) {
+
+	int Status = XST_SUCCESS;
+	XUsbPs_Endpoint *Ep;
+	XUsbPs_EpConfig *EpCfg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr      != NULL);
+
+	Ep = CfgPtr->Ep;
+	EpCfg = CfgPtr->EpCfg;
+
+	/* If transfer direction changes, dTDs has to be reset
+	 * Number of buffers are preset and should not to be changed.
+	 */
+	if(DirectionChanged) {
+		if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+			u8 *p;
+
+			/* Swap the pointer to the dTDs.
+			 */
+			Ep[EpNum].Out.dTDs = Ep[EpNum].In.dTDs;
+			p = (u8 *)(Ep[EpNum].Out.dTDs + XUSBPS_dTD_ALIGN * EpCfg[EpNum].Out.NumBufs);
+
+			/* Set the OUT buffer if buffer size is not zero
+			 */
+			if(EpCfg[EpNum].Out.BufSize > 0) {
+				Ep[EpNum].Out.dTDBufs = p;
+			}
+		} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+			Ep[EpNum].In.dTDs = Ep[EpNum].Out.dTDs;
+		}
+	}
+
+	/* Reset dTD progress tracking pointers
+	 */
+	if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+		Ep[EpNum].In.dTDHead = Ep[EpNum].In.dTDTail = Ep[EpNum].In.dTDs;
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		Ep[EpNum].Out.dTDCurr = Ep[EpNum].Out.dTDs;
+	}
+
+	/* Reinitialize information in QH
+	 */
+	XUsbPs_dQHReinitEp(CfgPtr, EpNum, NewDirection);
+
+	/* Reinitialize the dTD linked list, and flush the cache
+	 */
+	Status = XUsbPs_dTDReinitEp(CfgPtr, EpNum, NewDirection);
+	if(Status != XST_SUCCESS) {
+		return Status;
+	}
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+ * This function re-initializes the Queue Head List in memory.
+ * The endpoint 1 has been disabled before this call.
+ *
+ * @param	DevCfgPtr
+ * 		Pointer to the updated XUsbPs DEVICE configuration structure.
+ *
+ * @param	EpNum
+ *		The endpoint to be reconfigured.
+ *
+ * @param	NewDirection
+ *		The new transfer direction of endpoint 1
+ *
+ * @return	none
+ *
+ ******************************************************************************/
+static void XUsbPs_dQHReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+
+	/* Setup pointers for simpler access.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	/* Go through the list of Queue Head entries and:
+	 *
+	 * - Set Transfer Descriptor addresses
+	 * - Set Maximum Packet Size
+	 * - Disable Zero Length Termination (ZLT) for non-isochronous transfers
+	 * - Enable Interrupt On Setup (IOS)
+	 *
+	 */
+	if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		/* OUT Queue Heads.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+			XUSBPS_dQHCPTR, Ep[EpNum].Out.dTDs);
+
+		/* For isochronous, ep max packet size translates to different
+		 * values in queue head than other types.
+		 * Also	enable ZLT for isochronous.
+		 */
+		if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].Out.Type) {
+			XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].Out.dQH,
+   					EpCfg[EpNum].Out.MaxPacketSize);
+			XUsbPs_dQHEnableZLT(Ep[EpNum].Out.dQH);
+		}else {
+			XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].Out.dQH,
+				    EpCfg[EpNum].Out.MaxPacketSize);
+			XUsbPs_dQHDisableZLT(Ep[EpNum].Out.dQH);
+		}
+
+		XUsbPs_dQHSetIOS(Ep[EpNum].Out.dQH);
+
+		/* Set up the overlay next dTD pointer.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].Out.dQH,
+				XUSBPS_dQHdTDNLP, Ep[EpNum].Out.dTDs);
+
+		XUsbPs_dQHFlushCache(Ep[EpNum].Out.dQH);
+
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+
+		/* IN Queue Heads.
+		 */
+		XUsbPs_WritedQH(Ep[EpNum].In.dQH,
+			  XUSBPS_dQHCPTR, Ep[EpNum].In.dTDs);
+
+		/* Isochronous ep packet size can be larger than 1024. */
+		if(XUSBPS_EP_TYPE_ISOCHRONOUS == EpCfg[EpNum].In.Type) {
+			XUsbPs_dQHSetMaxPacketLenISO(Ep[EpNum].In.dQH,
+   				EpCfg[EpNum].In.MaxPacketSize);
+			XUsbPs_dQHEnableZLT(Ep[EpNum].In.dQH);
+		}else {
+			XUsbPs_dQHSetMaxPacketLen(Ep[EpNum].In.dQH,
+			    EpCfg[EpNum].In.MaxPacketSize);
+			XUsbPs_dQHDisableZLT(Ep[EpNum].In.dQH);
+		}
+
+		XUsbPs_dQHSetIOS(Ep[EpNum].In.dQH);
+
+		XUsbPs_dQHFlushCache(Ep[EpNum].In.dQH);
+	}
+
+}
+
+/*****************************************************************************/
+/**
+ *
+ * This function re-initializes the Transfer Descriptors lists in memory.
+ * The endpoint has been disabled before the call. The transfer descriptors
+ * list pointer has been initialized too.
+ *
+ * @param	DevCfgPtr
+ * 		Pointer to the XUsbPs DEVICE configuration structure.
+ *
+ * @param	EpNum
+ *		The endpoint to be reconfigured.
+ *
+ * @param	NewDirection
+ *		The new transfer direction of endpoint 1
+ *
+ * @return
+ *		- XST_SUCCESS: The operation completed successfully.
+ *		- XST_FAILURE: An error occured.
+ *
+ ******************************************************************************/
+static int XUsbPs_dTDReinitEp(XUsbPs_DeviceConfig *DevCfgPtr,
+int EpNum, unsigned short NewDirection)
+{
+	XUsbPs_Endpoint	*Ep;
+	XUsbPs_EpConfig	*EpCfg;
+	int	Td;
+	int	NumdTD;
+
+
+	/* Setup pointers for simpler access.
+	 */
+	Ep	= DevCfgPtr->Ep;
+	EpCfg	= DevCfgPtr->EpCfg;
+
+
+	if(NewDirection == XUSBPS_EP_DIRECTION_OUT) {
+		XUsbPs_EpOut	*Out = &Ep[EpNum].Out;
+
+		/* OUT Descriptors
+		 * ===============
+		 *
+		 * + Set the next link pointer
+		 * + Set the interrupt complete and the active bit
+		 * + Attach the buffer to the dTD
+		 */
+		NumdTD = EpCfg[EpNum].Out.NumBufs;
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int	Status;
+
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&Out->dTDs[Td]);
+
+			/* Set NEXT link pointer.
+			 */
+			XUsbPs_WritedTD(&Out->dTDs[Td], XUSBPS_dTDNLP,
+					  &Out->dTDs[NextTd]);
+
+			/* Set the OUT descriptor ACTIVE and enable the
+			 * interrupt on complete.
+			 */
+			XUsbPs_dTDSetActive(&Out->dTDs[Td]);
+			XUsbPs_dTDSetIOC(&Out->dTDs[Td]);
+
+			/* Set up the data buffer with the descriptor. If the
+			 * buffer pointer is NULL it means that we do not need
+			 * to attach a buffer to this descriptor.
+			 */
+			if (Out->dTDBufs != NULL) {
+
+				Status = XUsbPs_dTDAttachBuffer(
+						&Out->dTDs[Td],
+						Out->dTDBufs +
+							(Td * EpCfg[EpNum].Out.BufSize),
+						EpCfg[EpNum].Out.BufSize);
+				if (Status != XST_SUCCESS) {
+					return XST_FAILURE;
+				}
+			}
+			XUsbPs_dTDFlushCache(&Out->dTDs[Td]);
+		}
+	} else if(NewDirection == XUSBPS_EP_DIRECTION_IN) {
+		XUsbPs_EpIn	*In  = &Ep[EpNum].In;
+
+		/* IN Descriptors
+		 * ==============
+		 *
+		 * + Set the next link pointer
+		 * + Set the Terminate bit to mark it available
+		 */
+		NumdTD = EpCfg[EpNum].In.NumBufs;
+
+		for (Td = 0; Td < NumdTD; ++Td) {
+			int NextTd = (Td + 1) % NumdTD;
+
+			XUsbPs_dTDInvalidateCache(&In->dTDs[Td]);
+
+			/* Set NEXT link pointer.
+			 */
+			XUsbPs_WritedTD(&In->dTDs[Td], XUSBPS_dTDNLP,
+					  &In->dTDs[NextTd]);
+
+			/* Set the IN descriptor's TERMINATE bits.
+			 */
+			XUsbPs_dTDSetTerminate(&In->dTDs[Td]);
+
+			XUsbPs_dTDFlushCache(&In->dTDs[Td]);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
new file mode 100644
index 0000000..1cb0cfc
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h
@@ -0,0 +1,515 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_endpoint.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This is an internal file containung the definitions for endpoints. It is
+ * included by the xusbps_endpoint.c which is implementing the endpoint
+ * functions and by xusbps_intr.c.
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- --------------------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 
    
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_ENDPOINT_H
+#define XUSBPS_ENDPOINT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xusbps.h"
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+
+/**
+ * Endpoint Device Transfer Descriptor
+ *
+ * The dTD describes to the device controller the location and quantity of data
+ * to be sent/received for given transfer. The driver does not attempt to
+ * modify any field in an active dTD except the Next Link Pointer.
+ */
+#define XUSBPS_dTDNLP		0x00 /**< Pointer to the next descriptor */
+#define XUSBPS_dTDTOKEN	0x04 /**< Descriptor Token */
+#define XUSBPS_dTDBPTR0	0x08 /**< Buffer Pointer 0 */
+#define XUSBPS_dTDBPTR1	0x0C /**< Buffer Pointer 1 */
+#define XUSBPS_dTDBPTR2	0x10 /**< Buffer Pointer 2 */
+#define XUSBPS_dTDBPTR3	0x14 /**< Buffer Pointer 3 */
+#define XUSBPS_dTDBPTR4	0x18 /**< Buffer Pointer 4 */
+#define XUSBPS_dTDBPTR(n)	(XUSBPS_dTDBPTR0 + (n) * 0x04)
+#define XUSBPS_dTDRSRVD	0x1C /**< Reserved field */
+
+/* We use the reserved field in the dTD to store user data. */
+#define XUSBPS_dTDUSERDATA	XUSBPS_dTDRSRVD /**< Reserved field */
+
+
+/** @name dTD Next Link Pointer (dTDNLP) bit positions.
+ *  @{
+ */
+#define XUSBPS_dTDNLP_T_MASK		0x00000001
+				/**< USB dTD Next Link Pointer Terminate Bit */
+#define XUSBPS_dTDNLP_ADDR_MASK	0xFFFFFFE0
+				/**< USB dTD Next Link Pointer Address [31:5] */
+/* @} */
+
+
+/** @name dTD Token (dTDTOKEN) bit positions.
+ *  @{
+ */
+#define XUSBPS_dTDTOKEN_XERR_MASK	0x00000008 /**< dTD Transaction Error */
+#define XUSBPS_dTDTOKEN_BUFERR_MASK	0x00000020 /**< dTD Data Buffer Error */
+#define XUSBPS_dTDTOKEN_HALT_MASK	0x00000040 /**< dTD Halted Flag */
+#define XUSBPS_dTDTOKEN_ACTIVE_MASK	0x00000080 /**< dTD Active Bit */
+#define XUSBPS_dTDTOKEN_MULTO_MASK	0x00000C00 /**< Multiplier Override Field [1:0] */
+#define XUSBPS_dTDTOKEN_IOC_MASK	0x00008000 /**< Interrupt on Complete Bit */
+#define XUSBPS_dTDTOKEN_LEN_MASK	0x7FFF0000 /**< Transfer Length Field */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * IMPORTANT NOTE:
+ * ===============
+ *
+ * Many of the following macros modify Device Queue Head (dQH) data structures
+ * and Device Transfer Descriptor (dTD) data structures. Those structures can
+ * potentially reside in CACHED memory. Therefore, it's the callers
+ * responsibility to ensure cache coherency by using provided
+ *
+ * 	XUsbPs_dQHInvalidateCache()
+ * 	XUsbPs_dQHFlushCache()
+ * 	XUsbPs_dTDInvalidateCache()
+ * 	XUsbPs_dTDFlushCache()
+ *
+ * function calls.
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDInvalidateCache(dTDPtr) \
+		Xil_DCacheInvalidateRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dTDFlushCache(dTDPtr) \
+		Xil_DCacheFlushRange((unsigned int)dTDPtr, sizeof(XUsbPs_dTD))
+
+#define XUsbPs_dQHInvalidateCache(dQHPtr) \
+		Xil_DCacheInvalidateRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+#define XUsbPs_dQHFlushCache(dQHPtr) \
+		Xil_DCacheFlushRange((unsigned int)dQHPtr, sizeof(XUsbPs_dQH))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ * @param	Len is the length to be set. Range: 0..16384
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTransferLen(dTDPtr, Len)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) &	\
+				~XUSBPS_dTDTOKEN_LEN_MASK) | ((Len) << 16))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ *
+ * @return 	TransferLength field of the descriptor.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetNLP(dTDPtr)					\
+		(XUsbPs_dTD *) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP)\
+					& XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Next Link pointer of the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ * @param	NLP is the Next Link Pointer
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTransferLen(u32 dTDPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetNLP(dTDPtr, NLP)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			(XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) &	\
+				~XUSBPS_dTDNLP_ADDR_MASK) |		\
+					((NLP) & XUSBPS_dTDNLP_ADDR_MASK))
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro gets the Transfer Length for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @return 	TransferLength field of the descriptor.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_dTDGetTransferLen(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDGetTransferLen(dTDPtr)				\
+		(u32) ((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) 	\
+				& XUSBPS_dTDTOKEN_LEN_MASK) >> 16)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Complete (IOC) bit for the given Transfer
+ * Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetIOC(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetIOC(dTDPtr)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) |	\
+						XUSBPS_dTDTOKEN_IOC_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetTerminate(dTDPtr)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) |	\
+						XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Terminate bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDClrTerminate(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDClrTerminate(dTDPtr)				\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDNLP, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDNLP) &	\
+						~XUSBPS_dTDNLP_T_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro checks if the given descriptor is active.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @return
+ * 		- TRUE: The buffer is active.
+ * 		- FALSE: The buffer is not active.
+ *
+ * @note	C-style signature:
+ *		int XUsbPs_dTDIsActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDIsActive(dTDPtr)					\
+		((XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) &		\
+				XUSBPS_dTDTOKEN_ACTIVE_MASK) ? TRUE : FALSE)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Active bit for the given Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dTDSetActive(u32 dTDPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dTDSetActive(dTDPtr)					\
+		XUsbPs_WritedTD(dTDPtr, XUSBPS_dTDTOKEN, 		\
+			XUsbPs_ReaddTD(dTDPtr, XUSBPS_dTDTOKEN) |	\
+						XUSBPS_dTDTOKEN_ACTIVE_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Transfer Descriptor.
+ *
+ * @param	dTDPtr is a pointer to the dTD element.
+ * @param	Id is the field ID inside the dTD element to read.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_ReaddTD(u32 dTDPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddTD(dTDPtr, Id)	(*(u32 *)((u32)(dTDPtr) + (u32)(Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Transfer Descriptor.
+ *
+ * @param	dTDPtr is pointer to the dTD element.
+ * @param	Id is the field ID inside the dTD element to read.
+ * @param	Val is the value to write to the field.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_WritedTD(u32 dTDPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedTD(dTDPtr, Id, Val)	\
+			(*(u32 *) ((u32)(dTDPtr) + (u32)(Id)) = (u32)(Val))
+
+
+/******************************************************************************/
+/**
+ * Endpoint Device Queue Head
+ *
+ * Device queue heads are arranged in an array in a continuous area of memory
+ * pointed to by the ENDPOINTLISTADDR pointer. The device controller will index
+ * into this array based upon the endpoint number received from the USB bus.
+ * All information necessary to respond to transactions for all primed
+ * transfers is contained in this list so the Device Controller can readily
+ * respond to incoming requests without having to traverse a linked list.
+ *
+ * The device Endpoint Queue Head (dQH) is where all transfers are managed. The
+ * dQH is a 48-byte data structure, but must be aligned on a 64-byte boundary.
+ * During priming of an endpoint, the dTD (device transfer descriptor) is
+ * copied into the overlay area of the dQH, which starts at the nextTD pointer
+ * DWord and continues through the end of the buffer pointers DWords. After a
+ * transfer is complete, the dTD status DWord is updated in the dTD pointed to
+ * by the currentTD pointer. While a packet is in progress, the overlay area of
+ * the dQH is used as a staging area for the dTD so that the Device Controller
+ * can access needed information with little minimal latency.
+ *
+ * @note
+ *    Software must ensure that no interface data structure reachable by the
+ *    Device Controller spans a 4K-page boundary.  The first element of the
+ *    Endpoint Queue Head List must be aligned on a 4K boundary.
+ */
+#define XUSBPS_dQHCFG			0x00 /**< dQH Configuration */
+#define XUSBPS_dQHCPTR			0x04 /**< dQH Current dTD Pointer */
+#define XUSBPS_dQHdTDNLP		0x08 /**< dTD Next Link Ptr in dQH
+					       overlay */
+#define XUSBPS_dQHdTDTOKEN		0x0C /**< dTD Token in dQH overlay */
+#define XUSBPS_dQHSUB0			0x28 /**< USB dQH Setup Buffer 0 */
+#define XUSBPS_dQHSUB1			0x2C /**< USB dQH Setup Buffer 1 */
+
+
+/** @name dQH Configuration (dQHCFG) bit positions.
+ *  @{
+ */
+#define XUSBPS_dQHCFG_IOS_MASK		0x00008000
+					/**< USB dQH Interrupt on Setup Bit */
+#define XUSBPS_dQHCFG_MPL_MASK		0x07FF0000
+					/**< USB dQH Maximum Packet Length
+					 * Field [10:0] */
+#define XUSBPS_dQHCFG_MPL_SHIFT    16
+#define XUSBPS_dQHCFG_ZLT_MASK		0x20000000
+					/**< USB dQH Zero Length Termination
+					 * Select Bit */
+#define XUSBPS_dQHCFG_MULT_MASK		0xC0000000
+					/* USB dQH Number of Transactions Field
+					 * [1:0] */
+#define XUSBPS_dQHCFG_MULT_SHIFT       30
+/* @} */
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Maximum Packet Length field of the give Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Len is the length to be set.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHSetMaxPacketLen(u32 dQHPtr, u32 Len)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetMaxPacketLen(dQHPtr, Len)			\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			(XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+				~XUSBPS_dQHCFG_MPL_MASK) | ((Len) << 16))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro sets the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHSetIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHSetIOS(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) |	\
+						XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro clears the Interrupt On Setup (IOS) bit for an endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHClrIOS(u32 dQHPtr)
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHClrIOS(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+						~XUSBPS_dQHCFG_IOS_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro enables Zero Length Termination for the endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHEnableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHEnableZLT(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) &	\
+						~XUSBPS_dQHCFG_ZLT_MASK)
+
+
+/*****************************************************************************/
+/**
+ *
+ * This macro disables Zero Length Termination for the endpoint.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ *
+ * @note	C-style signature:
+ *		void XUsbPs_dQHDisableZLT(u32 dQHPtr)
+ *
+ *
+ ******************************************************************************/
+#define XUsbPs_dQHDisableZLT(dQHPtr)					\
+		XUsbPs_WritedQH(dQHPtr, XUSBPS_dQHCFG, 		\
+			XUsbPs_ReaddQH(dQHPtr, XUSBPS_dQHCFG) |	\
+						XUSBPS_dQHCFG_ZLT_MASK)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro reads the content of a field in a Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Id is the Field ID inside the dQH element to read.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_ReaddQH(u32 dQHPtr, u32 Id)
+ *
+ ******************************************************************************/
+#define XUsbPs_ReaddQH(dQHPtr, Id)	(*(u32 *)((u32)(dQHPtr) + (u32) (Id)))
+
+/*****************************************************************************/
+/**
+ *
+ * This macro writes a value to a field in a Queue Head.
+ *
+ * @param	dQHPtr is a pointer to the dQH element.
+ * @param	Id is the Field ID inside the dQH element to read.
+ * @param	Val is the Value to write to the field.
+ *
+ * @note	C-style signature:
+ *		u32 XUsbPs_WritedQH(u32 dQHPtr, u32 Id, u32 Val)
+ *
+ ******************************************************************************/
+#define XUsbPs_WritedQH(dQHPtr, Id, Val)	\
+			(*(u32 *) ((u32)(dQHPtr) + (u32)(Id)) = (u32)(Val))
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_ENDPOINT_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
new file mode 100644
index 0000000..9f20ba8
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xusbps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUsbPs_Config XUsbPs_ConfigTable[XPAR_XUSBPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_USB_0_DEVICE_ID,
+		XPAR_PS7_USB_0_BASEADDR
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
new file mode 100644
index 0000000..04963b2
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c
@@ -0,0 +1,122 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The implementation of the XUsbPs interface reset functionality
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.05a kpc  10/10/10 first version
+ * 
    
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+
+/************************** Constant Definitions ****************************/
+#define XUSBPS_RESET_TIMEOUT 0xFFFFF
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+
+/************************** Function Prototypes *****************************/
+
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given usbps interface by 
+* configuring the appropriate control bits in the usbps specifc registers.
+* the usbps reset sequence involves the below steps
+* 	Disbale the interrupts
+*	Clear the status registers
+*	Apply the reset command and wait for reset complete status
+*	Update the relevant control registers with reset values
+* @param   BaseAddress of the interface
+*
+* @return   N/A.
+*
+* @note     None.
+*
+******************************************************************************/
+void XUsbPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+	u32 Timeout = 0;
+	
+	/* Host and device mode */
+	/* Disable the interrupts */
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_IER_OFFSET,0x0);
+	/* Clear the interuupt status */
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_ISR_OFFSET);
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_ISR_OFFSET,RegVal);
+
+	/* Perform the reset operation using USB CMD register */	
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+	RegVal = RegVal | XUSBPS_CMD_RST_MASK;
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_CMD_OFFSET,RegVal);
+	RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);
+	/* Wait till the reset operation returns success */
+	/*
+	* FIX ME: right now no indication to the caller or user about
+	* timeout overflow
+	*/
+	while ((RegVal & XUSBPS_CMD_RST_MASK) && (Timeout < XUSBPS_RESET_TIMEOUT))
+	{
+		RegVal = XUsbPs_ReadReg(BaseAddress,XUSBPS_CMD_OFFSET);	
+		Timeout++;
+	}
+	/* Update periodic list base address register with reset value */		
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_LISTBASE_OFFSET,0x0);	
+	/* Update async/endpoint list base address register with reset value */		
+	XUsbPs_WriteReg(BaseAddress,XUSBPS_ASYNCLISTADDR_OFFSET,0x0);		
+	
+}
+
+
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
new file mode 100644
index 0000000..69f3ebf
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h
@@ -0,0 +1,526 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xusbps_hw.h
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xusbps.h.
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 1.04a nm   10/23/12 Fixed CR# 679106.
+ * 1.05a kpc  07/03/13 Added XUsbPs_ResetHw function prototype
+ * 2.00a kpc  04/03/14 Fixed CR#777764. Corrected max endpoint vale and masks 
+ * 
    
+ *
+ ******************************************************************************/
+#ifndef XUSBPS_HW_H
+#define XUSBPS_HW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XUSBPS_REG_SPACING		4
+
+/** @name Timer 0 Register offsets
+ *
+ * @{
+ */
+#define XUSBPS_TIMER0_LD_OFFSET	0x00000080
+#define XUSBPS_TIMER0_CTL_OFFSET	0x00000084
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_RUN_MASK		0x80000000
+#define XUSBPS_TIMER_STOP_MASK		0x80000000
+#define XUSBPS_TIMER_RESET_MASK	0x40000000
+#define XUSBPS_TIMER_REPEAT_MASK	0x01000000
+/* @} */
+
+/** @name Timer Control Register bit mask
+ *
+ * @{
+ */
+#define XUSBPS_TIMER_COUNTER_MASK	0x00FFFFFF
+/* @} */
+
+/** @name Device Hardware Parameters
+ *
+ * @{
+ */
+#define XUSBPS_HWDEVICE_OFFSET		0x0000000C
+
+#define XUSBPS_EP_NUM_MASK		0x3E
+#define XUSBPS_EP_NUM_SHIFT		1
+/* @} */
+
+/** @name Capability Regsiter offsets
+ */
+#define XUSBPS_HCSPARAMS_OFFSET		0x00000104
+
+/** @name Operational Register offsets.
+ * Register comments are tagged with "H:" and "D:" for Host and Device modes,
+ * respectively.
+ * Tags are only present for registers that have a different meaning DEVICE and
+ * HOST modes. Most registers are only valid for either DEVICE or HOST mode.
+ * Those registers don't have tags.
+ * @{
+ */
+#define XUSBPS_CMD_OFFSET		0x00000140 /**< Configuration */
+#define XUSBPS_ISR_OFFSET		0x00000144 /**< Interrupt Status */
+#define XUSBPS_IER_OFFSET		0x00000148 /**< Interrupt Enable */
+#define XUSBPS_FRAME_OFFSET		0x0000014C /**< USB Frame Index */
+#define XUSBPS_LISTBASE_OFFSET		0x00000154 /**< H: Periodic List Base Address */
+#define XUSBPS_DEVICEADDR_OFFSET	0x00000154 /**< D: Device Address */
+#define XUSBPS_ASYNCLISTADDR_OFFSET	0x00000158 /**< H: Async List Address */
+#define XUSBPS_EPLISTADDR_OFFSET	0x00000158 /**< D: Endpoint List Addr */
+#define XUSBPS_TTCTRL_OFFSET		0x0000015C /**< TT Control */
+#define XUSBPS_BURSTSIZE_OFFSET	0x00000160 /**< Burst Size */
+#define XUSBPS_TXFILL_OFFSET		0x00000164 /**< Tx Fill Tuning */
+#define XUSBPS_ULPIVIEW_OFFSET		0x00000170 /**< ULPI Viewport */
+#define XUSBPS_EPNAKISR_OFFSET		0x00000178 /**< Endpoint NAK IRQ Status */
+#define XUSBPS_EPNAKIER_OFFSET		0x0000017C /**< Endpoint NAK IRQ Enable */
+#define XUSBPS_PORTSCR1_OFFSET		0x00000184 /**< Port Control/Status 1 */
+
+/* NOTE: The Port Control / Status Register index is 1-based. */
+#define XUSBPS_PORTSCRn_OFFSET(n)	\
+		(XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING))
+
+
+#define XUSBPS_OTGCSR_OFFSET	0x000001A4 /**< OTG Status and Control */
+#define XUSBPS_MODE_OFFSET	0x000001A8 /**< USB Mode */
+#define XUSBPS_EPSTAT_OFFSET	0x000001AC /**< Endpoint Setup Status */
+#define XUSBPS_EPPRIME_OFFSET	0x000001B0 /**< Endpoint Prime */
+#define XUSBPS_EPFLUSH_OFFSET	0x000001B4 /**< Endpoint Flush */
+#define XUSBPS_EPRDY_OFFSET	0x000001B8 /**< Endpoint Ready */
+#define XUSBPS_EPCOMPL_OFFSET	0x000001BC /**< Endpoint Complete */
+#define XUSBPS_EPCR0_OFFSET	0x000001C0 /**< Endpoint Control 0 */
+#define XUSBPS_EPCR1_OFFSET	0x000001C4 /**< Endpoint Control 1 */
+#define XUSBPS_EPCR2_OFFSET	0x000001C8 /**< Endpoint Control 2 */
+#define XUSBPS_EPCR3_OFFSET	0x000001CC /**< Endpoint Control 3 */
+#define XUSBPS_EPCR4_OFFSET	0x000001D0 /**< Endpoint Control 4 */
+
+#define XUSBPS_MAX_ENDPOINTS	12	   /**< Number of supported Endpoints in
+					     *  this core. */
+#define XUSBPS_EP_OUT_MASK	0x00000FFF /**< OUR (RX) endpoint mask */
+#define XUSBPS_EP_IN_MASK	0x0FFF0000 /**< IN (TX) endpoint mask */
+#define XUSBPS_EP_ALL_MASK	0x0FFF0FFF /**< Mask used for endpoint control
+					     *  registers */
+#define XUSBPS_EPCRn_OFFSET(n)	\
+		(XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING))
+
+#define  XUSBPS_EPFLUSH_RX_SHIFT   0
+#define  XUSBPS_EPFLUSH_TX_SHIFT  16
+
+/* @} */
+
+
+
+/** @name Endpoint Control Register (EPCR) bit positions.
+ *  @{
+ */
+
+/* Definitions for TX Endpoint bits */
+#define XUSBPS_EPCR_TXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - TX */
+#define XUSBPS_EPCR_TXT_ISO_MASK	0x00040000 /**< Isochronous. Endpoint */
+#define XUSBPS_EPCR_TXT_BULK_MASK	0x00080000 /**< Bulk Endpoint - TX */
+#define XUSBPS_EPCR_TXT_INTR_MASK	0x000C0000 /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_TXS_MASK		0x00010000 /**< Stall TX endpoint */
+#define XUSBPS_EPCR_TXE_MASK		0x00800000 /**< Transmit enable  - TX */
+#define XUSBPS_EPCR_TXR_MASK		0x00400000 /**< Data Toggle Reset Bit */
+
+
+/* Definitions for RX Endpoint bits */
+#define XUSBPS_EPCR_RXT_CONTROL_MASK	0x00000000 /**< Control Endpoint - RX */
+#define XUSBPS_EPCR_RXT_ISO_MASK	0x00000004 /**< Isochronous Endpoint */
+#define XUSBPS_EPCR_RXT_BULK_MASK	0x00000008 /**< Bulk Endpoint - RX */
+#define XUSBPS_EPCR_RXT_INTR_MASK	0x0000000C /**< Interrupt Endpoint */
+#define XUSBPS_EPCR_RXS_MASK		0x00000001 /**< Stall RX endpoint. */
+#define XUSBPS_EPCR_RXE_MASK		0x00000080 /**< Transmit enable. - RX */
+#define XUSBPS_EPCR_RXR_MASK		0x00000040 /**< Data Toggle Reset Bit */
+/* @} */
+
+
+/** @name USB Command Register (CR) bit positions.
+ *  @{
+ */
+#define XUSBPS_CMD_RS_MASK	0x00000001 /**< Run/Stop */
+#define XUSBPS_CMD_RST_MASK	0x00000002 /**< Controller RESET */
+#define XUSBPS_CMD_FS01_MASK	0x0000000C /**< Frame List Size bit 0,1 */
+#define XUSBPS_CMD_PSE_MASK	0x00000010 /**< Periodic Sched Enable */
+#define XUSBPS_CMD_ASE_MASK	0x00000020 /**< Async Sched Enable */
+#define XUSBPS_CMD_IAA_MASK	0x00000040 /**< IRQ Async Advance Doorbell */
+#define XUSBPS_CMD_ASP_MASK	0x00000300 /**< Async Sched Park Mode Cnt */
+#define XUSBPS_CMD_ASPE_MASK	0x00000800 /**< Async Sched Park Mode Enbl */
+#define XUSBPS_CMD_SUTW_MASK	0x00002000 /**< Setup TripWire */
+#define XUSBPS_CMD_ATDTW_MASK	0x00004000 /**< Add dTD TripWire */
+#define XUSBPS_CMD_FS2_MASK	0x00008000 /**< Frame List Size bit 2 */
+#define XUSBPS_CMD_ITC_MASK	0x00FF0000 /**< IRQ Threshold Control */
+/* @} */
+
+
+/**
+ * @name Interrupt Threshold
+ * These definitions are used by software to set the maximum rate at which the
+ * USB controller will generate interrupt requests. The interrupt interval is
+ * given in number of micro-frames.
+ *
+ * USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
+ * packet each and every 1ms. USB also defines a high-speed micro-frame with a
+ * 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is
+ * generated. Data is sent in between the SOF packets. The interrupt threshold
+ * defines how many micro-frames the controller waits before issuing an
+ * interrupt after data has been received.
+ *
+ * For a threshold of 0 the controller will issue an interrupt immediately
+ * after the last byte of the data has been received. For a threshold n>0 the
+ * controller will wait for n micro-frames before issuing an interrupt.
+ *
+ * Therefore, a setting of 8 micro-frames (default) means that the controller
+ * will issue at most 1 interrupt per millisecond.
+ *
+ * @{
+ */
+#define XUSBPS_CMD_ITHRESHOLD_0	0x00 /**< Immediate interrupt. */
+#define XUSBPS_CMD_ITHRESHOLD_1	0x01 /**< 1 micro-frame */
+#define XUSBPS_CMD_ITHRESHOLD_2	0x02 /**< 2 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_4	0x04 /**< 4 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_8	0x08 /**< 8 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_16	0x10 /**< 16 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_32	0x20 /**< 32 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_64	0x40 /**< 64 micro-frames */
+#define XUSBPS_CMD_ITHRESHOLD_MAX	XUSBPS_CMD_ITHRESHOLD_64
+#define XUSBPS_CMD_ITHRESHOLD_DEFAULT	XUSBPS_CMD_ITHRESHOLD_8
+/* @} */
+
+
+
+/** @name USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER)
+ * bit positions.
+ *  @{
+ */
+#define XUSBPS_IXR_UI_MASK	0x00000001 /**< USB Transaction Complete */
+#define XUSBPS_IXR_UE_MASK	0x00000002 /**< Transaction Error */
+#define XUSBPS_IXR_PC_MASK	0x00000004 /**< Port Change Detect */
+#define XUSBPS_IXR_FRE_MASK	0x00000008 /**< Frame List Rollover */
+#define XUSBPS_IXR_AA_MASK	0x00000020 /**< Async Advance */
+#define XUSBPS_IXR_UR_MASK	0x00000040 /**< RESET Received */
+#define XUSBPS_IXR_SR_MASK	0x00000080 /**< Start of Frame */
+#define XUSBPS_IXR_SLE_MASK	0x00000100 /**< Device Controller Suspend */
+#define XUSBPS_IXR_ULPI_MASK	0x00000400 /**< ULPI IRQ */
+#define XUSBPS_IXR_HCH_MASK	0x00001000 /**< Host Controller Halted
+						* Read Only */
+#define XUSBPS_IXR_RCL_MASK	0x00002000 /**< USB Reclamation  Read Only */
+#define XUSBPS_IXR_PS_MASK	0x00004000 /**< Periodic Sched Status
+						* Read Only */
+#define XUSBPS_IXR_AS_MASK	0x00008000 /**< Async Sched Status Read only */
+#define XUSBPS_IXR_NAK_MASK	0x00010000 /**< NAK IRQ */
+#define XUSBPS_IXR_UA_MASK	0x00040000 /**< USB Host Async IRQ */
+#define XUSBPS_IXR_UP_MASK	0x00080000 /**< USB Host Periodic IRQ */
+#define XUSBPS_IXR_TI0_MASK	0x01000000 /**< Timer 0 Interrupt */
+#define XUSBPS_IXR_TI1_MASK	0x02000000 /**< Timer 1 Interrupt */
+
+#define XUSBPS_IXR_ALL			(XUSBPS_IXR_UI_MASK	| \
+					 XUSBPS_IXR_UE_MASK		| \
+					 XUSBPS_IXR_PC_MASK	| \
+					 XUSBPS_IXR_FRE_MASK	| \
+					 XUSBPS_IXR_AA_MASK	| \
+					 XUSBPS_IXR_UR_MASK		| \
+					 XUSBPS_IXR_SR_MASK		| \
+					 XUSBPS_IXR_SLE_MASK	| \
+					 XUSBPS_IXR_ULPI_MASK		| \
+					 XUSBPS_IXR_HCH_MASK	| \
+					 XUSBPS_IXR_RCL_MASK	| \
+					 XUSBPS_IXR_PS_MASK | \
+					 XUSBPS_IXR_AS_MASK		| \
+					 XUSBPS_IXR_NAK_MASK		| \
+					 XUSBPS_IXR_UA_MASK	| \
+					 XUSBPS_IXR_UP_MASK | \
+					 XUSBPS_IXR_TI0_MASK | \
+					 XUSBPS_IXR_TI1_MASK)
+					/**< Mask for ALL IRQ types */
+/* @} */
+
+
+/** @name USB Mode Register (MODE) bit positions.
+ *  @{
+ */
+#define XUSBPS_MODE_CM_MASK		0x00000003 /**< Controller Mode Select */
+#define XUSBPS_MODE_CM_IDLE_MASK	0x00000000
+#define XUSBPS_MODE_CM_DEVICE_MASK	0x00000002
+#define XUSBPS_MODE_CM_HOST_MASK	0x00000003
+#define XUSBPS_MODE_ES_MASK		0x00000004 /**< USB Endian Select */
+#define XUSBPS_MODE_SLOM_MASK		0x00000008 /**< USB Setup Lockout Mode Disable */
+#define XUSBPS_MODE_SDIS_MASK		0x00000010
+#define XUSBPS_MODE_VALID_MASK		0x0000001F
+
+/* @} */
+
+
+/** @name USB Device Address Register (DEVICEADDR) bit positions.
+ *  @{
+ */
+#define XUSBPS_DEVICEADDR_DEVICEAADV_MASK	0x01000000
+					/**< Device Addr Auto Advance */
+#define XUSBPS_DEVICEADDR_ADDR_MASK		0xFE000000
+					/**< Device Address */
+#define XUSBPS_DEVICEADDR_ADDR_SHIFT		25
+					/**< Address shift */
+#define XUSBPS_DEVICEADDR_MAX			127
+					/**< Biggest allowed address */
+/* @} */
+
+/** @name USB TT Control Register (TTCTRL) bit positions.
+ *  @{
+ */
+#define XUSBPS_TTCTRL_HUBADDR_MASK	0x7F000000 /**< TT Hub Address */
+/* @} */
+
+
+/** @name USB Burst Size Register (BURSTSIZE) bit posisions.
+ *  @{
+ */
+#define XUSBPS_BURSTSIZE_RX_MASK	0x000000FF /**< RX Burst Length */
+#define XUSBPS_BURSTSIZE_TX_MASK	0x0000FF00 /**< TX Burst Length */
+/* @} */
+
+
+/** @name USB Tx Fill Tuning Register (TXFILL) bit positions.
+ *  @{
+ */
+#define XUSBPS_TXFILL_OVERHEAD_MASK	0x000000FF
+					/**< Scheduler Overhead */
+#define XUSBPS_TXFILL_HEALTH_MASK	0x00001F00
+					/**< Scheduler Health Cntr */
+#define XUSBPS_TXFILL_BURST_MASK	0x003F0000
+					/**< FIFO Burst Threshold */
+/* @} */
+
+
+/** @name USB ULPI Viewport Register (ULPIVIEW) bit positions.
+ *  @{
+ */
+#define XUSBPS_ULPIVIEW_DATWR_MASK	0x000000FF /**< ULPI Data Write */
+#define XUSBPS_ULPIVIEW_DATRD_MASK	0x0000FF00 /**< ULPI Data Read */
+#define XUSBPS_ULPIVIEW_ADDR_MASK	0x00FF0000 /**< ULPI Data Address */
+#define XUSBPS_ULPIVIEW_PORT_MASK	0x07000000 /**< ULPI Port Number */
+#define XUSBPS_ULPIVIEW_SS_MASK	0x08000000 /**< ULPI Synchronous State */
+#define XUSBPS_ULPIVIEW_RW_MASK	0x20000000 /**< ULPI Read/Write Control */
+#define XUSBPS_ULPIVIEW_RUN_MASK	0x40000000 /**< ULPI Run */
+#define XUSBPS_ULPIVIEW_WU_MASK	0x80000000 /**< ULPI Wakeup */
+/* @} */
+
+
+/** @name Port Status Control Register bit positions.
+ *  @{
+ */
+#define XUSBPS_PORTSCR_CCS_MASK  0x00000001 /**< Current Connect Status */
+#define XUSBPS_PORTSCR_CSC_MASK  0x00000002 /**< Connect Status Change */
+#define XUSBPS_PORTSCR_PE_MASK	  0x00000004 /**< Port Enable/Disable */
+#define XUSBPS_PORTSCR_PEC_MASK  0x00000008 /**< Port Enable/Disable Change */
+#define XUSBPS_PORTSCR_OCA_MASK  0x00000010 /**< Over-current Active */
+#define XUSBPS_PORTSCR_OCC_MASK  0x00000020 /**< Over-current Change */
+#define XUSBPS_PORTSCR_FPR_MASK  0x00000040 /**< Force Port Resume */
+#define XUSBPS_PORTSCR_SUSP_MASK 0x00000080 /**< Suspend */
+#define XUSBPS_PORTSCR_PR_MASK	  0x00000100 /**< Port Reset */
+#define XUSBPS_PORTSCR_HSP_MASK  0x00000200 /**< High Speed Port */
+#define XUSBPS_PORTSCR_LS_MASK	  0x00000C00 /**< Line Status */
+#define XUSBPS_PORTSCR_PP_MASK	  0x00001000 /**< Port Power */
+#define XUSBPS_PORTSCR_PO_MASK	  0x00002000 /**< Port Owner */
+#define XUSBPS_PORTSCR_PIC_MASK  0x0000C000 /**< Port Indicator Control */
+#define XUSBPS_PORTSCR_PTC_MASK  0x000F0000 /**< Port Test Control */
+#define XUSBPS_PORTSCR_WKCN_MASK 0x00100000 /**< Wake on Connect Enable */
+#define XUSBPS_PORTSCR_WKDS_MASK 0x00200000 /**< Wake on Disconnect Enable */
+#define XUSBPS_PORTSCR_WKOC_MASK 0x00400000 /**< Wake on Over-current Enable */
+#define XUSBPS_PORTSCR_PHCD_MASK 0x00800000 /**< PHY Low Power Suspend -
+						* Clock Disable */
+#define XUSBPS_PORTSCR_PFSC_MASK 0x01000000 /**< Port Force Full Speed
+						* Connect */
+#define XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 /**< Port Speed */
+/* @} */
+
+
+/** @name On-The-Go Status Control Register (OTGCSR) bit positions.
+ *  @{
+ */
+#define XUSBPS_OTGSC_VD_MASK	 0x00000001 /**< VBus Discharge Bit */
+#define XUSBPS_OTGSC_VC_MASK	 0x00000002 /**< VBus Charge Bit */
+#define XUSBPS_OTGSC_HAAR_MASK	 0x00000004 /**< HW Assist Auto Reset
+				 		       *  Enable Bit */
+#define XUSBPS_OTGSC_OT_MASK	 0x00000008 /**< OTG Termination Bit */
+#define XUSBPS_OTGSC_DP_MASK	 0x00000010 /**< Data Pulsing Pull-up
+				 		       *  Enable Bit */
+#define XUSBPS_OTGSC_IDPU_MASK	 0x00000020 /**< ID Pull-up Enable Bit */
+#define XUSBPS_OTGSC_HADP_MASK	 0x00000040 /**< HW Assist Data Pulse
+							* Enable Bit */
+#define XUSBPS_OTGSC_HABA_MASK	 0x00000080 /**< USB Hardware Assist
+						       *  B Disconnect to A
+						       *  Connect Enable Bit */
+#define XUSBPS_OTGSC_ID_MASK	 0x00000100 /**< ID Status Flag */
+#define XUSBPS_OTGSC_AVV_MASK	 0x00000200 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASV_MASK	 0x00000400 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSV_MASK	 0x00000800 /**< USB B Session Valid Status Flag */
+#define XUSBPS_OTGSC_BSE_MASK	 0x00001000 /**< USB B Session End Status Flag */
+#define XUSBPS_OTGSC_1MST_MASK	 0x00002000 /**< USB 1 Millisecond Timer Status Flag */
+#define XUSBPS_OTGSC_DPS_MASK	 0x00004000 /**< Data Pulse Status Flag */
+#define XUSBPS_OTGSC_IDIS_MASK	 0x00010000 /**< USB ID Interrupt Status Flag */
+#define XUSBPS_OTGSC_AVVIS_MASK 0x00020000 /**< USB A VBus Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_ASVIS_MASK 0x00040000 /**< USB A Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSVIS_MASK 0x00080000 /**< USB B Session Valid Interrupt Status Flag */
+#define XUSBPS_OTGSC_BSEIS_MASK 0x00100000 /**< USB B Session End Interrupt Status Flag */
+#define XUSBPS_OTGSC_1MSS_MASK	 0x00200000 /**< 1 Millisecond Timer Interrupt Status Flag */
+#define XUSBPS_OTGSC_DPIS_MASK	 0x00400000 /**< Data Pulse Interrupt Status Flag */
+#define XUSBPS_OTGSC_IDIE_MASK	 0x01000000 /**< ID Interrupt Enable Bit */
+#define XUSBPS_OTGSC_AVVIE_MASK 0x02000000 /**< USB A VBus Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_ASVIE_MASK 0x04000000 /**< USB A Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSVIE_MASK 0x08000000 /**< USB B Session Valid Interrupt Enable Bit */
+#define XUSBPS_OTGSC_BSEE_MASK	 0x10000000 /**< USB B Session End Interrupt Enable Bit */
+#define XUSBPS_OTGSC_1MSE_MASK	 0x20000000 /**< 1 Millisecond Timer
+						* Interrupt Enable Bit */
+#define XUSBPS_OTGSC_DPIE_MASK	 0x40000000 /**< Data Pulse Interrupt
+							* Enable Bit */
+
+#define XUSBPS_OTG_ISB_ALL	(XUSBPS_OTGSC_IDIS_MASK |\
+				XUSBPS_OTGSC_AVVIS_MASK | \
+				XUSBPS_OTGSC_ASVIS_MASK | \
+				XUSBPS_OTGSC_BSVIS_MASK | \
+				XUSBPS_OTGSC_BSEIS_MASK | \
+				XUSBPS_OTGSC_1MSS_MASK | \
+				XUSBPS_OTGSC_DPIS_MASK)
+				/** Mask for All IRQ status masks */
+
+#define XUSBPS_OTG_IEB_ALL	(XUSBPS_OTGSC_IDIE_MASK |\
+				XUSBPS_OTGSC_AVVIE_MASK | \
+				XUSBPS_OTGSC_ASVIE_MASK | \
+				XUSBPS_OTGSC_BSVIE_MASK | \
+				XUSBPS_OTGSC_BSEE_IEB_MASK | \
+				XUSBPS_OTGSC_1MSE_MASK | \
+				XUSBPS_OTGSC_DPIE_MASK)
+				/** Mask for All IRQ Enable masks */
+/* @} */
+
+
+/**< Alignment of the Device Queue Head List BASE. */
+#define XUSBPS_dQH_BASE_ALIGN		2048
+
+/**< Alignment of a Device Queue Head structure. */
+#define XUSBPS_dQH_ALIGN		64
+
+/**< Alignment of a Device Transfer Descriptor structure. */
+#define XUSBPS_dTD_ALIGN		32
+
+/**< Size of one RX buffer for a OUT Transfer Descriptor. */
+#define XUSBPS_dTD_BUF_SIZE		4096
+
+/**< Maximum size of one RX/TX buffer. */
+#define XUSBPS_dTD_BUF_MAX_SIZE	16*1024
+
+/**< Alignment requirement for Transfer Descriptor buffers. */
+#define XUSBPS_dTD_BUF_ALIGN		4096
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the base address for the USB registers.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XUsbPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XUsbPs_ReadReg(BaseAddress, RegOffset) \
+				Xil_In32(BaseAddress + (RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	BaseAddress is the the base address for the USB registers.
+* @param	RegOffset is the register offset to be written.
+* @param	Data is the the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XUsbPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+ *****************************************************************************/
+#define XUsbPs_WriteReg(BaseAddress, RegOffset, Data) \
+				Xil_Out32(BaseAddress + (RegOffset), (Data))
+
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the USB PS interface
+ */
+void XUsbPs_ResetHw(u32 BaseAddress);
+/************************** Variable Definitions ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XUSBPS_L_H */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
new file mode 100644
index 0000000..83463bd
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c
@@ -0,0 +1,472 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/******************************************************************************/
+/**
+ * @file xusbps_intr.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * This file contains the functions that are related to interrupt processing
+ * for the EPB USB driver.
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ----------------------------------------------------------
+ * 1.00a jz  10/10/10 First release
+ * 1.03a nm  09/21/12 Fixed CR#678977. Added proper sequence for setup packet
+ *                    handling.
+ * 2.3   bss 01/19/16 Modified XUsbPs_EpQueueRequest function to fix CR#873972
+ *            (moving of dTD Head/Tail Pointers properly).
+ * 
    
+ ******************************************************************************/
+
+/***************************** Include Files **********************************/
+
+#include "xusbps.h"
+#include "xusbps_endpoint.h"
+
+/************************** Constant Definitions ******************************/
+
+/**************************** Type Definitions ********************************/
+
+/***************** Macros (Inline Functions) Definitions **********************/
+
+/************************** Variable Definitions ******************************/
+
+/************************** Function Prototypes *******************************/
+
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl);
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts);
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr);
+
+/*****************************************************************************/
+/**
+* This function is the first-level interrupt handler for the USB core. All USB
+* interrupts will be handled here. Depending on the type of the interrupt,
+* second level interrupt handler may be called. Second level interrupt
+* handlers will be registered by the user using the:
+*    XUsbPs_IntrSetHandler()
+* and/or
+*    XUsbPs_EpSetHandler()
+* functions.
+*
+*
+* @param	HandlerRef is a Reference passed to the interrupt register
+*		function. In our case this will be a pointer to the XUsbPs
+*		instance.
+*
+* @return	None
+*
+* @note		None
+*
+******************************************************************************/
+void XUsbPs_IntrHandler(void *HandlerRef)
+{
+	XUsbPs	*InstancePtr;
+
+	u32	IrqSts;
+
+	Xil_AssertVoid(HandlerRef != NULL);
+
+	InstancePtr = (XUsbPs *) HandlerRef;
+
+	/* Handle controller (non-endpoint) related interrupts. */
+	IrqSts = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_ISR_OFFSET);
+
+	/* Clear the interrupt status register. */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_ISR_OFFSET, IrqSts);
+
+	/* Nak interrupt, used to respond to host's IN request */
+	if(IrqSts & XUSBPS_IXR_NAK_MASK) {
+		/* Ack the hardware	 */
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPNAKISR_OFFSET,
+			XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPNAKISR_OFFSET));
+	}
+
+
+	/***************************************************************
+	 *
+	 * Handle general interrupts. Endpoint interrupts will be handler
+	 * later.
+	 *
+	 */
+
+	/* RESET interrupt.*/
+	if (IrqSts & XUSBPS_IXR_UR_MASK) {
+		XUsbPs_IntrHandleReset(InstancePtr, IrqSts);
+		return;
+	}
+
+	/* Check if we have a user handler that needs to be called. Note that
+	 * this is the handler for general interrupts. Endpoint interrupts will
+	 * be handled below.
+	 */
+	if ((IrqSts & InstancePtr->HandlerMask) && InstancePtr->HandlerFunc) {
+		(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+	}
+
+
+	/***************************************************************
+	 *
+	 * Handle Endpoint interrupts.
+	 *
+	 */
+	if (IrqSts & XUSBPS_IXR_UI_MASK) {
+		u32	EpStat;
+		u32	EpCompl;
+
+		/* ENDPOINT 0 SETUP PACKET HANDLING
+		 *
+		 * Check if we got a setup packet on endpoint 0. Currently we
+		 * only check for setup packets on endpoint 0 as we would not
+		 * expect setup packets on any other endpoint (even though it
+		 * is possible to send setup packets on other endpoints).
+		 */
+		EpStat = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPSTAT_OFFSET);
+		if (EpStat & 0x0001) {
+			/* Handle the setup packet */
+			XUsbPs_IntrHandleEp0Setup(InstancePtr);
+
+			/* Re-Prime the endpoint.
+			 * Endpoint is de-primed if a setup packet comes in.
+	 		 */
+			XUsbPs_EpPrime(InstancePtr, 0, XUSBPS_EP_DIRECTION_OUT);
+		}
+
+		/* Check for RX and TX complete interrupts. */
+		EpCompl = XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUSBPS_EPCOMPL_OFFSET);
+
+
+		/* ACK the complete interrupts. */
+		XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPCOMPL_OFFSET, EpCompl);
+
+		/* Check OUT (RX) endpoints. */
+		if (EpCompl & XUSBPS_EP_OUT_MASK) {
+			XUsbPs_IntrHandleRX(InstancePtr, EpCompl);
+		}
+
+		/* Check IN (TX) endpoints. */
+		if (EpCompl & XUSBPS_EP_IN_MASK) {
+			XUsbPs_IntrHandleTX(InstancePtr, EpCompl);
+		}
+	}
+}
+
+
+/*****************************************************************************/
+/**
+* This function registers the user callback handler for controller
+* (non-endpoint) interrupts.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	CallBackFunc is the Callback function to register.
+*		CallBackFunc may be NULL to clear the entry.
+* @param	CallBackRef is the user data reference passed to the
+*		callback function. CallBackRef may be NULL.
+* @param	Mask is the User interrupt mask. Defines which interrupts
+*		will cause the callback to be called.
+*
+* @return
+*		- XST_SUCCESS: Callback registered successfully.
+*		- XST_FAILURE: Callback could not be registered.
+*
+* @note		None.
+*
+******************************************************************************/
+int XUsbPs_IntrSetHandler(XUsbPs *InstancePtr,
+			   XUsbPs_IntrHandlerFunc CallBackFunc,
+			   void *CallBackRef, u32 Mask)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	InstancePtr->HandlerFunc	= CallBackFunc;
+	InstancePtr->HandlerRef		= CallBackRef;
+	InstancePtr->HandlerMask	= Mask;
+
+	return XST_SUCCESS;
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles TX buffer interrupts. It is called by the interrupt
+* when a transmit complete interrupt occurs. It returns buffers of completed
+* descriptors to the caller.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+* @param	EpCompl is the Bit mask of endpoints that caused a transmit
+*		complete interrupt.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleTX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+	int Index;
+	u32 Mask;
+	int NumEp;
+
+	/* Check all endpoints for TX complete bits.
+	 */
+	Mask	= 0x00010000;
+	NumEp	= InstancePtr->DeviceConfig.NumEndpoints;
+
+	/* Check for every endpoint if its TX complete bit is
+	 * set.
+	 */
+	for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+		XUsbPs_EpIn	*Ep;
+
+		if (!(EpCompl & Mask)) {
+			continue;
+		}
+		/* The TX complete bit for this endpoint is
+		 * set. Walk the list of descriptors to see
+		 * which ones are completed.
+		 */
+		Ep = &InstancePtr->DeviceConfig.Ep[Index].In;
+		do {
+
+			XUsbPs_dTDInvalidateCache(Ep->dTDTail);
+
+			/* If the descriptor is not active then the buffer has
+			 * not been sent yet.
+			 */
+			if (XUsbPs_dTDIsActive(Ep->dTDTail)) {
+				break;
+			}
+
+			if (Ep->HandlerFunc) {
+				void *BufPtr;
+
+				BufPtr = (void *) XUsbPs_ReaddTD(Ep->dTDTail,
+							XUSBPS_dTDUSERDATA);
+
+				Ep->HandlerFunc(Ep->HandlerRef, Index,
+						XUSBPS_EP_EVENT_DATA_TX,
+								BufPtr);
+			}
+
+			Ep->dTDTail = XUsbPs_dTDGetNLP(Ep->dTDTail);
+		} while(Ep->dTDTail != Ep->dTDHead);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+ * This function handles RX buffer interrupts. It is called by the interrupt
+ * when a receive complete interrupt occurs. It notifies the callback functions
+ * that have been registered with the individual endpoints that data has been
+ * received.
+ *
+ * @param	InstancePtr
+ * 		Pointer to the XUsbPs instance of the controller.
+ *
+ * @param	EpCompl
+ * 		Bit mask of endpoints that caused a receive complete interrupt.
+ * @return
+ *		none
+ *
+ ******************************************************************************/
+static void XUsbPs_IntrHandleRX(XUsbPs *InstancePtr, u32 EpCompl)
+{
+	XUsbPs_EpOut	*Ep;
+	int		Index;
+	u32		Mask;
+	int		NumEp;
+
+	/* Check all endpoints for RX complete bits. */
+	Mask	= 0x00000001;
+	NumEp	= InstancePtr->DeviceConfig.NumEndpoints;
+
+
+	/* Check for every endpoint if its RX complete bit is set.*/
+	for (Index = 0; Index < NumEp; Index++, Mask <<= 1) {
+		int numP = 0;
+
+		if (!(EpCompl & Mask)) {
+			continue;
+		}
+		Ep = &InstancePtr->DeviceConfig.Ep[Index].Out;
+
+		XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+
+		/* Handle all finished dTDs */
+		while (!XUsbPs_dTDIsActive(Ep->dTDCurr)) {
+			numP += 1;
+			if (Ep->HandlerFunc) {
+				Ep->HandlerFunc(Ep->HandlerRef, Index,
+						XUSBPS_EP_EVENT_DATA_RX, NULL);
+			}
+
+			Ep->dTDCurr = XUsbPs_dTDGetNLP(Ep->dTDCurr);
+			XUsbPs_dTDInvalidateCache(Ep->dTDCurr);
+		}
+		/* Re-Prime the endpoint.*/
+		XUsbPs_EpPrime(InstancePtr, Index, XUSBPS_EP_DIRECTION_OUT);
+	}
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a RESET interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param	InstancePtr is pointer to the XUsbPs instance of the controller
+* @param	IrqSts is the Interrupt status register content.
+*		To be passed on to the user.
+*
+* @return	None
+*
+* @Note		None.
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleReset(XUsbPs *InstancePtr, u32 IrqSts)
+{
+	int Timeout;
+
+	/* Clear all setup token semaphores by reading the
+	 * XUSBPS_EPSTAT_OFFSET register and writing its value back to
+	 * itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress, XUSBPS_EPSTAT_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPSTAT_OFFSET));
+
+	/* Clear all the endpoint complete status bits by reading the
+	 * XUSBPS_EPCOMPL_OFFSET register and writings its value back
+	 * to itself.
+	 */
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XUSBPS_EPCOMPL_OFFSET,
+		XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPCOMPL_OFFSET));
+
+	/* Cancel all endpoint prime status by waiting until all bits
+	 * in XUSBPS_EPPRIME_OFFSET are 0 and then writing 0xFFFFFFFF
+	 * to XUSBPS_EPFLUSH_OFFSET.
+	 *
+	 * Avoid hanging here by using a Timeout counter...
+	 */
+	Timeout = XUSBPS_TIMEOUT_COUNTER;
+	while ((XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUSBPS_EPPRIME_OFFSET) &
+					XUSBPS_EP_ALL_MASK) && --Timeout) {
+		/* NOP */
+	}
+	XUsbPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_EPFLUSH_OFFSET, 0xFFFFFFFF);
+
+	/* Make sure that the reset bit in XUSBPS_PORTSCR1_OFFSET is
+	 * still set at this point. If the code gets to this point and
+	 * the reset bit has already been cleared we are in trouble and
+	 * hardware reset is necessary.
+	 */
+	if (!(XUsbPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUSBPS_PORTSCR1_OFFSET) &
+				XUSBPS_PORTSCR_PR_MASK)) {
+		/* Send a notification to the user that a hardware
+		 * RESET is required. At this point we can only hope
+		 * that the user registered an interrupt handler and
+		 * will issue a hardware RESET.
+		 */
+		if (InstancePtr->HandlerFunc) {
+			(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef,
+						   IrqSts);
+		}
+		else {
+			for (;;);
+		}
+
+		/* If we get here there is nothing more to do. The user
+		 * should have reset the core.
+		 */
+		return;
+	}
+
+	/* Check if we have a user handler that needs to be called.
+	 */
+	if (InstancePtr->HandlerFunc) {
+		(InstancePtr->HandlerFunc)(InstancePtr->HandlerRef, IrqSts);
+	}
+
+	/* We are done. After RESET we don't proceed in the interrupt
+	 * handler.
+	 */
+}
+
+
+/*****************************************************************************/
+/**
+* This function handles a Setup Packet interrupt. It will notify the interrupt
+* handler callback of the RESET condition.
+*
+* @param	InstancePtr is a pointer to the XUsbPs instance of the
+*		controller.
+*
+* @return	None
+*
+* @Note 	None
+*
+******************************************************************************/
+static void XUsbPs_IntrHandleEp0Setup(XUsbPs *InstancePtr)
+{
+
+	XUsbPs_EpOut	*Ep;
+
+	/* Notifiy the user. */
+	Ep = &InstancePtr->DeviceConfig.Ep[0].Out;
+
+	if (Ep->HandlerFunc) {
+		Ep->HandlerFunc(Ep->HandlerRef, 0,
+				XUSBPS_EP_EVENT_SETUP_DATA_RECEIVED, NULL);
+	}
+}
+
+
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
new file mode 100644
index 0000000..a2070a7
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal 
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+ *
+ * @file xusbps_sinit.c
+* @addtogroup usbps_v2_4
+* @{
+ *
+ * The implementation of the XUsbPs driver's static initialzation
+ * functionality.
+ *
+ * 
    + * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.00a wgr  10/10/10 First release
+ * 
    
+ *
+ *****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xusbps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+extern XUsbPs_Config XUsbPs_ConfigTable[];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the controller configuration based on the unique controller ID. A
+* table contains the configuration info for each controller in the system.
+*
+* @param	DeviceID is the ID of the controller to look up the
+*		configuration for.
+*
+* @return
+*		A pointer to the configuration found or NULL if the specified
+*		controller ID was not found.
+*
+******************************************************************************/
+XUsbPs_Config *XUsbPs_LookupConfig(u16 DeviceID)
+{
+	XUsbPs_Config *CfgPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XUSBPS_NUM_INSTANCES; Index++) {
+		if (XUsbPs_ConfigTable[Index].DeviceID == DeviceID) {
+			CfgPtr = &XUsbPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
new file mode 100644
index 0000000..92a8656
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.c
@@ -0,0 +1,1831 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.c
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This file contains the driver API functions that can be used to access
+* the XADC device.
+*
+* Refer to the xadcps.h header file for more information about this driver.
+*
+* @note 	None.
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			to fix CR #693371
+* 2.1   bss    08/05/14	Modified Assert for XAdcPs_SetSingleChParams to fix
+*			CR #807563.
+* 2.2	bss	   04/27/14 Modified to use correct Device Config base address
+*						(CR#854437).
+* 
    
+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xadcps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data);
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset);
+
+
+/************************** Variable Definitions ****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function initializes a specific XAdcPs device/instance. This function
+* must be called prior to using the XADC device.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ConfigPtr points to the XAdcPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*
+* @note		The user needs to first call the XAdcPs_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XAdcPs_CfgInitialize() API.
+*
+******************************************************************************/
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr, XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+
+	u32 RegValue;
+	/*
+	 * Assert the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+
+	/*
+	 * Set the values read from the device config and the base address.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	/* Write Unlock value to Device Config Unlock register */
+	XAdcPs_WriteReg(XPAR_XDCFG_0_BASEADDR,
+				XADCPS_UNLK_OFFSET, XADCPS_UNLK_VALUE);
+
+	/* Enable the PS access of xadc and set FIFO thresholds */
+
+	RegValue = XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+			XADCPS_CFG_OFFSET);
+
+	RegValue = RegValue | XADCPS_CFG_ENABLE_MASK |
+			XADCPS_CFG_CFIFOTH_MASK | XADCPS_CFG_DFIFOTH_MASK;
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+					XADCPS_CFG_OFFSET, RegValue);
+
+	/* Release xadc from reset */
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+						XADCPS_MCTL_OFFSET, 0x00);
+
+	/*
+	 * Indicate the instance is now ready to use and
+	 * initialized without error.
+	 */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetConfigRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET, Data);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Config Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetConfigRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Config Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_CFG_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous Status Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Miscellaneous
+*		Status Register. Use the XADCPS_MSTS_*_MASK constants defined
+*		in xadcps_hw.h to interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscStatus(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous Status Register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MSTS_OFFSET);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions sets the contents of the Miscellaneous Control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Data is the 32 bit data to be written to the Register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetMiscCtrlRegister(XAdcPs *InstancePtr, u32 Data)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write to the Miscellaneous control register Register.
+	 */
+	 XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, Data);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The functions reads the contents of the Miscellaneous control register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	A 32-bit value representing the contents of the Config Register.
+*		Use the XADCPS_SR_*_MASK constants defined in xadcps_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetMiscCtrlRegister(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Miscellaneous control register and return the value.
+	 */
+	return XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This function resets the XADC Hard Macro in the device.
+*
+* @param	InstancePtr is a pointer to the Xxadc instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XAdcPs_Reset(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Generate the reset by Control
+	 * register and release from reset
+	 */
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, 0x10);
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,
+				XADCPS_MCTL_OFFSET, 0x00);
+}
+
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number. Use the XADCPS_CH_* defined in
+*		the file xadcps.h.
+*		The valid channels are
+*		- 0 to 6
+*		- 13 to 31
+*
+* @return	A 16-bit value representing the ADC converted data for the
+*		specified channel. The XADC Monitor/ADC device guarantees
+* 		a 10 bit resolution for the ADC converted data and data is the
+*		10 MSB bits of the 16 data read from the device.
+*
+* @note		The channels 7,8,9 are used for calibration of the device and
+*		hence there is no associated data with this channel.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel)
+{
+
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			 ((Channel >= XADCPS_CH_VCCPINT) &&
+			 (Channel <= XADCPS_CH_AUX_MAX)));
+
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+						(XADCPS_TEMP_OFFSET +
+						Channel));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	CoeffType specifies the calibration coefficient
+*		to be read. Use XADCPS_CALIB_* constants defined in xadcps.h to
+*		specify the calibration coefficient to be read.
+*
+* @return	A 16-bit value representing the calibration coefficient.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(CoeffType <= XADCPS_CALIB_GAIN_ERROR_COEFF);
+
+	/*
+	 * Read the selected calibration coefficient.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_ADC_A_SUPPLY_CALIB_OFFSET +
+					CoeffType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* specified parameters. Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in
+* xadcps.h to specify the parameters (Temperature, VccInt, VccAux, VBram,
+* VccPInt, VccPAux and VccPDro).
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	MeasurementType specifies the parameter for which the
+*		Minimum/Maximum measurement has to be read.
+*		Use XADCPS_MAX_* and XADCPS_MIN_* constants defined in xadcps.h to
+*		specify the data to be read.
+*
+* @return	A 16-bit value representing the maximum/minimum measurement for
+*		specified parameter.
+*		The XADC device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((MeasurementType <= XADCPS_MAX_VCCPDRO) ||
+			((MeasurementType >= XADCPS_MIN_VCCPINT) &&
+			(MeasurementType <= XADCPS_MIN_VCCPDRO)))
+
+	/*
+	 * Read and return the specified Minimum/Maximum measurement.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					(XADCPS_MAX_TEMP_OFFSET +
+					MeasurementType));
+	return (u16) RegData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Average is the number of samples of averaging programmed to the
+*		Configuration Register 0. Use the XADCPS_AVG_* definitions defined
+*		in xadcps.h file :
+*		- XADCPS_AVG_0_SAMPLES for no averaging
+*		- XADCPS_AVG_16_SAMPLES for 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES for 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES for 256 samples of averaging
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average)
+{
+	u32 RegData;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Average <= XADCPS_AVG_256_SAMPLES);
+
+	/*
+	 * Write the averaging value into the Configuration Register 0.
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_AVG_VALID_MASK);
+
+	RegData |=  (((u32) Average << XADCPS_CFR0_AVG_SHIFT));
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegData);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The averaging read from the Configuration Register 0 is
+*		returned. Use the XADCPS_AVG_* bit definitions defined in
+*		xadcps.h file to interpret the returned value :
+*		- XADCPS_AVG_0_SAMPLES means no averaging
+*		- XADCPS_AVG_16_SAMPLES means 16 samples of averaging
+*		- XADCPS_AVG_64_SAMPLES means 64 samples of averaging
+*		- XADCPS_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr)
+{
+	u32 Average;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging value from the Configuration Register 0.
+	 */
+	Average = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_AVG_VALID_MASK;
+
+
+	return ((u8) (Average >> XADCPS_CFR0_AVG_SHIFT));
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Channel is the channel number for the singel channel mode.
+*		The valid channels are 0 to 6, 8, and 13 to 31.
+*		If the external Mux is used then this specifies the channel
+*		oonnected to the external Mux. Please read the Device Spec
+*		to know which channels are valid.
+* @param 	IncreaseAcqCycles is a boolean parameter which specifies whether
+*		the Acquisition time for the external channels has to be
+*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+*		default 4 ADCCLK cycles (specify FALSE). This parameter is
+*		only valid for the external channels.
+* @param 	IsDifferentialMode is a boolean parameter which specifies
+*		unipolar(specify FALSE) or differential mode (specify TRUE) for
+*		the analog inputs. The 	input mode is only valid for the
+*		external channels.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note
+*		- The number of samples for the averaging for all the channels
+*		is set by using the function XAdcPs_SetAvg.
+*		- The calibration of the device is done by doing a ADC
+*		conversion on the calibration channel(channel 8). The input
+*		parameters IncreaseAcqCycles, IsDifferentialMode and
+*		IsEventMode are not valid for this channel
+*
+*
+*****************************************************************************/
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XADCPS_CH_VBRAM) ||
+			(Channel == XADCPS_CH_ADC_CALIB) ||
+			((Channel >= XADCPS_CH_VCCPINT) &&
+			(Channel <= XADCPS_CH_AUX_MAX)));
+	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+			(IncreaseAcqCycles == FALSE));
+	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+			(IsDifferentialMode == FALSE));
+
+	/*
+	 * Check if the device is in single channel mode else return failure
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+		XADCPS_SEQ_MODE_SINGCHAN)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					XADCPS_CFR0_AVG_VALID_MASK;
+
+	/*
+	 * Select the number of acquisition cycles. The acquisition cycles is
+	 * only valid for the external channels.
+	 */
+	if (IncreaseAcqCycles == TRUE) {
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_ACQ_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+
+	}
+
+	/*
+	 * Select the input mode. The input mode is only valid for the
+	 * external channels.
+	 */
+	if (IsDifferentialMode == TRUE) {
+
+		if (((Channel >= XADCPS_CH_AUX_MIN) &&
+			(Channel <= XADCPS_CH_AUX_MAX)) ||
+			(Channel == XADCPS_CH_VPVN)){
+			RegValue |= XADCPS_CFR0_DU_MASK;
+		} else {
+			return XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Select the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	}
+
+	/*
+	 * Write the given values into the Configuration Register 0.
+	 */
+	RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+				RegValue);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+*		in the Configuration Register 1.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will be
+*		disabled. This mask is formed by OR'ing XADCPS_CFR1_ALM_*_MASK and
+*		XADCPS_CFR1_OT_MASK masks defined in xadcps_hw.h.
+*
+* @return	None.
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that the alarms for bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The alarm outputs specified by the AlmEnableMask are negated
+*		before writing to the Configuration Register 1.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr, XADCPS_CFR1_OFFSET);
+
+	RegValue &= (u32)~XADCPS_CFR1_ALM_ALL_MASK;
+	RegValue |= (~AlmEnableMask & XADCPS_CFR1_ALM_ALL_MASK);
+
+	/*
+	 * Enable/disables the alarm enables for the specified alarm bits in the
+	 * Configuration Register 1.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	This is the bit-mask of the enabled alarm outputs in the
+*		Configuration Register 1. Use the masks XADCPS_CFR1_ALM*_* and
+*		XADCPS_CFR1_OT_MASK defined in xadcps_hw.h to interpret the
+*		returned value.
+*		Bit positions of 1 indicate that the alarm output is enabled.
+*		Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that alarms for the bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The enabled alarm outputs returned by this function is the
+*		negated value of the the data read from the Configuration
+*		Register 1.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the status of alarm output enables from the Configuration
+	 * Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_ALM_ALL_MASK;
+	return (u16) (~RegValue & XADCPS_CFR1_ALM_ALL_MASK);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified calibration in the Configuration
+* Register 1 :
+*
+* - XADCPS_CFR1_CAL_ADC_OFFSET_MASK : Calibration 0 -ADC offset correction
+* - XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : Calibration 1 -ADC gain and offset
+*						correction
+* - XADCPS_CFR1_CAL_PS_OFFSET_MASK : Calibration 2 -Power Supply sensor
+*					offset correction
+* - XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Calibration 3 -Power Supply sensor
+*						gain and offset correction
+* - XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Calibration is the Calibration to be applied.
+*		Use XADCPS_CFR1_CAL*_* bits defined in xadcps_hw.h.
+*		Multiple calibrations can be enabled at a time by oring the
+*		XADCPS_CFR1_CAL_ADC_* and XADCPS_CFR1_CAL_PS_* bits.
+*		Calibration can be disabled by specifying
+		XADCPS_CFR1_CAL_DISABLE_MASK;
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(((Calibration >= XADCPS_CFR1_CAL_ADC_OFFSET_MASK) &&
+			(Calibration <= XADCPS_CFR1_CAL_VALID_MASK)) ||
+			(Calibration == XADCPS_CFR1_CAL_DISABLE_MASK));
+
+	/*
+	 * Set the specified calibration in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+
+	RegValue &= (~ XADCPS_CFR1_CAL_VALID_MASK);
+	RegValue |= (Calibration & XADCPS_CFR1_CAL_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the value of the calibration enables from the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The value of the calibration enables in the Configuration
+*		Register 1 :
+*		- XADCPS_CFR1_CAL_ADC_OFFSET_MASK : ADC offset correction
+*		- XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK : ADC gain and offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_OFFSET_MASK : Power Supply sensor offset
+*				correction
+*		- XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK : Power Supply sensor
+*				gain and offset correction
+*		- XADCPS_CFR1_CAL_DISABLE_MASK : No Calibration
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the calibration enables from the Configuration Register 1.
+	 */
+	return (u16) XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_CAL_VALID_MASK;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+*		- Default safe mode (XADCPS_SEQ_MODE_SAFE)
+*		- One pass through sequence (XADCPS_SEQ_MODE_ONEPASS)
+*		- Continuous channel sequencing (XADCPS_SEQ_MODE_CONTINPASS)
+*		- Single Channel/Sequencer off (XADCPS_SEQ_MODE_SINGCHAN)
+*		- Simulataneous sampling mode (XADCPS_SEQ_MODE_SIMUL_SAMPLING)
+*		- Independent mode (XADCPS_SEQ_MODE_INDEPENDENT)
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	SequencerMode is the sequencer mode to be set.
+*		Use XADCPS_SEQ_MODE_* bits defined in xadcps.h.
+* @return	None.
+*
+* @note		Only one of the modes can be enabled at a time. Please
+*		read the Spec of the XADC for further information about the
+*		sequencer modes.
+*
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SequencerMode <= XADCPS_SEQ_MODE_SIMUL_SAMPLING) ||
+			(SequencerMode == XADCPS_SEQ_MODE_INDEPENDENT));
+
+	/*
+	 * Set the specified sequencer mode in the Configuration Register 1.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR1_OFFSET);
+	RegValue &= (~ XADCPS_CFR1_SEQ_VALID_MASK);
+	RegValue |= ((SequencerMode  << XADCPS_CFR1_SEQ_SHIFT) &
+					XADCPS_CFR1_SEQ_VALID_MASK);
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR1_OFFSET,
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The channel sequencer mode :
+*		- XADCPS_SEQ_MODE_SAFE : Default safe mode
+*		- XADCPS_SEQ_MODE_ONEPASS : One pass through sequence
+*		- XADCPS_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+*		- XADCPS_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+*		- XADCPS_SEQ_MODE_SIMUL_SAMPLING : Simulataneous sampling mode
+*		- XADCPS_SEQ_MODE_INDEPENDENT : Independent mode
+*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel sequencer mode from the Configuration Register 1.
+	 */
+	return ((u8) ((XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_CFR1_OFFSET) & XADCPS_CFR1_SEQ_VALID_MASK) >>
+			XADCPS_CFR1_SEQ_SHIFT));
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
+*		Valid values of the divisor are
+*		 - 0 to 255. Values 0, 1, 2 are all mapped to 2.
+*		Refer to the device specification for more details
+*
+* @return	None.
+*
+* @note		- The ADCCLK is an internal clock used by the ADC and is
+*		  synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		  divided by the user selection in the Configuration Register 2.
+*		- There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write the divisor value into the Configuration Register #2.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+			  Divisor << XADCPS_CFR2_CD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The divisor read from the Configuration Register 2.
+*
+* @note		The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr)
+{
+	u16 Divisor;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the divisor value from the Configuration Register 2.
+	 */
+	Divisor = (u16) XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_CFR2_OFFSET);
+
+	return (u8) (Divisor >> XADCPS_CFR2_CD_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be disabled before writing to these
+* regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	ChEnableMask is the bit mask of all the channels to be enabled.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+*		be disabled.
+*		The ChEnableMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Selection Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Selection Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable the specified channels in the ADC Channel Selection Sequencer
+	 * Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET,
+				(ChEnableMask & XADCPS_SEQ00_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET,
+				(ChEnableMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ01_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Gets the channel enable bits. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to interpret the Channel numbers. Bit masks of 1
+*		are the channels that are enabled and bit mask of 0 are
+*		the channels that are disabled.
+*
+* @return	None
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValEnable;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Read the channel enable bits for all the channels from the ADC
+	 *  Channel Selection Register.
+	 */
+	RegValEnable = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ00_OFFSET) &
+				XADCPS_SEQ00_CH_VALID_MASK;
+	RegValEnable |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ01_OFFSET) &
+				XADCPS_SEQ01_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+
+	return RegValEnable;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AvgEnableChMask is the bit mask of all the channels for which
+*		averaging is to be enabled. Use XADCPS_SEQ_CH__* defined in
+*		xadcps_hw.h to specify the Channel numbers. Averaging will be
+*		enabled for bit masks of 1 and disabled for bit mask of 0.
+*		The AvgEnableChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Averaging Enable Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Averaging Enables Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Enable/disable the averaging for the specified channels in the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET,
+				(AvgEnableChMask & XADCPS_SEQ02_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ03_OFFSET,
+				(AvgEnableChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ03_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The status of averaging (enabled/disabled) for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		averaging is enabled and bit mask of 0 are the channels for
+*		averaging is disabled
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr)
+{
+	u32 RegValAvg;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the averaging enable status for all the channels from the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	RegValAvg = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ02_OFFSET) & XADCPS_SEQ02_CH_VALID_MASK;
+	RegValAvg |= (XAdcPs_ReadInternalReg(InstancePtr,
+			XADCPS_SEQ03_OFFSET) & XADCPS_SEQ03_CH_VALID_MASK) <<
+			XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAvg;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the ADC
+* Channel Analog-Input Mode Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	InputModeChMask is the bit mask of all the channels for which
+*		the input mode is differential mode. Use XADCPS_SEQ_CH__* defined
+*		in xadcps_hw.h to specify the channel numbers. Differential
+*		input mode will be set for bit masks of 1 and unipolar input
+*		mode for bit masks of 0.
+*		The InputModeChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Analog-Input Mode Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None
+*
+*****************************************************************************/
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) != XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the input mode for the specified channels in the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET,
+				(InputModeChMask & XADCPS_SEQ04_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET,
+				(InputModeChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ05_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The input mode for all the channels.
+*		Use XADCPS_SEQ_CH_* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		input mode is differential and bit mask of 0 are the channels
+*		for which input mode is unipolar.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr)
+{
+	u32 InputMode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 *  Get the input mode for all the channels from the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	InputMode = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ04_OFFSET) &
+				XADCPS_SEQ04_CH_VALID_MASK;
+	InputMode |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ05_OFFSET) &
+				XADCPS_SEQ05_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be disabled
+* before writing to these regsiters.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AcqCyclesChMask is the bit mask of all the channels for which
+*		the number of acquisition cycles is to be extended.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to specify the Channel
+*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
+*		bit masks of 0.
+*		The AcqCyclesChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Acquisition Time Sequencer Registers.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Channel Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask)
+{
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XAdcPs_GetSequencerMode(InstancePtr) !=
+			XADCPS_SEQ_MODE_SAFE)) {
+		return XST_FAILURE;
+	}
+
+	/*
+	 * Set the Acquisition time for the specified channels in the
+	 * ADC Channel Acquisition Time Sequencer Registers.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET,
+				(AcqCyclesChMask & XADCPS_SEQ06_CH_VALID_MASK));
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET,
+				(AcqCyclesChMask >> XADCPS_SEQ_CH_AUX_SHIFT) &
+				XADCPS_SEQ07_CH_VALID_MASK);
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @returns 	The acquisition time for all the channels.
+*		Use XADCPS_SEQ_CH__* defined in xadcps_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		acquisition cycles are extended and bit mask of 0 are the
+*		channels for which acquisition cycles are not extended.
+*
+* @note		None
+*
+*****************************************************************************/
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr)
+{
+	u32 RegValAcq;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the Acquisition cycles for the specified channels from the ADC
+	 * Channel Acquisition Time Sequencer Registers.
+	 */
+	RegValAcq = XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ06_OFFSET) &
+				XADCPS_SEQ06_CH_VALID_MASK;
+	RegValAcq |= (XAdcPs_ReadInternalReg(InstancePtr,
+				XADCPS_SEQ07_OFFSET) &
+				XADCPS_SEQ07_CH_VALID_MASK) <<
+				XADCPS_SEQ_CH_AUX_SHIFT;
+
+	return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register to
+*		be set. Use XADCPS_ATR_* constants defined in xadcps.h to
+*		specify the index.
+* @param	Value is the 16-bit threshold value to write into the register.
+*
+* @return	None.
+*
+* @note		Use XAdcPs_SetOverTemp() to set the Over Temperature upper
+*		threshold value.
+*
+*****************************************************************************/
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value)
+{
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Write the value into the specified Alarm Threshold Register.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_ATR_TEMP_UPPER_OFFSET +
+					AlarmThrReg,Value);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register
+*		to be read. Use XADCPS_ATR_* constants defined in 	xadcps_hw.h
+*		to specify the index.
+*
+* @return	A 16-bit value representing the contents of the selected Alarm
+*		Threshold Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg)
+{
+	u32 RegData;
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(AlarmThrReg <= XADCPS_ATR_VCCPDRO_LOWER);
+
+	/*
+	 * Read the specified Alarm Threshold Register and return
+	 * the value
+	 */
+	RegData = XAdcPs_ReadInternalReg(InstancePtr,
+				(XADCPS_ATR_TEMP_UPPER_OFFSET + AlarmThrReg));
+
+	return (u16) RegData;
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function enables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	/*
+	 * Preserve the powerdown value and write OT enable value the into the
+	 * OT Upper Alarm Threshold Register.
+	 */
+	OtUpper |= XADCPS_ATR_OT_UPPER_ENB_VAL;
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables programming of the powerdown temperature for the
+* OverTemp signal in the OT Powerdown register.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr)
+{
+	u16 OtUpper;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the OT Upper Alarm Threshold Register.
+	 */
+	OtUpper = XAdcPs_ReadInternalReg(InstancePtr,
+					 XADCPS_ATR_OT_UPPER_OFFSET);
+	OtUpper &= ~(XADCPS_ATR_OT_UPPER_ENB_MASK);
+
+	XAdcPs_WriteInternalReg(InstancePtr,
+			  XADCPS_ATR_OT_UPPER_OFFSET, OtUpper);
+}
+
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the given channel.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_EC_MASK);
+
+	/*
+	 * Set the ADC mode.
+	 */
+	if (IsEventMode == TRUE) {
+		RegValue |= XADCPS_CFR0_EC_MASK;
+	} else {
+		RegValue &= ~XADCPS_CFR0_EC_MASK;
+	}
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function returns the sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	The sampling mode
+*		- 0 specifies continuous sampling
+*		- 1 specifies event driven sampling mode
+*
+* @note		None.
+*
+*****************************************************************************/
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr)
+{
+	u32 Mode;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the sampling mode from the Configuration Register 0.
+	 */
+	Mode = XAdcPs_ReadInternalReg(InstancePtr,
+				   XADCPS_CFR0_OFFSET) &
+				   XADCPS_CFR0_EC_MASK;
+	if (Mode) {
+
+		return 1;
+	}
+
+	return (0);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	MuxMode specifies whether External Mux is used
+*		- FALSE specifies NO external MUX
+*		- TRUE specifies External Mux is used
+* @param	Channel specifies the channel to be used for the
+*		external Mux. Please read the Device Spec for which
+*		channels are valid for which mode.
+*
+* @return	None.
+*
+* @note		There is no Assert in this function for checking the channel
+*		number if the external Mux is used. The user should provide a
+*		valid channel number.
+*
+*****************************************************************************/
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((MuxMode == TRUE) || (MuxMode == FALSE));
+
+	/*
+	 * Read the Configuration Register 0.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR0_OFFSET) &
+					(~XADCPS_CFR0_MUX_MASK);
+	/*
+	 * Select the Mux mode and the channel to be used.
+	 */
+	if (MuxMode == TRUE) {
+		RegValue |= XADCPS_CFR0_MUX_MASK;
+		RegValue |= (Channel & XADCPS_CFR0_CHANNEL_MASK);
+
+	}
+
+	/*
+	 * Write the mux mode into the Configuration Register 0.
+	 */
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR0_OFFSET,
+					RegValue);
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function sets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param 	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Mode < XADCPS_PD_MODE_XADC);
+
+
+	/*
+	 * Read the Configuration Register 2.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Select the Power Down mode.
+	 */
+	RegValue |= (Mode << XADCPS_CFR2_PD_SHIFT);
+
+	XAdcPs_WriteInternalReg(InstancePtr, XADCPS_CFR2_OFFSET,
+					RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Power Down mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Mode specifies the Power Down Mode
+*		- XADCPS_PD_MODE_NONE specifies NO Power Down (Both ADC A and
+*		ADC B are enabled)
+*		- XADCPS_PD_MODE_ADCB specfies the Power Down of ADC B
+*		- XADCPS_PD_MODE_XADC specifies the Power Down of
+*		both ADC A and ADC B.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr)
+{
+	u32 RegValue;
+
+	/*
+	 * Assert the arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the Power Down Mode.
+	 */
+	RegValue = XAdcPs_ReadInternalReg(InstancePtr,
+					XADCPS_CFR2_OFFSET) &
+					(~XADCPS_CFR2_PD_MASK);
+	/*
+	 * Return the Power Down mode.
+	 */
+	return (RegValue >> XADCPS_CFR2_PD_SHIFT);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for writing to XADC Registers using the command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be written.
+* @param	Data is the data to be written.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XAdcPs_WriteInternalReg(XAdcPs *InstancePtr, u32 RegOffset, u32 Data)
+{
+	u32 RegData;
+
+	/*
+	 * Write the Data into the FIFO Register.
+	 */
+	RegData = XAdcPs_FormatWriteData(RegOffset, Data, TRUE);
+
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Read the Read FIFO after any write since for each write
+	 * one location of Read FIFO gets updated
+	 */
+	XAdcPs_ReadFifo(InstancePtr);
+
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function is used for reading from the XADC Registers using the Data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+* @param	RegOffset is the offset of the XADC register to be read.
+*
+* @return	Data read from the FIFO
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+u32 XAdcPs_ReadInternalReg(XAdcPs *InstancePtr, u32 RegOffset)
+{
+
+	u32 RegData;
+
+	RegData = XAdcPs_FormatWriteData(RegOffset, 0x0, FALSE);
+
+	/* Read cmd to FIFO*/
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do a Dummy read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	/* Do a Dummy write to get the actual read */
+	XAdcPs_WriteFifo(InstancePtr, RegData);
+
+	/* Do the Actual read */
+	RegData = XAdcPs_ReadFifo(InstancePtr);
+
+	return RegData;
+
+}
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
new file mode 100644
index 0000000..549bfff
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h
@@ -0,0 +1,591 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps.h
+* @addtogroup xadcps_v2_2
+* @{
+* @details
+*
+* The XAdcPs driver supports the Xilinx XADC/ADC device.
+*
+* The XADC/ADC device has the following features:
+*	- 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the XADC/ADC device.
+*
+*
+*  XADC Channel Sequencer Modes 
+*
+* The  XADC Channel Sequencer supports the following operating modes:
+*
+*   -  Default : This is the default mode after power up.
+*		In this mode of operation the XADC operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   -  One pass through sequence : In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   -  Continuous cycling of sequence : In this mode the XADC
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   -  Single channel mode: In this mode the XADC Channel
+*		Sequencer is disabled and the XADC operates in a
+*		Single Channel Mode.
+*		The XADC can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*   -  Simultaneous Sampling Mode: In this mode the XADC Channel
+*		Sequencer will automatically sequence through eight fixed pairs
+*		of auxiliary analog input channels for simulataneous conversion.
+*   -  Independent ADC mode: In this mode the first ADC (A) is used to
+*		is used to implement a fixed monitoring mode similar to the
+*		default mode but the alarm fucntions ar eenabled.
+*		The second ADC (B) is available to be used with external analog
+*		input channels only.
+*
+* Read the XADC spec for more information about the sequencer modes.
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the XADC/ADC device.
+*
+* XAdcPs_CfgInitialize() API is used to initialize the XADC/ADC
+* device. The user needs to first call the XAdcPs_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XAdcPs_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The XADC/ADC device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* The interrupt mode is available only if hardware is configured to support
+* interrupts.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+*  Building the driver 
+*
+* The XAdcPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*  Limitations of the driver 
+*
+* XADC/ADC device can be accessed through the JTAG port and the PLB
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to care of this situation
+* in the user application code.
+*
+* 

    
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.01a bss    02/18/13	Modified XAdcPs_SetSeqChEnables,XAdcPs_SetSeqAvgEnables
+*			XAdcPs_SetSeqInputMode and XAdcPs_SetSeqAcqTime APIs
+*			in xadcps.c to fix CR #693371
+* 1.03a bss    11/01/13 Modified xadcps_hw.h to use correct Register offsets
+*			CR#749687
+* 2.1   bss    08/05/14 Added declarations for XAdcPs_SetSequencerEvent,
+*			XAdcPs_GetSamplingMode, XAdcPs_SetMuxMode,
+*			XAdcPs_SetPowerdownMode and XAdcPs_GetPowerdownMode
+*			functions.
+*			Modified Assert for XAdcPs_SetSingleChParams in
+*			xadcps.c to fix CR #807563.
+* 2.2   bss    04/27/14 Modified to use correct Device Config base address in
+*						xadcps.c (CR#854437).
+*       ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*       ms     04/05/17 Modified Comment lines in functions of xadcps
+*                       examples to recognize it as documentation block
+*                       for doxygen generation.
+*
+* 
    
+*
+*****************************************************************************/
+#ifndef XADCPS_H /* Prevent circular inclusions */
+#define XADCPS_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xadcps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XADCPS_CH_TEMP		0x0  /**< On Chip Temperature */
+#define XADCPS_CH_VCCINT	0x1  /**< VCCINT */
+#define XADCPS_CH_VCCAUX	0x2  /**< VCCAUX */
+#define XADCPS_CH_VPVN		0x3  /**< VP/VN Dedicated analog inputs */
+#define XADCPS_CH_VREFP		0x4  /**< VREFP */
+#define XADCPS_CH_VREFN		0x5  /**< VREFN */
+#define XADCPS_CH_VBRAM		0x6  /**< On-chip VBRAM Data Reg, 7 series */
+#define XADCPS_CH_SUPPLY_CALIB	0x07 /**< Supply Calib Data Reg */
+#define XADCPS_CH_ADC_CALIB	0x08 /**< ADC Offset Channel Reg */
+#define XADCPS_CH_GAINERR_CALIB 0x09 /**< Gain Error Channel Reg  */
+#define XADCPS_CH_VCCPINT	0x0D /**< On-chip PS VCCPINT Channel , Zynq */
+#define XADCPS_CH_VCCPAUX	0x0E /**< On-chip PS VCCPAUX Channel , Zynq */
+#define XADCPS_CH_VCCPDRO	0x0F /**< On-chip PS VCCPDRO Channel , Zynq */
+#define XADCPS_CH_AUX_MIN	 16 /**< Channel number for 1st Aux Channel */
+#define XADCPS_CH_AUX_MAX	 31 /**< Channel number for Last Aux channel */
+
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XADCPS_CALIB_SUPPLY_COEFF     0 /**< Supply Offset Calib Coefficient */
+#define XADCPS_CALIB_ADC_COEFF        1 /**< ADC Offset Calib Coefficient */
+#define XADCPS_CALIB_GAIN_ERROR_COEFF 2 /**< Gain Error Calib Coefficient*/
+/*@}*/
+
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XADCPS_MAX_TEMP		0 /**< Maximum Temperature Data */
+#define XADCPS_MAX_VCCINT	1 /**< Maximum VCCINT Data */
+#define XADCPS_MAX_VCCAUX	2 /**< Maximum VCCAUX Data */
+#define XADCPS_MAX_VBRAM	3 /**< Maximum VBRAM Data */
+#define XADCPS_MIN_TEMP		4 /**< Minimum Temperature Data */
+#define XADCPS_MIN_VCCINT	5 /**< Minimum VCCINT Data */
+#define XADCPS_MIN_VCCAUX	6 /**< Minimum VCCAUX Data */
+#define XADCPS_MIN_VBRAM	7 /**< Minimum VBRAM Data */
+#define XADCPS_MAX_VCCPINT	8 /**< Maximum VCCPINT Register , Zynq */
+#define XADCPS_MAX_VCCPAUX	9 /**< Maximum VCCPAUX Register , Zynq */
+#define XADCPS_MAX_VCCPDRO	0xA /**< Maximum VCCPDRO Register , Zynq */
+#define XADCPS_MIN_VCCPINT	0xC /**< Minimum VCCPINT Register , Zynq */
+#define XADCPS_MIN_VCCPAUX	0xD /**< Minimum VCCPAUX Register , Zynq */
+#define XADCPS_MIN_VCCPDRO	0xE /**< Minimum VCCPDRO Register , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XADCPS_ATR_TEMP_UPPER	 0 /**< High user Temperature */
+#define XADCPS_ATR_VCCINT_UPPER  1 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_UPPER  2 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_OT_UPPER	 3 /**< VCCAUX high voltage limit register */
+#define XADCPS_ATR_TEMP_LOWER	 4 /**< Upper Over Temperature limit Reg */
+#define XADCPS_ATR_VCCINT_LOWER	 5 /**< VCCINT high voltage limit register */
+#define XADCPS_ATR_VCCAUX_LOWER	 6 /**< VCCAUX low voltage limit register  */
+#define XADCPS_ATR_OT_LOWER	 7 /**< Lower Over Temperature limit */
+#define XADCPS_ATR_VBRAM_UPPER_  8 /**< VRBAM Upper Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_UPPER 9 /**< VCCPINT Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER 0xA /**< VCCPAUX Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER 0xB /**< VCCPDRO Upper Alarm Reg, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER	 0xC /**< VRBAM Lower Alarm Reg, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER 0xD /**< VCCPINT Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER 0xE /**< VCCPAUX Lower Alarm Reg , Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER 0xF /**< VCCPDRO Lower Alarm Reg , Zynq */
+
+/*@}*/
+
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XADCPS_AVG_0_SAMPLES	0  /**< No Averaging */
+#define XADCPS_AVG_16_SAMPLES	1  /**< Average 16 samples */
+#define XADCPS_AVG_64_SAMPLES	2  /**< Average 64 samples */
+#define XADCPS_AVG_256_SAMPLES	3  /**< Average 256 samples */
+
+/*@}*/
+
+
+/**
+ * @name Channel Sequencer Modes of operation
+ * @{
+ */
+#define XADCPS_SEQ_MODE_SAFE		0  /**< Default Safe Mode */
+#define XADCPS_SEQ_MODE_ONEPASS		1  /**< Onepass through Sequencer */
+#define XADCPS_SEQ_MODE_CONTINPASS	2  /**< Continuous Cycling Sequencer */
+#define XADCPS_SEQ_MODE_SINGCHAN	3  /**< Single channel -No Sequencing */
+#define XADCPS_SEQ_MODE_SIMUL_SAMPLING	4  /**< Simultaneous sampling */
+#define XADCPS_SEQ_MODE_INDEPENDENT	8  /**< Independent mode */
+
+/*@}*/
+
+
+
+/**
+ * @name Power Down Modes
+ * @{
+ */
+#define XADCPS_PD_MODE_NONE		0  /**< No Power Down  */
+#define XADCPS_PD_MODE_ADCB		1  /**< Power Down ADC B */
+#define XADCPS_PD_MODE_XADC		2  /**< Power Down ADC A and ADC B */
+/*@}*/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the XADC/ADC
+ * device.
+ */
+typedef struct {
+	u16  DeviceId;		/**< Unique ID of device */
+	u32  BaseAddress;	/**< Device base address */
+} XAdcPs_Config;
+
+
+/**
+ * The driver's instance data. The user is required to allocate a variable
+ * of this type for every XADC/ADC device in the system. A pointer to
+ * a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XAdcPs_Config Config;	/**< XAdcPs_Config of current device */
+	u32  IsReady;		/**< Device is initialized and ready  */
+
+} XAdcPs;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in Event Sampling mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in Event Sampling Mode.
+*		- FALSE if the device is in Continuous Sampling Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsEventSamplingMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsEventSamplingModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_EC_MASK) ?	\
+			TRUE : FALSE))
+
+
+/****************************************************************************/
+/**
+*
+* This macro checks if the XADC device is in External Mux mode.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return
+*		- TRUE if the device is in External Mux Mode.
+*		- FALSE if the device is NOT in External Mux Mode.
+*
+* @note		C-Style signature:
+*		int XAdcPs_IsExternalMuxMode(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_IsExternalMuxModeSet(InstancePtr)			\
+	(((XAdcPs_ReadInternalReg(InstancePtr,	 			\
+			XADCPS_CFR0_OFFSET) & XADCPS_CFR0_MUX_MASK) ?	\
+			TRUE : FALSE))
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC Raw Data to Temperature(centigrades).
+*
+* @param	AdcData is the Raw ADC Data from XADC.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToTemperature(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToTemperature(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00198421639f ) - 273.15f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts XADC/ADC Raw Data to Voltage(volts).
+*
+* @param	AdcData is the XADC/ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XAdcPs_RawToVoltage(u32 AdcData);
+*
+*****************************************************************************/
+#define XAdcPs_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to XADC/ADC Raw Data.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_TemperatureToRaw(float Temperature);
+*
+*****************************************************************************/
+#define XAdcPs_TemperatureToRaw(Temperature)				\
+	((int)(((Temperature) + 273.15f)*65536.0f*0.00198421639f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to XADC/ADC Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		XADC/ADC Raw Data.
+*
+* @return 	The XADC/ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XAdcPs_VoltageToRaw(float Voltage);
+*
+*****************************************************************************/
+#define XAdcPs_VoltageToRaw(Voltage)			 		\
+	((int)((Voltage)*65536.0f/3.0f))
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for writing to the XADC Registers using the
+* command FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XAdcPs_WriteFifo(XAdcPs *InstancePtr, u32 Data);
+*
+*****************************************************************************/
+#define XAdcPs_WriteFifo(InstancePtr, Data)				\
+	XAdcPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+			  XADCPS_CMDFIFO_OFFSET, Data);
+
+
+/****************************************************************************/
+/**
+*
+* This macro is used for reading from the XADC Registers using the
+* data FIFO.
+*
+* @param	InstancePtr is a pointer to the XAdcPs instance.
+*
+* @return	Data read from the FIFO
+*
+* @note		C-Style signature:
+*		u32 XAdcPs_ReadFifo(XAdcPs *InstancePtr);
+*
+*****************************************************************************/
+#define XAdcPs_ReadFifo(InstancePtr)				\
+	XAdcPs_ReadReg((InstancePtr)->Config.BaseAddress,	\
+			  XADCPS_RDFIFO_OFFSET);
+
+
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ * Functions in xadcps_sinit.c
+ */
+XAdcPs_Config *XAdcPs_LookupConfig(u16 DeviceId);
+
+/**
+ * Functions in xadcps.c
+ */
+int XAdcPs_CfgInitialize(XAdcPs *InstancePtr,
+				XAdcPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+
+u32 XAdcPs_GetStatus(XAdcPs *InstancePtr);
+
+u32 XAdcPs_GetAlarmOutputStatus(XAdcPs *InstancePtr);
+
+void XAdcPs_StartAdcConversion(XAdcPs *InstancePtr);
+
+void XAdcPs_Reset(XAdcPs *InstancePtr);
+
+u16 XAdcPs_GetAdcData(XAdcPs *InstancePtr, u8 Channel);
+
+u16 XAdcPs_GetCalibCoefficient(XAdcPs *InstancePtr, u8 CoeffType);
+
+u16 XAdcPs_GetMinMaxMeasurement(XAdcPs *InstancePtr, u8 MeasurementType);
+
+void XAdcPs_SetAvg(XAdcPs *InstancePtr, u8 Average);
+u8 XAdcPs_GetAvg(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSingleChParams(XAdcPs *InstancePtr,
+				u8 Channel,
+				int IncreaseAcqCycles,
+				int IsEventMode,
+				int IsDifferentialMode);
+
+
+void XAdcPs_SetAlarmEnables(XAdcPs *InstancePtr, u16 AlmEnableMask);
+u16 XAdcPs_GetAlarmEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetCalibEnables(XAdcPs *InstancePtr, u16 Calibration);
+u16 XAdcPs_GetCalibEnables(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerMode(XAdcPs *InstancePtr, u8 SequencerMode);
+u8 XAdcPs_GetSequencerMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAdcClkDivisor(XAdcPs *InstancePtr, u8 Divisor);
+u8 XAdcPs_GetAdcClkDivisor(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqChEnables(XAdcPs *InstancePtr, u32 ChEnableMask);
+u32 XAdcPs_GetSeqChEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAvgEnables(XAdcPs *InstancePtr, u32 AvgEnableChMask);
+u32 XAdcPs_GetSeqAvgEnables(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqInputMode(XAdcPs *InstancePtr, u32 InputModeChMask);
+u32 XAdcPs_GetSeqInputMode(XAdcPs *InstancePtr);
+
+int XAdcPs_SetSeqAcqTime(XAdcPs *InstancePtr, u32 AcqCyclesChMask);
+u32 XAdcPs_GetSeqAcqTime(XAdcPs *InstancePtr);
+
+void XAdcPs_SetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg, u16 Value);
+u16 XAdcPs_GetAlarmThreshold(XAdcPs *InstancePtr, u8 AlarmThrReg);
+
+void XAdcPs_EnableUserOverTemp(XAdcPs *InstancePtr);
+void XAdcPs_DisableUserOverTemp(XAdcPs *InstancePtr);
+
+void XAdcPs_SetSequencerEvent(XAdcPs *InstancePtr, int IsEventMode);
+
+int XAdcPs_GetSamplingMode(XAdcPs *InstancePtr);
+
+void XAdcPs_SetMuxMode(XAdcPs *InstancePtr, int MuxMode, u8 Channel);
+
+void XAdcPs_SetPowerdownMode(XAdcPs *InstancePtr, u32 Mode);
+
+u32 XAdcPs_GetPowerdownMode(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_selftest.c
+ */
+int XAdcPs_SelfTest(XAdcPs *InstancePtr);
+
+/**
+ * Functions in xadcps_intr.c
+ */
+void XAdcPs_IntrEnable(XAdcPs *InstancePtr, u32 Mask);
+void XAdcPs_IntrDisable(XAdcPs *InstancePtr, u32 Mask);
+u32 XAdcPs_IntrGetEnabled(XAdcPs *InstancePtr);
+
+u32 XAdcPs_IntrGetStatus(XAdcPs *InstancePtr);
+void XAdcPs_IntrClear(XAdcPs *InstancePtr, u32 Mask);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* End of protection macro. */
+/** @} */
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
new file mode 100644
index 0000000..22757f3
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xadcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] =
+{
+	{
+		XPAR_PS7_XADC_0_DEVICE_ID,
+		XPAR_PS7_XADC_0_BASEADDR
+	}
+};
+
+
diff --git a/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
new file mode 100644
index 0000000..55a47a4
--- /dev/null
+++ b/LED_Blink/LED_Blink.sdk/hello_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_hw.h
@@ -0,0 +1,502 @@
+/******************************************************************************
+*
+* Copyright (C) 2011 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xadcps_hw.h
+* @addtogroup xadcps_v2_2
+* @{
+*
+* This header file contains identifiers and basic driver functions (or
+* macros) that can be used to access the XADC device through the Device
+* Config Interface of the Zynq.
+*
+*
+* Refer to the device specification for more information about this driver.
+*
+* @note	 None.
+*
+*
+* 
    +*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    12/22/11 First release based on the XPS/AXI xadc driver
+* 1.03a bss    11/01/13 Modified macros to use correct Register offsets
+*			CR#749687
+*
+* 
    
+*
+*****************************************************************************/
+#ifndef XADCPS_HW_H /* Prevent circular inclusions */
+#define XADCPS_HW_H /* by using protection macros  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**@name Register offsets of XADC in the Device Config
+ *
+ * The following constants provide access to each of the registers of the
+ * XADC device.
+ * @{
+ */
+
+#define XADCPS_CFG_OFFSET	 0x00 /**< Configuration Register */
+#define XADCPS_INT_STS_OFFSET	 0x04 /**< Interrupt Status Register */
+#define XADCPS_INT_MASK_OFFSET	 0x08 /**< Interrupt Mask Register */
+#define XADCPS_MSTS_OFFSET	 0x0C /**< Misc status register */
+#define XADCPS_CMDFIFO_OFFSET	 0x10 /**< Command FIFO Register */
+#define XADCPS_RDFIFO_OFFSET	 0x14 /**< Read FIFO Register */
+#define XADCPS_MCTL_OFFSET	 0x18 /**< Misc control register */
+
+/* @} */
+
+
+
+
+
+/** @name XADC Config Register Bit definitions
+  * @{
+ */
+#define XADCPS_CFG_ENABLE_MASK	 0x80000000 /**< Enable access from PS mask */
+#define XADCPS_CFG_CFIFOTH_MASK  0x00F00000 /**< Command FIFO Threshold mask */
+#define XADCPS_CFG_DFIFOTH_MASK  0x000F0000 /**< Data FIFO Threshold mask */
+#define XADCPS_CFG_WEDGE_MASK	 0x00002000 /**< Write Edge Mask */
+#define XADCPS_CFG_REDGE_MASK	 0x00001000 /**< Read Edge Mask */
+#define XADCPS_CFG_TCKRATE_MASK  0x00000300 /**< Clock freq control */
+#define XADCPS_CFG_IGAP_MASK	 0x0000001F /**< Idle Gap between
+						* successive commands */
+/* @} */
+
+
+/** @name XADC Interrupt Status/Mask Register Bit definitions
+  *
+  * The definitions are same for the Interrupt Status Register and
+  * Interrupt Mask Register. They are defined only once.
+  * @{
+ */
+#define XADCPS_INTX_ALL_MASK   	   0x000003FF /**< Alarm Signals Mask  */
+#define XADCPS_INTX_CFIFO_LTH_MASK 0x00000200 /**< CMD FIFO less than threshold */
+#define XADCPS_INTX_DFIFO_GTH_MASK 0x00000100 /**< Data FIFO greater than threshold */
+#define XADCPS_INTX_OT_MASK	   0x00000080 /**< Over temperature Alarm Status */
+#define XADCPS_INTX_ALM_ALL_MASK   0x0000007F /**< Alarm Signals Mask  */
+#define XADCPS_INTX_ALM6_MASK	   0x00000040 /**< Alarm 6 Mask  */
+#define XADCPS_INTX_ALM5_MASK	   0x00000020 /**< Alarm 5 Mask  */
+#define XADCPS_INTX_ALM4_MASK	   0x00000010 /**< Alarm 4 Mask  */
+#define XADCPS_INTX_ALM3_MASK	   0x00000008 /**< Alarm 3 Mask  */
+#define XADCPS_INTX_ALM2_MASK	   0x00000004 /**< Alarm 2 Mask  */
+#define XADCPS_INTX_ALM1_MASK	   0x00000002 /**< Alarm 1 Mask  */
+#define XADCPS_INTX_ALM0_MASK	   0x00000001 /**< Alarm 0 Mask  */
+
+/* @} */
+
+
+/** @name XADC Miscellaneous Register Bit definitions
+  * @{
+ */
+#define XADCPS_MSTS_CFIFO_LVL_MASK  0x000F0000 /**< Command FIFO Level mask */
+#define XADCPS_MSTS_DFIFO_LVL_MASK  0x0000F000 /**< Data FIFO Level Mask  */
+#define XADCPS_MSTS_CFIFOF_MASK     0x00000800 /**< Command FIFO Full Mask  */
+#define XADCPS_MSTS_CFIFOE_MASK     0x00000400 /**< Command FIFO Empty Mask  */
+#define XADCPS_MSTS_DFIFOF_MASK     0x00000200 /**< Data FIFO Full Mask  */
+#define XADCPS_MSTS_DFIFOE_MASK     0x00000100 /**< Data FIFO Empty Mask  */
+#define XADCPS_MSTS_OT_MASK	    0x00000080 /**< Over Temperature Mask */
+#define XADCPS_MSTS_ALM_MASK	    0x0000007F /**< Alarms Mask  */
+/* @} */
+
+
+/** @name XADC Miscellaneous Control Register Bit definitions
+  * @{
+ */
+#define XADCPS_MCTL_RESET_MASK      0x00000010 /**< Reset XADC */
+#define XADCPS_MCTL_FLUSH_MASK      0x00000001 /**< Flush the FIFOs */
+/* @} */
+
+
+/**@name Internal Register offsets of the XADC
+ *
+ * The following constants provide access to each of the internal registers of
+ * the XADC device.
+ * @{
+ */
+
+/*
+ * XADC Internal Channel Registers
+ */
+#define XADCPS_TEMP_OFFSET		  0x00 /**< On-chip Temperature Reg */
+#define XADCPS_VCCINT_OFFSET		  0x01 /**< On-chip VCCINT Data Reg */
+#define XADCPS_VCCAUX_OFFSET		  0x02 /**< On-chip VCCAUX Data Reg */
+#define XADCPS_VPVN_OFFSET		  0x03 /**< ADC out of VP/VN	   */
+#define XADCPS_VREFP_OFFSET		  0x04 /**< On-chip VREFP Data Reg */
+#define XADCPS_VREFN_OFFSET		  0x05 /**< On-chip VREFN Data Reg */
+#define XADCPS_VBRAM_OFFSET		  0x06 /**< On-chip VBRAM , 7 Series */
+#define XADCPS_ADC_A_SUPPLY_CALIB_OFFSET  0x08 /**< ADC A Supply Offset Reg */
+#define XADCPS_ADC_A_OFFSET_CALIB_OFFSET  0x09 /**< ADC A Offset Data Reg */
+#define XADCPS_ADC_A_GAINERR_CALIB_OFFSET 0x0A /**< ADC A Gain Error Reg  */
+#define XADCPS_VCCPINT_OFFSET		  0x0D /**< On-chip VCCPINT Reg, Zynq */
+#define XADCPS_VCCPAUX_OFFSET		  0x0E /**< On-chip VCCPAUX Reg, Zynq */
+#define XADCPS_VCCPDRO_OFFSET		  0x0F /**< On-chip VCCPDRO Reg, Zynq */
+
+/*
+ * XADC External Channel Registers
+ */
+#define XADCPS_AUX00_OFFSET	0x10 /**< ADC out of VAUXP0/VAUXN0 */
+#define XADCPS_AUX01_OFFSET	0x11 /**< ADC out of VAUXP1/VAUXN1 */
+#define XADCPS_AUX02_OFFSET	0x12 /**< ADC out of VAUXP2/VAUXN2 */
+#define XADCPS_AUX03_OFFSET	0x13 /**< ADC out of VAUXP3/VAUXN3 */
+#define XADCPS_AUX04_OFFSET	0x14 /**< ADC out of VAUXP4/VAUXN4 */
+#define XADCPS_AUX05_OFFSET	0x15 /**< ADC out of VAUXP5/VAUXN5 */
+#define XADCPS_AUX06_OFFSET	0x16 /**< ADC out of VAUXP6/VAUXN6 */
+#define XADCPS_AUX07_OFFSET	0x17 /**< ADC out of VAUXP7/VAUXN7 */
+#define XADCPS_AUX08_OFFSET	0x18 /**< ADC out of VAUXP8/VAUXN8 */
+#define XADCPS_AUX09_OFFSET	0x19 /**< ADC out of VAUXP9/VAUXN9 */
+#define XADCPS_AUX10_OFFSET	0x1A /**< ADC out of VAUXP10/VAUXN10 */
+#define XADCPS_AUX11_OFFSET	0x1B /**< ADC out of VAUXP11/VAUXN11 */
+#define XADCPS_AUX12_OFFSET	0x1C /**< ADC out of VAUXP12/VAUXN12 */
+#define XADCPS_AUX13_OFFSET	0x1D /**< ADC out of VAUXP13/VAUXN13 */
+#define XADCPS_AUX14_OFFSET	0x1E /**< ADC out of VAUXP14/VAUXN14 */
+#define XADCPS_AUX15_OFFSET	0x1F /**< ADC out of VAUXP15/VAUXN15 */
+
+/*
+ * XADC Registers for Maximum/Minimum data captured for the
+ * on chip Temperature/VCCINT/VCCAUX data.
+ */
+#define XADCPS_MAX_TEMP_OFFSET		0x20 /**< Max Temperature Reg */
+#define XADCPS_MAX_VCCINT_OFFSET	0x21 /**< Max VCCINT Register */
+#define XADCPS_MAX_VCCAUX_OFFSET	0x22 /**< Max VCCAUX Register */
+#define XADCPS_MAX_VCCBRAM_OFFSET	0x23 /**< Max BRAM Register, 7 series */
+#define XADCPS_MIN_TEMP_OFFSET		0x24 /**< Min Temperature Reg */
+#define XADCPS_MIN_VCCINT_OFFSET	0x25 /**< Min VCCINT Register */
+#define XADCPS_MIN_VCCAUX_OFFSET	0x26 /**< Min VCCAUX Register */
+#define XADCPS_MIN_VCCBRAM_OFFSET	0x27 /**< Min BRAM Register, 7 series */
+#define XADCPS_MAX_VCCPINT_OFFSET	0x28 /**< Max VCCPINT Register, Zynq */
+#define XADCPS_MAX_VCCPAUX_OFFSET	0x29 /**< Max VCCPAUX Register, Zynq */
+#define XADCPS_MAX_VCCPDRO_OFFSET	0x2A /**< Max VCCPDRO Register, Zynq */
+#define XADCPS_MIN_VCCPINT_OFFSET	0x2C /**< Min VCCPINT Register, Zynq */
+#define XADCPS_MIN_VCCPAUX_OFFSET	0x2D /**< Min VCCPAUX Register, Zynq */
+#define XADCPS_MIN_VCCPDRO_OFFSET	0x2E /**< Min VCCPDRO Register,Zynq */
+ /* Undefined 0x2F to 0x3E */
+#define XADCPS_FLAG_OFFSET		0x3F /**< Flag Register */
+
+/*
+ * XADC Configuration Registers
+ */
+#define XADCPS_CFR0_OFFSET	0x40	/**< Configuration Register 0 */
+#define XADCPS_CFR1_OFFSET	0x41	/**< Configuration Register 1 */
+#define XADCPS_CFR2_OFFSET	0x42	/**< Configuration Register 2 */
+
+/* Test Registers 0x43 to 0x47 */
+
+/*
+ * XADC Sequence Registers
+ */
+#define XADCPS_SEQ00_OFFSET	0x48 /**< Seq Reg 00 Adc Channel Selection */
+#define XADCPS_SEQ01_OFFSET	0x49 /**< Seq Reg 01 Adc Channel Selection */
+#define XADCPS_SEQ02_OFFSET	0x4A /**< Seq Reg 02 Adc Average Enable */
+#define XADCPS_SEQ03_OFFSET	0x4B /**< Seq Reg 03 Adc Average Enable */
+#define XADCPS_SEQ04_OFFSET	0x4C /**< Seq Reg 04 Adc Input Mode Select */
+#define XADCPS_SEQ05_OFFSET	0x4D /**< Seq Reg 05 Adc Input Mode Select */
+#define XADCPS_SEQ06_OFFSET	0x4E /**< Seq Reg 06 Adc Acquisition Select */
+#define XADCPS_SEQ07_OFFSET	0x4F /**< Seq Reg 07 Adc Acquisition Select */
+
+/*
+ * XADC Alarm Threshold/Limit Registers (ATR)
+ */
+#define XADCPS_ATR_TEMP_UPPER_OFFSET	0x50 /**< Temp Upper Alarm Register */
+#define XADCPS_ATR_VCCINT_UPPER_OFFSET	0x51 /**< VCCINT Upper Alarm Reg */
+#define XADCPS_ATR_VCCAUX_UPPER_OFFSET	0x52 /**< VCCAUX Upper Alarm Reg */
+#define XADCPS_ATR_OT_UPPER_OFFSET	0x53 /**< Over Temp Upper Alarm Reg */
+#define XADCPS_ATR_TEMP_LOWER_OFFSET	0x54 /**< Temp Lower Alarm Register */
+#define XADCPS_ATR_VCCINT_LOWER_OFFSET	0x55 /**< VCCINT Lower Alarm Reg */
+#define XADCPS_ATR_VCCAUX_LOWER_OFFSET	0x56 /**< VCCAUX Lower Alarm Reg */
+#define XADCPS_ATR_OT_LOWER_OFFSET	0x57 /**< Over Temp Lower Alarm Reg */
+#define XADCPS_ATR_VBRAM_UPPER_OFFSET	0x58 /**< VBRAM Upper Alarm, 7 series */
+#define XADCPS_ATR_VCCPINT_UPPER_OFFSET	0x59 /**< VCCPINT Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_UPPER_OFFSET	0x5A /**< VCCPAUX Upper Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_UPPER_OFFSET	0x5B /**< VCCPDRO Upper Alarm, Zynq */
+#define XADCPS_ATR_VBRAM_LOWER_OFFSET	0x5C /**< VRBAM Lower Alarm, 7 Series */
+#define XADCPS_ATR_VCCPINT_LOWER_OFFSET	0x5D /**< VCCPINT Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPAUX_LOWER_OFFSET	0x5E /**< VCCPAUX Lower Alarm, Zynq */
+#define XADCPS_ATR_VCCPDRO_LOWER_OFFSET	0x5F /**< VCCPDRO Lower Alarm, Zynq */
+
+/* Undefined 0x60 to 0x7F */
+
+/*@}*/
+
+
+
+/**
+ * @name Configuration Register 0 (CFR0) mask(s)
+ * @{
+ */
+#define XADCPS_CFR0_CAL_AVG_MASK	0x8000 /**< Averaging enable Mask */
+#define XADCPS_CFR0_AVG_VALID_MASK	0x3000 /**< Averaging bit Mask */
+#define XADCPS_CFR0_AVG1_MASK		0x0000 /**< No Averaging */
+#define XADCPS_CFR0_AVG16_MASK		0x1000 /**< Average 16 samples */
+#define XADCPS_CFR0_AVG64_MASK	 	0x2000 /**< Average 64 samples */
+#define XADCPS_CFR0_AVG256_MASK 	0x3000 /**< Average 256 samples */
+#define XADCPS_CFR0_AVG_SHIFT	 	12     /**< Averaging bits shift */
+#define XADCPS_CFR0_MUX_MASK	 	0x0800 /**< External Mask Enable */
+#define XADCPS_CFR0_DU_MASK	 	0x0400 /**< Bipolar/Unipolar mode */
+#define XADCPS_CFR0_EC_MASK	 	0x0200 /**< Event driven/
+						 *  Continuous mode selection
+						 */
+#define XADCPS_CFR0_ACQ_MASK	 	0x0100 /**< Add acquisition by 6 ADCCLK */
+#define XADCPS_CFR0_CHANNEL_MASK	0x001F /**< Channel number bit Mask */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 1 (CFR1) mask(s)
+ * @{
+ */
+#define XADCPS_CFR1_SEQ_VALID_MASK	  0xF000 /**< Sequence bit Mask */
+#define XADCPS_CFR1_SEQ_SAFEMODE_MASK	  0x0000 /**< Default Safe Mode */
+#define XADCPS_CFR1_SEQ_ONEPASS_MASK	  0x1000 /**< Onepass through Seq */
+#define XADCPS_CFR1_SEQ_CONTINPASS_MASK	     0x2000 /**< Continuous Cycling Seq */
+#define XADCPS_CFR1_SEQ_SINGCHAN_MASK	     0x3000 /**< Single channel - No Seq */
+#define XADCPS_CFR1_SEQ_SIMUL_SAMPLING_MASK  0x4000 /**< Simulataneous Sampling Mask */
+#define XADCPS_CFR1_SEQ_INDEPENDENT_MASK  0x8000 /**< Independent Mode */
+#define XADCPS_CFR1_SEQ_SHIFT		  12     /**< Sequence bit shift */
+#define XADCPS_CFR1_ALM_VCCPDRO_MASK	  0x0800 /**< Alm 6 - VCCPDRO, Zynq  */
+#define XADCPS_CFR1_ALM_VCCPAUX_MASK	  0x0400 /**< Alm 5 - VCCPAUX, Zynq */
+#define XADCPS_CFR1_ALM_VCCPINT_MASK	  0x0200 /**< Alm 4 - VCCPINT, Zynq */
+#define XADCPS_CFR1_ALM_VBRAM_MASK	  0x0100 /**< Alm 3 - VBRAM, 7 series */
+#define XADCPS_CFR1_CAL_VALID_MASK	  0x00F0 /**< Valid Calibration Mask */
+#define XADCPS_CFR1_CAL_PS_GAIN_OFFSET_MASK  0x0080 /**< Calibration 3 -Power
+							Supply Gain/Offset
+							Enable */
+#define XADCPS_CFR1_CAL_PS_OFFSET_MASK	  0x0040 /**< Calibration 2 -Power
+							Supply Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_GAIN_OFFSET_MASK 0x0020 /**< Calibration 1 -ADC Gain
+							Offset Enable */
+#define XADCPS_CFR1_CAL_ADC_OFFSET_MASK	 0x0010 /**< Calibration 0 -ADC Offset
+							Enable */
+#define XADCPS_CFR1_CAL_DISABLE_MASK	0x0000 /**< No Calibration */
+#define XADCPS_CFR1_ALM_ALL_MASK	0x0F0F /**< Mask for all alarms */
+#define XADCPS_CFR1_ALM_VCCAUX_MASK	0x0008 /**< Alarm 2 - VCCAUX Enable */
+#define XADCPS_CFR1_ALM_VCCINT_MASK	0x0004 /**< Alarm 1 - VCCINT Enable */
+#define XADCPS_CFR1_ALM_TEMP_MASK	0x0002 /**< Alarm 0 - Temperature */
+#define XADCPS_CFR1_OT_MASK		0x0001 /**< Over Temperature Enable */
+
+/*@}*/
+
+/**
+ * @name Configuration Register 2 (CFR2) mask(s)
+ * @{
+ */
+#define XADCPS_CFR2_CD_VALID_MASK	0xFF00  /**
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a ssb    12/22/11 First release based on the XPS/AXI xadc driver
+*
+*
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znElo)r_$RqCp3xI;(E+{y})#?_Qy@}IaOM`KuXIR({9X)^!1|WkW21PvmNFtqPGLm z=x!vPe2Sl}VS3iFlI$%trfVg$8?vi3R>3`u!}OY|TdmF7$&+>F%o3AXpc7kf_8Und z+_`+rU9+o@@}9Df)zw|xl~QGAxW#o7yDeRQk}=X_HhY3~vX^4VD^+*P zm+b#G+6|!8DcQZa@n{Ap^JJnr-MFbxD{U{j;jWBhMVNN1l0o9`BD2^mY|d}D#vrjB z?(hOTXrrW$8pPO$Wgg-CHrx>dm6{FxC@lM=(LNWI3h1ZHNp6eI98KpjdUNK>Ik_sE z!vj-%|1igznk(u@FWJ6LN0Hg3)8f(=<_y6dA;@El?Q{AmhO;VWVkRx+9*VjFZk+~s zmY0)xZK{?S3^y%pOUkyxtO?qjo@CwBQ2oGcqp*k9M$Np=xOaRlsiB5utfMfbeWxMW zV5uRqM5-ZK*wm1HyrXm!dv>WKy7%VjObwmfoN9=j6*s_pklTyb!Iy<*XZcH&gOaU_ZZrSBb~h*G>2p%k=k-MapHr_O1AeaFU<= zE&n+2EbmlAnBMT;d(x zm`3#M+ds<0lfUhjc&l6>VJ^QnXX2T^IiwWwhd%al@%|Jo@1_6bdKvjiAGu4ygv0jL zecm8m-~_L(-_GW}w28Z3;hm;F-~_MkzVb>>CD#%1YhR+&Gx 0 } { + if {[catch {init_board [TE::BDEF::find_id $BOARD] 0} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-137 ERROR "Script (TE::INIT::init_board /[TE::BDEF::find_id/]) failed: $result."; return -code error} + } + switch $RUN { + -1 {TE::UTILS::te_msg TE_INIT-138 INFO " Clear only Mode selected..."} + 0 {start_existing_project $GUI } + 1 {generate_single_project $GUI } + 2 {generate_single_project_all $GUI } + 3 {generate_board_file_project_all $GUI } + default {abort_status "Error Initialisation..."; create_allboardfiles_status; return -code error "Error: Design run option $OPT not available, use [show_help]";} + } + TE::UTILS::te_msg TE_INIT-139 INFO "Run project finished without Error. \n \ + ------" + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished cmd functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--generate_dummi_project: for external programming without labtools and sdk only + proc generate_dummi_project {} { + file mkdir $TE::VPROJ_PATH/tmp + cd $TE::VPROJ_PATH/tmp + TE::UTILS::te_msg TE_INIT-140 STATUS "Create temporary vivado project in: [pwd]" + ::create_project -force tmp $TE::VPROJ_PATH/tmp + } + #-------------------------------- + #--delete_dummi_project: for external programming without labtools and sdk only + proc delete_dummi_project {oldpath} { + ::close_project + TE::UTILS::te_msg TE_INIT-141 STATUS "Delete temporary vivado project in: [pwd]" + cd $oldpath + if {[catch {file delete -force -- $TE::VPROJ_PATH/tmp} result ]} { + # somtimes is locked from other process + # puts "Info:(TE) Can't delete temporary folder." + } + } + #-------------------------------- + #--start_existing_project: + proc start_existing_project {GUI} { + if { [file exists $TE::VPROJ_PATH] } { + cd $TE::VPROJ_PATH + if { [file exists ${TE::VPROJ_NAME}.xpr] } { + TE::UTILS::te_msg TE_INIT-142 STATUS "Open existing project (File: ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.xpr)." + if {[catch {TE::VIV::open_project} result]} { TE::UTILS::te_msg TE_INIT-143 ERROR "Script (TE::VIV::open_project) failed: $result."; return -code error} + if {$GUI >= 1} {start_gui} + } else { + return -code error "Error: $TE::VPROJ_NAME.xpr not found in [pwd]"; + } + } else { + return -code error "Error: ${TE::VPROJ_PATH}/$TE::VPROJ_NAME.xpr not found"; + } + #--------------------------------------------- + } + #-------------------------------- + #--generate_single_project: + proc generate_single_project {GUI } { + if { [file exists $TE::VPROJ_PATH] } { + cd $TE::VPROJ_PATH + if { [file exists *.xpr] } { + return -code error "Error: Project folder not empty, clear [pwd]"; + } + } else { + TE::UTILS::te_msg TE_INIT-144 STATUS "Generate new project (Path: ${TE::VPROJ_PATH})." + file mkdir $TE::VPROJ_PATH + cd $TE::VPROJ_PATH + if {[catch {TE::VIV::create_project} result]} { TE::UTILS::te_msg TE_INIT-145 ERROR "Script (TE::VIV::create_project) failed: $result."; return -code error} + if {$GUI == 1} { start_gui } + if {[catch {TE::VIV::import_design} result]} { TE::UTILS::te_msg TE_INIT-146 ERROR "Script (TE::VIV::import_design) failed: $result."; return -code error} + if {$GUI == 2} { start_gui } + } + } + #-------------------------------- + #--generate_single_project_all: + proc generate_single_project_all {GUI} { + if {$GUI == 1} { generate_single_project 1 } else {generate_single_project 0 } + #-------------------------------------------------------- + run_current_project_all + #-------------------------------------------------------- + if {$GUI == 2} { start_gui} + } + #-------------------------------- + #--generate_board_file_project_all: + proc generate_board_file_project_all {GUI} { + + + foreach sublist $TE::BDEF::BOARD_DEFINITION { + set rundesign true + set id [lindex $sublist 0] + if {$id ne "ID" } { + if {[llength $TE::DESIGNRUNS] > 0} { + if {[lsearch -exact $TE::DESIGNRUNS $id] == -1} { + TE::UTILS::te_msg TE_INIT-147 STATUS "Skip ID: $id" + set rundesign false + } + } + if {$rundesign == true} { + TE::UTILS::te_msg TE_INIT-148 STATUS "Run project id $id (Path: [pwd]) \n \ + ------" + if {[catch {TE::UTILS::clean_vivado_project} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-149 ERROR "Script (TE::UTILS::clean_vivado_project) failed: $result."; return -code error} + if {[catch {TE::UTILS::clean_workspace_hsi} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-150 ERROR "Script (TE::UTILS::clean_workspace_hsi) failed: $result."; return -code error} + if {[catch {init_board $id 0} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-151 ERROR "Script (TE::init_board) failed: $result."; return -code error} + if {[catch {generate_single_project_all 0} result]} {abort_status "Error generate projects..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-152 ERROR "Script (TE::generate_single_project_all) failed: $result."; return -code error} + + TE::VIV::close_project + } + } + } + create_allboardfiles_status + } + #-------------------------------- + #--run_current_project_all: + proc run_current_project_all {} { + # if {[catch {TE::VIV::build_design ${TE::GEN_HW_BIT} ${TE::GEN_HW_MCS} ${TE::GEN_HW_RPT}} result]} {TE::VIV::report_summary;set message "Error:(TE) Script (TE::VIV::build_design) failed: $result."; abort_status $emessage; puts $emessage; return -code error} + set hw_options [list] + if {!${TE::GEN_HW_BIT}} {lappend hw_options "-disable_bitgen"; TE::UTILS::te_msg TE_INIT-153 WARNING "Auto-generation of Bit-file is disabled."} + if {!${TE::GEN_HW_RPT}} {lappend hw_options "-disable_reports"; TE::UTILS::te_msg TE_INIT-154 WARNING "Auto-generation of Report-file is disabled."} + if {!${TE::GEN_HW_HDF}} {lappend hw_options "-disable_hdf"; TE::UTILS::te_msg TE_INIT-155 WARNING "Auto-generation of HDF-file is disabled."} + if {!${TE::GEN_HW_MCS}} {lappend hw_options "-disable_mcsgen"; TE::UTILS::te_msg TE_INIT-156 WARNING "Auto-generation of MCS-file is disabled."} + if {[catch {eval TE::hw_build_design ${hw_options}} result]} {TE::VIV::report_summary;set emessage "Error: Script (TE::hw_build_design) failed: $result."; abort_status $emessage; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-157 ERROR "$emessage" ; return -code error} + #---------------------------------------------------------- + set sw_options [list] + if {!${TE::GEN_SW_HSI}} {lappend sw_options "-no_hsi"; TE::UTILS::te_msg TE_INIT-158 WARNING "Auto-generation of ELF-files is disabled."} + if {!${TE::GEN_SW_BIF}} {lappend sw_options "-no_bif"; TE::UTILS::te_msg TE_INIT-159 WARNING "Auto-generation of BIF-files is disabled."} + if {!${TE::GEN_SW_BIN}} {lappend sw_options "-no_bin"; TE::UTILS::te_msg TE_INIT-160 WARNING "Auto-generation of BIN-files is disabled."} + if {!${TE::GEN_SW_BITMCS}} {lappend sw_options "-no_bitmcs"; TE::UTILS::te_msg TE_INIT-161 WARNING "Auto-generation of BIT-files and MCS-files is disabled."} + if {${TE::GEN_SW_USEPREBULTHDF}} {lappend sw_options "-prebuilt_hdf_only"; lappend sw_options "$TE::SHORTDIR"; TE::UTILS::te_msg TE_INIT-162 WARNING "Prebuilt HDF is used."} + if {${TE::GEN_SW_FORCEBOOTGEN}} {lappend sw_options "-force_bin"; TE::UTILS::te_msg TE_INIT-163 WARNING "Force Boot.bin is used."} + lappend sw_options "-clear" + if {[catch {eval TE::sw_run_hsi ${sw_options}} result]} { set emessage "Error: Script (TE::sw_run_hsi) failed: $result."; abort_status $emessage; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-164 ERROR "$emessage" ; return -code error} + abort_status "Ok" + } + #-------------------------------- + #--generate_labtools_project: + proc generate_labtools_project { {gui ""} } { + if { [file exists $TE::VLABPROJ_PATH] } { + cd $TE::VLABPROJ_PATH + if { [file exists ${TE::VPROJ_NAME}.lpr] } { + if {[catch {TE::VLAB::open_project} result]} { TE::UTILS::te_msg TE_INIT-165 ERROR "Script (TE::VLAB::open_project) failed: $result."; return -code error} + } else { + if {[catch {TE::VLAB::create_project} result]} { TE::UTILS::te_msg TE_INIT-166 ERROR "Script (TE::VLAB::create_project) failed: $result."; return -code error} + } + } else { + TE::UTILS::te_msg TE_INIT-167 STATUS "Generate new project (Path: $TE::VLABPROJ_PATH)" + file mkdir $TE::VLABPROJ_PATH + cd $TE::VLABPROJ_PATH + if {[catch {TE::VLAB::create_project} result]} { TE::UTILS::te_msg TE_INIT-168 ERROR "Script (TE::VLAB::create_project) failed: $result."; return -code error} + } + if {$gui ne ""} { + start_gui + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished project design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # status files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--remove_status_files: + proc remove_status_files {} { + if { [file exists ${TE::LOG_PATH}/allboardparts.txt] } { + file delete -force ${TE::LOG_PATH}/allboardparts.txt + } + if { [file exists ${TE::LOG_PATH}/status.txt] } { + file delete -force ${TE::LOG_PATH}/status.txt + } + } + #-------------------------------- + #--create_allboardfiles_status: + proc create_allboardfiles_status {} { + set report_file ${TE::LOG_PATH}/allboardparts.txt + set fp_w [open ${report_file} "w"] + puts $fp_w "it's generate only for powershell polling..." + close $fp_w + } + #-------------------------------- + #--abort_status: + proc abort_status {message} { + set report_file ${TE::LOG_PATH}/status.txt + + if { ![file exists ${report_file}]} { + set fp_w [open ${report_file} "w"] + puts $fp_w "Run ${TE::BOARDPART} with Status $message" + close $fp_w + } else { + set fp_a [open ${report_file} "a"] + puts $fp_a "Run ${TE::BOARDPART} with Status $message" + close $fp_a + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished status files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "INFO:(TE) Load Designs script finished" +} + + diff --git a/zynqberrydemo1/scripts/script_environment.tcl b/zynqberrydemo1/scripts/script_environment.tcl new file mode 100644 index 0000000..c81803b --- /dev/null +++ b/zynqberrydemo1/scripts/script_environment.tcl @@ -0,0 +1,46 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/03 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/02/02 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval ::TE { + namespace eval ENV { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # initial vivado lib paths + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--set_path_boarddef: + proc set_path_boarddef {} { + TE::UTILS::te_msg TE_INIT-69 INFO "Set Board Definition path: $TE::BOARDDEF_PATH" + set_param board.repoPaths $TE::BOARDDEF_PATH + } + #-------------------------------- + #--set_path_boarddef: + proc set_path_ip {} { + TE::UTILS::te_msg TE_INIT-70 INFO "Set IP path : $TE::IP_PATH" + set_property IP_REPO_PATHS $TE::IP_PATH [current_fileset] + ::update_ip_catalog + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished vivado lib paths + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + + } + puts "INFO:(TE) Load environment script finished" +} + + diff --git a/zynqberrydemo1/scripts/script_external.tcl b/zynqberrydemo1/scripts/script_external.tcl new file mode 100644 index 0000000..7e17185 --- /dev/null +++ b/zynqberrydemo1/scripts/script_external.tcl @@ -0,0 +1,786 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/11 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/05/13 $ +# -------------------------------------------------------------------- +# -- 2017/05/12 bugfix missing bracket +# -- 2017/05/18 add pmuf to zynqmp bif +# -- 2017/06/13 add pmuf hsi/sdk support +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval EXT { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # *elf generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--run_sdk: + proc run_sdk {} { + set cur_path [pwd] + cd $TE::WORKSPACE_SDK_PATH + set tmplist [list] + if {[file exists ${TE::XILINXGIT_DEVICETREE}]} { + TE::UTILS::te_msg TE_SW-0 STATUS "Include Xilinx Device Tree git clone." + lappend tmplist "-lp" $TE::LIB_PATH + lappend tmplist "-lp" ${TE::XILINXGIT_DEVICETREE} + } else { + TE::UTILS::te_msg TE_SW-1 WARNING "Xilinx Device Tree git clone path not found (${TE::XILINXGIT_DEVICETREE})." + lappend tmplist "-lp" $TE::LIB_PATH + } + set command exec + lappend command xsdk + lappend command -workspace ${TE::WORKSPACE_SDK_PATH} + set hdffilename "" + [catch {set hdffilename [glob -join -dir ${TE::WORKSPACE_SDK_PATH}/ *.hdf]}] + if {[file exists ${TE::WORKSPACE_SDK_PATH}/${TE::PR_TOPLEVELNAME}.hdf]} { + lappend command -hwspec ${TE::WORKSPACE_SDK_PATH}/${TE::PR_TOPLEVELNAME}.hdf + } elseif {[file exists ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf]} { + lappend command -hwspec ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + } else { + lappend command -hwspec ${hdffilename} + } + # lappend command -hwspec ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + # lappend command -bit ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.bit + lappend command {*}$tmplist + # lappend command --vivrun + TE::UTILS::te_msg TE_SW-2 INFO "Start SKD: \n \ + Run \"$command\" in $TE::WORKSPACE_SDK_PATH \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-0 INFO "Command results from SDK \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } + #-------------------------------- + #--run_hsi: + proc run_hsi {} { + # list 0 for table header + if { [llength $TE::SW_APPLIST] > 1} { + set cur_path [pwd] + cd $TE::WORKSPACE_HSI_PATH + set tmp_libpath [list] + lappend tmp_libpath $TE::LIB_PATH + if {[file exists ${TE::XILINXGIT_DEVICETREE}]} { + TE::UTILS::te_msg TE_SW-3 STATUS "Include Xilinx Device Tree git clone." + lappend tmp_libpath ${TE::XILINXGIT_DEVICETREE} + } else { + TE::UTILS::te_msg TE_SW-4 WARNING "Xilinx Device Tree git clone path not found (${TE::XILINXGIT_DEVICETREE})." + } + set tmp_sw_liblist [list] + lappend tmp_sw_liblist $tmp_libpath + set tmp_sw_applist [list] + lappend tmp_sw_applist $TE::SW_APPLIST + # + set command exec + lappend command hsi + lappend command -source ${TE::SCRIPT_PATH}/script_hsi.tcl + lappend command -tclargs + lappend command "--sw_list ${tmp_sw_applist} --lib $tmp_sw_liblist --vivrun" + # lappend command --vivrun + TE::UTILS::te_msg TE_SW-5 INFO "Start HSI: \n \ + Run \"$command\" in $TE::WORKSPACE_HSI_PATH \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-1 INFO "Command results from HSI \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + TE::UTILS::copy_sw_files + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished *elf generation + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # *bit/*mcs generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--generate_app_bit_mcs: + proc generate_app_bit_mcs {{fname ""}} { + #microblaze + set int_shortdir ${TE::SHORTDIR} + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + } + #run only if *.mmi exists + if {[file exists ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi]} { + # read processor from mmi + set fp [open "${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi" r] + set file_data [read $fp] + close $fp + set tmp [split $file_data "\n"] + foreach t $tmp { + if {[string match *InstPath=* $t] } { + set splittstring [split $t "="] + set next false + set hitval "NA" + foreach part $splittstring { + if {$next} { + set hitval $part + break + } + if {[string match *InstPath* $part] } { + set next true + } + } + set hitval [string map {">" ""} $hitval] + set hitval [string map {"\"" ""} $hitval] + if { $hitval eq "NA"} { + TE::UTILS::te_msg TE_SW-6 ERROR "Processor not found in ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi." + return -code error "Processor not found in ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi."; + } + } + } + #--------------- + foreach sw_applist_line ${TE::SW_APPLIST} { + #generate modified mcs or bit only if app_list.csv->steps=0(generate all), add file to mcs use "FIRM" + set app_name [lindex $sw_applist_line 1] + if {[lindex $sw_applist_line 2] eq "0"} { + #read app name + #delete old one + if {[file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/${app_name}.bit]} { + file delete -force ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/${app_name}.bit + } + #make folder if not exists + file mkdir ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + # + #todo:hier noch in default suche? + TE::UTILS::te_msg TE_SW-7 STATUS "Generate ${app_name}.bit with app: ${app_name}." + set command exec + lappend command updatemem + lappend command -force + lappend command -meminfo ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi + lappend command -data ${TE::PREBUILT_SW_PATH}/${int_shortdir}/${app_name}.elf + lappend command -bit ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.bit + lappend command -proc $hitval + lappend command -out ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/${app_name}.bit + TE::UTILS::te_msg TE_SW-8 INFO "Start Update Memory: \n \ + Run \"$command\" in ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-2 INFO "Command results from Update Memory \"$command\": \n \ + $result \n \ + ------" + } + #write mcs + if {[lindex $sw_applist_line 2] eq "0" || [lindex $sw_applist_line 2] eq "FIRM"} { + if {$TE::CFGMEM_MEMSIZE_MB ne "NA"} { + #todo generate relativ path from absolute paths + set rel_bitfile "../prebuilt/hardware" + set rel_bitfile2 "../prebuilt/boot_images" + set rel_data_file ".." + #make folder if not exists + file mkdir ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + # + TE::UTILS::te_msg TE_SW-8 STATUS "Generate ${app_name}.mcs with app: ${app_name}." + #set bitfile to mcs load + if {[lindex $sw_applist_line 2] eq "FIRM"} { + set load_data "up 0x0 ${rel_bitfile}/${int_shortdir}/${TE::VPROJ_NAME}.bit " + } else { + set load_data "up 0x0 ${rel_bitfile2}/${int_shortdir}/${app_name}/${app_name}.bit " + } + #get upload data 01: + set data_index 5 + while {$data_index < [llength $sw_applist_line] } { + if {[lindex $sw_applist_line 5] ne "NA"} { + set load_data "$load_data up [lindex $sw_applist_line [expr $data_index+1]] ${rel_data_file}/[lindex $sw_applist_line $data_index] " + } + set data_index [expr $data_index+3] + } + #write mcs + # -loadbit $load_bit + write_cfgmem -force -format mcs -checksum FF -interface $TE::CFGMEM_IF -size $TE::CFGMEM_MEMSIZE_MB \ + -loaddata $load_data \ + -file ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/${app_name}.mcs + } else { + TE::UTILS::te_msg TE_SW-9 {CRITICAL WARNING} "FPGA FLASH TYP is not specified in *.board_files.csv. *.mcs file is not generated." + } + } + } + } else { + TE::UTILS::te_msg TE_SW-10 WARNING "${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi not found. Nothing is done." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished *bit/*mcs generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # *bin/*bif generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--generate_bif_files: + proc generate_bif_files {{fname ""}} { + set int_shortdir ${TE::SHORTDIR} + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + } + #todo generate relativ path from absolute paths + set checkfile "" + set fsbl_name "" + set rel_bif_bitfile "../../../hardware" + set rel_bif_fsbl "../../../software" + set rel_bif_hsipmu "../../../software" + set rel_bif_data01_file "../../../../" + set rel_bif_appfile "../../../" + set rel_base "" + set bif_bitfile "" + set bif_fsbl "" + set bif_data01_file "" + set bif_appfile "" + + #check bitfile + if {![file exists ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.bit]} { + # search default + if {![file exists ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit]} { + # default not found + TE::UTILS::te_msg TE_SW-11 ERROR "Bit-file was not found (${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.bit or ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit)" + return -code error "Project bit-file was not found (${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.bit or ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit)"; + } else { + set bif_bitfile "${rel_bif_bitfile}/default/${TE::VPROJ_NAME}.bit" + } + } else { + set bif_bitfile "${rel_bif_bitfile}/${int_shortdir}/${TE::VPROJ_NAME}.bit" + } + #search for fsbl + foreach sw_applist_line ${TE::SW_APPLIST} { + #read fsbl name + if {[lindex $sw_applist_line 2] eq "FSBL" || [lindex $sw_applist_line 2] eq "FSBL_EXT"} { + set fsbl_name [lindex $sw_applist_line 1] + if {![file exists ${TE::PREBUILT_SW_PATH}/${int_shortdir}/${fsbl_name}.elf]} { + # generate fsbl not found search default + if {![file exists ${TE::PREBUILT_SW_PATH}/default/${fsbl_name}.elf]} { + # default fsbl not found + TE::UTILS::te_msg TE_SW-12 ERROR "FSBL ELF-file was not found (${TE::PREBUILT_SW_PATH}/${int_shortdir}/${fsbl_name}.elf or ${TE::PREBUILT_SW_PATH}/default/${fsbl_name}.elf)." + return -code error "FSBL ELF-file was not found (${TE::PREBUILT_SW_PATH}/${int_shortdir}/${fsbl_name}.elf or ${TE::PREBUILT_SW_PATH}/default/${fsbl_name}.elf)."; + } else { + set bif_fsbl "${rel_bif_fsbl}/default/${fsbl_name}.elf" + TE::UTILS::te_msg TE_SW-13 INFO "Use FSBL from: ${bif_fsbl}" + } + } else { + set bif_fsbl "${rel_bif_fsbl}/${int_shortdir}/${fsbl_name}.elf" + TE::UTILS::te_msg TE_SW-14 INFO "Use FSBL from: ${bif_fsbl}" + } + } + } + foreach sw_applist_line ${TE::SW_APPLIST} { + #generate *.bif only if app_list.csv->steps=0(generate all) or steps=1(*.bif and *.bin use *.elf from prebuild folders ) + if {[lindex $sw_applist_line 2] eq "0" || [lindex $sw_applist_line 2] eq "1" || [lindex $sw_applist_line 2] eq "FSBL_APP"} { + #set correct folders + switch [lindex $sw_applist_line 3] { + "petalinux" { + set checkfile "${TE::PREBUILT_OS_PATH}/petalinux" + set rel_base "${rel_bif_appfile}os/petalinux" + + } + default {#standalone + set checkfile "${TE::PREBUILT_SW_PATH}" + set rel_base "${rel_bif_appfile}software" + } + } + #read fsbl name + #read app name and additional configs + set app_name [lindex $sw_applist_line 1] + TE::UTILS::te_msg TE_SW-15 STATUS "Generate BIF-file for: ${app_name}" + #delete old folder + if {[file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}]} { + file delete -force ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + } + #make new one + file mkdir ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + + if {![file exists ${checkfile}/${int_shortdir}/${app_name}.elf]} { + if { [lindex $sw_applist_line 2] eq "FSBL_APP"} { + # fsbl boot.bin only + set bif_appfile "" + } elseif {![file exists ${checkfile}/default/${app_name}.elf]} { + # search default + # default not found + TE::UTILS::te_msg TE_SW-16 ERROR "Application ELF-file was not found (${checkfile}/${int_shortdir}/${app_name}.elf or ${checkfile}/default/${app_name}.elf)." + return -code error "Application ELF-file was not found (${checkfile}/${int_shortdir}/${app_name}.elf or ${checkfile}/default/${app_name}.elf)."; + } else { + set bif_appfile "${rel_base}/default/${app_name}.elf" + } + + } else { + set bif_appfile "${rel_base}/${int_shortdir}/${app_name}.elf" + } + if {$TE::IS_ZSYS} { + #Zynq + set data01_file [lindex $sw_applist_line 5] + set data01_load [lindex $sw_applist_line 6] + set data01_offset [lindex $sw_applist_line 7] + #replace na with "" + if {[string match $data01_file "NA"]} { set bif_data01_file ""} else { set bif_data01_file "${rel_bif_data01_file}${data01_file}"} + if {[string match $data01_load "NA"]} { set data01_load ""} + if {[string match $data01_offset "NA"]} { set data01_offset ""} + + write_bif ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif $bif_fsbl $bif_bitfile $bif_appfile $bif_data01_file $data01_load $data01_offset "" "" "" + } elseif {$TE::IS_ZUSYS} { + #uzynq + set fsbl_config [lindex $sw_applist_line 5] + if {[string match $fsbl_config "NA"]} { set fsbl_config ""} + set destination_cpu [lindex $sw_applist_line 6] + if {[string match $destination_cpu "NA"]} { set destination_cpu ""} + set exception_level [lindex $sw_applist_line 7] + if {[string match $exception_level "NA"]} { set exception_level ""} + set atf [lindex $sw_applist_line 8] + if {[string match $atf "NA"]} { set atf ""} elseif {[file exists ${checkfile}/${int_shortdir}/${atf}]} { + set atf ${rel_base}/${int_shortdir}/${atf} + } elseif {[file exists ${checkfile}/default/${atf}]} { + set atf ${rel_base}/default/${atf} + } else { + TE::UTILS::te_msg TE_SW-17 WARNING "ATF File was not found in ${checkfile}/${int_shortdir}/${atf} or ${checkfile}/default/${atf}" + set atf "" + } + set pmu [lindex $sw_applist_line 9] + if {[string match $pmu "NA"]} { + set pmu "" + TE::UTILS::te_msg TE_SW-65 WARNING "PMU File not selected on apps_list.csv" + } elseif {[file exists ${TE::PREBUILT_SW_PATH}/${int_shortdir}/${pmu}]} { + set pmu ${rel_bif_hsipmu}/${int_shortdir}/${pmu} + } elseif {[file exists ${TE::PREBUILT_SW_PATH}/default/${pmu}]} { + set pmu ${rel_bif_hsipmu}/default/${pmu} + } elseif {[file exists ${checkfile}/${int_shortdir}/${pmu}]} { + set pmu ${rel_base}/${int_shortdir}/${pmu} + } elseif {[file exists ${checkfile}/default/${pmu}]} { + set pmu ${rel_base}/default/${pmu} + } else { + TE::UTILS::te_msg TE_SW-64 WARNING "PMU File ($pmu) was not found in all possible prebuilt folders" + set pmu "" + } + TE::UTILS::te_msg TE_SW-66 INFO "Use PMU from: ${pmu}" + + write_zusys_bif -biffile ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif -fsbl_config $fsbl_config -bootloader $bif_fsbl -pmu $pmu -bitfile $bif_bitfile -app $bif_appfile -destination_cpu $destination_cpu -exception_level $exception_level -atf $atf + + } else { + #error + TE::UTILS::te_msg TE_SW-18 ERROR "ZSYS or ZUSYS is not defined." + } + } + } + } + #-------------------------------- + #--write_bif: + proc write_bif { biffile {fsblfile "zynq_fsbl.elf"} {bitfile ""} {elffile ""} {data01_file ""} {data01_load ""} {data01_offset ""} {dtbfile ""} {intfile ""} {ssblfile ""} } { + + set bif_fp [open "$biffile" w] + + puts $bif_fp "the_ROM_image:\n\u007B" + # + # init data + # + if {$intfile!=""} { puts -nonewline $bif_fp { [init]}} + if {$intfile!=""} { puts $bif_fp $intfile} + if {$intfile == ""} {TE::UTILS::te_msg TE_SW-19 STATUS "INT FILE NOT DEFINED..."} + # + # FSBL + # + if {$fsblfile!=""} { puts -nonewline $bif_fp { [bootloader]}} + if {$fsblfile!=""} { puts $bif_fp $fsblfile} + if {$fsblfile == ""} {TE::UTILS::te_msg TE_SW-21 STATUS "FSBL FILE NOT DEFINED..."} + # + # BIT file + # + if {$bitfile!=""} { puts $bif_fp " $bitfile"} + if {$bitfile == ""} {TE::UTILS::te_msg TE_SW-22 STATUS "BIT FILE NOT DEFINED..."} + # + # .ELF file + # + if {$elffile!=""} { puts $bif_fp " $elffile"} + if {$elffile == ""} {TE::UTILS::te_msg TE_SW-23 STATUS "ELF FILE NOT DEFINED..."} + # + # SSBL + # + if {$ssblfile!=""} { puts $bif_fp " $ssblfile"} + if {$ssblfile == ""} {TE::UTILS::te_msg TE_SW-24 STATUS "SSBL FILE NOT DEFINED..."} + # + # DTB file + # + if {$dtbfile!=""} { puts $bif_fp " $dtbfile"} + if {$dtbfile == ""} {TE::UTILS::te_msg TE_SW-25 STATUS "DTB FILE NOT DEFINED..."} + # + # image.ub ore IMAGE file + # + + if {$data01_load!="" || $data01_offset!=""} { puts -nonewline $bif_fp { [}} + if {$data01_load!="" } { puts -nonewline $bif_fp {load = };puts -nonewline $bif_fp "$data01_load"} + if {$data01_load!="" && $data01_offset!=""} { puts -nonewline $bif_fp { , }} + if {$data01_offset!="" } { puts -nonewline $bif_fp {offset = };puts -nonewline $bif_fp "$data01_offset"} + if {$data01_load!="" || $data01_offset!=""} { puts -nonewline $bif_fp {]}} + if {$data01_file!=""} { puts $bif_fp $data01_file} + + if {$data01_load == ""} {TE::UTILS::te_msg TE_SW-26 STATUS "FILE01 LOAD NOT DEFINED..."} + if {$data01_offset == ""} {TE::UTILS::te_msg TE_SW-27 STATUS "FILE01 OFFSET NOT DEFINED..."} + if {$data01_file == ""} {TE::UTILS::te_msg TE_SW-28 STATUS "FILE01 FILE NOT DEFINED..."} + + + puts $bif_fp "\u007D" + + close $bif_fp + + } + #-------------------------------- + #--write_zusys_bif: + proc write_zusys_bif {{args ""}} { + set biffile "" + set fsbl_config "" + set bootloader "" + set pmu "" + set bitfile "" + set destination_cpu "" + set exception_level "" + #bl31.elf + set atf "" + set app "" + + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-biffile" { incr option; set biffile [lindex $args $option]} + "-fsbl_config" { incr option; set fsbl_config [lindex $args $option]} + "-bootloader" { incr option; set bootloader [lindex $args $option]} + "-pmu" { incr option; set pmu [lindex $args $option]} + "-bitfile" { incr option; set bitfile [lindex $args $option]} + "-destination_cpu" { incr option; set destination_cpu [lindex $args $option]} + "-exception_level" { incr option; set exception_level [lindex $args $option]} + "-atf" { incr option; set atf [lindex $args $option]} + "-app" { incr option; set app [lindex $args $option]} + default {TE::UTILS::te_msg TE_SW-29 ERROR "unrecognised option for BIF generation: [lindex $args $option]";return -code error } + } + } + set bif_fp [open "$biffile" w] + + puts $bif_fp "//arch = zynqmp; split = false; format = BIN" + puts $bif_fp "the_ROM_image:\n\u007B" + #fsbl_config + if {$fsbl_config!=""} { puts -nonewline $bif_fp { [fsbl_config]}} + if {$fsbl_config!=""} { puts $bif_fp $fsbl_config} + if {$fsbl_config == ""} {TE::UTILS::te_msg TE_SW-30 STATUS "FSBL_CONFIG NOT DEFINED..."} + #bootloader + if {$bootloader!=""} { puts -nonewline $bif_fp { [bootloader]}} + if {$bootloader!=""} { puts $bif_fp $bootloader} + if {$bootloader == ""} {TE::UTILS::te_msg TE_SW-31 STATUS "BOOTLOADER NOT DEFINED..."} + #pmuf + if {$pmu!=""} { puts -nonewline $bif_fp { [pmufw_image]}} + if {$pmu!=""} { puts $bif_fp $pmu} + if {$pmu == ""} {TE::UTILS::te_msg TE_SW-31 STATUS "PMU NOT DEFINED..."} + #bitfile + if {$bitfile!=""} { puts -nonewline $bif_fp { [destination_device = pl]}} + if {$bitfile!=""} { puts $bif_fp $bitfile} + if {$bitfile == ""} {TE::UTILS::te_msg TE_SW-32 STATUS "BITFILE NOT DEFINED..."} + #atf + if {$atf!=""} { puts -nonewline $bif_fp { [}} + if {$atf!=""} { puts -nonewline $bif_fp "destination_cpu =$destination_cpu"} + if {$atf!=""} { puts -nonewline $bif_fp ", exception_level =el-3"} + if {$atf!=""} { puts -nonewline $bif_fp {]}} + if {$atf!=""} { puts $bif_fp $atf} + if {$atf == ""} {TE::UTILS::te_msg TE_SW-33 STATUS "ATF BL31 ELF NOT DEFINED..."} + #elf + if {$app!=""} { puts -nonewline $bif_fp { [}} + if {$app!=""} { puts -nonewline $bif_fp "destination_cpu =$destination_cpu"} + if {$app!="" && $exception_level!=""} { puts -nonewline $bif_fp ", exception_level =$exception_level"} + if {$app!=""} { puts -nonewline $bif_fp {]}} + if {$app!=""} { puts $bif_fp $app} + if {$app == ""} {TE::UTILS::te_msg TE_SW-34 STATUS "APPLICATION ELF NOT DEFINED..."} + + puts $bif_fp "\u007D" + + close $bif_fp + + } + #-------------------------------- + #--generate_bootbin: + proc generate_bootbin {{fname ""}} { + set int_shortdir ${TE::SHORTDIR} + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + } + foreach sw_applist_line ${TE::SW_APPLIST} { + #generate *.bin only if app_list.csv->steps=0(generate all) or steps=1(*.bif and *.bin use *.elf from prebuild folders ) or steps=2(*.bin use *.elf and *.bif from prebuild folders) + if {[lindex $sw_applist_line 2]==0 || [lindex $sw_applist_line 2]==1 || [lindex $sw_applist_line 2]==2 || [lindex $sw_applist_line 2] eq "FSBL_APP"} { + #read app name + set app_name [lindex $sw_applist_line 1] + #delete old one + if {[file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bin]} { + file delete -force ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bin + } + # + if {![file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif]} { + TE::UTILS::te_msg TE_SW-35 ERROR "Application BIF-File found (${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif)." + return -code error "Application BIF-File found (${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif)."; + } + #todo:hier noch in default suche? + TE::UTILS::te_msg TE_SW-36 STATUS "Generate Boot.bin for Application: ${app_name}" + set cur_path [pwd] + cd ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + set command exec + lappend command bootgen + lappend command -image boot.bif + #Ultrascale+Zynq + if {$TE::IS_ZUSYS} { + lappend command -arch zynqmp + } + lappend command -w -o BOOT.bin + # puts $command + TE::UTILS::te_msg TE_SW-37 INFO "Start BootGen: \n \ + Run \"$command\" in ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-3 INFO "Command results from BootGen \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished *bin/*bif generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--get_available_apps: + proc get_available_apps {{fname ""}} { + set int_shortdir ${TE::SHORTDIR} + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + } + set applist [] + [catch {set applist [glob -join -dir ${TE::PREBUILT_BI_PATH}/${int_shortdir}/ *]}] + set app_txt "Following Applications are available: \n" + foreach app $applist { + set tmp [split $app "/"] + set app_txt "$app_txt [lindex $tmp [expr [llength $tmp]-1]]\n" + } + TE::UTILS::te_msg TE_PR-38 INFO "$app_txt ------" + } + #-------------------------------- + #--excecute_zynq_flash_programming: + proc excecute_zynq_flash_programming {use_basefolder app_name {fname ""}} { + set return_filename "" + set int_shortdir ${TE::SHORTDIR} + set int_flashtyp $TE::ZYNQFLASHTYP + set run_path "" + set bootbinname BOOT.bin + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + #get flashtyp form shortdir + set int_flashtyp "[TE::BDEF::get_zynqflashtyp $int_shortdir 4]" + } + if {![string match $int_flashtyp "NA"]} { + set cur_path [pwd] + if {$use_basefolder} { + set binfilename "" + if { ![catch {set binfilename [glob -join -dir ${TE::BASEFOLDER}/ *.bin]}] } { + TE::UTILS::te_msg TE_PR-39 STATUS "Used file:${binfilename}" + set return_filename ${binfilename} + set run_path $TE::BASEFOLDER + set nameonly [file tail [file rootname $binfilename]] + set bootbinname ${nameonly}.bin + } else { + TE::UTILS::te_msg TE_PR-40 ERROR "Bin-File was not found in ${TE::BASEFOLDER}." + return -code error "Bin-File was not found in ${TE::BASEFOLDER}."; + } + cd ${TE::BASEFOLDER} + } else { + if {![file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/BOOT.bin]} { + TE::UTILS::te_msg TE_PR-41 ERROR "Application Bin-File was not found (${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/BOOT.bin)." + return -code error "Application Bin-File was not found (${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/BOOT.bin)."; + } + cd ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + set run_path ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + set bootbinname BOOT.bin + TE::UTILS::te_msg TE_PR-40 STATUS "Used file:${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/Boot.bin" + set return_filename ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/Boot.bin + } + set command exec + + # lappend command zynq_flash + lappend command program_flash + lappend command -f $bootbinname + lappend command -flash_type $int_flashtyp + TE::UTILS::te_msg TE_PR-41 INFO "Start program flash: \n \ + Run \"$command\" in ${run_path} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-4 INFO "Command results from program flash \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } else { + TE::UTILS::te_msg TE_PR-42 ERROR "Programming failed: Zynq Flash Typ is not specified for this board part. See ${TE::BOARDDEF_PATH}/..._board_files.csv" + } + return $return_filename + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # utilities functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--svn_checkin: + proc svn_checkin {foldername {mgs ""}} { + set message $mgs + if {![file exists $foldername]} { + set message "Error: Folder not found ( $foldername)" + } else { + set cur_path [pwd] + cd ${foldername} + set command exec + lappend command svn + lappend command ci + lappend command -m $message + TE::UTILS::te_msg TE_UTIL-72 INFO "Start SVN Checkin: \n \ + Run \"$command\" in ${foldername} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-5 INFO "Command results from SVN check in \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } + } + #-------------------------------- + #--unzip_project: + proc unzip_project {zipname file_location} { + set command exec + if {${TE::ZIP_PATH} ne ""} { + if {[file tail [file rootname ${TE::ZIP_PATH}]] eq "7z"} { + lappend command ${TE::ZIP_PATH} + lappend command x ${file_location}/${zipname} + lappend command -o${file_location} + } else { + lappend command ${TE::ZIP_PATH} + lappend command -help + # lappend command -e ${file_location}/${zipname} + # lappend command ${file_location} + } + TE::UTILS::te_msg TE_UTIL-73 INFO "Start UNZIP: \n \ + Run \"$command\" \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-6 INFO "Command results from UNZIP \"$command\": \n \ + $result \n \ + ------" + } else { + TE::UTILS::te_msg TE_UTIL-74 {CRITICAL WARNING} "Zip not specified. Set zip path and *exe of the zip program in \"design_basic_settings.cmd\" file : example 7zip: @set ZIP_PATH=C:/Program Files (x86)/7-Zip/7z.exe" + } + } + #-------------------------------- + #--zip_project: + proc zip_project {zipname {excludelist ""}} { + #todo mit übergabeparameter prebuilt weglassen oder so + #remove old backup project copy + set sourcepath [string trim $TE::VPROJ_PATH "vivado"] + set destinationpath ${TE::BACKUP_PATH}/${TE::VPROJ_NAME} + if {[file exists ${destinationpath}]} { + file delete -force ${destinationpath} + } + #create new destination folder + file mkdir ${destinationpath} + set cur_path [pwd] + cd ${TE::BACKUP_PATH} + #get all files + set filelist [ glob ${sourcepath}*] + #remove backup folder + set findex [lsearch $filelist *backup] + set filelist [lreplace $filelist[set filelist {}] $findex $findex] + + foreach el $filelist { + file copy -force ${el} ${destinationpath} + } + set excludelist + foreach el $excludelist { + set find "" + if {[catch {set find [glob -join -dir $destinationpath $el]}]} { + TE::UTILS::te_msg TE_UTIL-75 INFO "$el not found." + } else { + TE::UTILS::te_msg TE_UTIL-76 INFO "Excluded from backup:$find" + file delete -force $find + } + } + set command exec + if {${TE::ZIP_PATH} ne ""} { + if {[file tail [file rootname ${TE::ZIP_PATH}]] eq "7z"} { + lappend command ${TE::ZIP_PATH} + lappend command a -tzip "$zipname.zip" + lappend command "./${TE::VPROJ_NAME}/" + lappend command -r + } else { + lappend command ${TE::ZIP_PATH} + lappend command -r + lappend command "$zipname.zip" + lappend command "./${TE::VPROJ_NAME}/*.*" + } + TE::UTILS::te_msg TE_UTIL-77 INFO "Start ZIP: \n \ + Run \"$command\" \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-7 INFO "Command results from ZIP \"$command\": \n \ + $result \n \ + ------" + } else { + TE::UTILS::te_msg TE_UTIL-78 {CRITICAL WARNING} "Zip not specified. Set zip path and *exe of the zip program in \"design_basic_settings.cmd\" file : example 7zip: @set ZIP_PATH=C:/Program Files (x86)/7-Zip/7z.exe" + } + #remove project copy + if {[file exists ${destinationpath}]} { + file delete -force ${destinationpath} + } + cd $cur_path + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished utilities functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # SDSoC functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--run_sdsoc: + proc run_sdsoc {} { + set cur_path [pwd] + cd ${TE::SDSOC_PATH} + set command exec + lappend command sdsoc + lappend command -workspace ${TE::SDSOC_PATH} + # lappend command -lp ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + TE::UTILS::te_msg TE_SW-38 INFO "Start SDSoC: \n \ + Run \"$command\" in ${TE::SDSOC_PATH} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-8 INFO "Command results from SDSoC \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished sdsoc functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "INFO:(TE) Load Vivado script finished" +} + + diff --git a/zynqberrydemo1/scripts/script_hsi.tcl b/zynqberrydemo1/scripts/script_hsi.tcl new file mode 100644 index 0000000..3fa4ab1 --- /dev/null +++ b/zynqberrydemo1/scripts/script_hsi.tcl @@ -0,0 +1,270 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/05 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/06/13 $ +# -------------------------------------------------------------------- +# -- 2017/06/13 add pmuf hsi support +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval HSI { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # TE HSI variablen declaration + # ----------------------------------------------------------------------------------------------------------------------------------------- + variable HDF_NAME + variable LIB_PATH + variable SW_APPLIST + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished TE HSI variablen declaration + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hsi hw functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--open_project: + proc open_project {} { + if {[catch {set TE::HSI::HDF_NAME [glob -join -dir [pwd] *.hdf]} result]} { puts "Error:(TE) Script (TE::HSI::hsi_open_project) failed: $result."; return -code error} + #todo: eventuell mal extra verzeichnis erstellen, wie sdk + open_hw_design ${TE::HSI::HDF_NAME} + } + #-------------------------------- + #--set_repopath: + proc set_repopath {} { + set_repo_path ${TE::HSI::LIB_PATH} + } + #-------------------------------- + #--close_project: + proc close_project {} { + close_hw_design [current_hw_design] + } + #-------------------------------- + #--get_processors: + proc get_processors {PROCESSOR_ID} { + set proc [get_cells -filter {IP_TYPE==PROCESSOR}] + if {[llength $proc] == 0} { + return -code error "Error:(TE) No Processor found in design ${TE::HSI::HDF_NAME}"; + } else { + if {[llength $proc] > 1} { + puts "Info:(TE) Multiple Processors found." + } + if {[llength $proc] > $PROCESSOR_ID} { + puts "Info:(TE) Processor [lindex $proc $PROCESSOR_ID] is used." + return [lindex $proc $PROCESSOR_ID] + } else { + return -code error "Error:(TE) No Processor ID $PROCESSOR_ID not found in design ${TE::HSI::HDF_NAME}"; + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished hw functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hsi sw functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--create_sw_project: + proc create_sw_project {app_name os uart {proc_id 0}} { + puts "Test: $app_name , $proc_id" + set cpu [get_processors $proc_id] + set hwdesign [current_hw_design] + set swdesign [hsi::create_sw_design system -proc $cpu -app $app_name -os $os] + set os [hsi::get_os] + if {$uart ne "NA"} { + #workaround to change uart -> currently generate_app will delete bsp and write default one + generate_app -hw $hwdesign -sw $swdesign -app $app_name -proc $cpu -dir $app_name -os $os + hsi::close_sw_design $swdesign + hsi::open_sw_design ${app_name}/${app_name}_bsp/system.mss + #reset old variables + set swdesign [get_sw_designs] + set os [hsi::get_os] + #set uart properties + common::set_property CONFIG.stdin $uart $os + common::set_property CONFIG.stdout $uart $os + #generate bsp + hsi::generate_bsp -dir ${app_name}/${app_name}_bsp/ -compile + cd ${app_name} + set result "" + #run make + if {[catch {set result [eval exec make]}]} {puts "Info:(TE) $result"} + cd .. + } else { + generate_app -hw $hwdesign -sw $swdesign -app $app_name -proc $cpu -os $os -dir $app_name -verbose -compile + } + close_sw_design $swdesign + } + #-------------------------------- + #--create_devicetree_project: + proc create_devicetree_project {app_name os} { + set cpu [get_processors 0] + set hwdesign [current_hw_design] + set swdesign [hsi::create_sw_design $app_name -proc $cpu -os $os] + generate_target -dir $app_name + close_sw_design $swdesign + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished sw functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hsi run functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--run_sw_apps: + proc run_sw_apps {} { + #search and generate fsbl and device tree + foreach sw_applist_line ${TE::HSI::SW_APPLIST} { + #generate fsbl only + if {[lindex $sw_applist_line 2] eq "FSBL" } { + set name [lindex $sw_applist_line 1] + set os [lindex $sw_applist_line 3] + set uart [lindex $sw_applist_line 4] + puts "Info:(TE) generate FSBL: $name os: $os Uart: $uart" + create_sw_project $name $os $uart + } + #generate pmu UynqMP only + if {[lindex $sw_applist_line 2] eq "PMU" } { + set name [lindex $sw_applist_line 1] + set os [lindex $sw_applist_line 3] + set uart [lindex $sw_applist_line 4] + #select pmu + set proc_id 6 + puts "Info:(TE) generate PMU: $name os: $os Uart: $uart" + create_sw_project $name $os $uart $proc_id + } + #generate device tree only + if {[lindex $sw_applist_line 2] eq "DTS" } { + set name [lindex $sw_applist_line 1] + set os [lindex $sw_applist_line 3] + puts "Info:(TE) generate Device-Tree: $name os: $os" + create_devicetree_project $name $os + } + } + #search and generate software apps + foreach sw_applist_line ${TE::HSI::SW_APPLIST} { + #generate *.bin only if app_list.csv->steps=0(generate all) or steps=3(*.elf only ) + if {[lindex $sw_applist_line 2] == 0 || [lindex $sw_applist_line 2] == 3} { + set name [lindex $sw_applist_line 1] + set os [lindex $sw_applist_line 3] + set uart [lindex $sw_applist_line 4] + puts "Info:(TE) generate app: $name os: $os Uart: $uart" + create_sw_project $name $os $uart + } + } + } + #-------------------------------- + #--debug_sw_app_list: + proc debug_sw_app_list {} { + set TE::HSI::SW_APPLIST [list] + foreach lpath ${TE::HSI::LIB_PATH} { + if {[file exists ${lpath}/apps_list.csv]} { + puts "Info:(TE) Read Software list from ${lpath}/apps_list.csv" + set fp [open "${lpath}/apps_list.csv" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + # set fsbl_name "" + foreach line $data { + # check file version ignore comments and empty lines + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #check version + set tmp [split $line "="] + #version is ignored for debug only + } elseif {[string match *#* $line] != 1 && [string length $line] > 0} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #splitt and append + set tmp [split $line ","] + lappend TE::HSI::SW_APPLIST $tmp + } + } + } + } + puts "------------------------------------------" + } + #-------------------------------- + #--run_all: + proc run_all {} { + #todo: run all als option und hsi auch über batch separat startbar + puts "Info:(TE) HSI...run all..." + if {[catch {open_project} result]} { puts "Error:(TE) Script (TE::HSI::open_project) failed: $result."; return -code error} + if {[catch {set_repopath} result]} { puts "Error:(TE) Script (TE::HSI::set_repopath) failed: $result."; return -code error} + #---------------------------------------- + if {[catch {run_sw_apps} result]} { puts "Error:(TE) Script (TE::HSI::run_sw_apps) failed: $result."; return -code error} + #---------------------------------------- + if {[catch {close_project} result]} { puts "Error:(TE) Script (TE::HSI::close_project) failed: $result."; return -code error} + } + #-------------------------------- + #--return_option: + proc return_option {option argc argv} { + if { $argc <= [expr $option + 1]} { + return -code error "Error:(TE) Read parameter failed" + } else { + puts "Info:(TE) Parameter Option Value: [lindex $argv [expr $option + 1]]" + return [lindex $argv [expr $option + 1]] + } + } + #-------------------------------- + #--hsi_main: + proc hsi_main {} { + global argc + global argv + set tmp_argc 0 + set tmp_argv 0 + if {$argc >= 1 } { + set tmp_argv [lindex $argv 0] + set tmp_argc [llength $tmp_argv] + } + + set vivrun false + variable SW_APPLIST + variable LIB_PATH + + for {set option 0} {$option < $tmp_argc} {incr option} { + puts "Info:(TE) Parameter Index: $option" + puts "Info:(TE) Parameter Option: [lindex $tmp_argv $option]" + switch [lindex $tmp_argv $option] { + "--sw_list" { set SW_APPLIST [return_option $option $tmp_argc $tmp_argv];incr option } + "--lib" { set LIB_PATH [return_option $option $tmp_argc $tmp_argv];incr option } + "--vivrun" { set vivrun true } + default { puts "" } + } + } + if {$vivrun==true} { + if {[catch {run_all} result]} { puts "Error:(TE) Script (TE::HSI::run_all) failed: $result."; exit} + exit + } + + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished run functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hsi run scripts + # ----------------------------------------------------------------------------------------------------------------------------------------- + if {[catch {hsi_main} result]} { puts "Error:(TE) Script (TE::HSI::hsi_main) failed: $result."; exit} + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished hsi run scripts + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "Info: Load HSI scripts finished" +} + + diff --git a/zynqberrydemo1/scripts/script_main.tcl b/zynqberrydemo1/scripts/script_main.tcl new file mode 100644 index 0000000..28d8483 --- /dev/null +++ b/zynqberrydemo1/scripts/script_main.tcl @@ -0,0 +1,184 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/02 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/06/30 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +puts "-----------------------------------------------------------------------" +#load source scripts +source ../scripts/script_settings.tcl +source ../scripts/script_environment.tcl +source ../scripts/script_vivado.tcl +source ../scripts/script_te_utils.tcl +source ../scripts/script_external.tcl +source ../scripts/script_designs.tcl +source ../scripts/script_usrcommands.tcl +source ../scripts/script_sdsoc.tcl +#sources from other programs: +# source ../scripts/main.tcl +# source ../scripts/hsi.tcl +set sdsoc_available "0" +catch {set sdsoc_available $::env(SDSOC_AVAILABLE)} +if {$sdsoc_available} { + set x_dir "" + set x_vers "" + catch {set x_dir $::env(XILDIR)} + catch {set x_vers $::env(VIVADO_VERSION)} + puts "INFO:(TE) Source Xilinx SDSoC Scripts (${x_dir}/SDx/${x_vers}/scripts/vivado/sdsoc_pfm.tcl)." + source -notrace ${x_dir}/SDx/${x_vers}/scripts/vivado/sdsoc_pfm.tcl +} +puts "-----------------------------------------------------------------------" + +namespace eval TE { + namespace eval INIT { + variable my_script $argv0 + # + + proc return_option {option} { + global argc + global argv + + if { $argc <= [expr $option + 1]} { + puts "ERROR:(TE) Read Parameter failed" + show_help + } else { + puts "INFO:(TE) Parameter Option Value: [lindex $argv [expr $option + 1]]" + return [lindex $argv [expr $option + 1]] + } + } + + proc show_help_batchfile_commands {} { + variable my_script + puts "--TODO: Rework Info for main" + puts "INFO:(TE) Batch-File TCL-Script start options:" + puts "write: vivado -source ../scripts/script_main.tcl -mode batch -notrace -tclargs " + puts "Options:" + puts "Programming:" + puts "--TODO: explanation" + puts "Create/Run Vivado project:" + puts "--run : run option: \ + -1-no nothing is done \ + 0 -open existing project(default) \ + 1 -create selected boardpart project \ + 2 -run selected boardpart project \ + 3 -run all boardpart project" + puts "--boardpart : Trenz Board ID from TEXXXX_boardfiles.csv (you can use ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list)" + puts "--gui : gui mode option:\ + 0 -disable(default) \ + 1 -before project generation \ + 2 -after project generation" + puts "--clean : clean project option:\ + 0 -no(default) \ + 1 -vivado project \ + 2 -vivado and hsi workspace \ + 3 -all (vivado, hsi and sdk workspace )\ + 4 -all and prebuilt (vivado, hsi and sdk workspace and prebuilt)" + puts "--help : display this help and exit" + puts "" + puts "Example: vivado -source ../scripts/script_main.tcl -mode batch -notrace -tclargs --part xc7z020clg484-1 --boardpart trenz.biz:te0720-02-1cf:part0:1.0 --clean" + } + + proc main {} { + global argc + global argv + # + set use_teprocedure "NA" + set use_labtoolsonly false + set use_run_labtools false + set use_clear_all false + set use_run_prebuild_sdk false + set use_zynq_programming false + set use_mcs_programming false + set use_bit_programming false + set use_basefolder false + set use_programming_app "NA" + set use_vivadogui 0 + set use_run 0 + set use_clean 0 + set use_board "NA" + cd .. + + puts "-----------------------------------------------------------------------" + init_pathvar + # + puts "-----------------------------------------------------------------------" + # + if {$argc == 0} { + puts "" + puts "INFO:(TE) Default configuration will be used." + puts "" + } else { + for {set option 0} {$option < $argc} {incr option} { + puts "INFO:(TE) Parameter Index: $option" + puts "INFO:(TE) Parameter Option: [lindex $argv $option]" + switch [lindex $argv $option] { + "--clear_all" { set use_clear_all true } + "--run_te_procedure" { set use_teprocedure [return_option $option]; incr option } + "--run_prebuild_sdk" { set use_run_prebuild_sdk true } + "--run_labtools" { set use_run_labtools true } + "--program_bin" { set use_zynq_programming true } + "--program_mcs" { set use_mcs_programming true } + "--program_bit" { set use_bit_programming true } + "--program_swapp" { set use_programming_app [return_option $option]; incr option } + "--use_basefolder" { set use_basefolder [return_option $option]; incr option } + "--labtools" { set use_labtoolsonly true } + "--run" { set use_run [return_option $option]; incr option } + "--boardpart" { set use_board [return_option $option]; incr option } + "--gui" { set use_vivadogui [return_option $option]; incr option } + "--clean" { set use_clean [return_option $option]; incr option } + "--help" { show_help_batchfile_commands } + "" { } + default { puts "Warning:(TE) unrecognised option: [lindex $argv $option]"; show_help } + } + } + } + + set starttime [clock seconds] + puts "-----------------------------------------------------------------------" + if {$use_clear_all} { + if {[catch {clear_project_all } result]} { puts "ERROR:(TE) Script (TE::INIT::clear_project_all) failed: $result."; return -code error} + } elseif {$use_teprocedure ne "NA"} { + if {[catch {run_te_procedure $use_teprocedure $use_board} result]} { puts "ERROR:(TE) Script (TE::INIT::run_te_procedure) failed: $result."; return -code error} + } elseif {$use_run_labtools} { + if {[catch {run_labtools $use_board } result]} { puts "ERROR:(TE) Script (TE::INIT::run_labtools) failed: $result."; return -code error} + } elseif {$use_run_prebuild_sdk} { + if {[catch {run_sdk $use_board } result]} { puts "ERROR:(TE) Script (TE::INIT::run_sdk) failed: $result."; return -code error} + } elseif {$use_bit_programming} { + if {[catch {program_fpga_bit $use_basefolder $use_board $use_programming_app $use_labtoolsonly} result]} { puts "ERROR:(TE) Script (TE::INIT::program_fpga_bit) failed: $result."; return -code error} + } elseif {$use_mcs_programming} { + if {[catch {program_fpga_mcs $use_basefolder $use_board $use_programming_app $use_labtoolsonly} result]} { puts "ERROR:(TE) Script (TE::INIT::program_fpga_mcs) failed: $result."; return -code error} + } elseif {$use_zynq_programming} { + if {[catch {program_zynq_bin $use_basefolder $use_board $use_programming_app $use_labtoolsonly} result]} { puts "ERROR:(TE) Script (TE::INIT::program_zynq_bin) failed: $result."; return -code error} + } else { + if {[catch {run_project $use_board $use_run $use_vivadogui $use_clean} result]} { puts "ERROR:(TE) Script (TE::INIT::run_project) failed: $result."; return -code error} + } + puts "-----------------------------------------------------------------------" + set stoptime [clock seconds] + set timeelapsed [expr $stoptime -$starttime] + + set report_file ${TE::LOG_PATH}/time_elapsed.txt + set fp_w [open ${report_file} "w"] + puts $fp_w "Times elapsed..." + puts $fp_w "$timeelapsed seconds" + puts $fp_w "..." + close $fp_w + + #--------------------------------------------- + } + + + + if {[catch {main} result]} { + puts "ERROR:(TE) Script (TE::main) failed: $result." + } + } +} \ No newline at end of file diff --git a/zynqberrydemo1/scripts/script_sdsoc.tcl b/zynqberrydemo1/scripts/script_sdsoc.tcl new file mode 100644 index 0000000..4f4e2c2 --- /dev/null +++ b/zynqberrydemo1/scripts/script_sdsoc.tcl @@ -0,0 +1,367 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/04/11 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2016/10/06 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval SDSOC { + + #------------------------------------ + #--create_sdsoc_structure: ... + proc create_sdsoc_structure {} { + #clear old sdsoc + puts "Info:(TE) Delete old SDSOC Project Structure (${TE::SDSOC_PATH})." + TE::UTILS::clean_sdsoc + puts "Info:(TE) Create new SDSOC Project Structure(${TE::SDSOC_PATH})." + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + #-------------------- + #old 2015.4 + # if {[file exists ${TE::SET_PATH}/sdsoc/arm-xilinx-eabi]} { + # file copy -force ${TE::SET_PATH}/sdsoc/arm-xilinx-eabi ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + # } else { + # file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/arm-xilinx-eabi + # } + # if {[file exists ${TE::SET_PATH}/sdsoc/arm-xilinx-linux-gnueabi]} { + # file copy -force ${TE::SET_PATH}/sdsoc/arm-xilinx-linux-gnueabi ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + # } else { + # file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/arm-xilinx-linux-gnueabi + # } + #new 2016.2 + #different settings between 7Series and UltraScaleZynq + if {$TE::IS_ZSYS || $TE::IS_MSYS } { + if {[file exists ${TE::SET_PATH}/sdsoc/aarch32-none]} { + file copy -force ${TE::SET_PATH}/sdsoc/aarch32-none ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + #used for different memory versions + if {[file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld_${TE::SHORTDIR}]} { + if {[file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld]} { + file delete -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld + } + file copy -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld_${TE::SHORTDIR} ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld + } + } else { + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none + } + } elseif {$TE::IS_ZUSYS} { + if {[file exists ${TE::SET_PATH}/sdsoc/aarch64-none-elf]} { + file copy -force ${TE::SET_PATH}/sdsoc/aarch64-none-elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + #used for different memory versions + if {[file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld_${TE::SHORTDIR}]} { + if {[file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld]} { + file delete -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld + } + file copy -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld_${TE::SHORTDIR} ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld + } + } else { + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf + } + } + #-------------------- + if {[file exists ${TE::SET_PATH}/sdsoc/boot]} { + file copy -force ${TE::SET_PATH}/sdsoc/boot ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + set prebuit_pl_path ${TE::PREBUILT_OS_PATH}/petalinux/default/ + if {[file exists ${TE::PREBUILT_OS_PATH}/petalinux/${TE::SHORTDIR}]} { + set prebuit_pl_path ${TE::PREBUILT_OS_PATH}/petalinux/${TE::SHORTDIR} + } + if {$TE::IS_ZSYS || $TE::IS_MSYS } { + #search for petalinux generated fsbl.elf + set elf_list [] + if { [catch {set elf_list [ glob ${prebuit_pl_path}/*.elf ] }] } { + } else { + foreach elf $elf_list { + if {[string match *fsbl* $elf]} { + file copy -force $elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/zynq_fsbl.elf + } + } + } + #search for sdk generated fsbl.elf -> overwrite petalinux fsbl.elf if exist + set elf_list [] + if { [catch {set elf_list [ glob ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/*.elf ] }] } { + } else { + foreach elf $elf_list { + if {[string match *fsbl* $elf]} { + file copy -force $elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/zynq_fsbl.elf + } + } + } + #copy rest of prebuilt files + # if {[file exists ${prebuit_pl_path}/urootfs.cpio.gz]} { + # file copy -force ${prebuit_pl_path}/urootfs.cpio.gz ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/uramdisk.image.gz + # } + # if {[file exists ${prebuit_pl_path}/system.dtb]} { + # file copy -force ${prebuit_pl_path}/system.dtb ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/devicetree.dtb + # } + # if {[file exists ${prebuit_pl_path}/uImage]} { + # file copy -force ${prebuit_pl_path}/uImage ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + if {[file exists ${prebuit_pl_path}/image.ub]} { + file copy -force ${prebuit_pl_path}/image.ub ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + if {[file exists ${prebuit_pl_path}/u-boot.elf]} { + file copy -force ${prebuit_pl_path}/u-boot.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + } elseif {$TE::IS_ZUSYS} { + #search for petalinux generated fsbl.elf + set elf_list [] + if { [catch {set elf_list [ glob ${prebuit_pl_path}/*.elf ] }] } { + } else { + foreach elf $elf_list { + if {[string match *fsbl* $elf]} { + file copy -force $elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/fsbl.elf + } + } + } + #search for sdk generated fsbl.elf -> overwrite petalinux fsbl.elf if exist + set elf_list [] + if { [catch {set elf_list [ glob ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/*.elf ] }] } { + } else { + foreach elf $elf_list { + if {[string match *fsbl* $elf]} { + file copy -force $elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/fsbl.elf + } + } + } + # #copy rest of prebuilt files + # if {[file exists ${prebuit_pl_path}/urootfs.cpio.gz]} { + # file copy -force ${prebuit_pl_path}/urootfs.cpio.gz ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/uramdisk.tar.gz + # } + # if {[file exists ${prebuit_pl_path}/system.dtb]} { + # file copy -force ${prebuit_pl_path}/system.dtb ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + # if {[file exists ${prebuit_pl_path}/uImage]} { + # file copy -force ${prebuit_pl_path}/uImage ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + # if {[file exists ${prebuit_pl_path}/bl31.elf]} { + # file copy -force ${prebuit_pl_path}/bl31.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + # if {[file exists ${prebuit_pl_path}/u-boot.elf]} { + # file copy -force ${prebuit_pl_path}/u-boot.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + #copy rest of prebuilt files + if {[file exists ${prebuit_pl_path}/image.ub]} { + file copy -force ${prebuit_pl_path}/image.ub ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + if {[file exists ${prebuit_pl_path}/bl31.elf]} { + file copy -force ${prebuit_pl_path}/bl31.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + if {[file exists ${prebuit_pl_path}/u-boot.elf]} { + file copy -force ${prebuit_pl_path}/u-boot.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + } + } else { + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot + } + #-------------------- + if {[file exists ${TE::SET_PATH}/sdsoc/samples]} { + file copy -force ${TE::SET_PATH}/sdsoc/samples ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + } else { + # file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/samples + } + #-------------------- + if {[file exists ${TE::SET_PATH}/sdsoc/hardware]} { + file copy -force ${TE::SET_PATH}/sdsoc/hardware ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit]} { + file copy -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/hardware/prebuilt/bitstream.bit + } + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf]} { + file copy -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/hardware/prebuilt/export/${TE::PR_TOPLEVELNAME}.hdf + } + } else { + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/hardware + } + } + #------------------------------------ + #--check_vivado_project: ... + proc check_and_modify_vivado_project {check_only} { + if {$check_only} { + puts "---------------------" + puts "Info:(TE) Run SDSOC check:" + puts " Notes:" + puts " -Errors: could not fixed automaticly" + puts " -Warnings: can be fixed automaticly or can be ignored." + puts " Run:" + } else { puts "Info:(TE) Run SDSOC check (modify project):"} + #------------------ + #check sdsoc environment : + # + if {!$TE::SDSOC_AVAILABLE } { + set txt "Error:(TE) SDSOC environment not set." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) SDSOC environment check passed";} + #------------------ + #check zip program : + # + if {![file exists $TE::ZIP_PATH]} { + set txt "Error:(TE) SDSOC ZIP program not found ($TE::ZIP_PATH)." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) SDSOC ZIP program check passed";} + #------------------ + #check pfm settings : + #file to generate hw.pfm + if {![file exists ${TE::SET_PATH}/sdsoc/sdsoc_pfm.tcl]} { + set txt "Error:(TE) Project specific TCL-File for HW_PFM-generation not found (${TE::SET_PATH}/sdsoc_pfm.tcl)." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) HW PFM check passed";} + #------------------ + #check pfm settings : + #file to generate sw.pfm (currently is only a copy) + if {![file exists ${TE::SET_PATH}/sdsoc/sdsoc_sw.pfm]} { + set txt "Error:(TE) Project specific File for SW_PFM-generation not found (${TE::SET_PATH}/sdsoc_sw.pfm)." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) SW PFM check passed";} + #------------------ + #check project name: + #must be platform_name (${TE::VPROJ_NAME}) + if {![file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.xpr]} { + set txt "Error:(TE) Vivado project name is not SDSOC compatible, should be: ${TE::VPROJ_NAME}.xpr" + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Vivado project name check passed";} + #------------------ + #check toplevel name: + #should be _wrapper + set toplevel [get_property top [current_fileset]] + if {![string match *_wrapper $toplevel]} { + set txt "Error:(TE) Top level is not SDSOC compatible, should be: *_wrapper" + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Top Level Name check passed";} + # if {![string match ${TE::VPROJ_NAME}* $toplevel]} { + # set txt "Warning:(TE) Current top level should be: ${TE::VPROJ_NAME}*" + # if {!$check_only} { + # # currently nothing must be done + # # return -code error $txt + # } else {puts " $txt";} + # } + #------------------ + #check processor system: + #must be processor system + if {!$TE::IS_ZSYS && !$TE::IS_ZUSYS && !$TE::IS_MSYS } { + set txt "Error:(TE) Block Design contains no processor system (Checked with TE::INIT::check_bdtyp)." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Processor check passed";} + #------------------ + #check project language: + #must be verilog + if {[get_property target_language [current_project]] ne "Verilog"} { + set txt "Warning:(TE) Vivado isn't a Verilog Project." + if {!$check_only} { + #change language + set_property target_language Verilog [current_project] + puts "Info:(TE) Target Language check passed (Project Modify:Set target Language to Verilog)" + # return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Target Language check passed";} + #------------------ + #check bd files: + #currently only one bdfile supported (TE) + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + set txt "Error:(TE) No Block Design found. Should be only one!" + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } elseif {[llength $bd_files]>1 } { + set txt "Error:(TE) More than one Block Design found. Should be only one!" + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) BD-Design count check passed";} + #------------------ + #check top level file language: + #must be verilog + set bd $bd_files + # open_bd_design $bd -quiet + # set bd_name [get_bd_designs] + set bd_name [open_bd_design $bd -quiet] + if {![file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.v]} { + set txt "Warning:(TE) Toplevel file should be Verilog." + if {!$check_only} { + #remove old vhdl toplevel + remove_files ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.vhd + file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.vhd + #make verilog top + make_wrapper -files [get_files $bd] -top + add_files -norecurse ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.v + update_compile_order -fileset ${TE::SOURCE_NAME} + update_compile_order -fileset ${TE::SIM_NAME} + puts "Info:(TE) Top Level check passed (Project Modify: Regenerate Toplevel as Verilog file)" + # return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Top Level check passed";} + close_bd_design [get_bd_designs $bd] + #------------------ + #check board part : + #board part not allowed + if {[get_property board_part [current_project]] ne ""} { + set txt "Warning:(TE) Board Part usage is not allowed for SDSOC." + if {!$check_only} { + TE::ADV::beta_hw_remove_board_part + puts "Info:(TE) Board Part check passed (Project Modify: Remove Board Part properties)" + # return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Board Part check passed";} + #------------------ + puts "---------------------" + } + + #------------------------------------ + #--export_vivado_project: ... + proc export_vivado_sdsoc_project {} { + puts "Info:(TE) Create SDSOC Vivado Project on: ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/vivado" + if { [file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/vivado] } { + file delete -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/vivado + } + archive_project ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/${TE::VPROJ_NAME}.xpr.zip -temp_dir ${TE::VPROJ_PATH}/.Xil/Vivado-xxxx- -force -include_config_settings + TE::EXT::unzip_project ${TE::VPROJ_NAME}.xpr.zip ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + file rename -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/${TE::VPROJ_NAME} ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/vivado + file delete -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/${TE::VPROJ_NAME}.xpr.zip + } + #------------------------------------ + #--create_sdsoc_pfm: ... + proc create_sdsoc_pfm {} { + puts "Info:(TE) Create SDSOC Vivado Project pfm: ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/" + #open bd design + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + puts "Warning:(TE) No BD-File found." + } + foreach bd $bd_files { + open_bd_design $bd + } + #generate hw pfm + puts "Info:(TE) Generate ${TE::VPROJ_NAME}_hw.pfm" + source -notrace ${TE::SET_PATH}/sdsoc/sdsoc_pfm.tcl + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}_hw.pfm ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + #generate sw pfm (todo generate content from existing files) + puts "Info:(TE) Generate ${TE::VPROJ_NAME}_sw.pfm" + file copy -force ${TE::SET_PATH}/sdsoc/sdsoc_sw.pfm ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/${TE::VPROJ_NAME}_sw.pfm + } + # # ------------------------------------------------------- + } + + puts "Info:(TE) Load SDSOC script finished" +} + + diff --git a/zynqberrydemo1/scripts/script_settings.tcl b/zynqberrydemo1/scripts/script_settings.tcl new file mode 100644 index 0000000..be6c429 --- /dev/null +++ b/zynqberrydemo1/scripts/script_settings.tcl @@ -0,0 +1,874 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/02 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/06/28 $ +# -------------------------------------------------------------------- +# -- 2017/06/13 new release version +# -- 2017/06/28 new board part csv version +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval ::TE { + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # TE variable declaration + # ----------------------------------------------------------------------------------------------------------------------------------------- + # overwrite Setting: + # create TCL file: /settings/development_settings.tcl + # overwrite example: + # set TE:: + # set TE::GEN_HW_BIT false + # ----------------------------------- + # Unsupported Settings: + # --------------------- + # Currently only one BD is allowed + # Multi BD Design is official not supported (maybe not all functions run correctly): + # For Multi BD Design do following: + # 1. set variable BD_MULTI to true + # 2. Make own Top-level File (Name: _top) in the folder "/hdl/" with file name: "_top.vhd" or "_top.v" + variable BD_MULTI false + # + variable DESIGNRUNS [list] + # ----------------------------------- + # Build Settings: + # Attention: there are dependencies between this properties! + # --------------------- + variable GEN_HW_DELETEOLDFILES true + variable GEN_HW_BIT true + variable GEN_HW_MCS true + variable GEN_HW_RPT true + variable GEN_HW_HDF true + variable GEN_SW_HSI true + variable GEN_SW_BIF true + variable GEN_SW_BIN true + variable GEN_SW_BITMCS true + variable GEN_SW_USEPREBULTHDF false + variable GEN_SW_FORCEBOOTGEN false + # ----------------------------------- + # Basic Settings: + # Attention: do not change following variables manually! + # --------------------- + # project path + variable BASEFOLDER + variable VPROJ_NAME + variable VPROJ_PATH + variable VLABPROJ_PATH + variable BOARDDEF_PATH + variable FIRMWARE_PATH + variable IP_PATH + variable BD_PATH + variable XDC_PATH + variable HDL_PATH + variable SET_PATH + variable WORKSPACE_PATH + variable WORKSPACE_HSI_PATH + variable WORKSPACE_SDK_PATH + variable LIB_PATH + variable PREBUILT_PATH + variable PREBUILT_HW_PATH + variable PREBUILT_SW_PATH + variable PREBUILT_BI_PATH + variable PREBUILT_OS_PATH + variable SCRIPT_PATH + variable DOC_PATH + variable LOG_PATH + variable BACKUP_PATH + variable ZIP_PATH + variable SDSOC_PATH + # ----------------------------------- + variable ZIP_IGNORE_LIST [list] + # ----------------------------------- + variable BATCH_FILE_NAME + variable VIVADO_AVAILABLE + variable LABTOOL_AVAILABLE + variable SDK_AVAILABLE + variable SDSOC_AVAILABLE + # ----------------------------------- + variable XILINXGIT_DEVICETREE + variable XILINXGIT_UBOOT + variable XILINXGIT_LINUX + # ----------------------------------- + # board_files + variable ID "NA" + variable PRODID "NA" + variable BOARDPART "NA" + variable PARTNAME "NA" + variable SHORTDIR "NA" + variable ZYNQFLASHTYP "NA" + variable FPGAFLASHTYP "NA" + variable CFGMEM_IF "NA" + variable CFGMEM_MEMSIZE_MB "NA" + # ----------------------------------- + #project run (use default name) + #for renaming use prefix sim*, syn*, imp* and con*! + variable TIMEOUT 120 + variable RUNNING_JOBS 4 + #todo: multiple runs and strategies and modified strategies + variable SIM_NAME sim_1 + variable SYNTH_NAME synth_1 + variable IMPL_NAME impl_1 + variable CONST_NAME constrs_1 + variable SOURCE_NAME sources_1 + # ----------------------------------- + # check csv file ids + variable SCRIPTVER "2017.1.03" + variable BOARDDEF_CSV "1.3" + variable SW_IP_CSV "2.0" + variable BDMOD_CSV "1.1" + variable ZIP_CSV "1.0" + # ----------------------------------- + variable SW_APPLIST [list] + #BOARD_DEFINITION currently in BDEF todo set to init in settings + variable BD_MOD_COMMENT [list] + variable BD_MOD_ADD [list] + variable BD_MOD_PCOMMENT [list] + variable BD_MOD_PADD [list] + variable BD_TCLNAME "NA" + variable PR_TOPLEVELNAME "NA" + variable IS_ZSYS false + variable IS_ZUSYS false + variable IS_MSYS false + variable IS_FSYS false + # ----------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished TE variables declaration + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + namespace eval INIT { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--import_usr_tcl: + proc init_usr_tcl {} { + # hidden function: official not supported + set usr_script [] + if { ![catch {set usr_script [glob -join -dir ${TE::SET_PATH}/usr/ *.tcl]}] } { + TE::UTILS::te_msg TE_INIT-58 INFO "Load additional user TCL-script:\n ${usr_script}" + uplevel 1 [ list ::source ${usr_script}] + } + } + #-------------------------------- + #--print_version: + proc print_version {} { + set viv_version "NA" + if {[catch {set viv_version [lindex [split [::version] "\n"] 0]}]} { set viv_version "NA" } + set TE::BATCH_FILE_NAME "NA" + if {[catch {set TE::BATCH_FILE_NAME $::env(batchfile_name)}]} { set TE::BATCH_FILE_NAME "NA" } + + TE::UTILS::te_msg TE_INIT-0 INFO "Script Info:\n \ + Vivado Version: $viv_version\n \ + TE Script Version: $TE::SCRIPTVER\n \ + Board Part (Definition Files) CSV Version: $TE::BOARDDEF_CSV\n \ + Software IP CSV Version: $TE::SW_IP_CSV\n \ + Board Design Modify CSV Version: $TE::BDMOD_CSV\n \ + ZIP ignore CSV Version: $TE::ZIP_CSV\n \ + ---\n \ + Start project with: $TE::BATCH_FILE_NAME\n \ + ------" + } + #-------------------------------- + #--print_environment_settings: + proc print_environment_settings {} { + set TE::VIVADO_AVAILABLE 0 + set TE::LABTOOL_AVAILABLE 0 + set TE::SDK_AVAILABLE 0 + set TE::SDSOC_AVAILABLE 0 + [catch {set TE::VIVADO_AVAILABLE $::env(VIVADO_AVAILABLE)}] + [catch {set TE::LABTOOL_AVAILABLE $::env(LABTOOL_AVAILABLE)}] + [catch {set TE::SDK_AVAILABLE $::env(SDK_AVAILABLE)}] + [catch {set TE::SDSOC_AVAILABLE $::env(SDSOC_AVAILABLE)}] + TE::UTILS::te_msg TE_INIT-1 INFO "Script Environment:\n \ + Vivado Setting: $TE::VIVADO_AVAILABLE \n \ + LabTools Setting: $TE::LABTOOL_AVAILABLE \n \ + SDK Setting: $TE::SDK_AVAILABLE \n \ + SDSOC Setting: $TE::SDSOC_AVAILABLE \n \ + ------" + + if {$TE::SDK_AVAILABLE==1 && $TE::SDSOC_AVAILABLE==1} { + TE::UTILS::te_msg TE_INIT-2 WARNING "SDK settings are overwritten by SDSOC settings." + } + } + #-------------------------------- + #--init_pathvar: + proc init_pathvar {} { + set tmppath [pwd] + if {[file tail [pwd]]=="vivado"} { + cd .. + } + set TE::BASEFOLDER [pwd] + set TE::VPROJ_NAME [file tail [pwd]] + set TE::VPROJ_PATH [pwd]/vivado + set TE::VLABPROJ_PATH [pwd]/vivado_lab + #-- + set TE::BOARDDEF_PATH [pwd]/board_files + set TE::FIRMWARE_PATH [pwd]/firmware + #-- + set TE::IP_PATH [pwd]/ip_lib + set TE::BD_PATH [pwd]/block_design + set TE::XDC_PATH [pwd]/constraints + set TE::HDL_PATH [pwd]/hdl + set TE::SET_PATH [pwd]/settings + #-- + set TE::WORKSPACE_PATH [pwd]/workspace + set TE::WORKSPACE_HSI_PATH ${TE::WORKSPACE_PATH}/hsi + set TE::WORKSPACE_SDK_PATH ${TE::WORKSPACE_PATH}/sdk + #-- + set TE::LIB_PATH [pwd]/sw_lib + set TE::SCRIPT_PATH [pwd]/scripts + set TE::DOC_PATH [pwd]/doc + #-- + set TE::PREBUILT_PATH [pwd]/prebuilt + set TE::PREBUILT_BI_PATH ${TE::PREBUILT_PATH}/boot_images + set TE::PREBUILT_HW_PATH ${TE::PREBUILT_PATH}/hardware + set TE::PREBUILT_SW_PATH ${TE::PREBUILT_PATH}/software + set TE::PREBUILT_OS_PATH ${TE::PREBUILT_PATH}/os + #-- + set TE::LOG_PATH [pwd]/v_log + set TE::BACKUP_PATH [pwd]/backup + #-- + set TE::ZIP_PATH "" + [catch {set TE::ZIP_PATH $::env(ZIP_PATH)}] + #-- + set TE::SDSOC_PATH [pwd]/sdsoc + set TE::XILINXGIT_DEVICETREE "" + [catch {set TE::XILINXGIT_DEVICETREE $::env(XILINXGIT_DEVICETREE)}] + set TE::XILINXGIT_UBOOT "" + [catch {set TE::XILINXGIT_UBOOT $::env(XILINXGIT_UBOOT)}] + set TE::XILINXGIT_LINUX "" + [catch {set TE::XILINXGIT_LINUX $::env(XILINXGIT_LINUX)}] + #-- + TE::UTILS::te_msg TE_INIT-3 INFO "Initial project names and paths:\n \ + TE::VPROJ_NAME: $TE::VPROJ_NAME \n \ + TE::VPROJ_PATH: $TE::VPROJ_PATH \n \ + TE::VLABPROJ_PATH: $TE::VLABPROJ_PATH \n \ + TE::BOARDDEF_PATH: $TE::BOARDDEF_PATH \n \ + TE::FIRMWARE_PATH: $TE::FIRMWARE_PATH \n \ + TE::IP_PATH: $TE::IP_PATH \n \ + TE::BD_PATH: $TE::BD_PATH \n \ + TE::XDC_PATH: $TE::XDC_PATH \n \ + TE::HDL_PATH: $TE::HDL_PATH \n \ + TE::SET_PATH: $TE::SET_PATH \n \ + TE::WORKSPACE_HSI_PATH: $TE::WORKSPACE_HSI_PATH \n \ + TE::WORKSPACE_SDK_PATH: $TE::WORKSPACE_SDK_PATH \n \ + TE::LIB_PATH: $TE::LIB_PATH \n \ + TE::SCRIPT_PATH: $TE::SCRIPT_PATH \n \ + TE::DOC_PATH: $TE::DOC_PATH \n \ + TE::PREBUILT_BI_PATH: $TE::PREBUILT_BI_PATH \n \ + TE::PREBUILT_HW_PATH: $TE::PREBUILT_HW_PATH \n \ + TE::PREBUILT_SW_PATH: $TE::PREBUILT_SW_PATH \n \ + TE::PREBUILT_OS_PATH: $TE::PREBUILT_OS_PATH \n \ + TE::LOG_PATH: $TE::LOG_PATH \n \ + TE::BACKUP_PATH: $TE::BACKUP_PATH \n \ + TE::ZIP_PATH: $TE::ZIP_PATH \n \ + TE::SDSOC_PATH: $TE::SDSOC_PATH \n \ + TE::XILINXGIT_DEVICETREE: $TE::XILINXGIT_DEVICETREE \n \ + TE::XILINXGIT_UBOOT: $TE::XILINXGIT_UBOOT \n \ + TE::XILINXGIT_LINUX: $TE::XILINXGIT_LINUX \n \ + ------" + + cd $tmppath + } + #-------------------------------- + #--init_board: + proc init_board {ID POS} { + TE::BDEF::get_check_unique_name $ID $POS + + set TE::ID [TE::BDEF::get_id $ID $POS] + set TE::PRODID [TE::BDEF::get_prodid $ID $POS] + set TE::BOARDPART [TE::BDEF::get_boardname $ID $POS] + set TE::PARTNAME [TE::BDEF::get_partname $ID $POS] + set TE::SHORTDIR [TE::BDEF::get_shortname $ID $POS] + set TE::ZYNQFLASHTYP [TE::BDEF::get_zynqflashtyp $ID $POS] + set tmp [TE::BDEF::get_fpgaflashtyp $ID $POS] + #todo extrakt CFGMEM_IF and CFGMEM_MEMSIZE_MB from FPGAFLASHTYP-name and from bitfile configuration + set tmp [split $tmp "|"] + if {[llength $tmp] eq 3} { + set TE::FPGAFLASHTYP [lindex $tmp 0] + set TE::CFGMEM_IF [lindex $tmp 1] + set TE::CFGMEM_MEMSIZE_MB [lindex $tmp 2] + } else { + set TE::FPGAFLASHTYP $tmp + set TE::CFGMEM_IF "NA" + set TE::CFGMEM_MEMSIZE_MB "NA" + } + TE::UTILS::te_msg TE_INIT-4 INFO "Board Part definition:\n \ + TE::ID: $TE::ID \n \ + TE::PRODID: $TE::PRODID \n \ + TE::PARTNAME: $TE::PARTNAME \n \ + TE::BOARDPART: $TE::BOARDPART \n \ + TE::SHORTDIR: $TE::SHORTDIR \n \ + TE::ZYNQFLASHTYP: $TE::ZYNQFLASHTYP \n \ + TE::FPGAFLASHTYP: $TE::FPGAFLASHTYP \n \ + ------" + } + #-------------------------------- + #--init_part_only: init fpga part if found in csv (used if board part is not defined on open project) + proc init_part_only {partname} { + #--check if fpga part is unique + #-2 not found + #-1 some same + #0 unique + #1 all same + set pcheck [TE::BDEF::get_check_unique_name $partname 2] + if {$pcheck == 0 } { + set TE::ID [TE::BDEF::get_id $partname 2] + set TE::PRODID "NA" + set TE::BOARDPART "NA" + set TE::PARTNAME [TE::BDEF::get_partname $partname 2] + set TE::SHORTDIR [TE::BDEF::get_shortname $partname 2] + set TE::ZYNQFLASHTYP [TE::BDEF::get_zynqflashtyp $partname 2] + set tmp [TE::BDEF::get_fpgaflashtyp $partname 2] + #todo extrakt CFGMEM_IF and CFGMEM_MEMSIZE_MB from FPGAFLASHTYP-name and from bitfile configuration + set tmp [split $tmp "|"] + if {[llength $tmp] eq 3} { + set TE::FPGAFLASHTYP [lindex $tmp 0] + set TE::CFGMEM_IF [lindex $tmp 1] + set TE::CFGMEM_MEMSIZE_MB [lindex $tmp 2] + } else { + set TE::FPGAFLASHTYP $tmp + set TE::CFGMEM_IF "NA" + set TE::CFGMEM_MEMSIZE_MB "NA" + } + + TE::UTILS::te_msg TE_INIT-5 WARNING "Board Part definition initialisation with unique part name:\n \ + TE::ID: $TE::ID \n \ + TE::PRODID: $TE::PRODID \n \ + TE::PARTNAME: $TE::PARTNAME \n \ + TE::BOARDPART: $TE::BOARDPART \n \ + TE::SHORTDIR: $TE::SHORTDIR \n \ + TE::ZYNQFLASHTYP: $TE::ZYNQFLASHTYP \n \ + TE::FPGAFLASHTYP: $TE::FPGAFLASHTYP \n \ + ------" + } elseif {$pcheck == 1 } { + #todo check if flash is the same on all definitions + set TE::ID "NA" + set TE::PRODID "NA" + set TE::BOARDPART "NA" + set TE::PARTNAME [TE::BDEF::get_partname $partname 2] + #short name is fpga name + set TE::SHORTDIR [TE::BDEF::get_shortname $partname 2] + set TE::ZYNQFLASHTYP "NA" + set TE::FPGAFLASHTYP "NA" + set TE::CFGMEM_IF "NA" + set TE::CFGMEM_MEMSIZE_MB "NA" + TE::UTILS::te_msg TE_INIT-6 WARNING "Board Part definition initialisation with same part name:\n \ + TE::ID: $TE::ID \n \ + TE::PRODID: $TE::PRODID \n \ + TE::PARTNAME: $TE::PARTNAME \n \ + TE::BOARDPART: $TE::BOARDPART \n \ + TE::SHORTDIR: $TE::SHORTDIR \n \ + TE::ZYNQFLASHTYP: $TE::ZYNQFLASHTYP \n \ + TE::FPGAFLASHTYP: $TE::FPGAFLASHTYP \n \ + ------" + } else { + set TE::ID "NA" + set TE::PRODID "NA" + set TE::BOARDPART "NA" + set TE::PARTNAME $partname + set TE::SHORTDIR $partname + set TE::ZYNQFLASHTYP "NA" + set TE::FPGAFLASHTYP "NA" + set TE::CFGMEM_IF "NA" + set TE::CFGMEM_MEMSIZE_MB "NA" + puts "Warning:(TE) Part name not found, use requested name:" + TE::UTILS::te_msg TE_INIT-7 {CRITICAL WARNING} "Board Part definition initialisation with unknown part name:\n \ + TE::ID: $TE::ID \n \ + TE::PRODID: $TE::PRODID \n \ + TE::PARTNAME: $TE::PARTNAME \n \ + TE::BOARDPART: $TE::BOARDPART \n \ + TE::SHORTDIR: $TE::SHORTDIR \n \ + TE::ZYNQFLASHTYP: $TE::ZYNQFLASHTYP \n \ + TE::FPGAFLASHTYP: $TE::FPGAFLASHTYP \n \ + ------" + } + + } + #-------------------------------- + #--check_bdtyp: check BD typ + proc check_bdtyp {} { + set bd_files [] + set TE::BD_TCLNAME "NA" + set TE::PR_TOPLEVELNAME "NA" + set TE::IS_ZSYS false + set TE::IS_ZUSYS false + set TE::IS_MSYS false + set TE::IS_FSYS false + #get bd_filelist + set bd_files [TE::UTILS::search_bd_files] + foreach bd $bd_files { + set TE::BD_TCLNAME [file tail [file rootname $bd]] + set TE::PR_TOPLEVELNAME "[string trim $TE::BD_TCLNAME "_bd"]_wrapper" + TE::UTILS::te_msg TE_INIT-8 INFO "Found BD-Design:\n \ + TE::BD_TCLNAME: $TE::BD_TCLNAME \n \ + TE::PR_TOPLEVELNAME: $TE::PR_TOPLEVELNAME \n \ + ------" + #check typ for other functions + if {[string match *zsys* $TE::BD_TCLNAME ]} {set TE::IS_ZSYS true; TE::UTILS::te_msg TE_INIT-9 STATUS " TE::IS_ZSYS: $TE::IS_ZSYS" + } elseif {[string match *zusys* $TE::BD_TCLNAME ]} {set TE::IS_ZUSYS true; TE::UTILS::te_msg TE_INIT-10 STATUS " TE::IS_ZUSYS: $TE::IS_ZUSYS" + } elseif {[string match *msys* $TE::BD_TCLNAME ]} {set TE::IS_MSYS true; TE::UTILS::te_msg TE_INIT-11 STATUS " TE::IS_MSYS: $TE::IS_MSYS" + } elseif {[string match *fsys* $TE::BD_TCLNAME ]} {set TE::IS_FSYS true; TE::UTILS::te_msg TE_INIT-12 STATUS " TE::IS_FSYS: $TE::IS_FSYS" + } else { + TE::UTILS::te_msg TE_INIT-13 WARNING "Not all TE-functions support unknown BD Filename. Use: \n \ + \"*zsys*.tcl\" for Systems with Zynq \n \ + \"*zusys*.tcl\" for Systems with UltraScale Zynq \n \ + \"*msys*.tcl\" for Systems with MicroBlaze \n \ + \"*fsys*.tcl\" for Systems with FPGA-Fabric design only \n \ + ------" + } + } + } + #-------------------------------- + #--init_boardlist: + proc init_boardlist {} { + set board_files "" + set TE::BDEF::BOARD_DEFINITION [list] + if { [catch {set board_files [ glob $TE::BOARDDEF_PATH/*board_files_mod.csv ] }] } { + if { [catch {set board_files [ glob $TE::BOARDDEF_PATH/*board_files.csv ] }] } { + TE::UTILS::te_msg TE_INIT-14 WARNING "No board part definition list found (Path: ${TE::BOARDDEF_PATH})." + } + } else { + TE::UTILS::te_msg TE_INIT-15 WARNING "Modified board part definition list found (File: ${board_files})." + } + if {$board_files ne ""} { + TE::UTILS::te_msg TE_INIT-16 INFO "Read board part definition list (File ${board_files})." + set fp [open "${board_files}" r] + set file_data [read $fp] + close $fp + # set TE::BDEF::BOARD_DEFINITION [list] + set data [split $file_data "\n"] + foreach line $data { + # check file version ignore comments and empty lines + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + set tmp [split $line "="] + if {[string match [lindex $tmp 1] $TE::BOARDDEF_CSV] != 1} { + TE::UTILS::te_msg TE_INIT-17 ERROR "Wrong board part definition CSV version (${TE::BOARDDEF_PATH}/board_files.csv) get [lindex $tmp 1] expected ${TE::BOARDDEF_CSV}." + return -code error "Wrong board part definition CSV version (${TE::BOARDDEF_PATH}/board_files.csv) get [lindex $tmp 1] expected ${TE::BOARDDEF_CSV}." + } + } elseif {[string match *#* $line] != 1 && [string length $line] > 0} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #splitt and append + set tmp [split $line ","] + lappend TE::BDEF::BOARD_DEFINITION $tmp + } + } + } + } + #-------------------------------- + #--init_app_list: + proc init_app_list {} { + set TE::SW_APPLIST [list] + if {[file exists ${TE::LIB_PATH}/apps_list.csv]} { + TE::UTILS::te_msg TE_INIT-18 INFO "Read Software list (File: ${TE::LIB_PATH}/apps_list.csv)." + set fp [open "${TE::LIB_PATH}/apps_list.csv" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + # set fsbl_name "" + foreach line $data { + # check file version ignore comments and empty lines + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #check version + set tmp [split $line "="] + if {[string match [lindex $tmp 1] $TE::SW_IP_CSV] != 1} { + TE::UTILS::te_msg TE_INIT-19 ERROR "Wrong Software Definition CSV Version (${TE::LIB_PATH}/apps_list.csv) get [lindex $tmp 1] expected ${TE::SW_IP_CSV}." + return -code error "Wrong Software Definition CSV Version (${TE::LIB_PATH}/apps_list.csv) get [lindex $tmp 1] expected $TE::SW_IP_CSV" + } + } elseif {[string match *#* $line] != 1 && [string length $line] > 0} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #splitt and append + set tmp [split $line ","] + lappend TE::SW_APPLIST $tmp + } + } + #------------------------------------------ + if {![file exists ${TE::XILINXGIT_DEVICETREE}]} { + set tmp_index -1 + foreach sw_applist_line ${TE::SW_APPLIST} { + incr tmp_index + #currently remove Device Tree from list (currently only additonal files) + if {[lindex $sw_applist_line 2] eq "DTS" } { + TE::UTILS::te_msg TE_INIT-20 {CRITICAL WARNING} "Xilinx Devicetree git clone path not found (Path: ${TE::XILINXGIT_DEVICETREE}). Device-Tree generation will be removed from apps_list.csv" + set TE::SW_APPLIST [lreplace $TE::SW_APPLIST $tmp_index $tmp_index] + } + } + } + #------------------------------------------ + } else { + TE::UTILS::te_msg TE_INIT-21 INFO "No software apps_list used." + } + } + #-------------------------------- + #--init_zip_ignore_list: + proc init_zip_ignore_list {} { + set TE::ZIP_IGNORE_LIST [list] + if {[file exists ${TE::SET_PATH}/zip_ignore_list.csv]} { + TE::UTILS::te_msg TE_INIT-22 INFO "Read ZIP ignore list (File: ${TE::LIB_PATH}/apps_list.csv)." + set fp [open "${TE::SET_PATH}/zip_ignore_list.csv" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + foreach line $data { + # check file version ignore comments and empty lines + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #check version + set tmp [split $line "="] + if {[string match [lindex $tmp 1] $TE::ZIP_CSV] != 1} { + TE::UTILS::te_msg TE_INIT-23 ERROR " Wrong Zip ignore definition CSV Version (${TE::SET_PATH}/zip_ignore_list.csv) get [lindex $tmp 1] expected ${TE::ZIP_CSV}." + return -code error "Wrong Zip ignore definition CSV Version (${TE::SET_PATH}/zip_ignore_list.csv) get [lindex $tmp 1] expected ${TE::ZIP_CSV}." + } + } elseif {[string match *#* $line] != 1 && [string length $line] > 0} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #splitt and append + set tmp [split $line ","] + lappend TE::ZIP_IGNORE_LIST $tmp + } + } + } else { + TE::UTILS::te_msg TE_INIT-24 INFO "No Zip ignore list used." + } + } + #-------------------------------- + #--init_mod_list: + proc init_mod_list {} { + set TE::BD_MOD_COMMENT [list] + set TE::BD_MOD_ADD [list] + set TE::BD_MOD_PCOMMENT [list] + set TE::BD_MOD_PADD [list] + if {[file exists ${TE::BD_PATH}/mod_bd.csv]} { + TE::UTILS::te_msg TE_INIT-25 INFO "Read BD modify list (File: ${TE::BD_PATH}/mod_bd.csv)." + set fp [open "${TE::BD_PATH}/mod_bd.csv" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + foreach line $data { + #ignore comments and empty lines + if {[string match *#* $line] != 1 && [string length $line] > 0} { + # check file version + if {[string match *CSV_VERSION* $line] } { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #check version + set tmp [split $line "="] + if {[string match [lindex $tmp 1] $TE::BDMOD_CSV] != 1} { + TE::UTILS::te_msg TE_INIT-26 ERROR " Wrong BD Modify CSV Version (${TE::BD_PATH}/mod_bd.csv) get [lindex $tmp 1] expected ${TE::BDMOD_CSV}." + return -code error " Wrong BD Modify CSV Version (${TE::BD_PATH}/mod_bd.csv) get [lindex $tmp 1] expected $TE::BDMOD_CSV" + } + } else { + #split line + set temp [split $line ","] + if {[llength $temp] <3} { + TE::UTILS::te_msg TE_INIT-27 WARNING "Not enough elements on line ($line). Line ignored." + } else { + #get line id +remove spaces and tabs + set line_id [string map {"\t" ""} [string map {" " ""} [lindex $temp 0]]] + #sort + if {$line_id eq "id"} { + #table header + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + set temp [split $line ","] + lappend TE::BD_MOD_COMMENT $temp + lappend TE::BD_MOD_ADD $temp + lappend TE::BD_MOD_PCOMMENT $temp + lappend TE::BD_MOD_PADD $temp + } elseif {$line_id==0} { + # ID 0: remove(comment) line + lappend TE::BD_MOD_COMMENT $temp + } elseif {$line_id==1} { + # ID 1: add line + if {[llength $temp] >3} { + # replaced removed comma from modify txt + set newinsert_list [list] + lappend newinsert_list [lindex $temp 0] + lappend newinsert_list [lindex $temp 1] + set addstring [lindex $temp 2] + for {set i 3} {$i < [llength $temp]} {incr i} { + set addstring "${addstring},[lindex $temp $i]" + } + lappend newinsert_list $addstring + set temp $newinsert_list + } + lappend TE::BD_MOD_ADD $temp + } elseif {$line_id==2} { + # ID 2: remove(comment) property + lappend TE::BD_MOD_PCOMMENT $temp + } elseif {$line_id==3} { + # ID 3: add property + lappend TE::BD_MOD_PADD $temp + } else { + #unsupported lines ignored + TE::UTILS::te_msg TE_INIT-28 WARNING "Unsupported id ($line_id). Line ignored." + } + } + } + } + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + + namespace eval BDEF { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # board part definition functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + variable BOARD_DEFINITION [list] + #{"ID" "PRODID" "PARTNAME" "BOARDNAME" "SHORTDIR"} + #extract board definition list from board definition file "board_files.csv" + #-------------------------------- + #--find_shortdir: + proc find_shortdir {NAME} { + variable BOARD_DEFINITION + #search in id + set value [get_shortname $NAME 0] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-29 STATUS "Found Shortname: $value";return $value} + #search in productid + set value [get_shortname $NAME 1] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-30 STATUS "Found Shortname: $value";return $value} + #search in boardname + set value [get_shortname $NAME 3] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-31 STATUS "Found Shortname: $value";return $value} + #search in shortname + set value [get_shortname $NAME 4] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-32 STATUS "Found Shortname: $value";return $value} + #search in part name (only if unique) + if {[get_check_unique_name $NAME 2]==0} { + set value [get_shortname $NAME 2] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-33 STATUS "Found Shortname: $value";return $value} + } + #default + TE::UTILS::te_msg TE_INIT-34 STATUS "No Shortname found for ${NAME}, use default " + return "default" + } + #-------------------------------- + #--find_id: + proc find_id {NAME} { + variable BOARD_DEFINITION + #search in id + set value [get_id $NAME 0] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-35 STATUS "Found ID: $value";return $value} + #search in productid + set value [get_id $NAME 1] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-36 STATUS "Found ID: $value";return $value} + #search in boardname + set value [get_id $NAME 3] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-37 STATUS "Found ID: $value";return $value} + #search in shortname + set value [get_id $NAME 4] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-38 STATUS "Found ID: $value";return $value} + #search in part name (only if unique) + if {[get_check_unique_name $NAME 2]==0} { + set value [get_id $NAME 2] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-39 STATUS "Found ID: $value";return $value} + } + #default + TE::UTILS::te_msg TE_INIT-40 STATUS "No ID found for ${NAME}, use NA " + return "NA" + } + #-------------------------------- + #--find_partname: + proc find_partname {NAME} { + variable BOARD_DEFINITION + #search in id + set value [get_partname $NAME 0] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-41 STATUS "Found part name: $value";return $value} + #search in productid + set value [get_partname $NAME 1] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-42 STATUS "Found part name: $value";return $value} + #search in boardname + set value [get_partname $NAME 3] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-43 STATUS "Found part name: $value";return $value} + #search in shortname + set value [get_partname $NAME 4] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-44 STATUS "Found part name: $value";return $value} + #search in part name (only if unique) + if {[get_check_unique_name $NAME 2]==0} { + set value [get_partname $NAME 2] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-45 STATUS "Found part name: $value";return $value} + } + #default + TE::UTILS::te_msg TE_INIT-46 STATUS "No part name found for ${NAME}, use NA " + return "NA" + } + #-------------------------------- + #--get_check_unique_name: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_check_unique_name {NAME POS} { + variable BOARD_DEFINITION + set part_count 0 + set max_count [expr [llength $BOARD_DEFINITION] -1] + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + set part_count [expr $part_count+1] + } + } + #-2 not found + #-1 some same + #0 unique + #1 all same + if {$part_count==0} { + TE::UTILS::te_msg TE_INIT-47 STATUS "Board part csv name check: $NAME not found on position $POS." + return -2 + } elseif {$part_count==$max_count} { + TE::UTILS::te_msg TE_INIT-48 STATUS "Board part csv name check: All names ($NAME) are equal on position $POS." + return 1 + } elseif {$part_count==1} { + TE::UTILS::te_msg TE_INIT-49 STATUS "Board part csv name check: $NAME is unique on position $POS." + return 0 + } else { + TE::UTILS::te_msg TE_INIT-50 STATUS "Board part csv name check: Only some names ($NAME) are equal on position $POS." + return -1 + } + } + #-------------------------------- + #--get_id: Name--> search name, POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_id {NAME POS} { + variable BOARD_DEFINITION + set last_id 0 + foreach sublist $BOARD_DEFINITION { + if {$last_id < [lindex $sublist 0] && [lindex $sublist 0] ne "ID"} { + set last_id [lindex $sublist 0] + } + # if { [string equal $NAME [lindex $sublist $POS]] } { + # return [lindex $sublist 0] + # } + if { [string match -nocase $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 0] + } + } + if {$NAME eq "LAST_ID"} { + #return the the highest id from the list + return $last_id + } + #default + TE::UTILS::te_msg TE_INIT-51 STATUS "ID not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_prodid: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_prodid {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 1] + } + } + #default + TE::UTILS::te_msg TE_INIT-52 STATUS "Product ID not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_partname: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_partname {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 2] + } + } + #default + TE::UTILS::te_msg TE_INIT-53 STATUS "Part Name not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_boardname: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_boardname {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 3] + } + } + #default + TE::UTILS::te_msg TE_INIT-54 STATUS "Board Name not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_shortname: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_shortname {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 4] + } + } + #default + TE::UTILS::te_msg TE_INIT-55 STATUS "Short Name not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_zynqflashtyp: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_zynqflashtyp {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 5] + } + } + #default + TE::UTILS::te_msg TE_INIT-56 STATUS "Zynq Flash typ not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_fpgaflashtyp: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_fpgaflashtyp {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 6] + } + } + #default + TE::UTILS::te_msg TE_INIT-57 STATUS "FPGA Flash typ not found for $NAME $POS, return default: NA" + return "NA" + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "INFO:(TE) Load Settings Script finished" +} \ No newline at end of file diff --git a/zynqberrydemo1/scripts/script_te_utils.tcl b/zynqberrydemo1/scripts/script_te_utils.tcl new file mode 100644 index 0000000..003af23 --- /dev/null +++ b/zynqberrydemo1/scripts/script_te_utils.tcl @@ -0,0 +1,766 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/04 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/05/18 $ +# -------------------------------------------------------------------- +# -- 2017/06/13 rise te_msg cnt +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval UTILS { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #-------------------------------- + #--te_msg: + proc te_msg {vmsg_id vmsg_sev vmsg_msg} { + # vmsg_id: TE_INIT, TE_UT, TE_EXT, TE_BD, TE_HW, TE_SW, TE_PR + #last vmsg_nr: + #TE_INIT 169 -> TE initialisation + #TE_UTIL 99 -> TE utilities + #TE_EXT 8 -> External + #TE_PS 1 -> PS modification 0,1-> external tcl-scripts with settings! + #TE_BD 26 -> Block Design + #TE_HW 81 -> HW Design + #TE_SW 66 -> SW Design + #TE_PR 84 -> Programming + # vmsg_sev: STATUS, INFO, WARNING, {CRITICAL WARNING}, ERROR + # set vmsg_id TE_DEF;set vmsg_sev STATUS;set vmsg_msg "Info"; + # common::send_msg_id "$vmsg_id" $vmsg_sev $vmsg_msg + if {[catch {common::send_msg_id "$vmsg_id" $vmsg_sev $vmsg_msg}] } {puts "${vmsg_sev}: ($vmsg_id) $vmsg_msg"} + #Info: Do not start Text with: -- + #TE::UTILS::te_msg TE_INIT-2 WARNING "SDK settings are overwritten by SDSOC settings." + #TE::UTILS::te_msg TE_INIT-0 INFO "Script Info: \n \ + # ------" + + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # search source files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--search_bd_files: search in TE::BD_PATH for *.tcl files return list + proc search_bd_files {} { + # search for block design for the board part only (folder with tcl must exist, otherwise base BD_Path is used!) + #currently only on bd.tcl is allowed + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::BD_PATH}/${TE::SHORTDIR} *.tcl]}] } { + if { [catch {set bd_files [glob -join -dir ${TE::BD_PATH}/ *.tcl]}] } { + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + TE::UTILS::te_msg TE_UTIL-0 WARNING "No Block-Design Export was found in ${TE::BD_PATH}, start vivado without bd-design" + } else { + TE::UTILS::te_msg TE_UTIL-1 WARNING "No Block-Design Export was found, use current Vivado project Block-Designs from:${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ ." + } + } + } + set bd_names "" + foreach bd $bd_files { + set bd_names "$bd_names $bd \n" + } + TE::UTILS::te_msg TE_UTIL-2 INFO "Following block designs were found: \n \ + $bd_names \ + ------" + if {!$TE::BD_MULTI} { + if {[llength $bd_files]>1 } { + TE::UTILS::te_msg TE_UTIL-3 WARNING "Currently only one Block-Design is supported with TE-scripts, deleted or rename file-extension from unused *.tcl in ${TE::BD_PATH} or ${TE::BD_PATH}/${TE::SHORTDIR}." + return -code error "Currently only one Block-Design is supported with TE-scripts, deleted or rename file-extension from unused *.tcl in ${TE::BD_PATH} or ${TE::BD_PATH}/${TE::SHORTDIR}." + } + } + return $bd_files + } + #-------------------------------- + #--search_xdc_files: search in TE::XDC_PATH for *xdc files return list + proc search_xdc_files {} { + # search for xdc file if bord part folder exist, this used too + set xdc_files [] + set base_xdc_files [] + set bp_xdc_files [] + if { [catch {set base_xdc_files [ glob $TE::XDC_PATH/*.xdc ] }] } { + TE::UTILS::te_msg TE_UTIL-4 WARNING "*.xdc search: ${TE::XDC_PATH}/ is empty." + } + if {[file exists ${TE::XDC_PATH}/${TE::SHORTDIR}/]} { + if { [catch {set bp_xdc_files [ glob $TE::XDC_PATH/${TE::SHORTDIR}/*.xdc ] }] } { + TE::UTILS::te_msg TE_UTIL-5 WARNING "*.xdc search: ${TE::XDC_PATH}/${TE::SHORTDIR}/ is empty." + } + #generate empty target xdc for gui constrains + if { ![file exists ${TE::XDC_PATH}/${TE::SHORTDIR}/vivado_target.xdc]} { + TE::UTILS::te_msg TE_UTIL-6 INFO "Generate ${TE::XDC_PATH}/${TE::SHORTDIR}/vivado_target.xdc" + close [ open ${TE::XDC_PATH}/${TE::SHORTDIR}/vivado_target.xdc w ] + lappend bp_xdc_files ${TE::XDC_PATH}/${TE::SHORTDIR}/vivado_target.xdc + } + set xdc_files [concat $base_xdc_files $bp_xdc_files] + } else { + set xdc_files $base_xdc_files + #generate empty target xdc for gui constrains + if { ![file exists ${TE::XDC_PATH}/vivado_target.xdc]} { + TE::UTILS::te_msg TE_UTIL-7 INFO "Generate ${TE::XDC_PATH}/vivado_target.xdc" + close [ open ${TE::XDC_PATH}/vivado_target.xdc w ] + lappend xdc_files ${TE::XDC_PATH}/vivado_target.xdc + } + } + + set xdc_names "" + foreach xdc $xdc_files { + set xdc_names "$xdc_names $xdc \n" + } + TE::UTILS::te_msg TE_UTIL-8 INFO "Following xdc files were found: \n \ + $xdc_names \ + ------" + + return $xdc_files + } + #-------------------------------- + #--search_xci_files: search in TE::HDL_PATH for *.xci files return list + proc search_xci_files {} { + set xci_files [list] + set xci_files_main [list] + set xci_files_sub [list] + catch {set xci_files_main [glob -join -dir $TE::HDL_PATH/xci/ *.xci]} + catch {set xci_files_sub [glob -join -dir $TE::HDL_PATH/xci/${TE::SHORTDIR}/ *.xci]} + set xci_files [concat $xci_files_main $xci_files_sub] + set xci_names "" + foreach xci_f $xci_files { + set xci_names "$xci_names $xci_f \n" + } + TE::UTILS::te_msg TE_UTIL-9 INFO "Following xci files were found: \n \ + $xci_names \ + ------" + + return $xci_files + } + #-------------------------------- + #--search_elf_files: search in TE::FIRMWARE_PATH for *.elf files return list + proc search_elf_files {} { + set elf_files_sub [list] + catch {set elf_files_sub [glob -join -dir ${TE::FIRMWARE_PATH} */*.elf]} + + set elf_names "" + foreach elf_f $elf_files_sub { + set elf_names "$elf_names $elf_f \n" + } + TE::UTILS::te_msg TE_UTIL-10 INFO "Following elf files were found: \n \ + $elf_names \ + ------" + + return $elf_files_sub + } + #-------------------------------- + #--search_hdl_files: search in TE::HDL_PATH for *.vhd and *.v files return list + proc search_hdl_files {} { + set hdl_files [list] + set vhd_files [list] + set vhd_files_sub1 [list] + set vhd_files_sub2 [list] + set v_files [list] + set v_files_sub1 [list] + set v_files_sub2 [list] + set sv_files [list] + set sv_files_sub1 [list] + set sv_files_sub2 [list] + catch {set vhd_files [glob -join -dir ${TE::HDL_PATH} *.vhd]} + catch {set vhd_files_sub1 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ *.vhd]} + catch {set vhd_files_sub2 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.vhd]} + catch {set v_files [glob -join -dir ${TE::HDL_PATH} *.v]} + catch {set v_files_sub1 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.v]} + catch {set v_files_sub2 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.v]} + catch {set sv_files [glob -join -dir ${TE::HDL_PATH} *.sv]} + catch {set sv_files_sub1 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.sv]} + catch {set sv_files_sub2 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.sv]} + set hdl_files [concat $vhd_files $vhd_files_sub1 $vhd_files_sub2 $v_files $v_files_sub1 $v_files_sub2 $sv_files $sv_files_sub1 $sv_files_sub2] + + set hdl_names "" + foreach hdl_f $hdl_files { + set hdl_names "$hdl_names $hdl_f \n" + } + TE::UTILS::te_msg TE_UTIL-11 INFO "Following hdl files were found: \n \ + $hdl_names \ + ------" + + return $hdl_files + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished search source files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # modify block design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--modify_block_design_tcl: + proc setinfo_to_block_design_tcl {datalist mod_file} { + TE::UTILS::te_msg TE_UTIL-22 INFO "Block Design tcl: info lines were added." + set data $datalist + if {$mod_file} { + # set data [linsert $data[set data {}] 0 "puts \"Info:(TE) This block design file has been modified. Modifications labelled with comment tag # #TE_MOD# on the Block-Design tcl-file.\""] + set data [linsert $data[set data {}] 0 "TE::UTILS::te_msg TE_BD-1 INFO \"This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag # #TE_MOD# on the Block-Design tcl-file.\""] + } + # set data [linsert $data[set data {}] 0 "puts \"Info:(TE) This block design file has been exported with Reference-Design Scripts from Trenz Electronic GmbH for Board Part:${TE::BOARDPART} with FPGA ${TE::PARTNAME} at [ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"].\""] + set data [linsert $data[set data {}] 0 "TE::UTILS::te_msg TE_BD-0 INFO \"This block design tcl-file was generate with Trenz Electronic GmbH Board Part:${TE::BOARDPART}, FPGA: ${TE::PARTNAME} at [ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"].\""] + return $data + } + #-------------------------------- + #--modify_block_design_tcl: load and save block design tcl (sub functions used for modifications) + proc modify_block_design_tcl {file_name mod_file} { + TE::UTILS::te_msg TE_UTIL-12 STATUS "Open bd design export [file tail [file rootname $file_name]]" + #read file to string list + set fp_r [open ${file_name} "r"] + set file_data [read $fp_r] + close $fp_r + + set data [split $file_data "\n"] + + #modify list elements () + if {$mod_file} { + if {[catch {set data [modify_block_design_commentlines $data]} result]} { TE::UTILS::te_msg TE_UTIL-13 ERROR "Script (TE::UTILS::modify_block_design_commentlines) failed: $result."; return -code error} + if {[catch {set data [modify_block_design_commentdesignprops $data]} result]} { TE::UTILS::te_msg TE_UTIL-14 ERROR "Script (TE::UTILS::modify_block_design_commentdesignprops) failed: $result."; return -code error} + if {[catch {set data [modify_block_design_add_lines $data]} result]} { TE::UTILS::te_msg TE_UTIL-15 ERROR "Script (TE::UTILS::modify_block_design_add_lines) failed: $result."; return -code error} + if {[catch {set data [modify_block_design_add_designprops $data]} result]} { TE::UTILS::te_msg TE_UTIL-16 ERROR "Script (TE::UTILS::modify_block_design_add_designprops) failed: $result."; return -code error} + } + # write info header + if {[catch {set data [TE::UTILS::setinfo_to_block_design_tcl $data $mod_file]} result]} { TE::UTILS::te_msg TE_UTIL-17 ERROR "Script (TE::UTILS::setinfo_to_block_design_tcl) failed: $result."; return -code error} + #write all list elements to file + set fp_w [open ${file_name} "w"] + foreach line $data { + puts $fp_w $line + } + close $fp_w + } + #-------------------------------- + #--modify_block_design_commentlines: + proc modify_block_design_commentlines {datalist} { + #data=tcl content + set data $datalist + #modify list elements + set line_index -1 + set mod_count 0 + foreach line $data { + incr line_index + foreach cname $TE::BD_MOD_COMMENT { + set line_check [lindex $cname 1] + #comment lines on tcl file, modified lines are ignored + if {[string match $line_check $line] && ![string match *#TE_MOD#* $line]} { + set data [lreplace $data[set data {}] $line_index $line_index "# #TE_MOD# $line"] + incr mod_count + } + } + } + TE::UTILS::te_msg TE_UTIL-18 INFO "Block Design tcl: $mod_count lines were commented out." + return $data + } + #-------------------------------- + #--modify_block_design_commentdesignprops: + proc modify_block_design_commentdesignprops {datalist} { + #data=tcl content + set data $datalist + #modify list elements + set mod_count 0 + foreach cname $TE::BD_MOD_PCOMMENT { + set prop_start_name "set_property -dict" + #get instant name + set inst_name [lindex $cname 1] + set prop_stop_name "\] \$$inst_name" + #modify list elements + set line_index -1 + set prop_start -1 + set prop_stop -1 + #search for property boundaries + foreach line $data { + incr line_index + if {[string match *$prop_start_name* $line] && ![string match *#TE_MOD#* $line]} { + set prop_start $line_index + } + if {[string match *$prop_stop_name $line] && ![string match *#TE_MOD#* $line]} { + set prop_stop $line_index + break; + } + } + #only if component found + if {$prop_start>=0 && $prop_stop>$prop_start} { + + set removed_items [list] + set item_cnt -1 + #removed items + foreach item $cname { + incr item_cnt + #ignore id and line_check + if {$item_cnt>1} { + set i $prop_stop + while {$i >= $prop_start} { + set i [expr $i-1] + set newline "[lindex $data $i]" + if {[string match *$item* $newline] && ![string match *#TE_MOD#* $newline]} { + lappend removed_items "# #TE_MOD# $newline" + set data [lreplace $data[set data {}] $i $i] + incr mod_count + } + } + } + } + #add removed items as comment after the component list + set inserpos [expr $prop_stop + 2 - [llength $removed_items]] + set data [linsert $data[set data {}] $inserpos "# #TE_MOD# #Empty Line"] + foreach el [lreverse $removed_items] { + set data [linsert $data[set data {}] $inserpos $el] + } + # if all properties are removed, clear empty property container + if {[expr $prop_stop-$prop_start]==[llength $removed_items]} { + set tmp "# #TE_MOD# [lindex $data $prop_start]" + set data [lreplace $data[set data {}] $prop_start $prop_start $tmp] + set tmp "# #TE_MOD# [lindex $data [expr $prop_start+1]]" + set data [lreplace $data[set data {}] [expr $prop_start+1] [expr $prop_start+1] $tmp] + } + } + } + TE::UTILS::te_msg TE_UTIL-19 INFO "Block Design tcl: $mod_count properties were commented out." + return $data + } + #-------------------------------- + #--modify_block_design_add_lines: + proc modify_block_design_add_lines {datalist} { + #data=tcl content + set data $datalist + #modify list elements + set line_index -1 + set mod_count 0 + foreach cname $TE::BD_MOD_ADD { + set line_check [lindex $cname 1] + set line_index -1 + foreach line $data { + incr line_index + #add lines on tcl file, modified lines are ignored + if {[string match $line_check $line] && ![string match *#TE_MOD#* $line]} { + # set data [lreplace $data[set data {}] $line_index $line_index "# #TE_MOD# $line"] + set data [linsert $data[set data {}] [expr $line_index+1] "# #TE_MOD#_Add next line#"] + set data [linsert $data[set data {}] [expr $line_index+2] [lindex $cname 2]] + incr mod_count + break + } + } + } + TE::UTILS::te_msg TE_UTIL-20 INFO "Block Design tcl: $mod_count lines were added." + return $data + } + #-------------------------------- + #--modify_block_design_add_designprops: + proc modify_block_design_add_designprops {datalist} { + #data=tcl content + set data $datalist + #modify list elements + set mod_count 0 + foreach cname $TE::BD_MOD_PADD { + #get instant name + set inst_name [lindex $cname 1] + set prop_stop_name "\] \$$inst_name" + #modify list elements + set line_index -1 + set prop_start -1 + set prop_stop -1 + set all_props_removed -1 + #search for property boundaries + foreach line $data { + incr line_index + if {[string match *$prop_stop_name $line]} { + if {![string match *#TE_MOD#* $line] } { + set prop_stop $line_index + } else { + set all_props_removed $line_index + } + break; + } + } + #if component props found + if {$prop_stop>-1} { + #add removed items as comment after the component list + set inserpos [expr $prop_stop + 1] + set el_index -1 + #add property as comment + foreach el $cname { + incr el_index + #ignore id and line_check + if {$el_index>1} { + set data [linsert $data[set data {}] $inserpos "# #TE_MOD#_add_property# $el"] + } + } + #add property + set inserpos [expr $prop_stop + -1] + set el_index -1 + foreach el $cname { + incr el_index + #ignore id and line_check + if {$el_index>1} { + set data [linsert $data[set data {}] $inserpos "$el \\"] + incr mod_count + } + } + } elseif {$all_props_removed>-1} { + #add removed items as comment after the component list + set inserpos [expr $all_props_removed + 1] + set el_index -1 + #add property as comment + foreach el $cname { + incr el_index + #ignore id and line_check + if {$el_index>1} { + set data [linsert $data[set data {}] $inserpos "# #TE_MOD#_add_property# $el"] + } + } + #add property + set inserpos [expr $all_props_removed + 1] + set el_index -1 + set data [linsert $data[set data {}] $inserpos " set_property -dict \[ list \\"] + incr inserpos + foreach el $cname { + incr el_index + #ignore id and line_check + if {$el_index>1} { + set data [linsert $data[set data {}] $inserpos "$el \\"] + incr inserpos + incr mod_count + } + } + set data [linsert $data[set data {}] $inserpos " \] \$[lindex $cname 1]"] + } + } + TE::UTILS::te_msg TE_UTIL-21 INFO "Block Design tcl: $mod_count properties were added." + return $data + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished modify block design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # generate workspace functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--workspace_info: + proc workspace_info {infofile info} { + set report_file ${infofile} + set fp_w [open ${report_file} "w"] + puts $fp_w "$info" + close $fp_w + } + #-------------------------------- + #--generate_workspace_hsi: + proc generate_workspace_hsi {{fname ""}} { + if {$fname eq ""} { + #use generated vivado data for workspace + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef]} { + file mkdir ${TE::WORKSPACE_HSI_PATH}/ + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef ${TE::WORKSPACE_HSI_PATH}/${TE::VPROJ_NAME}.hdf + # file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit ${TE::WORKSPACE_HSI_PATH} + workspace_info "${TE::WORKSPACE_PATH}/hsi_info.txt" "HSI Data used from ${TE::VPROJ_PATH}" + } else {TE::UTILS::te_msg TE_UTIL-23 WARNING "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef not found, HSI workspace was not generated."} + } else { + #use prebuilt data for workspace + set shortname "[TE::BDEF::find_shortdir $fname]" + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf]} { + file mkdir ${TE::WORKSPACE_HSI_PATH}/ + file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf ${TE::WORKSPACE_HSI_PATH}/${TE::VPROJ_NAME}.hdf + # file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.bit ${TE::WORKSPACE_HSI_PATH} + workspace_info "${TE::WORKSPACE_PATH}/hsi_info.txt" "HSI Data used from ${TE::PREBUILT_HW_PATH}/${shortname}" + } else {TE::UTILS::te_msg TE_UTIL-24 WARNING "${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf not found, HSI workspace was not generated."} + } + } + #-------------------------------- + #--generate_workspace_sdk: + proc generate_workspace_sdk {{fname ""}} { + #todo mal schauen ob vorher gelöcht werden muss oder ob überschreiben reicht + if {$fname eq ""} { + #use generated vivado data for workspace + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef]} { + file mkdir ${TE::WORKSPACE_SDK_PATH}/ + # file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + #use Toplevelname instead fo Project name -> export from Vivado GUI can used to + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef ${TE::WORKSPACE_SDK_PATH}/${TE::PR_TOPLEVELNAME}.hdf + # file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit ${TE::WORKSPACE_SDK_PATH} + workspace_info "${TE::WORKSPACE_PATH}/sdk_info.txt" "SDK Data used from ${TE::VPROJ_PATH}" + } else {TE::UTILS::te_msg TE_UTIL-25 WARNING "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef not found, SDK workspace was not generated."} + } else { + #use prebuilt data for workspace + set shortname "[TE::BDEF::find_shortdir $fname]" + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf]} { + file mkdir ${TE::WORKSPACE_SDK_PATH}/ + # file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + #use Toplevelname instead fo Project name -> export from Vivado GUI can used to + file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + # file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf ${TE::WORKSPACE_SDK_PATH}/${TE::PR_TOPLEVELNAME}.hdf + # file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.bit ${TE::WORKSPACE_SDK_PATH} + workspace_info "${TE::WORKSPACE_PATH}/sdk_info.txt" "SDK Data used from ${TE::PREBUILT_HW_PATH}/${shortname}" + } else {TE::UTILS::te_msg TE_UTIL-26 WARNING "${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf not found, SDK workspace was not generated."} + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished generate workspace functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # copy files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--copy_hw_files: + proc copy_hw_files { {deleteOldFile true}} { + #make new one + file mkdir ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR} + if {${TE::PR_TOPLEVELNAME} eq "NA" } { + TE::UTILS::te_msg TE_UTIL-27 {CRITICAL WARNING} "Script variable TE::PR_TOPLEVELNAME was not set, script properties will be reload." + TE::VIV::restore_scriptprops + } + #copy files only if bitfiles exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit]} { + #delete old prebuilt bitfile + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit} result]} {TE::UTILS::te_msg TE_UTIL-28 {CRITICAL WARNING} " $result"} + } + #copy and rename bitfile + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit + TE::UTILS::te_msg TE_UTIL-29 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit" + #-------------------------------- + #delete old prebuilt lpr + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.lpr] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.lpr} result]} {TE::UTILS::te_msg TE_UTIL-30 {CRITICAL WARNING} " $result"} + } + #copy and rename lpr + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.hw/${TE::VPROJ_NAME}.lpr ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.lpr + TE::UTILS::te_msg TE_UTIL-31 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.lpr was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.hw/${TE::VPROJ_NAME}.lpr" + #-------------------------------- + #delete old prebuilt ltx_file + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.ltx] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.ltx} result]} {TE::UTILS::te_msg TE_UTIL-32 {CRITICAL WARNING} " $result"} + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/debug_nets.ltx]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/debug_nets.ltx ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.ltx + TE::UTILS::te_msg TE_UTIL-33 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.ltx was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/debug_nets.ltx" + } else {TE::UTILS::te_msg TE_UTIL-34 INFO "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/debug_nets.ltx was not found."} + #delete old prebuilt hdf_file (hdf only on processor systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf} result]} {TE::UTILS::te_msg TE_UTIL-35 {CRITICAL WARNING} " $result"} + } + if {!$TE::IS_FSYS} { + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef]} { + #optional only on processor system: check bd file name --> for fsys no *hwdef and *sydef files needed + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf + TE::UTILS::te_msg TE_UTIL-35 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef" + } else {TE::UTILS::te_msg TE_UTIL-36 {CRITICAL WARNING} "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef was not found."} + } + #delete old prebuilt mmi (not for zynq systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mmi] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mmi} result]} {TE::UTILS::te_msg TE_UTIL-38 {CRITICAL WARNING} " $result"} + } + #delete old prebuilt mcs_file (not for zynq systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mcs] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mcs} result]} {TE::UTILS::te_msg TE_UTIL-39 {CRITICAL WARNING} " $result"} + } + #delete old prebuilt prm_file (not for zynq systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.prm] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.prm} result]} {TE::UTILS::te_msg TE_UTIL-40 {CRITICAL WARNING} " $result"} + } + #copy mmi + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mmi]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mmi ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mmi + TE::UTILS::te_msg TE_UTIL-41 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mmi was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mmi" + } else {TE::UTILS::te_msg TE_UTIL-42 WARNING "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mmi was not found."} + #copy mcs + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs]} { + #optional only on systems without processor used see TE::VIV::write_cfgmem for selection + #compare timestamps, if mcs is older than bitfile, rerun write mcs_file --> if gui is used to generate bitfile mcs will not recreate + set bittime [file mtime ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit] + set mcstime [file mtime ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs] + if {$mcstime < $bittime} { + TE::UTILS::te_msg TE_UTIL-43 INFO "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs is older as ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit . Regenerate mcs." + + if {[catch {TE::VIV::write_viv_cfgmem} result]} { TE::UTILS::te_msg TE_UTIL-44 ERROR "Script (TE::VIV::write_viv_cfgmem) failed: $result."; return -code error} + } + file mkdir ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.prm ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.prm + TE::UTILS::te_msg TE_UTIL-45 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.prm was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.prm" + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mcs + TE::UTILS::te_msg TE_UTIL-46 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.mcs was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs" + } else {TE::UTILS::te_msg TE_UTIL-47 WARNING "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs was not found."} + + } else {TE::UTILS::te_msg TE_UTIL-48 {CRITICAL WARNING} "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit was not found. Nothing was copied to prebuilt folder."} + } + #-------------------------------- + #--copy_sw_files: + proc copy_sw_files {} { + set dirs [glob -directory $TE::WORKSPACE_HSI_PATH *] + if { [llength $dirs] >0} { + #make new one + file mkdir ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR} + #copy files + foreach dir $dirs { + if {[file exists $dir/executable.elf]} { + #apps+fsbl + set fname [file tail $dir] + #delete old prebuilt elf file + if {[file exists ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/${fname}.elf]} { + if {[catch {file delete -force ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/${fname}.elf} result]} {TE::UTILS::te_msg TE_UTIL-49 {CRITICAL WARNING} " $result"} + } + #copy file + file copy -force $dir/executable.elf ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/${fname}.elf + TE::UTILS::te_msg TE_UTIL-50 INFO "${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/${fname}.elf was replaced with $dir/executable.elf" + } elseif {[file exists $dir/skeleton.dtsi]} { + #device tree + set fname [file tail $dir] + set devtree_folder ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${fname} + file mkdir ${devtree_folder} + if {[file exists ${devtree_folder}/skeleton.dtsi]} { + if {[catch {file delete -force ${devtree_folder}/skeleton.dtsi} result]} {TE::UTILS::te_msg TE_UTIL-51 {CRITICAL WARNING} " $result"} + } + if {[file exists ${devtree_folder}/system.dts]} { + if {[catch {file delete -force ${devtree_folder}/system.dts} result]} {TE::UTILS::te_msg TE_UTIL-52 {CRITICAL WARNING} " $result"} + } + if {[file exists ${devtree_folder}/zynq-7000.dtsi]} { + if {[catch {file delete -force ${devtree_folder}/zynq-7000.dtsi} result]} {TE::UTILS::te_msg TE_UTIL-53 {CRITICAL WARNING} " $result"} + } + file copy -force $dir/skeleton.dtsi ${devtree_folder}/skeleton.dtsi + file copy -force $dir/system.dts ${devtree_folder}/system.dts + file copy -force $dir/zynq-7000.dtsi ${devtree_folder}/zynq-7000.dtsi + TE::UTILS::te_msg TE_UTIL-54 INFO "Following device tree files are replaced \n \ + ${devtree_folder}/skeleton.dtsi was replaced with $dir/skeleton.dtsi \n \ + ${devtree_folder}/system.dts was replaced with $dir/system.dts \n \ + ${devtree_folder}/zynq-7000.dtsi was replaced with $dir/zynq-7000.dtsi \n \ + ------" + } + } + } else { + TE::UTILS::te_msg TE_UTIL-55 {CRITICAL WARNING} "$TE::WORKSPACE_HSI_PATH was empty. Nothing was copied to prebuilt folder." + } + } + #-------------------------------- + #--copy_hw_reports: + proc copy_hw_reports {} { + TE::UTILS::te_msg TE_UTIL-56 STATUS "Create reports in ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports" + file mkdir ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + #copy only if new bitfile exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit]} { + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + } + } + #create allways summary + create_prebuilt_hw_summary + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished copy files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--create_prebuilt_hw_summary: + proc create_prebuilt_hw_summary {} { + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}_summary.csv + set prebuilt_file ${TE::PREBUILT_HW_PATH}/hardware_summary.csv + #todo hardware_summary.csv erase of to large + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + if { ![file exists ${prebuilt_file}]} { + set fp_w [open ${prebuilt_file} "w"] + puts $fp_w [lindex $data 0] + puts $fp_w [lindex $data 1] + close $fp_w + } else { + set fp_a [open ${prebuilt_file} "a"] + puts $fp_a [lindex $data 1] + close $fp_a + } + TE::UTILS::te_msg TE_UTIL-57 INFO "Add HW report to: ${TE::PREBUILT_HW_PATH}/hardware_summary.csv" + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # clear functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--clean_vivado_project: + proc clean_vivado_project {} { + if { [file exists $TE::VPROJ_PATH] } { + if {[catch {file delete -force $TE::VPROJ_PATH} result]} {TE::UTILS::te_msg TE_UTIL-59 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-56 INFO "$TE::VPROJ_PATH was deleted."} + } + } + #-------------------------------- + #--clean_labtools_project: + proc clean_labtools_project {} { + if { [file exists $TE::VLABPROJ_PATH] } { + if {[catch {file delete -force $TE::VLABPROJ_PATH} result]} {TE::UTILS::te_msg TE_UTIL-60 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-61 INFO "$TE::VLABPROJ_PATH was deleted."} + } + } + #-------------------------------- + #--clean_workspace_hsi: + proc clean_workspace_hsi {} { + if { [file exists ${TE::WORKSPACE_HSI_PATH}] } { + if {[catch {file delete -force $TE::WORKSPACE_HSI_PATH} result]} {TE::UTILS::te_msg TE_UTIL-62 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-63 INFO "$TE::WORKSPACE_HSI_PATH was deleted."} + } + } + #-------------------------------- + #--clean_workspace_sdk: + proc clean_workspace_sdk {} { + if { [file exists ${TE::WORKSPACE_SDK_PATH}] } { + if {[catch {file delete -force $TE::WORKSPACE_SDK_PATH} result]} {TE::UTILS::te_msg TE_UTIL-64 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-65 INFO "$TE::WORKSPACE_SDK_PATH was deleted."} + } + } + #-------------------------------- + #--clean_workspace_all: + proc clean_workspace_all {} { + if { [file exists ${TE::WORKSPACE_PATH}] } { + if {[catch {file delete -force $TE::WORKSPACE_PATH} result]} {TE::UTILS::te_msg TE_UTIL-66 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-67 INFO "$TE::WORKSPACE_PATH was deleted."} + } + } + #-------------------------------- + #--clean_sdsoc: + proc clean_sdsoc {} { + if { [file exists ${TE::SDSOC_PATH}] } { + if {[catch {file delete -force $TE::SDSOC_PATH} result]} {TE::UTILS::te_msg TE_UTIL-68 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-69 INFO "$TE::SDSOC_PATH was deleted."} + } + } + #-------------------------------- + #--clean_all_generated_files: + proc clean_all_generated_files {} { + clean_vivado_project + clean_labtools_project + clean_workspace_hsi + clean_workspace_sdk + clean_workspace_all + clean_sdsoc + TE::UTILS::te_msg TE_UTIL-71 INFO "Clean all generated files finished." + } + #-------------------------------- + #--clean_prebuilt_all: + proc clean_prebuilt_all {} { + if { [file exists ${TE::PREBUILT_PATH}] } { + if {[catch {file delete -force $TE::PREBUILT_PATH} result]} {TE::UTILS::te_msg TE_UTIL-70 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-71 INFO "$TE::PREBUILT_PATH was deleted."} + } + } + #todo clean prebuilt single part -> bi hw ,sw, os + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "INFO:(TE) Load Utilities script finished" +} + + diff --git a/zynqberrydemo1/scripts/script_usrcommands.tcl b/zynqberrydemo1/scripts/script_usrcommands.tcl new file mode 100644 index 0000000..a6b12a9 --- /dev/null +++ b/zynqberrydemo1/scripts/script_usrcommands.tcl @@ -0,0 +1,991 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/16 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/02/06 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +# source in namespace of TE +namespace eval TE { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # help functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--help: + proc help {{args ""}} { + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-help" { set run_help true; incr option } + + default {TE::UTILS::te_msg TE_UTIL-79 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Help: \n\ + Description:\n\ + \ Display currently available user functions\n\ + Syntax:\n\ + \ help \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE\n\ + " + TE::UTILS::te_msg TE_INIT-93 STATUS $te_txt + } else { + TE::INIT::print_version + set te_txt "TE Script Help:\n\ + Available TE-Functions:" + if {![catch {set projectname [get_projects]} result]} { + set te_txt "$te_txt\n\ + \ ---------------------------------\n\ + \ Beta Test (advanced usage only!):\n\ + \ TE::ADV::beta_util_sdsoc_project \[-check_only\] \[-start_sdsoc\] \[-help\]\n\ + \ TE::ADV::beta_hw_remove_board_part \[-permanent\] \[-help\]\n\ + \ TE::ADV::beta_hw_export_rtl_ip \[-help\]" + } + set te_txt "$te_txt\n\ + \ ----------\n\ + \ Utilities:\n\ + \ TE::util_zip_project \[-save_all\] \[-remove_prebuilt\] \[-manual_filename \] \[-help\]\n\ + \ ------------\n\ + \ Programming:\n\ + \ TE::pr_init_hardware_manager \[-help\]\n\ + \ TE::pr_program_jtag_bitfile \[-used_board \] \[-swapp \] \[-available_apps\] \[-used_basefolder_bitfile\] \[-help\]\n\ + \ TE::pr_program_flash_binfile \[-no_reboot\] \[-used_board \] \[-swapp \] \[-available_apps\] \[-force_hw_manager\] \[-used_basefolder_binfile\] \[-help\]\n\ + \ TE::pr_program_flash_mcsfile \[-no_reboot\] \[-used_board \] \[-swapp \] \[-available_apps\] \[-used_basefolder_mcsfile\] \[-help\]" + if {![catch {set projectname [get_projects]} result]} { + # # on vivado project + set te_txt "$te_txt\n\ + \ ----------\n\ + \ Software Design:\n\ + \ TE::sw_run_hsi \[-run_only\] \[-prebuilt_hdf \] \[-no_hsi\] \[-no_bif\] \[-no_bin\] \[-no_bitmcs\] \[-force_bin\] \[-clear\] \[-help\]\n\ + \ TE::sw_run_sdk \[-open_only\] \[-update_hdf_only\] \[-prebuilt_hdf \] \[-clear\] \[-help\]\n\ + \ ----------\n\ + \ Hardware Design:\n\ + \ TE::hw_blockdesign_create_bd \[-bd_name\] \[-msys_local_mem\] \[-msys_ecc\] \[-msys_cache\] \[-msys_debug_module\] \[-msys_axi_periph\] \[-msys_axi_intc\] \[-msys_clk\] \[-help\]\n\ + \ TE::hw_blockdesign_export_tcl \[-no_mig_contents\] \[-no_validate\] \[-mod_tcl\] \[-svntxt \] \[-board_part_only\] \[-help\]\n\ + \ TE::hw_build_design \[-disable_bitgen\] \[-disable_hdf\] \[-disable_mcsgen\] \[-disable_reports\] \[-export_prebuilt\] \[-export_prebuilt_only\] \[-help\]" + } + set te_txt "$te_txt\n\ + ------------------------------------------\n\ + Note:Run only predefined TE-functions from this list. Run other TE-functions directly may cause errors.\n\ + Note:For more Informations see Trenz Electronic Wiki: https://wiki.trenz-electronic.de/display/PD/Project+Delivery \n\ + ------------------------------------------\n\ + " + TE::UTILS::te_msg TE_INIT-94 STATUS $te_txt + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished help functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hardware generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--hw_blockdesign_create_new_bd: + proc hw_blockdesign_create_bd {{args ""}} { + set bd_name "fsys" + set msys_local_mem "8KB" + set msys_ecc "None" + set msys_cache "None" + set msys_debug_module "Debug Only" + set msys_axi_periph "Enabled" + set msys_axi_intc "0" + set msys_clk "None" + + + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-bd_name" {incr option; set bd_name [lindex $args $option]} + "-help" {set run_help true} + default {TE::UTILS::te_msg TE_UTIL-80 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Create Block Design: \n\ + Description:\n\ + \ Create new Block Design with specified name. \n\ + \ Special Block Design names: \n\ + \ fsys -> used for FPGA-Fabric Design only. Generate empty Block Design. \n\ + \ msys -> used for Microblaze Design only. Generate Microblaze with defined parameters. \n\ + \ zsys -> used for 7Series Zynq Design only. Generate 7 Series Zynq with Board Part configuration and Carrier Board extended settings (if available). \n\ + \ zusys -> used for UltraScale Plus Zynq Design only. Generate UltraScale Plus Zynq with Board Part configuration and Carrier Board extended settings (if available). \n\ + Syntax:\n\ + \ TE::hw_blockdesign_create_bd \[-bd_name\] \[-msys_local_mem\] \[-msys_ecc\] \[-msys_cache\] \[-msys_debug_module\] \[-msys_axi_periph\] \[-msys_axi_intc\] \[-msys_clk\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-help\] Print help.\n\ + \ \[-bd_name\] Use one of the predefined names (def:fsys): fsys, msys, zsys, zusys \n\ + \ \[-msys_local_mem\] Use one of the predefined values(def:8KB): None, 4KB, 8KB, 16KB, 32KB, 64KB, 128KB \n\ + \ \[-msys_ecc\] Use one of the predefined values(def:None): None, Basic, Full \n\ + \ \[-msys_cache\] Use one of the predefined values(def:None): None, 4KB, 8KB, 16KB, 32KB, 64KB \n\ + \ \[-msys_debug_module\] Use one of the predefined values(def:Debug Only): None, Debug Only, \"Debug \& UART\", \"Extended Debug\" \n\ + \ \[-msys_axi_periph\] Use one of the predefined values(def:Enabled): Disabled, Enabled \n\ + \ \[-msys_axi_intc\] Use one of the predefined values(def:0): 0, 1 \n\ + \ \[-msys_clk\] Use one of the predefined values(def:None): None, \"New Clocking Wizard (100 MHz)\", \"New External Port (100 MHz)\" \n\ + Categories:\n\ + \ TE::VIV\n\ + " + TE::UTILS::te_msg TE_BD-19 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_BD-20 STATUS "Start Create Block Design." + # m_settings only used for msys + set m_settings {local_mem $msys_local_mem ecc $msys_ecc cache $msys_cache debug_module $msys_debug_module axi_periph $msys_axi_periph axi_intc $msys_axi_intc clk $msys_clk} + if {[catch {TE::VIV::create_new_blockdesign $bd_name $m_settings } result]} {TE::UTILS::te_msg TE_BD-21 ERROR "Script (TE::VIV::create_new_blockdesign) failed: $result."; return -code error} + TE::UTILS::te_msg TE_BD-22 STATUS "Create Block Design finished." + } + } + #-------------------------------- + #--hw_blockdesign_export_tcl: + proc hw_blockdesign_export_tcl {{args ""}} { + set no_mig "" + set no_validate "" + set boardpart_only "" + set mod_tcl "" + set svn_check false + set svn_msg "" + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-no_mig_contents" {set no_mig [lindex $args $option]} + "-mod_tcl" {set mod_tcl [lindex $args $option]} + "-no_validate" {set no_validate [lindex $args $option]} + "-svntxt" {incr option; set svn_check true; set svn_msg [lindex $args $option]} + "-board_part_only" {set boardpart_only [lindex $args $option]} + "-help" {set run_help true} + default {TE::UTILS::te_msg TE_UTIL-81 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Export Block Design: \n\ + Description:\n\ + \ Export Block Design as TCL-file. \n\ + \ File destination is $TE::BD_PATH or ${TE::BD_PATH}/${TE::SHORTDIR}/, if sub-folder exists. \n\ + \ If ${TE::BD_PATH}/${TE::SHORTDIR}/ exists, Block Designs from $TE::BD_PATH are ignored on project creation. \n\ + \ Attention: Open block-design will be saved automatically before export is run.\n\ + Syntax:\n\ + \ TE::hw_blockdesign_export_tcl \[-no_mig_contents\] \[-no_validate\] \[-mod_tcl\] \[-svntxt \] \[-board_part_only\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-no_mig_contents\] Vivado specific option when MIG is used: MIG-Configuration is excluded from TCL-File. Reference to mig.prj is used instead. Wrong usage will damaged design functionality!\n\ + \ \[-no_validate\] Design is saved without validation.\n\ + \ \[-board_part_only\] Export for this bord part only (tcl is stored in ${TE::BD_PATH}/${TE::SHORTDIR}/). \n\ + \ \[-mod_tcl\] TCL Content would be modified with content from $TE::BD_PATH\\mod_bd.tcl. If mod_bd.tcl don't exist or all commands inside are commented, nothing is changed. Wrong usage will damaged design functionality! \n\ + \ \[-svntxt \] Send svn commit with Text if SVN-versioning is used for the files in $TE::BD_PATH.\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VIV, TE::UTILS, TE::EXT\n\ + " + TE::UTILS::te_msg TE_BD-23 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_BD-24 STATUS "Start Export Block Design." + if {[catch {TE::VIV::export_blockdesign $no_mig $no_validate $boardpart_only $mod_tcl} result]} {TE::UTILS::te_msg TE_BD-24 ERROR "Script (TE::VIV::export_blockdesign) failed: $result."; return -code error} + if {$svn_check} { + if {[catch {TE::EXT::svn_checkin ${TE::BD_PATH} $svn_msg} result]} {TE::UTILS::te_msg TE_BD-25 ERROR "Script (TE::EXT::svn_checkin) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_BD-26 STATUS "Export Block Design finished." + } + } + #-------------------------------- + #--hw_build_design: + proc hw_build_design {{args ""}} { + set run_build true + set bitgen true + set mcsgen true + set reportgen true + set hdfgen true + set export_prebuild false + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-disable_bitgen" { set bitgen false} + "-disable_hdf" { set hdfgen false} + "-disable_mcsgen" { set mcsgen false} + "-disable_reports" { set reportgen false} + "-export_prebuilt_only" { set export_prebuild true; set run_build false} + "-export_prebuilt" { set export_prebuild true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-82 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Build Design: \n\ + Description:\n\ + \ Run Synthesises and Implementation with Bitstream generation. \n\ + \ Generate BIT-File on all BD-Names and MCS-File only on none Zynq/UltraScale Systems. \n\ + Syntax:\n\ + \ TE::hw_build_design \[-disable_bitgen\] \[-disable_hdf\] \[-disable_mcsgen\] \[-disable_reports\] \[-export_prebuilt\] \[-export_prebuilt_only\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-disable_bitgen\] Bit-File generation is disabled. \n\ + \ \[-disable_hdf\] HDF-File generation is disabled(delete *.sysdef). \n\ + \ \[-disable_mcsgen\] MCS-File generation for none Zynq/UltraScale Systems is disabled. \n\ + \ \[-disable_reports\] Report-Files generation for prebuilt folder is disabled. \n\ + \ \[-export_prebuilt\] Export generated HW-Files to the prebuilt folder (copy is done automatically, when hsi, sdk or jtag programming scripts starts in VIVADO). \n\ + \ \[-export_prebuilt_only\] Export generated HW-Files to the prebuilt folder without rebuild the design. \n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VIV,TE::UTILS\n\ + " + TE::UTILS::te_msg TE_HW-59 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_HW-60 STATUS "Start Build Design." + if {$run_build} { + if {[catch {TE::VIV::build_design $bitgen $mcsgen $reportgen $hdfgen} result]} {TE::UTILS::te_msg TE_HW-61 ERROR "Script (TE::VIV::build_design) failed: $result."; return -code error} + } + # copy is done if hsi, sdk or jtag programming is started or + if {$export_prebuild} { + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_HW-62 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_HW-63 INFO "No Hardware Reports found."} + } + TE::UTILS::te_msg TE_HW-64 STATUS "Build Design finished." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished hardware generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # software generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--sw_run_hsi: + proc sw_run_hsi {{args ""}} { + set run_help false + set run_copy true + set run_clear false + set run_prebuilt false + set run_prebuilt_hdf_only false + set run_hsi true + set run_bif true + set run_bin true + set force_bin false + set run_bitmcs true + set prebuilt_name "" + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-run_only" { set run_copy false} + "-prebuilt_hdf" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-prebuilt_hdf_only" { incr option; set run_prebuilt_hdf_only true; set prebuilt_name [lindex $args $option]} + "-no_hsi" { set run_hsi false} + "-no_bif" { set run_bif false} + "-no_bin" { set run_bin false} + "-no_bitmcs" { set run_bitmcs false} + "-force_bin" { set force_bin true} + "-clear" { set run_clear true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-83 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Run HSI: \n\ + Description:\n\ + \ Start HSI and create all software apps (*elf) and corresponding boot.bif and boot.bin (for Zynq/UZynq only) or .bit and .mcs (for MicroBlaze only), which are specified in apps_list.csv\n\ + \ Copy HW File and reports from the vivado project to the prebuilt folder if -prebuild_hdf isn't set (default)\n\ + \ *.hdef and *.sysdef are ignored if BD-Name is fsys (Without processor system). \n\ + \ Attention: Need SDK installation! \n\ + Syntax:\n\ + \ TE::sw_run_hsi \[-run_only\] \[-prebuilt_hdf \] \[-no_hsi\] \[-no_bif\] \[-no_bin\] \[-no_bitmcs\] \[-clear\] \[-help\]\n\ + Returns:\n\ + No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-prebuilt_hdf \] used *.bit and *.hdf from prebuilt folder instead of vivado project. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used. \n\ + \ \[-run_only\] used old data in workspace (*.bit and *.hdf)\n\ + \ \[-no_hsi\] disable *.elf generation\n\ + \ \[-no_bif\] disable boot.bif generation (for Zynq System only)\n\ + \ \[-no_bin\] disable boot.bin generation (for Zynq System only)\n\ + \ \[-force_bin\] disabllefor Zynq check for bif and bin generation\n\ + \ \[-no_bitmcs\] disable {appname}.bit and .mcs (for MicroBlaze System only) generation\n\ + \ \[-clear\] delete old data before workspace is created\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::UTILS, TE::EXT\n\ + " + TE::UTILS::te_msg TE_SW-39 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_SW-40 STATUS "Start HSI." + if {$run_clear} { + if {[catch {TE::UTILS::clean_workspace_hsi} result]} {TE::UTILS::te_msg TE_SW-41 ERROR "Script (TE::UTILS::clean_workspace_hsi) failed: $result."; return -code error} + } + + if {$run_hsi} { + if {$run_copy} { + if {$run_prebuilt} { + if {[catch {TE::UTILS::generate_workspace_hsi $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-42 ERROR "Script (TE::UTILS::generate_workspace_hsi) failed: $result."; return -code error} + } elseif {$run_prebuilt_hdf_only} { + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_SW-43 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_SW-44 INFO "No Hardware Reports found. "} + if {[catch {TE::UTILS::generate_workspace_hsi $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-45 ERROR "Script (TE::UTILS::generate_workspace_hsi) failed: $result."; return -code error} + } else { + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_SW-46 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_SW-47 INFO "No Hardware Reports found. "} + if {[catch {TE::UTILS::generate_workspace_hsi} result]} {TE::UTILS::te_msg TE_SW-48 ERROR "Script (TE::UTILS::generate_workspace_hsi) failed: $result."; return -code error} + } + } + if {[catch {TE::EXT::run_hsi} result]} {TE::UTILS::te_msg TE_SW-49 ERROR "Script (TE::EXT::run_hsi) failed: $result."; return -code error} + } + if {$TE::IS_ZSYS || $TE::IS_ZUSYS || $force_bin} { + #.bif and .bin only on zynq systems + if {$run_bif} { + if {[catch {TE::EXT::generate_bif_files $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-50 ERROR "Script (TE::EXT::generate_bif_files) failed: $result."; return -code error} + } + if {$run_bin} { + if {[catch {TE::EXT::generate_bootbin $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-51 ERROR "Script (TE::EXT::generate_bootbin) failed: $result."; return -code error} + } + } elseif {$TE::IS_MSYS} { + if {$run_bitmcs} { + if {[catch {TE::EXT::generate_app_bit_mcs $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-52 ERROR "Script (TE::EXT::generate_app_bit_mcs) failed: $result."; return -code error} + } + } else { + set te_txt "Boot.bif and Boot.bin only for Zynq-FPGAs available. .bit and .mcs only for MicroBlaze available. System will be checked with block design name, current BD file name is $TE::BD_TCLNAME .Use:\n\ + \ \"zsys_bd.tcl\" for Systems with Zynq \n\ + \ \"zusys_bd.tcl\" for Systems with UltraScale Zynq\n\ + \ \"msys_bd.tcl\" for Systems with MicroBlaze\n\ + \ \"fsys_bd.tcl\" for Systems with FPGA-Fabric design only\n\ + " + TE::UTILS::te_msg TE_SW-53 INFO $te_txt + } + TE::UTILS::te_msg TE_SW-54 STATUS "HSI finished." + } + } + #-------------------------------- + #--sw_run_sdk: + proc sw_run_sdk {{args ""}} { + set run_help false + set run_copy true + set start_sdk true + set run_clear false + set run_prebuilt false + set prebuilt_name "" + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-open_only" { set run_copy false} + "-update_hdf_only" { set start_sdk false} + "-prebuilt_hdf" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-clear" { set run_clear true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-84 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Run SDK: \n\ + Description:\n\ + \ Start SDK project in external folder $TE::WORKSPACE_SDK_PATH\n\ + \ Copy HW File and reports from the vivado project to the prebuilt folder if -prebuild_hdf isn't set (default)\n\ + \ *.hdef and *.sysdef are ignored if BD-Name is fsys (Without processor system). \n\ + \ Attention: If you use VIVADO GUI Command (File->Export-> Export Hardware..(Include Bit-file!) or File->Launch SDK) to Update or open SKD set new export path and workspace: $TE::WORKSPACE_SDK_PATH\n\ + \ Attention: Need SDK installation! \n\ + Syntax:\n\ + \ TE::sw_run_sdk \[-open_only\] \[-update_hdf_only\] \[-prebuilt_hdf \] \[-clear\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-prebuilt_hdf \] used *.hdf from prebuilt folder instead of vivado project. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used. \n\ + \ \[-open_only\] open SDK without update the *.hdf file \n\ + \ \[-update_hdf_only\] copy the new *.hdf file into the SDK workspace without open SDK\n\ + \ \[-clear\] delete old data before workspace is created\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::UTILS, TE::EXT\n\ + " + TE::UTILS::te_msg TE_SW-55 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_SW-56 STATUS "Start SDK" + if {$run_clear} { + if {[catch {TE::UTILS::clean_workspace_sdk} result]} {TE::UTILS::te_msg TE_SW-57 ERROR "Script (TE::UTILS::clean_workspace_sdk) failed: $result."; return -code error} + } + if {$run_copy} { + if {$run_prebuilt} { + if {[catch {TE::UTILS::generate_workspace_sdk $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-58 ERROR "Script (TE::UTILS::generate_workspace_sdk) failed: $result."; return -code error} + } else { + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_SW-59 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_SW-60 INFO "No Hardware Reports found."} + if {[catch {TE::UTILS::generate_workspace_sdk} result]} {TE::UTILS::te_msg TE_SW-61 ERROR "Script (TE::UTILS::generate_workspace_sdk) failed: $result."; return -code error} + } + } + if {$start_sdk} { + if {[catch {TE::EXT::run_sdk} result]} {TE::UTILS::te_msg TE_SW-62 ERROR "Script (TE::EXT::run_sdk) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_SW-63 STATUS "SDK finished." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished software generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--pr_program_flash_binfile: + proc pr_program_flash_binfile {{args ""}} { + set return_filename "" + set use_basefolder false + set use_sdk_flash true + set run_help false + set run_prebuilt false + set appname "" + set prebuilt_name "" + set print_available_apps false + set reboot true + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-no_reboot" { set reboot false} + "-used_board" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-swapp" { incr option; set appname [lindex $args $option]} + "-available_apps" { set print_available_apps true} + "-force_hw_manager" { set use_sdk_flash false} + "-used_basefolder_binfile" {set use_basefolder true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-85 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Program Flash with Bin-File: \n\ + Description:\n\ + \ Programming specified FPGA-Flash with bin-file (Zynq-Processors only).\n\ + \ It will be program the boot.bin from the corresponding prebuilt folder, which is set in the vivado project, if -used_board isn't set.\n\ + Syntax:\n\ + \ TE::pr_program_flash_binfile \[-no_reboot\] \[-used_board \] \[-swapp \] \[-available_apps\] \[-used_basefolder_binfile\] \[-help\]\n\ + Returns:\n\ + \ Programming file-name.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-no_reboot\] Memory will be only configured, no JTag reboot is done.\n\ + \ \[-used_board \] Used prebuilt folder board version instead of Vivado project settings. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used.\n\ + \ \[-swapp \] Software APP name which should be programmed.\n\ + \ \[-available_apps\] Return available software APP names from selected the prebuilt boot_images folder.\n\ + \ \[-force_hw_manager\] Force LabTools Hardware-Manager instead of SDK-Programmer. Boot.bin can be configured via SDK-Programmer or LabTools Hardware-Manager. If both available SDK-Programmer is used default. \n\ + \ \[-used_basefolder_binfile\] Use base-folder bin-file ($TE::BASEFOLDER). Should be only one *.bin!\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::EXT, TE::VLAB\n\ + " + TE::UTILS::te_msg TE_PR-43 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_PR-44 STATUS "Start Flash Programming with BIN File" + set starttime [clock seconds] + if {$print_available_apps} { + if {[catch {TE::EXT::get_available_apps $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-45 ERROR "Script (TE::EXT::get_available_apps) failed: $result."; return -code error} + } else { + if {$appname eq ""} {TE::UTILS::te_msg TE_PR-46 ERROR "No APP name is selected see \[pr_program_flash_binfile -help\]: $result."; return -code error} + if {$prebuilt_name ne ""} { + set id "[TE::BDEF::find_id $prebuilt_name]" + set zynqflashtyp_int [TE::BDEF::get_zynqflashtyp $id 0] + } else { + set zynqflashtyp_int $TE::ZYNQFLASHTYP + } + + set check_zynqflash false + if {$zynqflashtyp_int ne "NA"} { + set check_zynqflash true + } + + if {$::env(SDK_AVAILABLE) && $check_zynqflash && $use_sdk_flash} { + if {[catch {set return_filename [TE::EXT::excecute_zynq_flash_programming $use_basefolder $appname $prebuilt_name]} result]} {TE::UTILS::te_msg TE_PR-47 ERROR "Script (TE::EXT::excecute_zynq_flash_programming) failed: $result."; return -code error} + if {$reboot} { + set hw_close true + if {[catch {set hw_close [TE::VLAB::hw_open_jtag]} result]} {TE::UTILS::te_msg TE_PR-48 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + if {[catch {TE::VLAB::hw_fpga_boot_from_memory $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-49 ERROR "Script (TE::VLAB::hw_fpga_boot_from_memory) failed: $result."; return -code error} + if {$hw_close} { + if {[catch {TE::VLAB::hw_close_jtag} result]} {TE::UTILS::te_msg TE_PR-50 ERROR "Script (TE::VLAB::hw_close_jtag) failed: $result."; return -code error} + } + } + } else { + set hw_close true + if {[catch {set hw_close [TE::VLAB::hw_open_jtag]} result]} {TE::UTILS::te_msg TE_PR-51 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + + if {[catch {TE::VLAB::hw_create_flash_device $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-52 ERROR "Script (TE::VLAB::hw_create_flash_device) failed: $result."; return -code error} + if {[catch {set return_filename [TE::VLAB::hw_program_fpga_flash $use_basefolder "" bin $appname $prebuilt_name]} result]} {TE::UTILS::te_msg TE_PR-53 ERROR "Script (TE::VLAB::hw_program_fpga_flash) failed: $result."; return -code error} + + if {$reboot} { + if {[catch {TE::VLAB::hw_fpga_boot_from_memory $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-54 ERROR "Script (TE::VLAB::hw_fpga_boot_from_memory) failed: $result."; return -code error} + } + if {$hw_close} { + if {[catch {TE::VLAB::hw_close_jtag} result]} {TE::UTILS::te_msg TE_PR-55 ERROR "Script (TE::VLAB::hw_close_jtag) failed: $result."; return -code error} + } + } + } + set stoptime [clock seconds] + set timeelapsed [expr $stoptime -$starttime] + TE::UTILS::te_msg TE_PR-56 INFO "Programming elapsed time: $timeelapsed seconds" + TE::UTILS::te_msg TE_PR-57 STATUS "Flash Programming with BIN File finished" + } + return $return_filename + } + #-------------------------------- + #--pr_program_flash_mcsfile: + proc pr_program_flash_mcsfile {{args ""}} { + set return_filename "" + set run_help false + set run_prebuilt false + set appname "" + set prebuilt_name "" + set print_available_apps false + set reboot true + set term "pull-none" + set use_basefolder false + #pull-none (default)#pull-up #pull-down + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-no_reboot" { set reboot false} + "-used_board" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-unused_io_termination" { incr option; set term [lindex $args $option]} + "-swapp" { incr option; set appname [lindex $args $option]} + "-available_apps" { set print_available_apps true} + "-used_basefolder_mcsfile" {set use_basefolder true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-86 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Program Flash with MCS File: \n\ + Description:\n\ + \ Programming specified FPGA-Flash with mcs-File (No Zynq-Processors only).\n\ + \ It will be program the .mcs from the corresponding prebuilt folder which is set in the vivado/labtool project, if -used_board isn't set. \n\ + Syntax:\n\ + \ TE::pr_program_flash_mcsfile \[-no_reboot\] \[-used_board \] \[-unused_io_termination \] \[-swapp \] \[-available_apps\] \[-used_basefolder_mcsfile\] \[-help\]\n\ + Returns:\n\ + \ Programming file-name.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-no_reboot\] Memory will be only configured, no JTag reboot is done.\n\ + \ \[-used_board \] Used prebuilt folder board version instead of vivado project settings. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used.\n\ + \ \[-unused_io_termination \] Set termination for unused Device IO-Pins Available Settings are: pull-none, pull-up or pull-down. Default pull-none is used.\n\ + \ \[-swapp \] Software app name which should be programmed(If app name isn't set, the mcs-file from the prebuilt hardware folder is used). \n\ + \ \[-available_apps\] Return available software app names from selected the prebuilt boot_images folder.\n\ + \ \[-used_basefolder_mcsfile\] Use base-folder mcs-file ($TE::BASEFOLDER). Should be only one *.mcs!\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::EXT, TE::VLAB\n\ + " + TE::UTILS::te_msg TE_PR-58 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_PR-59 STATUS "Start Flash Programming with BIN File" + set starttime [clock seconds] + if {$print_available_apps} { + if {[catch {TE::EXT::get_available_apps $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-60 ERROR "Script (TE::EXT::get_available_apps) failed: $result."; return -code error} + } else { + if {!$run_prebuilt} { + if {![catch {set projectname [get_projects]} result]} { + #copy only on vivado project + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_PR-61 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_PR-62 INFO "No Hardware Reports found."} + } + } + set hw_close true + if {[catch {set hw_close [TE::VLAB::hw_open_jtag]} result]} {TE::UTILS::te_msg TE_PR-63 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + + if {[catch {TE::VLAB::hw_create_flash_device $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-64 ERROR "Script (TE::VLAB::hw_create_flash_device) failed: $result."; return -code error} + if {[catch {set return_filename [TE::VLAB::hw_program_fpga_flash $use_basefolder $term mcs $appname $prebuilt_name]} result]} {TE::UTILS::te_msg TE_PR-65 ERROR "Script (TE::VLAB::hw_program_fpga_flash) failed: $result."; return -code error} + + if {$reboot} { + if {[catch {TE::VLAB::hw_fpga_boot_from_memory $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-66 ERROR "Script (TE::VLAB::hw_fpga_boot_from_memory) failed: $result."; return -code error} + } + if {$hw_close} { + if {[catch {TE::VLAB::hw_close_jtag} result]} {TE::UTILS::te_msg TE_PR-67 ERROR "Script (TE::VLAB::hw_close_jtag) failed: $result."; return -code error} + } + } + set stoptime [clock seconds] + set timeelapsed [expr $stoptime -$starttime] + TE::UTILS::te_msg TE_PR-68 INFO "Programming elapsed time: $timeelapsed seconds" + TE::UTILS::te_msg TE_PR-69 STATUS "Flash Programming with BIN File finished." + } + return $return_filename + } + #-------------------------------- + #--pr_program_jtag_bitfile: + proc pr_program_jtag_bitfile {{args ""}} { + set return_filename "" + set print_available_apps false + set run_help false + set run_prebuilt false + set use_basefolder false + set prebuilt_name "" + set appname "" + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-used_board" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-swapp" { incr option; set appname [lindex $args $option]} + "-available_apps" { set print_available_apps true} + "-used_basefolder_bitfile" {set use_basefolder true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-87 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Program FPGA with Bit File: \n\ + Description:\n\ + \ Programming FPGA with BIT-File.\n\ + \ Copy HW File and reports from the Vivado project to the prebuilt folder, if -used_board isn't set (default)\n\ + Syntax:\n\ + \ TE::pr_program_jtag_bitfile \[-used_board \] \[-used_basefolder_bitfile\] \[-help\]\n\ + Returns:\n\ + \ Programming file-name.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-used_board \] Used prebuilt folder board version instead of vivado project settings. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used.\n\ + \ \[-swapp \] Software app name which should be programmed. (If app name isn't set, the bit-file from the prebuilt hardware folder is used)\n\ + \ \[-available_apps\] Return available software app names from selected the prebuilt boot_images folder.\n\ + \ \[-used_basefolder_bitfile\] Use base-folder bit-file ($TE::BASEFOLDER). Should be only one *.bit!\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VLAB\n\ + " + TE::UTILS::te_msg TE_PR-70 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_PR-71 STATUS "Start FPGA Programming with Bit File" + set starttime [clock seconds] + if {$print_available_apps} { + if {[catch {TE::EXT::get_available_apps $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-72 ERROR "Script (TE::EXT::get_available_apps) failed: $result."; return -code error} + } else { + if {!$run_prebuilt} { + if {![catch {set projectname [get_projects]} result]} { + #copy only on vivado project + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_PR-73 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_PR-74 INFO "No Hardware Reports found. "} + } + } + set hw_wasclosed false + if {[current_hw_server] eq ""} {set hw_wasclosed true} + if {[catch {TE::VLAB::hw_open_jtag} result]} {TE::UTILS::te_msg TE_PR-75 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + if {[catch {set return_filename [TE::VLAB::hw_program_fpga_device $use_basefolder $appname $prebuilt_name]} result]} {TE::UTILS::te_msg TE_PR-76 ERROR "Script (TE::VLAB::hw_program_fpga_device) failed: $result."; return -code error} + if {$hw_wasclosed} { + if {[catch {TE::VLAB::hw_close_jtag} result]} {TE::UTILS::te_msg TE_PR-77 ERROR "Script (TE::VLAB::hw_close_jtag) failed: $result."; return -code error} + } + } + set stoptime [clock seconds] + set timeelapsed [expr $stoptime -$starttime] + TE::UTILS::te_msg TE_PR-78 INFO "Programming elapsed time: $timeelapsed seconds" + TE::UTILS::te_msg TE_PR-79 STATUS "FPGA Programming with BIT File finished." + } + return $return_filename + } + #-------------------------------- + #--pr_init_hardware_manager: + proc pr_init_hardware_manager {{args ""}} { + set run_help false + set run_prebuilt false + set prebuilt_name "" + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-88 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Initialise Hardware Manager: \n\ + Description:\n\ + \ Open Hardware-Manager, auto-connect target device and initialise flash memory with configuration from *_board_files.csv.\n\ + \ If flash memory isn't specified, it will be ignored. \n\ + Syntax:\n\ + \ TE::pr_init_hardware_manager \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VLAB\n\ + " + TE::UTILS::te_msg TE_PR-80 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_PR-81 STATUS "Start Init Hardware Manager" + if {[catch {TE::VLAB::hw_open_jtag} result]} {TE::UTILS::te_msg TE_PR-82 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + if {${TE::FPGAFLASHTYP} ne "NA"} { + if {[catch {TE::VLAB::hw_create_flash_device} result]} {TE::UTILS::te_msg TE_PR-83 ERROR "Script (TE::VLAB::hw_create_flash_device) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_PR-84 STATUS "Initialise Hardware Manager finished." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # utilities functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--util_zip_project: + proc util_zip_project {{args ""}} { + set run_help false + set manual_name false + set tmp [split $TE::SHORTDIR "_"] + set zipname "" + + #settings + set remove_prebuilt false + set save_all false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-manual_filename" { incr option; set zipname [lindex $args $option];set manual_name true} + "-remove_prebuilt" { set remove_prebuilt true} + "-save_all" { set save_all true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-89 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {!$manual_name} { + #boardname + set zipname [lindex $tmp 0] + #projectname + set zipname "${zipname}-${TE::VPROJ_NAME}" + if {$remove_prebuilt} { + set zipname "${zipname}_noprebuilt" + } + if {$save_all} { + set zipname "${zipname}_all" + } + #vivado version + set zipname "${zipname}-vivado_$::env(VIVADO_VERSION)" + #Scipt version (last id) + set tmp [split $TE::SCRIPTVER "."] + set scriptver [lindex $tmp [expr [llength $tmp]-1]] + set zipname "${zipname}-build_${scriptver}" + #timestamp + set date "[ clock format [clock seconds] -format "%Y%m%d%H%M%S"]" + set zipname "${zipname}_${date}" + } + if {$run_help} { + set te_txt "TE Script Backup Project: \n\ + Description:\n\ + \ Generate Zip file from current project in folder $TE::BACKUP_PATH.\n\ + \ Supported ZIP-Programs:7z.exe (7 zip) and zip.exe (Info ZIP) \n\ + \ Did not save files, which are specified in /settings/zip_ignore_list.csv.\n\ + Syntax:\n\ + \ TE::util_zip_project \[-save_all\] \[-remove_prebuilt\] \[-manual_filename \] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-manual_filename \] Specify name instead auto-generate name.\n\ + \ \[-remove_prebuilt\] Save backup without prebuilt(Command is ignored if -save_all is selected).\n\ + \ \[-save_all\] Save all, otherwise work path like vivado, workspace, vlog and other specified folders/files are excluded.\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::EXT\n\ + " + TE::UTILS::te_msg TE_UTIL-95 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_UTIL-96 STATUS "Start Backup Project:" + if {$save_all} { + if {[catch {TE::EXT::zip_project $zipname} result]} {TE::UTILS::te_msg TE_UTIL-97 ERROR "Script (TE::EXT::zip_project) failed: $result."; return -code error} + } else { + #default list for old projects: + set excludelist "vivado vivado_lab workspace v_log run_prebuilt_all.cmd block_design/mod_bd.csv scripts/.svn sdsoc settings/development_settings.tcl" + #read ignore list from file + if {[llength $TE::ZIP_IGNORE_LIST] > 0} { + set excludelist [] + foreach entry $TE::ZIP_IGNORE_LIST { + if {[lindex $entry 0]==0} { + #only id0 objects + lappend excludelist [lindex $entry 1] + } elseif {[lindex $entry 0]==1} { + #only id1 objects + set find [] + catch {set find [glob -join -dir $TE::BASEFOLDER [lindex $entry 1]]} + foreach el $find { + set sl_start [expr [string length $TE::BASEFOLDER]+1] + set sl_stop [string length $el] + lappend excludelist [string range $el $sl_start $sl_stop] + } + } + } + } + if {$remove_prebuilt} { + lappend excludelist "prebuilt" + } + if {[catch {TE::EXT::zip_project $zipname $excludelist} result]} {TE::UTILS::te_msg UTIL-98 ERROR " Script (TE::EXT::zip_project) failed: $result."; return -code error} + } + TE::UTILS::te_msg UTIL-99 STATUS "Backup Project finished." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished utilities functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # beta test functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + namespace eval ADV { + #-------------------------------- + #--beta_util_sdsoc_project: + proc beta_util_sdsoc_project {{args ""}} { + set run_help false + set start_sdsoc false + set check_sdsoc false + + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-check_only" { set check_sdsoc true} + "-start_sdsoc" { set start_sdsoc true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-90 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + + if {$run_help} { + set te_txt "TE Script SDSoC Project: \n\ + Description:\n\ + \ Generate SDSoC project structure in $TE::SDSOC_PATH.\n\ + \ 7-ZIP-Program is required (see design_basic_settings.cmd).\n\ + \ Attention: This Project will be modified! To restore, close this Project after SDSOC generation an run create project batch file.\n\ + Syntax:\n\ + \ TE::ADV::beta_util_sdsoc_project \[-check_only\] \[-start_sdsoc\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-check_only\] Check this project for SDSOC support (no modification are done).\n\ + \ \[-start_sdsoc\] Start SDSOC with workspace: $TE::SDSOC_PATH.\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::SDSOC, TE::EXT\n\ + " + TE::UTILS::te_msg TE_HW-65 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_HW-66 STATUS "Start SDSoC Project:" + if {$check_sdsoc} { + if {[catch {TE::SDSOC::check_and_modify_vivado_project true} result]} {TE::UTILS::te_msg TE_HW-67 ERROR "Script (TE::SDSOC::check_and_modify_vivado_project) failed: $result."; return -code error} + } elseif {$start_sdsoc} { + if {[catch {TE::EXT::run_sdsoc} result]} {TE::UTILS::te_msg TE_HW-68 ERROR "Script (TE::EXT::run_sdsoc) failed: $result."; return -code error} + } else { + if {[catch {TE::SDSOC::create_sdsoc_structure} result]} {TE::UTILS::te_msg TE_HW-69 ERROR "Script (TE::SDSOC::create_sdsoc_structure) failed: $result."; return -code error} + if {[catch {TE::SDSOC::check_and_modify_vivado_project false} result]} {TE::UTILS::te_msg TE_HW-70 ERROR "Script (TE::SDSOC::check_and_modify_vivado_project) failed: $result."; return -code error} + #todo rebuild project files + if {[catch {TE::SDSOC::export_vivado_sdsoc_project} result]} {TE::UTILS::te_msg TE_HW-71 ERROR "Script (TE::SDSOC::export_vivado_sdsoc_project) failed: $result."; return -code error} + if {[catch {TE::SDSOC::create_sdsoc_pfm} result]} {TE::UTILS::te_msg TE_HW-72 ERROR "Script (TE::SDSOC::create_sdsoc_pfm) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_HW-73 STATUS "SDSoC Project finished." + } + } + #-------------------------------- + #--beta_hw_remove_board_part + proc beta_hw_remove_board_part {{args ""}} { + set temp_only true + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-permanent" {set temp_only false} + "-help" {set run_help true} + default {TE::UTILS::te_msg TE_UTIL-91 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Remove Board part: \n\ + Description:\n\ + \ Remove board part from project.\n\ + \ Attention:\n\ + \ Function not supported for all Block-Design IPs.\n\ + \ Check design after automatically modifications are done!\n\ + \ To restore project after permanent modification do:\n\ + \ Delete ${TE::BD_PATH}/*.tcl.\n\ + \ Rename ${TE::BD_PATH}/*.tcl_backup into ${TE::BD_PATH}/*.tcl.\n\ + \ Delete ${TE::BOARDDEF_PATH}/*_board_files_mod.csv.\n\ + Syntax:\n\ + \ TE::ADV::beta_hw_remove_board_part \[-permanent\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-permanent\] Board Part is removed permanently for this vivado project.TCL-File is generated and alternative board_part.cvs is used on design creation.\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VIV, TE::UTILS\n\ + " + TE::UTILS::te_msg TE_HW-74 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_HW-75 STATUS "Start Remove Board Part:" + if {[catch {TE::VIV::design_exclude_boarddef $temp_only} result]} {TE::UTILS::te_msg TE_HW-76 ERROR "Script (TE::VIV::design_exclude_boarddef) failed: $result."; return -code error} + TE::UTILS::te_msg TE_HW-77 STATUS "Remove Board Part finished." + } + } + #-------------------------------- + #--beta_hw_export_rtl_ip + proc beta_hw_export_rtl_ip {{args ""}} { + set run_help false + set board_part_only false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-help" {set run_help true} + default {TE::UTILS::te_msg TE_UTIL-92 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Remove Board part: \n\ + Description:\n\ + \ Export RTL-IP Cores (*.xci), which are not included in a Block-Design to ${TE::HDL_PATH}/xci/${TE::SHORTDIR}.\n\ + \ HDL and *.xci files, which include in the folder $TE::HDL_PATH are load automatically on project creation.\n\ + Syntax:\n\ + \ TE::ADV::beta_hw_export_rtl_ip \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VIV, TE::UTILS\n\ + " + TE::UTILS::te_msg TE_HW-78 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_HW-79 STATUS "Start Export RTL-IPs:" + if {[catch {TE::VIV::export_xci} result]} {TE::UTILS::te_msg TE_HW-80 ERROR "Script (TE::VIV::export_xci) failed: $result."; return -code error} + TE::UTILS::te_msg TE_HW-81 STATUS "Export RTL-IPs finished." + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished beta test functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + puts "INFO:(TE) Load User Command scripts finished" +} \ No newline at end of file diff --git a/zynqberrydemo1/scripts/script_vivado.tcl b/zynqberrydemo1/scripts/script_vivado.tcl new file mode 100644 index 0000000..78317ca --- /dev/null +++ b/zynqberrydemo1/scripts/script_vivado.tcl @@ -0,0 +1,1556 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/03 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/04/13 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval VIV { + + # ------------------------------------------------------- + # ----advanced functions are currently official not supported + # ------------------------------------------------------- + #-------------------------------- + #--export_vivado_setting: + proc export_vivado_setting {} { + # hidden function: official not supported + set old_file_data "" + if {![file exists $TE::SET_PATH]} { + file mkdir ${TE::SET_PATH}/ + } elseif {[file exists ${TE::SET_PATH}/project_settings.tcl]} { + # additional project settings + set fp_r [open ${TE::SET_PATH}/project_settings.tcl "r"] + set old_file_data [read $fp_r] + close $fp_r + } + set fp_w [open ${TE::SET_PATH}/project_settings.tcl "w"] + + puts $fp_w "##############################" + puts $fp_w "# --------------------------------------------------------------------" + puts $fp_w "# -- ***************************** " + puts $fp_w "# -- * Trenz Electronic GmbH * " + puts $fp_w "# -- * Holzweg 19A * " + puts $fp_w "# -- * 32257 Bünde * " + puts $fp_w "# -- * Germany * " + puts $fp_w "# -- ***************************** " + puts $fp_w "# --------------------------------------------------------------------" + puts $fp_w "##############################" + puts $fp_w "##Automatically exported settings:" + puts $fp_w "##Creation time: [ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"]" + puts $fp_w "##Board Part: [get_property board_part [current_project]]" + puts $fp_w "##Part: [get_property part [current_project]]" + puts $fp_w "#Export Settings currently not available." + puts $fp_w "#This file will be read on project generation only." + puts $fp_w "##############################" + puts $fp_w "#Old file settings:" + puts $fp_w $old_file_data + puts $fp_w "##############################" + puts $fp_w "#exported file settings:" + puts $fp_w "puts \"Info:(TE) Automatically exported settings.\"" + puts $fp_w "#set_property \"board_part\" [get_property board_part [current_project]] \[current_project\]" + puts $fp_w "#set_property \"part\" [get_property part [current_project]] \[current_project\]" + close $fp_w + TE::UTILS::te_msg TE_HW-0 STATUS "${TE::SET_PATH}/project_settings.tcl was created." + } + #-------------------------------- + #--import_vivado_setting: + proc import_vivado_setting {} { + # hidden function: official not supported + if {[file exists ${TE::SET_PATH}/project_settings.tcl]} { + # additional project settings + TE::UTILS::te_msg TE_HW-1 INFO "Load additional project properties from ${TE::SET_PATH}/project_settings.tcl" + source ${TE::SET_PATH}/project_settings.tcl + } + } + + #-------------------------------- + #--design_exclude_boarddef: + proc design_exclude_boarddef {temp_only} { + # hidden function: official not supported + #run only if board part is defined + if {[get_property board_part [current_project]] ne ""} { + #get bd files + set bd_files [list] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + } + if {[llength $bd_files]>1} { + TE::UTILS::te_msg TE_HW-1 ERROR "Exclude Board part failed. Only one Block Design supported for this function." + return -code error; + } + #run rtl for xdc export + synth_design -rtl -name rtl_1 + set pjc_xdc_path "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::CONST_NAME}" + file mkdir $pjc_xdc_path + #export io locs (needed if constrain in board part only) + write_xdc -force -mode port ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc + #remove wrong properties + set fp_r [open ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc "r"] + set file_data [read $fp_r] + close $fp_r + set data [split $file_data "\n"] + set fp_w [open ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc "w"] + puts $fp_w "##############################" + puts $fp_w "# --------------------------------------------------------------------" + puts $fp_w "# -- ***************************** " + puts $fp_w "# -- * Trenz Electronic GmbH * " + puts $fp_w "# -- * Holzweg 19A * " + puts $fp_w "# -- * 32257 Buende * " + puts $fp_w "# -- * Germany * " + puts $fp_w "# -- ***************************** " + puts $fp_w "# --------------------------------------------------------------------" + puts $fp_w "##############################" + puts $fp_w "##Automatically exported port constrains from exclude board part function:" + puts $fp_w "##Creation time: [ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"]" + puts $fp_w "##Board Part: [get_property board_part [current_project]]" + puts $fp_w "##Part: [get_property part [current_project]]" + puts $fp_w "##############################" + foreach line $data { + #ignore some properties + if {![string match "*set_property DIRECTION*" $line] && ![string match "*set_property IBUF_LOW_PWR*" $line] && ![string match "*current_instance -quiet*" $line]} { + puts $fp_w $line + } + } + close $fp_w + + #add constrains file + add_files -fileset ${TE::CONST_NAME} ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc + set_property used_in_synthesis false [get_files ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc] + #modify some ip setting manually + set mig_project "" + # set mig_addr_offset "" + foreach bd $bd_files { + open_bd_design $bd + TE::UTILS::te_msg TE_HW-2 INFO "Exclude Board part: Remove Board Part settings from IPs in $bd" + #------------- + #mig + if {[catch {[get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]}]} { + TE::UTILS::te_msg TE_HW-3 WARNING "Exclude Board part: MIG was found modified. Check Settings after run in $bd" + catch {set_property CONFIG.BOARD_MIG_PARAM Custom [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]} + catch {set mig_project [get_property CONFIG.XML_INPUT_FILE [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]]} + # catch {set mig_addr_offset [get_property range [get_bd_addr_segs -of_objects [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]]]} + } + #------------- + #TE ASIO + if {[catch {[get_bd_cells -hierarchical -filter {VLNV=~"*axis_asio_gpio*"}]}]} { + TE::UTILS::te_msg TE_HW-4 WARNING "Exclude Board part: ASIO IP was found and modified. Check Settings after run in $bd" + catch {set_property CONFIG.USE_BOARD_FLOW false [get_bd_cells -hierarchical -filter {VLNV=~"*axis_asio_gpio*"}]} + catch {set_property CONFIG.P0_BOARD_INTERFACE Custom [get_bd_cells -hierarchical -filter {VLNV=~"*axis_asio_gpio*"}]} + } + } + #disable board definition + set_property "part" "[get_property part [current_project]]" [current_project] + #update ip's + set ip_names [get_ips] + if {[llength $ip_names]>0 } { + ::report_ip_status -name ip_status + foreach ip $ip_names { + TE::UTILS::te_msg TE_HW-5 INFO "Exclude Board part: Upgrade IP: $ip_names" + if {[catch {::upgrade_ip [get_ips $ip]}] } {TE::UTILS::te_msg TE_HW-6 {CRITICAL WARNING} "Exclude Board part: Upgrade IP: $ip_names failed and will be ignored." } + } + ::report_ip_status -name ip_status + } + #restore some ip setting manually + foreach bd $bd_files { + #------------- + #mig + if {[catch {[get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]}]} { + catch {set_property CONFIG.XML_INPUT_FILE $mig_project [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]} + catch {assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]]} + # catch {set_property range $mig_addr_offset [get_bd_addr_segs -of_objects [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]]} + } + #------------- + #TE ASIO + if {[catch {[get_bd_cells -hierarchical -filter {VLNV=~"*axis_asio_gpio*"}]}]} { + } + #------------- + validate_bd_design + save_bd_design + close_bd_design [current_bd_design] + } + + if {!$temp_only} { + TE::UTILS::te_msg TE_HW-7 WARNING "Exclude Board part: Remove Board part on Backup files permanently." + # ----------------------------------------------------------------- + #copy exported xdc fie + file copy -force ${pjc_xdc_path}/exclude_boardpart_io_loc.xdc ${TE::XDC_PATH}/_i_exclude_boardpart_io_loc.xdc + # ----------------------------------------------------------------- + #backup old block designs tcl files + set bd_folder ${TE::BD_PATH}/ + if {[file exists ${TE::BD_PATH}/${TE::SHORTDIR}/]} { + set bd_folder ${TE::BD_PATH}/${TE::SHORTDIR}/ + } + set bd_names [] + if { ![catch {set bd_names [glob -join -dir ${bd_folder}/ *.tcl]}] } { + foreach bd $bd_names { + if {![file exists ${bd}_backup]} { + TE::UTILS::te_msg TE_HW-8 STATUS "Exclude Board part: Write Backup file: ${bd}_backup" + file copy -force ${bd} ${bd}_backup + } + } + } + # ----------------------------------------------------------------- + #write new bd file + TE::hw_blockdesign_export_tcl + # ----------------------------------------------------------------- + # write new board_files. + set board_files "" + if { [catch {set board_files [ glob $TE::BOARDDEF_PATH/*board_files.csv ] }] } { + TE::UTILS::te_msg TE_HW-9 WARNING "Exclude Board part: Board Part CSV list not found. Create *board_file_mod.csv generation failed." + } else { + set fp [open "${board_files}" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + set newdata [] + #boardname:3 + foreach line $data { + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + lappend newdata $line + lappend newdata "#Attention:This is a modified Board part CSV files." + } elseif {[string match *#* $line] != 1 && [string length $line] > 7} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #split and replaced + set tmp [split $line ","] + set tmp [lreplace $tmp[set tmp {}] 3 3 NA] + set newstring "" + set first 1 + foreach el $tmp { + if {$first} { + set newstring "$el" + set first 0 + } else { + set newstring "$newstring,$el" + } + } + lappend newdata $newstring + } else { + lappend newdata $line + } + } + #write all list elements to file + set new_name [file tail $board_files] + set new_name [file rootname $new_name] + set board_files "$TE::BOARDDEF_PATH/${new_name}_mod.csv" + set fp_w [open ${board_files} "w"] + foreach line $newdata { + puts $fp_w $line + } + close $fp_w + } + #----------------------------------------------------------------- + } + TE::UTILS::te_msg TE_HW-10 INFO "Exclude Board Part is done." + } else { + TE::UTILS::te_msg TE_HW-11 WARNING "Exclude Board Part failed, Board Part is not specified." + } + } + #-------------------------------- + #--design_include_boarddef: + proc design_include_boarddef {} { + TE::UTILS::te_msg TE_HW-12 WARNING "Sorry design_include_boarddef currently not available." + } + + #-------------------------------- + #--import_hdl: + proc import_hdl {} { + # hidden function: official not supported + if {[file exists $TE::HDL_PATH]} { + TE::UTILS::te_msg TE_HW-13 INFO "Import HDL files." + set hdl_names [TE::UTILS::search_hdl_files] + add_files $hdl_names + if {[lsearch $hdl_names *${TE::VPROJ_NAME}_top.vhd*]==0} { + #vhdl + set_property top ${TE::VPROJ_NAME}_top [current_fileset] + #overwrite bd_import toplevel_settings + set TE::PR_TOPLEVELNAME ${TE::VPROJ_NAME}_top + TE::UTILS::te_msg TE_HW-14 INFO "Set TE::PR_TOPLEVELNAME:$TE::PR_TOPLEVELNAME" + } elseif {[lsearch $hdl_names *${TE::VPROJ_NAME}_top.v*]==0} { + #Verilog + set_property top ${TE::VPROJ_NAME}_top [current_fileset] + #overwrite bd_import toplevel_settings + set TE::PR_TOPLEVELNAME ${TE::VPROJ_NAME}_top + TE::UTILS::te_msg TE_HW-15 INFO "Set TE::PR_TOPLEVELNAME:$TE::PR_TOPLEVELNAME" + } + # set attributes + foreach hdl $hdl_names { + set hdl_name [file tail [file rootname $hdl]] + if {[string match "*_simonly_*" $hdl_name] } { + set_property used_in_synthesis false [get_files $hdl] + TE::UTILS::te_msg TE_HW-16 INFO "Set $hdl_name synthesis property to false." + } + if {[string match "*_synonly_*" $hdl_name] } { + set_property used_in_simulation false [get_files $hdl] + TE::UTILS::te_msg TE_HW-17 INFO "Set $hdl_name simulation property to false." + } + } + } + } + + #------------------------------------ + #--import_xci: import xci files + proc import_xci {} { + # hidden function: official not supported + if {[file exists $TE::HDL_PATH/xci]} { + TE::UTILS::te_msg TE_HW-18 INFO "Import XCI files." + set ip_names [TE::UTILS::search_xci_files] + import_ip -files $ip_names + catch {set ip_names [get_ips]} + foreach ip $ip_names { + ##ips without block design ips + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] } { + TE::UTILS::te_msg TE_HW-19 INFO "Run out of context IP for: $ip" + generate_target {instantiation_template} [get_files ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] + update_compile_order -fileset ${TE::SOURCE_NAME} + generate_target all [get_files ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] + if {[get_property generate_synth_checkpoint [get_files ${ip}.xci]] == 1 && [get_property is_enabled [get_files ${ip}.xci]] == 1} { + create_ip_run [get_files -of_objects [get_fileset ${TE::SOURCE_NAME}] ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] + launch_run -jobs $TE::RUNNING_JOBS ${ip}_synth_1 + } + } + } + foreach ip $ip_names { + ##ips without ips from block design + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] } { + if {[get_property generate_synth_checkpoint [get_files ${ip}.xci]] == 1 && [get_property is_enabled [get_files ${ip}.xci]] == 1} { + wait_on_run -timeout ${TE::TIMEOUT} ${ip}_synth_1 + } + } + } + } + } + #------------------------------------ + #--export_xci: export xci files + proc export_xci {} { + # hidden function: official not supported + set ip_names [list] + catch {set ip_names [get_ips]} + if {[llength $ip_names] > 0} { + file mkdir $TE::HDL_PATH/xci/${TE::SHORTDIR} + + set ip_report "" + foreach ip $ip_names { + ##ips without block design ips + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] } { + set ip_report "$ip_report \n $ip" + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci $TE::HDL_PATH/xci/${TE::SHORTDIR}/${ip}.xci + } + } + TE::UTILS::te_msg TE_HW-20 INFO "Export: \n \ + $ip_report \n \ + to folder $TE::HDL_PATH/xci/${TE::SHORTDIR}/ \n \ + ------" + } + } + # ------------------------------------------------------- + # finished advanced function + # ------------------------------------------------------- + # ------------------------------------------------------- + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project creation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #------------------------------------ + #--create_project: create vivado project, set board definition and ip path, set default vivado properties + proc create_project {} { + #set board part file definition path + TE::ENV::set_path_boarddef + #create vivado project + ::create_project -force $TE::VPROJ_NAME $TE::VPROJ_PATH + #set local ip path + TE::ENV::set_path_ip + #set vivado properties + set_vprops + + } + #------------------------------------ + #--open_project: open excisting vivado project and restore importent script variables with settings from project + proc open_project {} { + #set board part file definition path + TE::ENV::set_path_boarddef + #open vivado project + ::open_project ${TE::VPROJ_NAME}.xpr + #restore vivado properties to script variables + restore_scriptprops + } + #------------------------------------ + #--close_project: close excisting vivado project + proc close_project {} { + #close vivado project + ::close_project + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished creation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project property functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #------------------------------------ + #--set_vprops: + proc set_vprops {} { + #set std properties + set_property "default_lib" "xil_defaultlib" [current_project] + set_property "simulator_language" "Mixed" [current_project] + set_property "target_language" "VHDL" [current_project] + if {[info exists TE::PARTNAME]} { + if {![string match $TE::PARTNAME "NA"]} { + set_property "part" $TE::PARTNAME [current_project] + } + } + if {[info exists TE::BOARDPART]} { + if {![string match $TE::BOARDPART "NA"]} { + set_property "board_part" $TE::BOARDPART [current_project] + } + } + #---------------------------------------------------------- + #hidden function write settings + import_vivado_setting + #---------------------------------------------------------- + #overwrite xilinx defaults + set_property name $TE::SIM_NAME [get_filesets sim_1] + set_property name $TE::SYNTH_NAME [get_runs synth_1] + set_property name $TE::IMPL_NAME [get_runs impl_1] + set_property name $TE::CONST_NAME [get_filesets constrs_1] + #---------------------------------------------------------- + } + #------------------------------------ + #--restore_scriptprops: + proc restore_scriptprops {} { + set ID [get_property board_part [current_project]] + if {$ID ne ""} { + TE::INIT::init_board $ID 3 + } else { + TE::INIT::init_part_only [get_property part [current_project]] + } + #check bd file names for some additional functions + if {[catch {TE::INIT::check_bdtyp} result]} {TE::UTILS::te_msg TE_HW-21 Error "Script (TE::INIT::check_bdtyp) failed: $result."; return -code error} + #check board parts + if { ![string equal $TE::PARTNAME [get_property part [current_project]]] } { + TE::UTILS::te_msg TE_HW-22 {CRITICAL WARNING} "Current part name is set to [get_property part [current_project]], expect $TE::PARTNAME for board part definition file $TE::BOARDPART" + } + #check top level name + if { ![string equal $TE::PR_TOPLEVELNAME [get_property top [current_fileset]]] } { + TE::UTILS::te_msg TE_HW-23 WARNING "Current top level name is set to [get_property top [current_fileset]], expect $TE::PR_TOPLEVELNAME from default initialisation. Set TE::PR_TOPLEVELNAME to [get_property top [current_fileset]]." + set TE::PR_TOPLEVELNAME [get_property top [current_fileset]] + } + #---------------------------------------------------------- + #set run paths + set TE::SIM_NAME [get_property name [get_filesets sim*]] + set TE::SYNTH_NAME [get_property name [get_runs syn*]] + set TE::IMPL_NAME [get_property name [get_runs imp*]] + set TE::CONST_NAME [get_property name [get_filesets con*]] + + TE::UTILS::te_msg TE_HW-24 INFO "Restore project parameters:\n \ + TE::SIM_NAME: $TE::SIM_NAME \n \ + TE::SYNTH_NAME: $TE::SYNTH_NAME \n \ + TE::IMPL_NAME: $TE::IMPL_NAME \n \ + TE::CONST_NAME: $TE::CONST_NAME \n \ + ------" + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished project property functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project source functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--import_design: + proc import_design {} { + TE::UTILS::te_msg TE_HW-25 STATUS "Start import design" + #load backup constrains and block design + set xdc_files [TE::UTILS::search_xdc_files] + import_xdc $xdc_files + set_xdcsetting $xdc_files + import_blockdesign + import_hdl + import_xci + import_elf + } + #-------------------------------- + #--import_xdc: + proc import_xdc {xdc_files} { + set target_file "" + foreach xdc $xdc_files { + read_xdc $xdc + if {[file tail $xdc] eq "vivado_target.xdc"} { + set target_file $xdc + } + } + + set_property target_constrs_file $target_file [current_fileset -constrset] + } + #-------------------------------- + #--set_xdcsetting: + proc set_xdcsetting {xdc_files} { + #set xdc properties depending on xdc name: processing order an usage + foreach xdc_file $xdc_files { + if {[string match *_e_* $xdc_file] == 1} { + set_property PROCESSING_ORDER EARLY [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-26 STATUS "Set processing order early for $xdc_file" + } elseif {[string match *_l_* $xdc_file] == 1} { + set_property PROCESSING_ORDER LATE [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-27 STATUS "Set processing order late for $xdc_file" + } else { + set_property PROCESSING_ORDER NORMAL [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-28 STATUS "Set processing order normal for $xdc_file" + } + if {[string match *_s_* $xdc_file] == 1} { + set_property USED_IN_IMPLEMENTATION 0 [get_files $xdc_file] + set_property USED_IN_SYNTHESIS 1 [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-29 STATUS "Set use for synthesis only for $xdc_file" + } elseif {[string match *_i_* $xdc_file] == 1} { + set_property USED_IN_SYNTHESIS 0 [get_files $xdc_file] + set_property USED_IN_IMPLEMENTATION 1 [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-30 STATUS "Set use for implementation only for $xdc_file" + } else { + set_property USED_IN_SYNTHESIS 1 [get_files $xdc_file] + set_property USED_IN_IMPLEMENTATION 1 [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-31 STATUS "Set use for synthesis and implementation for $xdc_file" + } + } + } + #-------------------------------- + #--reload_blockdesign: delete all bd and load bd.tcl files from backup + proc reload_blockdesign {} { + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + } + foreach bd $bd_files { + TE::UTILS::te_msg TE_HW-32 STATUS "Remove:$bd" + remove_files $bd + set bd_dir [file dirname $bd] + file delete -force $bd_dir + } + import_blockdesign + } + #-------------------------------- + #--import_blockdesign: imports and compile bd designs for vivado + proc import_blockdesign {} { + #check bd filenames for some additional functions + if {[catch {TE::INIT::check_bdtyp} result]} {TE::UTILS::te_msg TE_HW-33 ERROR "Script (TE::INIT::check_bdtyp) failed: $result."; return -code error} + + set bd_files [TE::UTILS::search_bd_files] + if {[llength $bd_files]>0 } { + #run bd tcl + foreach bd $bd_files { + # + if {[file extension $bd] eq ".tcl"} { + source $bd + close_bd_design [get_bd_designs] + } + } + #compile bd + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + } + foreach bd $bd_files { + open_bd_design $bd + validate_bd_design -force + generate_target all [get_files $bd] + #check if hdf to exists + set bd_name [get_bd_designs] + set tl_name "NA" + if { [catch {set tl_name [glob -join -dir $TE::HDL_PATH/ ${TE::VPROJ_NAME}_top.*]}] & [catch {set tl_name [glob -join -dir $TE::HDL_PATH/${TE::SHORTDIR}/ ${TE::VPROJ_NAME}_top.*]}] } { + TE::UTILS::te_msg TE_HW-34 INFO "Generate top level wrapper" + make_wrapper -files [get_files $bd] -top + add_files -norecurse ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.vhd + } else { + TE::UTILS::te_msg TE_HW-35 INFO "Use custom HDL top level file" + } + close_bd_design [get_bd_designs $bd] + #todo: use more bd files -> currently its check on init function only one is allowed + } + update_compile_order -fileset ${TE::SOURCE_NAME} + update_compile_order -fileset ${TE::SIM_NAME} + } + } + #-------------------------------- + #--export_blockdesign: export bd designs to clear vivado folder (if folder ${TE::BD_PATH}/${TE::SHORTDIR} exist it will be export for this boardpart only) + #-- create pdf for each bd and sub hierarchy + proc export_blockdesign {{args ""}} { + #read args + set bd_folder ${TE::BD_PATH} + set no_mig "" + set valid_bd true + set this_boardpart_only false + set mod_tcl false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-no_mig_contents" {set no_mig [lindex $args $option]} + "-no_validate" {set valid_bd false} + "-mod_tcl" {set mod_tcl true} + "-board_part_only" {set this_boardpart_only true} + "" {} + default { TE::UTILS::te_msg TE_HW-36 {CRITICAL WARNING} "Unrecognised option [lindex $args $option]is ignored" } + } + } + if {$this_boardpart_only} { + file mkdir ${TE::BD_PATH}/${TE::SHORTDIR}/ + } + if {[file exists ${TE::BD_PATH}/${TE::SHORTDIR}/]} { + set bd_folder ${TE::BD_PATH}/${TE::SHORTDIR}/ + } + #search for open projects + set bd_open false + set bd_open_file "" + set bd_open_name "" + + if {[current_bd_design -quiet] ne ""} { + #save currend bd configuration + # validate_bd_design -force + save_bd_design + set bd_open true + set bd_open_name "[current_bd_design]" + TE::UTILS::te_msg TE_BD-2 INFO "$bd_open_name was saved." + set bd_open_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/${bd_open_name}/${bd_open_name}.bd + # close_bd_design [get_bd_designs $bd_open_file] + } + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + TE::UTILS::te_msg TE_BD-3 WARNING "No BD-File was found." + } + if {!$TE::BD_MULTI} { + if {[llength $bd_files]>1 } { + TE::UTILS::te_msg TE_BD-4 WARNING "Currently only one block design supported, deleted unused bd.tcl from ${bd_folder}." + } + } + + foreach bd $bd_files { + open_bd_design $bd + if {$valid_bd} { + TE::UTILS::te_msg TE_BD-5 INFO "Validate Design." + validate_bd_design + } else { + TE::UTILS::te_msg TE_BD-6 WARNING "Validate Design disabled." + } + } + set vivado_bd_design_name [] + if { [catch {set vivado_bd_design_name [get_bd_designs]}] } { + TE::UTILS::te_msg TE_BD-7 {CRITICAL WARNING} "Block designs was not found." + + } else { + + set txt "Stored Block Designs: \n " + foreach bd $vivado_bd_design_name { + # puts "-exclude Layout, IP-Version and MIG-content" + # write_bd_tcl -force -exclude_layout -no_ip_version -no_mig_contents ${bd_folder}/${bd}_bd.tcl + set bf_tcl_name ${bd_folder}/${bd}_bd.tcl + set txt "${txt} File: ${bf_tcl_name} \n" + if {$no_mig eq ""} { + write_bd_tcl -force ${bf_tcl_name} + } else { + set txt "${txt} -Option: Remove MIG-Contents \n" + write_bd_tcl -force $no_mig ${bf_tcl_name} + } + # modify bd + if {[catch {TE::UTILS::modify_block_design_tcl ${bf_tcl_name} ${mod_tcl}} result]} { TE::UTILS::te_msg TE_BD-8 ERROR "Script (TE::UTILS::modify_block_design_tcl) failed: $result."; return -code error} + #export blockdesign as pdf + #sel doc_path + set doc_path ${TE::DOC_PATH}/ + if {[file exists ${TE::BD_PATH}/${TE::SHORTDIR}/]} { + set doc_path ${TE::DOC_PATH}/${TE::SHORTDIR}/ + } + file mkdir ${doc_path}/ + #delete old bd_*.pdf + set old_pdfs [] + if { [catch {set old_pdfs [glob -join -dir ${doc_path}/ bd_*.pdf]}] } { + } else { + TE::UTILS::te_msg TE_BD-9 INFO "Delete old Block Design PDFs in ${doc_path}" + foreach old_pdf $old_pdfs { + if {[catch {file delete -force ${old_pdf}}]} { + TE::UTILS::te_msg TE_BD-10 WARNING "Delete ${old_pdf} failed." + } + } + } + set txt "${txt} -Option: Write PDF-Layouts \n" + set sname bd_${TE::VPROJ_NAME}_hier_top.pdf + if {[catch {write_bd_layout -force -format pdf -scope all -orientation landscape ${doc_path}/${sname}}]} { + TE::UTILS::te_msg TE_BD-11 WARNING "Write ${doc_path}/${sname} failed." + } + set allsubs [get_bd_cells -filter {TYPE == hier}] + foreach sub $allsubs { + set tmp [string map {"/" ""} [join $sub]] + set sname bd_${TE::VPROJ_NAME}_hier_${tmp}.pdf + if {[catch {write_bd_layout -force -format pdf -hierarchy [get_bd_cells $sub] -orientation landscape ${doc_path}/${sname}}]} { + TE::UTILS::te_msg TE_BD-12 WARNING "Write ${doc_path}/${sname} failed." + } + } + # save is needed because print subsystem mod bd file + save_bd_design + # + if { $bd ne $bd_open_name || !$bd_open} { + close_bd_design [get_bd_designs ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/${bd}/${bd}.bd] + } + } + TE::UTILS::te_msg TE_BD-13 INFO "$txt" + } + } + #-------------------------------- + #--import_elf: + proc import_elf {} { + if {[file exists $TE::FIRMWARE_PATH]} { + set elf_names [TE::UTILS::search_elf_files] + # set microblaze elf + foreach elf_f $elf_names { + add_files -norecurse $elf_f + set tmp [split $elf_f "/"] + set tmpLength [llength $tmp] + if {$tmpLength>2} { + set elf_file [lindex $tmp [expr $tmpLength-1]] + set m_name [lindex $tmp [expr $tmpLength-2]] + set f_obj "*${m_name}/${elf_file}" + #todo multi bd design + set bd_files [list] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + } + foreach bd $bd_files { + set bd_name [file tail [file rootname $bd]] + set_property SCOPED_TO_REF $bd_name [get_files -all -of_objects [get_fileset sources_1] ${f_obj}] + #mcs only used if name contains SYSCONTROL or MCS + if {[string match -nocase *SYSCONTROL* $m_name] || [string match -nocase *MCS* $m_name]} { + set_property SCOPED_TO_CELLS "${m_name}/U0/microblaze_I" [get_files -all -of_objects [get_fileset sources_1] ${f_obj}] + } else { + set_property SCOPED_TO_CELLS "${m_name}" [get_files -all -of_objects [get_fileset sources_1] ${f_obj}] + } + } + } + } + } + } + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished project source functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project new block design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--creat_new_blockdesign: create empty block design with zynq initialisation: fsys,msys,zsys,zusys + proc create_new_blockdesign {{type fsys} {msys_conf {local_mem "8KB" ecc "None" cache "None" debug_module "Debug Only" axi_periph "Enabled" axi_intc "0" clk "None"}}} { + #check other bd files exists, currently only one is supported with this function + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + create_bd_design $type + if {$type eq "fsys"} { + TE::UTILS::te_msg TE_BD-14 INFO "For fsys Block Design is currently no additional initialisation intended." + } elseif {$type eq "zusys"} { + create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynq_ultra_ps_e_0 + apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" } [get_bd_cells zynq_ultra_ps_e_0] + + set tcl_ext [] + if { [catch {set tcl_ext [glob -join -dir ${TE::BOARDDEF_PATH}/carrier_extension/ *_preset.tcl]}] } { + } + foreach carrier_ext $tcl_ext { + TE::UTILS::te_msg TE_BD-15 INFO "Import carrier_settings from:[file tail $carrier_ext]." + source $carrier_ext + } + } elseif {$type eq "zsys"} { + create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7 processing_system7_0 + apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] + set tcl_ext [] + if { [catch {set tcl_ext [glob -join -dir ${TE::BOARDDEF_PATH}/carrier_extension/ *_preset.tcl]}] } { + } + foreach carrier_ext $tcl_ext { + TE::UTILS::te_msg TE_BD-16 INFO "Import carrier_settings from:[file tail $carrier_ext]." + source $carrier_ext + } + } elseif {$type eq "msys"} { + create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze microblaze_0 + #set test {local_mem "8KB" ecc "None" cache "None" debug_module "Debug Only" axi_periph "Enabled" axi_intc "0" clk "None"} + apply_bd_automation -rule xilinx.com:bd_rule:microblaze -config $msys_conf [get_bd_cells microblaze_0] + } else { + TE::UTILS::te_msg TE_BD-17 {CRITICAL WARNING} "Unknown Block-Design Type. No Type specific initialisation is done." + } + } else { + TE::UTILS::te_msg TE_BD-18 ERROR "Currently TE-Scripts supports only one Block-Design. Generation is cancelled." + return -code error + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished new block design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project build functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--build_design: + proc build_design {{bitgen true} {mcsgen true} {reportgen true} {hdfgen true}} { + if {[catch {run_synth} result]} {TE::UTILS::te_msg TE_HW-37 ERROR "Script (TE::VIV::run_synth) failed: $result."; return -code error} + if {[catch {run_impl} result]} {TE::UTILS::te_msg TE_HW-38 ERROR "Script (TE::VIV::run_impl) failed: $result."; return -code error} + if {$bitgen} { + if {[catch {write_viv_bitfile} result]} {TE::UTILS::te_msg TE_HW-39 ERROR "Script (TE::VIV::write_viv_bitfile) failed: $result."; return -code error} + } else { + #delete old one if exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit} result]} {TE::UTILS::te_msg TE_HW-40 WARNING "$result"} + } + TE::UTILS::te_msg TE_HW-41 WARNING "Bit-file generation is disabled on build design run." + } + if {$mcsgen} { + if {[catch {write_viv_cfgmem} result]} {TE::UTILS::te_msg TE_HW-42 ERROR "Script (TE::VIV::write_viv_cfgmem) failed: $result."; return -code error} + } else { + #delete old one if exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs} result]} {TE::UTILS::te_msg TE_HW-43 WARNING "$result"} + } + TE::UTILS::te_msg TE_HW-44 WARNING "MCS-file generation is disabled on build design run" + } + if {$reportgen} { + if {[catch {report_design} result]} {TE::UTILS::te_msg TE_HW-45 ERROR "Script (TE::VIV::report_design) failed: $result."; return -code error} + } else { + #delete old one if exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt} result]} {TE::UTILS::te_msg TE_HW-46 WARNING "$result"} + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt} result]} {TE::UTILS::te_msg TE_HW-47 WARNING "$result"} + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv} result]} {TE::UTILS::te_msg TE_HW-48 WARNING "$result"} + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc} result]} {TE::UTILS::te_msg TE_HW-49 WARNING "$result"} + } + TE::UTILS::te_msg TE_HW-50 WARNING "Report-files generation is disabled on build design run." + } + if {$hdfgen} { + #is done automatically with bitgen -> *.sysdef + } else { + #delete old one if exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef} result]} {TE::UTILS::te_msg TE_HW-51 WARNING "$result"} + } + TE::UTILS::te_msg TE_HW-52 WARNING "HDF-files generation is disabled on build design run." + } + } + #-------------------------------- + #--run_synth: + proc run_synth {} { + #syntheses + reset_run $TE::SYNTH_NAME + launch_runs $TE::SYNTH_NAME -jobs $TE::RUNNING_JOBS + wait_on_run -timeout $TE::TIMEOUT $TE::SYNTH_NAME + } + #-------------------------------- + #--run_impl: + proc run_impl {} { + #implementation and bitgen + reset_run $TE::IMPL_NAME + # launch_runs $TE::IMPL_NAME + launch_runs $TE::IMPL_NAME -to_step route_design -jobs $TE::RUNNING_JOBS + wait_on_run -timeout $TE::TIMEOUT $TE::IMPL_NAME + } + #-------------------------------- + #--write_viv_bitfile: + proc write_viv_bitfile {} { + launch_runs $TE::IMPL_NAME -to_step write_bitstream -jobs $TE::RUNNING_JOBS + wait_on_run -timeout $TE::TIMEOUT $TE::IMPL_NAME + } + #-------------------------------- + #--write_viv_cfgmem: + proc write_viv_cfgmem {} { + #used only if bd name is no zynq design (without processor system)! + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs]} { file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs } + if {!$TE::IS_ZSYS && !$TE::IS_ZUSYS} { + if {$TE::CFGMEM_MEMSIZE_MB ne "NA"} { + #check supported from *board_files.csv + #write mcs with *board_files.csv settings + if {[catch { write_cfgmem -force -format mcs -interface $TE::CFGMEM_IF -size $TE::CFGMEM_MEMSIZE_MB \ + -loadbit "up 0x0 ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit" \ + -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs\ + }]} { + #if failed try SPIX1 (default ) (faster than open design) + TE::UTILS::te_msg TE_HW-53 INFO "Generate MCS failed with $TE::CFGMEM_IF from *board_files.csv specification, try to generate SPIx1." + if {[catch { write_cfgmem -force -format mcs -interface SPIX1 -size $TE::CFGMEM_MEMSIZE_MB \ + -loadbit "up 0x0 ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit" \ + -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs\ + }]} { + #if failed get propery from design (needs some time) + TE::UTILS::te_msg TE_HW-54 INFO "Generate MCS failed with SPIx1, try to get information from implemented Design." + open_run $TE::IMPL_NAME + set tmp_cfgmem_if "SPIx[get_property BITSTREAM.CONFIG.SPI_BUSWIDTH [current_design]]" + close_design + write_cfgmem -force -format mcs -interface $tmp_cfgmem_if -size $TE::CFGMEM_MEMSIZE_MB \ + -loadbit "up 0x0 ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit" \ + -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs + TE::UTILS::te_msg TE_HW-55 INFO "Generate MCS with $tmp_cfgmem_if from current design setting (BITSTREAM.CONFIG.SPI_BUSWIDTH), but current Board Part supports $TE::CFGMEM_IF" + } else { + TE::UTILS::te_msg TE_HW-56 INFO "Generate MCS with SPIX1 (BITSTREAM.CONFIG.SPI_BUSWIDTH 1) from Bitfile, but current Board Part supports $TE::CFGMEM_IF also!" + } + } + } else { + TE::UTILS::te_msg TE_HW-57 {CRITICAL WARNING} "FPGAFLASHTYP Mem Size in MB is not specified in *.board_files.csv. *.mcs file is not generated." + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished built functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # report functions (todo to utilities) + # ----------------------------------------------------------------------------------------------------------------------------------------- + + #-------------------------------- + #--report_design: + proc report_design {} { + #-------------check toplevel name (if modified) + if { ![string equal $TE::PR_TOPLEVELNAME [get_property top [current_fileset]]] } { + TE::UTILS::te_msg TE_HW-58 INFO "Top Level Name ([get_property top [current_fileset]]) is not same then exspected from BD-File delivery ($TE::PR_TOPLEVELNAME). [get_property top [current_fileset]] is used in Script settings now." + set TE::PR_TOPLEVELNAME [get_property top [current_fileset]] + } + #-------------block design reports + #-------------synthese reports + #-------------implement reports + open_run $TE::IMPL_NAME + + #todo: + # report_debug_core -file ${TE::VPROJ_NAME}_debug_cores.txt + report_ip_status -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt + report_io -force -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt -format text + write_csv -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv + write_xdc -force -mode port ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc + + report_summary + close_design + } + #-------------------------------- + #--report_run: + proc report_run {} { + #todo eventuell auftrennen und dann noch report schreiben, wenn nicht alles durch geht + set date "[ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"]" + set status "Error" + set founderror -1 + #synth + set sythn_counts [extract_synth_summary] + set sythn_counts_split [split $sythn_counts ","] + set value [lindex $sythn_counts_split [expr [llength $sythn_counts_split]-1]] + if {$value != 0} {set founderror 1} + #impl + set impl_counts [extract_impl_summary] + set impl_counts_split [split $impl_counts ","] + set value [lindex $impl_counts_split [expr [llength $impl_counts_split]-1]] + if {$value != 0} {set founderror 1} + #drc + set drc_counts [extract_drc_summary] + set drc_counts_split [split $drc_counts ","] + set value [lindex $drc_counts_split [expr [llength $drc_counts_split]-1]] + if {$value != 0} {set founderror 1} + #timing + set timing_counts [extract_timing_summary] + set timing_counts_split [split $timing_counts ","] + set value [lindex $timing_counts_split [expr [llength $timing_counts_split]-1]] + if {[string compare "NA" $value ]==0} {set founderror 0} elseif {$value != 0} {set founderror 1} + if {$founderror == -1} {set status "Ok"} elseif {$founderror == 0} {set status "Ok(NA)"} + #write report + set report "[format "%-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s," "$date" "$status" "$TE::VPROJ_NAME" "$TE::SHORTDIR" "$TE::BOARDPART" "$TE::SYNTH_NAME" "$TE::IMPL_NAME" "[lindex $sythn_counts_split 0]" "[lindex $sythn_counts_split 1]" "[lindex $sythn_counts_split 2]" "[lindex $sythn_counts_split 3]" "[lindex $impl_counts_split 0]" "[lindex $impl_counts_split 1]" "[lindex $impl_counts_split 2]" "[lindex $impl_counts_split 3]" "[lindex $drc_counts_split 0]" "[lindex $drc_counts_split 1]" "[lindex $timing_counts_split 0]" "[lindex $timing_counts_split 1]" "[lindex $timing_counts_split 2]"]" + return $report + } + #-------------------------------- + #--report_summary: + proc report_summary {} { + set fp_w [open ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}_summary.csv "w"] + #write header + puts $fp_w [format "%-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s," "Date" "Status" "ProjName" "BoardDefShortName" "BoardDefName" "SynthName" "ImplName" "SynthInfo" "SynthWarnings" "SynthCritWarnings" "SynthError" "ImplInfo" "ImplWarnings" "ImplCritWarnings" "ImplError" "ImplDRCWarnings" "ImplDRCError" "ImplTimingWNS" "ImplTimingFaildEndpoints" "ImplTimingTNS"] + + puts $fp_w [report_run] + close $fp_w + } + #-------------------------------- + #--extract_synth_summary: + proc extract_synth_summary {} { + set synth_returns "0,0,0,FileNotFound" + + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::SYNTH_NAME}/${TE::PR_TOPLEVELNAME}.vds + if { ![file exists ${report_file}]} {return $synth_returns} + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + + foreach line $data { + if {[string match "*Infos*Warnings*Critical Warnings*Errors encountered*" $line]} { + set tmp [string map {"and" "," " " "" "Infos" "" "Warnings" "" "Critical" "" "Errors" "" "encountered." ""} "$line"] + #use only last log output + #return Infos, Warnings, Critical Warnings , Errors + set synth_returns $tmp + } + } + return $synth_returns + } + #-------------------------------- + #--extract_impl_summary: + proc extract_impl_summary {} { + set impl_returns "0,0,0,FileNotFound" + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.vdi + if { ![file exists ${report_file}]} {return $impl_returns} + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + + foreach line $data { + if {[string match "*Infos*Warnings*Critical Warnings*Errors encountered*" $line]} { + set tmp [string map {"and" "," " " "" "Infos" "" "Warnings" "" "Critical" "" "Errors" "" "encountered." ""} "$line"] + #use only last log output + #return Infos, Warnings, Critical Warnings , Errors + set impl_returns $tmp + } + } + return $impl_returns + } + #-------------------------------- + #--extract_drc_summary: + proc extract_drc_summary {} { + set drc_returns "0,FileNotFound" + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.vdi + if { ![file exists ${report_file}]} {return $drc_returns} + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + set err_count 0 + set warn_count 0 + + foreach line $data { + if {[string match "*DRC finished with*" $line]} { + set index [string first "with" $line 0] + set tmp [string range $line $index [string length $line]] + set tmp [string map {" " "" "with" "" "Errors" "" "Warnings" "" "Advisories" ""} "$tmp"] + set tmp [split $tmp ","] + if {[llength $tmp]==1} { + if {[string is integer [lindex $tmp 0]]} { + set err_count [expr $err_count + [lindex $tmp 0]] + } else { + set err_count 999999 + } + } else { + if {[string is integer [lindex $tmp 0]]} { + set err_count [expr $err_count + [lindex $tmp 0]] + } else { + set err_count 999999 + } + if {[string is integer [lindex $tmp 1]]} { + set warn_count [expr $warn_count + [lindex $tmp 1]] + } else { + set warn_count 999999 + } + } + } + } + #return Warnings, Errors + set drc_returns "$warn_count, $err_count" + return $drc_returns + } + #-------------------------------- + #--extract_timing_summary: + proc extract_timing_summary {} { + set timing_returns "0,0,FileNotFound" + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}_timing_summary_routed.rpt + if { ![file exists ${report_file}]} {return $timing_returns} + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + + set lineindex -1 + foreach line $data { + incr lineindex + if {[string match "*Design Timing Summary*" $line]} { + break; + } + } + set lineindex [expr $lineindex +6] + set tmp [join [lindex $data $lineindex] " "] + set timing_returns "[lindex $tmp 0],[lindex $tmp 2],[lindex $tmp 1]" + #return WNS, Faild Endpoints, TNS + return $timing_returns + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + namespace eval VLAB { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # vlab project functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + #-------------------------------- + #--create_project: + proc create_project {} { + #create vivado lab project + ::create_project -force $TE::VPROJ_NAME $TE::VLABPROJ_PATH + #set props.. + } + #-------------------------------- + #--open_project: + proc open_project {} { + #open vivado lab project + ::open_project ${TE::VPROJ_NAME}.lpr + } + #-------------------------------- + #--close_project: + proc close_project {} { + #close vivado project + ::close_project + } + #-------------------------------- + #--hw_open_jtag: + proc hw_open_jtag {} { + + #start new session + ::open_hw + if {[current_hw_server -quiet] eq ""} { + ::connect_hw_server + } + if {[current_hw_device -quiet] eq ""} { + ::open_hw_target + return true + } else { + return false + } + } + #-------------------------------- + #--hw_close_jtag: + proc hw_close_jtag {} { + ::close_hw + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished vlab project functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # device functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--hw_create_flash_device: + proc hw_create_flash_device {{fname ""}} { + #todo configs auswählbar + set partname_int "" + set flashtyp_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set id "[TE::BDEF::find_id $fname]" + set tmp [TE::BDEF::get_fpgaflashtyp $id 0] + set tmp [split $tmp "|"] + if {[llength $tmp] eq 3} { + set flashtyp_int [lindex $tmp 0] + } else { + set flashtyp_int $tmp + } + + } else { + set partname_int $TE::PARTNAME + set flashtyp_int $TE::FPGAFLASHTYP + } + set hw_fpga_name [hw_get_fpga $partname_int] + set_property PROBES.FILE "" $hw_fpga_name + #reset old propefiles + create_hw_cfgmem -hw_device $hw_fpga_name -mem_dev [lindex [get_cfgmem_parts ${flashtyp_int}] 0] + set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.VERIFY 0 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if {[catch {refresh_hw_device $hw_fpga_name}] } {} + } + #-------------------------------- + #--hw_get_fpga: + proc hw_get_fpga {{partname ""}} { + set partname_int $partname + if {$partname_int eq ""} {set partname_int $TE::PARTNAME} + set hw_fpga_name NA + set hw_fpga_found false + + foreach hwd [get_hw_devices] { + set name [lindex [split $hwd "_"] 0] + set hw_fpga_found [string match *$name* $partname_int] + if {$hw_fpga_found} {set hw_fpga_name $hwd;break;} + } + if {$hw_fpga_found} { + # ::refresh_hw_device $hw_fpga_name + } else { + # change compared name from automotive and defence grade fpga (has same hw-id than commercial) + set alt_partname [string map {xa xc xq xc} $partname_int] + foreach hwd [get_hw_devices] { + set name [lindex [split $hwd "_"] 0] + set hw_fpga_found [string match *$name* $alt_partname] + if {$hw_fpga_found} {set hw_fpga_name $hwd;break;} + } + if {$hw_fpga_found} { + # ::refresh_hw_device $hw_fpga_name + } else { + set rpt_txt "$partname_int Device not found. \n" + foreach hwd [get_hw_devices] { + set name [lindex [split $hwd "_"] 0] + set rpt_txt "$rpt_txt $partname_int and $alt_partname compare with *$name* failed. \n" + } + TE::UTILS::te_msg TE_PR-0 WARNING "$rpt_txt" + } + } + return $hw_fpga_name + } + #-------------------------------- + #--hw_fpga_boot_from_memory: + proc hw_fpga_boot_from_memory {{fname ""}} { + set partname_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + } else { + set partname_int $TE::PARTNAME + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$hw_fpga_name ne "NA"} { + ::boot_hw_device $hw_fpga_name + TE::UTILS::te_msg TE_PR-1 INFO "Reboot Device is done." + ::refresh_hw_device $hw_fpga_name + TE::UTILS::te_msg TE_PR-2 INFO "Reboot Device is done." + } else { + TE::UTILS::te_msg TE_PR-3 ERROR "Boot from Memory failed. Device not found." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished device functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # property functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--hw_set_bit_and_ltx_files: setup for bitfile configuration via labtools/vivado + proc hw_set_bit_and_ltx_files {use_basefolder app_name {fname ""}} { + set return_filename "" + set partname_int "" + set shortdir_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set shortdir_int "[TE::BDEF::find_shortdir $fname]" + } else { + set partname_int $TE::PARTNAME + set shortdir_int $TE::SHORTDIR + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$hw_fpga_name ne "NA"} { + if {$use_basefolder} { + set bitfilename "" + if { ![catch {set bitfilename [glob -join -dir ${TE::BASEFOLDER}/ *.bit]}] } { + TE::UTILS::te_msg TE_PR-4 INFO "Used file:${bitfilename}" + set return_filename ${bitfilename} + set_property PROGRAM.FILE ${bitfilename} $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-5 ERROR "Bitfile not found in ${TE::BASEFOLDER}. Nothing is done." + return -code error + } + } else { + if {$app_name eq "" || $app_name eq "NA"} { + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit]} { + #use bitfile from hardware folder (with bootloop for microblaze systems) + set_property PROGRAM.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit $hw_fpga_name + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-6 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-7 INFO "Used file:${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit" + set return_filename ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit + } else { + #use default bit from hardware folder (with bootloop for microblaze systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit]} { + set_property PROGRAM.FILE ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit $hw_fpga_name + if {[file exists ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-8 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-9 INFO "Used file:${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit" + set return_filename ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit + } else { + TE::UTILS::te_msg TE_PR-10 ERROR "${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit not found. Nothing is done." + return -code error + } + } + } else { + #use bitfile from bootimage folder (with programmed apps for microblaze systems) + set bitfilename "" + if { ![catch {set bitfilename [glob -join -dir ${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/ *.bit]}] } { + set_property PROGRAM.FILE ${bitfilename} $hw_fpga_name + #search in hardware folder for ltx + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-11 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-12 INFO "Used file:${bitfilename}" + set return_filename ${bitfilename} + } else { + TE::UTILS::te_msg TE_PR-13 ERROR "${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/*.bit not found. Nothing is done." + return -code error + } + } + } + } else { + TE::UTILS::te_msg TE_PR-14 ERROR "Program FPGA failed. Device not found." + return -code error + } + return $return_filename + } + #-------------------------------- + #--hw_set_bin_and_ltx_files: setup for binfile configuration via labtools/vivado + proc hw_set_bin_and_ltx_files {use_basefolder app_name fname} { + set return_filename "" + set partname_int "" + set shortdir_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set shortdir_int "[TE::BDEF::find_shortdir $fname]" + } else { + set partname_int $TE::PARTNAME + set shortdir_int $TE::SHORTDIR + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$hw_fpga_name ne "NA"} { + if {$use_basefolder} { + set binfilename "" + set ltxfilename "" + if { ![catch {set binfilename [glob -join -dir ${TE::BASEFOLDER}/ *.bin]}] } { + TE::UTILS::te_msg TE_PR-15 INFO "Used file:${binfilename}" + set return_filename ${binfilename} + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${binfilename}" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if { ![catch {set ltxfilename [glob -join -dir ${TE::BASEFOLDER}/ *.ltx]}] } { + set_property PROBES.FILE ${ltxfilename} $hw_fpga_name + } else { + set_property PROBES.FILE "" $hw_fpga_name + } + } else { + TE::UTILS::te_msg TE_PR-16 {CRITICAL WARNING} "Bin file not found in ${TE::BASEFOLDER}. Nothing is done." + return -code error + } + } else { + set binfilename "" + if { ![catch {set binfilename [glob -join -dir ${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/ *.bin]}] } { + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${binfilename}" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-17 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-18 INFO "Used file: ${binfilename}" + set return_filename ${binfilename} + } else { + TE::UTILS::te_msg TE_PR-19 ERROR "${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/*.bin not found. Nothing is done." + return -code error + } + } + } else { + TE::UTILS::te_msg TE_PR-20 ERROR "Program FPGA failed. Device not found." + return -code error + } + return $return_filename + } + #-------------------------------- + #--hw_set_mcs_and_ltx_files: setup for mcsfile configuration via labtools/vivado + proc hw_set_mcs_and_ltx_files {use_basefolder term app_name fname} { + set return_filename "" + set partname_int "" + set shortdir_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set shortdir_int "[TE::BDEF::find_shortdir $fname]" + } else { + set partname_int $TE::PARTNAME + set shortdir_int $TE::SHORTDIR + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$hw_fpga_name ne "NA"} { + if {$use_basefolder} { + set mcsfilename "" + set ltxfilename "" + if { ![catch {set mcsfilename [glob -join -dir ${TE::BASEFOLDER}/ *.mcs]}] } { + TE::UTILS::te_msg TE_PR-21 INFO "Used file:${mcsfilename}" + set return_filename ${mcsfilename} + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${mcsfilename}" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.UNUSED_PIN_TERMINATION ${term} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if { ![catch {set ltxfilename [glob -join -dir ${TE::BASEFOLDER}/ *.ltx]}] } { + set_property PROBES.FILE ${ltxfilename} $hw_fpga_name + } else { + set_property PROBES.FILE "" $hw_fpga_name + } + } else { + TE::UTILS::te_msg TE_PR-22 ERROR "MCS-file not found in ${TE::BASEFOLDER}. Nothing is done." + return -code error + } + } else { + if {$app_name eq "" || $app_name eq "NA"} { + #use mcs from hardware folder (with bootloop for microblaze systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs]} { + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.UNUSED_PIN_TERMINATION ${term} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-23 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-24 INFO "Used file:${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs" + set return_filename ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs + } else { + TE::UTILS::te_msg TE_PR-25 ERROR "${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs not found. Nothing is done" + return -code error + } + } else { + #use mcs from bootimage folder (with configured app for microblaze systems) + set mcsfilename "" + if { ![catch {set mcsfilename [glob -join -dir ${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/ *.mcs]}] } { + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${mcsfilename}" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.UNUSED_PIN_TERMINATION ${term} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + #search ltx from hardware folder + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-26 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-27 INFO "Used file:${mcsfilename}" + set return_filename ${mcsfilename} + } else { + TE::UTILS::te_msg TE_PR-28 ERROR "${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/*.mcs not found. Nothing is done." + return -code error + } + } + } + } else { + TE::UTILS::te_msg TE_PR-29 ERROR "Program FPGA failed. Device not found." + return -code error + } + return $return_filename + } + + #-------------------------------- + #--hw_reload_prope_file_device: + proc hw_reload_prope_file_device {{fname ""}} { + set partname_int "" + set shortdir_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set shortdir_int "[TE::BDEF::find_shortdir $fname]" + } else { + set partname_int $TE::PARTNAME + set shortdir_int $TE::SHORTDIR + } + set hw_fpga_name [hw_get_fpga $partname_int] + + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + TE::UTILS::te_msg TE_PR-30 INFO "New Probes file is set: ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx" + + } else { + TE::UTILS::te_msg TE_PR-31 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished property functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--hw_program_fpga_device: + proc hw_program_fpga_device { use_basefolder appname {fname ""}} { + #bitfile + set return_filename "" + set partname_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + } else { + set partname_int $TE::PARTNAME + } + set hw_fpga_name [hw_get_fpga $partname_int] + + if {![catch {set return_filename [hw_set_bit_and_ltx_files $use_basefolder $appname $fname]}] } { + program_hw_devices $hw_fpga_name + TE::UTILS::te_msg TE_PR-32 INFO "Programming BIT-file finished." + if {[catch {refresh_hw_device $hw_fpga_name}] } {} + } else { + TE::UTILS::te_msg TE_PR-33 ERROR "Program FPGA failed." + return -code error + } + return $return_filename + } + #-------------------------------- + #--hw_program_fpga_flash: + proc hw_program_fpga_flash {use_basefolder term bin appname {fname ""}} { + set return_filename "" + set partname_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + } else { + set partname_int $TE::PARTNAME + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$bin eq "bin"} { + #program bin file + if {![catch {set return_filename [hw_set_bin_and_ltx_files $use_basefolder $appname $fname]}] } { + program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + TE::UTILS::te_msg TE_PR-34 INFO "Programming BIN-file finished." + if {[catch {refresh_hw_device $hw_fpga_name}] } {} + } else { + TE::UTILS::te_msg TE_PR-35 ERROR "Program Flash failed." + return -code error + } + } else { + #program mcs file + if {![catch {set return_filename [hw_set_mcs_and_ltx_files $use_basefolder $term $appname $fname]}] } { + if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE $hw_fpga_name] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM $hw_fpga_name]]]] } { create_hw_bitstream -hw_device $hw_fpga_name [get_property PROGRAM.HW_CFGMEM_BITFILE $hw_fpga_name]; program_hw_devices $hw_fpga_name; }; + program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + TE::UTILS::te_msg TE_PR-36 INFO "Programming MCS-file finished." + if {[catch {refresh_hw_device $hw_fpga_name}] } {} + } else { + TE::UTILS::te_msg TE_PR-37 ERROR "Program Flash failed." + return -code error + } + } + return $return_filename + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + + puts "INFO:(TE) Load Vivado script finished" +} + + diff --git a/zynqberrydemo1/settings/project_settings.tcl b/zynqberrydemo1/settings/project_settings.tcl new file mode 100644 index 0000000..777dc02 --- /dev/null +++ b/zynqberrydemo1/settings/project_settings.tcl @@ -0,0 +1,2 @@ +set_property flow {Vivado Implementation 2017} [get_runs ${TE::IMPL_NAME}] +set_property strategy Performance_Explore [get_runs ${TE::IMPL_NAME}] diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/data/zynq_fsbl.tcl b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/data/zynq_fsbl.tcl new file mode 100644 index 0000000..e072f6f --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/data/zynq_fsbl.tcl @@ -0,0 +1,97 @@ +proc swapp_get_name {} { + return "Zynq FSBL - TE modified"; +} + +proc swapp_get_description {} { + return "First Stage Bootloader (FSBL) for Zynq. The FSBL configures the FPGA with HW bit stream (if it exists) \ + and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the \ + non-volatile memory (NAND/NOR/QSPI) to RAM (DDR) and starts executing it. It supports multiple partitions, \ + and each partition can be a code image or a bit stream.\ + TE-Modification: Modified HDMI Output DMA and Camera Input DMA on fsbl_hooks.c. Add. vdma.h, vdma.c\ + FSBL Template: 2017.1 \ + "; +} + +proc swapp_get_supported_processors {} { + return "ps7_cortexa9"; +} + +proc swapp_get_supported_os {} { + return "standalone"; +} + +proc check_standalone_os {} { + set oslist [hsi::get_os]; + + if { [llength $oslist] != 1 } { + return 0; + } + set os [lindex $oslist 0]; + + if { $os != "standalone" } { + error "This application is supported only on the Standalone Board Support Package."; + } +} + +proc swapp_is_supported_sw {} { + # make sure we are using standalone OS + #check_standalone_os; + + # make sure xilffs and xilrsa libraries are available + + set librarylist_1 [hsi::get_libs -filter "NAME==xilffs"]; + + + if { [llength $librarylist_1] == 0 } { + error "This application requires xilffs library in the Board Support Package."; + } +} + +proc swapp_is_supported_hw {} { + + # check processor type + set proc_instance [hsi::get_sw_processor]; + set hw_processor [common::get_property HW_INSTANCE $proc_instance] + + set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]]; + + if { $proc_type != "ps7_cortexa9" } { + error "This application is supported only for CortexA9 processors."; + } + + return 1; +} + + +proc get_stdout {} { + set os [hsi::get_os]; + set stdout [common::get_property CONFIG.STDOUT $os]; + return $stdout; +} + +proc check_stdout_hw {} { + set p7_uarts [hsi::get_cells -hier -filter "IP_NAME=ps7_uart"]; +} + +proc swapp_generate {} { + # generate/copy ps init files + ::hsi::utils::generate_psinit + + #delete unnecessary files (only ps7_init.c & ps7_init.h are needed for FSBL) + + set files(0) "ps7_init.html" + set files(1) "ps7_init.tcl" + set files(2) "ps7_init_gpl.c" + set files(3) "ps7_init_gpl.h" + + foreach init_file [array get files] { + file delete -force $init_file + } + +} + +proc swapp_get_linker_constraints {} { + + # don't generate a linker script. fsbl has its own linker script + return "lscript no"; +} diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl.h new file mode 100644 index 0000000..a0cf67b --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl.h @@ -0,0 +1,546 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file fsbl.h +* +* Contains the function prototypes, defines and macros for the +* First Stage Boot Loader (FSBL) functionality +* +* 

    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a	jz	03/04/11	Initial release
+* 2.00a	mb 	06/06/12	Removed the qspi define, will be picked from
+*						xparameters.h file
+* 3.00a np/mb 08/08/12	Added the error codes for the FSBL hook errors.
+* 						Added the debug levels
+* 4.00a sgd 02/28/13	Removed DDR initialization check
+*                       Removed DDR ECC initialization code
+*						Modified hand off address check to 1MB
+*						Added RSA authentication support
+*						Removed LPBK_DLY_ADJ register setting code as we use
+* 					 	divisor 8
+*						Removed check for Fabric is already initialized
+*
+* 						CR's fixed and description
+* 						689026:	FSBL doesn't hold PL resets active during
+* 						bit download
+* 						Resolution: PL resets are released just before
+* 						handoff
+*
+* 						689077:	FSBL hangs at Handoff clearing the
+* 						TX UART buffer
+*						Resolution: STDOUT_BASEADDRESS macro value changes
+*						based UART select, hence used STDOUT_BASEADDRESS
+*						as UART base address
+*
+* 						695578: FSBL failed to load standalone application
+* 						in secure bootmode
+*               		Resolution: Application will be placed at load address
+*               		instead of DDR temporary address
+*
+*               		699475: FSBL functionality is broken and its
+*               		not able to boot in QSPI/NAND bootmode
+*               		Resolution: New flags are added DevCfg driver
+*               		for handling loopback
+*               		XDCFG_CONCURRENT_NONSEC_READ_WRITE
+*                       XDCFG_CONCURRENT_SECURE_READ_WRITE
+*
+*               		683145: Define stack area for FIQ, UNDEF modes
+*               		in linker file
+*               		Resolution: FSBL linker modified to create stack area
+*               		for FIQ, UNDEF
+*                       
+*                       705664: FSBL fails to decrypt the bitstream when 
+*                       the image is AES encrypted using non-zero key value
+*                       Resolution: Fabric cleaning will not be done
+*                       for AES-E-Fuse encryption
+*                       
+*                       Watchdog disabled for AES E-Fuse encryption
+*
+* 5.00a sgd 05/17/13    Fallback support for E-Fuse encryption
+*                       Added QSPI Flash Size > 128Mbit support
+* 					    QSPI Dual Stack support
+* 					    Added Md5 checksum support
+*
+*                       CR's fixed and description
+*                       692045	FSBL: Linker script of FSBL has PHDR workaround,
+* 					    this needs to be fixed
+* 					    Resolution: Removed PHDR from Linker file
+*                       
+*                       704287	FSBL: fsbl.h file has a few error codes that 
+*                       are not used by FSBL, that needs to be removed
+*                       Resolution: Removed unused error codes
+*
+*                       704379	FSBL: Check if DDR is in proper state before
+*                       handoff
+* 					    Resolution: Added DDR initialization check
+* 					                           
+*                       709077	If FSBL_DEBUG and FSBL_DEBUG_INFO are defined, 
+*                       the debug level is FSBL_DEBUG only.
+*                       
+*                       710128 FSBL: Linux boot failing without load attribute
+*                       set for Linux partitions in BIF
+*                       Resolution: FSBL will load partitions with valid load
+*                       address and stop loading if any invalid load address
+*
+*                       708728 Issues seen while making HP interconnect
+*                       32 bit wide
+*                       Resolution: ps7_post_config function generated by PCW
+*                       will be called after Bit stream download
+*                       Added MMC support
+* 6.00a	kc	07/31/2013	CR's fixed and description
+* 						724166 FSBL doesn’t use PPK authenticated by Boot ROM
+* 						 for authenticating the Partition images
+* 						Resolution: FSBL now uses the PPK left by Boot ROM in
+* 						OCM for authencating the SPK
+*
+* 						724165 Partition Header used by FSBL is not
+* 						authenticated
+* 						Resolution: FSBL now authenticates the partition header
+*
+* 						691150 ps7_init does not check for peripheral
+* 						initialization failures or timeout on polls
+* 						Resolution: Return value of ps7_init() is now checked
+* 						by FSBL and prints the error string
+*
+* 						708316  PS7_init.tcl file should have Error mechanism
+* 						for all mask_poll
+* 						Resolution: Return value of ps7_init() is now checked
+* 						by FSBL and prints the error string
+*
+* 						732062 FSBL fails to build if UART not available
+* 						Resolution: Added define to call xil_printf only
+* 						if uart is defined
+*
+* 						722979 Provide customer-friendly changelogs in FSBL
+* 						Resolution: Added CR description for all the files
+*
+* 						732865 Backward compatibility for ps7_init function
+*						Resolution: Added a new define for ps7_init success
+*						and value is defined based on ps7_init define
+*
+*						Fix for CR#739711 - FSBL not able to read Large
+*						QSPI (512M) in IO Mode
+*						Resolution: Modified the address calculation
+*						algorithm in dual parallel mode for QSPI
+*
+* 7.00a kc  10/18/13    Integrated SD/MMC driver
+*			10/23/13	Support for armcc compiler added
+*						741003 FSBL has to check the HMAC error status after 
+*						decryption
+*						Resolution: Added code for checking the error status 
+*						after PCAP completion
+*						739968 FSBL should do the QSPI config settings for 
+*						Dual parallel configuration in IO mode
+*						Resolution: Added QSPI config settings in qspi.c
+*						724620 FSBL: How to handle PCAP_MODE after bitstream 
+*						configuration.
+*						Resolution: PCAP_MODE and PCAP_PR bits are now cleared  
+* 						after PCAP transfer completion
+*						726178 In the 14.6 FSBL function FabricInit() PROG_B 
+*						is kept active for 5mS.
+*						Resolution: PROG_B is now kept active for 5mS only incase 
+*						if efuse is the aes key source.
+*						755245 FSBL does not load partition if eMMC has only 
+*						one partition
+*						Resolution: Changed the if condition for MMC
+*			12/04/13    764382 FSBL: How to handle PCAP_MODE after bitstream 
+*						configuration
+*						Resolution: Reverted back the changes of 724620. PCAP_MODE
+*						and PCAP_PR bits are not changed
+* 8.00a kc  01/16/13    767798 Fsbl MD5 Checksum failiure for encrypted images
+* 						Resolution: For checksum enabled partitions, total 
+*						total partition image length is copied now.
+*						761895 FSBL should authenticate image only if
+*						partition owner was not set to u-boot
+*						Resolution: Partition owner check added in 
+*						image_mover.c
+* 			02/20/14	775631 - FSBL: FsblGetGlobalTimer() is not proper
+*						Resolution: Function argument is updated from value
+*						to pointer to reflect updated value
+* 9.00a kc  04/16/14	773866 - SetPpk() will fail on secure fallback
+*						unless FSBL* and FSBL are identical in length
+*						Resolution: PPK is set only once now.
+*						785778 - FSBL takes 8 seconds to
+* 						authenticate (RSA) a bitstream on zc706
+* 						Resolution: Data Caches are enabled only for
+* 						authentication.
+* 						791245 - Use of xilrsa in fsbl
+* 						Resolution: Rsa library is removed from fsbl source
+* 						and xilrsa is used from BSP
+* 10.00a kc 07/15/14	804595 Zynq FSBL - Issues with
+* 						fallback image offset handling using MD5
+* 						Resolution: Updated the checksum offset to add with
+* 						image base address
+* 						782309 Fallback support for AES
+* 						encryption with E-Fuse - Enhancement
+* 						Resolution: Same as 773866
+* 						809336 Minor code cleanup
+* 						Resolution Minor code changes
+*        kc 08/27/14	820356 - FSBL compilation fails with IAR compiler
+* 						Resolution: Change of __asm__ to __asm
+* 11.00a kv 10/08/14	826030 - FSBL:LinearBootDeviceFlag is not initialized
+*						in IO mode case.Due to which the variable is
+*						remaining in unknown state.
+*						Resolution: LinearBootDeviceFlag is initialized 0
+*						in main.c
+* 12.00a ssc 12/11/14	839182 - FSBL -In the file sd.c, f_mount is called with
+*                       two arguments but f_mount is expecting the 3 arguments
+*                       from build 2015.1_1210_1, causing compilation error.
+*						Resolution: Arguments for f_mount in InitSD() are
+*						changed as per new signature.
+* 13.00a ssc 04/10/15	846899 - FSBL -In the file pcap.c, to clear DMA done
+*                       count, devcfg.INT_STS register is written to, which is
+*                       not correct.
+*                       Resolution: Corresponding fields in the devcfg.STATUS
+*                       register are written to, for clearing DMA done count.
+* 14.00a gan 01/13/16   869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
+*						read command from LQSPI_CFG register instead of hard
+*		   				coded read command (0x6B).
+* 15.00a gan 07/21/16   953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
+* 						Fabric Initialization sequence is modified to check
+* 						the PL power before sequence starts and checking INIT_B
+* 						reset status twice in case of failure.
+* 16.00a gan 08/02/16   Fix for CR# 955897 -(2016.3)FSBL -
+* 						In pcap.c, check pl power through MCTRL register
+* 						for 3.0 and later versions of silicon.
+*
    +* +* +* +* @note +* +* Flags in FSBL +* +* FSBL_PERF +* +* This Flag can be set at compilation time. This flag is set for +* measuring the performance of FSBL.That is the time taken to execute is +* measured.when this flag is set.Execution time with reference to +* global timer is taken here +* +* Total Execution time is the time taken for executing FSBL till handoff +* to any application . +* If there is a bitstream in the partition header then the +* execution time includes the copying of the bitstream to DDR +* (in case of SD/NAND bootmode) +* and programming the devcfg dma is accounted. +* +* FSBL provides two debug levels +* DEBUG GENERAL - fsbl_printf under this category will appear only when the +* FSBL_DEBUG flag is set during compilation +* DEBUG_INFO - fsbl_printf under this category will appear when the +* FSBL_DEBUG_INFO flag is set during compilation +* For a more detailed output log can be used. +* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in +* RSA functions +* These macros are input to the fsbl_printf function +* +* DEBUG LEVELS +* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints +* that are with the DEBUG_GENERAL argument are shown +* FSBL_DEBUG_INFO is level 2, when this flag is set during the +* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port +* +* DEFAULT LEVEL +* By default no print messages will appear. +* +* NON_PS_INSTANTIATED_BITSTREAM +* +* FSBL will not enable the level shifters for a NON PS instantiated +* Bitstream.This flag can be set during compilation for a NON PS instantiated +* bitstream +* +* ECC_ENABLE +* This flag will be defined in the ps7_init.h file when ECC is enabled +* in the DDR configuration (XPS GUI) +* +* RSA_SUPPORT +* This flag is used to enable authentication feature +* Default this macro disabled, reason to avoid increase in code size +* +* MMC_SUPPORT +* This flag is used to enable MMC support feature +* +*******************************************************************************/ +#ifndef XIL_FSBL_H +#define XIL_FSBL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xparameters.h" +#include "xpseudo_asm.h" +#include "xil_printf.h" +#include "pcap.h" +#include "fsbl_debug.h" +#include "ps7_init.h" +#ifdef FSBL_PERF +#include "xtime_l.h" +#include +#endif + + +/************************** Constant Definitions *****************************/ +/* + * SDK release version + */ +#define SDK_RELEASE_YEAR 2017 +#define SDK_RELEASE_QUARTER 1 + +#define WORD_LENGTH_SHIFT 2 + +/* + * On a Successful handoff to an application FSBL sets this SUCCESS code + */ +#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */ + +/* + * Backward compatibility for ps7_init + */ +#ifdef NEW_PS7_ERR_CODE +#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS +#else +#define FSBL_PS7_INIT_SUCCESS (1) +#endif + +/* + * ERROR CODES + * The following are the Error codes that FSBL uses + * If the Debug prints are enabled only then the error codes will be + * seen on the com port.Without the debug prints enabled no error codes will + * be visible.There are not saved in any register + * Boot Mode States used for error and status output + * Error codes are defined below + */ +#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */ +#define ILLEGAL_RETURN 0xA001 /**< Illegal return */ +#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */ +#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */ +#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */ +#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */ +#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */ +#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */ +#define NO_DDR 0xA008 /**< DDR missing */ +#define SD_INIT_FAIL 0xA009 /**< SD Init fail */ +#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */ +#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */ +#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */ +#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */ +#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */ +#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */ +#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */ +#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */ +#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */ +/* + * FSBL Exception error codes + */ +#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */ +#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */ +#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */ +#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */ +#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */ +#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */ + +/* + * FSBL hook routine failures + */ +#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */ +#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream + download hook failed */ +#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream + download hook failed */ + +/* + * Watchdog related Error codes + */ +#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */ +#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */ + +/* + * SLCR Registers + */ +#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200) +#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240) +#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250) +#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254) +#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258) +#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C) +#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900) + +/* + * Efuse Status Register + */ +#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */ +#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */ + +/* + * PS reset control register define + */ +#define PS_RST_MASK 0x1 /**< PS software reset */ + +/* + * SLCR BOOT Mode Register defines + */ +#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */ + +/* + * Boot Modes + */ +#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */ +#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */ +#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */ +#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */ +#define SD_MODE 0x00000005 /**< SD Boot Mode */ +#define MMC_MODE 0x00000006 /**< MMC Boot Device */ + +#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */ +#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */ + +/* + * Golden image offset + */ +#define GOLDEN_IMAGE_OFFSET 0x8000 + +/* + * Silicon Version + */ +#define SILICON_VERSION_1 0 +#define SILICON_VERSION_2 1 +#define SILICON_VERSION_3 2 +#define SILICON_VERSION_3_1 3 + +/* + * DDR start address for storing the data temporarily(1M) + * Need to finalize correct logic + */ +#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR +#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR +#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR +#else +/* + * In case of PL DDR, this macros defined based PL DDR address + */ +#define DDR_START_ADDR 0x00 +#define DDR_END_ADDR 0x00 +#endif + +#define DDR_TEMP_START_ADDR DDR_START_ADDR +/* + * DDR test pattern + */ +#define DDR_TEST_PATTERN 0xAA55AA55 +#define DDR_TEST_OFFSET 0x100000 +/* + * + */ +#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/ +#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/ +#define NAND_FLASH_SIZE 0x8000000; /*128MB*/ +#define NOR_FLASH_SIZE 0x2000000; /*32MB*/ +#define LQSPI_CFG_OFFSET 0xA0 +#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000 + +/* + * These are the SLCR lock and unlock macros + */ +#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D) +#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B) + +#define IMAGE_HEADER_CHECKSUM_COUNT 10 + +/* Boot ROM Image defines */ +#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */ +#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */ +#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */ +#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */ +#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */ +#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */ +#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */ +#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */ +#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */ +#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */ +#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */ +#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */ + +/* Reboot status register defines: + * 0xF0000000 for FSBL fallback mask to notify Boot Rom + * 0x60000000 for FSBL to mark that FSBL has not handoff yet + * 0x00FFFFFF for user application to use across soft reset + */ +#define FSBL_FAIL_MASK 0xF0000000 +#define FSBL_IN_MASK 0x60000000 + +/* The address that holds the base address for the image Boot ROM found */ +#define BASEADDR_HOLDER 0xFFFFFFF8 + +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ + +void OutputStatus(u32 State); +void FsblFallback(void); + +int FsblSetNextPartition(int Num); +void *(memcpy_rom)(void * s1, const void * s2, u32 n); +char *strcpy_rom(char *Dest, const char *Src); + +void ClearFSBLIn(void); +void MarkFSBLIn(void); +void FsblHandoff(u32 FsblStartAddr); +u32 GetResetReason(void); + +#ifdef FSBL_PERF +void FsblGetGlobalTime (XTime * tCur); +void FsblMeasurePerfTime (XTime tCur, XTime tEnd); +#endif +void GetSiliconVersion(void); +void FsblHandoffExit(u32 FsblStartAddr); +void FsblHandoffJtagExit(); +/************************** Variable Definitions *****************************/ +extern int SkipPartition; + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_debug.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_debug.h new file mode 100644 index 0000000..2c41c23 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_debug.h @@ -0,0 +1,82 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file fsbl_debug.h +* +* This file contains the debug verbose information for FSBL print functionality +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a mb	01/09/12 Initial release
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef _FSBL_DEBUG_H +#define _FSBL_DEBUG_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define DEBUG_GENERAL 0x00000001 /* general debug messages */ +#define DEBUG_INFO 0x00000002 /* More debug information */ + +#if defined (FSBL_DEBUG_INFO) +#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL)) +#elif defined (FSBL_DEBUG) +#define fsbl_dbg_current_types (DEBUG_GENERAL) +#else +#define fsbl_dbg_current_types 0 +#endif + +#ifdef STDOUT_BASEADDRESS +#define fsbl_printf(type,...) \ + if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); } +#else +#define fsbl_printf(type, ...) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _FSBL_DEBUG_H */ diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c new file mode 100644 index 0000000..851d11d --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c @@ -0,0 +1,206 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/***************************************************************************** +* +* @file fsbl_hooks.c +* +* This file provides functions that serve as user hooks. The user can add the +* additional functionality required into these routines. This would help retain +* the normal FSBL flow unchanged. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date        Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a np   08/03/12 Initial release
+*
    +* +* @note +* +******************************************************************************/ + + +#include "fsbl.h" +#include "xstatus.h" +#include "fsbl_hooks.h" + +#include "vdma.h" +#include "xparameters.h" +#include "xil_hal.h" +#include "sleep.h" + +#include "xvtc.h" + +#define ENABLE_CAMERA +#define DIRECT_CAMERA_VIEW + +#ifdef DIRECT_CAMERA_VIEW +#define HDMI_FB_ADDR 0x1FC00000 +#define CAMERA_FB_ADDR 0x1FC00000 +#endif + +#ifndef DIRECT_CAMERA_VIEW +#define HDMI_FB_ADDR 0x1FC00000 +#define CAMERA_FB_ADDR 0x1F700000 +#endif +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + + +/****************************************************************************** +* This function is the hook which will be called before the bitstream download. +* The user can add all the customized code required to be executed before the +* bitstream download to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 FsblHookBeforeBitstreamDload(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + /* + * User logic to be added here. Errors to be stored in the status variable + * and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n"); + + return (Status); +} + +/****************************************************************************** +* This function is the hook which will be called after the bitstream download. +* The user can add all the customized code required to be executed after the +* bitstream download to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 FsblHookAfterBitstreamDload(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n"); + + return (Status); +} + +/****************************************************************************** +* This function is the hook which will be called before the FSBL does a handoff +* to the application. The user can add all the customized code required to be +* executed before the handoff to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 FsblHookBeforeHandoff(void) +{ + u32 Status; + + Status = XST_SUCCESS; + XVtc Vtc; + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n"); + + xil_printf("FSBL: Enabling VTC..\n\r"); + XVtc_Config *Config; + Config = XVtc_LookupConfig(XPAR_VTC_0_DEVICE_ID); + if (NULL == Config) { + xil_printf("XVtc_LookupConfig failure\r\n"); + return XST_FAILURE; + } + + Status = XVtc_CfgInitialize(&Vtc, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("XVtc_CfgInitialize failure\r\n"); + return XST_FAILURE; + } + + XVtc_DisableSync(&Vtc); + XVtc_EnableGenerator(&Vtc); + + xil_printf("FSBL: Enabling Out VDMA at 0x%08x..\n\r",HDMI_FB_ADDR); + vdma_out_init(XPAR_VIDEO_OUT_AXI_VDMA_0_DEVICE_ID, HDMI_FB_ADDR, 1280, 720, 4); +#ifdef ENABLE_CAMERA + xil_printf("FSBL: Enabling In VDMA at 0x%08x..\n\r",CAMERA_FB_ADDR); + vdma_in_init(XPAR_VIDEO_IN_AXI_VDMA_0_DEVICE_ID, CAMERA_FB_ADDR, 1280, 720, 4); +#endif + return (Status); +} + + +/****************************************************************************** +* This function is the hook which will be called in case FSBL fall back +* +* @param None +* +* @return None +* +****************************************************************************/ +void FsblHookFallback(void) +{ + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n"); + while(1); +} + + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h new file mode 100644 index 0000000..784f7ed --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file fsbl_hooks.h +* +* Contains the function prototypes, defines and macros required by fsbl_hooks.c +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a	np/mb	10/08/12	Initial release
+*				Corrected the prototype
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef FSBL_HOOKS_H_ +#define FSBL_HOOKS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "fsbl.h" + + +/************************** Function Prototypes ******************************/ + +/* FSBL hook function which is called before bitstream download */ +u32 FsblHookBeforeBitstreamDload(void); + +/* FSBL hook function which is called after bitstream download */ +u32 FsblHookAfterBitstreamDload(void); + +/* FSBL hook function which is called before handoff to the application */ +u32 FsblHookBeforeHandoff(void); + +/* FSBL hook function which is called in FSBL fallback */ +void FsblHookFallback(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/image_mover.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/image_mover.c new file mode 100644 index 0000000..1bad673 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/image_mover.c @@ -0,0 +1,1335 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file image_mover.c +* +* Move partitions to either DDR to execute or to program FPGA. +* It performs partition walk. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz	05/24/11	Initial release
+* 2.00a jz	06/30/11	Updated partition header defs for 64-byte
+*			 			alignment change in data2mem tool
+* 2.00a mb	05/25/12	Updated for standalone based bsp FSBL
+* 			 			Nand/SD encryption and review comments
+* 3.00a np	08/30/12	Added FSBL user hook calls
+* 						(before and after bitstream download.)
+* 4.00a sgd	02/28/13	Fix for CR#691148 Secure bootmode error in devcfg test
+*						Fix for CR#695578 FSBL failed to load standalone 
+*						application in secure bootmode
+*
+* 4.00a sgd	04/23/13	Fix for CR#710128 FSBL failed to load standalone 
+*						application in secure bootmode
+* 5.00a kc	07/30/13	Fix for CR#724165 Partition Header used by FSBL 
+*						is not authenticated
+* 						Fix for CR#724166 FSBL doesn�t use PPK authenticated 
+*						by Boot ROM for authenticating the Partition images 
+* 						Fix for CR#732062 FSBL fails to build if UART not 
+*						available 
+* 7.00a kc  10/30/13    Fix for CR#755245 FSBL does not load partition
+*                       if eMMC has only one partition
+* 8.00a kc  01/16/13    Fix for CR#767798  FSBL MD5 Checksum failure
+* 						for encrypted images
+*						Fix for CR#761895 FSBL should authenticate image
+*						only if partition owner was not set to u-boot
+* 9.00a kc  04/16/14    Fix for CR#785778  FSBL takes 8 seconds to 
+* 						authenticate (RSA) a bitstream on zc706
+* 10.00a kc 07/15/14	Fix for CR#804595 Zynq FSBL - Issues with
+* 						fallback image offset handling using MD5
+* 						Fix for PR#782309 Fallback support for AES
+* 						encryption with E-Fuse - Enhancement
+*
+*
    +* +* @note +* A partition is either an executable or a bitstream to program FPGA +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "fsbl.h" +#include "image_mover.h" +#include "xil_printf.h" +#include "xreg_cortexa9.h" +#include "pcap.h" +#include "fsbl_hooks.h" +#include "md5.h" + +#ifdef XPAR_XWDTPS_0_BASEADDR +#include "xwdtps.h" +#endif + +#ifdef RSA_SUPPORT +#include "rsa.h" +#include "xil_cache.h" +#endif +/************************** Constant Definitions *****************************/ + +/* We are 32-bit machine */ +#define MAXIMUM_IMAGE_WORD_LEN 0x40000000 +#define MD5_CHECKSUM_SIZE 16 + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset); +u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum); +u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum); + +/************************** Variable Definitions *****************************/ +/* + * Partition information flags + */ +u8 EncryptedPartitionFlag; +u8 PLPartitionFlag; +u8 PSPartitionFlag; +u8 SignedPartitionFlag; +u8 PartitionChecksumFlag; +u8 BitstreamFlag; +u8 ApplicationFlag; + +u32 ExecutionAddress; +ImageMoverType MoveImage; + +/* + * Header array + */ +PartHeader PartitionHeader[MAX_PARTITION_NUMBER]; +u32 PartitionCount; +u32 FsblLength; + +#ifdef XPAR_XWDTPS_0_BASEADDR +extern XWdtPs Watchdog; /* Instance of WatchDog Timer */ +#endif + +extern u32 Silicon_Version; +extern u32 FlashReadBaseAddress; +extern u8 LinearBootDeviceFlag; +extern XDcfg *DcfgInstPtr; + +/*****************************************************************************/ +/** +* +* This function +* +* @param +* +* @return +* +* +* @note None +* +****************************************************************************/ +u32 LoadBootImage(void) +{ + u32 RebootStatusRegister = 0; + u32 MultiBootReg = 0; + u32 ImageStartAddress = 0; + u32 PartitionNum; + u32 PartitionDataLength; + u32 PartitionImageLength; + u32 PartitionTotalSize; + u32 PartitionExecAddr; + u32 PartitionAttr; + u32 ExecAddress = 0; + u32 PartitionLoadAddr; + u32 PartitionStartAddr; + u32 PartitionChecksumOffset; + u8 ExecAddrFlag = 0 ; + u32 Status; + PartHeader *HeaderPtr; + u32 EfuseStatusRegValue; +#ifdef RSA_SUPPORT + u32 HeaderSize; +#endif + /* + * Resetting the Flags + */ + BitstreamFlag = 0; + ApplicationFlag = 0; + + RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG); + fsbl_printf(DEBUG_INFO, + "Reboot status register: 0x%08lx\r\n",RebootStatusRegister); + + if (Silicon_Version == SILICON_VERSION_1) { + /* + * Clear out fallback mask from previous run + * We start from the first partition again + */ + if ((RebootStatusRegister & FSBL_FAIL_MASK) == + FSBL_FAIL_MASK) { + fsbl_printf(DEBUG_INFO, + "Reboot status shows previous run falls back\r\n"); + RebootStatusRegister &= ~(FSBL_FAIL_MASK); + Xil_Out32(REBOOT_STATUS_REG, RebootStatusRegister); + } + + /* + * Read the image start address + */ + ImageStartAddress = *(u32 *)BASEADDR_HOLDER; + } else { + /* + * read the multiboot register + */ + MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET); + + fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08lx\r\n",MultiBootReg); + + /* + * Compute the image start address + */ + ImageStartAddress = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK) + * GOLDEN_IMAGE_OFFSET; + } + + fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08lx\r\n",ImageStartAddress); + + /* + * Get partitions header information + */ + Status = GetPartitionHeaderInfo(ImageStartAddress); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Partition Header Load Failed\r\n"); + OutputStatus(GET_HEADER_INFO_FAIL); + FsblFallback(); + } + + /* + * RSA is not implemented in 1.0 and 2.0 + * silicon + */ + if ((Silicon_Version != SILICON_VERSION_1) && + (Silicon_Version != SILICON_VERSION_2)) { + /* + * Read Efuse Status Register + */ + EfuseStatusRegValue = Xil_In32(EFUSE_STATUS_REG); + if (EfuseStatusRegValue & EFUSE_STATUS_RSA_ENABLE_MASK) { + fsbl_printf(DEBUG_GENERAL,"RSA enabled for Chip\r\n"); +#ifdef RSA_SUPPORT + /* + * Set the Ppk + */ + SetPpk(); + + /* + * Read partition header with signature + */ + Status = GetImageHeaderAndSignature(ImageStartAddress, + (u32 *)DDR_TEMP_START_ADDR); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, + "Read Partition Header signature Failed\r\n"); + OutputStatus(GET_HEADER_INFO_FAIL); + FsblFallback(); + } + HeaderSize=TOTAL_HEADER_SIZE+RSA_SIGNATURE_SIZE; + + Status = AuthenticatePartition((u8 *)DDR_TEMP_START_ADDR, HeaderSize); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, + "Partition Header signature Failed\r\n"); + OutputStatus(GET_HEADER_INFO_FAIL); + FsblFallback(); + } +#else + /* + * In case user not enabled RSA authentication feature + */ + fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n"); + OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL); + FsblFallback(); +#endif + } + } + +#ifdef MMC_SUPPORT + /* + * In case of MMC support + * boot image preset in MMC will not have FSBL partition + */ + PartitionNum = 0; +#else + /* + * First partition header was ignored by FSBL + * As it contain FSBL partition information + */ + PartitionNum = 1; +#endif + + while (PartitionNum < PartitionCount) { + + fsbl_printf(DEBUG_INFO, "Partition Number: %lu\r\n", PartitionNum); + + HeaderPtr = &PartitionHeader[PartitionNum]; + + /* + * Print partition header information + */ + HeaderDump(HeaderPtr); + + /* + * Validate partition header + */ + Status = ValidateHeader(HeaderPtr); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "INVALID_HEADER_FAIL\r\n"); + OutputStatus(INVALID_HEADER_FAIL); + FsblFallback(); + } + + /* + * Load partition header information in to local variables + */ + PartitionDataLength = HeaderPtr->DataWordLen; + PartitionImageLength = HeaderPtr->ImageWordLen; + PartitionExecAddr = HeaderPtr->ExecAddr; + PartitionAttr = HeaderPtr->PartitionAttr; + PartitionLoadAddr = HeaderPtr->LoadAddr; + PartitionChecksumOffset = HeaderPtr->CheckSumOffset; + PartitionStartAddr = HeaderPtr->PartitionStart; + PartitionTotalSize = HeaderPtr->PartitionWordLen; + + /* + * Partition owner should be FSBL to validate the partition + */ + if ((PartitionAttr & ATTRIBUTE_PARTITION_OWNER_MASK) != + ATTRIBUTE_PARTITION_OWNER_FSBL) { + /* + * if FSBL is not the owner of partition, + * skip this partition, continue with next partition + */ + fsbl_printf(DEBUG_INFO, "Skipping partition %0lx\r\n", + PartitionNum); + /* + * Increment partition number + */ + PartitionNum++; + continue; + } + + if (PartitionAttr & ATTRIBUTE_PL_IMAGE_MASK) { + fsbl_printf(DEBUG_INFO, "Bitstream\r\n"); + PLPartitionFlag = 1; + PSPartitionFlag = 0; + BitstreamFlag = 1; + if (ApplicationFlag == 1) { +#ifdef STDOUT_BASEADDRESS + xil_printf("\r\nFSBL Warning !!!" + "Bitstream not loaded into PL\r\n"); + xil_printf("Partition order invalid\r\n"); +#endif + break; + } + } + + if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) { + fsbl_printf(DEBUG_INFO, "Application\r\n"); + PSPartitionFlag = 1; + PLPartitionFlag = 0; + ApplicationFlag = 1; + } + + /* + * Encrypted partition will have different value + * for Image length and data length + */ + if (PartitionDataLength != PartitionImageLength) { + fsbl_printf(DEBUG_INFO, "Encrypted\r\n"); + EncryptedPartitionFlag = 1; + } else { + EncryptedPartitionFlag = 0; + } + + /* + * Check for partition checksum check + */ + if (PartitionAttr & ATTRIBUTE_CHECKSUM_TYPE_MASK) { + PartitionChecksumFlag = 1; + } else { + PartitionChecksumFlag = 0; + } + + /* + * RSA signature check + */ + if (PartitionAttr & ATTRIBUTE_RSA_PRESENT_MASK) { + fsbl_printf(DEBUG_INFO, "RSA Signed\r\n"); + SignedPartitionFlag = 1; + } else { + SignedPartitionFlag = 0; + } + + /* + * Load address check + * Loop will break when PS load address zero and partition is + * un-signed or un-encrypted + */ + if ((PSPartitionFlag == 1) && (PartitionLoadAddr < DDR_START_ADDR)) { + if ((PartitionLoadAddr == 0) && + (!((SignedPartitionFlag == 1) || + (EncryptedPartitionFlag == 1)))) { + break; + } else { + fsbl_printf(DEBUG_GENERAL, + "INVALID_LOAD_ADDRESS_FAIL\r\n"); + OutputStatus(INVALID_LOAD_ADDRESS_FAIL); + FsblFallback(); + } + } + + if (PSPartitionFlag && (PartitionLoadAddr > DDR_END_ADDR)) { + fsbl_printf(DEBUG_GENERAL, + "INVALID_LOAD_ADDRESS_FAIL\r\n"); + OutputStatus(INVALID_LOAD_ADDRESS_FAIL); + FsblFallback(); + } + + /* + * Load execution address of first PS partition + */ + if (PSPartitionFlag && (!ExecAddrFlag)) { + ExecAddrFlag++; + ExecAddress = PartitionExecAddr; + } + + /* + * FSBL user hook call before bitstream download + */ + if (PLPartitionFlag) { + Status = FsblHookBeforeBitstreamDload(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAIL\r\n"); + OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL); + FsblFallback(); + } + } + + /* + * Move partitions from boot device + */ + Status = PartitionMove(ImageStartAddress, HeaderPtr); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"PARTITION_MOVE_FAIL\r\n"); + OutputStatus(PARTITION_MOVE_FAIL); + FsblFallback(); + } + + if ((SignedPartitionFlag) || (PartitionChecksumFlag)) { + if(PLPartitionFlag) { + /* + * PL partition loaded in to DDR temporary address + * for authentication and checksum verification + */ + PartitionStartAddr = DDR_TEMP_START_ADDR; + } else { + PartitionStartAddr = PartitionLoadAddr; + } + + if (PartitionChecksumFlag) { + /* + * Validate the partition data with checksum + */ + Status = ValidateParition(PartitionStartAddr, + (PartitionTotalSize << WORD_LENGTH_SHIFT), + ImageStartAddress + + (PartitionChecksumOffset << WORD_LENGTH_SHIFT)); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"PARTITION_CHECKSUM_FAIL\r\n"); + OutputStatus(PARTITION_CHECKSUM_FAIL); + FsblFallback(); + } + + fsbl_printf(DEBUG_INFO, "Partition Validation Done\r\n"); + } + + /* + * Authentication Partition + */ + if (SignedPartitionFlag == 1 ) { +#ifdef RSA_SUPPORT + Xil_DCacheEnable(); + Status = AuthenticatePartition((u8*)PartitionStartAddr, + (PartitionTotalSize << WORD_LENGTH_SHIFT)); + if (Status != XST_SUCCESS) { + Xil_DCacheFlush(); + Xil_DCacheDisable(); + fsbl_printf(DEBUG_GENERAL,"AUTHENTICATION_FAIL\r\n"); + OutputStatus(AUTHENTICATION_FAIL); + FsblFallback(); + } + fsbl_printf(DEBUG_INFO,"Authentication Done\r\n"); + Xil_DCacheFlush(); + Xil_DCacheDisable(); +#else + /* + * In case user not enabled RSA authentication feature + */ + fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n"); + OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL); + FsblFallback(); +#endif + } + + /* + * Decrypt PS partition + */ + if (EncryptedPartitionFlag && PSPartitionFlag) { + Status = DecryptPartition(PartitionStartAddr, + PartitionDataLength, + PartitionImageLength); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"DECRYPTION_FAIL\r\n"); + OutputStatus(DECRYPTION_FAIL); + FsblFallback(); + } + } + + /* + * Load Signed PL partition in Fabric + */ + if (PLPartitionFlag) { + Status = PcapLoadPartition((u32*)PartitionStartAddr, + (u32*)PartitionLoadAddr, + PartitionImageLength, + PartitionDataLength, + EncryptedPartitionFlag); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"BITSTREAM_DOWNLOAD_FAIL\r\n"); + OutputStatus(BITSTREAM_DOWNLOAD_FAIL); + FsblFallback(); + } + } + } + + + /* + * FSBL user hook call after bitstream download + */ + if (PLPartitionFlag) { + Status = FsblHookAfterBitstreamDload(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"FSBL_AFTER_BSTREAM_HOOK_FAIL\r\n"); + OutputStatus(FSBL_AFTER_BSTREAM_HOOK_FAIL); + FsblFallback(); + } + } + /* + * Increment partition number + */ + PartitionNum++; + } + + return ExecAddress; +} + +/*****************************************************************************/ +/** +* +* This function loads all partition header information in global array +* +* @param ImageAddress is the start address of the image +* +* @return - XST_SUCCESS if Get partition Header information successful +* - XST_FAILURE if Get Partition Header information failed +* +* @note None +* +****************************************************************************/ +u32 GetPartitionHeaderInfo(u32 ImageBaseAddress) +{ + u32 PartitionHeaderOffset; + u32 Status; + + + /* + * Get the length of the FSBL from BootHeader + */ + Status = GetFsblLength(ImageBaseAddress, &FsblLength); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n"); + return XST_FAILURE; + } + + /* + * Get the start address of the partition header table + */ + Status = GetPartitionHeaderStartAddr(ImageBaseAddress, + &PartitionHeaderOffset); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n"); + return XST_FAILURE; + } + + /* + * Header offset on flash + */ + PartitionHeaderOffset += ImageBaseAddress; + + fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08lx\r\n", + PartitionHeaderOffset); + + /* + * Load all partitions header data in to global variable + */ + Status = LoadPartitionsHeaderInfo(PartitionHeaderOffset, + &PartitionHeader[0]); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Header Information Load Failed\r\n"); + return XST_FAILURE; + } + + /* + * Get partitions count from partitions header information + */ + PartitionCount = GetPartitionCount(&PartitionHeader[0]); + + fsbl_printf(DEBUG_INFO, "Partition Count: %lu\r\n", PartitionCount); + + /* + * Partition Count check + */ + if (PartitionCount >= MAX_PARTITION_NUMBER) { + fsbl_printf(DEBUG_GENERAL, "Invalid Partition Count\r\n"); + return XST_FAILURE; +#ifndef MMC_SUPPORT + } else if (PartitionCount <= 1) { + fsbl_printf(DEBUG_GENERAL, "There is no partition to load\r\n"); + return XST_FAILURE; +#endif + } + + return XST_SUCCESS; +} + + +/*****************************************************************************/ +/** +* +* This function goes to the partition header of the specified partition +* +* @param ImageAddress is the start address of the image +* +* @return Offset Partition header address of the image +* +* @return - XST_SUCCESS if Get Partition Header start address successful +* - XST_FAILURE if Get Partition Header start address failed +* +* @note None +* +****************************************************************************/ +u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset) +{ + u32 Status; + + Status = MoveImage(ImageAddress + IMAGE_PHDR_OFFSET, (u32)Offset, 4); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function goes to the partition header of the specified partition +* +* @param ImageAddress is the start address of the image +* +* @return Offset to Image header table address of the image +* +* @return - XST_SUCCESS if Get Partition Header start address successful +* - XST_FAILURE if Get Partition Header start address failed +* +* @note None +* +****************************************************************************/ +u32 GetImageHeaderStartAddr(u32 ImageAddress, u32 *Offset) +{ + u32 Status; + + Status = MoveImage(ImageAddress + IMAGE_HDR_OFFSET, (u32)Offset, 4); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} +/*****************************************************************************/ +/** +* +* This function gets the length of the FSBL +* +* @param ImageAddress is the start address of the image +* +* @return FsblLength is the length of the fsbl +* +* @return - XST_SUCCESS if fsbl length reading is successful +* - XST_FAILURE if fsbl length reading failed +* +* @note None +* +****************************************************************************/ +u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength) +{ + u32 Status; + + Status = MoveImage(ImageAddress + IMAGE_TOT_BYTE_LEN_OFFSET, + (u32)FsblLength, 4); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed reading FsblLength\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +#ifdef RSA_SUPPORT +/*****************************************************************************/ +/** +* +* This function goes to read the image headers and its signature. Image +* header consists of image header table, image headers, partition +* headers +* +* @param ImageBaseAddress is the start address of the image header +* +* @return Offset Partition header address of the image +* +* @return - XST_SUCCESS if Get Partition Header start address successful +* - XST_FAILURE if Get Partition Header start address failed +* +* @note None +* +****************************************************************************/ +u32 GetImageHeaderAndSignature(u32 ImageBaseAddress, u32 *Offset) +{ + u32 Status; + u32 ImageHeaderOffset; + + /* + * Get the start address of the partition header table + */ + Status = GetImageHeaderStartAddr(ImageBaseAddress, &ImageHeaderOffset); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n"); + return XST_FAILURE; + } + + Status = MoveImage(ImageBaseAddress+ImageHeaderOffset, (u32)Offset, + TOTAL_HEADER_SIZE + RSA_SIGNATURE_SIZE); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} +#endif +/*****************************************************************************/ +/** +* +* This function get the header information of the all the partitions and load into +* global array +* +* @param PartHeaderOffset Offset address where the header information present +* +* @param Header Partition header pointer +* +* @return - XST_SUCCESS if Load Partitions Header information successful +* - XST_FAILURE if Load Partitions Header information failed +* +* @note None +* +****************************************************************************/ +u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header) +{ + u32 Status; + + Status = MoveImage(PartHeaderOffset, (u32)Header, sizeof(PartHeader)*MAX_PARTITION_NUMBER); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/*****************************************************************************/ +/** +* +* This function dumps the partition header. +* +* @param Header Partition header pointer +* +* @return None +* +* @note None +* +******************************************************************************/ +void HeaderDump(PartHeader *Header) +{ + fsbl_printf(DEBUG_INFO, "Header Dump\r\n"); + fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08lx\r\n", + Header->ImageWordLen); + fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08lx\r\n", + Header->DataWordLen); + fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08lx\r\n", + Header->PartitionWordLen); + fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08lx\r\n", + Header->LoadAddr); + fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08lx\r\n", + Header->ExecAddr); + fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08lx\r\n", + Header->PartitionStart); + fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08lx\r\n", + Header->PartitionAttr); + fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08lx\r\n", + Header->CheckSumOffset); + fsbl_printf(DEBUG_INFO, "Section Count: 0x%08lx\r\n", + Header->SectionCount); + fsbl_printf(DEBUG_INFO, "Checksum: 0x%08lx\r\n", + Header->CheckSum); +} + + +/******************************************************************************/ +/** +* +* This function calculates the partitions count from header information +* +* @param Header Partition header pointer +* +* @return Count Partition count +* +* @note None +* +*******************************************************************************/ +u32 GetPartitionCount(PartHeader *Header) +{ + u32 Count=0; + struct HeaderArray *Hap; + + for(Count = 0; Count < MAX_PARTITION_NUMBER; Count++) { + Hap = (struct HeaderArray *)&Header[Count]; + if(IsLastPartition(Hap)!=XST_FAILURE) + break; + } + + return Count; +} + +/******************************************************************************/ +/** +* This function check whether the current partition is the end of partitions +* +* The partition is the end of the partitions if it looks like this: +* 0x00000000 +* 0x00000000 +* .... +* 0x00000000 +* 0x00000000 +* 0xFFFFFFFF +* +* @param H is a pointer to struct HeaderArray +* +* @return +* - XST_SUCCESS if it is the last partition +* - XST_FAILURE if it is not last partition +* +****************************************************************************/ +u32 IsLastPartition(struct HeaderArray *H) +{ + int Index; + + if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != 0xFFFFFFFF) { + return XST_FAILURE; + } + + for (Index = 0; Index < PARTITION_HDR_WORD_COUNT - 1; Index++) { + + if (H->Fields[Index] != 0x0) { + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function validates the partition header. +* +* @param Header Partition header pointer +* +* @return +* - XST_FAILURE if bad header. +* - XST_SUCCESS if successful. +* +* @note None +* +*******************************************************************************/ +u32 ValidateHeader(PartHeader *Header) +{ + struct HeaderArray *Hap; + + Hap = (struct HeaderArray *)Header; + + /* + * If there are no partitions to load, fail + */ + if (IsEmptyHeader(Hap) == XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "IMAGE_HAS_NO_PARTITIONS\r\n"); + return XST_FAILURE; + } + + /* + * Validate partition header checksum + */ + if (ValidatePartitionHeaderChecksum(Hap) != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "PARTITION_HEADER_CORRUPTION\r\n"); + return XST_FAILURE; + } + + /* + * Validate partition data size + */ + if (Header->ImageWordLen > MAXIMUM_IMAGE_WORD_LEN) { + fsbl_printf(DEBUG_GENERAL, "INVALID_PARTITION_LENGTH\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* This function check whether the current partition header is empty. +* A partition header is considered empty if image word length is 0 and the +* last word is 0. +* +* @param H is a pointer to struct HeaderArray +* +* @return +* - XST_SUCCESS , If the partition header is empty +* - XST_FAILURE , If the partition header is NOT empty +* +* @note Caller is responsible to make sure the address is valid. +* +* +****************************************************************************/ +u32 IsEmptyHeader(struct HeaderArray *H) +{ + int Index; + + for (Index = 0; Index < PARTITION_HDR_WORD_COUNT; Index++) { + if (H->Fields[Index] != 0x0) { + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function checks the header checksum If the header checksum is not valid +* XST_FAILURE is returned. +* +* @param H is a pointer to struct HeaderArray +* +* @return +* - XST_SUCCESS is header checksum is ok +* - XST_FAILURE if the header checksum is not correct +* +* @note None. +* +****************************************************************************/ +u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H) +{ + u32 Checksum; + u32 Count; + + Checksum = 0; + + for (Count = 0; Count < PARTITION_HDR_CHECKSUM_WORD_COUNT; Count++) { + /* + * Read the word from the header + */ + Checksum += H->Fields[Count]; + } + + /* + * Invert checksum, last bit of error checking + */ + Checksum ^= 0xFFFFFFFF; + + /* + * Validate the checksum + */ + if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != Checksum) { + fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8lx != 0x%8.8lx\r\n", + Checksum, H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT]); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function load the partition from boot device +* +* @param ImageBaseAddress Base address on flash +* @param Header Partition header pointer +* +* @return +* - XST_SUCCESS if partition move successful +* - XST_FAILURE if check failed move failed +* +* @note None +* +*******************************************************************************/ +u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header) +{ + u32 SourceAddr; + u32 Status; + u8 SecureTransferFlag = 0; + u32 LoadAddr; + u32 ImageWordLen; + u32 DataWordLen; + + SourceAddr = ImageBaseAddress; + SourceAddr += Header->PartitionStart<LoadAddr; + ImageWordLen = Header->ImageWordLen; + DataWordLen = Header->DataWordLen; + + /* + * Add flash base address for linear boot devices + */ + if (LinearBootDeviceFlag) { + SourceAddr += FlashReadBaseAddress; + } + + /* + * Partition encrypted + */ + if(EncryptedPartitionFlag) { + SecureTransferFlag = 1; + } + + /* + * For Signed or checksum enabled partition, + * Total partition image need to copied to DDR + */ + if (SignedPartitionFlag || PartitionChecksumFlag) { + ImageWordLen = Header->PartitionWordLen; + DataWordLen = Header->PartitionWordLen; + } + + /* + * Encrypted and Signed PS partition need to be loaded on to DDR + * without decryption + */ + if (PSPartitionFlag && + (SignedPartitionFlag || PartitionChecksumFlag) && + EncryptedPartitionFlag) { + SecureTransferFlag = 0; + } + + /* + * CPU is used for data transfer in case of non-linear + * boot device + */ + if (!LinearBootDeviceFlag) { + /* + * PL partition copied to DDR temporary location + */ + if (PLPartitionFlag) { + LoadAddr = DDR_TEMP_START_ADDR; + } + + Status = MoveImage(SourceAddr, + LoadAddr, + (ImageWordLen << WORD_LENGTH_SHIFT)); + if(Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Move Image Failed\r\n"); + return XST_FAILURE; + } + + /* + * As image present at load address + */ + SourceAddr = LoadAddr; + } + + if ((LinearBootDeviceFlag && PLPartitionFlag && + (SignedPartitionFlag || PartitionChecksumFlag)) || + (LinearBootDeviceFlag && PSPartitionFlag) || + ((!LinearBootDeviceFlag) && PSPartitionFlag && SecureTransferFlag)) { + /* + * PL signed partition copied to DDR temporary location + * using non-secure PCAP for linear boot device + */ + if(PLPartitionFlag){ + SecureTransferFlag = 0; + LoadAddr = DDR_TEMP_START_ADDR; + } + + /* + * Data transfer using PCAP + */ + Status = PcapDataTransfer((u32*)SourceAddr, + (u32*)LoadAddr, + ImageWordLen, + DataWordLen, + SecureTransferFlag); + if(Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "PCAP Data Transfer Failed\r\n"); + return XST_FAILURE; + } + + /* + * As image present at load address + */ + SourceAddr = LoadAddr; + } + + /* + * Load Bitstream partition in to fabric only + * if checksum and authentication bits are not set + */ + if (PLPartitionFlag && (!(SignedPartitionFlag || PartitionChecksumFlag))) { + Status = PcapLoadPartition((u32*)SourceAddr, + (u32*)Header->LoadAddr, + Header->ImageWordLen, + Header->DataWordLen, + EncryptedPartitionFlag); + if(Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "PCAP Bitstream Download Failed\r\n"); + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function load the decrypts partition +* +* @param StartAddr Source start address +* @param DataLength Data length in words +* @param ImageLength Image length in words +* +* @return +* - XST_SUCCESS if decryption successful +* - XST_FAILURE if decryption failed +* +* @note None +* +*******************************************************************************/ +u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength) +{ + u32 Status; + u8 SecureTransferFlag =1; + + /* + * Data transfer using PCAP + */ + Status = PcapDataTransfer((u32*)StartAddr, + (u32*)StartAddr, + ImageLength, + DataLength, + SecureTransferFlag); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"PCAP Data Transfer failed \r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** +* +* This function Validate Partition Data by using checksum preset in image +* +* @param Partition header pointer +* @param Partition check sum offset +* @return +* - XST_SUCCESS if partition data is ok +* - XST_FAILURE if partition data is corrupted +* +* @note None +* +*******************************************************************************/ +u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset) +{ + u8 Checksum[MD5_CHECKSUM_SIZE]; + u8 CalcChecksum[MD5_CHECKSUM_SIZE]; + u32 Status; + u32 Index; + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Prevent WDT reset + */ + XWdtPs_RestartWdt(&Watchdog); +#endif + + /* + * Get checksum from flash + */ + Status = GetPartitionChecksum(ChecksumOffset, &Checksum[0]); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO, "Actual checksum\r\n"); + + for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) { + fsbl_printf(DEBUG_INFO, "0x%0x ",Checksum[Index]); + } + + fsbl_printf(DEBUG_INFO, "\r\n"); + + /* + * Calculate checksum for the partition + */ + Status = CalcPartitionChecksum(StartAddr, Length, &CalcChecksum[0]); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO, "Calculated checksum\r\n"); + + for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) { + fsbl_printf(DEBUG_INFO, "0x%0x ",CalcChecksum[Index]); + } + + fsbl_printf(DEBUG_INFO, "\r\n"); + + /* + * Compare actual checksum with the calculated checksum + */ + for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) { + if(Checksum[Index] != CalcChecksum[Index]) { + fsbl_printf(DEBUG_GENERAL, "Error: " + "Partition DataChecksum 0x%0x!= 0x%0x\r\n", + Checksum[Index], CalcChecksum[Index]); + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function gets partition checksum from flash +* +* @param Check sum offset +* @param Checksum pointer +* @return +* - XST_SUCCESS if checksum read success +* - XST_FAILURE if unable get checksum +* +* @note None +* +*******************************************************************************/ +u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum) +{ + u32 Status; + + Status = MoveImage(ChecksumOffset, (u32)Checksum, MD5_CHECKSUM_SIZE); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function calculates the checksum preset in image +* +* @param Start address +* @param Length of the data +* @param Checksum pointer +* +* @return +* - XST_SUCCESS if Checksum calculate successful +* - XST_FAILURE if Checksum calculate failed +* +* @note None +* +*******************************************************************************/ +u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum) +{ + /* + * Calculate checksum using MD5 algorithm + */ + md5((u8*)SourceAddr, DataLength, Checksum, 0 ); + + return XST_SUCCESS; +} + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/image_mover.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/image_mover.h new file mode 100644 index 0000000..dad66f1 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/image_mover.h @@ -0,0 +1,161 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file image_mover.h +* +* This file contains the interface for moving the image from FLASH to OCM + +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz	03/04/11	Initial release
+* 2.00a jz	06/04/11	partition header expands to 12 words
+* 5.00a kc	07/30/13	Added defines for image header information
+* 8.00a kc	01/16/13	Added defines for partition owner attribute
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___IMAGE_MOVER_H___ +#define ___IMAGE_MOVER_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "fsbl.h" + +/************************** Constant Definitions *****************************/ +#define PARTITION_NUMBER_SHIFT 24 +#define MAX_PARTITION_NUMBER (0xE) + +/* Boot Image Header defines */ +#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */ +#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */ +#define IMAGE_HEADER_SIZE (64) +#define IMAGE_HEADER_TABLE_SIZE (64) +#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE) +#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE) +#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \ + TOTAL_IMAGE_HEADER_SIZE + \ + TOTAL_PARTITION_HEADER_SIZE + 64) + +/* Partition Header defines */ +#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */ +#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */ +#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */ +#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */ +#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */ +#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */ +#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */ +#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */ +#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */ +#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */ +#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/ + +/* Attribute word defines */ +#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */ +#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */ +#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */ +#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */ +#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */ +#define ATTRIBUTE_PARTITION_OWNER_MASK 0x30000 /* Partition Owner */ + +#define ATTRIBUTE_PARTITION_OWNER_FSBL 0x00000 /* FSBL Partition Owner */ + + +/**************************** Type Definitions *******************************/ +typedef u32 (*ImageMoverType)( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthBytes); + +typedef struct StructPartHeader { + u32 ImageWordLen; /* 0x0 */ + u32 DataWordLen; /* 0x4 */ + u32 PartitionWordLen; /* 0x8 */ + u32 LoadAddr; /* 0xC */ + u32 ExecAddr; /* 0x10 */ + u32 PartitionStart; /* 0x14 */ + u32 PartitionAttr; /* 0x18 */ + u32 SectionCount; /* 0x1C */ + u32 CheckSumOffset; /* 0x20 */ + u32 Pads1[1]; + u32 ACOffset; /* 0x28 */ + u32 Pads2[4]; + u32 CheckSum; /* 0x3C */ +}PartHeader; + +struct HeaderArray { + u32 Fields[16]; +}; + + +/***************** Macros (Inline Functions) Definitions *********************/ +#define MoverIn32 Xil_In32 +#define MoverOut32 Xil_Out32 + +/************************** Function Prototypes ******************************/ +u32 LoadBootImage(void); +u32 GetPartitionHeaderInfo(u32 ImageBaseAddress); +u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header); +u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H); +u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset); +u32 GetImageHeaderAndSignature(u32 ImageAddress, u32 *Offset); +u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength); +u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header); +u32 IsEmptyHeader(struct HeaderArray *H); +u32 IsLastPartition(struct HeaderArray *H); +void HeaderDump(PartHeader *Header); +u32 GetPartitionCount(PartHeader *Header); +u32 ValidateHeader(PartHeader *Header); +u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + + +#endif /* ___IMAGE_MOVER_H___ */ + + + + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/main.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/main.c new file mode 100644 index 0000000..958e3c0 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/main.c @@ -0,0 +1,1532 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file main.c +* +* The main file for the First Stage Boot Loader (FSBL). +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz	06/04/11	Initial release
+* 2.00a mb	25/05/12	standalone based FSBL
+* 3.00a np/mb	08/03/12	Added call to FSBL user hook - before handoff.
+*				DDR ECC initialization added
+* 				fsbl print with verbose added
+* 				Performance measurement added
+* 				Flushed the UART Tx buffer
+* 				Added the performance time for ECC DDR init
+* 				Added clearing of ECC Error Code
+* 				Added the watchdog timer value
+* 4.00a sgd 02/28/13	Code Cleanup
+* 						Fix for CR#681014 - ECC init in FSBL should not
+* 						                    call fabric_init()
+* 						Fix for CR#689077 - FSBL hangs at Handoff clearing the
+* 						                    TX UART buffer when using UART0
+* 						                    instead of UART1
+*						Fix for CR#694038 - FSBL debug logs always prints 14.3
+*											as the Revision number - this is
+*										    incorrect
+*						Fix for CR#694039 - FSBL prints "unsupported silicon
+*											version for v3.0" 3.0 Silicon
+*                       Fix for CR#699475 - FSBL functionality is broken and
+*                                           its not able to boot in QSPI/NAND
+*                                           bootmode
+*                       Removed DDR initialization check
+*                       Removed DDR ECC initialization code
+*						Modified hand off address check to 1MB
+*						Added RSA authentication support
+*						Watchdog disabled for AES E-Fuse encryption
+* 5.00a sgd 05/17/13	Fallback support for E-Fuse encryption
+*                       Fix for CR#708728 - Issues seen while making HP
+*                                           interconnect 32 bit wide
+* 6.00a kc  07/30/13    Fix for CR#708316 - PS7_init.tcl file should have
+*                                           Error mechanism for all mask_poll
+*                       Fix for CR#691150 - ps7_init does not check for
+*                                           peripheral initialization failures
+*                                           or timeout on polls
+*                       Fix for CR#724165 - Partition Header used by FSBL is
+*                                           not authenticated
+*                       Fix for CR#724166 - FSBL doesn’t use PPK authenticated
+*                                           by Boot ROM for authenticating
+*                                           the Partition images
+*                       Fix for CR#722979 - Provide customer-friendly
+*                                           changelogs in FSBL
+*                       Fix for CR#732865 - Backward compatibility for ps7_init
+*                       					function
+* 7.00a kc  10/18/13    Integrated SD/MMC driver
+* 8.00a kc  02/20/14	Fix for CR#775631 - FSBL: FsblGetGlobalTimer() 
+*											is not proper
+* 9.00a kc  04/16/14	Fix for CR#724166 - SetPpk() will fail on secure
+*		 									fallback unless FSBL* and FSBL
+*		 									are identical in length
+* 10.00a kc 07/24/14	Fix for CR#809336 - Minor code cleanup
+*        kc 08/27/14	Fix for CR#820356 - FSBL compilation fails with
+* 											IAR compiler
+* 11.00a kv 10/08/14	Fix for CR#826030 - LinearBootDeviceFlag should
+*											be initialized to 0 in IO mode
+*											case
+* 15.00a gan 07/21/16   Fix for CR# 953654 -(2016.3)FSBL -
+* 											In pcap.c/pcap.h/main.c,
+* 											Fabric Initialization sequence
+* 											is modified to check the PL power
+* 											before sequence starts and checking
+* 											INIT_B reset status twice in case
+* 											of failure.
+*
    +* +* @note +* FSBL runs from OCM, Based on the boot mode selected, FSBL will copy +* the partitions from the flash device. If the partition is bitstream then +* the bitstream is programmed in the Fabric and for an partition that is +* an application , FSBL will copy the application into DDR and does a +* handoff.The application should not be starting at the OCM address, +* FSBL does not remap the DDR. Application should use DDR starting from 1MB +* +* FSBL can be stitched along with bitstream and application using bootgen +* +* Refer to fsbl.h file for details on the compilation flags supported in FSBL +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "fsbl.h" +#include "qspi.h" +#include "nand.h" +#include "nor.h" +#include "sd.h" +#include "pcap.h" +#include "image_mover.h" +#include "xparameters.h" +#include "xil_cache.h" +#include "xil_exception.h" +#include "xstatus.h" +#include "fsbl_hooks.h" +#include "xtime_l.h" + +#ifdef XPAR_XWDTPS_0_BASEADDR +#include "xwdtps.h" +#endif + +#ifdef STDOUT_BASEADDRESS +#ifdef XPAR_XUARTPS_0_BASEADDR +#include "xuartps_hw.h" +#endif +#endif + +#ifdef RSA_SUPPORT +#include "rsa.h" +#endif + +/************************** Constant Definitions *****************************/ + +#ifdef XPAR_XWDTPS_0_BASEADDR +#define WDT_DEVICE_ID XPAR_XWDTPS_0_DEVICE_ID +#define WDT_EXPIRE_TIME 100 +#define WDT_CRV_SHIFT 12 +#endif + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifdef XPAR_XWDTPS_0_BASEADDR +XWdtPs Watchdog; /* Instance of WatchDog Timer */ +#endif +/************************** Function Prototypes ******************************/ +extern int ps7_init(); +extern char* getPS7MessageInfo(unsigned key); +#ifdef PS7_POST_CONFIG +extern int ps7_post_config(); +#endif + +static void Update_MultiBootRegister(void); +/* Exception handlers */ +static void RegisterHandlers(void); +static void Undef_Handler (void); +static void SVC_Handler (void); +static void PreFetch_Abort_Handler (void); +static void Data_Abort_Handler (void); +static void IRQ_Handler (void); +static void FIQ_Handler (void); + + +#ifdef XPAR_XWDTPS_0_BASEADDR +int InitWatchDog(void); +u32 ConvertTime_WdtCounter(u32 seconds); +void CheckWDTReset(void); +#endif + +u32 NextValidImageCheck(void); + +u32 DDRInitCheck(void); + +/************************** Variable Definitions *****************************/ +/* + * Base Address for the Read Functionality for Image Processing + */ +u32 FlashReadBaseAddress = 0; +/* + * Silicon Version + */ +u32 Silicon_Version; + +/* + * Boot Device flag + */ +u8 LinearBootDeviceFlag=0; + +u32 PcapCtrlRegVal; + +u8 SystemInitFlag; + +extern ImageMoverType MoveImage; +extern XDcfg *DcfgInstPtr; +extern u8 BitstreamFlag; +#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +extern u32 QspiFlashSize; +#endif +/*****************************************************************************/ +/** +* +* This is the main function for the FSBL ROM code. +* +* +* @param None. +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +* @note +* +****************************************************************************/ +int main(void) +{ + u32 BootModeRegister = 0; + u32 HandoffAddress = 0; + u32 Status = XST_SUCCESS; + + /* + * PCW initialization for MIO,PLL,CLK and DDR + */ + Status = ps7_init(); + if (Status != FSBL_PS7_INIT_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"PS7_INIT_FAIL : %s\r\n", + getPS7MessageInfo(Status)); + OutputStatus(PS7_INIT_FAIL); + /* + * Calling FsblHookFallback instead of Fallback + * since, devcfg driver is not yet initialized + */ + FsblHookFallback(); + } + + /* + * Unlock SLCR for SLCR register write + */ + SlcrUnlock(); + + /* If Performance measurement is required + * then read the Global Timer value , Please note that the + * time taken for mio, clock and ddr initialisation + * done in the ps7_init function is not accounted in the FSBL + * + */ +#ifdef FSBL_PERF + XTime tCur = 0; + FsblGetGlobalTime(&tCur); +#endif + + /* + * Flush the Caches + */ + Xil_DCacheFlush(); + + /* + * Disable Data Cache + */ + Xil_DCacheDisable(); + + /* + * Register the Exception handlers + */ + RegisterHandlers(); + + /* + * Print the FSBL Banner + */ + fsbl_printf(DEBUG_GENERAL,"\n\rXilinx First Stage Boot Loader \n\r"); + fsbl_printf(DEBUG_GENERAL,"Release %d.%d %s-%s\r\n", + SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER, + __DATE__,__TIME__); + +#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR + + /* + * DDR Read/write test + */ + Status = DDRInitCheck(); + if (Status == XST_FAILURE) { + fsbl_printf(DEBUG_GENERAL,"DDR_INIT_FAIL \r\n"); + /* Error Handling here */ + OutputStatus(DDR_INIT_FAIL); + /* + * Calling FsblHookFallback instead of Fallback + * since, devcfg driver is not yet initialized + */ + FsblHookFallback(); + } + + + /* + * PCAP initialization + */ + Status = InitPcap(); + if (Status == XST_FAILURE) { + fsbl_printf(DEBUG_GENERAL,"PCAP_INIT_FAIL \n\r"); + OutputStatus(PCAP_INIT_FAIL); + /* + * Calling FsblHookFallback instead of Fallback + * since, devcfg driver is not yet initialized + */ + FsblHookFallback(); + } + + fsbl_printf(DEBUG_INFO,"Devcfg driver initialized \r\n"); + + /* + * Get the Silicon Version + */ + GetSiliconVersion(); + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Check if WDT Reset has occurred or not + */ + CheckWDTReset(); + + /* + * Initialize the Watchdog Timer so that it is ready to use + */ + Status = InitWatchDog(); + if (Status == XST_FAILURE) { + fsbl_printf(DEBUG_GENERAL,"WATCHDOG_INIT_FAIL \n\r"); + OutputStatus(WDT_INIT_FAIL); + FsblFallback(); + } + fsbl_printf(DEBUG_INFO,"Watchdog driver initialized \r\n"); +#endif + + /* + * Get PCAP controller settings + */ + PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr); + + /* + * Check for AES source key + */ + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * For E-Fuse AES encryption Watch dog Timer disabled and + * User not allowed to do system reset + */ +#ifdef XPAR_XWDTPS_0_BASEADDR + fsbl_printf(DEBUG_INFO,"Watchdog Timer Disabled\r\n"); + XWdtPs_Stop(&Watchdog); +#endif + fsbl_printf(DEBUG_INFO,"User not allowed to do " + "any system resets\r\n"); + } + + /* + * Store FSBL run state in Reboot Status Register + */ + MarkFSBLIn(); + + /* + * Read bootmode register + */ + BootModeRegister = Xil_In32(BOOT_MODE_REG); + BootModeRegister &= BOOT_MODES_MASK; + + /* + * QSPI BOOT MODE + */ +#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR + +#ifdef MMC_SUPPORT + /* + * To support MMC boot + * QSPI boot mode detection ignored + */ + if (BootModeRegister == QSPI_MODE) { + BootModeRegister = MMC_MODE; + } +#endif + + if (BootModeRegister == QSPI_MODE) { + fsbl_printf(DEBUG_GENERAL,"Boot mode is QSPI\n\r"); + InitQspi(); + MoveImage = QspiAccess; + fsbl_printf(DEBUG_INFO,"QSPI Init Done \r\n"); + } else +#endif + + /* + * NAND BOOT MODE + */ +#ifdef XPAR_PS7_NAND_0_BASEADDR + if (BootModeRegister == NAND_FLASH_MODE) { + /* + * Boot ROM always initialize the nand at lower speed + * This is the chance to put it to an optimum speed for your nand + * device + */ + fsbl_printf(DEBUG_GENERAL,"Boot mode is NAND\n"); + + Status = InitNand(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"NAND_INIT_FAIL \r\n"); + /* + * Error Handling here + */ + OutputStatus(NAND_INIT_FAIL); + FsblFallback(); + } + MoveImage = NandAccess; + fsbl_printf(DEBUG_INFO,"NAND Init Done \r\n"); + } else +#endif + + /* + * NOR BOOT MODE + */ + if (BootModeRegister == NOR_FLASH_MODE) { + fsbl_printf(DEBUG_GENERAL,"Boot mode is NOR\n\r"); + /* + * Boot ROM always initialize the nor at lower speed + * This is the chance to put it to an optimum speed for your nor + * device + */ + InitNor(); + fsbl_printf(DEBUG_INFO,"NOR Init Done \r\n"); + MoveImage = NorAccess; + } else + + /* + * SD BOOT MODE + */ +#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR) + + if (BootModeRegister == SD_MODE) { + fsbl_printf(DEBUG_GENERAL,"Boot mode is SD\r\n"); + + /* + * SD initialization returns file open error or success + */ + Status = InitSD("BOOT.BIN"); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"SD_INIT_FAIL\r\n"); + OutputStatus(SD_INIT_FAIL); + FsblFallback(); + } + MoveImage = SDAccess; + fsbl_printf(DEBUG_INFO,"SD Init Done \r\n"); + } else + + if (BootModeRegister == MMC_MODE) { + fsbl_printf(DEBUG_GENERAL,"Booting Device is MMC\r\n"); + + /* + * MMC initialization returns file open error or success + */ + Status = InitSD("BOOT.BIN"); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"MMC_INIT_FAIL\r\n"); + OutputStatus(SD_INIT_FAIL); + FsblFallback(); + } + MoveImage = SDAccess; + fsbl_printf(DEBUG_INFO,"MMC Init Done \r\n"); + } else + +#endif + + /* + * JTAG BOOT MODE + */ + if (BootModeRegister == JTAG_MODE) { + fsbl_printf(DEBUG_GENERAL,"Boot mode is JTAG\r\n"); + /* + * Stop the Watchdog before JTAG handoff + */ +#ifdef XPAR_XWDTPS_0_BASEADDR + XWdtPs_Stop(&Watchdog); +#endif + /* + * Clear our mark in reboot status register + */ + ClearFSBLIn(); + + /* + * SLCR lock + */ + SlcrLock(); + + FsblHandoffJtagExit(); + } else { + fsbl_printf(DEBUG_GENERAL,"ILLEGAL_BOOT_MODE \r\n"); + OutputStatus(ILLEGAL_BOOT_MODE); + /* + * fallback starts, no return + */ + FsblFallback(); + } + + fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08lx\r\n", FlashReadBaseAddress); + + /* + * Check for valid flash address + */ + if ((FlashReadBaseAddress != XPS_QSPI_LINEAR_BASEADDR) && + (FlashReadBaseAddress != XPS_NAND_BASEADDR) && + (FlashReadBaseAddress != XPS_NOR_BASEADDR) && + (FlashReadBaseAddress != XPS_SDIO0_BASEADDR)) { + fsbl_printf(DEBUG_GENERAL,"INVALID_FLASH_ADDRESS \r\n"); + OutputStatus(INVALID_FLASH_ADDRESS); + FsblFallback(); + } + + /* + * NOR and QSPI (parallel) are linear boot devices + */ + if ((FlashReadBaseAddress == XPS_NOR_BASEADDR)) { + fsbl_printf(DEBUG_INFO, "Linear Boot Device\r\n"); + LinearBootDeviceFlag = 1; + } + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Prevent WDT reset + */ + XWdtPs_RestartWdt(&Watchdog); +#endif + + /* + * This used only in case of E-Fuse encryption + * For image search + */ + SystemInitFlag = 1; + + /* + * Load boot image + */ + HandoffAddress = LoadBootImage(); + + fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08lx\r\n",HandoffAddress); + + /* + * For Performance measurement + */ +#ifdef FSBL_PERF + XTime tEnd = 0; + fsbl_printf(DEBUG_GENERAL,"Total Execution time is "); + FsblMeasurePerfTime(tCur,tEnd); +#endif + + /* + * FSBL handoff to valid handoff address or + * exit in JTAG + */ + FsblHandoff(HandoffAddress); + +#else + OutputStatus(NO_DDR); + FsblFallback(); +#endif + + return Status; +} + +/******************************************************************************/ +/** +* +* This function reset the CPU and goes for Boot ROM fallback handling +* +* @param None +* +* @return None +* +* @note None +* +****************************************************************************/ +void FsblFallback(void) +{ + u32 RebootStatusReg; + u32 Status; + u32 HandoffAddr; + u32 BootModeRegister; + + /* + * Read bootmode register + */ + BootModeRegister = Xil_In32(BOOT_MODE_REG); + BootModeRegister &= BOOT_MODES_MASK; + + /* + * Fallback support check + */ + if (!((BootModeRegister == QSPI_MODE) || + (BootModeRegister == NAND_FLASH_MODE) || + (BootModeRegister == NOR_FLASH_MODE))) { + fsbl_printf(DEBUG_INFO,"\r\n" + "This Boot Mode Doesn't Support Fallback\r\n"); + ClearFSBLIn(); + FsblHookFallback(); + } + + /* + * update the Multiboot Register for Golden search hunt + */ + Update_MultiBootRegister(); + + /* + * Notify Boot ROM something is wrong + */ + RebootStatusReg = Xil_In32(REBOOT_STATUS_REG); + + /* + * Set the FSBL Fail mask + */ + Xil_Out32(REBOOT_STATUS_REG, RebootStatusReg | FSBL_FAIL_MASK); + + /* + * Barrier for synchronization + */ + __asm( + "dsb\n\t" + "isb" + ); + + /* + * Check for AES source key + */ + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * Next valid image search can happen only + * when system initialization done + */ + if (SystemInitFlag == 1) { + /* + * Clean the Fabric + */ + Status = FabricInit(); + if(Status != XST_SUCCESS){ + ClearFSBLIn(); + FsblHookFallback(); + } + +#ifdef RSA_SUPPORT + + /* + * Making sure PPK is set for efuse error cases + */ + SetPpk(); +#endif + + /* + * Search for next valid image + */ + Status = NextValidImageCheck(); + if(Status != XST_SUCCESS){ + fsbl_printf(DEBUG_INFO,"\r\nNo Image Found\r\n"); + ClearFSBLIn(); + FsblHookFallback(); + } + + /* + * Load next valid image + */ + HandoffAddr = LoadBootImage(); + + /* + * Handoff to next image + */ + FsblHandoff(HandoffAddr); + } else { + fsbl_printf(DEBUG_INFO,"System Initialization Failed\r\n"); + fsbl_printf(DEBUG_INFO,"\r\nNo Image Search\r\n"); + ClearFSBLIn(); + FsblHookFallback(); + } + } + + /* + * Reset PS, so Boot ROM will restart + */ + Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK); +} + + +/******************************************************************************/ +/** +* +* This function hands the A9/PS to the loaded user code. +* +* @param none +* +* @return none +* +* @note This function does not return. +* +****************************************************************************/ +void FsblHandoff(u32 FsblStartAddr) +{ + u32 Status; + + /* + * Enable level shifter + */ + if(BitstreamFlag) { + /* + * FSBL will not enable the level shifters for a NON PS instantiated + * Bitstream + * CR# 671028 + * This flag can be set during compilation for a NON PS instantiated + * bitstream + */ +#ifndef NON_PS_INSTANTIATED_BITSTREAM +#ifdef PS7_POST_CONFIG + ps7_post_config(); + /* + * Unlock SLCR for SLCR register write + */ + SlcrUnlock(); +#else + /* + * Set Level Shifters DT618760 + */ + Xil_Out32(PS_LVL_SHFTR_EN, LVL_PL_PS); + fsbl_printf(DEBUG_INFO,"Enabling Level Shifters PL to PS " + "Address = 0x%x Value = 0x%x \n\r", + PS_LVL_SHFTR_EN, Xil_In32(PS_LVL_SHFTR_EN)); + + /* + * Enable AXI interface + */ + Xil_Out32(FPGA_RESET_REG, 0); + fsbl_printf(DEBUG_INFO,"AXI Interface enabled \n\r"); + fsbl_printf(DEBUG_INFO, "FPGA Reset Register " + "Address = 0x%x , Value = 0x%x \r\n", + FPGA_RESET_REG ,Xil_In32(FPGA_RESET_REG)); +#endif +#endif + } + + /* + * FSBL user hook call before handoff to the application + */ + Status = FsblHookBeforeHandoff(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"FSBL_HANDOFF_HOOK_FAIL\r\n"); + OutputStatus(FSBL_HANDOFF_HOOK_FAIL); + FsblFallback(); + } + +#ifdef XPAR_XWDTPS_0_BASEADDR + XWdtPs_Stop(&Watchdog); +#endif + + /* + * Clear our mark in reboot status register + */ + ClearFSBLIn(); + + if(FsblStartAddr == 0) { + /* + * SLCR lock + */ + SlcrLock(); + + fsbl_printf(DEBUG_INFO,"No Execution Address JTAG handoff \r\n"); + FsblHandoffJtagExit(); + } else { + fsbl_printf(DEBUG_GENERAL,"SUCCESSFUL_HANDOFF\r\n"); + OutputStatus(SUCCESSFUL_HANDOFF); + FsblHandoffExit(FsblStartAddr); + } + + OutputStatus(ILLEGAL_RETURN); + + FsblFallback(); +} + +/******************************************************************************/ +/** +* +* This function outputs the status for the provided State in the boot process. +* +* @param State is where in the boot process the output is desired. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void OutputStatus(u32 State) +{ +#ifdef STDOUT_BASEADDRESS +#ifdef XPAR_XUARTPS_0_BASEADDR + u32 UartReg = 0; +#endif + + fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4lx\r\n", State); + /* + * The TX buffer needs to be flushed out + * If this is not done some of the prints will not appear on the + * serial output + */ +#ifdef XPAR_XUARTPS_0_BASEADDR + UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET); + while ((UartReg & XUARTPS_SR_TXEMPTY) != XUARTPS_SR_TXEMPTY) { + UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET); + } +#endif +#endif +} + +/******************************************************************************/ +/** +* +* This function handles the error and lockdown processing and outputs the status +* for the provided State in the boot process. +* +* This function is called upon exceptions. +* +* @param State - where in the boot process the error occured. +* +* @return None. +* +* @note This function does not return, the PS block is reset +* +****************************************************************************/ +void ErrorLockdown(u32 State) +{ + /* + * Store the error status + */ + OutputStatus(State); + + /* + * Fall back + */ + FsblFallback(); +} + +/******************************************************************************/ +/** +* +* This function copies a memory region to another memory region +* +* @param s1 is starting address for destination +* @param s2 is starting address for the source +* @param n is the number of bytes to copy +* +* @return Starting address for destination +* +****************************************************************************/ +void *(memcpy_rom)(void * s1, const void * s2, u32 n) +{ + char *dst = (char *)s1; + const char *src = (char *)s2; + + /* + * Loop and copy + */ + while (n-- != 0) + *dst++ = *src++; + return s1; +} +/******************************************************************************/ +/** +* +* This function copies a string to another, the source string must be null- +* terminated. +* +* @param Dest is starting address for the destination string +* @param Src is starting address for the source string +* +* @return Starting address for the destination string +* +****************************************************************************/ +char *strcpy_rom(char *Dest, const char *Src) +{ + unsigned i; + for (i=0; Src[i] != '\0'; ++i) + Dest[i] = Src[i]; + Dest[i] = '\0'; + return Dest; +} + + +/******************************************************************************/ +/** +* +* This function sets FSBL is running mask in reboot status register +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void MarkFSBLIn(void) +{ + Xil_Out32(REBOOT_STATUS_REG, + Xil_In32(REBOOT_STATUS_REG) | FSBL_IN_MASK); +} + + +/******************************************************************************/ +/** +* +* This function clears FSBL is running mask in reboot status register +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void ClearFSBLIn(void) +{ + Xil_Out32(REBOOT_STATUS_REG, + (Xil_In32(REBOOT_STATUS_REG)) & ~(FSBL_FAIL_MASK)); +} + +/******************************************************************************/ +/** +* +* This function Registers the Exception Handlers +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +static void RegisterHandlers(void) +{ + Xil_ExceptionInit(); + + /* + * Initialize the vector table. Register the stub Handler for each + * exception. + */ + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT, + (Xil_ExceptionHandler)Undef_Handler, + (void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SWI_INT, + (Xil_ExceptionHandler)SVC_Handler, + (void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT, + (Xil_ExceptionHandler)PreFetch_Abort_Handler, + (void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT, + (Xil_ExceptionHandler)Data_Abort_Handler, + (void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, + (Xil_ExceptionHandler)IRQ_Handler,(void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT, + (Xil_ExceptionHandler)FIQ_Handler,(void *) 0); + + Xil_ExceptionEnable(); + +} + +static void Undef_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"UNDEFINED_HANDLER\r\n"); + ErrorLockdown (EXCEPTION_ID_UNDEFINED_INT); +} + +static void SVC_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"SVC_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_SWI_INT); +} + +static void PreFetch_Abort_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"PREFETCH_ABORT_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_PREFETCH_ABORT_INT); +} + +static void Data_Abort_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"DATA_ABORT_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_DATA_ABORT_INT); +} + +static void IRQ_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"IRQ_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_IRQ_INT); +} + +static void FIQ_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"FIQ_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_FIQ_INT); +} + + +/******************************************************************************/ +/** +* +* This function Updates the Multi boot Register to enable golden image +* search for boot rom +* +* @param None +* +* @return +* return none +* +****************************************************************************/ +static void Update_MultiBootRegister(void) +{ + u32 MultiBootReg = 0; + + if (Silicon_Version != SILICON_VERSION_1) { + /* + * Read the mulitboot register + */ + MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET); + + /* + * Incrementing multiboot register by one + */ + MultiBootReg++; + + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET, + MultiBootReg); + + fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08lx\r\n", + MultiBootReg); + } +} + + +/****************************************************************************** +* +* This function reset the CPU and goes for Boot ROM fallback handling +* +* @param None +* +* @return None +* +* @note None +* +*******************************************************************************/ + +u32 GetResetReason(void) +{ + u32 Regval; + + /* We are using REBOOT_STATUS_REG, we have to use bits 23:16 */ + /* for storing the RESET_REASON register value*/ + Regval = ((Xil_In32(REBOOT_STATUS_REG) >> 16) & 0xFF); + + return Regval; +} + + +/****************************************************************************** +* +* This function Gets the ticks from the Global Timer +* +* @param Current time +* +* @return +* None +* +* @note None +* +*******************************************************************************/ +#ifdef FSBL_PERF +void FsblGetGlobalTime (XTime *tCur) +{ + XTime_GetTime(tCur); +} + + +/****************************************************************************** +* +* This function Measures the execution time +* +* @param Current time , End time +* +* @return +* None +* +* @note None +* +*******************************************************************************/ +void FsblMeasurePerfTime (XTime tCur, XTime tEnd) +{ + double tDiff = 0.0; + double tPerfSeconds; + XTime_GetTime(&tEnd); + tDiff = (double)tEnd - (double)tCur; + + /* + * Convert tPerf into Seconds + */ + tPerfSeconds = tDiff/COUNTS_PER_SECOND; + +#if defined(STDOUT_BASEADDRESS) + printf("%f seconds \r\n",tPerfSeconds); +#endif + +} +#endif + +/****************************************************************************** +* +* This function initializes the Watchdog driver and starts the timer +* +* @param None +* +* @return +* - XST_SUCCESS if the Watchdog driver is initialized +* - XST_FAILURE if Watchdog driver initialization fails +* +* @note None +* +*******************************************************************************/ +#ifdef XPAR_XWDTPS_0_BASEADDR +int InitWatchDog(void) +{ + u32 Status = XST_SUCCESS; + XWdtPs_Config *ConfigPtr; /* Config structure of the WatchDog Timer */ + u32 CounterValue = 1; + + ConfigPtr = XWdtPs_LookupConfig(WDT_DEVICE_ID); + Status = XWdtPs_CfgInitialize(&Watchdog, + ConfigPtr, + ConfigPtr->BaseAddress); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"Watchdog Driver init Failed \n\r"); + return XST_FAILURE; + } + + /* + * Setting the divider value + */ + XWdtPs_SetControlValue(&Watchdog, + XWDTPS_CLK_PRESCALE, + XWDTPS_CCR_PSCALE_4096); + /* + * Convert time to Watchdog counter reset value + */ + CounterValue = ConvertTime_WdtCounter(WDT_EXPIRE_TIME); + + /* + * Set the Watchdog counter reset value + */ + XWdtPs_SetControlValue(&Watchdog, + XWDTPS_COUNTER_RESET, + CounterValue); + /* + * enable reset output, as we are only using this as a basic counter + */ + XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL); + + /* + * Start the Watchdog timer + */ + XWdtPs_Start(&Watchdog); + + XWdtPs_RestartWdt(&Watchdog); + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function checks whether WDT reset has happened during FSBL run +* +* If WDT reset happened during FSBL run, then need to fallback +* +* @param None. +* +* @return +* None +* +* @note None +* +****************************************************************************/ +void CheckWDTReset(void) +{ + u32 ResetReason; + u32 RebootStatusRegister; + + RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG); + + /* + * For 1.0 Silicon the reason for Reset is in the ResetReason Register + * Hence this register can be read to know the cause for previous reset + * that happened. + * Check if that reset is a Software WatchDog reset that happened + */ + if (Silicon_Version == SILICON_VERSION_1) { + ResetReason = Xil_In32(RESET_REASON_REG); + } else { + ResetReason = GetResetReason(); + } + /* + * If the FSBL_IN_MASK Has not been cleared, WDT happened + * before FSBL exits + */ + if ((ResetReason & RESET_REASON_SWDT) == RESET_REASON_SWDT ) { + if ((RebootStatusRegister & FSBL_FAIL_MASK) == FSBL_IN_MASK) { + /* + * Clear the SWDT Reset bit + */ + ResetReason &= ~RESET_REASON_SWDT; + if (Silicon_Version == SILICON_VERSION_1) { + /* + * for 1.0 Silicon we need to write + * 1 to the RESET REASON Clear register + */ + Xil_Out32(RESET_REASON_CLR, 1); + } else { + Xil_Out32(REBOOT_STATUS_REG, ResetReason); + } + + fsbl_printf(DEBUG_GENERAL,"WDT_RESET_OCCURED \n\r"); + } + } +} + + +/****************************************************************************** +* +* This function converts time into Watchdog counter value +* +* @param watchdog expire time in seconds +* +* @return +* Counter value for Watchdog +* +* @note None +* +*******************************************************************************/ +u32 ConvertTime_WdtCounter(u32 seconds) +{ + double time = 0.0; + double CounterValue; + u32 Crv = 0; + u32 Prescaler,PrescalerValue; + + Prescaler = XWdtPs_GetControlValue(&Watchdog, XWDTPS_CLK_PRESCALE); + + if (Prescaler == XWDTPS_CCR_PSCALE_0008) + PrescalerValue = 8; + if (Prescaler == XWDTPS_CCR_PSCALE_0064) + PrescalerValue = 64; + if (Prescaler == XWDTPS_CCR_PSCALE_4096) + PrescalerValue = 4096; + + time = (double)(PrescalerValue) / (double)XPAR_PS7_WDT_0_WDT_CLK_FREQ_HZ; + + CounterValue = seconds / time; + + Crv = (u32)CounterValue; + Crv >>= WDT_CRV_SHIFT; + + return Crv; +} + +#endif + + +/****************************************************************************** +* +* This function Gets the Silicon Version stores in global variable +* +* @param None +* +* @return None +* +* @note None +* +*******************************************************************************/ +void GetSiliconVersion(void) +{ + /* + * Get the silicon version + */ + Silicon_Version = XDcfg_GetPsVersion(DcfgInstPtr); + if(Silicon_Version == SILICON_VERSION_3_1) { + fsbl_printf(DEBUG_GENERAL,"Silicon Version 3.1\r\n"); + } else { + fsbl_printf(DEBUG_GENERAL,"Silicon Version %lu.0\r\n", + Silicon_Version + 1); + } +} + + +/****************************************************************************** +* +* This function HeaderChecksum will calculates the header checksum and +* compares with checksum read from flash +* +* @param FlashOffsetAddress Flash offset address +* +* @return +* - XST_SUCCESS if ID matches +* - XST_FAILURE if ID mismatches +* +* @note None +* +*******************************************************************************/ +u32 HeaderChecksum(u32 FlashOffsetAddress){ + u32 Checksum = 0; + u32 Count; + u32 TempValue = 0; + + for (Count = 0; Count < IMAGE_HEADER_CHECKSUM_COUNT; Count++) { + /* + * Read the word from the header + */ + MoveImage(FlashOffsetAddress + IMAGE_WIDTH_CHECK_OFFSET + (Count*4), (u32)&TempValue, 4); + + /* + * Update checksum + */ + Checksum += TempValue; + } + + /* + * Invert checksum, last bit of error checking + */ + Checksum ^= 0xFFFFFFFF; + MoveImage(FlashOffsetAddress + IMAGE_CHECKSUM_OFFSET, (u32)&TempValue, 4); + + /* + * Validate the checksum + */ + if (TempValue != Checksum){ + fsbl_printf(DEBUG_INFO, "Checksum = %8.8lx\r\n", Checksum); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/****************************************************************************** +* +* This function ImageCheckID will do check for XLNX pattern +* +* @param FlashOffsetAddress Flash offset address +* +* @return +* - XST_SUCCESS if ID matches +* - XST_FAILURE if ID mismatches +* +* @note None +* +*******************************************************************************/ +u32 ImageCheckID(u32 FlashOffsetAddress){ + u32 ID; + + /* + * Read in the header info + */ + MoveImage(FlashOffsetAddress + IMAGE_IDENT_OFFSET, (u32)&ID, 4); + + /* + * Check the ID, make sure image is XLNX format + */ + if (ID != IMAGE_IDENT){ + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/****************************************************************************** +* +* This function NextValidImageCheck search for valid boot image +* +* @param None +* +* @return +* - XST_SUCCESS if valid image found +* - XST_FAILURE if no image found +* +* @note None +* +*******************************************************************************/ +u32 NextValidImageCheck(void) +{ + u32 ImageBaseAddr; + u32 MultiBootReg; + u32 BootDevMaxSize=0; + + fsbl_printf(DEBUG_GENERAL, "Searching For Next Valid Image"); + + /* + * Setting variable with maximum flash size based on boot mode + */ +#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR + if (FlashReadBaseAddress == XPS_QSPI_LINEAR_BASEADDR) { + BootDevMaxSize = QspiFlashSize; + } +#endif + + if (FlashReadBaseAddress == XPS_NAND_BASEADDR) { + BootDevMaxSize = NAND_FLASH_SIZE; + } + + if (FlashReadBaseAddress == XPS_NOR_BASEADDR) { + BootDevMaxSize = NOR_FLASH_SIZE; + } + + /* + * Read the multiboot register + */ + MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET); + + /* + * Compute the image start address + */ + ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK) + * GOLDEN_IMAGE_OFFSET; + + /* + * Valid image search continue till end of the flash + * With increment 32KB in each iteration + */ + while (ImageBaseAddr < BootDevMaxSize) { + + fsbl_printf(DEBUG_INFO,"."); + + /* + * Valid image search using XLNX pattern at fixed offset + * and header checksum + */ + if ((ImageCheckID(ImageBaseAddr) == XST_SUCCESS) && + (HeaderChecksum(ImageBaseAddr) == XST_SUCCESS)) { + + fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8lx\r\n", + ImageBaseAddr); + /* + * Update multiboot register + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET, + MultiBootReg); + + return XST_SUCCESS; + } + + /* + * Increment mulitboot count + */ + MultiBootReg++; + + /* + * Compute the image start address + */ + ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK) + * GOLDEN_IMAGE_OFFSET; + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** +* +* This function Checks for the ddr initialization completion +* +* @param None. +* +* @return +* - XST_SUCCESS if the initialization is successful +* - XST_FAILURE if the initialization is NOT successful +* +* @note None. +* +****************************************************************************/ +u32 DDRInitCheck(void) +{ + u32 ReadVal; + + /* + * Write and Read from the DDR location for sanity checks + */ + Xil_Out32(DDR_START_ADDR, DDR_TEST_PATTERN); + ReadVal = Xil_In32(DDR_START_ADDR); + if (ReadVal != DDR_TEST_PATTERN) { + return XST_FAILURE; + } + + /* + * Write and Read from the DDR location for sanity checks + */ + Xil_Out32(DDR_START_ADDR + DDR_TEST_OFFSET, DDR_TEST_PATTERN); + ReadVal = Xil_In32(DDR_START_ADDR + DDR_TEST_OFFSET); + if (ReadVal != DDR_TEST_PATTERN) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/md5.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/md5.c new file mode 100644 index 0000000..e7cf7ea --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/md5.c @@ -0,0 +1,484 @@ +/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) + * All rights reserved. + * + * This package is an SSL implementation written + * by Eric Young (eay@cryptsoft.com). + * The implementation was written so as to conform with Netscapes SSL. + * + * This library is free for commercial and non-commercial use as long as + * the following conditions are aheared to. The following conditions + * apply to all code found in this distribution, be it the RC4, RSA, + * lhash, DES, etc., code; not just the SSL code. The SSL documentation + * included with this distribution is covered by the same copyright terms + * except that the holder is Tim Hudson (tjh@cryptsoft.com). + * + * Copyright remains Eric Young's, and as such any Copyright notices in + * the code are not to be removed. + * If this package is used in a product, Eric Young should be given attribution + * as the author of the parts of the library used. + * This can be in the form of a textual message at program startup or + * in documentation (online or textual) provided with the package. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * "This product includes cryptographic software written by + * Eric Young (eay@cryptsoft.com)" + * The word 'cryptographic' can be left out if the rouines from the library + * being used are not cryptographic related :-). + * 4. If you include any Windows specific code (or a derivative thereof) from + * the apps directory (application code) you must include an acknowledgement: + * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" + * + * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * The licence and distribution terms for any publically available version or + * derivative of this code cannot be changed. i.e. this code cannot simply be + * copied and put under another distribution licence + * [including the GNU Public Licence.] + */ +/*****************************************************************************/ +/** +* +* @file md5.c +* +* Contains code to calculate checksum using md5 algorithm +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00a sgd	05/17/13 Initial release
+*
+*
+*
    +* +* @note +* +******************************************************************************/ +/****************************** Include Files *********************************/ + +#include "md5.h" + +/******************************************************************************/ +/** +* +* This function sets the memory +* +* @param dest +* +* @param ch +* +* @param count +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void * MD5Memset( void *dest, int ch, u32 count ) +{ + register char *dst8 = (char*)dest; + + while( count-- ) + *dst8++ = ch; + + return dest; +} + +/******************************************************************************/ +/** +* +* This function copy the memory +* +* @param dest +* +* @param ch +* +* @param count +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void * MD5Memcpy( void *dest, const void *src, + u32 count, boolean doByteSwap ) +{ + register char * dst8 = (char*)dest; + register char * src8 = (char*)src; + + if( doByteSwap == FALSE ) { + while( count-- ) + *dst8++ = *src8++; + } else { + count /= sizeof( u32 ); + + while( count-- ) { + dst8[ 0 ] = src8[ 3 ]; + dst8[ 1 ] = src8[ 2 ]; + dst8[ 2 ] = src8[ 1 ]; + dst8[ 3 ] = src8[ 0 ]; + + dst8 += 4; + src8 += 4; + } + } + + return dest; +} + +/******************************************************************************/ +/** +* +* This function is the core of the MD5 algorithm, +* this alters an existing MD5 hash to +* reflect the addition of 16 longwords of new data. MD5Update blocks +* the data and converts bytes into longwords for this routine. +* +* Use binary integer part of the sine of integers (Radians) as constants. +* Calculated as: +* +* for( i = 0; i < 63; i++ ) +* k[ i ] := floor( abs( sin( i + 1 ) ) Ă— pow( 2, 32 ) ) +* +* Following number is the per-round shift amount. +* +* @param dest +* +* @param ch +* +* @param count +* +* @return None +* +* @note None +* +****************************************************************************/ +void MD5Transform( u32 *buffer, u32 *intermediate ) +{ + register u32 a, b, c, d; + + a = buffer[ 0 ]; + b = buffer[ 1 ]; + c = buffer[ 2 ]; + d = buffer[ 3 ]; + + MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 ); + MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 ); + MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 ); + MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 ); + MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 ); + MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 ); + MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 ); + MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 ); + MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 ); + MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 ); + MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 ); + MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 ); + MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 ); + MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 ); + MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 ); + MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 ); + + MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 ); + MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 ); + MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 ); + MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 ); + MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 ); + MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 ); + MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 ); + MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 ); + MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 ); + MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 ); + MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 ); + MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 ); + MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 ); + MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 ); + MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 ); + MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 ); + + MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 ); + MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 ); + MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 ); + MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 ); + MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 ); + MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 ); + MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 ); + MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 ); + MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 ); + MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 ); + MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 ); + MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 ); + MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 ); + MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 ); + MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 ); + MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 ); + + MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 ); + MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 ); + MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 ); + MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 ); + MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 ); + MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 ); + MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 ); + MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 ); + MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 ); + MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 ); + MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 ); + MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 ); + MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 ); + MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 ); + MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 ); + MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 ); + + buffer[ 0 ] += a; + buffer[ 1 ] += b; + buffer[ 2 ] += c; + buffer[ 3 ] += d; + +} + +/******************************************************************************/ +/** +* +* This function Start MD5 accumulation +* Set bit count to 0 and buffer to mysterious initialization constants +* +* @param +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void MD5Init( MD5Context *context ) +{ + + context->buffer[ 0 ] = 0x67452301; + context->buffer[ 1 ] = 0xefcdab89; + context->buffer[ 2 ] = 0x98badcfe; + context->buffer[ 3 ] = 0x10325476; + + context->bits[ 0 ] = 0; + context->bits[ 1 ] = 0; + +} + + +/******************************************************************************/ +/** +* +* This function updates context to reflect the concatenation of another +* buffer full of bytes +* +* @param +* +* @param +* +* @param +* +* @param +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void MD5Update( MD5Context *context, u8 *buffer, + u32 len, boolean doByteSwap ) +{ + register u32 temp; + register u8 * p; + + /* + * Update bitcount + */ + + temp = context->bits[ 0 ]; + + if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) { + /* + * Carry from low to high + */ + context->bits[ 1 ]++; + } + + context->bits[ 1 ] += len >> 29; + + /* + * Bytes already in shsInfo->data + */ + + temp = ( temp >> 3 ) & 0x3f; + + /* + * Handle any leading odd-sized chunks + */ + + if( temp ) { + p = (u8 *)context->intermediate + temp; + + temp = MD5_SIGNATURE_BYTE_SIZE - temp; + + if( len < temp ) { + MD5Memcpy( p, buffer, len, doByteSwap ); + return; + } + + MD5Memcpy( p, buffer, temp, doByteSwap ); + + MD5Transform( context->buffer, (u32 *)context->intermediate ); + + buffer += temp; + len -= temp; + + } + + /* + * Process data in 64-byte, 512 bit, chunks + */ + + while( len >= MD5_SIGNATURE_BYTE_SIZE ) { + MD5Memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE, + doByteSwap ); + + MD5Transform( context->buffer, (u32 *)context->intermediate ); + + buffer += MD5_SIGNATURE_BYTE_SIZE; + len -= MD5_SIGNATURE_BYTE_SIZE; + + } + + /* + * Handle any remaining bytes of data + */ + MD5Memcpy( context->intermediate, buffer, len, doByteSwap ); + +} + +/******************************************************************************/ +/** +* +* This function final wrap-up - pad to 64-byte boundary with the bit pattern +* 1 0* (64-bit count of bits processed, MSB-first +* +* @param +* +* @param +* +* @param +* +* @param +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void MD5Final( MD5Context *context, u8 *digest, + boolean doByteSwap ) +{ + u32 count; + u8 * p; + + /* + * Compute number of bytes mod 64 + */ + count = ( context->bits[ 0 ] >> 3 ) & 0x3F; + + /* + * Set the first char of padding to 0x80. This is safe since there is + * always at least one byte free + */ + p = context->intermediate + count; + *p++ = 0x80; + + /* + * Bytes of padding needed to make 64 bytes + */ + count = MD5_SIGNATURE_BYTE_SIZE - 1 - count; + + /* + * Pad out to 56 mod 64 + */ + if( count < 8 ) { + /* + * Two lots of padding: Pad the first block to 64 bytes + */ + MD5Memset( p, 0, count ); + + MD5Transform( context->buffer, (u32 *)context->intermediate ); + + /* + * Now fill the next block with 56 bytes + */ + MD5Memset( context->intermediate, 0, 56 ); + } else { + /* + * Pad block to 56 bytes + */ + MD5Memset( p, 0, count - 8 ); + } + + /* + * Append length in bits and transform + */ + ( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ]; + ( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ]; + + MD5Transform( context->buffer, (u32 *)context->intermediate ); + + /* + * Now return the digest + */ + MD5Memcpy( digest, context->buffer, 16, doByteSwap ); +} + +/******************************************************************************/ +/** +* +* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at +* 'input'. 'digest' must have enough space to hold 16 bytes +* +* @param +* +* @param +* +* @param +* +* @param +* +* @return None +* +* @note None +* +****************************************************************************/ +void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap ) +{ + MD5Context context; + + MD5Init( &context ); + + MD5Update( &context, input, len, doByteSwap ); + + MD5Final( &context, digest, doByteSwap ); +} diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/md5.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/md5.h new file mode 100644 index 0000000..1b28ddd --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/md5.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file md5.h +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00a sgd	05/17/13 Initial release
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___MD5_H___ +#define ___MD5_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +#define MD5_SIGNATURE_BYTE_SIZE 64 + +/**************************** Type Definitions *******************************/ + +typedef u8 boolean; +typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ]; + +struct MD5Context + { + u32 buffer[ 4 ]; + u32 bits[ 2 ]; + signature intermediate; + }; +typedef struct MD5Context MD5Context; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/* + * The four core functions - F1 is optimized somewhat + */ +#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) ) +#define F2( x, y, z ) F1( z, x, y ) +#define F3( x, y, z ) ( x ^ y ^ z ) +#define F4( x, y, z ) ( y ^ ( x | ~z ) ) + + +/* + * This is the central step in the MD5 algorithm + */ +#define MD5_STEP( f, w, x, y, z, data, s ) \ + ( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x ) + + +/************************** Function Prototypes ******************************/ + +void * MD5Memset( void *dest, int ch, u32 count ); + +void * MD5Memcpy( void *dest, const void *src, u32 count, boolean doByteSwap ); + +void MD5Transform( u32 *buffer, u32 *intermediate ); + +void MD5Init( MD5Context *context ); + +void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap ); + +void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap ); + +void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap ); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + + +#endif /* ___MD5_H___ */ diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nand.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nand.c new file mode 100644 index 0000000..9bf4ec0 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nand.c @@ -0,0 +1,295 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file nand.c +* +* Contains code for the NAND FLASH functionality. Bad Block management +* is simple: skip the bad blocks and keep going. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 2.00a  mb	25/05/12 fsbl changes for standalone bsp based
+* 3.00a sgd	30/01/13 Code cleanup
+* 5.00a sgd	17/05/13 Support for Multi Boot
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xparameters.h" +#include "fsbl.h" +#ifdef XPAR_PS7_NAND_0_BASEADDR +#include "nand.h" +#include "xnandps_bbm.h" + + +/************************** Constant Definitions *****************************/ + +#define NAND_DEVICE_ID XPAR_XNANDPS_0_DEVICE_ID + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr, + u64 Offset, + u32 Length); + +/************************** Variable Definitions *****************************/ + +extern u32 FlashReadBaseAddress; +extern u32 FlashOffsetAddress; + +XNandPs *NandInstPtr; +XNandPs NandInstance; /* XNand Instance. */ + +/******************************************************************************/ +/** +* +* This function initializes the controller for the NAND FLASH interface. +* +* @param none +* +* @return +* - XST_SUCCESS if the controller initializes correctly +* - XST_FAILURE if the controller fails to initializes correctly +* +* @note none. +* +****************************************************************************/ +u32 InitNand(void) +{ + + u32 Status; + XNandPs_Config *ConfigPtr; + + /* + * Set up pointers to instance and the config structure + */ + NandInstPtr = &NandInstance; + + /* + * Initialize the flash driver. + */ + ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE_ID); + + if (ConfigPtr == NULL) { + fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r"); + return XST_FAILURE; + } + + Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr, + ConfigPtr->SmcBase,ConfigPtr->FlashBase); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"NAND intialization failed \n \r"); + return XST_FAILURE; + } + + /* + * Set up base address for access + */ + FlashReadBaseAddress = XPS_NAND_BASEADDR; + + fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n", + NandInstPtr->Geometry.FlashWidth); + + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n", + Status); + return XST_FAILURE; + } + + /* + * set up the FLASH access pointers + */ + fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r"); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** +* +* This function provides the NAND FLASH interface for the Simplified header +* functionality. This function handles bad blocks. +* +* The source address is the absolute good address, bad blocks are skipped +* without incrementing the source address. +* +* @param SourceAddress is address in FLASH data space, absolute good address +* @param DestinationAddress is address in OCM data space +* +* @return XST_SUCCESS if the transfer completes correctly +* XST_FAILURE if the transfer fails to completes correctly +* +* @note none. +* +****************************************************************************/ +u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes) +{ + u32 ActLen; + u32 BlockOffset; + u32 Block; + u32 Status; + u32 BytesLeft = LengthBytes; + u32 BlockSize = NandInstPtr->Geometry.BlockSize; + u8 *BufPtr = (u8 *)DestinationAddress; + u32 ReadLen; + u32 BlockReadLen; + u32 Offset; + u32 TmpAddress = 0 ; + u32 BlockCount = 0; + u32 BadBlocks = 0; + + /* + * First get bad blocks before the source address + */ + while (TmpAddress < SourceAddress) { + while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) == + XST_SUCCESS) { + BlockCount ++; + BadBlocks ++; + } + + TmpAddress += BlockSize; + BlockCount ++; + } + + Offset = SourceAddress + BadBlocks * BlockSize; + + /* + * Calculate the actual length including bad blocks + */ + ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes); + + /* + * Check if the actual length cross flash size + */ + if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) { + return XST_FAILURE; + } + + while (BytesLeft > 0) { + BlockOffset = Offset & (BlockSize - 1); + Block = (Offset & ~(BlockSize - 1))/BlockSize; + BlockReadLen = BlockSize - BlockOffset; + + Status = XNandPs_IsBlockBad(NandInstPtr, Block); + if (Status == XST_SUCCESS) { + /* Move to next block */ + Offset += BlockReadLen; + continue; + } + + /* + * Check if we cross block boundary + */ + if (BytesLeft < BlockReadLen) { + ReadLen = BytesLeft; + } else { + ReadLen = BlockReadLen; + } + + /* + * Read from the NAND flash + */ + Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL); + if (Status != XST_SUCCESS) { + return Status; + } + BytesLeft -= ReadLen; + Offset += ReadLen; + BufPtr += ReadLen; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function returns the length including bad blocks from a given offset and +* length. +* +* @param NandInstPtr is the pointer to the XNandPs instance. +* @param Offset is the flash data address to read from. +* @param Length is number of bytes to read. +* +* @return +* - Return actual length including bad blocks. +* +* @note None. +* +******************************************************************************/ +static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr, + u64 Offset, + u32 Length) +{ + u32 BlockSize = NandInstPtr->Geometry.BlockSize; + u32 CurBlockLen; + u32 CurBlock; + u32 Status; + u32 TempLen = 0; + u32 ActLen = 0; + + while (TempLen < Length) { + CurBlockLen = BlockSize - (Offset & (BlockSize - 1)); + CurBlock = (Offset & ~(BlockSize - 1))/BlockSize; + + /* + * Check if the block is bad + */ + Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock); + if (Status != XST_SUCCESS) { + /* Good Block */ + TempLen += CurBlockLen; + } + ActLen += CurBlockLen; + Offset += CurBlockLen; + if (Offset >= NandInstPtr->Geometry.DeviceSize) { + break; + } + } + + return ActLen; +} + +#endif diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nand.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nand.h new file mode 100644 index 0000000..1f5ee52 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nand.h @@ -0,0 +1,91 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file nand.h +* +* This file contains the interface for the NAND FLASH functionality +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 2.00a mb	30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
+* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___NAND_H___ +#define ___NAND_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + + +#ifdef XPAR_PS7_NAND_0_BASEADDR + +#include "xnandps.h" +#include "xnandps_bbm.h" +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +u32 InitNand(void); + +u32 NandAccess( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthWords); +#endif +/************************** Variable Definitions *****************************/ + + +#ifdef __cplusplus +} +#endif + + +#endif /* ___NAND_H___ */ + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nor.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nor.c new file mode 100644 index 0000000..4705bcc --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nor.c @@ -0,0 +1,144 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file nor.c +* +* Contains code for the NOR FLASH functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 2.00a mb	25/05/12 mio init removed
+* 3.00a sgd	30/01/13 Code cleanup
+*
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "fsbl.h" +#include "nor.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +extern u32 FlashReadBaseAddress; + +/******************************************************************************/ +/******************************************************************************/ +/** +* +* This function initializes the controller for the NOR FLASH interface. +* +* @param None +* +* @return None +* +* @note None. +* +****************************************************************************/ +void InitNor(void) +{ + + /* + * Set up the base address for access + */ + FlashReadBaseAddress = XPS_NOR_BASEADDR; +} + +/******************************************************************************/ +/** +* +* This function provides the NOR FLASH interface for the Simplified header +* functionality. +* +* @param SourceAddress is address in FLASH data space +* @param DestinationAddress is address in OCM data space +* @param LengthBytes is the data length to transfer in bytes +* +* @return +* - XST_SUCCESS if the write completes correctly +* - XST_FAILURE if the write fails to completes correctly +* +* @note None. +* +****************************************************************************/ +u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes) +{ + u32 Data; + u32 Count; + u32 *SourceAddr; + u32 *DestAddr; + u32 LengthWords; + + /* + * check for non-word tail + * add bytes to cover the end + */ + if ((LengthBytes%4) != 0){ + + LengthBytes += (4 - (LengthBytes & 0x00000003)); + } + + LengthWords = LengthBytes >> WORD_LENGTH_SHIFT; + + SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress); + DestAddr = (u32 *)(DestinationAddress); + + /* + * Word transfers, endianism isn't an issue + */ + for (Count=0; Count < LengthWords; Count++){ + + Data = Xil_In32((u32)(SourceAddr++)); + Xil_Out32((u32)(DestAddr++), Data); + } + + return XST_SUCCESS; +} + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nor.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nor.h new file mode 100644 index 0000000..4c15825 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/nor.h @@ -0,0 +1,87 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file nor.h +* +* This file contains the interface for the NOR FLASH functionality +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___NOR_H___ +#define ___NOR_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +/************************** Constant Definitions *****************************/ + +#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + + +void InitNor(void); + +u32 NorAccess( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthBytes); + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + + +#endif /* ___NOR_H___ */ + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/pcap.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/pcap.c new file mode 100644 index 0000000..40351c8 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/pcap.c @@ -0,0 +1,816 @@ +/***************************************************************************** +* +* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file pcap.c +* +* Contains code for enabling and accessing the PCAP +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	02/10/10	Initial release
+* 2.00a jz	05/28/11	Add SD support
+* 2.00a mb	25/05/12	using the EDK provided devcfg driver
+* 						Nand/SD encryption and review comments
+* 3.00a mb  16/08/12	Added the poll function
+*						Removed the FPGA_RST_CTRL define
+*						Added the flag for NON PS instantiated bitstream
+* 4.00a sgd 02/28/13	Fix for CR#681014 - ECC init in FSBL should not call
+*                                           fabric_init()
+* 						Fix for CR#689026 - FSBL doesn't hold PL resets active
+* 						                    during bit download
+* 						Fix for CR#699475 - FSBL functionality is broken and
+* 						                    its not able to boot in QSPI/NAND
+* 						                    bootmode
+*						Fix for CR#705664 - FSBL fails to decrypt the
+*						                    bitstream when the image is AES
+*						                    encrypted using non-zero key value
+* 6.00a kc  08/30/13    Fix for CR#722979 - Provide customer-friendly
+*                                           changelogs in FSBL
+* 7.00a kc	10/25/13	Fix for CR#724620 - How to handle PCAP_MODE after
+*						                    bitstream configuration
+*						Fix for CR#726178 - FabricInit() PROG_B is kept active
+*						                    for 5mS.
+* 						Fix for CR#731839 - FSBL has to check the
+* 											HMAC error status after decryption
+*			12/04/13	Fix for CR#764382 - How to handle PCAP_MODE after
+*						                    bitstream configuration - PCAP_MODE
+*											and PCAP_PR bits are not modified
+* 8.00a kc  2/20/14		Fix for CR#775631 - FSBL: FsblGetGlobalTimer() 
+*						is not proper
+* 10.00a kc 07/24/14    Fix for CR#809336 - Minor code cleanup
+* 13.00a ssc 04/10/15   Fix for CR#846899 - Corrected logic to clear
+*                                           DMA done count
+* 15.00a gan 07/21/16   Fix for CR# 953654 -(2016.3)FSBL -
+* 											In pcap.c/pcap.h/main.h,
+* 											Fabric Initialization sequence
+* 											is modified to check the PL power
+* 											before sequence starts and checking
+* 											INIT_B reset status twice in case
+* 											of failure.
+* 16.00a gan 08/02/16   Fix for CR# 955897 -(2016.3)FSBL -
+* 											In pcap.c, check pl power
+* 											through MCTRL register for
+* 											3.0 and later versions of silicon.
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "pcap.h" +#include "nand.h" /* For NAND geometry information */ +#include "fsbl.h" +#include "image_mover.h" /* For MoveImage */ +#include "xparameters.h" +#include "xil_exception.h" +#include "xdevcfg.h" +#include "sleep.h" +#include "xtime_l.h" + +#ifdef XPAR_XWDTPS_0_BASEADDR +#include "xwdtps.h" +#endif +/************************** Constant Definitions *****************************/ +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are only defined here such that a user can easily + * change all the needed parameters in one place. + */ + +#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount); + +/************************** Variable Definitions *****************************/ +/* Devcfg driver instance */ +static XDcfg DcfgInstance; +XDcfg *DcfgInstPtr; +extern u32 Silicon_Version; +#ifdef XPAR_XWDTPS_0_BASEADDR +extern XWdtPs Watchdog; /* Instance of WatchDog Timer */ +#endif + +/******************************************************************************/ +/** +* +* This function transfer data using PCAP +* +* @param SourceDataPtr is a pointer to where the data is read from +* @param DestinationDataPtr is a pointer to where the data is written to +* @param SourceLength is the length of the data to be moved in words +* @param DestinationLength is the length of the data to be moved in words +* @param SecureTransfer indicated the encryption key location, 0 for +* non-encrypted +* +* @return +* - XST_SUCCESS if the transfer is successful +* - XST_FAILURE if the transfer fails +* +* @note None +* +****************************************************************************/ +u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr, + u32 SourceLength, u32 DestinationLength, u32 SecureTransfer) +{ + u32 Status; + u32 IntrStsReg; + u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE; + + /* + * Check for secure transfer + */ + if (SecureTransfer) { + PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE; + } + +#ifdef FSBL_PERF + XTime tXferCur = 0; + FsblGetGlobalTime(&tXferCur); +#endif + + /* + * Clear the PCAP status registers + */ + Status = ClearPcapStatus(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n"); + return XST_FAILURE; + } + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Prevent WDT reset + */ + XWdtPs_RestartWdt(&Watchdog); +#endif + + /* + * PCAP single DMA transfer setup + */ + SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER); + DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER); + + /* + * Transfer using Device Configuration + */ + Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr, + SourceLength, + (u8 *)DestinationDataPtr, + DestinationLength, PcapTransferType); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status); + return XST_FAILURE; + } + + /* + * Dump the PCAP registers + */ + PcapDumpRegisters(); + + /* + * Poll for the DMA done + */ + Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n"); + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r"); + + /* + * Check for errors + */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) { + fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n"); + return XST_FAILURE; + } + + /* + * For Performance measurement + */ +#ifdef FSBL_PERF + XTime tXferEnd = 0; + fsbl_printf(DEBUG_GENERAL,"Time taken is "); + FsblMeasurePerfTime(tXferCur,tXferEnd); +#endif + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function loads PL partition using PCAP +* +* @param SourceDataPtr is a pointer to where the data is read from +* @param DestinationDataPtr is a pointer to where the data is written to +* @param SourceLength is the length of the data to be moved in words +* @param DestinationLength is the length of the data to be moved in words +* @param SecureTransfer indicated the encryption key location, 0 for +* non-encrypted +* +* @return +* - XST_SUCCESS if the transfer is successful +* - XST_FAILURE if the transfer fails +* +* @note None +* +****************************************************************************/ +u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr, + u32 SourceLength, u32 DestinationLength, u32 SecureTransfer) +{ + u32 Status; + u32 IntrStsReg; + u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE; + + /* + * Check for secure transfer + */ + if (SecureTransfer) { + PcapTransferType = XDCFG_SECURE_PCAP_WRITE; + } + +#ifdef FSBL_PERF + XTime tXferCur = 0; + FsblGetGlobalTime(&tXferCur); +#endif + + /* + * Clear the PCAP status registers + */ + Status = ClearPcapStatus(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n"); + return XST_FAILURE; + } + + /* + * For Bitstream case destination address will be 0xFFFFFFFF + */ + DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS; + + /* + * New Bitstream download initialization sequence + */ + Status = FabricInit(); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Prevent WDT reset + */ + XWdtPs_RestartWdt(&Watchdog); +#endif + + /* + * PCAP single DMA transfer setup + */ + SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER); + DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER); + + /* + * Transfer using Device Configuration + */ + Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr, + SourceLength, + (u8 *)DestinationDataPtr, + DestinationLength, PcapTransferType); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status); + return XST_FAILURE; + } + + + /* + * Dump the PCAP registers + */ + PcapDumpRegisters(); + + + /* + * Poll for the DMA done + */ + Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n"); + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r"); + + /* + * Poll for FPGA Done + */ + Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n"); + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r"); + + /* + * Check for errors + */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) { + fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n"); + return XST_FAILURE; + } + + /* + * For Performance measurement + */ +#ifdef FSBL_PERF + XTime tXferEnd = 0; + fsbl_printf(DEBUG_GENERAL,"Time taken is "); + FsblMeasurePerfTime(tXferCur,tXferEnd); +#endif + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** +* +* This function Initializes the PCAP driver. +* +* @param none +* +* @return +* - XST_SUCCESS if the pcap driver initialization is successful +* - XST_FAILURE if the pcap driver initialization fails +* +* @note none +* +****************************************************************************/ +int InitPcap(void) +{ + XDcfg_Config *ConfigPtr; + int Status = XST_SUCCESS; + DcfgInstPtr = &DcfgInstance; + + /* + * Initialize the Device Configuration Interface driver. + */ + ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID); + + Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr, + ConfigPtr->BaseAddr); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} +/******************************************************************************/ +/** +* +* This function programs the Fabric for use. +* +* @param None +* +* @return +* - XST_SUCCESS if the Fabric initialization is successful +* - XST_FAILURE if the Fabric initialization fails +* @note None +* +****************************************************************************/ +u32 FabricInit(void) +{ + u32 PcapReg; + u32 PcapCtrlRegVal; + u32 StatusReg; + u32 MctrlReg; + u32 PcfgInit; + u32 TimerExpired=0; + XTime tCur=0; + XTime tEnd=0; + + + /* + * Set Level Shifters DT618760 - PS to PL enabling + */ + Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL); + fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n", + Xil_In32(PS_LVL_SHFTR_EN)); + + /* + * Get DEVCFG controller settings + */ + PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + /* + * Check the PL power status + */ + if(Silicon_Version >= SILICON_VERSION_3) + { + MctrlReg = XDcfg_GetMiscControlRegister(DcfgInstPtr); + + if((MctrlReg & XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) != + XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) + { + fsbl_printf(DEBUG_INFO,"Fabric not powered up\r\n"); + return XST_FAILURE; + } + } + + + /* + * Setting PCFG_PROG_B signal to high + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Check for AES source key + */ + PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr); + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * 5msec delay + */ + usleep(5000); + } + + /* + * Setting PCFG_PROG_B signal to low + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Check for AES source key + */ + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * 5msec delay + */ + usleep(5000); + } + + /* + * Polling the PCAP_INIT status for Reset or timeout + */ + + XTime_GetTime(&tCur); + do + { + PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) & + XDCFG_STATUS_PCFG_INIT_MASK); + if(PcfgInit == 0) + { + break; + } + XTime_GetTime(&tEnd); + if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd) + { + TimerExpired = 1; + } + + } while(!TimerExpired); + + if(TimerExpired == 1) + { + TimerExpired = 0; + /* + * Came here due to expiration and PCAP_INIT is set. + * Retry PCFG_PROG_B High -> Low again + */ + + /* + * Setting PCFG_PROG_B signal to high + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Check for AES source key + */ + PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr); + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * 5msec delay + */ + usleep(5000); + } + + /* + * Setting PCFG_PROG_B signal to low + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Check for AES source key + */ + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * 5msec delay + */ + usleep(5000); + } + /* + * Polling the PCAP_INIT status for Reset or timeout (second iteration) + */ + + XTime_GetTime(&tCur); + do + { + PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) & + XDCFG_STATUS_PCFG_INIT_MASK); + if(PcfgInit == 0) + { + break; + } + XTime_GetTime(&tEnd); + if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd) + { + TimerExpired = 1; + } + + } while(!TimerExpired); + + if(TimerExpired == 1) + { + /* + * Came here due to PCAP_INIT is not getting reset + * for PCFG_PROG_B signal High -> Low + */ + fsbl_printf(DEBUG_INFO,"Fabric Init failed\r\n"); + return XST_FAILURE; + } + } + + /* + * Setting PCFG_PROG_B signal to high + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Polling the PCAP_INIT status for Set + */ + while(!(XDcfg_GetStatusRegister(DcfgInstPtr) & + XDCFG_STATUS_PCFG_INIT_MASK)); + + /* + * Get Device configuration status + */ + StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr); + fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg); + + fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n"); + + return XST_SUCCESS; +} +/******************************************************************************/ +/** +* +* This function Clears the PCAP status registers. +* +* @param None +* +* @return +* - XST_SUCCESS if the pcap status registers are cleared +* - XST_FAILURE if errors are there +* - XST_DEVICE_BUSY if Pcap device is busy +* @note None +* +****************************************************************************/ +u32 ClearPcapStatus(void) +{ + + u32 StatusReg; + u32 IntStatusReg; + + /* + * Clear it all, so if Boot ROM comes back, it can proceed + */ + XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF); + + /* + * Get PCAP Interrupt Status Register + */ + IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr); + if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) { + fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n", + IntStatusReg); + return XST_FAILURE; + } + + /* + * Read the PCAP status register for DMA status + */ + StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr); + + fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg); + + /* + * If the queue is full, return w/ XST_DEVICE_BUSY + */ + if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK) { + + fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n"); + return XST_DEVICE_BUSY; + } + + fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n"); + + /* + * There are unacknowledged DMA commands outstanding + */ + if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) != + XDCFG_STATUS_DMA_CMD_Q_E_MASK) { + + IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr); + + if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) != + XDCFG_IXR_DMA_DONE_MASK){ + /* + * Error state, transfer cannot occur + */ + fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n"); + return XST_FAILURE; + } + else { + /* + * clear out the status + */ + XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK); + } + } + + if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) { + XDcfg_SetStatusRegister(DcfgInstPtr, StatusReg | + XDCFG_STATUS_DMA_DONE_CNT_MASK); + } + + fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n"); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** +* +* This function prints PCAP register status. +* +* @param none +* +* @return none +* +* @note none +* +****************************************************************************/ +void PcapDumpRegisters (void) { + + fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n"); + + fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET)); +} + +/******************************************************************************/ +/** +* +* This function Polls for the DMA done or FPGA done. +* +* @param none +* +* @return +* - XST_SUCCESS if polling for DMA/FPGA done is successful +* - XST_FAILURE if polling for DMA/FPGA done fails +* +* @note none +* +****************************************************************************/ +int XDcfgPollDone(u32 MaskValue, u32 MaxCount) +{ + int Count = MaxCount; + u32 IntrStsReg = 0; + + /* + * poll for the DMA done + */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + while ((IntrStsReg & MaskValue) != + MaskValue) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + Count -=1; + + if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) { + fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n", + IntrStsReg); + PcapDumpRegisters(); + return XST_FAILURE; + } + + if(!Count) { + fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n"); + return XST_FAILURE; + } + if (Count > (MAX_COUNT-100)) { + fsbl_printf(DEBUG_GENERAL,"."); + } + } + + fsbl_printf(DEBUG_GENERAL,"\n\r"); + + XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue); + + return XST_SUCCESS; +} diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/pcap.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/pcap.h new file mode 100644 index 0000000..d9400b0 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/pcap.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file pcap.h +* +* This file contains the interface for intiializing and accessing the PCAP +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	02/10/10 Initial release
+* 2.00a mb  16/08/12 Added the macros and function prototypes
+* 15.00a gan 07/21/16   953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
+* 						Fabric Initialization sequence is modified to check
+* 						the PL power before sequence starts and checking INIT_B
+* 						reset status twice in case of failure.
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___PCAP_H___ +#define ___PCAP_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xdevcfg.h" + +/************************** Function Prototypes ******************************/ + + +/* Multiboot register offset mask */ +#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF +#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000 +/*Miscellaneous Control Register mask*/ +#define XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK 0x00000100 +#define COUNTS_PER_MILLI_SECOND (COUNTS_PER_SECOND/1000) + +#define PCAP_LAST_TRANSFER 1 +#define MAX_COUNT 1000000000 +#define LVL_PL_PS 0x0000000F +#define LVL_PS_PL 0x0000000A + +/* Fix for #672779 */ +#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + +int InitPcap(void); +void PcapDumpRegisters(void); +u32 ClearPcapStatus(void); +u32 FabricInit(void); +int XDcfgPollDone(u32 MaskValue, u32 MaxCount); +u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength, + u32 DestinationLength, u32 Flags); +u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength, + u32 DestinationLength, u32 Flags); +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + + +#endif /* ___PCAP_H___ */ + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.c new file mode 100644 index 0000000..cd8a445 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.c @@ -0,0 +1,12946 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B00[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: TRACE CURRENT PORT SIZE + // .. FINISH: TRACE CURRENT PORT SIZE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: OUTPUT ENABLE + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: I2C RESET + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: TRACE CURRENT PORT SIZE + // .. FINISH: TRACE CURRENT PORT SIZE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: OUTPUT ENABLE + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: I2C RESET + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: TRACE CURRENT PORT SIZE + // .. FINISH: TRACE CURRENT PORT SIZE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: OUTPUT ENABLE + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: I2C RESET + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.h new file mode 100644 index 0000000..7b2f445 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.h @@ -0,0 +1,140 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 25000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 23809523 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 50000000 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/qspi.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/qspi.c new file mode 100644 index 0000000..6fdf055 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/qspi.c @@ -0,0 +1,764 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file qspi.c +* +* Contains code for the QSPI FLASH functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 3.00a mb  25/06/12 InitQspi, data is read first and required config bits
+*                    are set
+* 4.00a sg	02/28/13 Cleanup
+* 					 Removed LPBK_DLY_ADJ register setting code as we use
+* 					 divisor 8
+* 5.00a sgd	05/17/13 Added Flash Size > 128Mbit support
+* 					 Dual Stack support
+*					 Fix for CR:721674 - FSBL- Failed to boot from Dual
+*					                     stacked QSPI
+* 6.00a kc  08/30/13 Fix for CR#722979 - Provide customer-friendly
+*                                        changelogs in FSBL
+*                    Fix for CR#739711 - FSBL not able to read Large QSPI
+*                    					 (512M) in IO Mode
+* 7.00a kc  10/25/13 Fix for CR#739968 - FSBL should do the QSPI config
+*                    					 settings for Dual parallel
+*                    					 configuration in IO mode
+* 14.0 gan 01/13/16  Fix for CR#869081 - (2016.1)FSBL picks the qspi read
+*                                        command from LQSPI_CFG register
+*					 					 instead of hard coded read
+*					 					 command (0x6B).
+*
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "qspi.h" +#include "image_mover.h" + +#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +#include "xqspips_hw.h" +#include "xqspips.h" + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID + +/* + * The following constants define the commands which may be sent to the FLASH + * device. + */ +#define QUAD_READ_CMD 0x6B +#define READ_ID_CMD 0x9F + +#define WRITE_ENABLE_CMD 0x06 +#define BANK_REG_RD 0x16 +#define BANK_REG_WR 0x17 +/* Bank register is called Extended Address Reg in Micron */ +#define EXTADD_REG_RD 0xC8 +#define EXTADD_REG_WR 0xC5 + +#define COMMAND_OFFSET 0 /* FLASH instruction */ +#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */ +#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */ +#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */ +#define DATA_OFFSET 4 /* Start of Data for Read/Write */ +#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad + reads */ +#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and + quad reads */ +#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */ +#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */ +#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */ +/* + * The following constants specify the extra bytes which are sent to the + * FLASH on the QSPI interface, that are not data, but control information + * which includes the command and address + */ +#define OVERHEAD_SIZE 4 + +/* + * The following constants specify the max amount of data and the size of the + * the buffer required to hold the data and overhead to transfer the data to + * and from the FLASH. + */ +#define DATA_SIZE 4096 + +/* + * The following defines are for dual flash interface. + */ +#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */ +#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between + address and return data */ + +#define SINGLE_QSPI_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \ + LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + +#define DUAL_QSPI_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \ + XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \ + XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \ + LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + +#define DUAL_STACK_CONFIG_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \ + LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + +#define SINGLE_QSPI_IO_CONFIG_QUAD_READ (LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + +#define DUAL_QSPI_IO_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \ + XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \ + LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +XQspiPs QspiInstance; +XQspiPs *QspiInstancePtr; +u32 QspiFlashSize; +u32 QspiFlashMake; +extern u32 FlashReadBaseAddress; +extern u8 LinearBootDeviceFlag; + +/* + * The following variables are used to read and write to the eeprom and they + * are global to avoid having large buffers on the stack + */ +u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE]; +u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE]; + +/******************************************************************************/ +/** +* +* This function initializes the controller for the QSPI interface. +* +* @param None +* +* @return None +* +* @note None +* +****************************************************************************/ +u32 InitQspi(void) +{ + XQspiPs_Config *QspiConfig; + int Status; + + QspiInstancePtr = &QspiInstance; + + /* + * Set up the base address for access + */ + FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR; + + /* + * Initialize the QSPI driver so that it's ready to use + */ + QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID); + if (NULL == QspiConfig) { + return XST_FAILURE; + } + + Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig, + QspiConfig->BaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Set Manual Chip select options and drive HOLD_B pin high. + */ + XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION | + XQSPIPS_HOLD_B_DRIVE_OPTION); + + /* + * Set the prescaler for QSPI clock + */ + XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8); + + /* + * Assert the FLASH chip select. + */ + XQspiPs_SetSlaveSelect(QspiInstancePtr); + + /* + * Read Flash ID and extract Manufacture and Size information + */ + Status = FlashReadID(); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + if (XPAR_PS7_QSPI_0_QSPI_MODE == SINGLE_FLASH_CONNECTION) { + + fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n"); + /* + * For Flash size <128Mbit controller configured in linear mode + */ + if (QspiFlashSize <= FLASH_SIZE_16MB) { + LinearBootDeviceFlag = 1; + + /* + * Enable linear mode + */ + XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION | + XQSPIPS_HOLD_B_DRIVE_OPTION); + + /* + * Single linear read + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, SINGLE_QSPI_CONFIG_QUAD_READ); + + /* + * Enable the controller + */ + XQspiPs_Enable(QspiInstancePtr); + } else { + /* + * Single flash IO read + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, SINGLE_QSPI_IO_CONFIG_QUAD_READ); + + /* + * Enable the controller + */ + XQspiPs_Enable(QspiInstancePtr); + } + } + + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) { + + fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n"); + /* + * For Single Flash size <128Mbit controller configured in linear mode + */ + if (QspiFlashSize <= FLASH_SIZE_16MB) { + /* + * Setting linear access flag + */ + LinearBootDeviceFlag = 1; + + /* + * Enable linear mode + */ + XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION | + XQSPIPS_HOLD_B_DRIVE_OPTION); + + /* + * Dual linear read + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_QUAD_READ); + + /* + * Enable the controller + */ + XQspiPs_Enable(QspiInstancePtr); + } else { + /* + * Dual flash IO read + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_IO_CONFIG_QUAD_READ); + + /* + * Enable the controller + */ + XQspiPs_Enable(QspiInstancePtr); + + } + + /* + * Total flash size is two time of single flash size + */ + QspiFlashSize = 2 * QspiFlashSize; + } + + /* + * It is expected to same flash size for both chip selection + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) { + + fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n"); + + QspiFlashSize = 2 * QspiFlashSize; + + /* + * Enable two flash memories on separate buses + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_STACK_CONFIG_READ); + } + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* This function reads serial FLASH ID connected to the SPI interface. +* It then deduces the make and size of the flash and obtains the +* connection mode to point to corresponding parameters in the flash +* configuration table. The flash driver will function based on this and +* it presently supports Micron and Spansion - 128, 256 and 512Mbit and +* Winbond 128Mbit +* +* @param none +* +* @return XST_SUCCESS if read id, otherwise XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +u32 FlashReadID(void) +{ + u32 Status; + + /* + * Read ID in Auto mode. + */ + WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD; + WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */ + WriteBuffer[ADDRESS_2_OFFSET] = 0x00; + WriteBuffer[ADDRESS_3_OFFSET] = 0x00; + + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer, + RD_ID_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n"); + + fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1], + ReadBuffer[2], + ReadBuffer[3]); + + /* + * Deduce flash make + */ + if (ReadBuffer[1] == MICRON_ID) { + QspiFlashMake = MICRON_ID; + fsbl_printf(DEBUG_INFO, "MICRON "); + } else if(ReadBuffer[1] == SPANSION_ID) { + QspiFlashMake = SPANSION_ID; + fsbl_printf(DEBUG_INFO, "SPANSION "); + } else if(ReadBuffer[1] == WINBOND_ID) { + QspiFlashMake = WINBOND_ID; + fsbl_printf(DEBUG_INFO, "WINBOND "); + } else if(ReadBuffer[1] == MACRONIX_ID) { + QspiFlashMake = MACRONIX_ID; + fsbl_printf(DEBUG_INFO, "MACRONIX "); + } + + /* + * Deduce flash Size + */ + if (ReadBuffer[3] == FLASH_SIZE_ID_128M) { + QspiFlashSize = FLASH_SIZE_128M; + fsbl_printf(DEBUG_INFO, "128M Bits\r\n"); + } else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) { + QspiFlashSize = FLASH_SIZE_256M; + fsbl_printf(DEBUG_INFO, "256M Bits\r\n"); + } else if ((ReadBuffer[3] == FLASH_SIZE_ID_512M) + || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_512M)) { + QspiFlashSize = FLASH_SIZE_512M; + fsbl_printf(DEBUG_INFO, "512M Bits\r\n"); + } else if ((ReadBuffer[3] == FLASH_SIZE_ID_1G) + || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_1G)) { + QspiFlashSize = FLASH_SIZE_1G; + fsbl_printf(DEBUG_INFO, "1G Bits\r\n"); + } + + return XST_SUCCESS; +} + + +/****************************************************************************** +* +* This function reads from the serial FLASH connected to the +* QSPI interface. +* +* @param Address contains the address to read data from in the FLASH. +* @param ByteCount contains the number of bytes to read. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void FlashRead(u32 Address, u32 ByteCount) +{ + /* + * Setup the write command with the specified address and data for the + * FLASH + */ + u32 LqspiCrReg; + u8 ReadCommand; + + LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr); + ReadCommand = (u8) (LqspiCrReg & XQSPIPS_LQSPI_CR_INST_MASK); + WriteBuffer[COMMAND_OFFSET] = ReadCommand; + WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16); + WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8); + WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF); + + ByteCount += DUMMY_SIZE; + + /* + * Send the read command to the FLASH to read the specified number + * of bytes from the FLASH, send the read command and address and + * receive the specified number of bytes of data in the data buffer + */ + XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer, + ByteCount + OVERHEAD_SIZE); +} + +/******************************************************************************/ +/** +* +* This function provides the QSPI FLASH interface for the Simplified header +* functionality. +* +* @param SourceAddress is address in FLASH data space +* @param DestinationAddress is address in DDR data space +* @param LengthBytes is the length of the data in Bytes +* +* @return +* - XST_SUCCESS if the write completes correctly +* - XST_FAILURE if the write fails to completes correctly +* +* @note none. +* +****************************************************************************/ +u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes) +{ + u8 *BufferPtr; + u32 Length = 0; + u32 BankSel = 0; + u32 LqspiCrReg; + u32 Status; + u8 BankSwitchFlag = 1; + + /* + * Linear access check + */ + if (LinearBootDeviceFlag == 1) { + /* + * Check for non-word tail, add bytes to cover the end + */ + if ((LengthBytes%4) != 0){ + LengthBytes += (4 - (LengthBytes & 0x00000003)); + } + + memcpy((void*)DestinationAddress, + (const void*)(SourceAddress + FlashReadBaseAddress), + (size_t)LengthBytes); + } else { + /* + * Non Linear access + */ + BufferPtr = (u8*)DestinationAddress; + + /* + * Dual parallel connection actual flash is half + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) { + SourceAddress = SourceAddress/2; + } + + while(LengthBytes > 0) { + /* + * Local of DATA_SIZE size used for read/write buffer + */ + if(LengthBytes > DATA_SIZE) { + Length = DATA_SIZE; + } else { + Length = LengthBytes; + } + + /* + * Dual stack connection + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) { + /* + * Get the current LQSPI configuration value + */ + LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr); + + /* + * Select lower or upper Flash based on sector address + */ + if (SourceAddress >= (QspiFlashSize/2)) { + /* + * Set selection to U_PAGE + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, + LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK); + + /* + * Subtract first flash size when accessing second flash + */ + SourceAddress = SourceAddress - (QspiFlashSize/2); + + fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r"); + + /* + * Assert the FLASH chip select. + */ + XQspiPs_SetSlaveSelect(QspiInstancePtr); + } + } + + /* + * Select bank + */ + if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) { + BankSel = SourceAddress/FLASH_SIZE_16MB; + + fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel); + + Status = SendBankSelect(BankSel); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r"); + return XST_FAILURE; + } + + BankSwitchFlag = 0; + } + + /* + * If data to be read spans beyond the current bank, then + * calculate length in current bank else no change in length + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) { + /* + * In dual parallel mode, check should be for half + * the length. + */ + if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK)) + { + Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress; + /* + * Above length calculated is for single flash + * Length should be doubled since dual parallel + */ + Length = Length * 2; + BankSwitchFlag = 1; + } + } else { + if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK)) + { + Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress; + BankSwitchFlag = 1; + } + } + + /* + * Copying the image to local buffer + */ + FlashRead(SourceAddress, Length); + + /* + * Moving the data from local buffer to DDR destination address + */ + memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length); + + /* + * Updated the variables + */ + LengthBytes -= Length; + + /* + * For Dual parallel connection address increment should be half + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) { + SourceAddress += Length/2; + } else { + SourceAddress += Length; + } + + BufferPtr = (u8*)((u32)BufferPtr + Length); + } + + /* + * Reset Bank selection to zero + */ + Status = SendBankSelect(0); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r"); + return XST_FAILURE; + } + + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) { + + /* + * Reset selection to L_PAGE + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, + LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK)); + + fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r"); + + /* + * Assert the FLASH chip select. + */ + XQspiPs_SetSlaveSelect(QspiInstancePtr); + } + } + + return XST_SUCCESS; +} + + + +/****************************************************************************** +* +* This functions selects the current bank +* +* @param BankSel is the bank to be selected in the flash device(s). +* +* @return XST_SUCCESS if bank selected +* XST_FAILURE if selection failed +* @note None. +* +******************************************************************************/ +u32 SendBankSelect(u8 BankSel) +{ + u32 Status; + + /* + * bank select commands for Micron and Spansion are different + * Macronix bank select is same as Micron + */ + if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) { + /* + * For micron command WREN should be sent first + * except for some specific feature set + */ + WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD; + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL, + WRITE_ENABLE_CMD_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Send the Extended address register write command + * written, no receive buffer required + */ + WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR; + WriteBuffer[ADDRESS_1_OFFSET] = BankSel; + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL, + BANK_SEL_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + if (QspiFlashMake == SPANSION_ID) { + WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR; + WriteBuffer[ADDRESS_1_OFFSET] = BankSel; + + /* + * Send the Extended address register write command + * written, no receive buffer required + */ + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL, + BANK_SEL_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + /* + * For testing - Read bank to verify + */ + if (QspiFlashMake == SPANSION_ID) { + WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD; + WriteBuffer[ADDRESS_1_OFFSET] = 0x00; + + /* + * Send the Extended address register write command + * written, no receive buffer required + */ + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer, + BANK_SEL_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) { + WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD; + WriteBuffer[ADDRESS_1_OFFSET] = 0x00; + + /* + * Send the Extended address register write command + * written, no receive buffer required + */ + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer, + BANK_SEL_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + if (ReadBuffer[1] != BankSel) { + fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel, + ReadBuffer[1]); + return XST_FAILURE; + } + + return XST_SUCCESS; +} +#endif + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/qspi.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/qspi.h new file mode 100644 index 0000000..18dc374 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/qspi.h @@ -0,0 +1,128 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file qspi.h +* +* This file contains the interface for the QSPI FLASH functionality +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 3.00a mb  01/09/12 Added the Delay Values defines for qspi
+* 5.00a sgd	05/17/13 Added Flash Size > 128Mbit support
+* 					 Dual Stack support
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___QSPI_H___ +#define ___QSPI_H___ + +#include "fsbl.h" +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "fsbl.h" + +/************************** Constant Definitions *****************************/ +#define SINGLE_FLASH_CONNECTION 0 +#define DUAL_STACK_CONNECTION 1 +#define DUAL_PARALLEL_CONNECTION 2 +#define FLASH_SIZE_16MB 0x1000000 + +/* + * Bank mask + */ +#define BANKMASK 0xF000000 + +/* + * Identification of Flash + * Micron: + * Byte 0 is Manufacturer ID; + * Byte 1 is first byte of Device ID - 0xBB or 0xBA + * Byte 2 is second byte of Device ID describes flash size: + * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20 + * Spansion: + * Byte 0 is Manufacturer ID; + * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02 + * Byte 2 is second byte of Device ID describes flash size: + * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20 + */ + +#define MICRON_ID 0x20 +#define SPANSION_ID 0x01 +#define WINBOND_ID 0xEF +#define MACRONIX_ID 0xC2 + +#define FLASH_SIZE_ID_128M 0x18 +#define FLASH_SIZE_ID_256M 0x19 +#define FLASH_SIZE_ID_512M 0x20 +#define FLASH_SIZE_ID_1G 0x21 +/* Macronix size constants are different for 512M and 1G */ +#define MACRONIX_FLASH_SIZE_ID_512M 0x1A +#define MACRONIX_FLASH_SIZE_ID_1G 0x1B + +/* + * Size in bytes + */ +#define FLASH_SIZE_128M 0x1000000 +#define FLASH_SIZE_256M 0x2000000 +#define FLASH_SIZE_512M 0x4000000 +#define FLASH_SIZE_1G 0x8000000 + +/************************** Function Prototypes ******************************/ +u32 InitQspi(void); + +u32 QspiAccess( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthBytes); + +u32 FlashReadID(void); +u32 SendBankSelect(u8 BankSel); +/************************** Variable Definitions *****************************/ + + +#ifdef __cplusplus +} +#endif + + +#endif /* ___QSPI_H___ */ + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/rsa.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/rsa.c new file mode 100644 index 0000000..ef6e506 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/rsa.c @@ -0,0 +1,361 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file rsa.c +* +* Contains code for the RSA authentication +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.00a sgd	02/28/13 Initial release
+* 6.00a kc	07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
+* 					 Fix for CR#724165 - Partition Header used by FSBL is
+*                                        not authenticated
+*                    Fix for CR#724166 - FSBL doesn’t use PPK authenticated
+*                                        by Boot ROM for authenticating
+*                                        the Partition images
+*                    Fix for CR#722979 - Provide customer-friendly
+*                                        changelogs in FSBL
+* 9.00a kc  04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
+*					 					 fallback unless FSBL* and FSBL are
+*					 					 identical in length
+*					 Fix for CR#791245 - Use of xilrsa in FSBL
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifdef RSA_SUPPORT +#include "fsbl.h" +#include "rsa.h" +#include "xilrsa.h" + +#ifdef XPAR_XWDTPS_0_BASEADDR +#include "xwdtps.h" +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +#ifdef XPAR_XWDTPS_0_BASEADDR +extern XWdtPs Watchdog; /* Instance of WatchDog Timer */ +#endif + + +/************************** Variable Definitions *****************************/ + +static u8 *PpkModular; +static u8 *PpkModularEx; +static u32 PpkExp; +static u32 PpkAlreadySet=0; + +extern u32 FsblLength; + +void FsblPrintArray (u8 *Buf, u32 Len, char *Str) +{ +#ifdef FSBL_DEBUG_RSA + int Index; + fsbl_printf(DEBUG_INFO, "%s START\r\n", Str); + for (Index=0;Index +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 4.00a sg 02/28/13 Initial release +* +* +* +* @note +* +******************************************************************************/ +#ifndef ___RSA_H___ +#define ___RSA_H___ + +#ifdef __cplusplus +extern "C" { +#endif +/***************************** Include Files *********************************/ + + +#define RSA_PPK_MODULAR_SIZE 256 +#define RSA_PPK_MODULAR_EXT_SIZE 256 +#define RSA_PPK_EXPO_SIZE 64 +#define RSA_SPK_MODULAR_SIZE 256 +#define RSA_SPK_MODULAR_EXT_SIZE 256 +#define RSA_SPK_EXPO_SIZE 64 +#define RSA_SPK_SIGNATURE_SIZE 256 +#define RSA_PARTITION_SIGNATURE_SIZE 256 +#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */ +#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */ +#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */ + +void SetPpk(void ); +u32 AuthenticatePartition(u8 *Buffer, u32 Size); +u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash); + +#ifdef __cplusplus +} +#endif + +#endif /* ___RSA_H___ */ diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/sd.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/sd.c new file mode 100644 index 0000000..9fb8086 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/sd.c @@ -0,0 +1,191 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file sd.c +* +* Contains code for the SD card FLASH functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz	04/28/11 Initial release
+* 7.00a kc  10/18/13 Integrated SD/MMC driver
+* 12.00a ssc 12/11/14 Fix for CR# 839182
+*
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xparameters.h" +#include "fsbl.h" + +#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR) + +#ifndef XPAR_PS7_SD_0_S_AXI_BASEADDR +#define XPAR_PS7_SD_0_S_AXI_BASEADDR XPAR_XSDPS_0_BASEADDR +#endif + +#include "xstatus.h" + +#include "ff.h" +#include "sd.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +extern u32 FlashReadBaseAddress; + + +static FIL fil; /* File object */ +static FATFS fatfs; +static char buffer[32]; +static char *boot_file = buffer; + +/******************************************************************************/ +/******************************************************************************/ +/** +* +* This function initializes the controller for the SD FLASH interface. +* +* @param filename of the file that is to be used +* +* @return +* - XST_SUCCESS if the controller initializes correctly +* - XST_FAILURE if the controller fails to initializes correctly +* +* @note None. +* +****************************************************************************/ +u32 InitSD(const char *filename) +{ + + FRESULT rc; + TCHAR *path = "0:/"; /* Logical drive number is 0 */ + + /* Register volume work area, initialize device */ + rc = f_mount(&fatfs, path, 0); + fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc); + + if (rc != FR_OK) { + return XST_FAILURE; + } + + strcpy_rom(buffer, filename); + boot_file = (char *)buffer; + FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR; + + rc = f_open(&fil, boot_file, FA_READ); + if (rc) { + fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc); + return XST_FAILURE; + } + + return XST_SUCCESS; + +} + +/******************************************************************************/ +/** +* +* This function provides the SD FLASH interface for the Simplified header +* functionality. +* +* @param SourceAddress is address in FLASH data space +* @param DestinationAddress is address in OCM data space +* @param LengthBytes is the number of bytes to move +* +* @return +* - XST_SUCCESS if the write completes correctly +* - XST_FAILURE if the write fails to completes correctly +* +* @note None. +* +****************************************************************************/ +u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes) +{ + + FRESULT rc; /* Result code */ + UINT br; + + rc = f_lseek(&fil, SourceAddress); + if (rc) { + fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %lx\n", SourceAddress); + return XST_FAILURE; + } + + rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br); + + if (rc) { + fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc); + } + + return XST_SUCCESS; + +} /* End of SDAccess */ + + +/******************************************************************************/ +/** +* +* This function closes the file object +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void ReleaseSD(void) { + + f_close(&fil); + return; + + +} +#endif + + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/sd.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/sd.h new file mode 100644 index 0000000..6283eb6 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/sd.h @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file sd.h +* +* This file contains the interface for the Secure Digital (SD) card +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bh	03/10/11 Initial release
+* 7.00a kc  10/18/13 Integrated SD/MMC driver
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___SD_H___ +#define ___SD_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + + +/************************** Function Prototypes ******************************/ + +#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR) +u32 InitSD(const char *); + +u32 SDAccess( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthWords); + +void ReleaseSD(void); +#endif +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + + +#endif /* ___SD_H___ */ + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/vdma.c b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/vdma.c new file mode 100644 index 0000000..329f185 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/vdma.c @@ -0,0 +1,167 @@ +/* + */ + +#include "xil_printf.h" +//#include "sleep.h" + + +#include "vdma.h" + +XAxiVdma OutVdma; +XAxiVdma InVdma; + +XAxiVdma_DmaSetup VDMAOutCfg; +XAxiVdma_DmaSetup VDMAInCfg; + +u32 vdma_version() { + return XAxiVdma_GetVersion(&OutVdma); +} + +int vdma_out_start() { + int Status; + + // MM2S Startup + Status = XAxiVdma_DmaStart(&OutVdma, XAXIVDMA_READ); + if (Status != XST_SUCCESS) + { + xil_printf("Start read transfer failed %d\n\r", Status); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +int vdma_in_start() { + int Status; + + // MM2S Startup + Status = XAxiVdma_DmaStart(&InVdma, XAXIVDMA_WRITE); + if (Status != XST_SUCCESS) + { + xil_printf("Start read transfer failed %d\n\r", Status); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +int vdma_stop() { + XAxiVdma_DmaStop(&OutVdma, XAXIVDMA_READ); + return XST_SUCCESS; +} + + +int vdma_out_init(short DeviceID, int base_address, int h_width, int v_width, int bpp) +{ + XAxiVdma_Config *Config; + int Status; + + + Config = XAxiVdma_LookupConfig(DeviceID); + if (NULL == Config) { + xil_printf("XAxiVdma_LookupConfig failure\r\n"); + return XST_FAILURE; + } + + Status = XAxiVdma_CfgInitialize(&OutVdma, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("XAxiVdma_CfgInitialize failure\r\n"); + return XST_FAILURE; + } + + VDMAOutCfg.EnableCircularBuf = 1; + VDMAOutCfg.EnableFrameCounter = 0; + VDMAOutCfg.FixedFrameStoreAddr = 0; + + VDMAOutCfg.EnableSync = 1; + VDMAOutCfg.PointNum = 1; + + VDMAOutCfg.FrameDelay = 0; + + VDMAOutCfg.VertSizeInput = v_width; + VDMAOutCfg.HoriSizeInput = h_width * bpp; + VDMAOutCfg.Stride = VDMAOutCfg.HoriSizeInput; + + Status = XAxiVdma_DmaConfig(&OutVdma, XAXIVDMA_READ, &VDMAOutCfg); + if (Status != XST_SUCCESS) { + xdbg_printf(XDBG_DEBUG_ERROR, + "Read channel config failed %d\r\n", Status); + + return XST_FAILURE; + } + + VDMAOutCfg.FrameStoreStartAddr[0] = base_address; + + Status = XAxiVdma_DmaSetBufferAddr(&OutVdma, XAXIVDMA_READ, VDMAOutCfg.FrameStoreStartAddr); + if (Status != XST_SUCCESS) { + xdbg_printf(XDBG_DEBUG_ERROR,"Read channel set buffer address failed %d\r\n", Status); + return XST_FAILURE; + } + + + Status = vdma_out_start(); + if (Status != XST_SUCCESS) { + xil_printf("error starting VDMA..!"); + return Status; + } + return XST_SUCCESS; + +} + +int vdma_in_init(short DeviceID, int base_address, int h_width, int v_width, int bpp) +{ + XAxiVdma_Config *Config; + int Status; + + Config = XAxiVdma_LookupConfig(DeviceID); + if (NULL == Config) { + xil_printf("XAxiVdma_LookupConfig failure\r\n"); + return XST_FAILURE; + } + + Status = XAxiVdma_CfgInitialize(&InVdma, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("XAxiVdma_CfgInitialize failure\r\n"); + return XST_FAILURE; + } + + VDMAInCfg.EnableCircularBuf = 1; + VDMAInCfg.EnableFrameCounter = 0; + VDMAInCfg.FixedFrameStoreAddr = 0; + + VDMAInCfg.EnableSync = 1; + VDMAInCfg.PointNum = 1; + + VDMAInCfg.FrameDelay = 0; + + VDMAInCfg.VertSizeInput = v_width; + VDMAInCfg.HoriSizeInput = h_width * bpp; + VDMAInCfg.Stride = VDMAInCfg.HoriSizeInput; + + Status = XAxiVdma_DmaConfig(&InVdma, XAXIVDMA_WRITE, &VDMAInCfg); + if (Status != XST_SUCCESS) { + xdbg_printf(XDBG_DEBUG_ERROR, + "Read channel config failed %d\r\n", Status); + + return XST_FAILURE; + } + + VDMAInCfg.FrameStoreStartAddr[0] = base_address; + + Status = XAxiVdma_DmaSetBufferAddr(&InVdma, XAXIVDMA_WRITE, VDMAInCfg.FrameStoreStartAddr); + if (Status != XST_SUCCESS) { + xdbg_printf(XDBG_DEBUG_ERROR,"Write channel set buffer address failed %d\r\n", Status); + return XST_FAILURE; + } + + + Status = vdma_in_start(); + if (Status != XST_SUCCESS) { + xil_printf("error starting VDMA..!"); + return Status; + } + + return XST_SUCCESS; + +} + diff --git a/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/vdma.h b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/vdma.h new file mode 100644 index 0000000..79c1662 --- /dev/null +++ b/zynqberrydemo1/sw_lib/sw_apps/zynq_fsbl/src/vdma.h @@ -0,0 +1,14 @@ + +#ifndef VDMA_H_ +#define VDMA_H_ + +#include "xaxivdma.h" + + +extern XAxiVdma Vdma; /**< Instance of the VDMA Device */ +int vdma_out_init(short DeviceID, int base_address, int h_width, int v_width, int bpp); +int vdma_in_init(short DeviceID, int base_address, int h_width, int v_width, int bpp); + +u32 vdma_version(); + +#endif /* VDMA_H_ */ diff --git a/zynqberrydemo3/_readme.txt b/zynqberrydemo3/_readme.txt new file mode 100644 index 0000000..4a7d866 --- /dev/null +++ b/zynqberrydemo3/_readme.txt @@ -0,0 +1,73 @@ +Project Description +========================================================================== +Important notes: + 1.Please use short path name on Windows OS. The OS allows only 256 characters in normal path. + 2.Please do not use space character on path name. +========================================================================== +1. Create Command Files and open documentation links: + On Windows OS: run "_create_win_setup.cmd" and follow setup instructions + On Linux OS: run "_create_linux_setup.sh" and follow setup instructions +============================== +2. Create Vivado Project on Windows OS use instructions from option 1 of: + ===== + https://wiki.trenz-electronic.de/display/PD/Vivado+Projects + ===== + 1.Modify start setting: + ===== + Edit "design_basic_settings.cmd" with text editor: + Set your vivado installation path for edit: + @set XILDIR=C:\Xilinx + @set VIVADO_VERSION=2017.1 + In this example the it search in + C:\Xilinx\Vivado\2017.1 for VIVADO + C:\Xilinx\SDK\2017.1 for SDK (optional for some functionality, HSI/SDK) + C:\Xilinx\Vivado_Lab\2017.1 for VIVADO Labtools (optional for some functionality) + Set the correct part number for your pcb variant (see board_files/TE0710_board_files.csv), edit: + @set PARTNUMBER=1 + ===== + 2.Run "vivado_create_project_guimode.cmd" +============================== +2. Create Vivado Project on Linux use instructions from option 1 of: + ===== + https://wiki.trenz-electronic.de/display/PD/Vivado+Projects + ===== + 1.Modify start setting: + ===== + Edit "design_basic_settings.sh" with text editor: + Set your vivado installation path for edit: + @set XILDIR=/opt/Xilinx + @set VIVADO_VERSION=2017.1 + In this example the it search in + /opt/Vivado/2017.1 for VIVADO + /opt/SDK/2017.1 for SDK (optional for some functionality, HSI/SDK) + /opt/Vivado_Lab/2017.1 for VIVADO Labtools (optional for some functionality) + Set the correct part number for your pcb variant (see board_files/TE0710_board_files.csv), edit: + @set PARTNUMBER=1 + ===== + 2.Run "vivado_create_project_guimode.sh" +============================== +There are also other options available: + ===== + https://wiki.trenz-electronic.de/display/PD/Vivado+Projects +============================== +Attention: + ===== + Run design_clear_design_folders.cmd/sh clear all generated files and folders (vivado, workspace(hsi & sdk), vlog,...)! +============================== +Basic documentations: + ===== + Project Delivery: + https://wiki.trenz-electronic.de/display/PD/Project+Delivery + == + VIVADO/SDK/SDSoC + https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264 + == + Trenz Electronic SoMs + https://wiki.trenz-electronic.de/display/PD/All+Trenz+Electronic+SoMs + == + Additional Information for the are available on the download page of the design + https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic //Reference_Design// +============================== +===== +NOTES +===== \ No newline at end of file diff --git a/zynqberrydemo3/block_design/zsys_bd.tcl b/zynqberrydemo3/block_design/zsys_bd.tcl new file mode 100644 index 0000000..6b47c52 --- /dev/null +++ b/zynqberrydemo3/block_design/zsys_bd.tcl @@ -0,0 +1,1126 @@ +TE::UTILS::te_msg TE_BD-0 INFO "This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0726_7s:part0:3.1, FPGA: xc7z007sclg225-1 at 2017-06-12T13:37:13." +TE::UTILS::te_msg TE_BD-1 INFO "This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag # #TE_MOD# on the Block-Design tcl-file." + +################################################################ +# This is a generated script based on design: zsys +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2017.1 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source zsys_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z007sclg225-1 + set_property BOARD_PART trenz.biz:te0726_7s:part0:3.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +set design_name zsys + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: video_out +proc create_hier_cell_video_out { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_video_out() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 CLKWIZ_AXI + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 VDMA_AXI + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 VIDEO_OUT_AXI + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 VTC_AXI + + # Create pins + create_bd_pin -dir I -type clk axi_aclk + create_bd_pin -dir I -from 0 -to 0 -type rst axi_int_aresetn + create_bd_pin -dir I -from 0 -to 0 -type rst axi_per_aresetn + create_bd_pin -dir O hdmi_clk_n + create_bd_pin -dir O hdmi_clk_p + create_bd_pin -dir O -from 2 -to 0 hdmi_data_n + create_bd_pin -dir O -from 2 -to 0 hdmi_data_p + create_bd_pin -dir I -type clk ref_clk + create_bd_pin -dir O -type intr tx_dma_int + + # Create instance: Video_IO_2_HDMI_TMDS_0, and set properties + set Video_IO_2_HDMI_TMDS_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:Video_IO_2_HDMI_TMDS:1.0 Video_IO_2_HDMI_TMDS_0 ] + set_property -dict [ list \ +CONFIG.C_CLK_SWAP {true} \ +CONFIG.C_D0_SWAP {true} \ +CONFIG.C_INT_CLOCKING {false} \ +CONFIG.C_VIDEO_MODE {0} \ + ] $Video_IO_2_HDMI_TMDS_0 + + # Create instance: axi_mem_intercon, and set properties + set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] + set_property -dict [ list \ +CONFIG.NUM_MI {1} \ + ] $axi_mem_intercon + + # Create instance: axi_vdma_0, and set properties + set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0 ] + set_property -dict [ list \ +CONFIG.c_include_s2mm {0} \ +CONFIG.c_m_axi_mm2s_data_width {32} \ +CONFIG.c_mm2s_genlock_mode {0} \ +CONFIG.c_mm2s_linebuffer_depth {1024} \ +CONFIG.c_mm2s_max_burst_length {16} \ +CONFIG.c_num_fstores {1} \ +CONFIG.c_s2mm_genlock_mode {0} \ + ] $axi_vdma_0 + + # Create instance: axis_fb_conv_0, and set properties + set axis_fb_conv_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_fb_conv:1.0 axis_fb_conv_0 ] + + # Create instance: clk_wiz_1, and set properties + set clk_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.4 clk_wiz_1 ] + set_property -dict [ list \ +CONFIG.CLKIN1_JITTER_PS {50.0} \ +CONFIG.CLKOUT1_JITTER {333.287} \ +CONFIG.CLKOUT1_PHASE_ERROR {322.999} \ +CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {74.250} \ +CONFIG.CLKOUT2_JITTER {256.477} \ +CONFIG.CLKOUT2_PHASE_ERROR {322.999} \ +CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {371.250} \ +CONFIG.CLKOUT2_USED {true} \ +CONFIG.CLKOUT3_JITTER {325.031} \ +CONFIG.CLKOUT3_PHASE_ERROR {569.784} \ +CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {100.000} \ +CONFIG.CLKOUT3_USED {false} \ +CONFIG.CLKOUT4_JITTER {357.108} \ +CONFIG.CLKOUT4_PHASE_ERROR {569.784} \ +CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {100.000} \ +CONFIG.CLKOUT4_USED {false} \ +CONFIG.JITTER_SEL {Min_O_Jitter} \ +CONFIG.MMCM_BANDWIDTH {HIGH} \ +CONFIG.MMCM_CLKFBOUT_MULT_F {37.125} \ +CONFIG.MMCM_CLKIN1_PERIOD {5.000} \ +CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ +CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.000} \ +CONFIG.MMCM_CLKOUT1_DIVIDE {2} \ +CONFIG.MMCM_CLKOUT2_DIVIDE {1} \ +CONFIG.MMCM_CLKOUT3_DIVIDE {1} \ +CONFIG.MMCM_DIVCLK_DIVIDE {10} \ +CONFIG.NUM_OUT_CLKS {2} \ +CONFIG.USE_DYN_RECONFIG {true} \ + ] $clk_wiz_1 + + # Create instance: v_axi4s_vid_out_0, and set properties + set v_axi4s_vid_out_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_axi4s_vid_out:4.0 v_axi4s_vid_out_0 ] + set_property -dict [ list \ +CONFIG.C_HAS_ASYNC_CLK {1} \ + ] $v_axi4s_vid_out_0 + + # Create instance: v_tc_0, and set properties + set v_tc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_tc:6.1 v_tc_0 ] + set_property -dict [ list \ +CONFIG.GEN_F0_VBLANK_HEND {1280} \ +CONFIG.GEN_F0_VBLANK_HSTART {1280} \ +CONFIG.GEN_F0_VFRAME_SIZE {750} \ +CONFIG.GEN_F0_VSYNC_HEND {1280} \ +CONFIG.GEN_F0_VSYNC_HSTART {1280} \ +CONFIG.GEN_F0_VSYNC_VEND {729} \ +CONFIG.GEN_F0_VSYNC_VSTART {724} \ +CONFIG.GEN_F1_VBLANK_HEND {1280} \ +CONFIG.GEN_F1_VBLANK_HSTART {1280} \ +CONFIG.GEN_F1_VFRAME_SIZE {750} \ +CONFIG.GEN_F1_VSYNC_HEND {1280} \ +CONFIG.GEN_F1_VSYNC_HSTART {1280} \ +CONFIG.GEN_F1_VSYNC_VEND {729} \ +CONFIG.GEN_F1_VSYNC_VSTART {724} \ +CONFIG.GEN_HACTIVE_SIZE {1280} \ +CONFIG.GEN_HFRAME_SIZE {1650} \ +CONFIG.GEN_HSYNC_END {1430} \ +CONFIG.GEN_HSYNC_START {1390} \ +CONFIG.GEN_VACTIVE_SIZE {720} \ +CONFIG.HAS_AXI4_LITE {true} \ +CONFIG.VIDEO_MODE {720p} \ +CONFIG.enable_detection {false} \ +CONFIG.max_clocks_per_line {4096} \ +CONFIG.max_lines_per_frame {2048} \ + ] $v_tc_0 + + # Create interface connections + connect_bd_intf_net -intf_net CLKWIZ_AXI_1 [get_bd_intf_pins CLKWIZ_AXI] [get_bd_intf_pins clk_wiz_1/s_axi_lite] + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins VIDEO_OUT_AXI] [get_bd_intf_pins axi_mem_intercon/M00_AXI] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins VDMA_AXI] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins VTC_AXI] [get_bd_intf_pins v_tc_0/ctrl] + connect_bd_intf_net -intf_net axi_vdma_0_M_AXIS_MM2S [get_bd_intf_pins axi_vdma_0/M_AXIS_MM2S] [get_bd_intf_pins axis_fb_conv_0/S_AXIS] + connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_MM2S [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins axi_vdma_0/M_AXI_MM2S] + connect_bd_intf_net -intf_net axis_fb_conv_0_video_out [get_bd_intf_pins axis_fb_conv_0/video_out] [get_bd_intf_pins v_axi4s_vid_out_0/video_in] + connect_bd_intf_net -intf_net v_axi4s_vid_out_0_vid_io_out [get_bd_intf_pins Video_IO_2_HDMI_TMDS_0/vid_io_in] [get_bd_intf_pins v_axi4s_vid_out_0/vid_io_out] + connect_bd_intf_net -intf_net v_tc_0_vtiming_out [get_bd_intf_pins v_axi4s_vid_out_0/vtiming_in] [get_bd_intf_pins v_tc_0/vtiming_out] + + # Create port connections + connect_bd_net -net ARESETN_2 [get_bd_pins axi_int_aresetn] [get_bd_pins axi_mem_intercon/ARESETN] + connect_bd_net -net Video_IO_2_HDMI_TMDS_0_hdmi_clk_n [get_bd_pins hdmi_clk_n] [get_bd_pins Video_IO_2_HDMI_TMDS_0/hdmi_clk_n] + connect_bd_net -net Video_IO_2_HDMI_TMDS_0_hdmi_clk_p [get_bd_pins hdmi_clk_p] [get_bd_pins Video_IO_2_HDMI_TMDS_0/hdmi_clk_p] + connect_bd_net -net Video_IO_2_HDMI_TMDS_0_hdmi_data_n [get_bd_pins hdmi_data_n] [get_bd_pins Video_IO_2_HDMI_TMDS_0/hdmi_data_n] + connect_bd_net -net Video_IO_2_HDMI_TMDS_0_hdmi_data_p [get_bd_pins hdmi_data_p] [get_bd_pins Video_IO_2_HDMI_TMDS_0/hdmi_data_p] + connect_bd_net -net aclk_1 [get_bd_pins axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_vdma_0/m_axi_mm2s_aclk] [get_bd_pins axi_vdma_0/m_axis_mm2s_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk] [get_bd_pins axis_fb_conv_0/s_axis_aclk] [get_bd_pins clk_wiz_1/s_axi_aclk] [get_bd_pins v_axi4s_vid_out_0/aclk] [get_bd_pins v_tc_0/s_axi_aclk] + connect_bd_net -net aresetn_1 [get_bd_pins axi_per_aresetn] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_vdma_0/axi_resetn] [get_bd_pins axis_fb_conv_0/s_axis_aresetn] [get_bd_pins clk_wiz_1/s_axi_aresetn] [get_bd_pins v_axi4s_vid_out_0/aresetn] [get_bd_pins v_tc_0/s_axi_aresetn] + connect_bd_net -net axi_vdma_0_mm2s_introut [get_bd_pins tx_dma_int] [get_bd_pins axi_vdma_0/mm2s_introut] + connect_bd_net -net clk_in1_1 [get_bd_pins ref_clk] [get_bd_pins clk_wiz_1/clk_in1] + connect_bd_net -net clk_wiz_1_clk_out2 [get_bd_pins Video_IO_2_HDMI_TMDS_0/video_clk5x_in] [get_bd_pins clk_wiz_1/clk_out2] + connect_bd_net -net clk_wiz_1_locked [get_bd_pins Video_IO_2_HDMI_TMDS_0/lock_in] [get_bd_pins clk_wiz_1/locked] + connect_bd_net -net v_axi4s_vid_out_0_vtg_ce [get_bd_pins v_axi4s_vid_out_0/vtg_ce] [get_bd_pins v_tc_0/gen_clken] + connect_bd_net -net video_clk_in_1 [get_bd_pins Video_IO_2_HDMI_TMDS_0/video_clk_in] [get_bd_pins clk_wiz_1/clk_out1] [get_bd_pins v_axi4s_vid_out_0/vid_io_out_clk] [get_bd_pins v_tc_0/clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: video_in +proc create_hier_cell_video_in { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_video_in() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 VDMA_AXI + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:aximm_rtl:1.0 VIDEO_IN_AXI + + # Create pins + create_bd_pin -dir I -type clk axi_aclk + create_bd_pin -dir I -from 0 -to 0 -type rst axi_aresetn + create_bd_pin -dir I -from 0 -to 0 axi_int_aresetn + create_bd_pin -dir I colors_mode + create_bd_pin -dir I csi_clk_n + create_bd_pin -dir I csi_clk_p + create_bd_pin -dir I -from 0 -to 0 csi_data_lp_n + create_bd_pin -dir I -from 0 -to 0 csi_data_lp_p + create_bd_pin -dir I -from 1 -to 0 csi_data_n + create_bd_pin -dir I -from 1 -to 0 csi_data_p + create_bd_pin -dir I -from 0 -to 0 enable + create_bd_pin -dir I -type rst ext_reset_in + create_bd_pin -dir I processing_clk + create_bd_pin -dir I ref_clk + create_bd_pin -dir O rx_dma_int + + # Create instance: axi_interconnect_0, and set properties + set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] + set_property -dict [ list \ +CONFIG.NUM_MI {1} \ + ] $axi_interconnect_0 + + # Create instance: axi_vdma_0, and set properties + set axi_vdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.3 axi_vdma_0 ] + set_property -dict [ list \ +CONFIG.c_include_mm2s {0} \ +CONFIG.c_include_s2mm_dre {1} \ +CONFIG.c_m_axi_s2mm_data_width {64} \ +CONFIG.c_mm2s_genlock_mode {0} \ +CONFIG.c_num_fstores {1} \ +CONFIG.c_s2mm_genlock_mode {0} \ +CONFIG.c_s2mm_linebuffer_depth {4096} \ +CONFIG.c_s2mm_max_burst_length {32} \ + ] $axi_vdma_0 + + # Create instance: axis_data_fifo_0, and set properties + set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ] + set_property -dict [ list \ +CONFIG.FIFO_DEPTH {16384} \ +CONFIG.HAS_TLAST {1} \ +CONFIG.IS_ACLK_ASYNC {1} \ +CONFIG.TDATA_NUM_BYTES {2} \ +CONFIG.TUSER_WIDTH {1} \ + ] $axis_data_fifo_0 + + # Create instance: axis_data_fifo_3, and set properties + set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_3 ] + + # Create instance: axis_data_fifo_4, and set properties + set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_4 ] + set_property -dict [ list \ +CONFIG.FIFO_DEPTH {4096} \ +CONFIG.IS_ACLK_ASYNC {1} \ + ] $axis_data_fifo_4 + + # Create instance: axis_raw_demosaic_0, and set properties + set axis_raw_demosaic_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_raw_demosaic:1.0 axis_raw_demosaic_0 ] + set_property -dict [ list \ +CONFIG.C_COLOR_POS {2} \ +CONFIG.C_IN_TYPE {1} \ +CONFIG.C_MODE {1} \ + ] $axis_raw_demosaic_0 + + # Create instance: axis_raw_unpack_0, and set properties + set axis_raw_unpack_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_raw_unpack:1.0 axis_raw_unpack_0 ] + set_property -dict [ list \ +CONFIG.C_IMP_TYPE {1} \ +CONFIG.C_OUT_TYPE {1} \ + ] $axis_raw_unpack_0 + + # Create instance: csi2_d_phy_rx_0, and set properties + set csi2_d_phy_rx_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:csi2_d_phy_rx:1.0 csi2_d_phy_rx_0 ] + set_property -dict [ list \ +CONFIG.C_ADD_IDELAYCTRL {true} \ +CONFIG.C_CALIB_WAIT {8191} \ +CONFIG.C_NUM_LP_LANES {1} \ +CONFIG.C_RATE_LIMIT {50} \ +CONFIG.C_USE_DELAY {true} \ + ] $csi2_d_phy_rx_0 + + # Create instance: csi_to_axis_0, and set properties + set csi_to_axis_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:csi_to_axis:1.0 csi_to_axis_0 ] + set_property -dict [ list \ +CONFIG.C_TIMEOUT {255} \ + ] $csi_to_axis_0 + + # Create instance: proc_sys_reset_0, and set properties + set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] + + # Create instance: proc_sys_reset_1, and set properties + set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] + + # Create interface connections + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins csi_to_axis_0/M_AXIS] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins VDMA_AXI] [get_bd_intf_pins axi_vdma_0/S_AXI_LITE] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins VIDEO_IN_AXI] [get_bd_intf_pins axi_interconnect_0/M00_AXI] + connect_bd_intf_net -intf_net axi_vdma_0_M_AXI_S2MM [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins axi_vdma_0/M_AXI_S2MM] + connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins axis_raw_unpack_0/S_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axis_data_fifo_3/M_AXIS] [get_bd_intf_pins axis_raw_demosaic_0/S_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins axi_vdma_0/S_AXIS_S2MM] [get_bd_intf_pins axis_data_fifo_4/M_AXIS] + connect_bd_intf_net -intf_net axis_raw_demosaic_0_M_AXIS [get_bd_intf_pins axis_data_fifo_4/S_AXIS] [get_bd_intf_pins axis_raw_demosaic_0/M_AXIS] + connect_bd_intf_net -intf_net axis_raw_unpack_0_M_AXIS [get_bd_intf_pins axis_data_fifo_3/S_AXIS] [get_bd_intf_pins axis_raw_unpack_0/M_AXIS] + connect_bd_intf_net -intf_net csi2_d_phy_rx_0_RX_MIPI_PPI [get_bd_intf_pins csi2_d_phy_rx_0/RX_MIPI_PPI] [get_bd_intf_pins csi_to_axis_0/RX_MIPI_PPI] + connect_bd_intf_net -intf_net csi_to_axis_0_data_err [get_bd_intf_pins csi2_d_phy_rx_0/data_err] [get_bd_intf_pins csi_to_axis_0/data_err] + + # Create port connections + connect_bd_net -net CSI_AXIS_RSTN [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins csi_to_axis_0/m_axis_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] + connect_bd_net -net ENABLE_STREAM [get_bd_pins enable] [get_bd_pins csi_to_axis_0/enable_in] + connect_bd_net -net axi_int_aresetn_1 [get_bd_pins axi_int_aresetn] [get_bd_pins axi_interconnect_0/ARESETN] + connect_bd_net -net axi_vdma_0_s2mm_introut [get_bd_pins rx_dma_int] [get_bd_pins axi_vdma_0/s2mm_introut] + connect_bd_net -net colors_mode_1 [get_bd_pins colors_mode] [get_bd_pins axis_raw_demosaic_0/colors_mode] + connect_bd_net -net csi_clk_n_1 [get_bd_pins csi_clk_n] [get_bd_pins csi2_d_phy_rx_0/clk_rxn] + connect_bd_net -net csi_clk_p_1 [get_bd_pins csi_clk_p] [get_bd_pins csi2_d_phy_rx_0/clk_rxp] + connect_bd_net -net csi_data_lp_n_1 [get_bd_pins csi_data_lp_n] [get_bd_pins csi2_d_phy_rx_0/data_lp_n] + connect_bd_net -net csi_data_lp_p_1 [get_bd_pins csi_data_lp_p] [get_bd_pins csi2_d_phy_rx_0/data_lp_p] + connect_bd_net -net csi_data_n_1 [get_bd_pins csi_data_n] [get_bd_pins csi2_d_phy_rx_0/data_rxn] + connect_bd_net -net csi_data_p_1 [get_bd_pins csi_data_p] [get_bd_pins csi2_d_phy_rx_0/data_rxp] + connect_bd_net -net ext_reset_in_1 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] + connect_bd_net -net m_axi_aclk [get_bd_pins axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_vdma_0/m_axi_s2mm_aclk] [get_bd_pins axi_vdma_0/s_axi_lite_aclk] [get_bd_pins axi_vdma_0/s_axis_s2mm_aclk] [get_bd_pins axis_data_fifo_4/m_axis_aclk] + connect_bd_net -net m_axis_aresetn_1 [get_bd_pins axi_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_vdma_0/axi_resetn] [get_bd_pins axis_data_fifo_4/m_axis_aresetn] + connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axis_data_fifo_0/m_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins axis_raw_demosaic_0/axis_aresetn] [get_bd_pins axis_raw_unpack_0/axis_aresetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn] + connect_bd_net -net processing_clk_1 [get_bd_pins processing_clk] [get_bd_pins axis_data_fifo_0/m_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins axis_raw_demosaic_0/axis_aclk] [get_bd_pins axis_raw_unpack_0/axis_aclk] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] + connect_bd_net -net ref_clk_in_1 [get_bd_pins ref_clk] [get_bd_pins csi2_d_phy_rx_0/in_delay_clk] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins csi2_d_phy_rx_0/rxbyteclkhs] [get_bd_pins csi_to_axis_0/m_axis_aclk] [get_bd_pins csi_to_axis_0/rxbyteclkhs] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: resets +proc create_hier_cell_resets { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_resets() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + + # Create pins + create_bd_pin -dir I -type clk axi_clk + create_bd_pin -dir O -from 0 -to 0 -type rst axi_int_aresetn + create_bd_pin -dir O -from 0 -to 0 -type rst axi_per_aresetn + create_bd_pin -dir I -type rst ext_reset_in + + # Create instance: rst_processing_system7_0_50M, and set properties + set rst_processing_system7_0_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_processing_system7_0_50M ] + + # Create port connections + connect_bd_net -net ext_reset_in_1 [get_bd_pins ext_reset_in] [get_bd_pins rst_processing_system7_0_50M/ext_reset_in] + connect_bd_net -net rst_processing_system7_0_50M_interconnect_aresetn [get_bd_pins axi_int_aresetn] [get_bd_pins rst_processing_system7_0_50M/interconnect_aresetn] + connect_bd_net -net rst_processing_system7_0_50M_peripheral_aresetn [get_bd_pins axi_per_aresetn] [get_bd_pins rst_processing_system7_0_50M/peripheral_aresetn] + connect_bd_net -net slowest_sync_clk_1 [get_bd_pins axi_clk] [get_bd_pins rst_processing_system7_0_50M/slowest_sync_clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + +# Hierarchical cell: audio +proc create_hier_cell_audio { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_audio() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMA_RX_ACK + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMA_RX_REQ + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 DMA_TX_ACK + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 DMA_TX_REQ + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn + + # Create pins + create_bd_pin -dir I audio_clk + create_bd_pin -dir I -type clk axi_aclk + create_bd_pin -dir I -from 0 -to 0 -type rst axi_resetn + create_bd_pin -dir O pwm_l_out + create_bd_pin -dir O pwm_r_out + + # Create instance: axi_i2s_adi_0, and set properties + set axi_i2s_adi_0 [ create_bd_cell -type ip -vlnv digilentinc.com:user:axi_i2s_adi:1.2 axi_i2s_adi_0 ] + set_property -dict [ list \ +CONFIG.C_DMA_TYPE {1} \ + ] $axi_i2s_adi_0 + + # Create instance: axis_to_i2s_0, and set properties + set axis_to_i2s_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_to_i2s:1.0 axis_to_i2s_0 ] + + # Create instance: i2s_to_pwm_0, and set properties + set i2s_to_pwm_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:i2s_to_pwm:1.0 i2s_to_pwm_0 ] + + # Create instance: xadc_wiz_0, and set properties + set xadc_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.3 xadc_wiz_0 ] + set_property -dict [ list \ +CONFIG.ADC_CONVERSION_RATE {1000} \ +CONFIG.DCLK_FREQUENCY {150} \ +CONFIG.ENABLE_AXI4STREAM {true} \ +CONFIG.ENABLE_RESET {true} \ +CONFIG.ENABLE_VCCDDRO_ALARM {false} \ +CONFIG.ENABLE_VCCPAUX_ALARM {false} \ +CONFIG.ENABLE_VCCPINT_ALARM {false} \ +CONFIG.INTERFACE_SELECTION {None} \ +CONFIG.OT_ALARM {false} \ +CONFIG.SINGLE_CHANNEL_SELECTION {VP_VN} \ +CONFIG.USER_TEMP_ALARM {false} \ +CONFIG.VCCAUX_ALARM {false} \ +CONFIG.VCCINT_ALARM {false} \ + ] $xadc_wiz_0 + + # Create interface connections + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins Vp_Vn] [get_bd_intf_pins xadc_wiz_0/Vp_Vn] + connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins DMA_TX_ACK] [get_bd_intf_pins axi_i2s_adi_0/DMA_TX_ACK] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins DMA_TX_REQ] [get_bd_intf_pins axi_i2s_adi_0/DMA_TX_REQ] + connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins DMA_RX_REQ] [get_bd_intf_pins axi_i2s_adi_0/DMA_RX_REQ] + connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins DMA_RX_ACK] [get_bd_intf_pins axi_i2s_adi_0/DMA_RX_ACK] + connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins S00_AXI] [get_bd_intf_pins axi_i2s_adi_0/S00_AXI] + connect_bd_intf_net -intf_net xadc_wiz_0_M_AXIS [get_bd_intf_pins axis_to_i2s_0/s_axis] [get_bd_intf_pins xadc_wiz_0/M_AXIS] + + # Create port connections + connect_bd_net -net BCLK [get_bd_pins axi_i2s_adi_0/BCLK_O] [get_bd_pins axis_to_i2s_0/i2s_bclk] [get_bd_pins i2s_to_pwm_0/i2s_bclk] + connect_bd_net -net DATA_CLK_I_1 [get_bd_pins audio_clk] [get_bd_pins axi_i2s_adi_0/DATA_CLK_I] + connect_bd_net -net LRCLK [get_bd_pins axi_i2s_adi_0/LRCLK_O] [get_bd_pins axis_to_i2s_0/i2s_lrclk] [get_bd_pins i2s_to_pwm_0/i2s_lrclk] + connect_bd_net -net i2s_to_pwm_0_pwm_l_out [get_bd_pins pwm_l_out] [get_bd_pins i2s_to_pwm_0/pwm_l_out] + connect_bd_net -net i2s_to_pwm_0_pwm_r_out [get_bd_pins pwm_r_out] [get_bd_pins i2s_to_pwm_0/pwm_r_out] + connect_bd_net -net m_axis_resetn_1 [get_bd_pins axi_resetn] [get_bd_pins axi_i2s_adi_0/DMA_REQ_RX_RSTN] [get_bd_pins axi_i2s_adi_0/DMA_REQ_TX_RSTN] [get_bd_pins axi_i2s_adi_0/s00_axi_aresetn] [get_bd_pins axis_to_i2s_0/s_axis_aresetn] [get_bd_pins xadc_wiz_0/m_axis_resetn] + connect_bd_net -net play_sdata [get_bd_pins axi_i2s_adi_0/SDATA_O] [get_bd_pins i2s_to_pwm_0/i2s_sdata] + connect_bd_net -net rec_sdata [get_bd_pins axi_i2s_adi_0/SDATA_I] [get_bd_pins axis_to_i2s_0/i2s_sdata] + connect_bd_net -net s_axis_aclk_1 [get_bd_pins axi_aclk] [get_bd_pins axi_i2s_adi_0/DMA_REQ_RX_ACLK] [get_bd_pins axi_i2s_adi_0/DMA_REQ_TX_ACLK] [get_bd_pins axi_i2s_adi_0/s00_axi_aclk] [get_bd_pins axis_to_i2s_0/s_axis_aclk] [get_bd_pins i2s_to_pwm_0/clk_in] [get_bd_pins xadc_wiz_0/m_axis_aclk] [get_bd_pins xadc_wiz_0/s_axis_aclk] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports +# #TE_MOD# set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] +# #TE_MOD# set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + set GPIO_1 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 GPIO_1 ] + set Vp_Vn [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn ] + + # Create ports + set PWM_L [ create_bd_port -dir O PWM_L ] + set PWM_R [ create_bd_port -dir O PWM_R ] + set csi_c_clk_n [ create_bd_port -dir I csi_c_clk_n ] + set csi_c_clk_p [ create_bd_port -dir I csi_c_clk_p ] + set csi_d_lp_n [ create_bd_port -dir I -from 0 -to 0 csi_d_lp_n ] + set csi_d_lp_p [ create_bd_port -dir I -from 0 -to 0 csi_d_lp_p ] + set csi_d_n [ create_bd_port -dir I -from 1 -to 0 csi_d_n ] + set csi_d_p [ create_bd_port -dir I -from 1 -to 0 csi_d_p ] + set hdmi_clk_n [ create_bd_port -dir O hdmi_clk_n ] + set hdmi_clk_p [ create_bd_port -dir O hdmi_clk_p ] + set hdmi_data_n [ create_bd_port -dir O -from 2 -to 0 hdmi_data_n ] + set hdmi_data_p [ create_bd_port -dir O -from 2 -to 0 hdmi_data_p ] + + # Create instance: audio + create_hier_cell_audio [current_bd_instance .] audio + + # Create instance: axi_reg32_0, and set properties + set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0 ] + set_property -dict [ list \ +CONFIG.C_NUM_RO_REG {1} \ +CONFIG.C_NUM_WR_REG {1} \ + ] $axi_reg32_0 + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] +# #TE_MOD#_Add next line# + apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1"} [get_bd_cells processing_system7_0] +# #TE_MOD#_Add next line# + set tcl_ext [];if { [catch {set tcl_ext [glob -join -dir ${TE::BOARDDEF_PATH}/carrier_extension/ *_preset.tcl]}] } {};foreach carrier_ext $tcl_ext { source $carrier_ext}; + set_property -dict [ list \ +CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ +CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {160.000000} \ +CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {12.307692} \ +CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ +CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ +CONFIG.PCW_CLK0_FREQ {160000000} \ +CONFIG.PCW_CLK1_FREQ {100000000} \ +CONFIG.PCW_CLK2_FREQ {200000000} \ +CONFIG.PCW_CLK3_FREQ {12307692} \ +CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ +CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ +CONFIG.PCW_DM_WIDTH {2} \ +CONFIG.PCW_DQS_WIDTH {2} \ +CONFIG.PCW_DQ_WIDTH {16} \ +CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {External} \ +CONFIG.PCW_EN_CLK1_PORT {1} \ +CONFIG.PCW_EN_CLK2_PORT {1} \ +CONFIG.PCW_EN_CLK3_PORT {1} \ +CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_GPIO {1} \ +CONFIG.PCW_EN_EMIO_I2C0 {1} \ +CONFIG.PCW_EN_EMIO_PJTAG {0} \ +CONFIG.PCW_EN_EMIO_SDIO0 {0} \ +CONFIG.PCW_EN_EMIO_SPI0 {0} \ +CONFIG.PCW_EN_EMIO_SPI1 {0} \ +CONFIG.PCW_EN_EMIO_TTC0 {1} \ +CONFIG.PCW_EN_EMIO_TTC1 {0} \ +CONFIG.PCW_EN_EMIO_UART0 {0} \ +CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ +CONFIG.PCW_EN_GPIO {1} \ +CONFIG.PCW_EN_I2C0 {1} \ +CONFIG.PCW_EN_I2C1 {1} \ +CONFIG.PCW_EN_QSPI {1} \ +CONFIG.PCW_EN_SDIO0 {0} \ +CONFIG.PCW_EN_SDIO1 {1} \ +CONFIG.PCW_EN_SPI0 {0} \ +CONFIG.PCW_EN_SPI1 {0} \ +CONFIG.PCW_EN_TTC0 {1} \ +CONFIG.PCW_EN_TTC1 {0} \ +CONFIG.PCW_EN_UART0 {0} \ +CONFIG.PCW_EN_UART1 {1} \ +CONFIG.PCW_EN_USB0 {1} \ +CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ +CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ +CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {4} \ +CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {4} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {26} \ +CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {5} \ +CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ +CONFIG.PCW_FCLK_CLK2_BUF {TRUE} \ +CONFIG.PCW_FCLK_CLK3_BUF {TRUE} \ +CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {160} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {100} \ +CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200} \ +CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {12.288} \ +CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ +CONFIG.PCW_FPGA_FCLK2_ENABLE {1} \ +CONFIG.PCW_FPGA_FCLK3_ENABLE {1} \ +CONFIG.PCW_FTM_CTI_IN0 {} \ +CONFIG.PCW_FTM_CTI_IN2 {} \ +CONFIG.PCW_FTM_CTI_OUT0 {} \ +CONFIG.PCW_FTM_CTI_OUT2 {} \ +CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_EMIO_GPIO_IO {24} \ +CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {24} \ +CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ +CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ +CONFIG.PCW_I2C0_GRP_INT_ENABLE {1} \ +CONFIG.PCW_I2C0_GRP_INT_IO {EMIO} \ +CONFIG.PCW_I2C0_I2C0_IO {EMIO} \ +CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_I2C1_GRP_INT_ENABLE {1} \ +CONFIG.PCW_I2C1_GRP_INT_IO {EMIO} \ +CONFIG.PCW_I2C1_I2C1_IO {MIO 48 .. 49} \ +CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {111.111115} \ +CONFIG.PCW_I2C_RESET_ENABLE {0} \ +CONFIG.PCW_I2C_RESET_SELECT {} \ +CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ +CONFIG.PCW_SD0_GRP_WP_IO {} \ +CONFIG.PCW_SD1_GRP_CD_ENABLE {1} \ +CONFIG.PCW_SD1_GRP_CD_IO {MIO 0} \ +CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \ +CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ +CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {16} \ +CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ +CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS0_IO {} \ +CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ +CONFIG.PCW_SPI0_GRP_SS2_IO {} \ +CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ +CONFIG.PCW_SPI1_GRP_SS0_IO {} \ +CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ +CONFIG.PCW_SPI1_GRP_SS2_IO {} \ +CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ +CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ +CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {32} \ +CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_TTC0_TTC0_IO {EMIO} \ +CONFIG.PCW_TTC1_TTC1_IO {} \ +CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ +CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_UART1_UART1_IO {MIO 8 .. 9} \ +CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {16} \ +CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ +CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NONE} \ +CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_ENABLE {1} \ +CONFIG.PCW_USB0_RESET_IO {MIO 7} \ +CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ +CONFIG.PCW_USB_RESET_ENABLE {1} \ +CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ +CONFIG.PCW_USE_DMA0 {1} \ +CONFIG.PCW_USE_DMA1 {1} \ +CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \ +CONFIG.PCW_USE_M_AXI_GP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP0 {1} \ +CONFIG.PCW_USE_S_AXI_HP1 {1} \ + ] $processing_system7_0 + +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {780} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {550} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {53.995} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {77.166} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {700} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {520} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {57.044} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {81.244} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {86.1835} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {86.1835} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {86.1835} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {86.1835} \ +# #TE_MOD# CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.614} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.434} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.029} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.005} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.433} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.318} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.070} \ +# #TE_MOD# CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.082} \ +# #TE_MOD# #Empty Line + # Create instance: processing_system7_0_axi_periph, and set properties + set processing_system7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 processing_system7_0_axi_periph ] + set_property -dict [ list \ +CONFIG.NUM_MI {6} \ + ] $processing_system7_0_axi_periph + + # Create instance: resets + create_hier_cell_resets [current_bd_instance .] resets + + # Create instance: video_in + create_hier_cell_video_in [current_bd_instance .] video_in + + # Create instance: video_out + create_hier_cell_video_out [current_bd_instance .] video_out + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + set_property -dict [ list \ +CONFIG.NUM_PORTS {2} \ + ] $xlconcat_0 + + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + set_property -dict [ list \ +CONFIG.DIN_FROM {0} \ +CONFIG.DIN_TO {0} \ +CONFIG.DIN_WIDTH {32} \ + ] $xlslice_0 + + # Create instance: xlslice_1, and set properties + set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] + set_property -dict [ list \ +CONFIG.DIN_FROM {1} \ +CONFIG.DIN_TO {1} \ +CONFIG.DIN_WIDTH {32} \ +CONFIG.DOUT_WIDTH {1} \ + ] $xlslice_1 + + # Create interface connections + connect_bd_intf_net -intf_net Vp_Vn_1 [get_bd_intf_ports Vp_Vn] [get_bd_intf_pins audio/Vp_Vn] + connect_bd_intf_net -intf_net audio_DMA_RX_REQ [get_bd_intf_pins audio/DMA_RX_REQ] [get_bd_intf_pins processing_system7_0/DMA1_REQ] + connect_bd_intf_net -intf_net audio_DMA_TX_REQ [get_bd_intf_pins audio/DMA_TX_REQ] [get_bd_intf_pins processing_system7_0/DMA0_REQ] +# #TE_MOD# connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_DMA0_ACK [get_bd_intf_pins audio/DMA_TX_ACK] [get_bd_intf_pins processing_system7_0/DMA0_ACK] + connect_bd_intf_net -intf_net processing_system7_0_DMA1_ACK [get_bd_intf_pins audio/DMA_RX_ACK] [get_bd_intf_pins processing_system7_0/DMA1_ACK] +# #TE_MOD# connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] + connect_bd_intf_net -intf_net processing_system7_0_GPIO_0 [get_bd_intf_ports GPIO_1] [get_bd_intf_pins processing_system7_0/GPIO_0] + connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins processing_system7_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M00_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M00_AXI] [get_bd_intf_pins video_out/VDMA_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M01_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M01_AXI] [get_bd_intf_pins video_in/VDMA_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M02_AXI [get_bd_intf_pins audio/S00_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M03_AXI [get_bd_intf_pins axi_reg32_0/S_AXI] [get_bd_intf_pins processing_system7_0_axi_periph/M03_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M04_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M04_AXI] [get_bd_intf_pins video_out/VTC_AXI] + connect_bd_intf_net -intf_net processing_system7_0_axi_periph_M05_AXI [get_bd_intf_pins processing_system7_0_axi_periph/M05_AXI] [get_bd_intf_pins video_out/CLKWIZ_AXI] + connect_bd_intf_net -intf_net video_in_M00_AXI [get_bd_intf_pins processing_system7_0/S_AXI_HP1] [get_bd_intf_pins video_in/VIDEO_IN_AXI] + connect_bd_intf_net -intf_net video_out_M00_AXI [get_bd_intf_pins processing_system7_0/S_AXI_HP0] [get_bd_intf_pins video_out/VIDEO_OUT_AXI] + + # Create port connections + connect_bd_net -net audio_pwm_l_out [get_bd_ports PWM_L] [get_bd_pins audio/pwm_l_out] + connect_bd_net -net audio_pwm_r_out [get_bd_ports PWM_R] [get_bd_pins audio/pwm_r_out] + connect_bd_net -net axi_reg32_0_WR0 [get_bd_pins axi_reg32_0/WR0] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_1/Din] + connect_bd_net -net csi_c_clk_n_1 [get_bd_ports csi_c_clk_n] [get_bd_pins video_in/csi_clk_n] + connect_bd_net -net csi_c_clk_p_1 [get_bd_ports csi_c_clk_p] [get_bd_pins video_in/csi_clk_p] + connect_bd_net -net csi_d_lp_n_1 [get_bd_ports csi_d_lp_n] [get_bd_pins video_in/csi_data_lp_n] + connect_bd_net -net csi_d_lp_p_1 [get_bd_ports csi_d_lp_p] [get_bd_pins video_in/csi_data_lp_p] + connect_bd_net -net csi_d_n_1 [get_bd_ports csi_d_n] [get_bd_pins video_in/csi_data_n] + connect_bd_net -net csi_d_p_1 [get_bd_ports csi_d_p] [get_bd_pins video_in/csi_data_p] + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins audio/axi_aclk] [get_bd_pins axi_reg32_0/s_axi_aclk] [get_bd_pins processing_system7_0/DMA0_ACLK] [get_bd_pins processing_system7_0/DMA1_ACLK] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP1_ACLK] [get_bd_pins processing_system7_0_axi_periph/ACLK] [get_bd_pins processing_system7_0_axi_periph/M00_ACLK] [get_bd_pins processing_system7_0_axi_periph/M01_ACLK] [get_bd_pins processing_system7_0_axi_periph/M02_ACLK] [get_bd_pins processing_system7_0_axi_periph/M03_ACLK] [get_bd_pins processing_system7_0_axi_periph/M04_ACLK] [get_bd_pins processing_system7_0_axi_periph/M05_ACLK] [get_bd_pins processing_system7_0_axi_periph/S00_ACLK] [get_bd_pins resets/axi_clk] [get_bd_pins video_in/axi_aclk] [get_bd_pins video_in/processing_clk] [get_bd_pins video_out/axi_aclk] + connect_bd_net -net processing_system7_0_FCLK_CLK2 [get_bd_pins processing_system7_0/FCLK_CLK2] [get_bd_pins video_in/ref_clk] [get_bd_pins video_out/ref_clk] + connect_bd_net -net processing_system7_0_FCLK_CLK3 [get_bd_pins audio/audio_clk] [get_bd_pins processing_system7_0/FCLK_CLK3] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins resets/ext_reset_in] [get_bd_pins video_in/ext_reset_in] + connect_bd_net -net rst_processing_system7_0_50M_interconnect_aresetn [get_bd_pins processing_system7_0_axi_periph/ARESETN] [get_bd_pins resets/axi_int_aresetn] [get_bd_pins video_in/axi_int_aresetn] [get_bd_pins video_out/axi_int_aresetn] + connect_bd_net -net rst_processing_system7_0_50M_peripheral_aresetn [get_bd_pins audio/axi_resetn] [get_bd_pins axi_reg32_0/s_axi_aresetn] [get_bd_pins processing_system7_0_axi_periph/M00_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M01_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M02_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M03_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M04_ARESETN] [get_bd_pins processing_system7_0_axi_periph/M05_ARESETN] [get_bd_pins processing_system7_0_axi_periph/S00_ARESETN] [get_bd_pins resets/axi_per_aresetn] [get_bd_pins video_in/axi_aresetn] [get_bd_pins video_out/axi_per_aresetn] + connect_bd_net -net video_in_rx_dma_int [get_bd_pins video_in/rx_dma_int] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net video_out_hdmi_clk_n [get_bd_ports hdmi_clk_n] [get_bd_pins video_out/hdmi_clk_n] + connect_bd_net -net video_out_hdmi_clk_p [get_bd_ports hdmi_clk_p] [get_bd_pins video_out/hdmi_clk_p] + connect_bd_net -net video_out_hdmi_data_n [get_bd_ports hdmi_data_n] [get_bd_pins video_out/hdmi_data_n] + connect_bd_net -net video_out_hdmi_data_p [get_bd_ports hdmi_data_p] [get_bd_pins video_out/hdmi_data_p] + connect_bd_net -net video_out_mm2s_introut [get_bd_pins video_out/tx_dma_int] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] + connect_bd_net -net xlslice_0_Dout [get_bd_pins video_in/enable] [get_bd_pins xlslice_0/Dout] + connect_bd_net -net xlslice_1_Dout [get_bd_pins video_in/colors_mode] [get_bd_pins xlslice_1/Dout] + + # Create address segments + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs audio/axi_i2s_adi_0/S00_AXI/S00_AXI_reg] SEG_axi_i2s_adi_0_S00_AXI_reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_reg32_0/S_AXI/S_AXI_reg] SEG_axi_reg32_0_S_AXI_reg + create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video_out/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43010000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video_in/axi_vdma_0/S_AXI_LITE/Reg] SEG_axi_vdma_0_Reg1 + create_bd_addr_seg -range 0x00010000 -offset 0x43C30000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video_out/clk_wiz_1/s_axi_lite/Reg] SEG_clk_wiz_1_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C20000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs video_out/v_tc_0/ctrl/Reg] SEG_v_tc_0_Reg + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces video_in/axi_vdma_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_processing_system7_0_HP1_DDR_LOWOCM + create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces video_out/axi_vdma_0/Data_MM2S] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + + diff --git a/zynqberrydemo3/board_files/TE0726/1.0/board.xml b/zynqberrydemo3/board_files/TE0726/1.0/board.xml new file mode 100644 index 0000000..01bb3f3 --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/1.0/board.xml @@ -0,0 +1,69 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_01 Board File Image + + + + + + + 0.1 + + + + + 1.0 + + + ZYNQ-7 TE0726-01 ZynqBerry Board (form factor Raspberry Pi) with 128MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV01. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726/1.0/part0_pins.xml b/zynqberrydemo3/board_files/TE0726/1.0/part0_pins.xml new file mode 100644 index 0000000..f7ce2ba --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/1.0/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726/1.0/preset.xml b/zynqberrydemo3/board_files/TE0726/1.0/preset.xml new file mode 100644 index 0000000..aa55c3d --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/1.0/preset.xml @@ -0,0 +1,116 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726/2.1/board.xml b/zynqberrydemo3/board_files/TE0726/2.1/board.xml new file mode 100644 index 0000000..5fe89cf --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/2.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_R Board File Image + + + + + + + 0.3 + 0.2 + + + + + 2.1 + + + ZYNQ-7 TE0726-R ZynqBerry Board (form factor Raspberry Pi) with 128MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726/2.1/part0_pins.xml b/zynqberrydemo3/board_files/TE0726/2.1/part0_pins.xml new file mode 100644 index 0000000..1d0deec --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/2.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726/2.1/preset.xml b/zynqberrydemo3/board_files/TE0726/2.1/preset.xml new file mode 100644 index 0000000..e6f98eb --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/2.1/preset.xml @@ -0,0 +1,256 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726/3.1/board.xml b/zynqberrydemo3/board_files/TE0726/3.1/board.xml new file mode 100644 index 0000000..7facc84 --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/3.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_M Board File Image + + + + + + + 0.3 + 0.2 + + + + + 3.1 + + + ZYNQ-7 TE0726-M ZynqBerry Board (form factor Raspberry Pi) with 512MB Memory and 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726/3.1/part0_pins.xml b/zynqberrydemo3/board_files/TE0726/3.1/part0_pins.xml new file mode 100644 index 0000000..2c43aef --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/3.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726/3.1/preset.xml b/zynqberrydemo3/board_files/TE0726/3.1/preset.xml new file mode 100644 index 0000000..c9afaf8 --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726/3.1/preset.xml @@ -0,0 +1,283 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726_7S/3.1/board.xml b/zynqberrydemo3/board_files/TE0726_7S/3.1/board.xml new file mode 100644 index 0000000..14d4db1 --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726_7S/3.1/board.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + ZYNQ-7 TE0726_M Board File Image + + + + + + + 0.3 + 0.2 + + + + + 3.1 + + + ZYNQ-7S TE0726-07S ZynqBerry Board (form factor Raspberry Pi) with single ARM Cortex-A9, 512MB Memory, 100MBit Ethernet, speed grade -1 and commercial temperature range. Supported PCB Revisions: REV03 and REV02. Note: primary boot device is QSPI, SD can be used as secondary boot device only. + + + + + + + FPGA part on the board + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726_7S/3.1/part0_pins.xml b/zynqberrydemo3/board_files/TE0726_7S/3.1/part0_pins.xml new file mode 100644 index 0000000..0449cdd --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726_7S/3.1/part0_pins.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/zynqberrydemo3/board_files/TE0726_7S/3.1/preset.xml b/zynqberrydemo3/board_files/TE0726_7S/3.1/preset.xml new file mode 100644 index 0000000..764f8c6 --- /dev/null +++ b/zynqberrydemo3/board_files/TE0726_7S/3.1/preset.xml @@ -0,0 +1,283 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/zynqberrydemo3/console/readme.txt b/zynqberrydemo3/console/readme.txt new file mode 100644 index 0000000..922ccd0 --- /dev/null +++ b/zynqberrydemo3/console/readme.txt @@ -0,0 +1,4 @@ +Console command files for reference design root directory. +Use console command file for generation: +_create_linux_setup.sh +_create_win_setup.cmd \ No newline at end of file diff --git a/zynqberrydemo3/constraints/_i_bitgen_common.xdc b/zynqberrydemo3/constraints/_i_bitgen_common.xdc new file mode 100644 index 0000000..5c862d0 --- /dev/null +++ b/zynqberrydemo3/constraints/_i_bitgen_common.xdc @@ -0,0 +1,7 @@ +# +# Common BITGEN related settings for TE0726 +# +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property CFGBVS VCCO [current_design] + diff --git a/zynqberrydemo3/constraints/_i_common.xdc b/zynqberrydemo3/constraints/_i_common.xdc new file mode 100644 index 0000000..3077d50 --- /dev/null +++ b/zynqberrydemo3/constraints/_i_common.xdc @@ -0,0 +1,5 @@ +# +# +# +set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] + diff --git a/zynqberrydemo3/constraints/_i_csi.xdc b/zynqberrydemo3/constraints/_i_csi.xdc new file mode 100644 index 0000000..77d913e --- /dev/null +++ b/zynqberrydemo3/constraints/_i_csi.xdc @@ -0,0 +1,18 @@ +set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p] +set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}] +set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}] +set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}] +set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}] +set_property INTERNAL_VREF 0.6 [get_iobanks 34] +set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}] +# RPI Camera 1 +create_clock -period 6.250 -name csi_clk -add [get_ports csi_c_clk_p] +# RPI Camera 2.1 +#create_clock -period 1.875 -name csi_clk -add [get_ports csi_c_clk_p] + diff --git a/zynqberrydemo3/constraints/_i_hdmi.xdc b/zynqberrydemo3/constraints/_i_hdmi.xdc new file mode 100644 index 0000000..c45e7fe --- /dev/null +++ b/zynqberrydemo3/constraints/_i_hdmi.xdc @@ -0,0 +1,8 @@ +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p] +set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p] + +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[*]}] +set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}] +set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}] +set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}] + diff --git a/zynqberrydemo3/constraints/_i_te0726.xdc b/zynqberrydemo3/constraints/_i_te0726.xdc new file mode 100644 index 0000000..c259487 --- /dev/null +++ b/zynqberrydemo3/constraints/_i_te0726.xdc @@ -0,0 +1,90 @@ +#set_property IOSTANDARD LVCMOS33 [get_ports spdif_tx_o] +#set_property PACKAGE_PIN K15 [get_ports spdif_tx_o] + +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[*]}] +# GPIO Pins +# GPIO2 +set_property PACKAGE_PIN K15 [get_ports {gpio_1_tri_io[0]}] +# GPIO3 +set_property PACKAGE_PIN J14 [get_ports {gpio_1_tri_io[1]}] +# GPIO4 +set_property PACKAGE_PIN H12 [get_ports {gpio_1_tri_io[2]}] +# GPIO5 +set_property PACKAGE_PIN N14 [get_ports {gpio_1_tri_io[3]}] +# GPIO6 +set_property PACKAGE_PIN R15 [get_ports {gpio_1_tri_io[4]}] +# GPIO7 +set_property PACKAGE_PIN L14 [get_ports {gpio_1_tri_io[5]}] +# GPIO8 +set_property PACKAGE_PIN L15 [get_ports {gpio_1_tri_io[6]}] +# GPIO9 +set_property PACKAGE_PIN J13 [get_ports {gpio_1_tri_io[7]}] +# GPIO10 +set_property PACKAGE_PIN H14 [get_ports {gpio_1_tri_io[8]}] +# GPIO11 +set_property PACKAGE_PIN J15 [get_ports {gpio_1_tri_io[9]}] +# GPIO12 +set_property PACKAGE_PIN M15 [get_ports {gpio_1_tri_io[10]}] +# GPIO13 +set_property PACKAGE_PIN R13 [get_ports {gpio_1_tri_io[11]}] +# GPIO16 +set_property PACKAGE_PIN L13 [get_ports {gpio_1_tri_io[12]}] +# GPIO17 +set_property PACKAGE_PIN G11 [get_ports {gpio_1_tri_io[13]}] +# GPIO18 +set_property PACKAGE_PIN H11 [get_ports {gpio_1_tri_io[14]}] +# GPIO19 +set_property PACKAGE_PIN R12 [get_ports {gpio_1_tri_io[15]}] +# GPIO20 +set_property PACKAGE_PIN M14 [get_ports {gpio_1_tri_io[16]}] +# GPIO21 +set_property PACKAGE_PIN P15 [get_ports {gpio_1_tri_io[17]}] +# GPIO22 +set_property PACKAGE_PIN H13 [get_ports {gpio_1_tri_io[18]}] +# GPIO23 +set_property PACKAGE_PIN J11 [get_ports {gpio_1_tri_io[19]}] +# GPIO24 +set_property PACKAGE_PIN K11 [get_ports {gpio_1_tri_io[20]}] +# GPIO25 +set_property PACKAGE_PIN K13 [get_ports {gpio_1_tri_io[21]}] +# GPIO26 +set_property PACKAGE_PIN L12 [get_ports {gpio_1_tri_io[22]}] +# GPIO27 +set_property PACKAGE_PIN G12 [get_ports {gpio_1_tri_io[23]}] + +## DSI_D0_N +#set_property PACKAGE_PIN F13 [get_ports {gpio_1_tri_io[24]}] +## DSI_D0_P +#set_property PACKAGE_PIN F14 [get_ports {gpio_1_tri_io[25]}] +## DSI_D1_N +#set_property PACKAGE_PIN F12 [get_ports {gpio_1_tri_io[26]}] +## DSI_D1_P +#set_property PACKAGE_PIN E13 [get_ports {gpio_1_tri_io[27]}] +## DSI_C_N +#set_property PACKAGE_PIN E11 [get_ports {gpio_1_tri_io[28]}] +## DSI_C_P +#set_property PACKAGE_PIN E12 [get_ports {gpio_1_tri_io[29]}] + +## CSI_D0_N +#set_property PACKAGE_PIN M11 [get_ports {gpio_1_tri_io[30]}] +## CSI_D0_P +#set_property PACKAGE_PIN M10 [get_ports {gpio_1_tri_io[31]}] +## CSI_D1_N +#set_property PACKAGE_PIN P14 [get_ports {gpio_1_tri_io[32]}] +## CSI_D2_P +#set_property PACKAGE_PIN P13 [get_ports {gpio_1_tri_io[33]}] +## CSI_C_N +#set_property PACKAGE_PIN N12 [get_ports {gpio_1_tri_io[34]}] +## CSI_C_P +#set_property PACKAGE_PIN N11 [get_ports {gpio_1_tri_io[35]}] +## PWM_R +##set_property PACKAGE_PIN N8 [get_ports {gpio_1_tri_io[36]}] +## PWM_L +##set_property PACKAGE_PIN N7 [get_ports {gpio_1_tri_io[37]}] + +# PWM_R +set_property PACKAGE_PIN N8 [get_ports PWM_R] +# PWM_L +set_property PACKAGE_PIN N7 [get_ports PWM_L] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_*] + diff --git a/zynqberrydemo3/constraints/_i_timing.xdc b/zynqberrydemo3/constraints/_i_timing.xdc new file mode 100644 index 0000000..2f420d1 --- /dev/null +++ b/zynqberrydemo3/constraints/_i_timing.xdc @@ -0,0 +1,13 @@ +set_clock_groups -asynchronous -group [get_clocks clk_fpga_3] -group [get_clocks clk_fpga_0] +set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/tx_sync/out_data_reg[4]}] +set_property ASYNC_REG true [get_cells {zsys_i/audio/axi_i2s_adi_0/U0/ctrl/SDATA_O_reg[0]}] +set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_fpga_3] + +set_false_path -from [get_pins {zsys_i/axi_reg32_0/U0/axi_reg32_v1_0_S_AXI_inst/slv_reg16_reg[1]/C}] -to [get_pins zsys_i/video_in/axis_raw_demosaic_0/U0/colors_mode_i_reg/D] +set_false_path -from [get_pins zsys_i/video_in/csi_to_axis_0/U0/lane_align_inst/err_req_reg/C] -to [get_pins zsys_i/video_in/csi2_d_phy_rx_0/U0/clock_upd_req_reg/D] + +set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_max_first_increment_reg[2]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D] +set_false_path -from [get_pins {zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C}] -to [get_pins zsys_i/video_in/axi_vdma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D] + + + diff --git a/zynqberrydemo3/constraints/vivado_target.xdc b/zynqberrydemo3/constraints/vivado_target.xdc new file mode 100644 index 0000000..e69de29 diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/component.xml b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/component.xml new file mode 100644 index 0000000..5d57029 --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/component.xml @@ -0,0 +1,545 @@ + + + trenz.biz + user + Video_IO_2_HDMI_TMDS + 1.0 + + + vid_io_in + + + + + + + VBLANK + + + vid_vblank + + + + + ACTIVE_VIDEO + + + vid_active_video + + + + + VSYNC + + + vid_vsync + + + + + DATA + + + vid_data + + + + + HBLANK + + + vid_hblank + + + + + HSYNC + + + vid_hsync + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + Video_IO_2_HDMI_TMDS_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 1224790b + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + Video_IO_2_HDMI_TMDS_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 1224790b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 35d6fe5d + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + 799cb8bb + + + + + + + video_clk_in + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_clk5x_in + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + lock_in + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + vid_data + + in + + 23 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_active_video + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_hblank + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_vblank + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_hsync + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + vid_vsync + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + hdmi_data_p + + out + + 2 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + hdmi_data_n + + out + + 2 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + hdmi_clk_p + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + hdmi_clk_n + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_CLK_SWAP + HDMI CLK P/N Swap + FALSE + + + C_D0_SWAP + HDMI D0 P/N Swap + FALSE + + + C_D1_SWAP + HDMI D1 P/N Swap + FALSE + + + C_D2_SWAP + HDMI D2 P/N Swap + FALSE + + + C_INT_CLOCKING + C Int Clocking + true + + + C_VIDEO_MODE + Video Mode + 0 + + + + + + choice_pairs_c4f3a1c9 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/tmds_encoder.vhd + vhdlSource + + + src/serdes_ddr.vhd + vhdlSource + + + hdl/dvi_encoder.vhd + vhdlSource + + + hdl/clock_system.vhd + vhdlSource + + + hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd + vhdlSource + CHECKSUM_e3ad9cc9 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/tmds_encoder.vhd + vhdlSource + USED_IN_ipstatic + + + src/serdes_ddr.vhd + vhdlSource + + + hdl/dvi_encoder.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/clock_system.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/Video_IO_2_HDMI_TMDS_v1_0.tcl + tclSource + CHECKSUM_60af6022 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_utilityxitfiles_view_fileset + + gui/Video_IO_2_HDMI_TMDS_v1_0.gtcl + GTCL + + + + Video_IO_2_HDMI_TMDS + + + Component_Name + Video_IO_2_HDMI_TMDS_v1_0 + + + C_CLK_SWAP + HDMI CLK P/N Swap + FALSE + + + C_D0_SWAP + HDMI D0 P/N Swap + FALSE + + + C_D1_SWAP + HDMI D1 P/N Swap + FALSE + + + C_D2_SWAP + HDMI D2 P/N Swap + FALSE + + + C_VIDEO_MODE + Video Mode + 0 + + + + true + + + + + + C_INT_CLOCKING + Internal Clocks System + true + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /Video_&_Image_Processing + + Video IO to HDMI TMDS Interface v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 26 + + xilinx.com:user:Video_IO_2_HDMI_TMDS:1.0 + + 2017-05-12T14:48:23Z + + b:/cores/2015.4/design/te0726/iotest/ip_lib/video_io_2_hdmi_tmds_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/Video_IO_2_HDMI_TMDS_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd new file mode 100644 index 0000000..71e5f47 --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/Video_IO_2_HDMI_TMDS_v1_0.vhd @@ -0,0 +1,229 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity Video_IO_2_HDMI_TMDS_v1_0 is +generic ( + -- Pin swap options + C_CLK_SWAP : boolean := FALSE; + C_D0_SWAP : boolean := FALSE; + C_D1_SWAP : boolean := FALSE; + C_D2_SWAP : boolean := FALSE; + + -- Clocking options + C_INT_CLOCKING : BOOLEAN := TRUE; + C_VIDEO_MODE : integer range 0 to 8 := 2 +-- 0 = VGA (640x480 @ 60 Hz) 25 250 24b +-- 1 = 480p (720x480 @ 60 Hz) 27 270 24b +-- 2 = SVGA (800x600 @ 60 Hz) 40 400 24b +-- 3 = XGA (1024x768 @ 60 Hz) 65 650 24b +-- 4 = HD (1366x768 @ 60 Hz) 85.5 855 24b +-- 5 = WXGA (1280x800 @ 60 Hz) 71 710 24b +-- 6 = HDTV 720p (1280x720 @ 60 Hz) 74.25 742.5 24b +-- 7 = HDTV 1080i (1920x1080 @ 60 Hz interlaced) 74.25 742.5 24b +-- 8 = SXGA (1280x1024 @ 60 Hz) 108 1080 24b +); +port ( + -- Clocks + video_clk_in : in STD_LOGIC; -- Main clock Input + video_clk5x_in : in STD_LOGIC; -- SERDES clock Input + lock_in : in STD_LOGIC; -- External PLL locking + -- Video IO Interface + vid_data : in STD_LOGIC_VECTOR(23 downto 0); + vid_active_video : in STD_LOGIC; + vid_hblank : in STD_LOGIC; + vid_vblank : in STD_LOGIC; + vid_hsync : in STD_LOGIC; + vid_vsync : in STD_LOGIC; + -- HDMI Interface + hdmi_data_p : out STD_LOGIC_VECTOR(2 downto 0); + hdmi_data_n : out STD_LOGIC_VECTOR(2 downto 0); + hdmi_clk_p : out STD_LOGIC; + hdmi_clk_n : out STD_LOGIC +); +end Video_IO_2_HDMI_TMDS_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of Video_IO_2_HDMI_TMDS_v1_0 is +---------------------------------------------------------------------------------- +component clock_system is +generic( + C_VIDEO_MODE : integer range 0 to 9 := 2 +); +port ( + clk_in : in STD_LOGIC; + pclk1x : out STD_LOGIC; + pclk5x : out STD_LOGIC; + lock : out STD_LOGIC +); +end component; + +component serdes_ddr is +port ( + clk_in : in STD_LOGIC; + clk_dv_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(9 downto 0); + data_out : out STD_LOGIC +); +end component; + +component dvi_encoder is +port ( + clkin : in STD_LOGIC; + rstin : in STD_LOGIC; + blue_din : in STD_LOGIC_VECTOR(7 downto 0); + green_din : in STD_LOGIC_VECTOR(7 downto 0); + red_din : in STD_LOGIC_VECTOR(7 downto 0); + hsync : in STD_LOGIC; + vsync : in STD_LOGIC; + de : in STD_LOGIC; + blue_dout : out STD_LOGIC_VECTOR(9 downto 0); + green_dout : out STD_LOGIC_VECTOR(9 downto 0); + red_dout : out STD_LOGIC_VECTOR(9 downto 0) +); +end component; +---------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +-- Clock system +signal pclk5x : STD_LOGIC; +signal pclk1x : STD_LOGIC; +signal lock : STD_LOGIC; +signal reset : STD_LOGIC; +signal serdes_rst : STD_LOGIC; +-- Video system +signal red_data : STD_LOGIC_VECTOR(7 downto 0); +signal green_data : STD_LOGIC_VECTOR(7 downto 0); +signal blue_data : STD_LOGIC_VECTOR(7 downto 0); +type s_data_type is array (5 downto 0) of STD_LOGIC_VECTOR(9 downto 0); +signal s_data_r : s_data_type; +signal s_data_o : s_data_type; +signal tmds_out : STD_LOGIC_VECTOR(3 downto 0); +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +int_clock_sys: if C_INT_CLOCKING = TRUE generate +begin + -- Clock system + clock_system_inst: clock_system + generic map( + C_VIDEO_MODE => C_VIDEO_MODE + ) + port map( + clk_in => video_clk_in, + pclk1x => pclk1x, + pclk5x => pclk5x, + lock => lock + ); +end generate; +ext_clock_sys: if C_INT_CLOCKING = FALSE generate +begin + lock <= lock_in; + pclk1x <= video_clk_in; + pclk5x <= video_clk5x_in; +end generate; +---------------------------------------------------------------------------------- +serdes_rst <= not lock; +reset <= net_gnd; +---------------------------------------------------------------------------------- +-- Video system +red_data <= vid_data(23 downto 16); +green_data <= vid_data( 7 downto 0); +blue_data <= vid_data(15 downto 8); +-- Encoder +enc_inst: dvi_encoder +port map( + clkin => pclk1x, + rstin => reset, + blue_din => blue_data, + green_din => green_data, + red_din => red_data, + hsync => vid_hsync, + vsync => vid_vsync, + de => vid_active_video, + blue_dout => s_data_r(0), + green_dout => s_data_r(1), + red_dout => s_data_r(2) +); +-- HDMI Clock generation +s_data_r(3) <= b"11111_00000"; +---------------------------------------------------------------------------------- +-- Bitswap +---------------------------------------------------------------------------------- +d0_direct: if C_D0_SWAP = FALSE generate + s_data_o(0) <= s_data_r(0); +end generate; +d0_inv: if C_D0_SWAP = TRUE generate + s_data_o(0) <= not s_data_r(0); +end generate; + +d1_direct: if C_D1_SWAP = FALSE generate + s_data_o(1) <= s_data_r(1); +end generate; +d1_inv: if C_D1_SWAP = TRUE generate + s_data_o(1) <= not s_data_r(1); +end generate; + +d2_direct: if C_D2_SWAP = FALSE generate + s_data_o(2) <= s_data_r(2); +end generate; +d2_inv: if C_D2_SWAP = TRUE generate + s_data_o(2) <= not s_data_r(2); +end generate; + +clk_direct: if C_CLK_SWAP = FALSE generate + s_data_o(3) <= s_data_r(3); +end generate; +clk_inv: if C_CLK_SWAP = TRUE generate + s_data_o(3) <= not s_data_r(3); +end generate; +---------------------------------------------------------------------------------- +-- Serdes +---------------------------------------------------------------------------------- +HDMI_ddr_lines_gen: for i in 0 to 3 generate +begin + serdes_ddr_inst: serdes_ddr + port map( + clk_in => pclk5x, + clk_dv_in => pclk1x, + reset_in => serdes_rst, + data_in => s_data_o(i), + data_out => tmds_out(i) + ); +end generate; +---------------------------------------------------------------------------------- +-- Output buffers +---------------------------------------------------------------------------------- +obufds_d0_inst: OBUFDS +port map( + I => tmds_out(0), + O => hdmi_data_p(0), + OB => hdmi_data_n(0) +); +obufds_d1_inst: OBUFDS +port map( + I => tmds_out(1), + O => hdmi_data_p(1), + OB => hdmi_data_n(1) +); +obufds_d2_inst: OBUFDS +port map( + I => tmds_out(2), + O => hdmi_data_p(2), + OB => hdmi_data_n(2) +); +obufds_clk_inst: OBUFDS +port map( + I => tmds_out(3), + O => hdmi_clk_p, + OB => hdmi_clk_n +); +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/clock_system.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/clock_system.vhd new file mode 100644 index 0000000..b0e23a8 --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/clock_system.vhd @@ -0,0 +1,282 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity clock_system is +generic( + C_VIDEO_MODE : integer range 0 to 8 := 2 +-- 0 = VGA (640x480 @ 60 Hz) 25 250 24b +-- 1 = 480p (720x480 @ 60 Hz) 27 270 24b +-- 2 = SVGA (800x600 @ 60 Hz) 40 400 24b +-- 3 = XGA (1024x768 @ 60 Hz) 65 650 24b +-- 4 = HD (1366x768 @ 60 Hz) 85.5 855 24b +-- 5 = WXGA (1280x800 @ 60 Hz) 71 710 24b +-- 6 = HDTV 720p (1280x720 @ 60 Hz) 74.25 742.5 24b +-- 7 = HDTV 1080i (1920x1080 @ 60 Hz interlaced) 74.25 742.5 24b +-- 8 = SXGA (1280x1024 @ 60 Hz) 108 1080 24b +); +port ( + clk_in : in STD_LOGIC; + pclk1x : out STD_LOGIC; + pclk5x : out STD_LOGIC; + lock : out STD_LOGIC +); +end clock_system; +------------------------------------------------------------------------------- +architecture Behavioral of clock_system is +------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +-- Clock system +signal clkfbout : STD_LOGIC; +signal pllclk5x_pll : STD_LOGIC; +signal pllclk5x_pll_g : STD_LOGIC; +signal pllclk1x_pll : STD_LOGIC; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +VGA_gen: if C_VIDEO_MODE = 0 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 40.0, + CLKFBOUT_MULT => 20, -- x10 clock + CLKOUT0_DIVIDE => 4, -- x5 clock + CLKOUT1_DIVIDE => 20, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +m480p_gen: if C_VIDEO_MODE = 1 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 37.037, + CLKFBOUT_MULT => 20, -- x10 clock + CLKOUT0_DIVIDE => 4, -- x5 clock + CLKOUT1_DIVIDE => 20, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +SVGA_gen: if C_VIDEO_MODE = 2 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 25.0, + CLKFBOUT_MULT => 20, -- x10 clock + CLKOUT0_DIVIDE => 4, -- x5 clock + CLKOUT1_DIVIDE => 20, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +XGA_gen: if C_VIDEO_MODE = 3 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 15.3846, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +HD_gen: if C_VIDEO_MODE = 4 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 11.6959, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +WXGA_gen: if C_VIDEO_MODE = 5 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 14.0845, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +HDTV_720p_gen: if C_VIDEO_MODE = 6 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 13.468, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +HDTV_1080p_gen: if C_VIDEO_MODE = 7 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 13.468, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +SXGA_gen: if C_VIDEO_MODE = 8 generate +begin +pll_inst: PLL_BASE +generic map( + CLKIN_PERIOD => 9.2592, + CLKFBOUT_MULT => 10, -- x10 clock + CLKOUT0_DIVIDE => 2, -- x5 clock + CLKOUT1_DIVIDE => 10, -- x1 clock + COMPENSATION => "INTERNAL" +) +port map ( + CLKFBOUT => clkfbout, + CLKOUT0 => pllclk5x_pll, + CLKOUT1 => pllclk1x_pll, + CLKOUT2 => open, + CLKOUT3 => open, + CLKOUT4 => open, + CLKOUT5 => open, + LOCKED => lock, + CLKFBIN => clkfbout, + CLKIN => clk_in, + RST => net_gnd +); +end generate; +------------------------------------------------------------------------------- +dclk_BUFIO_inst : BUFIO +port map ( + I => pllclk5x_pll, + O => pclk5x +); + +out_clk_BUFG_inst : BUFG +port map ( + I => pllclk1x_pll, + O => pclk1x +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/convert_30to15_fifo.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/convert_30to15_fifo.vhd new file mode 100644 index 0000000..cdcde89 --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/convert_30to15_fifo.vhd @@ -0,0 +1,194 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity convert_30to15_fifo is +port ( + rst : in STD_LOGIC; -- reset + clk : in STD_LOGIC; -- clock input + clkx2 : in STD_LOGIC; -- 2x clock input + datain : in STD_LOGIC_VECTOR(29 downto 0); -- input data for 2:1 serialisation + dataout : out STD_LOGIC_VECTOR(14 downto 0) +); +end convert_30to15_fifo; +------------------------------------------------------------------------------- +architecture Behavioral of convert_30to15_fifo is +------------------------------------------------------------------------------- +constant net_vcc : STD_LOGIC := '1'; + +component dram16xn is +generic( + DATA_WIDTH : integer := 20 +); +port ( + clk : in STD_LOGIC; + write_en : in STD_LOGIC; + address : in STD_LOGIC_VECTOR(3 downto 0); + address_dp : in STD_LOGIC_VECTOR(3 downto 0); + data_in : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); + o_data_out : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); + o_data_out_dp : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) +); +end component; + +---------------------------------------------------- +-- Here we instantiate a 16x10 Dual Port RAM +-- and fill first it with data aligned to +-- clk domain +---------------------------------------------------- +signal wa : STD_LOGIC_VECTOR( 3 downto 0); -- RAM read address +signal wa_d : STD_LOGIC_VECTOR( 3 downto 0); -- RAM read address +signal ra : STD_LOGIC_VECTOR( 3 downto 0); -- RAM read address +signal ra_d : STD_LOGIC_VECTOR( 3 downto 0); -- RAM read address +signal dataint : STD_LOGIC_VECTOR(29 downto 0); -- RAM output + +constant ADDR0 : STD_LOGIC_VECTOR(3 downto 0) := "0000"; +constant ADDR1 : STD_LOGIC_VECTOR(3 downto 0) := "0001"; +constant ADDR2 : STD_LOGIC_VECTOR(3 downto 0) := "0010"; +constant ADDR3 : STD_LOGIC_VECTOR(3 downto 0) := "0011"; +constant ADDR4 : STD_LOGIC_VECTOR(3 downto 0) := "0100"; +constant ADDR5 : STD_LOGIC_VECTOR(3 downto 0) := "0101"; +constant ADDR6 : STD_LOGIC_VECTOR(3 downto 0) := "0110"; +constant ADDR7 : STD_LOGIC_VECTOR(3 downto 0) := "0111"; +constant ADDR8 : STD_LOGIC_VECTOR(3 downto 0) := "1000"; +constant ADDR9 : STD_LOGIC_VECTOR(3 downto 0) := "1001"; +constant ADDR10 : STD_LOGIC_VECTOR(3 downto 0) := "1010"; +constant ADDR11 : STD_LOGIC_VECTOR(3 downto 0) := "1011"; +constant ADDR12 : STD_LOGIC_VECTOR(3 downto 0) := "1100"; +constant ADDR13 : STD_LOGIC_VECTOR(3 downto 0) := "1101"; +constant ADDR14 : STD_LOGIC_VECTOR(3 downto 0) := "1110"; +constant ADDR15 : STD_LOGIC_VECTOR(3 downto 0) := "1111"; + +signal rstsync : STD_LOGIC; +signal rstsync_q : STD_LOGIC; +signal rstp : STD_LOGIC; +signal sync : STD_LOGIC; +signal db : STD_LOGIC_VECTOR(29 downto 0); +signal mux : STD_LOGIC_VECTOR(14 downto 0); +------------------------------------------------------------------------------- +attribute ASYNC_REG : string; +attribute ASYNC_REG of rstsync : signal is "true"; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +process(wa) +begin + case wa is + when ADDR0 => wa_d <= ADDR1 ; + when ADDR1 => wa_d <= ADDR2 ; + when ADDR2 => wa_d <= ADDR3 ; + when ADDR3 => wa_d <= ADDR4 ; + when ADDR4 => wa_d <= ADDR5 ; + when ADDR5 => wa_d <= ADDR6 ; + when ADDR6 => wa_d <= ADDR7 ; + when ADDR7 => wa_d <= ADDR8 ; + when ADDR8 => wa_d <= ADDR9 ; + when ADDR9 => wa_d <= ADDR10; + when ADDR10 => wa_d <= ADDR11; + when ADDR11 => wa_d <= ADDR12; + when ADDR12 => wa_d <= ADDR13; + when ADDR13 => wa_d <= ADDR14; + when ADDR14 => wa_d <= ADDR15; + when others => wa_d <= ADDR0; + end case; +end process; + +process(clk, rst) +begin + if(rst = '1')then + wa <= (others => '0'); + elsif(clk = '1' and clk'event)then + wa <= wa_d; + end if; +end process; + +-- Dual Port fifo to bridge data from clk to clkx2 +fifo_inst: dram16xn +generic map( + DATA_WIDTH => 30 +) +port map( + clk => clk, + write_en => net_vcc, + address => wa, + address_dp => ra, + data_in => datain, + o_data_out => open, + o_data_out_dp => dataint +); + +----------------------------------------------------------------/ +-- Here starts clk2x domain for fifo read out +-- FIFO read is set to be once every 2 cycles of clk2x in order +-- to keep up pace with the fifo write speed +-- Also FIFO read reset is delayed a bit in order to avoid +-- underflow. +----------------------------------------------------------------/ +process(ra) +begin + case ra is + when ADDR0 => ra_d <= ADDR1 ; + when ADDR1 => ra_d <= ADDR2 ; + when ADDR2 => ra_d <= ADDR3 ; + when ADDR3 => ra_d <= ADDR4 ; + when ADDR4 => ra_d <= ADDR5 ; + when ADDR5 => ra_d <= ADDR6 ; + when ADDR6 => ra_d <= ADDR7 ; + when ADDR7 => ra_d <= ADDR8 ; + when ADDR8 => ra_d <= ADDR9 ; + when ADDR9 => ra_d <= ADDR10; + when ADDR10 => ra_d <= ADDR11; + when ADDR11 => ra_d <= ADDR12; + when ADDR12 => ra_d <= ADDR13; + when ADDR13 => ra_d <= ADDR14; + when ADDR14 => ra_d <= ADDR15; + when others => ra_d <= ADDR0; + end case; +end process; + +fdp_rst: FDP +port map( + C => clkx2, + D => rst, + PRE => rst, + Q => rstsync +); + +fd_rstsync: FD +port map( + C => clkx2, + D => rstsync, + Q => rstsync_q +); + +fd_rstp: FD +port map( + C => clkx2, + D => rstsync_q, + Q => rstp +); + +mux <= db(14 downto 0) when (sync = '0') else db(29 downto 15); + +process(clkx2, rstp) +begin + if(rstp = '1')then + sync <= '0'; + ra <= (others => '0'); + elsif(clkx2 = '1' and clkx2'event)then + sync <= not sync; + if(sync = '1')then + ra <= ra_d; + db <= dataint; + end if; + dataout <= mux; + end if; +end process; +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dram16xn.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dram16xn.vhd new file mode 100644 index 0000000..e7d15c0 --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dram16xn.vhd @@ -0,0 +1,51 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity dram16xn is +generic( + DATA_WIDTH : integer := 20 +); +port ( + clk : in STD_LOGIC; + write_en : in STD_LOGIC; + address : in STD_LOGIC_VECTOR(3 downto 0); + address_dp : in STD_LOGIC_VECTOR(3 downto 0); + data_in : in STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); + o_data_out : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0); + o_data_out_dp : out STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) +); +end dram16xn; +------------------------------------------------------------------------------- +architecture Behavioral of dram16xn is +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +bit_gen: for i in 0 to DATA_WIDTH-1 generate +begin + ram_inst: RAM16X1D + port map( + D => data_in(i), --insert input signal + WE => write_en, --insert Write Enable signal + WCLK => clk, --insert Write Clock signal + A0 => address(0), --insert Address 0 signal port SPO + A1 => address(1), --insert Address 1 signal port SPO + A2 => address(2), --insert Address 2 signal port SPO + A3 => address(3), --insert Address 3 signal port SPO + DPRA0 => address_dp(0), --insert Address 0 signal dual port DPO + DPRA1 => address_dp(1), --insert Address 1 signal dual port DPO + DPRA2 => address_dp(2), --insert Address 2 signal dual port DPO + DPRA3 => address_dp(3), --insert Address 3 signal dual port DPO + SPO => o_data_out(i), --insert output signal SPO + DPO => o_data_out_dp(i) --insert output signal DPO + ); +end generate; +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dvi_encoder.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dvi_encoder.vhd new file mode 100644 index 0000000..6f2154a --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/dvi_encoder.vhd @@ -0,0 +1,75 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +---------------------------------------------------------------------------------- +entity dvi_encoder is +port ( + clkin : in STD_LOGIC; -- pixel clock + rstin : in STD_LOGIC; -- reset + blue_din : in STD_LOGIC_VECTOR(7 downto 0); -- Blue data in + green_din : in STD_LOGIC_VECTOR(7 downto 0); -- Green data in + red_din : in STD_LOGIC_VECTOR(7 downto 0); -- Red data in + hsync : in STD_LOGIC; -- hsync data + vsync : in STD_LOGIC; -- vsync data + de : in STD_LOGIC; -- data enable + blue_dout : out STD_LOGIC_VECTOR(9 downto 0); + green_dout : out STD_LOGIC_VECTOR(9 downto 0); + red_dout : out STD_LOGIC_VECTOR(9 downto 0) +); +end dvi_encoder; +------------------------------------------------------------------------------- +architecture Behavioral of dvi_encoder is +------------------------------------------------------------------------------- +constant net_gnd : STD_LOGIC := '0'; +component tmds_encoder is +port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(7 downto 0); + c0_in : in STD_LOGIC; + c1_in : in STD_LOGIC; + de_in : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR(9 downto 0) +); +end component; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +encb_inst: tmds_encoder +port map( + clk_in => clkin, + rst_in => rstin, + data_in => blue_din, + c0_in => hsync, + c1_in => vsync, + de_in => de, + data_out => blue_dout +); + +encg_inst: tmds_encoder +port map( + clk_in => clkin, + rst_in => rstin, + data_in => green_din, + c0_in => net_gnd, + c1_in => net_gnd, + de_in => de, + data_out => green_dout +); + +encr_inst: tmds_encoder +port map( + clk_in => clkin, + rst_in => rstin, + data_in => red_din, + c0_in => net_gnd, + c1_in => net_gnd, + de_in => de, + data_out => red_dout +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes.vhd new file mode 100644 index 0000000..44d7c3c --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes.vhd @@ -0,0 +1,79 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity serdes is +port ( + clk_in : in STD_LOGIC; + clk_dv_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(4 downto 0); + data_out : out STD_LOGIC +); +end serdes; +------------------------------------------------------------------------------- +architecture Behavioral of serdes is +------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +OSERDESE2_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "SDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "SDR", -- "BUF", "SDR" or "DDR" + -- DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + -- DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 5, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => data_out, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => open, + SHIFTOUT2 => open, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => data_in(0), + D2 => data_in(1), + D3 => data_in(2), + D4 => data_in(3), + D5 => data_in(4), + D6 => net_gnd, + D7 => net_gnd, + D8 => net_gnd, + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => net_gnd, + SHIFTIN2 => net_gnd, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes_ddr.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes_ddr.vhd new file mode 100644 index 0000000..df0dd2c --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/serdes_ddr.vhd @@ -0,0 +1,128 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity serdes_ddr is +port ( + clk_in : in STD_LOGIC; + clk_dv_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(9 downto 0); + data_out : out STD_LOGIC +); +end serdes_ddr; +------------------------------------------------------------------------------- +architecture Behavioral of serdes_ddr is +------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +-- Signals +signal shift_a : STD_LOGIC; +signal shift_b : STD_LOGIC; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +OSERDESE2_m_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 10, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => data_out, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => open, + SHIFTOUT2 => open, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => data_in(0), + D2 => data_in(1), + D3 => data_in(2), + D4 => data_in(3), + D5 => data_in(4), + D6 => data_in(5), + D7 => data_in(6), + D8 => data_in(7), + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => shift_a, + SHIFTIN2 => shift_b, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); + +OSERDESE2_s_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 10, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => open, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => shift_a, + SHIFTOUT2 => shift_b, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => net_gnd, + D2 => net_gnd, + D3 => data_in(8), + D4 => data_in(9), + D5 => net_gnd, + D6 => net_gnd, + D7 => net_gnd, + D8 => net_gnd, + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => net_gnd, + SHIFTIN2 => net_gnd, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/tmds_encoder.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/tmds_encoder.vhd new file mode 100644 index 0000000..468dddb --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/hdl/tmds_encoder.vhd @@ -0,0 +1,180 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +---------------------------------------------------------------------------------- +entity tmds_encoder is +port ( + clk_in : in STD_LOGIC; + rst_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(7 downto 0); + c0_in : in STD_LOGIC; + c1_in : in STD_LOGIC; + de_in : in STD_LOGIC; + data_out : out STD_LOGIC_VECTOR(9 downto 0) +); +end tmds_encoder; +------------------------------------------------------------------------------- +architecture Behavioral of tmds_encoder is +------------------------------------------------------------------------------- +signal n1d : UNSIGNED(3 downto 0); -- number of 1s in din +signal din_q : STD_LOGIC_VECTOR(7 downto 0); +signal decision_a : STD_LOGIC; +signal decision_b : STD_LOGIC; +signal decision_c : STD_LOGIC; +signal q_m : STD_LOGIC_VECTOR(8 downto 0); +signal n1q_m : UNSIGNED(3 downto 0); -- number of 1s and 0s for q_m +signal n0q_m : UNSIGNED(3 downto 0); +signal cnt : UNSIGNED(4 downto 0); -- disparity counter, MSB is the sign bit + +constant CTRLTOKEN0 : STD_LOGIC_VECTOR(9 downto 0) := b"1101010100"; +constant CTRLTOKEN1 : STD_LOGIC_VECTOR(9 downto 0) := b"0010101011"; +constant CTRLTOKEN2 : STD_LOGIC_VECTOR(9 downto 0) := b"0101010100"; +constant CTRLTOKEN3 : STD_LOGIC_VECTOR(9 downto 0) := b"1010101011"; + +signal de_q : STD_LOGIC; +signal de_reg : STD_LOGIC; +signal c0_q : STD_LOGIC; +signal c1_q : STD_LOGIC; +signal c_reg : STD_LOGIC_VECTOR(1 downto 0); +signal q_m_reg : STD_LOGIC_VECTOR(8 downto 0); +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + n1d <= + resize(UNSIGNED(data_in(0 downto 0)),4) + + resize(UNSIGNED(data_in(1 downto 1)),4) + + resize(UNSIGNED(data_in(2 downto 2)),4) + + resize(UNSIGNED(data_in(3 downto 3)),4) + + resize(UNSIGNED(data_in(4 downto 4)),4) + + resize(UNSIGNED(data_in(5 downto 5)),4) + + resize(UNSIGNED(data_in(6 downto 6)),4) + + resize(UNSIGNED(data_in(7 downto 7)),4); + din_q <= data_in; + end if; +end process; + +--assign decision1 = (n1d > 4'h4) | ((n1d == 4'h4) & (din_q(0] == 1'b0)); +decision_a <= '1' when ((n1d > to_unsigned(4,4)) or ((n1d = to_unsigned(4,4)) and (din_q(0) = '0'))) else '0'; + +q_m(0) <= din_q(0); +q_m(1) <= (q_m(0) xnor din_q(1)) when (decision_a = '1') else (q_m(0) xor din_q(1)); +q_m(2) <= (q_m(1) xnor din_q(2)) when (decision_a = '1') else (q_m(1) xor din_q(2)); +q_m(3) <= (q_m(2) xnor din_q(3)) when (decision_a = '1') else (q_m(2) xor din_q(3)); +q_m(4) <= (q_m(3) xnor din_q(4)) when (decision_a = '1') else (q_m(3) xor din_q(4)); +q_m(5) <= (q_m(4) xnor din_q(5)) when (decision_a = '1') else (q_m(4) xor din_q(5)); +q_m(6) <= (q_m(5) xnor din_q(6)) when (decision_a = '1') else (q_m(5) xor din_q(6)); +q_m(7) <= (q_m(6) xnor din_q(7)) when (decision_a = '1') else (q_m(6) xor din_q(7)); +q_m(8) <= '0' when (decision_a = '1') else '1'; +------------------------------------------------------------------------------- +-- Stage 2: 9 bit -> 10 bit +-- Refer to DVI 1.0 Specification, page 29, Figure 3-5 +------------------------------------------------------------------------------- +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + n1q_m <= + resize(UNSIGNED(q_m(0 downto 0)),4) + + resize(UNSIGNED(q_m(1 downto 1)),4) + + resize(UNSIGNED(q_m(2 downto 2)),4) + + resize(UNSIGNED(q_m(3 downto 3)),4) + + resize(UNSIGNED(q_m(4 downto 4)),4) + + resize(UNSIGNED(q_m(5 downto 5)),4) + + resize(UNSIGNED(q_m(6 downto 6)),4) + + resize(UNSIGNED(q_m(7 downto 7)),4); + n0q_m <= + to_unsigned(8,4) - ( + resize(UNSIGNED(q_m(0 downto 0)),4) + + resize(UNSIGNED(q_m(1 downto 1)),4) + + resize(UNSIGNED(q_m(2 downto 2)),4) + + resize(UNSIGNED(q_m(3 downto 3)),4) + + resize(UNSIGNED(q_m(4 downto 4)),4) + + resize(UNSIGNED(q_m(5 downto 5)),4) + + resize(UNSIGNED(q_m(6 downto 6)),4) + + resize(UNSIGNED(q_m(7 downto 7)),4)); + end if; +end process; + +decision_b <= '1' when ((cnt = to_unsigned(0,5)) or (n1q_m = n0q_m)) else '0'; +------------------------------------------------------------------------------- +-- [(cnt > 0) and (N1q_m > N0q_m)] or [(cnt < 0) and (N0q_m > N1q_m)] +------------------------------------------------------------------------------- +decision_c <= '1' when ((cnt(4) = '0') and (n1q_m > n0q_m)) or ((cnt(4) = '1') and (n0q_m > n1q_m)) else '0'; +------------------------------------------------------------------------------- +-- pipe line alignment +------------------------------------------------------------------------------- +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + de_q <= de_in; + de_reg <= de_q; + c0_q <= c0_in; + c1_q <= c1_in; + q_m_reg <= q_m; + c_reg <= c1_q & c0_q; + end if; +end process; +------------------------------------------------------------------------------- +-- 10-bit out +-- disparity counter +------------------------------------------------------------------------------- +process(clk_in, rst_in) +begin + if(rst_in = '1')then + data_out <= (others => '0'); + cnt <= (others => '0'); + elsif(clk_in = '1' and clk_in'event)then + if(de_reg = '1')then + if(decision_b = '1')then + data_out(9) <= not q_m_reg(8); + data_out(8) <= q_m_reg(8); + if(q_m_reg(8) = '1')then + data_out(7 downto 0) <= q_m_reg(7 downto 0); + else + data_out(7 downto 0) <= not q_m_reg(7 downto 0); + end if; + if(q_m_reg(8) = '0')then + cnt <= cnt + resize(n0q_m,5) - resize(n1q_m,5); + else + cnt <= cnt + resize(n1q_m,5) - resize(n0q_m,5); + end if; + else + if(decision_c = '1')then + data_out(9) <= '1'; + data_out(8) <= q_m_reg(8); + data_out(7 downto 0) <= not q_m_reg(7 downto 0); + if(q_m_reg(8) = '1')then + cnt <= cnt + to_unsigned(2,5) + (resize(n0q_m,5) - resize(n1q_m,5)); + else + cnt <= cnt + (resize(n0q_m,5) - resize(n1q_m,5)); + end if; + else + data_out(9) <= '0'; + data_out(8) <= q_m_reg(8); + data_out(7 downto 0) <= q_m_reg(7 downto 0); + if(q_m_reg(8) = '0')then + cnt <= cnt - to_unsigned(2,5) + (resize(n1q_m,5) - resize(n0q_m,5)); + else + cnt <= cnt + (resize(n1q_m,5) - resize(n0q_m,5)); + end if; + end if; + end if; + else + case(c_reg)is + when "00" => data_out <= CTRLTOKEN0; + when "01" => data_out <= CTRLTOKEN1; + when "10" => data_out <= CTRLTOKEN2; + when others => data_out <= CTRLTOKEN3; + end case; + cnt <= (others => '0'); + end if; + end if; +end process; +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/src/serdes_ddr.vhd b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/src/serdes_ddr.vhd new file mode 100644 index 0000000..df0dd2c --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/src/serdes_ddr.vhd @@ -0,0 +1,128 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +---------------------------------------------------------------------------------- +entity serdes_ddr is +port ( + clk_in : in STD_LOGIC; + clk_dv_in : in STD_LOGIC; + reset_in : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(9 downto 0); + data_out : out STD_LOGIC +); +end serdes_ddr; +------------------------------------------------------------------------------- +architecture Behavioral of serdes_ddr is +------------------------------------------------------------------------------- +-- Constants +constant net_gnd : STD_LOGIC := '0'; +constant net_vcc : STD_LOGIC := '1'; +-- Signals +signal shift_a : STD_LOGIC; +signal shift_b : STD_LOGIC; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +OSERDESE2_m_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 10, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "MASTER", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => data_out, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => open, + SHIFTOUT2 => open, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => data_in(0), + D2 => data_in(1), + D3 => data_in(2), + D4 => data_in(3), + D5 => data_in(4), + D6 => data_in(5), + D7 => data_in(6), + D8 => data_in(7), + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => shift_a, + SHIFTIN2 => shift_b, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); + +OSERDESE2_s_inst : OSERDESE2 +generic map ( + DATA_RATE_OQ => "DDR", -- "SDR" or "DDR" + DATA_RATE_TQ => "DDR", -- "BUF", "SDR" or "DDR" + DATA_WIDTH => 10, -- Parallel data width (2-8,10) + INIT_OQ => '0', -- Initial value of OQ output (0/1) + INIT_TQ => '0', -- Initial value of TQ output (0/1) + SERDES_MODE => "SLAVE", -- "MASTER" or "SLAVE" + SRVAL_OQ => '0', -- OQ output value when SR is used (0/1) + SRVAL_TQ => '0', -- TQ output value when SR is used (0/1) + TBYTE_CTL => "FALSE", -- Enable tristate byte operation ("TRUE" or "FALSE") + TBYTE_SRC => "FALSE", -- Tristate byte source ("TRUE" or "FALSE") + TRISTATE_WIDTH => 1 -- 3-state converter width (1 or 4) +) +port map ( + OFB => open, -- 1-bit output: Feedback path for data output + OQ => open, -- 1-bit output: Data path output + -- SHIFTOUT1/SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each) + SHIFTOUT1 => shift_a, + SHIFTOUT2 => shift_b, + TBYTEOUT => open, -- 1-bit output: Byte group tristate output + TFB => open, -- 1-bit output: 3-state control output + TQ => open, -- 1-bit output: 3-state control output + CLK => clk_in, -- 1-bit input: High speed clock input + CLKDIV => clk_dv_in, -- 1-bit input: Divided clock input + -- D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) + D1 => net_gnd, + D2 => net_gnd, + D3 => data_in(8), + D4 => data_in(9), + D5 => net_gnd, + D6 => net_gnd, + D7 => net_gnd, + D8 => net_gnd, + OCE => net_vcc, -- 1-bit input: Output data clock enable input + RST => reset_in, -- 1-bit input: Reset input + -- SHIFTIN1/SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each) + SHIFTIN1 => net_gnd, + SHIFTIN2 => net_gnd, + -- T1 - T4: 1-bit (each) input: Parallel 3-state inputs + T1 => net_gnd, + T2 => net_gnd, + T3 => net_gnd, + T4 => net_gnd, + TBYTEIN => net_gnd, -- 1-bit input: Byte group tristate input + TCE => net_gnd -- 1-bit input: 3-state clock enable input +); +-------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/xgui/Video_IO_2_HDMI_TMDS_v1_0.tcl b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/xgui/Video_IO_2_HDMI_TMDS_v1_0.tcl new file mode 100644 index 0000000..02321a4 --- /dev/null +++ b/zynqberrydemo3/ip_lib/Video_IO_2_HDMI_TMDS_1.0/xgui/Video_IO_2_HDMI_TMDS_v1_0.tcl @@ -0,0 +1,119 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/Video_IO_2_HDMI_TMDS_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set Clocking [ipgui::add_group $IPINST -name "Clocking" -parent ${Page_0} -display_name {Clocking Options}] + ipgui::add_param $IPINST -name "C_INT_CLOCKING" -parent ${Clocking} + ipgui::add_param $IPINST -name "C_VIDEO_MODE" -parent ${Clocking} -widget comboBox + + #Adding Group + set Pins_swap [ipgui::add_group $IPINST -name "Pins swap" -parent ${Page_0}] + ipgui::add_param $IPINST -name "C_CLK_SWAP" -parent ${Pins_swap} + ipgui::add_param $IPINST -name "C_D0_SWAP" -parent ${Pins_swap} + ipgui::add_param $IPINST -name "C_D1_SWAP" -parent ${Pins_swap} + ipgui::add_param $IPINST -name "C_D2_SWAP" -parent ${Pins_swap} + + + +} + +proc update_PARAM_VALUE.C_VIDEO_MODE { PARAM_VALUE.C_VIDEO_MODE PARAM_VALUE.C_INT_CLOCKING } { + # Procedure called to update C_VIDEO_MODE when any of the dependent parameters in the arguments change + + set C_VIDEO_MODE ${PARAM_VALUE.C_VIDEO_MODE} + set C_INT_CLOCKING ${PARAM_VALUE.C_INT_CLOCKING} + set values(C_INT_CLOCKING) [get_property value $C_INT_CLOCKING] + if { [gen_USERPARAMETER_C_VIDEO_MODE_ENABLEMENT $values(C_INT_CLOCKING)] } { + set_property enabled true $C_VIDEO_MODE + } else { + set_property enabled false $C_VIDEO_MODE + } +} + +proc validate_PARAM_VALUE.C_VIDEO_MODE { PARAM_VALUE.C_VIDEO_MODE } { + # Procedure called to validate C_VIDEO_MODE + return true +} + +proc update_PARAM_VALUE.C_CLK_SWAP { PARAM_VALUE.C_CLK_SWAP } { + # Procedure called to update C_CLK_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_CLK_SWAP { PARAM_VALUE.C_CLK_SWAP } { + # Procedure called to validate C_CLK_SWAP + return true +} + +proc update_PARAM_VALUE.C_D0_SWAP { PARAM_VALUE.C_D0_SWAP } { + # Procedure called to update C_D0_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D0_SWAP { PARAM_VALUE.C_D0_SWAP } { + # Procedure called to validate C_D0_SWAP + return true +} + +proc update_PARAM_VALUE.C_D1_SWAP { PARAM_VALUE.C_D1_SWAP } { + # Procedure called to update C_D1_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D1_SWAP { PARAM_VALUE.C_D1_SWAP } { + # Procedure called to validate C_D1_SWAP + return true +} + +proc update_PARAM_VALUE.C_D2_SWAP { PARAM_VALUE.C_D2_SWAP } { + # Procedure called to update C_D2_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D2_SWAP { PARAM_VALUE.C_D2_SWAP } { + # Procedure called to validate C_D2_SWAP + return true +} + +proc update_PARAM_VALUE.C_INT_CLOCKING { PARAM_VALUE.C_INT_CLOCKING } { + # Procedure called to update C_INT_CLOCKING when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_INT_CLOCKING { PARAM_VALUE.C_INT_CLOCKING } { + # Procedure called to validate C_INT_CLOCKING + return true +} + + +proc update_MODELPARAM_VALUE.C_CLK_SWAP { MODELPARAM_VALUE.C_CLK_SWAP PARAM_VALUE.C_CLK_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_CLK_SWAP}] ${MODELPARAM_VALUE.C_CLK_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D0_SWAP { MODELPARAM_VALUE.C_D0_SWAP PARAM_VALUE.C_D0_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D0_SWAP}] ${MODELPARAM_VALUE.C_D0_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D1_SWAP { MODELPARAM_VALUE.C_D1_SWAP PARAM_VALUE.C_D1_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D1_SWAP}] ${MODELPARAM_VALUE.C_D1_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D2_SWAP { MODELPARAM_VALUE.C_D2_SWAP PARAM_VALUE.C_D2_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D2_SWAP}] ${MODELPARAM_VALUE.C_D2_SWAP} +} + +proc update_MODELPARAM_VALUE.C_INT_CLOCKING { MODELPARAM_VALUE.C_INT_CLOCKING PARAM_VALUE.C_INT_CLOCKING } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_INT_CLOCKING}] ${MODELPARAM_VALUE.C_INT_CLOCKING} +} + +proc update_MODELPARAM_VALUE.C_VIDEO_MODE { MODELPARAM_VALUE.C_VIDEO_MODE PARAM_VALUE.C_VIDEO_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_VIDEO_MODE}] ${MODELPARAM_VALUE.C_VIDEO_MODE} +} + diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/bd/bd.tcl b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/bd/bd.tcl new file mode 100644 index 0000000..4804aeb --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/component.xml b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/component.xml new file mode 100644 index 0000000..dc899b3 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/component.xml @@ -0,0 +1,1973 @@ + + + digilentinc.com + user + axi_i2s_adi + 1.2 + + + S00_AXI + + + + + + + + + AWADDR + + + s00_axi_awaddr + + + + + AWPROT + + + s00_axi_awprot + + + + + AWVALID + + + s00_axi_awvalid + + + + + AWREADY + + + s00_axi_awready + + + + + WDATA + + + s00_axi_wdata + + + + + WSTRB + + + s00_axi_wstrb + + + + + WVALID + + + s00_axi_wvalid + + + + + WREADY + + + s00_axi_wready + + + + + BRESP + + + s00_axi_bresp + + + + + BVALID + + + s00_axi_bvalid + + + + + BREADY + + + s00_axi_bready + + + + + ARADDR + + + s00_axi_araddr + + + + + ARPROT + + + s00_axi_arprot + + + + + ARVALID + + + s00_axi_arvalid + + + + + ARREADY + + + s00_axi_arready + + + + + RDATA + + + s00_axi_rdata + + + + + RRESP + + + s00_axi_rresp + + + + + RVALID + + + s00_axi_rvalid + + + + + RREADY + + + s00_axi_rready + + + + + + WIZ.DATA_WIDTH + 32 + + + WIZ.NUM_REG + 12 + + + SUPPORTS_NARROW_BURST + 0 + + + + + S00_AXI_RST + + + + + + + RST + + + s00_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S00_AXI_CLK + + + + + + + CLK + + + s00_axi_aclk + + + + + + ASSOCIATED_BUSIF + S00_AXI + + + ASSOCIATED_RESET + s00_axi_aresetn + + + + + S_AXIS + + + + + + + TVALID + + + S_AXIS_TVALID + + + + + TLAST + + + S_AXIS_TLAST + + + + + TDATA + + + S_AXIS_TDATA + + + + + TREADY + + + S_AXIS_TREADY + + + + + + + optional + true + + + + + + S_AXIS_CLK + + + + + + + CLK + + + S_AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + S_AXIS + + + + + + optional + true + + + + + + M_AXIS + + + + + + + TVALID + + + M_AXIS_TVALID + + + + + TLAST + + + M_AXIS_TLAST + + + + + TDATA + + + M_AXIS_TDATA + + + + + TKEEP + + + M_AXIS_TKEEP + + + + + TREADY + + + M_AXIS_TREADY + + + + + + + optional + true + + + + + + M_AXIS_CLK + + + + + + + CLK + + + M_AXIS_ACLK + + + + + + ASSOCIATED_BUSIF + M_AXIS + + + + + + optional + true + + + + + + DMA_TX_REQ + + + + + + + TUSER + + + DMA_REQ_TX_DRTYPE + + + + + TVALID + + + DMA_REQ_TX_DRVALID + + + + + TLAST + + + DMA_REQ_TX_DRLAST + + + + + TREADY + + + DMA_REQ_TX_DRREADY + + + + + + + optional + false + + + + + + DMA_TX_ACK + + + + + + + TUSER + + + DMA_REQ_TX_DATYPE + + + + + TVALID + + + DMA_REQ_TX_DAVALID + + + + + TREADY + + + DMA_REQ_TX_DAREADY + + + + + + + optional + false + + + + + + DMA_RX_REQ + + + + + + + TUSER + + + DMA_REQ_RX_DRTYPE + + + + + TVALID + + + DMA_REQ_RX_DRVALID + + + + + TLAST + + + DMA_REQ_RX_DRLAST + + + + + TREADY + + + DMA_REQ_RX_DRREADY + + + + + + + optional + false + + + + + + DMA_RX_ACK + + + + + + + TUSER + + + DMA_REQ_RX_DATYPE + + + + + TVALID + + + DMA_REQ_RX_DAVALID + + + + + TREADY + + + DMA_REQ_RX_DAREADY + + + + + + + optional + false + + + + + + DMA_TX_CLK + + + + + + + CLK + + + DMA_REQ_TX_ACLK + + + + + + ASSOCIATED_BUSIF + DMA_TX_REQ:DMA_TX_ACK + + + ASSOCIATED_RESET + DMA_REQ_TX_RSTN + + + + + + optional + false + + + + + + DMA_TX_RST + + + + + + + RST + + + DMA_REQ_TX_RSTN + + + + + + POLARITY + ACTIVE_LOW + + + + + + optional + false + + + + + + DMA_RX_CLK + + + + + + + CLK + + + DMA_REQ_RX_ACLK + + + + + + ASSOCIATED_BUSIF + DMA_RX_REQ:DMA_RX_ACK + + + ASSOCIATED_RESET + DMA_REQ_RX_RSTN + + + + + + optional + false + + + + + + DMA_RX_RST + + + + + + + RST + + + DMA_REQ_RX_RSTN + + + + + + POLARITY + ACTIVE_LOW + + + + + + optional + false + + + + + + + + S00_AXI + + S00_AXI_reg + 0 + 4096 + 32 + register + + + OFFSET_BASE_PARAM + C_S00_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S00_AXI_HIGHADDR + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axi_i2s_adi_v1_2 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + c5577600 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axi_i2s_adi_v1_2 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + c5577600 + + + + + xilinx_softwaredriver + Software Driver + :vivado.xilinx.com:sw.driver + + xilinx_softwaredriver_view_fileset + + + + viewChecksum + d0fc4f4c + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e9171d0c + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + DATA_CLK_I + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + BCLK_O + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + LRCLK_O + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + SDATA_O + + out + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + SDATA_I + + in + + 0 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + MUTEN_O + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TREADY + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TDATA + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TLAST + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + S_AXIS_TVALID + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TREADY + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TDATA + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TLAST + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TVALID + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + M_AXIS_TKEEP + + out + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_RSTN + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DAVALID + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DATYPE + + in + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DAREADY + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DRVALID + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DRTYPE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DRLAST + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_TX_DRREADY + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_ACLK + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_RSTN + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DAVALID + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DATYPE + + in + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DAREADY + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DRVALID + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DRTYPE + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DRLAST + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + DMA_REQ_RX_DRREADY + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awaddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_awready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_wready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_bready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_araddr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_arready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_rready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axi_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_S00_AXI_DATA_WIDTH + C S00 AXI DATA WIDTH + Width of S_AXI data bus + 32 + + + C_S00_AXI_ADDR_WIDTH + C S00 AXI ADDR WIDTH + Width of S_AXI address bus + 6 + + + C_SLOT_WIDTH + C Slot Width + 24 + + + C_LRCLK_POL + C Lrclk Pol + 0 + + + C_BCLK_POL + C Bclk Pol + 0 + + + C_DMA_TYPE + C Dma Type + 0 + + + C_NUM_CH + C Num Ch + 1 + + + C_HAS_TX + C Has Tx + 1 + + + C_HAS_RX + C Has Rx + 1 + + + + + + choices_0 + 32 + + + choices_1 + 1 + 0 + + + choices_2 + 0 + 1 + + + choices_3 + 0 + 1 + + + choices_4 + 0 + 1 + + + choices_5 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + + + choices_6 + 0 + 1 + + + choices_7 + 0 + 1 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axi_i2s_adi_v1_2.vhd + vhdlSource + CHECKSUM_c1ef5310 + + + hdl/i2s_rx.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/i2s_tx.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/i2s_clkgen.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/fifo_synchronizer.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/i2s_controller.vhd + vhdlSource + axi_i2s_adi_v1_00_a + + + hdl/adi_common/axi_ctrlif.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/adi_common/axi_streaming_dma_rx_fifo.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/adi_common/pl330_dma_fifo.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/adi_common/axi_streaming_dma_tx_fifo.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/adi_common/dma_fifo.vhd + vhdlSource + adi_common_v1_00_a + + + hdl/axi_i2s_adi_S_AXI.vhd + vhdlSource + CHECKSUM_8dec4efa + xil_defaultlib + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axi_i2s_adi_v1_2.vhd + vhdlSource + + + hdl/i2s_rx.vhd + vhdlSource + + + hdl/i2s_tx.vhd + vhdlSource + + + hdl/i2s_clkgen.vhd + vhdlSource + + + hdl/fifo_synchronizer.vhd + vhdlSource + + + hdl/i2s_controller.vhd + vhdlSource + + + hdl/adi_common/axi_ctrlif.vhd + vhdlSource + + + hdl/adi_common/axi_streaming_dma_rx_fifo.vhd + vhdlSource + + + hdl/adi_common/pl330_dma_fifo.vhd + vhdlSource + + + hdl/adi_common/axi_streaming_dma_tx_fifo.vhd + vhdlSource + + + hdl/adi_common/dma_fifo.vhd + vhdlSource + + + hdl/axi_i2s_adi_S_AXI.vhd + vhdlSource + + + + xilinx_softwaredriver_view_fileset + + drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.mdd + mdd + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl + tclSource + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/src/Makefile + unknown + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.h + cSource + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c + cSource + USED_IN_hw_handoff + + + drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c + cSource + USED_IN_hw_handoff + + + + xilinx_xpgui_view_fileset + + xgui/axi_i2s_adi_v1_2.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_70145134 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + Sends and receives audio data to/from an ADI I2S audio codec + + + C_S00_AXI_BASEADDR + AXI BASEADDR + 0xFFFFFFFF + + + + false + + + + + + C_S00_AXI_HIGHADDR + AXI HIGHADDR + 0x00000000 + + + + false + + + + + + Component_Name + axi_i2s_adi_v1_2 + + + C_LRCLK_POL + LRCLK Polarity + 0 + + + C_BCLK_POL + BCLK Polarity + 0 + + + C_DMA_TYPE + DMA Type + 0 + + + C_HAS_TX + Enable Audio Output + 1 + + + C_HAS_RX + Enable Audio Input + 1 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + AXI_Peripheral + + AXI I2S Audio + Digilent + http://www.digilentinc.com + 1 + + natinst.com:user:axi_i2s_adi:1.2 + + 2015-03-05T05:38:11Z + + C:/sam_work/Vivado_projects/14_4/ip_repo/axi_i2s_adi_1.2 + C:/sam_work/Vivado_projects/14_4/ip_repo/axi_i2s_adi_1.2 + + + + 2014.4 + + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl new file mode 100644 index 0000000..25ef87e --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/data/axi_i2s_adi.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "axi_i2s_adi" "NUM_INSTANCES" "DEVICE_ID" "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR" +} diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c new file mode 100644 index 0000000..f950fdd --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.c @@ -0,0 +1,6 @@ + + +/***************************** Include Files *******************************/ +#include "axi_i2s_adi.h" + +/************************** Function Definitions ***************************/ diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.h b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.h new file mode 100644 index 0000000..d13f29d --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi.h @@ -0,0 +1,87 @@ + +#ifndef AXI_I2S_ADI_H +#define AXI_I2S_ADI_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define AXI_I2S_ADI_S00_AXI_SLV_REG0_OFFSET 0 +#define AXI_I2S_ADI_S00_AXI_SLV_REG1_OFFSET 4 +#define AXI_I2S_ADI_S00_AXI_SLV_REG2_OFFSET 8 +#define AXI_I2S_ADI_S00_AXI_SLV_REG3_OFFSET 12 +#define AXI_I2S_ADI_S00_AXI_SLV_REG4_OFFSET 16 +#define AXI_I2S_ADI_S00_AXI_SLV_REG5_OFFSET 20 +#define AXI_I2S_ADI_S00_AXI_SLV_REG6_OFFSET 24 +#define AXI_I2S_ADI_S00_AXI_SLV_REG7_OFFSET 28 +#define AXI_I2S_ADI_S00_AXI_SLV_REG8_OFFSET 32 +#define AXI_I2S_ADI_S00_AXI_SLV_REG9_OFFSET 36 +#define AXI_I2S_ADI_S00_AXI_SLV_REG10_OFFSET 40 +#define AXI_I2S_ADI_S00_AXI_SLV_REG11_OFFSET 44 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a AXI_I2S_ADI register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the AXI_I2S_ADIdevice. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void AXI_I2S_ADI_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define AXI_I2S_ADI_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a AXI_I2S_ADI register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the AXI_I2S_ADI device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 AXI_I2S_ADI_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define AXI_I2S_ADI_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the AXI_I2S_ADI instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus AXI_I2S_ADI_Reg_SelfTest(void * baseaddr_p); + +#endif // AXI_I2S_ADI_H diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c new file mode 100644 index 0000000..3fe1e5a --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/drivers/axi_i2s_adi_v1_0/src/axi_i2s_adi_selftest.c @@ -0,0 +1,60 @@ + +/***************************** Include Files *******************************/ +#include "axi_i2s_adi.h" +#include "xparameters.h" +#include "stdio.h" +#include "xil_io.h" + +/************************** Constant Definitions ***************************/ +#define READ_WRITE_MUL_FACTOR 0x10 + +/************************** Function Definitions ***************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the AXI_I2S_ADIinstance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus AXI_I2S_ADI_Reg_SelfTest(void * baseaddr_p) +{ + u32 baseaddr; + int write_loop_index; + int read_loop_index; + int Index; + + baseaddr = (u32) baseaddr_p; + + xil_printf("******************************\n\r"); + xil_printf("* User Peripheral Self Test\n\r"); + xil_printf("******************************\n\n\r"); + + /* + * Write to user logic slave module register(s) and read back + */ + xil_printf("User logic slave module test...\n\r"); + + for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) + AXI_I2S_ADI_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); + for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) + if ( AXI_I2S_ADI_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ + xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); + return XST_FAILURE; + } + + xil_printf(" - slave register write/read passed\n\n\r"); + + return XST_SUCCESS; +} diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/axi_i2s_adi_v1_2_tb.v b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/axi_i2s_adi_v1_2_tb.v new file mode 100644 index 0000000..34f4457 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/axi_i2s_adi_v1_2_tb.v @@ -0,0 +1,184 @@ + +`timescale 1 ns / 1 ps + +`include "axi_i2s_adi_v1_2_tb_include.vh" + +// lite_response Type Defines +`define RESPONSE_OKAY 2'b00 +`define RESPONSE_EXOKAY 2'b01 +`define RESP_BUS_WIDTH 2 +`define BURST_TYPE_INCR 2'b01 +`define BURST_TYPE_WRAP 2'b10 + +// AMBA AXI4 Lite Range Constants +`define S00_AXI_MAX_BURST_LENGTH 1 +`define S00_AXI_DATA_BUS_WIDTH 32 +`define S00_AXI_ADDRESS_BUS_WIDTH 32 +`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8 + +module axi_i2s_adi_v1_2_tb; + reg tb_ACLK; + reg tb_ARESETn; + + // Create an instance of the example tb + `BD_WRAPPER dut (.ACLK(tb_ACLK), + .ARESETN(tb_ARESETn)); + + // Local Variables + + // AMBA S00_AXI AXI4 Lite Local Reg + reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite; + reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0]; + reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response; + reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress; + reg [3-1:0] S00_AXI_mtestProtection_lite; + integer S00_AXI_mtestvectorlite; // Master side testvector + integer S00_AXI_mtestdatasizelite; + integer result_slave_lite; + + + // Simple Reset Generator and test + initial begin + tb_ARESETn = 1'b0; + #500; + // Release the reset on the posedge of the clk. + @(posedge tb_ACLK); + tb_ARESETn = 1'b1; + @(posedge tb_ACLK); + end + + // Simple Clock Generator + initial tb_ACLK = 1'b0; + always #10 tb_ACLK = !tb_ACLK; + + //------------------------------------------------------------------------ + // TEST LEVEL API: CHECK_RESPONSE_OKAY + //------------------------------------------------------------------------ + // Description: + // CHECK_RESPONSE_OKAY(lite_response) + // This task checks if the return lite_response is equal to OKAY + //------------------------------------------------------------------------ + task automatic CHECK_RESPONSE_OKAY; + input [`RESP_BUS_WIDTH-1:0] response; + begin + if (response !== `RESPONSE_OKAY) begin + $display("TESTBENCH ERROR! lite_response is not OKAY", + "\n expected = 0x%h",`RESPONSE_OKAY, + "\n actual = 0x%h",response); + $stop; + end + end + endtask + + //------------------------------------------------------------------------ + // TEST LEVEL API: COMPARE_LITE_DATA + //------------------------------------------------------------------------ + // Description: + // COMPARE_LITE_DATA(expected,actual) + // This task checks if the actual data is equal to the expected data. + // X is used as don't care but it is not permitted for the full vector + // to be don't care. + //------------------------------------------------------------------------ + task automatic COMPARE_LITE_DATA; + input expected; + input actual; + begin + if (expected === 'hx || actual === 'hx) begin + $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); + result_slave_lite = 0; + $stop; + end + + if (actual != expected) begin + $display("TESTBENCH ERROR! Data expected is not equal to actual.", + "\nexpected = 0x%h",expected, + "\nactual = 0x%h",actual); + result_slave_lite = 0; + $stop; + end + else + begin + $display("TESTBENCH Passed! Data expected is equal to actual.", + "\n expected = 0x%h",expected, + "\n actual = 0x%h",actual); + end + end + endtask + + task automatic S00_AXI_TEST; + begin + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST : S00_AXI"); + $display("Simple register write and read example"); + $display("---------------------------------------------------------"); + + S00_AXI_mtestvectorlite = 0; + S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS; + S00_AXI_mtestProtection_lite = 0; + S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE; + + result_slave_lite = 1; + + for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1) + begin + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress, + S00_AXI_mtestProtection_lite, + S00_AXI_test_data_lite[S00_AXI_mtestvectorlite], + S00_AXI_mtestdatasizelite, + S00_AXI_lite_response); + $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response); + CHECK_RESPONSE_OKAY(S00_AXI_lite_response); + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress, + S00_AXI_mtestProtection_lite, + S00_AXI_rd_data_lite, + S00_AXI_lite_response); + $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response); + CHECK_RESPONSE_OKAY(S00_AXI_lite_response); + COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite); + $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite); + S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004; + end + + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!"); + if ( result_slave_lite ) begin + $display("PTGEN_TEST: PASSED!"); + end else begin + $display("PTGEN_TEST: FAILED!"); + end + $display("---------------------------------------------------------"); + end + endtask + + // Create the test vectors + initial begin + // When performing debug enable all levels of INFO messages. + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1); + + // Create test data vectors + S00_AXI_test_data_lite[0] = 32'h0101FFFF; + S00_AXI_test_data_lite[1] = 32'habcd0001; + S00_AXI_test_data_lite[2] = 32'hdead0011; + S00_AXI_test_data_lite[3] = 32'hbeef0011; + end + + // Drive the BFM + initial begin + // Wait for end of reset + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + S00_AXI_TEST(); + + end + +endmodule diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/design.tcl b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/design.tcl new file mode 100644 index 0000000..28acdfc --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/bfm_design/design.tcl @@ -0,0 +1,91 @@ +proc create_ipi_design { offsetfile design_name } { + create_bd_design $design_name + open_bd_design $design_name + + # Create Clock and Reset Ports + set ACLK [ create_bd_port -dir I -type clk ACLK ] + set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK + set ARESETN [ create_bd_port -dir I -type rst ARESETN ] + set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN + set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK + + # Create instance: axi_i2s_adi_0, and set properties + set axi_i2s_adi_0 [ create_bd_cell -type ip -vlnv natinst.com:user:axi_i2s_adi:1.2 axi_i2s_adi_0] + + # Create instance: master_0, and set properties + set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0] + set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0 + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins axi_i2s_adi_0/S00_AXI] + + # Create port connections + connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins axi_i2s_adi_0/S00_AXI_ACLK] + connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins axi_i2s_adi_0/S00_AXI_ARESETN] + + # Auto assign address + assign_bd_address + + # Copy all address to interface_address.vh file + set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/axi_i2s_adi_v1_2_tb_include.vh" + set fp [open $offset_file "w"] + puts $fp "`ifndef axi_i2s_adi_v1_2_tb_include_vh_" + puts $fp "`define axi_i2s_adi_v1_2_tb_include_vh_\n" + puts $fp "//Configuration current bd names" + puts $fp "`define BD_INST_NAME ${design_name}_i" + puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" + puts $fp "//Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]] + set offset_hex [string replace $offset 0 1 "32'h"] + puts $fp "`define S00_AXI_SLAVE_ADDRESS ${offset_hex}" + + puts $fp "`endif" + close $fp +} + +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores natinst.com:user:axi_i2s_adi:1.2]]]] +set test_bench_file ${ip_path}/example_designs/bfm_design/axi_i2s_adi_v1_2_tb.v +set interface_address_vh_file "" + +# Set IP Repository and Update IP Catalogue +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "axi_i2s_adi_v1_2_bfm_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +create_ipi_design interface_address_vh_file ${design_name} +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +set_property SOURCE_SET sources_1 [get_filesets sim_1] +import_files -fileset sim_1 -norecurse -force $test_bench_file +remove_files -quiet -fileset sim_1 axi_i2s_adi_v1_2_tb_include.vh +import_files -fileset sim_1 -norecurse -force $interface_address_vh_file +set_property top axi_i2s_adi_v1_2_tb [get_filesets sim_1] +set_property top_lib {} [get_filesets sim_1] +set_property top_file {} [get_filesets sim_1] +launch_xsim -simset sim_1 -mode behavioral +restart +run 1000 us diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/axi_i2s_adi_v1_2_hw_test.tcl b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/axi_i2s_adi_v1_2_hw_test.tcl new file mode 100644 index 0000000..21eba43 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/axi_i2s_adi_v1_2_hw_test.tcl @@ -0,0 +1,45 @@ +# Runtime Tcl commands to interact with - axi_i2s_adi_v1_2 + +# Sourcing design address info tcl +set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd +source ${bd_path}/axi_i2s_adi_v1_2_include.tcl + +# jtag axi master interface hardware name, change as per your design. +set jtag_axi_master hw_axi_1 +set ec 0 + +# hw test script +# Delete all previous axis transactions +if { [llength [get_hw_axi_txns -quiet]] } { + delete_hw_axi_txn [get_hw_axi_txns -quiet] +} + + +# Test all lite slaves. +set wdata_1 abcd1234 + +# Test: S00_AXI +# Create a write transaction at s00_axi_addr address +create_hw_axi_txn w_s00_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s00_axi_addr -data $wdata_1 +# Create a read transaction at s00_axi_addr address +create_hw_axi_txn r_s00_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s00_axi_addr +# Initiate transactions +run_hw_axi r_s00_axi_addr +run_hw_axi w_s00_axi_addr +run_hw_axi r_s00_axi_addr +set rdata_tmp [get_property DATA [get_hw_axi_txn r_s00_axi_addr]] +# Compare read data +if { $rdata_tmp == $wdata_1 } { + puts "Data comparison test pass for - S00_AXI" +} else { + puts "Data comparison test fail for - S00_AXI, expected-$wdata_1 actual-$rdata_tmp" + inc ec +} + +# Check error flag +if { $ec == 0 } { + puts "PTGEN_TEST: PASSED!" +} else { + puts "PTGEN_TEST: FAILED!" +} + diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/design.tcl b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/design.tcl new file mode 100644 index 0000000..254844c --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/example_designs/debug_hw_design/design.tcl @@ -0,0 +1,175 @@ + +proc create_ipi_design { offsetfile design_name } { + + create_bd_design $design_name + open_bd_design $design_name + + # Create and configure Clock/Reset + create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 + create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 + + #check if current_board is set, if true - figure out required clocks. + set is_board_clock_found 0 + set is_board_reset_found 0 + set external_reset_port "" + set external_clock_port "" + + if { [current_board_part -quiet] != "" } { + + #check if any reset interface exists in board. + set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ] + if { $board_reset ne "" } { + set is_board_reset_found 1 + apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design] + apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design] + set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]] + if { $external_rst ne "" } { + set external_reset_port [get_property NAME $external_rst] + } + } else { + send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually." + } + + # check for differential clock, exclude any special clocks which has TYPE property. + set board_clock_busifs "" + foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] { + set type [get_property PARAM.TYPE $busif] + if { $type == "" } { + set board_clock_busifs $busif + break + } + } + if { $board_clock_busifs ne "" } { + apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design] + set is_board_clock_found 1 + } else { + # check for single ended clock + set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ] + if { $board_sclock_busifs ne "" } { + apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design] + set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]] + if { $external_clk ne "" } { + set external_clock_port [get_property NAME $external_clk] + } + set is_board_clock_found 1 + } else { + send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually." + } + } + + } else { + send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually." + } + + #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning. + if { $is_board_reset_found == 0 } { + create_bd_port -dir I -type rst reset_rtl + set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] + set external_reset_port reset_rtl + } + if { $is_board_clock_found == 0 } { + create_bd_port -dir I -type clk clock_rtl + connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] + set external_clock_port clock_rtl + } + + #Avoid IPI DRC, make clock port synchronous to reset + if { $external_clock_port ne "" && $external_reset_port ne "" } { + set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] + } + + # Connect other sys_reset pins + connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] + + # Create instance: axi_i2s_adi_0, and set properties + set axi_i2s_adi_0 [ create_bd_cell -type ip -vlnv natinst.com:user:axi_i2s_adi:1.2 axi_i2s_adi_0 ] + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] + set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] + connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Create instance: axi_peri_interconnect, and set properties + set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] + connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] + set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] + + set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Connect all clock & reset of axi_i2s_adi_0 slave interfaces.. + connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins axi_i2s_adi_0/S00_AXI] + connect_bd_net [get_bd_pins axi_i2s_adi_0/s00_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_i2s_adi_0/s00_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + + # Auto assign address + assign_bd_address + + # Copy all address to axi_i2s_adi_v1_2_include.tcl file + set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/axi_i2s_adi_v1_2_include.tcl" + set fp [open $offset_file "w"] + puts $fp "# Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_i2s_adi_0_S00_AXI_* ]] + puts $fp "set s00_axi_addr ${offset}" + + close $fp +} + +# Set IP Repository and Update IP Catalogue +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores natinst.com:user:axi_i2s_adi:1.2]]]] +set hw_test_file ${ip_path}/example_designs/debug_hw_design/axi_i2s_adi_v1_2_hw_test.tcl + +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "axi_i2s_adi_v1_2_hw_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +set intf_address_include_file "" +create_ipi_design intf_address_include_file ${design_name} +save_bd_design +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +puts "-------------------------------------------------------------------------------------------------" +puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " +puts " please perform following steps to test design in targeted board." +puts "1. Generate bitstream" +puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" +puts "3. Download generated bitstream" +puts "4. Run generated hardware test using below command, this invokes basic read/write operation" +puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" +puts " : source -notrace ${hw_test_file}" +puts "-------------------------------------------------------------------------------------------------" + diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_ctrlif.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_ctrlif.vhd new file mode 100644 index 0000000..972b2c2 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_ctrlif.vhd @@ -0,0 +1,151 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_ctrlif is + generic + ( + C_NUM_REG : integer := 32; + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 32; + C_FAMILY : string := "virtex6" + ); + port + ( + -- AXI bus interface + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_RREADY : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_AWREADY : out std_logic; + + rd_addr : out integer range 0 to C_NUM_REG - 1; + rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + rd_ack : out std_logic; + rd_stb : in std_logic; + + wr_addr : out integer range 0 to C_NUM_REG - 1; + wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + wr_ack : in std_logic; + wr_stb : out std_logic + ); +end entity axi_ctrlif; + + +architecture Behavioral of axi_ctrlif is + type state_type is (IDLE, RESP, ACK); + signal rd_state : state_type; + signal wr_state : state_type; +begin + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + rd_state <= IDLE; + else + case rd_state is + when IDLE => + if S_AXI_ARVALID = '1' then + rd_state <= RESP; + rd_addr <= to_integer(unsigned(S_AXI_ARADDR(31 downto 2))); + end if; + when RESP => + if rd_stb = '1' and S_AXI_RREADY = '1' then + rd_state <= IDLE; + end if; + when others => null; + end case; + end if; + end if; + end process; + + S_AXI_ARREADY <= '1' when rd_state = IDLE else '0'; + S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0'; + S_AXI_RRESP <= "00"; + rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0'; + S_AXI_RDATA <= rd_data; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + wr_state <= IDLE; + else + case wr_state is + when IDLE => + if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then + wr_state <= ACK; + end if; + when ACK => + wr_state <= RESP; + when RESP => + if S_AXI_BREADY = '1' then + wr_state <= IDLE; + end if; + end case; + end if; + end if; + end process; + + wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0'; + wr_data <= S_AXI_WDATA; + wr_addr <= to_integer(unsigned(S_AXI_AWADDR(31 downto 2))); + + S_AXI_AWREADY <= '1' when wr_state = ACK else '0'; + S_AXI_WREADY <= '1' when wr_state = ACK else '0'; + + S_AXI_BRESP <= "00"; + S_AXI_BVALID <= '1' when wr_state = RESP else '0'; +end; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_rx_fifo.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_rx_fifo.vhd new file mode 100644 index 0000000..99154a2 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_rx_fifo.vhd @@ -0,0 +1,80 @@ +library ieee; +use ieee.std_logic_1164.all; + +library adi_common_v1_00_a; +use adi_common_v1_00_a.dma_fifo; + +entity axi_streaming_dma_rx_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + period_len : in integer range 0 to 65535; + + -- Read port + M_AXIS_ACLK : in std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TDATA : out std_logic_vector(FIFO_DWIDTH-1 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of axi_streaming_dma_rx_fifo is + signal out_stb : std_logic; + + signal period_count : integer range 0 to 65535; + signal last : std_logic; +begin + + M_AXIS_TVALID <= out_stb; + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => in_stb, + in_ack => in_ack, + in_data => in_data, + out_stb => out_stb, + out_ack => M_AXIS_TREADY, + out_data => M_AXIS_TDATA + ); + + M_AXIS_TKEEP <= "1111"; + M_AXIS_TLAST <= '1' when period_count = 0 else '0'; + + period_counter: process(M_AXIS_ACLK) is + begin + if resetn = '0' then + period_count <= period_len; + else + if out_stb = '1' and M_AXIS_TREADY = '1' then + if period_count = 0 then + period_count <= period_len; + else + period_count <= period_count - 1; + end if; + end if; + end if; + end process; +end; \ No newline at end of file diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd new file mode 100644 index 0000000..5d50208 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/axi_streaming_dma_tx_fifo.vhd @@ -0,0 +1,74 @@ +library ieee; +use ieee.std_logic_1164.all; + +library adi_common_v1_00_a; +use adi_common_v1_00_a.dma_fifo; + +entity axi_streaming_dma_tx_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + -- Write port + S_AXIS_ACLK : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TDATA : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TVALID : in std_logic; + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of axi_streaming_dma_tx_fifo is + signal in_ack : std_logic; + signal drain_dma : Boolean; +begin + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => S_AXIS_TVALID, + in_ack => in_ack, + in_data => S_AXIS_TDATA, + out_stb => out_stb, + out_ack => out_ack, + out_data => out_data + ); + + drain_process: process (S_AXIS_ACLK) is + variable enable_d1 : Boolean; + begin + if rising_edge(S_AXIS_ACLK) then + if resetn = '0' then + drain_dma <= False; + else + if S_AXIS_TLAST = '1' then + drain_dma <= False; + elsif enable_d1 and enable then + drain_dma <= True; + end if; + enable_d1 := enable; + end if; + end if; + end process; + + S_AXIS_TREADY <= '1' when in_ack = '1' or drain_dma else '0'; +end; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/dma_fifo.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/dma_fifo.vhd new file mode 100644 index 0000000..5339d73 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/dma_fifo.vhd @@ -0,0 +1,69 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dma_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of dma_fifo is + + constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1; + type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0); + signal data_fifo : MEM; + signal wr_addr : natural range 0 to FIFO_MAX; + signal rd_addr : natural range 0 to FIFO_MAX; + signal full, empty : Boolean; + +begin + in_ack <= '0' when full else '1'; + + out_stb <= '0' when empty else '1'; + out_data <= data_fifo(rd_addr); + + fifo: process (clk) is + variable free_cnt : integer range 0 to FIFO_MAX + 1; + begin + if rising_edge(clk) then + if (resetn = '0') or (fifo_reset = '1') then + wr_addr <= 0; + rd_addr <= 0; + free_cnt := FIFO_MAX + 1; + empty <= True; + full <= False; + else + if in_stb = '1' and not full then + data_fifo(wr_addr) <= in_data; + wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1); + free_cnt := free_cnt - 1; + end if; + + if out_ack = '1' and not empty then + rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1); + free_cnt := free_cnt + 1; + end if; + + full <= free_cnt = 0; + empty <= free_cnt = FIFO_MAX + 1; + end if; + end if; + end process; +end; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/pl330_dma_fifo.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/pl330_dma_fifo.vhd new file mode 100644 index 0000000..2e53bbc --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/adi_common/pl330_dma_fifo.vhd @@ -0,0 +1,140 @@ +library ieee; +use ieee.std_logic_1164.all; + +library adi_common_v1_00_a; +use adi_common_v1_00_a.dma_fifo; + +entity pl330_dma_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32; + FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- PL330 DMA interface + dclk : in std_logic; + dresetn : in std_logic; + davalid : in std_logic; + daready : out std_logic; + datype : in std_logic_vector(1 downto 0); + drvalid : out std_logic; + drready : in std_logic; + drtype : out std_logic_vector(1 downto 0); + drlast : out std_logic; + + DBG : out std_logic_vector(7 downto 0) + ); +end; + +architecture imp of pl330_dma_fifo is + signal request_data : Boolean; + + type state_type is (IDLE, REQUEST, WAITING, FLUSH); + signal state : state_type; + signal i_in_ack : std_logic; + signal i_out_stb : std_logic; +begin + + in_ack <= i_in_ack; + out_stb <= i_out_stb; + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => in_stb, + in_ack => i_in_ack, + in_data => in_data, + out_stb => i_out_stb, + out_ack => out_ack, + out_data => out_data + ); + + request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1'; + + drlast <= '0'; + daready <= '1'; + + drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0'; + drtype <= "00" when state = REQUEST else "10"; + + DBG(0) <= davalid; + DBG(2 downto 1) <= datype; + DBG(3) <= '1' when request_data else '0'; + + process (state) + begin + case state is + when IDLE => DBG(5 downto 4) <= "00"; + when REQUEST => DBG(5 downto 4) <= "01"; + when WAITING => DBG(5 downto 4) <= "10"; + when FLUSH => DBG(5 downto 4) <= "11"; + end case; + end process; + + pl330_req_fsm: process (dclk) is + begin + if rising_edge(dclk) then + if dresetn = '0' then + state <= IDLE; + else + -- The controller may send a FLUSH request at any time and it won't + -- respond to any of our requests until we've ack the FLUSH request. + -- The FLUSH request is also supposed to reset our state machine, so + -- go back to idle after having acked the FLUSH. + if davalid = '1' and datype = "10" then + state <= FLUSH; + else + case state is + -- Nothing to do, wait for the fifo to run empty + when IDLE => + if request_data and enable then + state <= REQUEST; + end if; + -- Send out a request to the PL330 + when REQUEST => + if drready = '1' then + state <= WAITING; + end if; + -- Wait for a ACK from the PL330 that it did transfer the data + when WAITING => + if fifo_reset = '1' then + state <= IDLE; + elsif davalid = '1' then + if datype = "00" then + state <= IDLE; + end if; + end if; + -- Send out an ACK for the flush + when FLUSH => + if drready = '1' then + state <= IDLE; + end if; + end case; + end if; + end if; + end if; + end process; +end; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_S_AXI.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_S_AXI.vhd new file mode 100644 index 0000000..26c72ae --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_S_AXI.vhd @@ -0,0 +1,361 @@ +-------------------------------------------------------------------------------- +-- +-- File: +-- axi_i2s_adi_S_AXI.vhd +-- +-- Module: +-- AXIS I2S Controller AXI Slave Interface +-- +-- Author: +-- Tinghui Wang (Steve) +-- Sam Bobrowicz +-- +-- Description: +-- AXI-Lite Register Interface for AXI I2S Controller +-- +-- Copyright notice: +-- Copyright (C) 2014 Digilent Inc. +-- +-- License: +-- This program is free software; distributed under the terms of +-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License") +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- +-- 1. Redistributions of source code must retain the above copyright notice, this +-- list of conditions and the following disclaimer. +-- 2. Redistributions in binary form must reproduce the above copyright notice, +-- this list of conditions and the following disclaimer in the documentation +-- and/or other materials provided with the distribution. +-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names +-- of its contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE +-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED +-- OF THE POSSIBILITY OF SUCH DAMAGE. +-- +-------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity axi_i2s_adi_S_AXI is + generic ( + -- Users to add parameters here + + -- User parameters ends + -- Do not modify the parameters beyond this line + + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + rd_addr : out integer range 0 to 12 - 1; + rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + rd_ack : out std_logic; + + wr_addr : out integer range 0 to 12 - 1; + wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + wr_stb : out std_logic; + -- User ports ends + -- Do not modify the ports beyond this line + + -- Global Clock Signal + S_AXI_ACLK : in std_logic; + -- Global Reset Signal. This Signal is Active LOW + S_AXI_ARESETN : in std_logic; + -- Write address (issued by master, acceped by Slave) + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Write channel Protection type. This signal indicates the + -- privilege and security level of the transaction, and whether + -- the transaction is a data access or an instruction access. + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + -- Write address valid. This signal indicates that the master signaling + -- valid write address and control information. + S_AXI_AWVALID : in std_logic; + -- Write address ready. This signal indicates that the slave is ready + -- to accept an address and associated control signals. + S_AXI_AWREADY : out std_logic; + -- Write data (issued by master, acceped by Slave) + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Write strobes. This signal indicates which byte lanes hold + -- valid data. There is one write strobe bit for each eight + -- bits of the write data bus. + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + -- Write valid. This signal indicates that valid write + -- data and strobes are available. + S_AXI_WVALID : in std_logic; + -- Write ready. This signal indicates that the slave + -- can accept the write data. + S_AXI_WREADY : out std_logic; + -- Write response. This signal indicates the status + -- of the write transaction. + S_AXI_BRESP : out std_logic_vector(1 downto 0); + -- Write response valid. This signal indicates that the channel + -- is signaling a valid write response. + S_AXI_BVALID : out std_logic; + -- Response ready. This signal indicates that the master + -- can accept a write response. + S_AXI_BREADY : in std_logic; + -- Read address (issued by master, acceped by Slave) + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Protection type. This signal indicates the privilege + -- and security level of the transaction, and whether the + -- transaction is a data access or an instruction access. + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + -- Read address valid. This signal indicates that the channel + -- is signaling valid read address and control information. + S_AXI_ARVALID : in std_logic; + -- Read address ready. This signal indicates that the slave is + -- ready to accept an address and associated control signals. + S_AXI_ARREADY : out std_logic; + -- Read data (issued by slave) + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Read response. This signal indicates the status of the + -- read transfer. + S_AXI_RRESP : out std_logic_vector(1 downto 0); + -- Read valid. This signal indicates that the channel is + -- signaling the required read data. + S_AXI_RVALID : out std_logic; + -- Read ready. This signal indicates that the master can + -- accept the read data and response information. + S_AXI_RREADY : in std_logic + ); +end axi_i2s_adi_S_AXI; + +architecture arch_imp of axi_i2s_adi_S_AXI is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 3; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + wr_data <= S_AXI_WDATA; + wr_addr <= to_integer(unsigned(axi_awaddr((C_S_AXI_ADDR_WIDTH - 1) downto 2))); + wr_stb <= slv_reg_wren; + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + rd_ack <= slv_reg_rden; + reg_data_out <= rd_data; + rd_addr <= to_integer(unsigned(axi_araddr((C_S_AXI_ADDR_WIDTH - 1) downto 2))); + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + + -- Add user logic here + + + -- User logic ends + +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_v1_2.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_v1_2.vhd new file mode 100644 index 0000000..83c3f39 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/axi_i2s_adi_v1_2.vhd @@ -0,0 +1,469 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library axi_i2s_adi_v1_00_a; +use axi_i2s_adi_v1_00_a.i2s_controller; + +library adi_common_v1_00_a; +use adi_common_v1_00_a.axi_streaming_dma_rx_fifo; +use adi_common_v1_00_a.axi_streaming_dma_tx_fifo; +use adi_common_v1_00_a.pl330_dma_fifo; +use adi_common_v1_00_a.axi_ctrlif; + + +entity axi_i2s_adi_v1_2 is + generic ( + -- Users to add parameters here + C_SLOT_WIDTH : integer := 24; + C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_DMA_TYPE : integer := 0; + C_NUM_CH : integer := 1; + C_HAS_TX : integer := 1; + C_HAS_RX : integer := 1; + -- User parameters ends + -- Do not modify the parameters beyond this line + + + -- Parameters of Axi Slave Bus Interface S00_AXI + C_S00_AXI_DATA_WIDTH : integer := 32; + C_S00_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + -- Users to add ports here + -- Serial Data interface + DATA_CLK_I : in std_logic; + BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); + LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); + SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); + SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); + MUTEN_O : out std_logic; + + -- AXI Streaming DMA TX interface + S_AXIS_ACLK : in std_logic; + S_AXIS_TREADY : out std_logic; + S_AXIS_TDATA : in std_logic_vector(31 downto 0); + S_AXIS_TLAST : in std_logic; + S_AXIS_TVALID : in std_logic; + + -- AXI Streaming DMA RX interface + M_AXIS_ACLK : in std_logic; + M_AXIS_TREADY : in std_logic; + M_AXIS_TDATA : out std_logic_vector(31 downto 0); + M_AXIS_TLAST : out std_logic; + M_AXIS_TVALID : out std_logic; + M_AXIS_TKEEP : out std_logic_vector(3 downto 0); + + --PL330 DMA TX interface + DMA_REQ_TX_ACLK : in std_logic; + DMA_REQ_TX_RSTN : in std_logic; + DMA_REQ_TX_DAVALID : in std_logic; + DMA_REQ_TX_DATYPE : in std_logic_vector(1 downto 0); + DMA_REQ_TX_DAREADY : out std_logic; + DMA_REQ_TX_DRVALID : out std_logic; + DMA_REQ_TX_DRTYPE : out std_logic_vector(1 downto 0); + DMA_REQ_TX_DRLAST : out std_logic; + DMA_REQ_TX_DRREADY : in std_logic; + + -- PL330 DMA RX interface + DMA_REQ_RX_ACLK : in std_logic; + DMA_REQ_RX_RSTN : in std_logic; + DMA_REQ_RX_DAVALID : in std_logic; + DMA_REQ_RX_DATYPE : in std_logic_vector(1 downto 0); + DMA_REQ_RX_DAREADY : out std_logic; + DMA_REQ_RX_DRVALID : out std_logic; + DMA_REQ_RX_DRTYPE : out std_logic_vector(1 downto 0); + DMA_REQ_RX_DRLAST : out std_logic; + DMA_REQ_RX_DRREADY : in std_logic; + -- User ports ends + -- Do not modify the ports beyond this line + + + -- Ports of Axi Slave Bus Interface S00_AXI + s00_axi_aclk : in std_logic; + s00_axi_aresetn : in std_logic; + s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_awprot : in std_logic_vector(2 downto 0); + s00_axi_awvalid : in std_logic; + s00_axi_awready : out std_logic; + s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0); + s00_axi_wvalid : in std_logic; + s00_axi_wready : out std_logic; + s00_axi_bresp : out std_logic_vector(1 downto 0); + s00_axi_bvalid : out std_logic; + s00_axi_bready : in std_logic; + s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0); + s00_axi_arprot : in std_logic_vector(2 downto 0); + s00_axi_arvalid : in std_logic; + s00_axi_arready : out std_logic; + s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0); + s00_axi_rresp : out std_logic_vector(1 downto 0); + s00_axi_rvalid : out std_logic; + s00_axi_rready : in std_logic + ); +end axi_i2s_adi_v1_2; + +architecture arch_imp of axi_i2s_adi_v1_2 is + + -- component declaration + component axi_i2s_adi_S_AXI is + generic ( + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 6 + ); + port ( + rd_addr : out integer range 0 to 12 - 1; + rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + rd_ack : out std_logic; + + wr_addr : out integer range 0 to 12 - 1; + wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + wr_stb : out std_logic; + S_AXI_ACLK : in std_logic; + S_AXI_ARESETN : in std_logic; + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + S_AXI_AWVALID : in std_logic; + S_AXI_AWREADY : out std_logic; + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + S_AXI_WVALID : in std_logic; + S_AXI_WREADY : out std_logic; + S_AXI_BRESP : out std_logic_vector(1 downto 0); + S_AXI_BVALID : out std_logic; + S_AXI_BREADY : in std_logic; + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + S_AXI_ARVALID : in std_logic; + S_AXI_ARREADY : out std_logic; + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + S_AXI_RRESP : out std_logic_vector(1 downto 0); + S_AXI_RVALID : out std_logic; + S_AXI_RREADY : in std_logic + ); + end component axi_i2s_adi_S_AXI; + + signal i2s_reset : std_logic; +signal tx_fifo_reset : std_logic; +signal tx_enable : Boolean; +signal tx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0); +signal tx_ack : std_logic; +signal tx_stb : std_logic; +signal tx_fifo_full : std_logic; +signal tx_fifo_empty : std_logic; +signal tx_in_ack : std_logic; + + +signal rx_enable : Boolean; +signal rx_fifo_reset : std_logic; +signal rx_data : std_logic_vector(C_SLOT_WIDTH - 1 downto 0); +signal rx_ack : std_logic; +signal rx_stb : std_logic; +signal rx_fifo_full : std_logic; +signal rx_fifo_empty : std_logic; +signal rx_out_stb : std_logic; + +signal bclk_div_rate : natural range 0 to 255; +signal lrclk_div_rate : natural range 0 to 255; + +signal period_len : integer range 0 to 65535; + +signal I2S_RESET_REG : std_logic_vector(31 downto 0); +signal I2S_CONTROL_REG : std_logic_vector(31 downto 0); +signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0); +signal PERIOD_LEN_REG : std_logic_vector(31 downto 0); + +constant FIFO_AWIDTH : integer := integer(ceil(log2(real(C_NUM_CH * 8)))); + +-- Audio samples FIFO +constant RAM_ADDR_WIDTH : integer := 7; +type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0); + +-- RX FIFO signals +signal audio_fifo_rx : RAM_TYPE; +signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1; +signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1; +signal tvalid : std_logic := '0'; +signal rx_tlast : std_logic; +signal drain_tx_dma : std_logic; + +signal rx_sample : std_logic_vector(23 downto 0); + +signal wr_data : std_logic_vector(31 downto 0); +signal rd_data : std_logic_vector(31 downto 0); +signal wr_addr : integer range 0 to 11; +signal rd_addr : integer range 0 to 11; +signal wr_stb : std_logic; +signal rd_ack : std_logic; +signal tx_fifo_stb : std_logic; +signal rx_fifo_ack : std_logic; +signal cnt : integer range 0 to 2**16-1; + +begin + +-- Instantiation of Axi Bus Interface S00_AXI +axi_i2s_adi_S_AXI_inst : axi_i2s_adi_S_AXI + generic map ( + C_S_AXI_DATA_WIDTH => C_S00_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S00_AXI_ADDR_WIDTH + ) + port map ( + rd_addr => rd_addr, + rd_data => rd_data, + rd_ack => rd_ack, + + wr_addr => wr_addr, + wr_data => wr_data, + wr_stb => wr_stb, + S_AXI_ACLK => s00_axi_aclk, + S_AXI_ARESETN => s00_axi_aresetn, + S_AXI_AWADDR => s00_axi_awaddr, + S_AXI_AWPROT => s00_axi_awprot, + S_AXI_AWVALID => s00_axi_awvalid, + S_AXI_AWREADY => s00_axi_awready, + S_AXI_WDATA => s00_axi_wdata, + S_AXI_WSTRB => s00_axi_wstrb, + S_AXI_WVALID => s00_axi_wvalid, + S_AXI_WREADY => s00_axi_wready, + S_AXI_BRESP => s00_axi_bresp, + S_AXI_BVALID => s00_axi_bvalid, + S_AXI_BREADY => s00_axi_bready, + S_AXI_ARADDR => s00_axi_araddr, + S_AXI_ARPROT => s00_axi_arprot, + S_AXI_ARVALID => s00_axi_arvalid, + S_AXI_ARREADY => s00_axi_arready, + S_AXI_RDATA => s00_axi_rdata, + S_AXI_RRESP => s00_axi_rresp, + S_AXI_RVALID => s00_axi_rvalid, + S_AXI_RREADY => s00_axi_rready + ); + + -- Add user logic here +process (s00_axi_aclk) + begin + if rising_edge(s00_axi_aclk) then + if s00_axi_aresetn = '0' then + cnt <= 0; + else + cnt <= (cnt + 1) mod 2**16; + end if; + end if; + end process; + + streaming_dma_tx_gen: if C_DMA_TYPE = 0 and C_HAS_TX = 1 generate + tx_fifo : entity axi_streaming_dma_tx_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24 + ) + port map( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + S_AXIS_ACLK => S_AXIS_ACLK, + S_AXIS_TREADY => S_AXIS_TREADY, + S_AXIS_TDATA => S_AXIS_TDATA(31 downto 8), + S_AXIS_TLAST => S_AXIS_TLAST, + S_AXIS_TVALID => S_AXIS_TVALID, + + out_stb => tx_stb, + out_ack => tx_ack, + out_data => tx_data + ); + end generate; + + streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate + rx_fifo : entity axi_streaming_dma_rx_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24 + ) + port map( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + period_len => period_len, + + in_stb => rx_stb, + in_ack => rx_ack, + in_data => rx_data, + + M_AXIS_ACLK => M_AXIS_ACLK, + M_AXIS_TREADY => M_AXIS_TREADY, + M_AXIS_TDATA => M_AXIS_TDATA(31 downto 8), + M_AXIS_TLAST => M_AXIS_TLAST, + M_AXIS_TVALID => M_AXIS_TVALID, + M_AXIS_TKEEP => M_AXIS_TKEEP + ); + + M_AXIS_TDATA(7 downto 0) <= (others => '0'); + end generate; + + pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate + tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0'; + + tx_fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24, + FIFO_DIRECTION => 0 + ) + port map ( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + in_data => wr_data(31 downto 8), + in_stb => tx_fifo_stb, + in_ack => tx_in_ack, + + out_ack => tx_ack, + out_stb => tx_stb, + out_data => tx_data, + + dclk => DMA_REQ_TX_ACLK, + dresetn => DMA_REQ_TX_RSTN, + davalid => DMA_REQ_TX_DAVALID, + daready => DMA_REQ_TX_DAREADY, + datype => DMA_REQ_TX_DATYPE, + drvalid => DMA_REQ_TX_DRVALID, + drready => DMA_REQ_TX_DRREADY, + drtype => DMA_REQ_TX_DRTYPE, + drlast => DMA_REQ_TX_DRLAST + ); + end generate; + + + pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate + rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0'; + + rx_fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24, + FIFO_DIRECTION => 1 + ) + port map ( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + fifo_reset => rx_fifo_reset, + enable => rx_enable, + + in_ack => rx_ack, + in_stb => rx_stb, + in_data => rx_data, + + out_data => rx_sample, + out_ack => rx_fifo_ack, + out_stb => rx_out_stb, + + dclk => DMA_REQ_RX_ACLK, + dresetn => DMA_REQ_RX_RSTN, + davalid => DMA_REQ_RX_DAVALID, + daready => DMA_REQ_RX_DAREADY, + datype => DMA_REQ_RX_DATYPE, + drvalid => DMA_REQ_RX_DRVALID, + drready => DMA_REQ_RX_DRREADY, + drtype => DMA_REQ_RX_DRTYPE, + drlast => DMA_REQ_RX_DRLAST + ); + end generate; + + ctrl : entity i2s_controller + generic map ( + C_SLOT_WIDTH => C_SLOT_WIDTH, + C_BCLK_POL => C_BCLK_POL, + C_LRCLK_POL => C_LRCLK_POL, + C_NUM_CH => C_NUM_CH, + C_HAS_TX => C_HAS_TX, + C_HAS_RX => C_HAS_RX + ) + port map ( + clk => s00_axi_aclk, + resetn => s00_axi_aresetn, + + data_clk => DATA_CLK_I, + BCLK_O => BCLK_O, + LRCLK_O => LRCLK_O, + SDATA_O => SDATA_O, + SDATA_I => SDATA_I, + + tx_enable => tx_enable, + tx_ack => tx_ack, + tx_stb => tx_stb, + tx_data => tx_data, + + rx_enable => rx_enable, + rx_ack => rx_ack, + rx_stb => rx_stb, + rx_data => rx_data, + + bclk_div_rate => bclk_div_rate, + lrclk_div_rate => lrclk_div_rate + ); + + + + tx_fifo_full <= not(tx_in_ack); + tx_fifo_empty <= not(tx_stb); + rx_fifo_full <= not(rx_ack); + rx_fifo_empty <= not(rx_out_stb); + i2s_reset <= I2S_RESET_REG(0); + tx_fifo_reset <= I2S_RESET_REG(1); + rx_fifo_reset <= I2S_RESET_REG(2); + tx_enable <= I2S_CONTROL_REG(0) = '1'; + rx_enable <= I2S_CONTROL_REG(1) = '1'; + MUTEN_O <= not(I2S_CONTROL_REG(2)); + bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0))); + lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16))); + period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0))); + + process(rd_addr) + begin + case rd_addr is + when 1 => rd_data <= I2S_CONTROL_REG and x"00000007"; + when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff"; + when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff"; + when 8 => rd_data <= x"0000000" & rx_fifo_full & rx_fifo_empty & tx_fifo_full & tx_fifo_empty; + when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8)); + when others => rd_data <= (others => '0'); + end case; + end process; + + process(s00_axi_aclk) is + begin + if rising_edge(s00_axi_aclk) then + if s00_axi_aresetn = '0' then + I2S_RESET_REG <= (others => '0'); + I2S_CONTROL_REG <= (others => '0'); + I2S_CLK_CONTROL_REG <= (others => '0'); + PERIOD_LEN_REG <= (others => '0'); + else + -- Auto-clear the Reset Register bits + I2S_RESET_REG(0) <= '0'; + I2S_RESET_REG(1) <= '0'; + I2S_RESET_REG(2) <= '0'; + if wr_stb = '1' then + case wr_addr is + when 0 => I2S_RESET_REG <= wr_data; + when 1 => I2S_CONTROL_REG <= wr_data; + when 2 => I2S_CLK_CONTROL_REG <= wr_data; + when 6 => PERIOD_LEN_REG <= wr_data; + when others => null; + end case; + end if; + end if; + end if; + end process; + -- User logic ends + +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/fifo_synchronizer.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/fifo_synchronizer.vhd new file mode 100644 index 0000000..0218f34 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/fifo_synchronizer.vhd @@ -0,0 +1,108 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_synchronizer is + generic ( + DEPTH : integer := 4; + WIDTH : integer := 2 + ); + port ( + resetn : in std_logic; + + in_clk : in std_logic; + in_data : in std_logic_vector(WIDTH - 1 downto 0); + in_tick : in std_logic; + + out_clk : in std_logic; + out_data : out std_logic_vector(WIDTH - 1 downto 0); + out_tick : out std_logic + ); + +end fifo_synchronizer; + +architecture impl of fifo_synchronizer is + type DATA_SYNC_FIFO_TYPE is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0); + signal fifo: DATA_SYNC_FIFO_TYPE; + + signal rd_addr : natural range 0 to DEPTH - 1; + signal wr_addr : natural range 0 to DEPTH - 1; + + signal tick : std_logic; + signal tick_d1 : std_logic; + signal tick_d2 : std_logic; +begin + + process (in_clk) + begin + if rising_edge(in_clk) then + if resetn = '0' then + wr_addr <= 0; + tick <= '0'; + else + if in_tick = '1' then + fifo(wr_addr) <= in_data; + wr_addr <= (wr_addr + 1) mod DEPTH; + tick <= not tick; + end if; + end if; + end if; + end process; + + process (out_clk) + begin + if rising_edge(out_clk) then + if resetn = '0' then + rd_addr <= 0; + tick_d1 <= '0'; + tick_d2 <= '0'; + else + tick_d1 <= tick; + tick_d2 <= tick_d1; + out_tick <= tick_d1 xor tick_d2; + if (tick_d1 xor tick_d2) = '1' then + rd_addr <= (rd_addr + 1) mod DEPTH; + out_data <= fifo(rd_addr); + end if; + end if; + end if; + end process; + +end; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_clkgen.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_clkgen.vhd new file mode 100644 index 0000000..874099a --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_clkgen.vhd @@ -0,0 +1,133 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity i2s_clkgen is + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + + enable : in Boolean ; -- Enable clockgen + + tick : in std_logic; + + bclk_div_rate : in natural range 0 to 255; + lrclk_div_rate : in natural range 0 to 255; + + bclk : out std_logic; -- Bit Clock + lrclk : out std_logic; -- Frame Clock + channel_sync : out std_logic; + frame_sync : out std_logic + ); +end i2s_clkgen; + +architecture Behavioral of i2s_clkgen is + signal reset_int : Boolean; + + signal prev_bclk_div_rate : natural range 0 to 255; + signal prev_lrclk_div_rate : natural range 0 to 255; + + signal bclk_count : natural range 0 to 255; + signal lrclk_count : natural range 0 to 255; + + signal bclk_int : std_logic; + signal lrclk_int : std_logic; + + signal lrclk_tick : Boolean; +begin + + reset_int <= resetn = '0' or not enable; + + bclk <= bclk_int; + lrclk <= lrclk_int; + +----------------------------------------------------------------------------------- +-- Serial clock generation BCLK_O +----------------------------------------------------------------------------------- + bclk_gen: process(clk) + begin + if rising_edge(clk) then + prev_bclk_div_rate <= bclk_div_rate; + if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then + bclk_int <= '1'; + bclk_count <= bclk_div_rate; + else + if tick = '1' then + if bclk_count = bclk_div_rate then + bclk_count <= 0; + bclk_int <= not bclk_int; + else + bclk_count <= bclk_count + 1; + end if; + end if; + end if; + end if; + end process bclk_gen; + + lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1'; + + channel_sync <= '1' when lrclk_count = 1 else '0'; + frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0'; + +----------------------------------------------------------------------------------- +-- Frame clock generator LRCLK_O +----------------------------------------------------------------------------------- + lrclk_gen: process(clk) + begin + if rising_edge(clk) then + prev_lrclk_div_rate <= lrclk_div_rate; + -- Reset + if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then + lrclk_int <= '1'; + lrclk_count <= lrclk_div_rate; + else + if lrclk_tick then + if lrclk_count = lrclk_div_rate then + lrclk_count <= 0; + lrclk_int <= not lrclk_int; + else + lrclk_count <= lrclk_count + 1; + end if; + end if; + end if; + end if; + end process lrclk_gen; + +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_controller.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_controller.vhd new file mode 100644 index 0000000..59bde04 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_controller.vhd @@ -0,0 +1,282 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +library axi_i2s_adi_v1_00_a; +use axi_i2s_adi_v1_00_a.fifo_synchronizer; +use axi_i2s_adi_v1_00_a.i2s_clkgen; +use axi_i2s_adi_v1_00_a.i2s_tx; +use axi_i2s_adi_v1_00_a.i2s_rx; + +entity i2s_controller is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_NUM_CH : integer := 1; + C_HAS_TX : integer := 1; + C_HAS_RX : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + + data_clk : in std_logic; -- Data clock should be less than clk / 4 + BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock + LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock + SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output + SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input + + tx_enable : in Boolean; -- Enable TX + tx_ack : out std_logic; -- Request new Slot Data + tx_stb : in std_logic; -- Request new Slot Data + tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in + + rx_enable : in Boolean; -- Enable RX + rx_ack : in std_logic; + rx_stb : out std_logic; -- Valid Slot Data + rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out + + -- Runtime parameter + bclk_div_rate : in natural range 0 to 255; + lrclk_div_rate : in natural range 0 to 255 + ); +end i2s_controller; + +architecture Behavioral of i2s_controller is +constant NUM_TX : integer := C_HAS_TX * C_NUM_CH; +constant NUM_RX : integer := C_HAS_RX * C_NUM_CH; + +signal enable : Boolean; + +signal tick : std_logic; +signal tick_d1 : std_logic; +signal tick_d2 : std_logic; + +signal BCLK_O_int : std_logic; +signal LRCLK_O_int : std_logic; + +signal tx_bclk : std_logic; +signal tx_lrclk : std_logic; +signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0); +signal tx_tick : std_logic; +signal tx_channel_sync : std_logic; +signal tx_frame_sync : std_logic; + +signal bclk_tick : std_logic; + +signal rx_bclk : std_logic; +signal rx_lrclk : std_logic; +signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0); +signal rx_channel_sync : std_logic; +signal rx_frame_sync : std_logic; + +signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0); +signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0); +signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0); +signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0); + +begin + enable <= rx_enable or tx_enable; + + -- Generate tick signal in the DATA_CLK_I domain + process (data_clk) + begin + if rising_edge(data_clk) then + if resetn = '0' then + tick <= '0'; + else + tick <= not tick; + end if; + end if; + end process; + + process (clk) + begin + if rising_edge(clk) then + if resetn = '0' then + tick_d1 <= '0'; + tick_d2 <= '0'; + else + tick_d1 <= tick; + tick_d2 <= tick_d1; + end if; + end if; + end process; + + tx_tick <= tick_d2 xor tick_d1; + + tx_sync_fifo_in(0) <= tx_channel_sync; + tx_sync_fifo_in(1) <= tx_frame_sync; + tx_sync_fifo_in(2) <= tx_bclk; + tx_sync_fifo_in(3) <= tx_lrclk; + tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata; + + process (data_clk) + begin + if rising_edge(data_clk) then + if resetn = '0' then + BCLK_O <= (others => '1'); + LRCLK_O <= (others => '1'); + SDATA_O <= (others => '0'); + else + if C_BCLK_POL = 0 then + BCLK_O <= (others => tx_sync_fifo_out(2)); + else + BCLK_O <= (others => not tx_sync_fifo_out(2)); + end if; + + if C_LRCLK_POL = 0 then + LRCLK_O <= (others => tx_sync_fifo_out(3)); + else + LRCLK_O <= (others => not tx_sync_fifo_out(3)); + end if; + + if C_HAS_TX = 1 then + SDATA_O <= tx_sync_fifo_out(3 + NUM_TX downto 4); + end if; + + if C_HAS_RX = 1 then + rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0); + rx_sync_fifo_in(3 + NUM_RX downto 4) <= SDATA_I; + end if; + end if; + end if; + end process; + + tx_sync: entity fifo_synchronizer + generic map ( + DEPTH => 4, + WIDTH => NUM_TX + 4 + ) + port map ( + resetn => resetn, + in_clk => clk, + in_data => tx_sync_fifo_in, + in_tick => tx_tick, + + out_clk => data_clk, + out_data => tx_sync_fifo_out + ); + + clkgen: entity i2s_clkgen + port map( + clk => clk, + resetn => resetn, + enable => enable, + tick => tx_tick, + + bclk_div_rate => bclk_div_rate, + lrclk_div_rate => lrclk_div_rate, + + channel_sync => tx_channel_sync, + frame_sync => tx_frame_sync, + + bclk => tx_bclk, + lrclk => tx_lrclk + ); + + tx_gen: if C_HAS_TX = 1 generate + tx: entity i2s_tx + generic map ( + C_SLOT_WIDTH => C_SLOT_WIDTH, + C_NUM => NUM_TX + ) + port map ( + clk => clk, + resetn => resetn, + enable => tx_enable, + + channel_sync => tx_channel_sync, + frame_sync => tx_frame_sync, + bclk => tx_bclk, + sdata => tx_sdata, + + ack => tx_ack, + stb => tx_stb, + data => tx_data + ); + end generate; + + rx_gen: if C_HAS_RX = 1 generate + rx: entity i2s_rx + generic map ( + C_SLOT_WIDTH => C_SLOT_WIDTH, + C_NUM => NUM_RX + ) + port map ( + clk => clk, + resetn => resetn, + enable => rx_enable, + + channel_sync => rx_channel_sync, + frame_sync => rx_frame_sync, + bclk => rx_bclk, + sdata => rx_sdata, + + ack => rx_ack, + stb => rx_stb, + data => rx_data + ); + + rx_channel_sync <= rx_sync_fifo_out(0); + rx_frame_sync <= rx_sync_fifo_out(1); + rx_bclk <= rx_sync_fifo_out(2); + rx_lrclk <= rx_sync_fifo_out(3); + rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4); + + rx_sync: entity fifo_synchronizer + generic map ( + DEPTH => 4, + WIDTH => NUM_RX + 4 + ) + port map ( + resetn => resetn, + in_clk => data_clk, + in_data => rx_sync_fifo_in, + in_tick => '1', + + out_clk => clk, + out_data => rx_sync_fifo_out + ); + + end generate; + +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_rx.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_rx.vhd new file mode 100644 index 0000000..aa4e584 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_rx.vhd @@ -0,0 +1,180 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2s_rx is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_NUM : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + enable : in Boolean; -- Enable RX + + bclk : in std_logic; -- Bit Clock + channel_sync : in std_logic; -- Channel Sync + frame_sync : in std_logic; -- Frame Sync + sdata : in std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output + + stb : out std_logic; -- Data available + ack : in std_logic; -- Data has been consumed + data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in + ); +end i2s_rx; + +architecture Behavioral of i2s_rx is + type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0); + type mem_latched is array (0 to C_NUM - 1) of std_logic_vector(C_SLOT_WIDTH - 1 downto 0); + signal data_int : mem; + signal data_latched : mem_latched; + signal reset_int : Boolean; + signal enable_int : Boolean; + + signal bit_sync : std_logic; + signal channel_sync_int : std_logic; + signal frame_sync_int : std_logic; + + signal bclk_d1 : std_logic; + + type sequencer_state_type is (IDLE, ACTIVE); + signal sequencer_state : sequencer_state_type; + signal seq : natural range 0 to C_NUM - 1; + + signal ovf_frame_cnt : natural range 0 to 1; +begin + + reset_int <= (resetn = '0') or not enable; + + process (clk) + begin + if rising_edge(clk) then + if resetn = '0' then + bclk_d1 <= '0'; + else + bclk_d1 <= bclk; + end if; + end if; + end process; + + bit_sync <= (bclk xor bclk_d1) and bclk; + channel_sync_int <= channel_sync and bit_sync; + frame_sync_int <= frame_sync and bit_sync; + + stb <= '1' when sequencer_state = ACTIVE else '0'; + + sequencer: process (clk) + begin + if rising_edge(clk) then + if reset_int or not enable_int then + sequencer_state <= IDLE; + ovf_frame_cnt <= 0; + seq <= 0; + else + case sequencer_state is + when IDLE => + if channel_sync_int = '1' then + if ovf_frame_cnt = 0 then + sequencer_state <= ACTIVE; + else + ovf_frame_cnt <= (ovf_frame_cnt + 1) mod 2; + end if; + end if; + when ACTIVE => + -- The unlikely event the last ack came in in the same clock + -- cyclce as the channel sync signal will still be treated + -- as an overflow. This keeps the logic simple + if ack = '1' then + if seq = C_NUM - 1 then + sequencer_state <= IDLE; + seq <= 0; + else + seq <= seq + 1; + end if; + end if; + if channel_sync_int = '1' then + ovf_frame_cnt <= (ovf_frame_cnt + 1) mod 2; + end if; + end case; + end if; + end if; + end process; + + data <= data_latched(seq); + + gen: for i in 0 to C_NUM - 1 generate + + unserialize_data: process(clk) + begin + if rising_edge(clk) then + if reset_int then + data_int(i) <= (others => '0'); + elsif bit_sync = '1' then + if channel_sync = '1' then + if sequencer_state = IDLE then + data_latched(i) <= data_int(i)(31 downto 32 - C_SLOT_WIDTH); +-- data_latched(i) <= data_int(i)(31 downto 32 - +-- C_SLOT_WIDTH + 8) & +-- std_logic_vector(to_unsigned(i+1,8)); + end if; + end if; + data_int(i) <= data_int(i)(30 downto 0) & sdata(i); + end if; + end if; + end process unserialize_data; + end generate; + + enable_sync: process (clk) + begin + if rising_edge(clk) then + if reset_int then + enable_int <= False; + else + if enable and frame_sync_int = '1' then + enable_int <= True; + elsif not enable then + enable_int <= False; + end if; + end if; + end if; + end process enable_sync; + +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_tx.vhd b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_tx.vhd new file mode 100644 index 0000000..a055d15 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/hdl/i2s_tx.vhd @@ -0,0 +1,134 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2013(c) Analog Devices, Inc. +-- Author: Lars-Peter Clausen +-- +-- All rights reserved. +-- +-- Redistribution and use in source and binary forms, with or without modification, +-- are permitted provided that the following conditions are met: +-- - Redistributions of source code must retain the above copyright +-- notice, this list of conditions and the following disclaimer. +-- - Redistributions in binary form must reproduce the above copyright +-- notice, this list of conditions and the following disclaimer in +-- the documentation and/or other materials provided with the +-- distribution. +-- - Neither the name of Analog Devices, Inc. nor the names of its +-- contributors may be used to endorse or promote products derived +-- from this software without specific prior written permission. +-- - The use of this software may or may not infringe the patent rights +-- of one or more patent holders. This license does not release you +-- from the requirement that you obtain separate licenses from these +-- patent holders to use this software. +-- - Use of the software either in source or binary form, must be run +-- on or directly connected to an Analog Devices Inc. component. +-- +-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +-- PARTICULAR PURPOSE ARE DISCLAIMED. +-- +-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity i2s_tx is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_NUM : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + enable : in Boolean; -- Enable TX + + bclk : in std_logic; -- Bit Clock + channel_sync : in std_logic; -- Channel Sync + frame_sync : in std_logic; -- Frame Sync + sdata : out std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output + + ack : out std_logic; -- Request new Slot Data + stb : in std_logic; -- Request new Slot Data + data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in + ); +end i2s_tx; + +architecture Behavioral of i2s_tx is + type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0); + signal data_int : mem; + signal reset_int : Boolean; + signal enable_int : Boolean; + + signal bit_sync : std_logic; + signal channel_sync_int : std_logic; + signal frame_sync_int : std_logic; + signal channel_sync_int_d1 : std_logic; + + signal bclk_d1 : std_logic; +begin + + reset_int <= resetn = '0' or not enable; + + process (clk) + begin + if rising_edge(clk) then + if resetn = '0' then + bclk_d1 <= '0'; + channel_sync_int_d1 <= '0'; + else + bclk_d1 <= bclk; + channel_sync_int_d1 <= channel_sync_int; + end if; + end if; + end process; + + bit_sync <= (bclk xor bclk_d1) and not bclk; + channel_sync_int <= channel_sync and bit_sync; + frame_sync_int <= frame_sync and bit_sync; + + ack <= '1' when channel_sync_int_d1 = '1' and enable_int else '0'; + + gen: for i in 0 to C_NUM - 1 generate + + serialize_data: process(clk) + begin + if rising_edge(clk) then + if reset_int then + data_int(i)(31 downto 0) <= (others => '0'); + elsif bit_sync = '1' then + if channel_sync_int = '1' then + data_int(i)(31 downto 32-C_SLOT_WIDTH) <= data; + data_int(i)(31-C_SLOT_WIDTH downto 0) <= (others => '0'); + else + data_int(i) <= data_int(i)(30 downto 0) & '0'; + end if; + end if; + end if; + end process serialize_data; + sdata(i) <= data_int(i)(31) when enable_int else '0'; + + end generate; + + enable_sync: process (clk) + begin + if rising_edge(clk) then + if reset_int then + enable_int <= False; + else + if enable and frame_sync_int = '1' and stb = '1' then + enable_int <= True; + elsif not enable then + enable_int <= False; + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/xgui/axi_i2s_adi_v1_2.tcl b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/xgui/axi_i2s_adi_v1_2.tcl new file mode 100644 index 0000000..df0c86f --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_i2s_adi_1.2/xgui/axi_i2s_adi_v1_2.tcl @@ -0,0 +1,105 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_S00_AXI_BASEADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S00_AXI_HIGHADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_LRCLK_POL" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_BCLK_POL" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_DMA_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_HAS_TX" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_HAS_RX" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_BCLK_POL { PARAM_VALUE.C_BCLK_POL } { + # Procedure called to update C_BCLK_POL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_BCLK_POL { PARAM_VALUE.C_BCLK_POL } { + # Procedure called to validate C_BCLK_POL + return true +} + +proc update_PARAM_VALUE.C_DMA_TYPE { PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to update C_DMA_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_DMA_TYPE { PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to validate C_DMA_TYPE + return true +} + +proc update_PARAM_VALUE.C_HAS_RX { PARAM_VALUE.C_HAS_RX } { + # Procedure called to update C_HAS_RX when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_HAS_RX { PARAM_VALUE.C_HAS_RX } { + # Procedure called to validate C_HAS_RX + return true +} + +proc update_PARAM_VALUE.C_HAS_TX { PARAM_VALUE.C_HAS_TX } { + # Procedure called to update C_HAS_TX when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_HAS_TX { PARAM_VALUE.C_HAS_TX } { + # Procedure called to validate C_HAS_TX + return true +} + +proc update_PARAM_VALUE.C_LRCLK_POL { PARAM_VALUE.C_LRCLK_POL } { + # Procedure called to update C_LRCLK_POL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_LRCLK_POL { PARAM_VALUE.C_LRCLK_POL } { + # Procedure called to validate C_LRCLK_POL + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to update C_S00_AXI_BASEADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_BASEADDR { PARAM_VALUE.C_S00_AXI_BASEADDR } { + # Procedure called to validate C_S00_AXI_BASEADDR + return true +} + +proc update_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to update C_S00_AXI_HIGHADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S00_AXI_HIGHADDR { PARAM_VALUE.C_S00_AXI_HIGHADDR } { + # Procedure called to validate C_S00_AXI_HIGHADDR + return true +} + + +proc update_MODELPARAM_VALUE.C_LRCLK_POL { MODELPARAM_VALUE.C_LRCLK_POL PARAM_VALUE.C_LRCLK_POL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_LRCLK_POL}] ${MODELPARAM_VALUE.C_LRCLK_POL} +} + +proc update_MODELPARAM_VALUE.C_BCLK_POL { MODELPARAM_VALUE.C_BCLK_POL PARAM_VALUE.C_BCLK_POL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_BCLK_POL}] ${MODELPARAM_VALUE.C_BCLK_POL} +} + +proc update_MODELPARAM_VALUE.C_DMA_TYPE { MODELPARAM_VALUE.C_DMA_TYPE PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_DMA_TYPE}] ${MODELPARAM_VALUE.C_DMA_TYPE} +} + +proc update_MODELPARAM_VALUE.C_HAS_TX { MODELPARAM_VALUE.C_HAS_TX PARAM_VALUE.C_HAS_TX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_HAS_TX}] ${MODELPARAM_VALUE.C_HAS_TX} +} + +proc update_MODELPARAM_VALUE.C_HAS_RX { MODELPARAM_VALUE.C_HAS_RX PARAM_VALUE.C_HAS_RX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_HAS_RX}] ${MODELPARAM_VALUE.C_HAS_RX} +} + diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/axi_reg32_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/component.xml b/zynqberrydemo3/ip_lib/axi_reg32_1.0/component.xml new file mode 100644 index 0000000..f1f9721 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/component.xml @@ -0,0 +1,2288 @@ + + + trenz.biz + user + axi_reg32 + 1.0 + + + S_AXI + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + WIZ.DATA_WIDTH + 32 + + + WIZ.NUM_REG + 32 + + + SUPPORTS_NARROW_BURST + 0 + + + + + S_AXI_RST + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S_AXI_CLK + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + + + S_AXI + + S_AXI_reg + 0 + 4096 + 32 + register + + + OFFSET_BASE_PARAM + C_S_AXI_BASEADDR + + + OFFSET_HIGH_PARAM + C_S_AXI_HIGHADDR + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axi_reg32_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + e1c055d0 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axi_reg32_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + e1c055d0 + + + + + xilinx_softwaredriver + Software Driver + :vivado.xilinx.com:sw.driver + + xilinx_softwaredriver_view_fileset + + + + viewChecksum + 61d40803 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c9c5ebb6 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + viewChecksum + a8354ffc + + + + + + + RR0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + RR1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + optional + true + + + + + + RR2 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + 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Width of S_AXI address bus + 7 + + + C_REG_WIDTH + C Reg Width + 32 + + + + false + + + + + + C_NUM_RO_REG + C Num Ro Reg + 2 + + + C_NUM_WR_REG + C Num Wr Reg + 2 + + + C_WR_READABLE + C Wr Readable + true + + + C_RR0_ALIAS + C Rr0 Alias + RR0 + + + C_RR1_ALIAS + C Rr1 Alias + RR1 + + + C_WR0_ALIAS + C Wr0 Alias + WR0 + + + C_WR1_ALIAS + C Wr1 Alias + WR1 + + + C_RR2_ALIAS + C Rr2 Alias + RR2 + + + C_RR3_ALIAS + C Rr3 Alias + RR3 + + + C_RR4_ALIAS + C Rr4 Alias + RR4 + + + C_RR5_ALIAS + C Rr5 Alias + RR5 + + + C_RR6_ALIAS + C Rr6 Alias + RR6 + + + C_RR7_ALIAS + C Rr7 Alias + RR7 + + + C_RR8_ALIAS + C Rr8 Alias + RR8 + + + C_RR9_ALIAS + C Rr9 Alias + RR9 + + + C_RR10_ALIAS + C Rr10 Alias + RR10 + + + C_RR11_ALIAS + C Rr11 Alias + RR11 + + + C_RR12_ALIAS + C Rr12 Alias + RR12 + + + C_RR13_ALIAS + C Rr13 Alias + RR13 + + + C_RR14_ALIAS + C Rr14 Alias + RR14 + + + C_RR15_ALIAS + C Rr15 Alias + RR15 + + + C_WR2_ALIAS + C Wr2 Alias + WR2 + + + C_WR3_ALIAS + C Wr3 Alias + WR3 + + + C_WR4_ALIAS + C Wr4 Alias + WR4 + + + C_WR5_ALIAS + C Wr5 Alias + WR5 + + + C_WR6_ALIAS + C Wr6 Alias + WR6 + + + C_WR7_ALIAS + C Wr7 Alias + WR7 + + + C_WR8_ALIAS + C Wr8 Alias + WR8 + + + C_WR9_ALIAS + C Wr9 Alias + WR9 + + + C_WR10_ALIAS + C Wr10 Alias + WR10 + + + C_WR11_ALIAS + C Wr11 Alias + WR11 + + + C_WR12_ALIAS + C Wr12 Alias + WR12 + + + C_WR13_ALIAS + C Wr13 Alias + WR13 + + + C_WR14_ALIAS + C Wr14 Alias + WR14 + + + C_WR15_ALIAS + C Wr15 Alias + WR15 + + + C_WR0_DEFAULT + C Wr0 Default + 0 + + + C_WR1_DEFAULT + C Wr1 Default + 0 + + + C_WR2_DEFAULT + C Wr2 Default + 0 + + + C_WR3_DEFAULT + C Wr3 Default + 0 + + + C_WR4_DEFAULT + C Wr4 Default + 0 + + + C_WR5_DEFAULT + C Wr5 Default + 0 + + + C_WR6_DEFAULT + C Wr6 Default + 0 + + + C_WR7_DEFAULT + C Wr7 Default + 0 + + + C_WR8_DEFAULT + C Wr8 Default + 0 + + + C_WR9_DEFAULT + C Wr9 Default + 0 + + + C_WR10_DEFAULT + C Wr10 Default + 0 + + + C_WR11_DEFAULT + C Wr11 Default + 0 + + + C_WR12_DEFAULT + C Wr12 Default + 0 + + + C_WR13_DEFAULT + C Wr13 Default + 0 + + + C_WR14_DEFAULT + C Wr14 Default + 0 + + + C_WR15_DEFAULT + C Wr15 Default + 0 + + + + + + choices_0 + 32 + + + choices_1 + 1 + 0 + + + choices_2 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + choices_3 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axi_reg32_v1_0_S_AXI.vhd + vhdlSource + axi_lib + + + hdl/axi_reg32_v1_0.vhd + vhdlSource + CHECKSUM_99fe5a45 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axi_reg32_v1_0_S_AXI.vhd + vhdlSource + axi_lib + + + hdl/axi_reg32_v1_0.vhd + vhdlSource + + + + xilinx_softwaredriver_view_fileset + + drivers/axi_reg32_v1_0/data/axi_reg32.mdd + mdd + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/data/axi_reg32.tcl + tclSource + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/src/Makefile + unknown + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/src/axi_reg32.h + cSource + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/src/axi_reg32.c + cSource + USED_IN_hw_handoff + + + drivers/axi_reg32_v1_0/src/axi_reg32_selftest.c + cSource + USED_IN_hw_handoff + + + + xilinx_xpgui_view_fileset + + xgui/axi_reg32_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_11b62932 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_utilityxitfiles_view_fileset + + gui/axi_reg32_v1_0.gtcl + GTCL + + + + AXI Register Bank 16/16 v1.0 + + + C_S_AXI_DATA_WIDTH + C S AXI DATA WIDTH + Width of S_AXI data bus + 32 + + + + false + + + + + + C_S_AXI_ADDR_WIDTH + C S AXI ADDR WIDTH + Width of S_AXI address bus + 7 + + + + false + + + + + + C_S_AXI_BASEADDR + C S AXI BASEADDR + 0xFFFFFFFF + + + + false + + + + + + C_S_AXI_HIGHADDR + C S AXI HIGHADDR + 0x00000000 + + + + false + + + + + + Component_Name + axi_reg32_v1_0 + + + C_NUM_RO_REG + Number of input registers + 2 + + + C_NUM_WR_REG + Number of output registers + 2 + + + C_WR_READABLE + Output registers are readable + true + + + C_RR0_ALIAS + RR0 + RR0 + + + + true + + + + + + C_RR1_ALIAS + RR1 + RR1 + + + + true + + + + + + C_WR0_ALIAS + WR0 + WR0 + + + C_WR1_ALIAS + WR1 + WR1 + + + C_RR2_ALIAS + RR2 + RR2 + + + C_RR3_ALIAS + RR3 + RR3 + + + C_RR4_ALIAS + RR4 + RR4 + + + C_RR5_ALIAS + RR5 + RR5 + + + C_RR6_ALIAS + RR6 + RR6 + + + C_RR7_ALIAS + RR7 + RR7 + + + C_RR8_ALIAS + RR8 + RR8 + + + C_RR9_ALIAS + RR9 + RR9 + + + C_RR10_ALIAS + RR10 + RR10 + + + C_RR11_ALIAS + RR11 + RR11 + + + C_RR12_ALIAS + RR12 + RR12 + + + C_RR13_ALIAS + RR13 + RR13 + + + C_RR14_ALIAS + RR14 + RR14 + + + C_RR15_ALIAS + RR15 + RR15 + + + C_WR2_ALIAS + WR2 + WR2 + + + C_WR3_ALIAS + WR3 + WR3 + + + C_WR4_ALIAS + WR4 + WR4 + + + C_WR5_ALIAS + WR5 + WR5 + + + C_WR6_ALIAS + WR6 + WR6 + + + C_WR7_ALIAS + WR7 + WR7 + + + C_WR8_ALIAS + WR8 + WR8 + + + C_WR9_ALIAS + WR9 + WR9 + + + C_WR10_ALIAS + WR10 + WR10 + + + C_WR11_ALIAS + WR11 + WR11 + + + C_WR12_ALIAS + WR12 + WR12 + + + C_WR13_ALIAS + WR13 + WR13 + + + C_WR14_ALIAS + WR14 + WR14 + + + C_WR15_ALIAS + WR15 + WR15 + + + C_WR0_DEFAULT + WR0 Value + 0 + + + C_WR1_DEFAULT + WR1 Value + 0 + + + C_WR2_DEFAULT + WR2 Value + 0 + + + C_WR3_DEFAULT + WR3 Value + 0 + + + C_WR4_DEFAULT + WR4 Value + 0 + + + C_WR5_DEFAULT + WR5 Value + 0 + + + C_WR6_DEFAULT + WR6 Value + 0 + + + C_WR7_DEFAULT + WR7 Value + 0 + + + C_WR8_DEFAULT + WR8 Value + 0 + + + C_WR9_DEFAULT + WR9 Value + 0 + + + C_WR10_DEFAULT + WR10 Value + 0 + + + C_WR11_DEFAULT + WR11 Value + 0 + + + C_WR12_DEFAULT + WR12 Value + 0 + + + C_WR13_DEFAULT + WR13 Value + 0 + + + C_WR14_DEFAULT + WR14 Value + 0 + + + C_WR15_DEFAULT + WR15 Value + 0 + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + AXI_Peripheral + + AXI Register Bank 16/16 v1.0 + Trenz Electronic GmbH + 13 + 2015-12-03T08:47:21Z + + b:/cores/2014.4/ip/axi_reg32_1.0 + + + + 2014.4 + + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/data/axi_reg32.tcl b/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/data/axi_reg32.tcl new file mode 100644 index 0000000..9044b7c --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/data/axi_reg32.tcl @@ -0,0 +1,5 @@ + + +proc generate {drv_handle} { + xdefine_include_file $drv_handle "xparameters.h" "axi_reg32" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" +} diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.c b/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.c new file mode 100644 index 0000000..1db5c5c --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.c @@ -0,0 +1,6 @@ + + +/***************************** Include Files *******************************/ +#include "axi_reg32.h" + +/************************** Function Definitions ***************************/ diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.h b/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.h new file mode 100644 index 0000000..58bb7b4 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32.h @@ -0,0 +1,107 @@ + +#ifndef AXI_REG32_H +#define AXI_REG32_H + + +/****************** Include Files ********************/ +#include "xil_types.h" +#include "xstatus.h" + +#define RR0_OFFSET 0 +#define RR1_OFFSET 4 +#define RR2_OFFSET 8 +#define RR3_OFFSET 12 +#define RR4_OFFSET 16 +#define RR5_OFFSET 20 +#define RR6_OFFSET 24 +#define RR7_OFFSET 28 +#define RR8_OFFSET 32 +#define RR9_OFFSET 36 +#define RR10_OFFSET 40 +#define RR11_OFFSET 44 +#define RR12_OFFSET 48 +#define RR13_OFFSET 52 +#define RR14_OFFSET 56 +#define RR15_OFFSET 60 +#define WR0_OFFSET 64 +#define WR1_OFFSET 68 +#define WR2_OFFSET 72 +#define WR3_OFFSET 76 +#define WR4_OFFSET 80 +#define WR5_OFFSET 84 +#define WR6_OFFSET 88 +#define WR7_OFFSET 92 +#define WR8_OFFSET 96 +#define WR9_OFFSET 100 +#define WR10_OFFSET 104 +#define WR11_OFFSET 108 +#define WR12_OFFSET 112 +#define WR13_OFFSET 116 +#define WR14_OFFSET 120 +#define WR15_OFFSET 124 + + +/**************************** Type Definitions *****************************/ +/** + * + * Write a value to a AXI_REG32 register. A 32 bit write is performed. + * If the component is implemented in a smaller width, only the least + * significant data is written. + * + * @param BaseAddress is the base address of the AXI_REG32device. + * @param RegOffset is the register offset from the base to write to. + * @param Data is the data written to the register. + * + * @return None. + * + * @note + * C-style signature: + * void AXI_REG32_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data) + * + */ +#define AXI_REG32_mWriteReg(BaseAddress, RegOffset, Data) \ + Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/** + * + * Read a value from a AXI_REG32 register. A 32 bit read is performed. + * If the component is implemented in a smaller width, only the least + * significant data is read from the register. The most significant data + * will be read as 0. + * + * @param BaseAddress is the base address of the AXI_REG32 device. + * @param RegOffset is the register offset from the base to write to. + * + * @return Data is the data from the register. + * + * @note + * C-style signature: + * u32 AXI_REG32_mReadReg(u32 BaseAddress, unsigned RegOffset) + * + */ +#define AXI_REG32_mReadReg(BaseAddress, RegOffset) \ + Xil_In32((BaseAddress) + (RegOffset)) + +/************************** Function Prototypes ****************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the AXI_REG32 instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus AXI_REG32_Reg_SelfTest(void * baseaddr_p); + +#endif // AXI_REG32_H diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32_selftest.c b/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32_selftest.c new file mode 100644 index 0000000..dc45655 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/drivers/axi_reg32_v1_0/src/axi_reg32_selftest.c @@ -0,0 +1,60 @@ + +/***************************** Include Files *******************************/ +#include "axi_reg32.h" +#include "xparameters.h" +#include "stdio.h" +#include "xil_io.h" + +/************************** Constant Definitions ***************************/ +#define READ_WRITE_MUL_FACTOR 0x10 + +/************************** Function Definitions ***************************/ +/** + * + * Run a self-test on the driver/device. Note this may be a destructive test if + * resets of the device are performed. + * + * If the hardware system is not built correctly, this function may never + * return to the caller. + * + * @param baseaddr_p is the base address of the AXI_REG32instance to be worked on. + * + * @return + * + * - XST_SUCCESS if all self-test code passed + * - XST_FAILURE if any self-test code failed + * + * @note Caching must be turned off for this function to work. + * @note Self test may fail if data memory and device are not on the same bus. + * + */ +XStatus AXI_REG32_Reg_SelfTest(void * baseaddr_p) +{ + u32 baseaddr; + int write_loop_index; + int read_loop_index; + int Index; + + baseaddr = (u32) baseaddr_p; + + xil_printf("******************************\n\r"); + xil_printf("* User Peripheral Self Test\n\r"); + xil_printf("******************************\n\n\r"); + + /* + * Write to user logic slave module register(s) and read back + */ + xil_printf("User logic slave module test...\n\r"); + + for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++) + AXI_REG32_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR); + for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++) + if ( AXI_REG32_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){ + xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4); + return XST_FAILURE; + } + + xil_printf(" - slave register write/read passed\n\n\r"); + + return XST_SUCCESS; +} diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/bfm_design/axi_reg32_v1_0_tb.v b/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/bfm_design/axi_reg32_v1_0_tb.v new file mode 100644 index 0000000..a2b9560 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/bfm_design/axi_reg32_v1_0_tb.v @@ -0,0 +1,184 @@ + +`timescale 1 ns / 1 ps + +`include "axi_reg32_v1_0_tb_include.vh" + +// lite_response Type Defines +`define RESPONSE_OKAY 2'b00 +`define RESPONSE_EXOKAY 2'b01 +`define RESP_BUS_WIDTH 2 +`define BURST_TYPE_INCR 2'b01 +`define BURST_TYPE_WRAP 2'b10 + +// AMBA AXI4 Lite Range Constants +`define S_AXI_MAX_BURST_LENGTH 1 +`define S_AXI_DATA_BUS_WIDTH 32 +`define S_AXI_ADDRESS_BUS_WIDTH 32 +`define S_AXI_MAX_DATA_SIZE (`S_AXI_DATA_BUS_WIDTH*`S_AXI_MAX_BURST_LENGTH)/8 + +module axi_reg32_v1_0_tb; + reg tb_ACLK; + reg tb_ARESETn; + + // Create an instance of the example tb + `BD_WRAPPER dut (.ACLK(tb_ACLK), + .ARESETN(tb_ARESETn)); + + // Local Variables + + // AMBA S_AXI AXI4 Lite Local Reg + reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_rd_data_lite; + reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_test_data_lite [3:0]; + reg [`RESP_BUS_WIDTH-1:0] S_AXI_lite_response; + reg [`S_AXI_ADDRESS_BUS_WIDTH-1:0] S_AXI_mtestAddress; + reg [3-1:0] S_AXI_mtestProtection_lite; + integer S_AXI_mtestvectorlite; // Master side testvector + integer S_AXI_mtestdatasizelite; + integer result_slave_lite; + + + // Simple Reset Generator and test + initial begin + tb_ARESETn = 1'b0; + #500; + // Release the reset on the posedge of the clk. + @(posedge tb_ACLK); + tb_ARESETn = 1'b1; + @(posedge tb_ACLK); + end + + // Simple Clock Generator + initial tb_ACLK = 1'b0; + always #10 tb_ACLK = !tb_ACLK; + + //------------------------------------------------------------------------ + // TEST LEVEL API: CHECK_RESPONSE_OKAY + //------------------------------------------------------------------------ + // Description: + // CHECK_RESPONSE_OKAY(lite_response) + // This task checks if the return lite_response is equal to OKAY + //------------------------------------------------------------------------ + task automatic CHECK_RESPONSE_OKAY; + input [`RESP_BUS_WIDTH-1:0] response; + begin + if (response !== `RESPONSE_OKAY) begin + $display("TESTBENCH ERROR! lite_response is not OKAY", + "\n expected = 0x%h",`RESPONSE_OKAY, + "\n actual = 0x%h",response); + $stop; + end + end + endtask + + //------------------------------------------------------------------------ + // TEST LEVEL API: COMPARE_LITE_DATA + //------------------------------------------------------------------------ + // Description: + // COMPARE_LITE_DATA(expected,actual) + // This task checks if the actual data is equal to the expected data. + // X is used as don't care but it is not permitted for the full vector + // to be don't care. + //------------------------------------------------------------------------ + task automatic COMPARE_LITE_DATA; + input expected; + input actual; + begin + if (expected === 'hx || actual === 'hx) begin + $display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!"); + result_slave_lite = 0; + $stop; + end + + if (actual != expected) begin + $display("TESTBENCH ERROR! Data expected is not equal to actual.", + "\nexpected = 0x%h",expected, + "\nactual = 0x%h",actual); + result_slave_lite = 0; + $stop; + end + else + begin + $display("TESTBENCH Passed! Data expected is equal to actual.", + "\n expected = 0x%h",expected, + "\n actual = 0x%h",actual); + end + end + endtask + + task automatic S_AXI_TEST; + begin + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST : S_AXI"); + $display("Simple register write and read example"); + $display("---------------------------------------------------------"); + + S_AXI_mtestvectorlite = 0; + S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS; + S_AXI_mtestProtection_lite = 0; + S_AXI_mtestdatasizelite = `S_AXI_MAX_DATA_SIZE; + + result_slave_lite = 1; + + for (S_AXI_mtestvectorlite = 0; S_AXI_mtestvectorlite <= 3; S_AXI_mtestvectorlite = S_AXI_mtestvectorlite + 1) + begin + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S_AXI_mtestAddress, + S_AXI_mtestProtection_lite, + S_AXI_test_data_lite[S_AXI_mtestvectorlite], + S_AXI_mtestdatasizelite, + S_AXI_lite_response); + $display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_lite_response); + CHECK_RESPONSE_OKAY(S_AXI_lite_response); + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_mtestAddress, + S_AXI_mtestProtection_lite, + S_AXI_rd_data_lite, + S_AXI_lite_response); + $display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_rd_data_lite,S_AXI_lite_response); + CHECK_RESPONSE_OKAY(S_AXI_lite_response); + COMPARE_LITE_DATA(S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_rd_data_lite); + $display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S_AXI_mtestvectorlite,S_AXI_mtestvectorlite); + S_AXI_mtestAddress = S_AXI_mtestAddress + 32'h00000004; + end + + $display("---------------------------------------------------------"); + $display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!"); + if ( result_slave_lite ) begin + $display("PTGEN_TEST: PASSED!"); + end else begin + $display("PTGEN_TEST: FAILED!"); + end + $display("---------------------------------------------------------"); + end + endtask + + // Create the test vectors + initial begin + // When performing debug enable all levels of INFO messages. + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1); + + // Create test data vectors + S_AXI_test_data_lite[0] = 32'h0101FFFF; + S_AXI_test_data_lite[1] = 32'habcd0001; + S_AXI_test_data_lite[2] = 32'hdead0011; + S_AXI_test_data_lite[3] = 32'hbeef0011; + end + + // Drive the BFM + initial begin + // Wait for end of reset + wait(tb_ARESETn === 0) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + wait(tb_ARESETn === 1) @(posedge tb_ACLK); + + S_AXI_TEST(); + + end + +endmodule diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/bfm_design/design.tcl b/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/bfm_design/design.tcl new file mode 100644 index 0000000..019686e --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/bfm_design/design.tcl @@ -0,0 +1,91 @@ +proc create_ipi_design { offsetfile design_name } { + create_bd_design $design_name + open_bd_design $design_name + + # Create Clock and Reset Ports + set ACLK [ create_bd_port -dir I -type clk ACLK ] + set_property -dict [ list CONFIG.FREQ_HZ {100000000} CONFIG.PHASE {0.000} CONFIG.CLK_DOMAIN "${design_name}_ACLK" ] $ACLK + set ARESETN [ create_bd_port -dir I -type rst ARESETN ] + set_property -dict [ list CONFIG.POLARITY {ACTIVE_LOW} ] $ARESETN + set_property CONFIG.ASSOCIATED_RESET ARESETN $ACLK + + # Create instance: axi_reg32_0, and set properties + set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0] + + # Create instance: master_0, and set properties + set master_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cdn_axi_bfm master_0] + set_property -dict [ list CONFIG.C_PROTOCOL_SELECTION {2} ] $master_0 + + # Create interface connections + connect_bd_intf_net [get_bd_intf_pins master_0/M_AXI_LITE] [get_bd_intf_pins axi_reg32_0/S_AXI] + + # Create port connections + connect_bd_net -net aclk_net [get_bd_ports ACLK] [get_bd_pins master_0/M_AXI_LITE_ACLK] [get_bd_pins axi_reg32_0/S_AXI_ACLK] + connect_bd_net -net aresetn_net [get_bd_ports ARESETN] [get_bd_pins master_0/M_AXI_LITE_ARESETN] [get_bd_pins axi_reg32_0/S_AXI_ARESETN] + + # Auto assign address + assign_bd_address + + # Copy all address to interface_address.vh file + set bd_path [file dirname [get_property NAME [get_files ${design_name}.bd]]] + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/axi_reg32_v1_0_tb_include.vh" + set fp [open $offset_file "w"] + puts $fp "`ifndef axi_reg32_v1_0_tb_include_vh_" + puts $fp "`define axi_reg32_v1_0_tb_include_vh_\n" + puts $fp "//Configuration current bd names" + puts $fp "`define BD_INST_NAME ${design_name}_i" + puts $fp "`define BD_WRAPPER ${design_name}_wrapper\n" + puts $fp "//Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs -of_objects [get_bd_addr_spaces master_0/Data_lite]]] + set offset_hex [string replace $offset 0 1 "32'h"] + puts $fp "`define S_AXI_SLAVE_ADDRESS ${offset_hex}" + + puts $fp "`endif" + close $fp +} + +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores trenz.biz:user:axi_reg32:1.0]]]] +set test_bench_file ${ip_path}/example_designs/bfm_design/axi_reg32_v1_0_tb.v +set interface_address_vh_file "" + +# Set IP Repository and Update IP Catalogue +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "axi_reg32_v1_0_bfm_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +create_ipi_design interface_address_vh_file ${design_name} +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +set_property SOURCE_SET sources_1 [get_filesets sim_1] +import_files -fileset sim_1 -norecurse -force $test_bench_file +remove_files -quiet -fileset sim_1 axi_reg32_v1_0_tb_include.vh +import_files -fileset sim_1 -norecurse -force $interface_address_vh_file +set_property top axi_reg32_v1_0_tb [get_filesets sim_1] +set_property top_lib {} [get_filesets sim_1] +set_property top_file {} [get_filesets sim_1] +launch_xsim -simset sim_1 -mode behavioral +restart +run 1000 us diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/axi_reg32_v1_0_hw_test.tcl b/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/axi_reg32_v1_0_hw_test.tcl new file mode 100644 index 0000000..2f63ccb --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/axi_reg32_v1_0_hw_test.tcl @@ -0,0 +1,45 @@ +# Runtime Tcl commands to interact with - axi_reg32_v1_0 + +# Sourcing design address info tcl +set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd +source ${bd_path}/axi_reg32_v1_0_include.tcl + +# jtag axi master interface hardware name, change as per your design. +set jtag_axi_master hw_axi_1 +set ec 0 + +# hw test script +# Delete all previous axis transactions +if { [llength [get_hw_axi_txns -quiet]] } { + delete_hw_axi_txn [get_hw_axi_txns -quiet] +} + + +# Test all lite slaves. +set wdata_1 abcd1234 + +# Test: S_AXI +# Create a write transaction at s_axi_addr address +create_hw_axi_txn w_s_axi_addr [get_hw_axis $jtag_axi_master] -type write -address $s_axi_addr -data $wdata_1 +# Create a read transaction at s_axi_addr address +create_hw_axi_txn r_s_axi_addr [get_hw_axis $jtag_axi_master] -type read -address $s_axi_addr +# Initiate transactions +run_hw_axi r_s_axi_addr +run_hw_axi w_s_axi_addr +run_hw_axi r_s_axi_addr +set rdata_tmp [get_property DATA [get_hw_axi_txn r_s_axi_addr]] +# Compare read data +if { $rdata_tmp == $wdata_1 } { + puts "Data comparison test pass for - S_AXI" +} else { + puts "Data comparison test fail for - S_AXI, expected-$wdata_1 actual-$rdata_tmp" + inc ec +} + +# Check error flag +if { $ec == 0 } { + puts "PTGEN_TEST: PASSED!" +} else { + puts "PTGEN_TEST: FAILED!" +} + diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/design.tcl b/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/design.tcl new file mode 100644 index 0000000..77acc83 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/example_designs/debug_hw_design/design.tcl @@ -0,0 +1,175 @@ + +proc create_ipi_design { offsetfile design_name } { + + create_bd_design $design_name + open_bd_design $design_name + + # Create and configure Clock/Reset + create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz sys_clk_0 + create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset sys_reset_0 + + #check if current_board is set, if true - figure out required clocks. + set is_board_clock_found 0 + set is_board_reset_found 0 + set external_reset_port "" + set external_clock_port "" + + if { [current_board_part -quiet] != "" } { + + #check if any reset interface exists in board. + set board_reset [lindex [get_board_part_interfaces -filter { BUSDEF_NAME == reset_rtl && MODE == slave }] 0 ] + if { $board_reset ne "" } { + set is_board_reset_found 1 + apply_board_connection -board_interface $board_reset -ip_intf sys_clk_0/reset -diagram [current_bd_design] + apply_board_connection -board_interface $board_reset -ip_intf sys_reset_0/ext_reset -diagram [current_bd_design] + set external_rst [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/reset]]] + if { $external_rst ne "" } { + set external_reset_port [get_property NAME $external_rst] + } + } else { + send_msg "ptgen 51-200" WARNING "No reset interface found in current_board, Users may need to specify the location constraints manually." + } + + # check for differential clock, exclude any special clocks which has TYPE property. + set board_clock_busifs "" + foreach busif [get_board_part_interfaces -filter "BUSDEF_NAME == diff_clock_rtl"] { + set type [get_property PARAM.TYPE $busif] + if { $type == "" } { + set board_clock_busifs $busif + break + } + } + if { $board_clock_busifs ne "" } { + apply_board_connection -board_interface $board_clock_busifs -ip_intf sys_clk_0/CLK_IN1_D -diagram [current_bd_design] + set is_board_clock_found 1 + } else { + # check for single ended clock + set board_sclock_busifs [lindex [get_board_part_interfaces -filter "BUSDEF_NAME == clock_rtl"] 0 ] + if { $board_sclock_busifs ne "" } { + apply_board_connection -board_interface $board_sclock_busifs -ip_intf sys_clk_0/clock_CLK_IN1 -diagram [current_bd_design] + set external_clk [get_bd_ports -quiet -of_objects [get_bd_nets -quiet -of_objects [get_bd_pins -quiet sys_clk_0/clk_in1]]] + if { $external_clk ne "" } { + set external_clock_port [get_property NAME $external_clk] + } + set is_board_clock_found 1 + } else { + send_msg "ptgen 51-200" WARNING "No clock interface found in current_board, Users may need to specify the location constraints manually." + } + } + + } else { + send_msg "ptgen 51-201" WARNING "No board selected in current_project. Users may need to specify the location constraints manually." + } + + #if there is no corresponding board interface found, assume constraints will be provided manually while pin planning. + if { $is_board_reset_found == 0 } { + create_bd_port -dir I -type rst reset_rtl + set_property CONFIG.POLARITY [get_property CONFIG.POLARITY [get_bd_pins sys_clk_0/reset]] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_pins sys_reset_0/ext_reset_in] [get_bd_ports reset_rtl] + connect_bd_net [get_bd_ports reset_rtl] [get_bd_pins sys_clk_0/reset] + set external_reset_port reset_rtl + } + if { $is_board_clock_found == 0 } { + create_bd_port -dir I -type clk clock_rtl + connect_bd_net [get_bd_pins sys_clk_0/clk_in1] [get_bd_ports clock_rtl] + set external_clock_port clock_rtl + } + + #Avoid IPI DRC, make clock port synchronous to reset + if { $external_clock_port ne "" && $external_reset_port ne "" } { + set_property CONFIG.ASSOCIATED_RESET $external_reset_port [get_bd_ports $external_clock_port] + } + + # Connect other sys_reset pins + connect_bd_net [get_bd_pins sys_reset_0/slowest_sync_clk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins sys_clk_0/locked] [get_bd_pins sys_reset_0/dcm_locked] + + # Create instance: axi_reg32_0, and set properties + set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0 ] + + # Create instance: jtag_axi_0, and set properties + set jtag_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:jtag_axi jtag_axi_0 ] + set_property -dict [list CONFIG.PROTOCOL {0}] [get_bd_cells jtag_axi_0] + connect_bd_net [get_bd_pins jtag_axi_0/aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins jtag_axi_0/aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Create instance: axi_peri_interconnect, and set properties + set axi_peri_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect axi_peri_interconnect ] + connect_bd_net [get_bd_pins axi_peri_interconnect/ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/ARESETN] [get_bd_pins sys_reset_0/interconnect_aresetn] + set_property -dict [ list CONFIG.NUM_SI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/S00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + connect_bd_intf_net [get_bd_intf_pins jtag_axi_0/M_AXI] [get_bd_intf_pins axi_peri_interconnect/S00_AXI] + + set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_peri_interconnect + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ACLK] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_peri_interconnect/M00_ARESETN] [get_bd_pins sys_reset_0/peripheral_aresetn] + + # Connect all clock & reset of axi_reg32_0 slave interfaces.. + connect_bd_intf_net [get_bd_intf_pins axi_peri_interconnect/M00_AXI] [get_bd_intf_pins axi_reg32_0/S_AXI] + connect_bd_net [get_bd_pins axi_reg32_0/s_axi_aclk] [get_bd_pins sys_clk_0/clk_out1] + connect_bd_net [get_bd_pins axi_reg32_0/s_axi_aresetn] [get_bd_pins sys_reset_0/peripheral_aresetn] + + + # Auto assign address + assign_bd_address + + # Copy all address to axi_reg32_v1_0_include.tcl file + set bd_path [get_property DIRECTORY [current_project]]/[current_project].srcs/[current_fileset]/bd + upvar 1 $offsetfile offset_file + set offset_file "${bd_path}/axi_reg32_v1_0_include.tcl" + set fp [open $offset_file "w"] + puts $fp "# Configuration address parameters" + + set offset [get_property OFFSET [get_bd_addr_segs /jtag_axi_0/Data/SEG_axi_reg32_0_S_AXI_* ]] + puts $fp "set s_axi_addr ${offset}" + + close $fp +} + +# Set IP Repository and Update IP Catalogue +set ip_path [file dirname [file normalize [get_property XML_FILE_NAME [ipx::get_cores trenz.biz:user:axi_reg32:1.0]]]] +set hw_test_file ${ip_path}/example_designs/debug_hw_design/axi_reg32_v1_0_hw_test.tcl + +set repo_paths [get_property ip_repo_paths [current_fileset]] +if { [lsearch -exact -nocase $repo_paths $ip_path ] == -1 } { + set_property ip_repo_paths "$ip_path [get_property ip_repo_paths [current_fileset]]" [current_fileset] + update_ip_catalog +} + +set design_name "" +set all_bd {} +set all_bd_files [get_files *.bd -quiet] +foreach file $all_bd_files { +set file_name [string range $file [expr {[string last "/" $file] + 1}] end] +set bd_name [string range $file_name 0 [expr {[string last "." $file_name] -1}]] +lappend all_bd $bd_name +} + +for { set i 1 } { 1 } { incr i } { + set design_name "axi_reg32_v1_0_hw_${i}" + if { [lsearch -exact -nocase $all_bd $design_name ] == -1 } { + break + } +} + +set intf_address_include_file "" +create_ipi_design intf_address_include_file ${design_name} +save_bd_design +validate_bd_design + +set wrapper_file [make_wrapper -files [get_files ${design_name}.bd] -top -force] +import_files -force -norecurse $wrapper_file + +puts "-------------------------------------------------------------------------------------------------" +puts "INFO NEXT STEPS : Until this stage, debug hardware design has been created, " +puts " please perform following steps to test design in targeted board." +puts "1. Generate bitstream" +puts "2. Setup your targeted board, open hardware manager and open new(or existing) hardware target" +puts "3. Download generated bitstream" +puts "4. Run generated hardware test using below command, this invokes basic read/write operation" +puts " to every interface present in the peripheral : xilinx.com:user:myip:1.0" +puts " : source -notrace ${hw_test_file}" +puts "-------------------------------------------------------------------------------------------------" + diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0.vhd b/zynqberrydemo3/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0.vhd new file mode 100644 index 0000000..7cc74c8 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0.vhd @@ -0,0 +1,263 @@ +---------------------------------------------------------------------------------------------------- +--! @file axi_reg32_v1_0.vhd +--! @brief xxx +--! @author Antti Lukats +--! @version 1.0 +--! @date 2015 +--! @copyright Copyright 2015 Trenz Electronic GmbH +--! @license MIT License +--! @pre Vivado 2014.4+ +---------------------------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library axi_lib; + use axi_lib.all; + + +entity axi_reg32_v1_0 is + generic ( + -- Users to add parameters here + C_NUM_RO_REG : integer range 0 to 16 := 16; + C_NUM_WR_REG : integer range 0 to 16 := 16; + + C_WR_READABLE: boolean := true; + + C_RR0_ALIAS : string := "RR0"; + C_RR1_ALIAS : string := "RR1"; + C_RR2_ALIAS : string := "RR2"; + C_RR3_ALIAS : string := "RR3"; + + C_RR4_ALIAS : string := "RR4"; + C_RR5_ALIAS : string := "RR5"; + C_RR6_ALIAS : string := "RR6"; + C_RR7_ALIAS : string := "RR7"; + + C_RR8_ALIAS : string := "RR8"; + C_RR9_ALIAS : string := "RR9"; + C_RR10_ALIAS : string := "RR10"; + C_RR11_ALIAS : string := "RR11"; + + C_RR12_ALIAS : string := "RR12"; + C_RR13_ALIAS : string := "RR13"; + C_RR14_ALIAS : string := "RR14"; + C_RR15_ALIAS : string := "RR15"; + + -- + C_WR0_ALIAS : string := "WR0"; + C_WR1_ALIAS : string := "WR1"; + C_WR2_ALIAS : string := "WR2"; + C_WR3_ALIAS : string := "WR3"; + + C_WR4_ALIAS : string := "WR4"; + C_WR5_ALIAS : string := "WR5"; + C_WR6_ALIAS : string := "WR6"; + C_WR7_ALIAS : string := "WR7"; + + C_WR8_ALIAS : string := "WR8"; + C_WR9_ALIAS : string := "WR9"; + C_WR10_ALIAS : string := "WR10"; + C_WR11_ALIAS : string := "WR11"; + + C_WR12_ALIAS : string := "WR12"; + C_WR13_ALIAS : string := "WR13"; + C_WR14_ALIAS : string := "WR14"; + C_WR15_ALIAS : string := "WR15"; + + C_WR0_DEFAULT : integer := 0; + C_WR1_DEFAULT : integer := 0; + C_WR2_DEFAULT : integer := 0; + C_WR3_DEFAULT : integer := 0; + C_WR4_DEFAULT : integer := 0; + C_WR5_DEFAULT : integer := 0; + C_WR6_DEFAULT : integer := 0; + C_WR7_DEFAULT : integer := 0; + C_WR8_DEFAULT : integer := 0; + C_WR9_DEFAULT : integer := 0; + C_WR10_DEFAULT : integer := 0; + C_WR11_DEFAULT : integer := 0; + C_WR12_DEFAULT : integer := 0; + C_WR13_DEFAULT : integer := 0; + C_WR14_DEFAULT : integer := 0; + C_WR15_DEFAULT : integer := 0; + + + C_REG_WIDTH : integer range 8 to 32 := 32; + -- User parameters ends + -- Do not modify the parameters beyond this line + + + -- Parameters of Axi Slave Bus Interface S_AXI + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 7 + ); + port ( + -- Users to add ports here + + RR0 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR1 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR2 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR3 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR4 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR5 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR6 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR7 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR8 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR9 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR10 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR11 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR12 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR13 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR14 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR15 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR0 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR1 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR2 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR3 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR4 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR5 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR6 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR7 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR8 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR9 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR10 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR11 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR12 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR13 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR14 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR15 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + + -- User ports ends + -- Do not modify the ports beyond this line + + + -- Ports of Axi Slave Bus Interface S_AXI + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_awprot : in std_logic_vector(2 downto 0); + s_axi_awvalid : in std_logic; + s_axi_awready : out std_logic; + s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_wvalid : in std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_bready : in std_logic; + s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_arprot : in std_logic_vector(2 downto 0); + s_axi_arvalid : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_rready : in std_logic + ); +end axi_reg32_v1_0; + +architecture arch_imp of axi_reg32_v1_0 is + +begin + +-- Instantiation of Axi Bus Interface S_AXI +axi_reg32_v1_0_S_AXI_inst : entity axi_lib.axi_reg32_v1_0_S_AXI + generic map ( + C_NUM_RO_REG => C_NUM_RO_REG, + C_NUM_WR_REG => C_NUM_WR_REG, + C_WR_READABLE => C_WR_READABLE, + + C_WR0_DEFAULT => C_WR0_DEFAULT, + C_WR1_DEFAULT => C_WR1_DEFAULT, + C_WR2_DEFAULT => C_WR2_DEFAULT, + C_WR3_DEFAULT => C_WR3_DEFAULT, + C_WR4_DEFAULT => C_WR4_DEFAULT, + C_WR5_DEFAULT => C_WR5_DEFAULT, + C_WR6_DEFAULT => C_WR6_DEFAULT, + C_WR7_DEFAULT => C_WR7_DEFAULT, + C_WR8_DEFAULT => C_WR8_DEFAULT, + C_WR9_DEFAULT => C_WR9_DEFAULT, + C_WR10_DEFAULT => C_WR10_DEFAULT, + C_WR11_DEFAULT => C_WR11_DEFAULT, + C_WR12_DEFAULT => C_WR12_DEFAULT, + C_WR13_DEFAULT => C_WR13_DEFAULT, + C_WR14_DEFAULT => C_WR14_DEFAULT, + C_WR15_DEFAULT => C_WR15_DEFAULT, + + C_REG_WIDTH => C_REG_WIDTH, + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH + ) + port map ( + RR0 => RR0, + RR1 => RR1, + RR2 => RR2, + RR3 => RR3, + RR4 => RR4, + RR5 => RR5, + RR6 => RR6, + RR7 => RR7, + RR8 => RR8, + RR9 => RR9, + RR10 => RR10, + RR11 => RR11, + RR12 => RR12, + RR13 => RR13, + RR14 => RR14, + RR15 => RR15, + + WR0 => WR0, + WR1 => WR1, + WR2 => WR2, + WR3 => WR3, + WR4 => WR4, + WR5 => WR5, + WR6 => WR6, + WR7 => WR7, + WR8 => WR8, + WR9 => WR9, + WR10 => WR10, + WR11 => WR11, + WR12 => WR12, + WR13 => WR13, + WR14 => WR14, + WR15 => WR15, + + S_AXI_ACLK => s_axi_aclk, + S_AXI_ARESETN => s_axi_aresetn, + S_AXI_AWADDR => s_axi_awaddr, + S_AXI_AWPROT => s_axi_awprot, + S_AXI_AWVALID => s_axi_awvalid, + S_AXI_AWREADY => s_axi_awready, + S_AXI_WDATA => s_axi_wdata, + S_AXI_WSTRB => s_axi_wstrb, + S_AXI_WVALID => s_axi_wvalid, + S_AXI_WREADY => s_axi_wready, + S_AXI_BRESP => s_axi_bresp, + S_AXI_BVALID => s_axi_bvalid, + S_AXI_BREADY => s_axi_bready, + S_AXI_ARADDR => s_axi_araddr, + S_AXI_ARPROT => s_axi_arprot, + S_AXI_ARVALID => s_axi_arvalid, + S_AXI_ARREADY => s_axi_arready, + S_AXI_RDATA => s_axi_rdata, + S_AXI_RRESP => s_axi_rresp, + S_AXI_RVALID => s_axi_rvalid, + S_AXI_RREADY => s_axi_rready + ); + + -- Add user logic here + + -- User logic ends + +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0_S_AXI.vhd b/zynqberrydemo3/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0_S_AXI.vhd new file mode 100644 index 0000000..670d6f0 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/hdl/axi_reg32_v1_0_S_AXI.vhd @@ -0,0 +1,766 @@ +---------------------------------------------------------------------------------------------------- +--! @file axi_reg32_v1_0_S_AXI.vhd +--! @brief xxx +--! @author Antti Lukats +--! @version 1.0 +--! @date 2015 +--! @copyright Copyright 2015 Trenz Electronic GmbH +--! @license MIT License +--! @pre Vivado 2014.4+ +---------------------------------------------------------------------------------------------------- + +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library axi_lib; + use axi_lib.all; + +entity axi_reg32_v1_0_S_AXI is + generic ( + -- Users to add parameters here + C_NUM_RO_REG : integer range 0 to 16 := 2; + C_NUM_WR_REG : integer range 0 to 16 := 2; + C_WR_READABLE: boolean := true; + + + C_WR0_DEFAULT : integer := 0; + C_WR1_DEFAULT : integer := 0; + C_WR2_DEFAULT : integer := 0; + C_WR3_DEFAULT : integer := 0; + C_WR4_DEFAULT : integer := 0; + C_WR5_DEFAULT : integer := 0; + C_WR6_DEFAULT : integer := 0; + C_WR7_DEFAULT : integer := 0; + C_WR8_DEFAULT : integer := 0; + C_WR9_DEFAULT : integer := 0; + C_WR10_DEFAULT : integer := 0; + C_WR11_DEFAULT : integer := 0; + C_WR12_DEFAULT : integer := 0; + C_WR13_DEFAULT : integer := 0; + C_WR14_DEFAULT : integer := 0; + C_WR15_DEFAULT : integer := 0; + + C_REG_WIDTH : integer range 8 to 32 := 32; + -- User parameters ends + -- Do not modify the parameters beyond this line + + -- Width of S_AXI data bus + C_S_AXI_DATA_WIDTH : integer := 32; + -- Width of S_AXI address bus + C_S_AXI_ADDR_WIDTH : integer := 7 + ); + port ( + -- Users to add ports here + + RR0 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR1 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR2 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR3 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR4 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR5 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR6 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR7 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR8 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR9 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR10 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR11 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + RR12 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR13 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR14 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + RR15 : in std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR0 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR1 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR2 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR3 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR4 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR5 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR6 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR7 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR8 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR9 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR10 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR11 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + WR12 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR13 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR14 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + WR15 : out std_logic_vector(C_REG_WIDTH-1 downto 0); + + + -- User ports ends + -- Do not modify the ports beyond this line + + -- Global Clock Signal + S_AXI_ACLK : in std_logic; + -- Global Reset Signal. This Signal is Active LOW + S_AXI_ARESETN : in std_logic; + -- Write address (issued by master, acceped by Slave) + S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Write channel Protection type. This signal indicates the + -- privilege and security level of the transaction, and whether + -- the transaction is a data access or an instruction access. + S_AXI_AWPROT : in std_logic_vector(2 downto 0); + -- Write address valid. This signal indicates that the master signaling + -- valid write address and control information. + S_AXI_AWVALID : in std_logic; + -- Write address ready. This signal indicates that the slave is ready + -- to accept an address and associated control signals. + S_AXI_AWREADY : out std_logic; + -- Write data (issued by master, acceped by Slave) + S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Write strobes. This signal indicates which byte lanes hold + -- valid data. There is one write strobe bit for each eight + -- bits of the write data bus. + S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + -- Write valid. This signal indicates that valid write + -- data and strobes are available. + S_AXI_WVALID : in std_logic; + -- Write ready. This signal indicates that the slave + -- can accept the write data. + S_AXI_WREADY : out std_logic; + -- Write response. This signal indicates the status + -- of the write transaction. + S_AXI_BRESP : out std_logic_vector(1 downto 0); + -- Write response valid. This signal indicates that the channel + -- is signaling a valid write response. + S_AXI_BVALID : out std_logic; + -- Response ready. This signal indicates that the master + -- can accept a write response. + S_AXI_BREADY : in std_logic; + -- Read address (issued by master, acceped by Slave) + S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + -- Protection type. This signal indicates the privilege + -- and security level of the transaction, and whether the + -- transaction is a data access or an instruction access. + S_AXI_ARPROT : in std_logic_vector(2 downto 0); + -- Read address valid. This signal indicates that the channel + -- is signaling valid read address and control information. + S_AXI_ARVALID : in std_logic; + -- Read address ready. This signal indicates that the slave is + -- ready to accept an address and associated control signals. + S_AXI_ARREADY : out std_logic; + -- Read data (issued by slave) + S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + -- Read response. This signal indicates the status of the + -- read transfer. + S_AXI_RRESP : out std_logic_vector(1 downto 0); + -- Read valid. This signal indicates that the channel is + -- signaling the required read data. + S_AXI_RVALID : out std_logic; + -- Read ready. This signal indicates that the master can + -- accept the read data and response information. + S_AXI_RREADY : in std_logic + ); +end axi_reg32_v1_0_S_AXI; + +architecture arch_imp of axi_reg32_v1_0_S_AXI is + + -- AXI4LITE signals + signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_awready : std_logic; + signal axi_wready : std_logic; + signal axi_bresp : std_logic_vector(1 downto 0); + signal axi_bvalid : std_logic; + signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + signal axi_arready : std_logic; + signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal axi_rresp : std_logic_vector(1 downto 0); + signal axi_rvalid : std_logic; + + -- Example-specific design signals + -- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH + -- ADDR_LSB is used for addressing 32/64 bit registers/memories + -- ADDR_LSB = 2 for 32 bits (n downto 2) + -- ADDR_LSB = 3 for 64 bits (n downto 3) + constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1; + constant OPT_MEM_ADDR_BITS : integer := 4; + ------------------------------------------------ + ---- Signals for user logic register space example + -------------------------------------------------- + ---- Number of Slave Registers 32 + signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg4 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg5 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg6 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg7 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg8 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg9 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg10 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg11 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg12 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg13 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg14 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg15 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg16 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg17 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg18 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg19 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg20 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg21 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg22 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg23 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg24 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg25 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg26 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg27 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg28 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg29 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg30 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal slv_reg31 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + + signal slv_reg16r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg17r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg18r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg19r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg20r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg21r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg22r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg23r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg24r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg25r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg26r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg27r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg28r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg29r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg30r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + signal slv_reg31r :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0) := (others=>'0'); + + signal slv_reg_rden : std_logic; + signal slv_reg_wren : std_logic; + signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal byte_index : integer; + +begin + -- I/O Connections assignments + + S_AXI_AWREADY <= axi_awready; + S_AXI_WREADY <= axi_wready; + S_AXI_BRESP <= axi_bresp; + S_AXI_BVALID <= axi_bvalid; + S_AXI_ARREADY <= axi_arready; + S_AXI_RDATA <= axi_rdata; + S_AXI_RRESP <= axi_rresp; + S_AXI_RVALID <= axi_rvalid; + -- Implement axi_awready generation + -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awready <= '0'; + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- slave is ready to accept write address when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_awready <= '1'; + else + axi_awready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_awaddr latching + -- This process is used to latch the address when both + -- S_AXI_AWVALID and S_AXI_WVALID are valid. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_awaddr <= (others => '0'); + else + if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then + -- Write Address latching + axi_awaddr <= S_AXI_AWADDR; + end if; + end if; + end if; + end process; + + -- Implement axi_wready generation + -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is + -- de-asserted when reset is low. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_wready <= '0'; + else + if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then + -- slave is ready to accept write data when + -- there is a valid write address and write data + -- on the write address and data bus. This design + -- expects no outstanding transactions. + axi_wready <= '1'; + else + axi_wready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and write logic generation + -- The write data is accepted and written to memory mapped registers when + -- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to + -- select byte enables of slave registers while writing. + -- These registers are cleared when reset (active low) is applied. + -- Slave register write enable is asserted when valid address and data are available + -- and the slave is ready to accept the write address and write data. + slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ; + + process (S_AXI_ACLK) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + slv_reg16 <= STD_LOGIC_VECTOR(to_unsigned(C_WR0_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg17 <= STD_LOGIC_VECTOR(to_unsigned(C_WR1_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg18 <= STD_LOGIC_VECTOR(to_unsigned(C_WR2_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg19 <= STD_LOGIC_VECTOR(to_unsigned(C_WR3_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg20 <= STD_LOGIC_VECTOR(to_unsigned(C_WR4_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg21 <= STD_LOGIC_VECTOR(to_unsigned(C_WR5_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg22 <= STD_LOGIC_VECTOR(to_unsigned(C_WR6_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg23 <= STD_LOGIC_VECTOR(to_unsigned(C_WR7_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg24 <= STD_LOGIC_VECTOR(to_unsigned(C_WR8_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg25 <= STD_LOGIC_VECTOR(to_unsigned(C_WR9_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg26 <= STD_LOGIC_VECTOR(to_unsigned(C_WR10_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg27 <= STD_LOGIC_VECTOR(to_unsigned(C_WR11_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg28 <= STD_LOGIC_VECTOR(to_unsigned(C_WR12_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg29 <= STD_LOGIC_VECTOR(to_unsigned(C_WR13_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg30 <= STD_LOGIC_VECTOR(to_unsigned(C_WR14_DEFAULT,C_S_AXI_DATA_WIDTH)); + slv_reg31 <= STD_LOGIC_VECTOR(to_unsigned(C_WR15_DEFAULT,C_S_AXI_DATA_WIDTH)); + else + loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + if (slv_reg_wren = '1') then + case loc_addr is + when b"10000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 16 + slv_reg16(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 17 + slv_reg17(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 18 + slv_reg18(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 19 + slv_reg19(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 20 + slv_reg20(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 21 + slv_reg21(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 22 + slv_reg22(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"10111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 23 + slv_reg23(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11000" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 24 + slv_reg24(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11001" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 25 + slv_reg25(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11010" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 26 + slv_reg26(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11011" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 27 + slv_reg27(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11100" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 28 + slv_reg28(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11101" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 29 + slv_reg29(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11110" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 30 + slv_reg30(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when b"11111" => + for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop + if ( S_AXI_WSTRB(byte_index) = '1' ) then + -- Respective byte enables are asserted as per write strobes + -- slave registor 31 + slv_reg31(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8); + end if; + end loop; + when others => + slv_reg16 <= slv_reg16; + slv_reg17 <= slv_reg17; + slv_reg18 <= slv_reg18; + slv_reg19 <= slv_reg19; + slv_reg20 <= slv_reg20; + slv_reg21 <= slv_reg21; + slv_reg22 <= slv_reg22; + slv_reg23 <= slv_reg23; + slv_reg24 <= slv_reg24; + slv_reg25 <= slv_reg25; + slv_reg26 <= slv_reg26; + slv_reg27 <= slv_reg27; + slv_reg28 <= slv_reg28; + slv_reg29 <= slv_reg29; + slv_reg30 <= slv_reg30; + slv_reg31 <= slv_reg31; + end case; + end if; + end if; + end if; + end process; + + -- Implement write response logic generation + -- The write response and response valid signals are asserted by the slave + -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. + -- This marks the acceptance of address and indicates the status of + -- write transaction. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_bvalid <= '0'; + axi_bresp <= "00"; --need to work more on the responses + else + if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then + axi_bvalid <= '1'; + axi_bresp <= "00"; + elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high) + axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high) + end if; + end if; + end if; + end process; + + -- Implement axi_arready generation + -- axi_arready is asserted for one S_AXI_ACLK clock cycle when + -- S_AXI_ARVALID is asserted. axi_awready is + -- de-asserted when reset (active low) is asserted. + -- The read address is also latched when S_AXI_ARVALID is + -- asserted. axi_araddr is reset to zero on reset assertion. + + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_arready <= '0'; + axi_araddr <= (others => '1'); + else + if (axi_arready = '0' and S_AXI_ARVALID = '1') then + -- indicates that the slave has acceped the valid read address + axi_arready <= '1'; + -- Read Address latching + axi_araddr <= S_AXI_ARADDR; + else + axi_arready <= '0'; + end if; + end if; + end if; + end process; + + -- Implement axi_arvalid generation + -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both + -- S_AXI_ARVALID and axi_arready are asserted. The slave registers + -- data are available on the axi_rdata bus at this instance. The + -- assertion of axi_rvalid marks the validity of read data on the + -- bus and axi_rresp indicates the status of read transaction.axi_rvalid + -- is deasserted on reset (active low). axi_rresp and axi_rdata are + -- cleared to zero on reset (active low). + process (S_AXI_ACLK) + begin + if rising_edge(S_AXI_ACLK) then + if S_AXI_ARESETN = '0' then + axi_rvalid <= '0'; + axi_rresp <= "00"; + else + if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then + -- Valid read data is available at the read data bus + axi_rvalid <= '1'; + axi_rresp <= "00"; -- 'OKAY' response + elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then + -- Read data is accepted by the master + axi_rvalid <= '0'; + end if; + end if; + end if; + end process; + + -- Implement memory mapped register select and read logic generation + -- Slave register read enable is asserted when valid address is available + -- and the slave is ready to accept the read address. + slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ; + + process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16r, slv_reg17r, slv_reg18r, slv_reg19r, slv_reg20r, slv_reg21r, slv_reg22r, slv_reg23r, slv_reg24r, slv_reg25r, slv_reg26r, slv_reg27r, slv_reg28r, slv_reg29r, slv_reg30r, slv_reg31r, axi_araddr, S_AXI_ARESETN, slv_reg_rden) + variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0); + begin + -- Address decoding for reading registers + loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB); + case loc_addr is + when b"00000" => + reg_data_out <= slv_reg0; + when b"00001" => + reg_data_out <= slv_reg1; + when b"00010" => + reg_data_out <= slv_reg2; + when b"00011" => + reg_data_out <= slv_reg3; + when b"00100" => + reg_data_out <= slv_reg4; + when b"00101" => + reg_data_out <= slv_reg5; + when b"00110" => + reg_data_out <= slv_reg6; + when b"00111" => + reg_data_out <= slv_reg7; + when b"01000" => + reg_data_out <= slv_reg8; + when b"01001" => + reg_data_out <= slv_reg9; + when b"01010" => + reg_data_out <= slv_reg10; + when b"01011" => + reg_data_out <= slv_reg11; + when b"01100" => + reg_data_out <= slv_reg12; + when b"01101" => + reg_data_out <= slv_reg13; + when b"01110" => + reg_data_out <= slv_reg14; + when b"01111" => + reg_data_out <= slv_reg15; + + when b"10000" => + reg_data_out <= slv_reg16r; + when b"10001" => + reg_data_out <= slv_reg17r; + when b"10010" => + reg_data_out <= slv_reg18r; + when b"10011" => + reg_data_out <= slv_reg19r; + when b"10100" => + reg_data_out <= slv_reg20r; + when b"10101" => + reg_data_out <= slv_reg21r; + when b"10110" => + reg_data_out <= slv_reg22r; + when b"10111" => + reg_data_out <= slv_reg23r; + when b"11000" => + reg_data_out <= slv_reg24r; + when b"11001" => + reg_data_out <= slv_reg25r; + when b"11010" => + reg_data_out <= slv_reg26r; + when b"11011" => + reg_data_out <= slv_reg27r; + when b"11100" => + reg_data_out <= slv_reg28r; + when b"11101" => + reg_data_out <= slv_reg29r; + when b"11110" => + reg_data_out <= slv_reg30r; + when b"11111" => + reg_data_out <= slv_reg31r; + when others => + reg_data_out <= (others => '0'); + end case; + end process; + + -- Output register or memory read data + process( S_AXI_ACLK ) is + begin + if (rising_edge (S_AXI_ACLK)) then + if ( S_AXI_ARESETN = '0' ) then + axi_rdata <= (others => '0'); + else + if (slv_reg_rden = '1') then + -- When there is a valid read address (S_AXI_ARVALID) with + -- acceptance of read address by the slave (axi_arready), + -- output the read dada + -- Read address mux + axi_rdata <= reg_data_out; -- register read data + end if; + end if; + end if; + end process; + + + slv_reg0 <= RR0; + slv_reg1 <= RR1; + slv_reg2 <= RR2; + slv_reg3 <= RR3; + slv_reg4 <= RR4; + slv_reg5 <= RR5; + slv_reg6 <= RR6; + slv_reg7 <= RR7; + slv_reg8 <= RR8; + slv_reg9 <= RR9; + slv_reg10 <= RR10; + slv_reg11 <= RR11; + slv_reg12 <= RR12; + slv_reg13 <= RR13; + slv_reg14 <= RR14; + slv_reg15 <= RR15; + + WR0 <= slv_reg16; + WR1 <= slv_reg17; + WR2 <= slv_reg18; + WR3 <= slv_reg19; + WR4 <= slv_reg20; + WR5 <= slv_reg21; + WR6 <= slv_reg22; + WR7 <= slv_reg23; + WR8 <= slv_reg24; + WR9 <= slv_reg25; + WR10 <= slv_reg26; + WR11 <= slv_reg27; + WR12 <= slv_reg28; + WR13 <= slv_reg29; + WR14 <= slv_reg30; + WR15 <= slv_reg31; + + +WR_readable_Gen: if C_WR_READABLE = true generate + slv_reg16r <= slv_reg16; +WR17_Gen: if C_NUM_WR_REG > 1 generate + slv_reg17r <= slv_reg17; +end generate; +WR18_Gen: if C_NUM_WR_REG > 2 generate + slv_reg18r <= slv_reg18; +end generate; +WR19_Gen: if C_NUM_WR_REG > 3 generate + slv_reg19r <= slv_reg19; +end generate; +WR20_Gen: if C_NUM_WR_REG > 4 generate + slv_reg20r <= slv_reg20; +end generate; +WR21_Gen: if C_NUM_WR_REG > 5 generate + slv_reg21r <= slv_reg21; +end generate; +WR22_Gen: if C_NUM_WR_REG > 6 generate + slv_reg22r <= slv_reg22; +end generate; +WR23_Gen: if C_NUM_WR_REG > 7 generate + slv_reg23r <= slv_reg23; +end generate; +WR24_Gen: if C_NUM_WR_REG > 8 generate + slv_reg24r <= slv_reg24; +end generate; +WR25_Gen: if C_NUM_WR_REG > 9 generate + slv_reg25r <= slv_reg25; +end generate; +WR26_Gen: if C_NUM_WR_REG > 10 generate + slv_reg26r <= slv_reg26; +end generate; +WR27_Gen: if C_NUM_WR_REG > 11 generate + slv_reg27r <= slv_reg27; +end generate; +WR28_Gen: if C_NUM_WR_REG > 12 generate + slv_reg28r <= slv_reg28; +end generate; +WR29_Gen: if C_NUM_WR_REG > 13 generate + slv_reg29r <= slv_reg29; +end generate; +WR30_Gen: if C_NUM_WR_REG > 14 generate + slv_reg30r <= slv_reg30; +end generate; +WR31_Gen: if C_NUM_WR_REG > 15 generate + slv_reg31r <= slv_reg31; +end generate; + +end generate WR_readable_Gen; + +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axi_reg32_1.0/xgui/axi_reg32_v1_0.tcl b/zynqberrydemo3/ip_lib/axi_reg32_1.0/xgui/axi_reg32_v1_0.tcl new file mode 100644 index 0000000..631cdd0 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axi_reg32_1.0/xgui/axi_reg32_v1_0.tcl @@ -0,0 +1,853 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/axi_reg32_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0" -display_name {AXI}] + ipgui::add_param $IPINST -name "C_S_AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S_AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S_AXI_BASEADDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S_AXI_HIGHADDR" -parent ${Page_0} + + #Adding Page + set Read_Registers [ipgui::add_page $IPINST -name "Read Registers" -display_name {Input Registers}] + ipgui::add_param $IPINST -name "C_NUM_RO_REG" -parent ${Read_Registers} -widget comboBox + #Adding Group + set Input_Registe_Alias [ipgui::add_group $IPINST -name "Input Registe Alias" -parent ${Read_Registers} -display_name {Input Register Alias}] + ipgui::add_param $IPINST -name "C_RR0_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR1_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR2_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR3_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR4_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR5_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR6_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR7_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR8_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR9_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR10_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR11_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR12_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR13_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR14_ALIAS" -parent ${Input_Registe_Alias} + ipgui::add_param $IPINST -name "C_RR15_ALIAS" -parent ${Input_Registe_Alias} + + + #Adding Page + set Output_Registers [ipgui::add_page $IPINST -name "Output Registers"] + ipgui::add_param $IPINST -name "C_WR_READABLE" -parent ${Output_Registers} + ipgui::add_param $IPINST -name "C_NUM_WR_REG" -parent ${Output_Registers} -widget comboBox + #Adding Group + set Registers [ipgui::add_group $IPINST -name "Registers" -parent ${Output_Registers} -layout horizontal] + #Adding Group + set Register_Aliases [ipgui::add_group $IPINST -name "Register Aliases" -parent ${Registers} -display_name {Aliases}] + ipgui::add_param $IPINST -name "C_WR0_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR1_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR2_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR3_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR4_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR5_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR6_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR7_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR8_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR9_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR10_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR11_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR12_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR13_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR14_ALIAS" -parent ${Register_Aliases} + ipgui::add_param $IPINST -name "C_WR15_ALIAS" -parent ${Register_Aliases} + + #Adding Group + set Default [ipgui::add_group $IPINST -name "Default" -parent ${Registers}] + ipgui::add_param $IPINST -name "C_WR0_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR1_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR2_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR3_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR4_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR5_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR6_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR7_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR8_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR9_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR10_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR11_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR12_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR13_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR14_DEFAULT" -parent ${Default} + ipgui::add_param $IPINST -name "C_WR15_DEFAULT" -parent ${Default} + + + + +} + +proc update_PARAM_VALUE.C_NUM_RO_REG { PARAM_VALUE.C_NUM_RO_REG } { + # Procedure called to update C_NUM_RO_REG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_NUM_RO_REG { PARAM_VALUE.C_NUM_RO_REG } { + # Procedure called to validate C_NUM_RO_REG + return true +} + +proc update_PARAM_VALUE.C_NUM_WR_REG { PARAM_VALUE.C_NUM_WR_REG } { + # Procedure called to update C_NUM_WR_REG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_NUM_WR_REG { PARAM_VALUE.C_NUM_WR_REG } { + # Procedure called to validate C_NUM_WR_REG + return true +} + +proc update_PARAM_VALUE.C_RR0_ALIAS { PARAM_VALUE.C_RR0_ALIAS } { + # Procedure called to update C_RR0_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR0_ALIAS { PARAM_VALUE.C_RR0_ALIAS } { + # Procedure called to validate C_RR0_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR10_ALIAS { PARAM_VALUE.C_RR10_ALIAS } { + # Procedure called to update C_RR10_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR10_ALIAS { PARAM_VALUE.C_RR10_ALIAS } { + # Procedure called to validate C_RR10_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR11_ALIAS { PARAM_VALUE.C_RR11_ALIAS } { + # Procedure called to update C_RR11_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR11_ALIAS { PARAM_VALUE.C_RR11_ALIAS } { + # Procedure called to validate C_RR11_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR12_ALIAS { PARAM_VALUE.C_RR12_ALIAS } { + # Procedure called to update C_RR12_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR12_ALIAS { PARAM_VALUE.C_RR12_ALIAS } { + # Procedure called to validate C_RR12_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR13_ALIAS { PARAM_VALUE.C_RR13_ALIAS } { + # Procedure called to update C_RR13_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR13_ALIAS { PARAM_VALUE.C_RR13_ALIAS } { + # Procedure called to validate C_RR13_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR14_ALIAS { PARAM_VALUE.C_RR14_ALIAS } { + # Procedure called to update C_RR14_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR14_ALIAS { PARAM_VALUE.C_RR14_ALIAS } { + # Procedure called to validate C_RR14_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR15_ALIAS { PARAM_VALUE.C_RR15_ALIAS } { + # Procedure called to update C_RR15_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR15_ALIAS { PARAM_VALUE.C_RR15_ALIAS } { + # Procedure called to validate C_RR15_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR1_ALIAS { PARAM_VALUE.C_RR1_ALIAS } { + # Procedure called to update C_RR1_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR1_ALIAS { PARAM_VALUE.C_RR1_ALIAS } { + # Procedure called to validate C_RR1_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR2_ALIAS { PARAM_VALUE.C_RR2_ALIAS } { + # Procedure called to update C_RR2_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR2_ALIAS { PARAM_VALUE.C_RR2_ALIAS } { + # Procedure called to validate C_RR2_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR3_ALIAS { PARAM_VALUE.C_RR3_ALIAS } { + # Procedure called to update C_RR3_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR3_ALIAS { PARAM_VALUE.C_RR3_ALIAS } { + # Procedure called to validate C_RR3_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR4_ALIAS { PARAM_VALUE.C_RR4_ALIAS } { + # Procedure called to update C_RR4_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR4_ALIAS { PARAM_VALUE.C_RR4_ALIAS } { + # Procedure called to validate C_RR4_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR5_ALIAS { PARAM_VALUE.C_RR5_ALIAS } { + # Procedure called to update C_RR5_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR5_ALIAS { PARAM_VALUE.C_RR5_ALIAS } { + # Procedure called to validate C_RR5_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR6_ALIAS { PARAM_VALUE.C_RR6_ALIAS } { + # Procedure called to update C_RR6_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR6_ALIAS { PARAM_VALUE.C_RR6_ALIAS } { + # Procedure called to validate C_RR6_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR7_ALIAS { PARAM_VALUE.C_RR7_ALIAS } { + # Procedure called to update C_RR7_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR7_ALIAS { PARAM_VALUE.C_RR7_ALIAS } { + # Procedure called to validate C_RR7_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR8_ALIAS { PARAM_VALUE.C_RR8_ALIAS } { + # Procedure called to update C_RR8_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR8_ALIAS { PARAM_VALUE.C_RR8_ALIAS } { + # Procedure called to validate C_RR8_ALIAS + return true +} + +proc update_PARAM_VALUE.C_RR9_ALIAS { PARAM_VALUE.C_RR9_ALIAS } { + # Procedure called to update C_RR9_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RR9_ALIAS { PARAM_VALUE.C_RR9_ALIAS } { + # Procedure called to validate C_RR9_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR0_ALIAS { PARAM_VALUE.C_WR0_ALIAS } { + # Procedure called to update C_WR0_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR0_ALIAS { PARAM_VALUE.C_WR0_ALIAS } { + # Procedure called to validate C_WR0_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR0_DEFAULT { PARAM_VALUE.C_WR0_DEFAULT } { + # Procedure called to update C_WR0_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR0_DEFAULT { PARAM_VALUE.C_WR0_DEFAULT } { + # Procedure called to validate C_WR0_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR10_ALIAS { PARAM_VALUE.C_WR10_ALIAS } { + # Procedure called to update C_WR10_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR10_ALIAS { PARAM_VALUE.C_WR10_ALIAS } { + # Procedure called to validate C_WR10_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR10_DEFAULT { PARAM_VALUE.C_WR10_DEFAULT } { + # Procedure called to update C_WR10_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR10_DEFAULT { PARAM_VALUE.C_WR10_DEFAULT } { + # Procedure called to validate C_WR10_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR11_ALIAS { PARAM_VALUE.C_WR11_ALIAS } { + # Procedure called to update C_WR11_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR11_ALIAS { PARAM_VALUE.C_WR11_ALIAS } { + # Procedure called to validate C_WR11_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR11_DEFAULT { PARAM_VALUE.C_WR11_DEFAULT } { + # Procedure called to update C_WR11_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR11_DEFAULT { PARAM_VALUE.C_WR11_DEFAULT } { + # Procedure called to validate C_WR11_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR12_ALIAS { PARAM_VALUE.C_WR12_ALIAS } { + # Procedure called to update C_WR12_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR12_ALIAS { PARAM_VALUE.C_WR12_ALIAS } { + # Procedure called to validate C_WR12_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR12_DEFAULT { PARAM_VALUE.C_WR12_DEFAULT } { + # Procedure called to update C_WR12_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR12_DEFAULT { PARAM_VALUE.C_WR12_DEFAULT } { + # Procedure called to validate C_WR12_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR13_ALIAS { PARAM_VALUE.C_WR13_ALIAS } { + # Procedure called to update C_WR13_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR13_ALIAS { PARAM_VALUE.C_WR13_ALIAS } { + # Procedure called to validate C_WR13_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR13_DEFAULT { PARAM_VALUE.C_WR13_DEFAULT } { + # Procedure called to update C_WR13_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR13_DEFAULT { PARAM_VALUE.C_WR13_DEFAULT } { + # Procedure called to validate C_WR13_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR14_ALIAS { PARAM_VALUE.C_WR14_ALIAS } { + # Procedure called to update C_WR14_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR14_ALIAS { PARAM_VALUE.C_WR14_ALIAS } { + # Procedure called to validate C_WR14_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR14_DEFAULT { PARAM_VALUE.C_WR14_DEFAULT } { + # Procedure called to update C_WR14_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR14_DEFAULT { PARAM_VALUE.C_WR14_DEFAULT } { + # Procedure called to validate C_WR14_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR15_ALIAS { PARAM_VALUE.C_WR15_ALIAS } { + # Procedure called to update C_WR15_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR15_ALIAS { PARAM_VALUE.C_WR15_ALIAS } { + # Procedure called to validate C_WR15_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR15_DEFAULT { PARAM_VALUE.C_WR15_DEFAULT } { + # Procedure called to update C_WR15_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR15_DEFAULT { PARAM_VALUE.C_WR15_DEFAULT } { + # Procedure called to validate C_WR15_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR1_ALIAS { PARAM_VALUE.C_WR1_ALIAS } { + # Procedure called to update C_WR1_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR1_ALIAS { PARAM_VALUE.C_WR1_ALIAS } { + # Procedure called to validate C_WR1_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR1_DEFAULT { PARAM_VALUE.C_WR1_DEFAULT } { + # Procedure called to update C_WR1_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR1_DEFAULT { PARAM_VALUE.C_WR1_DEFAULT } { + # Procedure called to validate C_WR1_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR2_ALIAS { PARAM_VALUE.C_WR2_ALIAS } { + # Procedure called to update C_WR2_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR2_ALIAS { PARAM_VALUE.C_WR2_ALIAS } { + # Procedure called to validate C_WR2_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR2_DEFAULT { PARAM_VALUE.C_WR2_DEFAULT } { + # Procedure called to update C_WR2_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR2_DEFAULT { PARAM_VALUE.C_WR2_DEFAULT } { + # Procedure called to validate C_WR2_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR3_ALIAS { PARAM_VALUE.C_WR3_ALIAS } { + # Procedure called to update C_WR3_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR3_ALIAS { PARAM_VALUE.C_WR3_ALIAS } { + # Procedure called to validate C_WR3_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR3_DEFAULT { PARAM_VALUE.C_WR3_DEFAULT } { + # Procedure called to update C_WR3_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR3_DEFAULT { PARAM_VALUE.C_WR3_DEFAULT } { + # Procedure called to validate C_WR3_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR4_ALIAS { PARAM_VALUE.C_WR4_ALIAS } { + # Procedure called to update C_WR4_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR4_ALIAS { PARAM_VALUE.C_WR4_ALIAS } { + # Procedure called to validate C_WR4_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR4_DEFAULT { PARAM_VALUE.C_WR4_DEFAULT } { + # Procedure called to update C_WR4_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR4_DEFAULT { PARAM_VALUE.C_WR4_DEFAULT } { + # Procedure called to validate C_WR4_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR5_ALIAS { PARAM_VALUE.C_WR5_ALIAS } { + # Procedure called to update C_WR5_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR5_ALIAS { PARAM_VALUE.C_WR5_ALIAS } { + # Procedure called to validate C_WR5_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR5_DEFAULT { PARAM_VALUE.C_WR5_DEFAULT } { + # Procedure called to update C_WR5_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR5_DEFAULT { PARAM_VALUE.C_WR5_DEFAULT } { + # Procedure called to validate C_WR5_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR6_ALIAS { PARAM_VALUE.C_WR6_ALIAS } { + # Procedure called to update C_WR6_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR6_ALIAS { PARAM_VALUE.C_WR6_ALIAS } { + # Procedure called to validate C_WR6_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR6_DEFAULT { PARAM_VALUE.C_WR6_DEFAULT } { + # Procedure called to update C_WR6_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR6_DEFAULT { PARAM_VALUE.C_WR6_DEFAULT } { + # Procedure called to validate C_WR6_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR7_ALIAS { PARAM_VALUE.C_WR7_ALIAS } { + # Procedure called to update C_WR7_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR7_ALIAS { PARAM_VALUE.C_WR7_ALIAS } { + # Procedure called to validate C_WR7_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR7_DEFAULT { PARAM_VALUE.C_WR7_DEFAULT } { + # Procedure called to update C_WR7_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR7_DEFAULT { PARAM_VALUE.C_WR7_DEFAULT } { + # Procedure called to validate C_WR7_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR8_ALIAS { PARAM_VALUE.C_WR8_ALIAS } { + # Procedure called to update C_WR8_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR8_ALIAS { PARAM_VALUE.C_WR8_ALIAS } { + # Procedure called to validate C_WR8_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR8_DEFAULT { PARAM_VALUE.C_WR8_DEFAULT } { + # Procedure called to update C_WR8_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR8_DEFAULT { PARAM_VALUE.C_WR8_DEFAULT } { + # Procedure called to validate C_WR8_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR9_ALIAS { PARAM_VALUE.C_WR9_ALIAS } { + # Procedure called to update C_WR9_ALIAS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR9_ALIAS { PARAM_VALUE.C_WR9_ALIAS } { + # Procedure called to validate C_WR9_ALIAS + return true +} + +proc update_PARAM_VALUE.C_WR9_DEFAULT { PARAM_VALUE.C_WR9_DEFAULT } { + # Procedure called to update C_WR9_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR9_DEFAULT { PARAM_VALUE.C_WR9_DEFAULT } { + # Procedure called to validate C_WR9_DEFAULT + return true +} + +proc update_PARAM_VALUE.C_WR_READABLE { PARAM_VALUE.C_WR_READABLE } { + # Procedure called to update C_WR_READABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WR_READABLE { PARAM_VALUE.C_WR_READABLE } { + # Procedure called to validate C_WR_READABLE + return true +} + +proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to validate C_S_AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S_AXI_BASEADDR { PARAM_VALUE.C_S_AXI_BASEADDR } { + # Procedure called to update C_S_AXI_BASEADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_BASEADDR { PARAM_VALUE.C_S_AXI_BASEADDR } { + # Procedure called to validate C_S_AXI_BASEADDR + return true +} + +proc update_PARAM_VALUE.C_S_AXI_HIGHADDR { PARAM_VALUE.C_S_AXI_HIGHADDR } { + # Procedure called to update C_S_AXI_HIGHADDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_HIGHADDR { PARAM_VALUE.C_S_AXI_HIGHADDR } { + # Procedure called to validate C_S_AXI_HIGHADDR + return true +} + + +proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_REG_WIDTH { MODELPARAM_VALUE.C_REG_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + # WARNING: There is no corresponding user parameter named "C_REG_WIDTH". Setting updated value from the model parameter. +set_property value 32 ${MODELPARAM_VALUE.C_REG_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_NUM_RO_REG { MODELPARAM_VALUE.C_NUM_RO_REG PARAM_VALUE.C_NUM_RO_REG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_NUM_RO_REG}] ${MODELPARAM_VALUE.C_NUM_RO_REG} +} + +proc update_MODELPARAM_VALUE.C_NUM_WR_REG { MODELPARAM_VALUE.C_NUM_WR_REG PARAM_VALUE.C_NUM_WR_REG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_NUM_WR_REG}] ${MODELPARAM_VALUE.C_NUM_WR_REG} +} + +proc update_MODELPARAM_VALUE.C_WR_READABLE { MODELPARAM_VALUE.C_WR_READABLE PARAM_VALUE.C_WR_READABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR_READABLE}] ${MODELPARAM_VALUE.C_WR_READABLE} +} + +proc update_MODELPARAM_VALUE.C_RR0_ALIAS { MODELPARAM_VALUE.C_RR0_ALIAS PARAM_VALUE.C_RR0_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR0_ALIAS}] ${MODELPARAM_VALUE.C_RR0_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR1_ALIAS { MODELPARAM_VALUE.C_RR1_ALIAS PARAM_VALUE.C_RR1_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR1_ALIAS}] ${MODELPARAM_VALUE.C_RR1_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR0_ALIAS { MODELPARAM_VALUE.C_WR0_ALIAS PARAM_VALUE.C_WR0_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR0_ALIAS}] ${MODELPARAM_VALUE.C_WR0_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR1_ALIAS { MODELPARAM_VALUE.C_WR1_ALIAS PARAM_VALUE.C_WR1_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR1_ALIAS}] ${MODELPARAM_VALUE.C_WR1_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR2_ALIAS { MODELPARAM_VALUE.C_RR2_ALIAS PARAM_VALUE.C_RR2_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR2_ALIAS}] ${MODELPARAM_VALUE.C_RR2_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR3_ALIAS { MODELPARAM_VALUE.C_RR3_ALIAS PARAM_VALUE.C_RR3_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR3_ALIAS}] ${MODELPARAM_VALUE.C_RR3_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR4_ALIAS { MODELPARAM_VALUE.C_RR4_ALIAS PARAM_VALUE.C_RR4_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR4_ALIAS}] ${MODELPARAM_VALUE.C_RR4_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR5_ALIAS { MODELPARAM_VALUE.C_RR5_ALIAS PARAM_VALUE.C_RR5_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR5_ALIAS}] ${MODELPARAM_VALUE.C_RR5_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR6_ALIAS { MODELPARAM_VALUE.C_RR6_ALIAS PARAM_VALUE.C_RR6_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR6_ALIAS}] ${MODELPARAM_VALUE.C_RR6_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR7_ALIAS { MODELPARAM_VALUE.C_RR7_ALIAS PARAM_VALUE.C_RR7_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR7_ALIAS}] ${MODELPARAM_VALUE.C_RR7_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR8_ALIAS { MODELPARAM_VALUE.C_RR8_ALIAS PARAM_VALUE.C_RR8_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR8_ALIAS}] ${MODELPARAM_VALUE.C_RR8_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR9_ALIAS { MODELPARAM_VALUE.C_RR9_ALIAS PARAM_VALUE.C_RR9_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR9_ALIAS}] ${MODELPARAM_VALUE.C_RR9_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR10_ALIAS { MODELPARAM_VALUE.C_RR10_ALIAS PARAM_VALUE.C_RR10_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR10_ALIAS}] ${MODELPARAM_VALUE.C_RR10_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR11_ALIAS { MODELPARAM_VALUE.C_RR11_ALIAS PARAM_VALUE.C_RR11_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR11_ALIAS}] ${MODELPARAM_VALUE.C_RR11_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR12_ALIAS { MODELPARAM_VALUE.C_RR12_ALIAS PARAM_VALUE.C_RR12_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR12_ALIAS}] ${MODELPARAM_VALUE.C_RR12_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR13_ALIAS { MODELPARAM_VALUE.C_RR13_ALIAS PARAM_VALUE.C_RR13_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR13_ALIAS}] ${MODELPARAM_VALUE.C_RR13_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR14_ALIAS { MODELPARAM_VALUE.C_RR14_ALIAS PARAM_VALUE.C_RR14_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR14_ALIAS}] ${MODELPARAM_VALUE.C_RR14_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_RR15_ALIAS { MODELPARAM_VALUE.C_RR15_ALIAS PARAM_VALUE.C_RR15_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RR15_ALIAS}] ${MODELPARAM_VALUE.C_RR15_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR2_ALIAS { MODELPARAM_VALUE.C_WR2_ALIAS PARAM_VALUE.C_WR2_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR2_ALIAS}] ${MODELPARAM_VALUE.C_WR2_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR3_ALIAS { MODELPARAM_VALUE.C_WR3_ALIAS PARAM_VALUE.C_WR3_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR3_ALIAS}] ${MODELPARAM_VALUE.C_WR3_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR4_ALIAS { MODELPARAM_VALUE.C_WR4_ALIAS PARAM_VALUE.C_WR4_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR4_ALIAS}] ${MODELPARAM_VALUE.C_WR4_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR5_ALIAS { MODELPARAM_VALUE.C_WR5_ALIAS PARAM_VALUE.C_WR5_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR5_ALIAS}] ${MODELPARAM_VALUE.C_WR5_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR6_ALIAS { MODELPARAM_VALUE.C_WR6_ALIAS PARAM_VALUE.C_WR6_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR6_ALIAS}] ${MODELPARAM_VALUE.C_WR6_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR7_ALIAS { MODELPARAM_VALUE.C_WR7_ALIAS PARAM_VALUE.C_WR7_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR7_ALIAS}] ${MODELPARAM_VALUE.C_WR7_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR8_ALIAS { MODELPARAM_VALUE.C_WR8_ALIAS PARAM_VALUE.C_WR8_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR8_ALIAS}] ${MODELPARAM_VALUE.C_WR8_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR9_ALIAS { MODELPARAM_VALUE.C_WR9_ALIAS PARAM_VALUE.C_WR9_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR9_ALIAS}] ${MODELPARAM_VALUE.C_WR9_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR10_ALIAS { MODELPARAM_VALUE.C_WR10_ALIAS PARAM_VALUE.C_WR10_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR10_ALIAS}] ${MODELPARAM_VALUE.C_WR10_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR11_ALIAS { MODELPARAM_VALUE.C_WR11_ALIAS PARAM_VALUE.C_WR11_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR11_ALIAS}] ${MODELPARAM_VALUE.C_WR11_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR12_ALIAS { MODELPARAM_VALUE.C_WR12_ALIAS PARAM_VALUE.C_WR12_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR12_ALIAS}] ${MODELPARAM_VALUE.C_WR12_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR13_ALIAS { MODELPARAM_VALUE.C_WR13_ALIAS PARAM_VALUE.C_WR13_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR13_ALIAS}] ${MODELPARAM_VALUE.C_WR13_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR14_ALIAS { MODELPARAM_VALUE.C_WR14_ALIAS PARAM_VALUE.C_WR14_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR14_ALIAS}] ${MODELPARAM_VALUE.C_WR14_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR15_ALIAS { MODELPARAM_VALUE.C_WR15_ALIAS PARAM_VALUE.C_WR15_ALIAS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR15_ALIAS}] ${MODELPARAM_VALUE.C_WR15_ALIAS} +} + +proc update_MODELPARAM_VALUE.C_WR0_DEFAULT { MODELPARAM_VALUE.C_WR0_DEFAULT PARAM_VALUE.C_WR0_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR0_DEFAULT}] ${MODELPARAM_VALUE.C_WR0_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR1_DEFAULT { MODELPARAM_VALUE.C_WR1_DEFAULT PARAM_VALUE.C_WR1_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR1_DEFAULT}] ${MODELPARAM_VALUE.C_WR1_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR2_DEFAULT { MODELPARAM_VALUE.C_WR2_DEFAULT PARAM_VALUE.C_WR2_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR2_DEFAULT}] ${MODELPARAM_VALUE.C_WR2_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR3_DEFAULT { MODELPARAM_VALUE.C_WR3_DEFAULT PARAM_VALUE.C_WR3_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR3_DEFAULT}] ${MODELPARAM_VALUE.C_WR3_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR4_DEFAULT { MODELPARAM_VALUE.C_WR4_DEFAULT PARAM_VALUE.C_WR4_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR4_DEFAULT}] ${MODELPARAM_VALUE.C_WR4_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR5_DEFAULT { MODELPARAM_VALUE.C_WR5_DEFAULT PARAM_VALUE.C_WR5_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR5_DEFAULT}] ${MODELPARAM_VALUE.C_WR5_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR6_DEFAULT { MODELPARAM_VALUE.C_WR6_DEFAULT PARAM_VALUE.C_WR6_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR6_DEFAULT}] ${MODELPARAM_VALUE.C_WR6_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR7_DEFAULT { MODELPARAM_VALUE.C_WR7_DEFAULT PARAM_VALUE.C_WR7_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR7_DEFAULT}] ${MODELPARAM_VALUE.C_WR7_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR8_DEFAULT { MODELPARAM_VALUE.C_WR8_DEFAULT PARAM_VALUE.C_WR8_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR8_DEFAULT}] ${MODELPARAM_VALUE.C_WR8_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR9_DEFAULT { MODELPARAM_VALUE.C_WR9_DEFAULT PARAM_VALUE.C_WR9_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR9_DEFAULT}] ${MODELPARAM_VALUE.C_WR9_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR10_DEFAULT { MODELPARAM_VALUE.C_WR10_DEFAULT PARAM_VALUE.C_WR10_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR10_DEFAULT}] ${MODELPARAM_VALUE.C_WR10_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR11_DEFAULT { MODELPARAM_VALUE.C_WR11_DEFAULT PARAM_VALUE.C_WR11_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR11_DEFAULT}] ${MODELPARAM_VALUE.C_WR11_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR12_DEFAULT { MODELPARAM_VALUE.C_WR12_DEFAULT PARAM_VALUE.C_WR12_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR12_DEFAULT}] ${MODELPARAM_VALUE.C_WR12_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR13_DEFAULT { MODELPARAM_VALUE.C_WR13_DEFAULT PARAM_VALUE.C_WR13_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR13_DEFAULT}] ${MODELPARAM_VALUE.C_WR13_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR14_DEFAULT { MODELPARAM_VALUE.C_WR14_DEFAULT PARAM_VALUE.C_WR14_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR14_DEFAULT}] ${MODELPARAM_VALUE.C_WR14_DEFAULT} +} + +proc update_MODELPARAM_VALUE.C_WR15_DEFAULT { MODELPARAM_VALUE.C_WR15_DEFAULT PARAM_VALUE.C_WR15_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WR15_DEFAULT}] ${MODELPARAM_VALUE.C_WR15_DEFAULT} +} + diff --git a/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/component.xml b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/component.xml new file mode 100644 index 0000000..3affb02 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/component.xml @@ -0,0 +1,369 @@ + + + trenz.biz + user + axis_audio_pwm + 1.0 + + + S00_AXIS + + + + + + + TDATA + + + s00_axis_tdata + + + + + TVALID + + + s00_axis_tvalid + + + + + TREADY + + + s00_axis_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + + + S00_AXIS_RST + + + + + + + RST + + + s00_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S00_AXIS_CLK + + + + + + + CLK + + + s00_axis_aclk + + + + + + ASSOCIATED_BUSIF + S00_AXIS + + + ASSOCIATED_RESET + s00_axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_audio_pwm_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + e37e5f7b + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_audio_pwm_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + e37e5f7b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 85d97987 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + pwm_l_out + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + pwm_r_out + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tdata + + in + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s00_axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_SYS_FREQ + C Sys Freq + 150000000 + + + C_PWM_FREQ + C Pwm Freq + 100000 + + + + + + choice_list_6fc15197 + 32 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd + vhdlSource + + + hdl/axis_audio_pwm_v1_0.vhd + vhdlSource + CHECKSUM_b42f8d78 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/axis_audio_pwm_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_audio_pwm_v1_0.tcl + tclSource + CHECKSUM_8d217f22 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + AXI4-Stream Audio PWM v1.0 + + + Component_Name + axis_audio_pwm_v1_0 + + + C_SYS_FREQ + Clock Frequency + 150000000 + + + C_PWM_FREQ + PWM Frequency + 100000 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /AXI_Peripheral + /Digital_Signal_Processing/Modulation + /Embedded_Processing/AXI_Peripheral/Low_Speed_Peripheral + + AXI4-Stream Audio PWM v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 4 + + xilinx.com:user:axis_audio_pwm:1.0 + + 2016-04-01T12:30:24Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_audio_pwm_1.0 + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_audio_pwm_1.0 + + + + 2015.4.2 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0.vhd b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0.vhd new file mode 100644 index 0000000..0d849c6 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0.vhd @@ -0,0 +1,86 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity axis_audio_pwm_v1_0 is +generic ( + C_SYS_FREQ : INTEGER := 150000000; + C_PWM_FREQ : INTEGER := 100000 -- Usually from 50 to 100 kHz +); +port ( + -- PWM Outs + pwm_l_out : out STD_LOGIC; + pwm_r_out : out STD_LOGIC; + -- Ports of Axi Slave Bus Interface S00_AXIS + s00_axis_aclk : in STD_LOGIC; + s00_axis_aresetn : in STD_LOGIC; + s00_axis_tready : out STD_LOGIC; + s00_axis_tdata : in STD_LOGIC_VECTOR(31 downto 0); + s00_axis_tvalid : in STD_LOGIC +); +end axis_audio_pwm_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_audio_pwm_v1_0 is +---------------------------------------------------------------------------------- +constant C_CNT_MAX : INTEGER := 32767; +constant C_CNT_MIN : INTEGER := -32767; +constant C_STEP : INTEGER := 131072 / (C_SYS_FREQ/C_PWM_FREQ); +---------------------------------------------------------------------------------- +signal left_ch_val : SIGNED(15 downto 0); -- Data latches +signal right_ch_val : SIGNED(15 downto 0); +signal pwm_cnt : SIGNED(15 downto 0); -- Reference signal +signal pwm_cnt_dir : STD_LOGIC; -- Saw direction +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +s00_axis_tready <= '1'; -- Always ready +-- Data latch +process(s00_axis_aclk) +begin + if(s00_axis_aclk = '1' and s00_axis_aclk'event)then + if(s00_axis_tvalid = '1')then + left_ch_val <= SIGNED(s00_axis_tdata(15 downto 0)); + right_ch_val <= SIGNED(s00_axis_tdata(31 downto 16)); + end if; + end if; +end process; + +-- PWM Coding +process(s00_axis_aclk) +begin + if(s00_axis_aclk = '1' and s00_axis_aclk'event)then + -- Triangle reference signal + if(pwm_cnt_dir = '0')then -- Up count + if(pwm_cnt >= TO_SIGNED((C_CNT_MAX - C_STEP),16))then + pwm_cnt_dir <= '1'; + pwm_cnt <= pwm_cnt - C_STEP; + else + pwm_cnt <= pwm_cnt + C_STEP; + end if; + else -- Down count + if(pwm_cnt <= TO_SIGNED((C_CNT_MIN + C_STEP),16))then + pwm_cnt_dir <= '0'; + pwm_cnt <= pwm_cnt + C_STEP; + else + pwm_cnt <= pwm_cnt - C_STEP; + end if; + end if; + -- Comparators + if(left_ch_val > pwm_cnt)then + pwm_l_out <= '1'; + else + pwm_l_out <= '0'; + end if; + if(right_ch_val > pwm_cnt)then + pwm_r_out <= '1'; + else + pwm_r_out <= '0'; + end if; + end if; +end process; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd new file mode 100644 index 0000000..227c142 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/hdl/axis_audio_pwm_v1_0_S00_AXIS.vhd @@ -0,0 +1,177 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axis_audio_pwm_v1_0_S00_AXIS is + generic ( + -- Users to add parameters here + + -- User parameters ends + -- Do not modify the parameters beyond this line + + -- AXI4Stream sink: Data Width + C_S_AXIS_TDATA_WIDTH : integer := 32 + ); + port ( + -- Users to add ports here + + -- User ports ends + -- Do not modify the ports beyond this line + + -- AXI4Stream sink: Clock + S_AXIS_ACLK : in std_logic; + -- AXI4Stream sink: Reset + S_AXIS_ARESETN : in std_logic; + -- Ready to accept data in + S_AXIS_TREADY : out std_logic; + -- Data in + S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0); + -- Byte qualifier + S_AXIS_TSTRB : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0); + -- Indicates boundary of last packet + S_AXIS_TLAST : in std_logic; + -- Data is in valid + S_AXIS_TVALID : in std_logic + ); +end axis_audio_pwm_v1_0_S00_AXIS; + +architecture arch_imp of axis_audio_pwm_v1_0_S00_AXIS is + -- function called clogb2 that returns an integer which has the + -- value of the ceiling of the log base 2. + function clogb2 (bit_depth : integer) return integer is + variable depth : integer := bit_depth; + begin + if (depth = 0) then + return(0); + else + for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers + if(depth <= 1) then + return(clogb2); + else + depth := depth / 2; + end if; + end loop; + end if; + end; + + -- Total number of input data. + constant NUMBER_OF_INPUT_WORDS : integer := 8; + -- bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO. + constant bit_num : integer := clogb2(NUMBER_OF_INPUT_WORDS-1); + -- Define the states of state machine + -- The control state machine oversees the writing of input streaming data to the FIFO, + -- and outputs the streaming data from the FIFO + type state is ( IDLE, -- This is the initial/idle state + WRITE_FIFO); -- In this state FIFO is written with the + -- input stream data S_AXIS_TDATA + signal axis_tready : std_logic; + -- State variable + signal mst_exec_state : state; + -- FIFO implementation signals + signal byte_index : integer; + -- FIFO write enable + signal fifo_wren : std_logic; + -- FIFO full flag + signal fifo_full_flag : std_logic; + -- FIFO write pointer + signal write_pointer : integer range 0 to bit_num-1 ; + -- sink has accepted all the streaming data and stored in FIFO + signal writes_done : std_logic; + + type BYTE_FIFO_TYPE is array (0 to (NUMBER_OF_INPUT_WORDS-1)) of std_logic_vector(((C_S_AXIS_TDATA_WIDTH/4)-1)downto 0); +begin + -- I/O Connections assignments + + S_AXIS_TREADY <= axis_tready; + -- Control state machine implementation + process(S_AXIS_ACLK) + begin + if (rising_edge (S_AXIS_ACLK)) then + if(S_AXIS_ARESETN = '0') then + -- Synchronous reset (active low) + mst_exec_state <= IDLE; + else + case (mst_exec_state) is + when IDLE => + -- The sink starts accepting tdata when + -- there tvalid is asserted to mark the + -- presence of valid streaming data + if (S_AXIS_TVALID = '1')then + mst_exec_state <= WRITE_FIFO; + else + mst_exec_state <= IDLE; + end if; + + when WRITE_FIFO => + -- When the sink has accepted all the streaming input data, + -- the interface swiches functionality to a streaming master + if (writes_done = '1') then + mst_exec_state <= IDLE; + else + -- The sink accepts and stores tdata + -- into FIFO + mst_exec_state <= WRITE_FIFO; + end if; + + when others => + mst_exec_state <= IDLE; + + end case; + end if; + end if; + end process; + -- AXI Streaming Sink + -- + -- The example design sink is always ready to accept the S_AXIS_TDATA until + -- the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words. + axis_tready <= '1' when ((mst_exec_state = WRITE_FIFO) and (write_pointer <= NUMBER_OF_INPUT_WORDS-1)) else '0'; + + process(S_AXIS_ACLK) + begin + if (rising_edge (S_AXIS_ACLK)) then + if(S_AXIS_ARESETN = '0') then + write_pointer <= 0; + writes_done <= '0'; + else + if (write_pointer <= NUMBER_OF_INPUT_WORDS-1) then + if (fifo_wren = '1') then + -- write pointer is incremented after every write to the FIFO + -- when FIFO write signal is enabled. + write_pointer <= write_pointer + 1; + writes_done <= '0'; + end if; + if ((write_pointer = NUMBER_OF_INPUT_WORDS-1) or S_AXIS_TLAST = '1') then + -- reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data + -- has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage). + writes_done <= '1'; + end if; + end if; + end if; + end if; + end process; + + -- FIFO write enable generation + fifo_wren <= S_AXIS_TVALID and axis_tready; + + -- FIFO Implementation + FIFO_GEN: for byte_index in 0 to (C_S_AXIS_TDATA_WIDTH/8-1) generate + + signal stream_data_fifo : BYTE_FIFO_TYPE; + begin + -- Streaming input data is stored in FIFO + process(S_AXIS_ACLK) + begin + if (rising_edge (S_AXIS_ACLK)) then + if (fifo_wren = '1') then + stream_data_fifo(write_pointer) <= S_AXIS_TDATA((byte_index*8+7) downto (byte_index*8)); + end if; + end if; + end process; + + end generate FIFO_GEN; + + -- Add user logic here + + -- User logic ends + +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/xgui/axis_audio_pwm_v1_0.tcl b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/xgui/axis_audio_pwm_v1_0.tcl new file mode 100644 index 0000000..3fa319f --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_audio_pwm_1.0/xgui/axis_audio_pwm_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_PWM_FREQ" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_SYS_FREQ" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_PWM_FREQ { PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to update C_PWM_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_PWM_FREQ { PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to validate C_PWM_FREQ + return true +} + +proc update_PARAM_VALUE.C_SYS_FREQ { PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to update C_SYS_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_SYS_FREQ { PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to validate C_SYS_FREQ + return true +} + + +proc update_MODELPARAM_VALUE.C_SYS_FREQ { MODELPARAM_VALUE.C_SYS_FREQ PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_SYS_FREQ}] ${MODELPARAM_VALUE.C_SYS_FREQ} +} + +proc update_MODELPARAM_VALUE.C_PWM_FREQ { MODELPARAM_VALUE.C_PWM_FREQ PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_PWM_FREQ}] ${MODELPARAM_VALUE.C_PWM_FREQ} +} + diff --git a/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/component.xml b/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/component.xml new file mode 100644 index 0000000..e02e2b6 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/component.xml @@ -0,0 +1,515 @@ + + + trenz.biz + user + axis_fb_conv + 1.0 + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TUSER + + + s_axis_tuser + + + + + + WIZ.DATA_WIDTH + 32 + + + + + video_out + + + + + + + TDATA + + + video_out_tdata + + + + + TLAST + + + video_out_tlast + + + + + TVALID + + + video_out_tvalid + + + + + TREADY + + + video_out_tready + + + + + TUSER + + + video_out_tuser + + + + + + WIZ.DATA_WIDTH + 32 + + + + + S_AXIS_RST + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + S_AXIS_CLK + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS:video_out + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_fb_conv_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + c2b53453 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_fb_conv_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + c2b53453 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e24204be + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tdata + + out + + 23 + 0 + + + + std_logic_vector + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tlast + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tuser + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tvalid + + out + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + video_out_tready + + in + + + std_logic + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_FB_MODE + C Fb Mode + 1 + + + + false + + + + + + + + + choices_0 + 32 + + + choices_1 + 32 + + + choices_2 + 0 + 1 + + + + + xilinx_vhdlsynthesis_view_fileset + + src/axis_fb_conv_v1_0.vhd + vhdlSource + CHECKSUM_6e7698d9 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + src/axis_fb_conv_v1_0.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_fb_conv_v1_0.tcl + tclSource + XGUI_VERSION_2 + CHECKSUM_bc827756 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + axis_fb_conv_v1.0 + + + Component_Name + axis_fb_conv_v1_0 + + + C_FB_MODE + Framebuffer Mode + 1 + + + + false + + + + + + + + + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + virtexu + kintexu + + + AXI_Peripheral + + axis_fb_conv_v1.0 + Trenz Electronic GmbH + 5 + 2015-06-04T13:44:40Z + + b:/cores/2014.4/ip/axis_fb_conv_1.0 + + + + 2014.4 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/src/axis_fb_conv_v1_0.vhd b/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/src/axis_fb_conv_v1_0.vhd new file mode 100644 index 0000000..6177079 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/src/axis_fb_conv_v1_0.vhd @@ -0,0 +1,78 @@ +---------------------------------------------------------------------------------------------------- +--! @file axis_fb_conv_v1_0.vhd +--! @brief Simple remapper to convert 16 or 32 bit AXI4-Stream into Xilinx 24 bit Video Stream +--! @author Antti Lukats +--! @version 1.0 +--! @date 2015 +--! @copyright Copyright 2015 Trenz Electronic GmbH +--! @license BSD +--! @pre Vivado 2014.4+ +--! @pre Xilinx VDMA configured with 16 or 32 bit output +---------------------------------------------------------------------------------------------------- + +--! Use standard library +library ieee; +--! Use logic elements + use ieee.std_logic_1164.all; + +--! AXI4-Stream Remapper to be used with: +--! Linux Simple Frame Buffer driver, +--! Xilinx VDMA and Xilinx AXI4-stream to Video Out IP Cores. +entity axis_fb_conv_v1_0 is + generic ( + --! Format: The format of the framebuffer surface. Valid values are: + --! r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b). + --! a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r). + C_FB_MODE : integer range 0 to 1 := 1 --! Mode is set as: 0 = r5g6b5, 1 = a8b8g8r8 + ); + port ( + s_axis_aclk : in std_logic; --! not used + s_axis_aresetn : in std_logic; --! not used + --------------------------------------------------------------------- + s_axis_tready : out std_logic; --! direct bypass + s_axis_tdata : in std_logic_vector(C_FB_MODE*16+16-1 downto 0); --! Pixel data from VDMA IP Core + s_axis_tlast : in std_logic; --! end of line: direct bypass + s_axis_tuser : in std_logic; --! SOF: direct bypass + s_axis_tvalid : in std_logic; --! direct bypass + --------------------------------------------------------------------- + video_out_tvalid : out std_logic; --! direct from input Stream TVALID + video_out_tdata : out std_logic_vector(23 downto 0); --! Remapped TDATA + video_out_tlast : out std_logic; --! direct from input Stream TLAST + video_out_tuser : out std_logic; --! direct from input Stream TUSER + video_out_tready : in std_logic --! direct to input Stream TREADY + ); +end axis_fb_conv_v1_0; + +--! Simple remapper, only function is remap, there is no other logic used +architecture arch_imp of axis_fb_conv_v1_0 is + +signal r : std_logic_vector(7 downto 0) := (others => '0'); --! Red Component +signal g : std_logic_vector(7 downto 0) := (others => '0'); --! Green Component +signal b : std_logic_vector(7 downto 0) := (others => '0'); --! Blue Component +signal a : std_logic_vector(7 downto 0) := (others => '0'); --! Transparency, not used currently + +begin + video_out_tvalid <= s_axis_tvalid; -- Direct bypass + video_out_tlast <= s_axis_tlast; -- Direct bypass + video_out_tuser <= s_axis_tuser; -- Direct bypass + s_axis_tready <= video_out_tready; -- Direct bypass + +-- r5g6b5 (16-bit pixels, d[15:11]=r, d[10:5]=g, d[4:0]=b). +Video_16_bit_Gen: if C_FB_MODE = 0 generate + r(7 downto 3) <= s_axis_tdata(15 downto 11); + g(7 downto 2) <= s_axis_tdata(10 downto 5); + b(7 downto 3) <= s_axis_tdata(4 downto 0); +end generate Video_16_bit_Gen; + +-- a8b8g8r8 (32-bit pixels, d[31:24]=a, d[23:16]=b, d[15:8]=g, d[7:0]=r). +Video_32_bit_Gen: if C_FB_MODE = 1 generate + b(7 downto 0) <= s_axis_tdata(23 downto 16); + g(7 downto 0) <= s_axis_tdata(15 downto 8); + r(7 downto 0) <= s_axis_tdata(7 downto 0); +end generate Video_32_bit_Gen; + +-- construct Xilinx Video RGB format +-- R B G, see PG044 +video_out_tdata(23 downto 0) <= r & b & g; + +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/xgui/axis_fb_conv_v1_0.tcl b/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/xgui/axis_fb_conv_v1_0.tcl new file mode 100644 index 0000000..a29491b --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_fb_conv_1.0/xgui/axis_fb_conv_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_FB_MODE" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_FB_MODE { PARAM_VALUE.C_FB_MODE } { + # Procedure called to update C_FB_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_FB_MODE { PARAM_VALUE.C_FB_MODE } { + # Procedure called to validate C_FB_MODE + return true +} + + +proc update_MODELPARAM_VALUE.C_FB_MODE { MODELPARAM_VALUE.C_FB_MODE PARAM_VALUE.C_FB_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_FB_MODE}] ${MODELPARAM_VALUE.C_FB_MODE} +} + diff --git a/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/component.xml b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/component.xml new file mode 100644 index 0000000..3956dca --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/component.xml @@ -0,0 +1,586 @@ + + + trenz.biz + user + axis_raw_demosaic + 1.0 + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TUSER + + + s_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + TUSER + + + m_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + axis_aresetn + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_aclk + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS:M_AXIS + + + ASSOCIATED_RESET + axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_raw_demosaic_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 340c8292 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_raw_demosaic_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 340c8292 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 766ecffa + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + colors_mode + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_RAW_WIDTH + C Raw Width + 10 + + + C_MODE + C Mode + 1 + + + C_IN_TYPE + C In Type + 1 + + + C_COLOR_POS + C Color Pos + 0 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_f5adc799 + 10 + 8 + + + choice_pairs_719c03b1 + 1 + 4 + + + choice_pairs_8aadb9bc + 0 + 1 + 2 + + + choice_pairs_e37d2356 + 0 + 1 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/dualport_ram.vhd + vhdlSource + + + hdl/gamma_rom.vhd + vhdlSource + + + hdl/axis_raw_demosaic_v1_0.vhd + vhdlSource + CHECKSUM_d52eb58c + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/dualport_ram.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/gamma_rom.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/axis_raw_demosaic_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_raw_demosaic_v1_0.tcl + tclSource + CHECKSUM_6e4393c6 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + RAW format demosaic + + + Component_Name + axis_raw_demosaic_v1_0 + + + C_RAW_WIDTH + Raw Width + 10 + + + C_MODE + Mode + 1 + + + C_IN_TYPE + Input Type + 1 + + + C_COLOR_POS + Colors Position + 0 + + + + + + virtex7 + artix7 + kintex7 + qzynq + zynq + + + /AXI_Peripheral + /Video_&_Image_Processing + + RAW Demosaic v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 20 + + xilinx.com:user:axis_raw_demosaic:1.0 + + 2017-05-18T06:15:26Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_raw_demosaic_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_raw_demosaic_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/axis_raw_demosaic_v1_0.vhd b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/axis_raw_demosaic_v1_0.vhd new file mode 100644 index 0000000..f7b861b --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/axis_raw_demosaic_v1_0.vhd @@ -0,0 +1,252 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity axis_raw_demosaic_v1_0 is +generic ( + C_MODE : integer range 0 to 1 := 1; + C_COLOR_POS : integer range 0 to 2 := 0; + C_IN_TYPE : integer range 1 to 4 := 1; + C_RAW_WIDTH : integer := 10 +); +port ( + axis_aclk : in STD_LOGIC; + axis_aresetn : in STD_LOGIC; + + colors_mode : in STD_LOGIC; + + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_IN_TYPE*16-1 downto 0); + s_axis_tuser : in STD_LOGIC; + s_axis_tlast : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_IN_TYPE*32-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC +); +end axis_raw_demosaic_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_raw_demosaic_v1_0 is +---------------------------------------------------------------------------------- +component dualport_ram is +port ( + clk : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR(10 downto 0); + addrb : in STD_LOGIC_VECTOR(10 downto 0); + dia : in STD_LOGIC_VECTOR(9 downto 0); + dob : out STD_LOGIC_VECTOR(9 downto 0) +); +end component; + +component gamma_rom is +port( + addra : in STD_LOGIC_VECTOR(9 downto 0); + clka : in STD_LOGIC; + douta : out STD_LOGIC_VECTOR(7 downto 0) +); +end component; +---------------------------------------------------------------------------------- +signal tx_alpha : STD_LOGIC_VECTOR(7 downto 0); +signal tx_blue : STD_LOGIC_VECTOR(7 downto 0); +signal tx_green : STD_LOGIC_VECTOR(7 downto 0); +signal tx_red : STD_LOGIC_VECTOR(7 downto 0); +signal x_cnt : UNSIGNED(15 downto 0); +signal y_cnt : UNSIGNED(15 downto 0); +type sm_state_type is (ST_IDLE, ST_PROCESS, ST_SEND); +signal sm_state : sm_state_type := ST_IDLE; +signal up_pixel_data : STD_LOGIC_VECTOR(C_RAW_WIDTH-1 downto 0); +signal pixel_data : STD_LOGIC_VECTOR(C_RAW_WIDTH-1 downto 0); +signal position : STD_LOGIC_VECTOR(1 downto 0); +signal tx_valid : STD_LOGIC; +signal tx_user : STD_LOGIC; +signal tx_last : STD_LOGIC; +signal x_wr_addr : UNSIGNED(15 downto 0); +signal x_rd_addr : UNSIGNED(15 downto 0); +signal ram_write : STD_LOGIC; +signal ram_wr_addr : STD_LOGIC_VECTOR(10 downto 0); +signal ram_rd_addr : STD_LOGIC_VECTOR(10 downto 0); +signal ram_wr_data : STD_LOGIC_VECTOR( 9 downto 0); +signal ram_rd_data : STD_LOGIC_VECTOR( 9 downto 0); +type raw_pixel is array (3 downto 0) of STD_LOGIC_VECTOR(C_RAW_WIDTH-1 downto 0); +signal pixel : raw_pixel; +type std_pixel is array (3 downto 0) of STD_LOGIC_VECTOR(7 downto 0); +signal pixel_gamma : std_pixel; +signal colors_mode_i : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +ram_wr_addr <= STD_LOGIC_VECTOR(x_wr_addr(10 downto 0)); +ram_rd_addr <= STD_LOGIC_VECTOR(x_rd_addr(10 downto 0)); +ram_wr_data <= pixel(0); +up_pixel_data <= ram_rd_data; +pixel_data <= s_axis_tdata(C_RAW_WIDTH-1 downto 0); +---------------------------------------------------------------------------------- +ram_inst: dualport_ram +port map( + clk => axis_aclk, + wea => ram_write, + addra => ram_wr_addr, + addrb => ram_rd_addr, + dia => ram_wr_data, + dob => ram_rd_data +); +---------------------------------------------------------------------------------- +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_state is + when ST_IDLE => + if(s_axis_tvalid = '1')then + sm_state <= ST_PROCESS; + pixel(0) <= pixel_data; + pixel(1) <= pixel(0); + pixel(2) <= up_pixel_data; + pixel(3) <= pixel(2); + tx_user <= s_axis_tuser; + tx_last <= s_axis_tlast; + x_wr_addr <= x_cnt; + ram_write <= '1'; + position <= y_cnt(0) & x_cnt(0); + if(s_axis_tlast = '1')then + x_cnt <= (others => '0'); + x_rd_addr <= (others => '0'); + else + x_cnt <= x_cnt + 1; + x_rd_addr <= x_cnt + 1; + end if; + if(s_axis_tuser = '1')then + y_cnt <= (others => '0'); + elsif(s_axis_tlast = '1')then + y_cnt <= y_cnt + 1; + end if; + else + ram_write <= '0'; + end if; + when ST_PROCESS => + ram_write <= '0'; + sm_state <= ST_SEND; + when ST_SEND => + if(m_axis_tready = '1')then + if(s_axis_tvalid = '0')then + sm_state <= ST_IDLE; + ram_write <= '0'; + else + sm_state <= ST_PROCESS; + pixel(0) <= pixel_data; + pixel(1) <= pixel(0); + pixel(2) <= up_pixel_data; + pixel(3) <= pixel(2); + tx_user <= s_axis_tuser; + tx_last <= s_axis_tlast; + x_wr_addr <= x_cnt; + ram_write <= '1'; + position <= y_cnt(0) & x_cnt(0); + if(s_axis_tlast = '1')then + x_cnt <= (others => '0'); + x_rd_addr <= (others => '0'); + else + x_cnt <= x_cnt + 1; + x_rd_addr <= x_cnt + 1; + end if; + if(s_axis_tuser = '1')then + y_cnt <= (others => '0'); + elsif(s_axis_tlast = '1')then + y_cnt <= y_cnt + 1; + end if; + end if; + end if; + end case; + end if; +end process; +---------------------------------------------------------------------------------- +gamma_rom_gen: for i in 0 to 3 generate +begin + pa_gamma_inst: gamma_rom + port map( + addra => pixel(i), + clka => axis_aclk, + douta => pixel_gamma(i) + ); +end generate; +---------------------------------------------------------------------------------- +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + if(C_COLOR_POS = 0)then + colors_mode_i <= '0'; + elsif(C_COLOR_POS = 1)then + colors_mode_i <= '1'; + else -- C_COLOR_POS = 2 + colors_mode_i <= colors_mode; + end if; + end if; +end process; +---------------------------------------------------------------------------------- +tx_alpha <= (others => '0'); +-- Demosaic (Color) +demosaic_gen: if C_MODE = 1 generate +begin + + process(sm_state, m_axis_tready) + begin + case sm_state is + when ST_IDLE => s_axis_tready <= '1'; + when ST_PROCESS => s_axis_tready <= '0'; + when ST_SEND => s_axis_tready <= m_axis_tready; + end case; + end process; + + m_axis_tvalid <= '1' when (sm_state = ST_SEND) else '0'; + m_axis_tuser <= tx_user; + m_axis_tlast <= tx_last; + + process(position, tx_alpha, pixel_gamma, colors_mode_i) + begin + if(colors_mode_i = '0')then + case position is + when "01" => m_axis_tdata <= tx_alpha & pixel_gamma(1) & pixel_gamma(0) & pixel_gamma(2); + when "00" => m_axis_tdata <= tx_alpha & pixel_gamma(0) & pixel_gamma(1) & pixel_gamma(3); + when "11" => m_axis_tdata <= tx_alpha & pixel_gamma(3) & pixel_gamma(1) & pixel_gamma(0); + when "10" => m_axis_tdata <= tx_alpha & pixel_gamma(2) & pixel_gamma(0) & pixel_gamma(1); + when others => null; + end case; + else + case position is + when "01" => m_axis_tdata <= tx_alpha & pixel_gamma(2) & pixel_gamma(0) & pixel_gamma(1); + when "00" => m_axis_tdata <= tx_alpha & pixel_gamma(3) & pixel_gamma(1) & pixel_gamma(0); + when "11" => m_axis_tdata <= tx_alpha & pixel_gamma(0) & pixel_gamma(1) & pixel_gamma(3); + when "10" => m_axis_tdata <= tx_alpha & pixel_gamma(1) & pixel_gamma(0) & pixel_gamma(2); + when others => null; + end case; + end if; + end process; + +end generate; +---------------------------------------------------------------------------------- +-- Bypass (Raw grayscale) +bypass_gen: if C_MODE = 0 generate +begin + s_axis_tready <= m_axis_tready; + m_axis_tvalid <= s_axis_tvalid; + m_axis_tuser <= s_axis_tuser; + m_axis_tlast <= s_axis_tlast; + data_gen: for i in 0 to C_IN_TYPE-1 generate + begin + m_axis_tdata(i*32+31 downto i*32) <= x"00" & + s_axis_tdata(i*16+9 downto i*16+2) & + s_axis_tdata(i*16+9 downto i*16+2) & + s_axis_tdata(i*16+9 downto i*16+2); + end generate; +end generate; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/dualport_ram.vhd b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/dualport_ram.vhd new file mode 100644 index 0000000..85042bc --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/dualport_ram.vhd @@ -0,0 +1,39 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.STD_LOGIC_unsigned.all; +---------------------------------------------------------------------------------- +entity dualport_ram is +port ( + clk : in STD_LOGIC; + wea : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR(10 downto 0); + addrb : in STD_LOGIC_VECTOR(10 downto 0); + dia : in STD_LOGIC_VECTOR(9 downto 0); + dob : out STD_LOGIC_VECTOR(9 downto 0) +); +end dualport_ram; +---------------------------------------------------------------------------------- +architecture dualport_ram_arch of dualport_ram is +type ram_type is array (2047 downto 0) of STD_LOGIC_VECTOR (9 downto 0); +signal ram : ram_type; +---------------------------------------------------------------------------------- +attribute block_ram : boolean; +attribute block_ram of ram : signal is TRUE; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process (clk) +begin + if (clk'event and clk = '1') then + if (wea = '1') then + ram(conv_integer(addra)) <= dia; + end if; + dob <= ram(conv_integer(addrb)); + end if; +end process; +---------------------------------------------------------------------------------- +end dualport_ram_arch; diff --git a/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/gamma_rom.vhd b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/gamma_rom.vhd new file mode 100644 index 0000000..fc84945 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/hdl/gamma_rom.vhd @@ -0,0 +1,98 @@ +---------------------------------------------------------------------------------- +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.STD_LOGIC_arith.all; +use ieee.STD_LOGIC_unsigned.all; +---------------------------------------------------------------------------------- +entity gamma_rom is +port( + addra : in STD_LOGIC_VECTOR(9 downto 0); + clka : in STD_LOGIC; + douta : out STD_LOGIC_VECTOR(7 downto 0) +); +end gamma_rom; +---------------------------------------------------------------------------------- +architecture Behavioral of gamma_rom is +---------------------------------------------------------------------------------- +type rom_type is array (1023 downto 0) of std_logic_vector (7 downto 0); +signal rom : rom_type := ( +x"ff", x"ff", x"ff", x"ff", x"fe", x"fe", x"fe", x"fe", x"fe", x"fe", x"fe", x"fd", x"fd", x"fd", x"fd", x"fd", +x"fd", x"fd", x"fc", x"fc", x"fc", x"fc", x"fc", x"fc", x"fc", x"fc", x"fb", x"fb", x"fb", x"fb", x"fb", x"fb", +x"fb", x"fa", x"fa", x"fa", x"fa", x"fa", x"fa", x"fa", x"f9", x"f9", x"f9", x"f9", x"f9", x"f9", x"f9", x"f8", +x"f8", x"f8", x"f8", x"f8", x"f8", x"f8", x"f7", x"f7", x"f7", x"f7", x"f7", x"f7", x"f7", x"f6", x"f6", x"f6", +x"f6", x"f6", x"f6", x"f6", x"f5", x"f5", x"f5", x"f5", x"f5", x"f5", x"f5", x"f4", x"f4", x"f4", x"f4", x"f4", +x"f4", x"f4", x"f3", x"f3", x"f3", x"f3", x"f3", x"f3", x"f3", x"f2", x"f2", x"f2", x"f2", x"f2", x"f2", x"f2", +x"f1", x"f1", x"f1", x"f1", x"f1", x"f1", x"f1", x"f0", x"f0", x"f0", x"f0", x"f0", x"f0", x"f0", x"ef", x"ef", +x"ef", x"ef", x"ef", x"ef", x"ef", x"ee", x"ee", x"ee", x"ee", x"ee", x"ee", x"ed", x"ed", x"ed", x"ed", x"ed", +x"ed", x"ed", x"ec", x"ec", x"ec", x"ec", x"ec", x"ec", x"ec", x"eb", x"eb", x"eb", x"eb", x"eb", x"eb", x"eb", +x"ea", x"ea", x"ea", x"ea", x"ea", x"ea", x"e9", x"e9", x"e9", x"e9", x"e9", x"e9", x"e9", x"e8", x"e8", x"e8", +x"e8", x"e8", x"e8", x"e8", x"e7", x"e7", x"e7", x"e7", x"e7", x"e7", x"e7", x"e6", x"e6", x"e6", x"e6", x"e6", +x"e6", x"e5", x"e5", x"e5", x"e5", x"e5", x"e5", x"e5", x"e4", x"e4", x"e4", x"e4", x"e4", x"e4", x"e3", x"e3", +x"e3", x"e3", x"e3", x"e3", x"e3", x"e2", x"e2", x"e2", x"e2", x"e2", x"e2", x"e2", x"e1", x"e1", x"e1", x"e1", +x"e1", x"e1", x"e0", x"e0", x"e0", x"e0", x"e0", x"e0", x"e0", x"df", x"df", x"df", x"df", x"df", x"df", x"de", +x"de", x"de", x"de", x"de", x"de", x"de", x"dd", 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x"41", x"40", x"40", x"40", x"3f", x"3f", x"3e", x"3e", +x"3d", x"3d", x"3d", x"3c", x"3c", x"3b", x"3b", x"3a", x"3a", x"39", x"39", x"39", x"38", x"38", x"37", x"37", +x"36", x"36", x"35", x"35", x"34", x"34", x"33", x"33", x"32", x"32", x"31", x"31", x"30", x"30", x"2f", x"2f", +x"2e", x"2e", x"2d", x"2c", x"2c", x"2b", x"2b", x"2a", x"2a", x"29", x"28", x"28", x"27", x"26", x"26", x"25", +x"25", x"24", x"23", x"23", x"22", x"21", x"20", x"20", x"1f", x"1e", x"1d", x"1d", x"1c", x"1b", x"1a", x"19", +x"18", x"18", x"17", x"16", x"15", x"13", x"12", x"11", x"10", x"0f", x"0d", x"0c", x"0a", x"08", x"05", x"00" +); +attribute rom_style : string; +attribute rom_style of rom : signal is "block"; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process (clka) +begin + if rising_edge(clka) then + douta <= rom(conv_integer(addra)); + end if; +end process; +---------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/xgui/axis_raw_demosaic_v1_0.tcl b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/xgui/axis_raw_demosaic_v1_0.tcl new file mode 100644 index 0000000..b4dad42 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_demosaic_1.0/xgui/axis_raw_demosaic_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_MODE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_IN_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_RAW_WIDTH" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_COLOR_POS" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_COLOR_POS { PARAM_VALUE.C_COLOR_POS } { + # Procedure called to update C_COLOR_POS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_COLOR_POS { PARAM_VALUE.C_COLOR_POS } { + # Procedure called to validate C_COLOR_POS + return true +} + +proc update_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to update C_IN_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to validate C_IN_TYPE + return true +} + +proc update_PARAM_VALUE.C_MODE { PARAM_VALUE.C_MODE } { + # Procedure called to update C_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_MODE { PARAM_VALUE.C_MODE } { + # Procedure called to validate C_MODE + return true +} + +proc update_PARAM_VALUE.C_RAW_WIDTH { PARAM_VALUE.C_RAW_WIDTH } { + # Procedure called to update C_RAW_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RAW_WIDTH { PARAM_VALUE.C_RAW_WIDTH } { + # Procedure called to validate C_RAW_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_RAW_WIDTH { MODELPARAM_VALUE.C_RAW_WIDTH PARAM_VALUE.C_RAW_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RAW_WIDTH}] ${MODELPARAM_VALUE.C_RAW_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_MODE { MODELPARAM_VALUE.C_MODE PARAM_VALUE.C_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_MODE}] ${MODELPARAM_VALUE.C_MODE} +} + +proc update_MODELPARAM_VALUE.C_IN_TYPE { MODELPARAM_VALUE.C_IN_TYPE PARAM_VALUE.C_IN_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IN_TYPE}] ${MODELPARAM_VALUE.C_IN_TYPE} +} + +proc update_MODELPARAM_VALUE.C_COLOR_POS { MODELPARAM_VALUE.C_COLOR_POS PARAM_VALUE.C_COLOR_POS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_COLOR_POS}] ${MODELPARAM_VALUE.C_COLOR_POS} +} + diff --git a/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/component.xml b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/component.xml new file mode 100644 index 0000000..7574af6 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/component.xml @@ -0,0 +1,524 @@ + + + trenz.biz + user + axis_raw_unpack + 1.0 + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TUSER + + + s_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + TUSER + + + m_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + axis_aresetn + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_aclk + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS:M_AXIS + + + ASSOCIATED_RESET + axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_raw_unpack_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 71a3a0ad + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_raw_unpack_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 71a3a0ad + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 18ee627c + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tdata + + out + + 63 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + + C_IMP_TYPE + C Imp Type + 0 + + + C_OUT_TYPE + C Out Type + 4 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_719c03b1 + 1 + 4 + + + choice_pairs_a91bb82a + 0 + 1 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/srl_fifo.vhd + vhdlSource + + + hdl/axis_raw_unpack_v1_0.vhd + vhdlSource + CHECKSUM_4d998fbe + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/srl_fifo.vhd + vhdlSource + + + hdl/axis_raw_unpack_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_raw_unpack_v1_0.tcl + tclSource + CHECKSUM_13a7b1e1 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + RAW10 2 Lanes format unpack + + + Component_Name + axis_raw_unpack_v1_0 + + + C_IMP_TYPE + Implementation Type + 0 + + + C_OUT_TYPE + Output Type + 4 + + + + + + virtex7 + artix7 + zynq + kintex7 + + + /AXI_Peripheral + /Video_&_Image_Processing + + RAW10 Unpack v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 17 + + xilinx.com:user:axis_raw_unpack:1.0 + + 2017-05-17T15:02:49Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_raw_unpack_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_raw_unpack_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/hdl/axis_raw_unpack_v1_0.vhd b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/hdl/axis_raw_unpack_v1_0.vhd new file mode 100644 index 0000000..82940b6 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/hdl/axis_raw_unpack_v1_0.vhd @@ -0,0 +1,288 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +Library UNISIM; +use UNISIM.vcomponents.all; +Library UNIMACRO; +use UNIMACRO.vcomponents.all; +---------------------------------------------------------------------------------- +entity axis_raw_unpack_v1_0 is +generic ( + C_IMP_TYPE : integer range 0 to 1 := 0; + C_OUT_TYPE : integer range 1 to 4 := 4 +); +port ( + axis_aclk : in STD_LOGIC; + axis_aresetn : in STD_LOGIC; + -- Ports of Axi Slave Bus Interface S_AXIS + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(15 downto 0); + s_axis_tuser : in STD_LOGIC; + s_axis_tlast : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + -- Ports of Axi Master Bus Interface M_AXIS + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_OUT_TYPE*16-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC +); +end axis_raw_unpack_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_raw_unpack_v1_0 is +---------------------------------------------------------------------------------- +constant C_DEVICE : STRING := "7SERIES"; +constant C_FIFO_SIZE : STRING := "18Kb"; +type sm_rx_state_type is (ST_IDLE, ST_PA, ST_PB, ST_PC, ST_PD); +signal sm_rx_state : sm_rx_state_type := ST_IDLE; +type sm_tx_state_type is (ST_WAIT, ST_TXA, ST_TXB, ST_TXC, ST_TXD); +signal sm_tx_state : sm_tx_state_type := ST_WAIT; +type sm_rxp_state_type is (ST_PIDLE, ST_PPA, ST_PPB, ST_PPC, ST_PPD, ST_PPW); +signal sm_rxp_state : sm_rxp_state_type := ST_PIDLE; + +signal pixels_data : STD_LOGIC_VECTOR(39 downto 0); +signal last : STD_LOGIC; +signal user : STD_LOGIC; +signal pixel_a : STD_LOGIC_VECTOR(9 downto 0); +signal pixel_b : STD_LOGIC_VECTOR(9 downto 0); +signal pixel_c : STD_LOGIC_VECTOR(9 downto 0); +signal pixel_d : STD_LOGIC_VECTOR(9 downto 0); +signal pixels_valid : STD_LOGIC; +signal buffer_we : STD_LOGIC; +signal buffer_re : STD_LOGIC; +signal buffer_full : STD_LOGIC; +signal buffer_empty : STD_LOGIC; +signal buffer_in_data : STD_LOGIC_VECTOR(41 downto 0); +signal buffer_out_data : STD_LOGIC_VECTOR(41 downto 0); + +component srl_fifo is +generic( + C_DEPTH : integer := 32; + C_WIDTH : integer := 8 +); +port ( + clk_in : in STD_LOGIC; + we_in : in STD_LOGIC; + re_in : in STD_LOGIC; + full_out : out STD_LOGIC; + empty_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0) +); +end component; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +-- 16 bit input implementation +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_rx_state is + when ST_IDLE => + buffer_we <= '0'; + if(s_axis_tvalid = '1')then + pixels_data( 9 downto 2) <= s_axis_tdata( 7 downto 0); -- P0 + pixels_data(19 downto 12) <= s_axis_tdata(15 downto 8); -- P1 + user <= s_axis_tuser; + if(s_axis_tlast /= '1')then + sm_rx_state <= ST_PA; + end if; + end if; + + when ST_PA => + buffer_we <= '0'; + if(s_axis_tvalid = '1')then + pixels_data(29 downto 22) <= s_axis_tdata( 7 downto 0); -- P2 + pixels_data(39 downto 32) <= s_axis_tdata(15 downto 8); -- P3 + if(s_axis_tuser = '1')then -- Problem + sm_rx_state <= ST_PA; + elsif(s_axis_tlast /= '1')then + sm_rx_state <= ST_PB; + else + sm_rx_state <= ST_IDLE; + end if; + end if; + + when ST_PB => + if((s_axis_tvalid = '1') and (buffer_full = '0'))then + pixel_a( 9 downto 2) <= pixels_data( 9 downto 2); + pixel_a( 1 downto 0) <= s_axis_tdata( 1 downto 0); + pixel_b( 9 downto 2) <= pixels_data(19 downto 12); + pixel_b( 1 downto 0) <= s_axis_tdata( 3 downto 2); + pixel_c( 9 downto 2) <= pixels_data(29 downto 22); + pixel_c( 1 downto 0) <= s_axis_tdata( 5 downto 4); + pixel_d( 9 downto 2) <= pixels_data(39 downto 32); + pixel_d( 1 downto 0) <= s_axis_tdata( 7 downto 6); + last <= s_axis_tlast; + buffer_we <= '1'; + pixels_data( 9 downto 2) <= s_axis_tdata(15 downto 8); + if(s_axis_tuser = '1')then -- Problem + sm_rx_state <= ST_PA; + elsif(s_axis_tlast /= '1')then + sm_rx_state <= ST_PC; + else + sm_rx_state <= ST_IDLE; + end if; + end if; + + when ST_PC => + buffer_we <= '0'; + if(s_axis_tvalid = '1')then + pixels_data(19 downto 12) <= s_axis_tdata( 7 downto 0); -- P1 + pixels_data(29 downto 22) <= s_axis_tdata(15 downto 8); -- P2 + if(s_axis_tuser = '1')then -- Problem + sm_rx_state <= ST_PA; + elsif(s_axis_tlast /= '1')then + sm_rx_state <= ST_PD; + else + sm_rx_state <= ST_IDLE; + end if; + end if; + + when ST_PD => + if((s_axis_tvalid = '1') and (buffer_full = '0'))then + pixel_a( 9 downto 2) <= pixels_data( 9 downto 2); + pixel_a( 1 downto 0) <= s_axis_tdata( 9 downto 8); + pixel_b( 9 downto 2) <= pixels_data(19 downto 12); + pixel_b( 1 downto 0) <= s_axis_tdata(11 downto 10); + pixel_c( 9 downto 2) <= pixels_data(29 downto 22); + pixel_c( 1 downto 0) <= s_axis_tdata(13 downto 12); + pixel_d( 9 downto 2) <= s_axis_tdata( 7 downto 0); + pixel_d( 1 downto 0) <= s_axis_tdata(15 downto 14); + buffer_we <= '1'; + user <= '0'; + last <= s_axis_tlast; + if(s_axis_tuser = '1')then -- Problem + sm_rx_state <= ST_PA; + else + sm_rx_state <= ST_IDLE; + end if; + end if; + end case; + end if; +end process; + +process(sm_rx_state, pixels_valid) +begin + case sm_rx_state is + when ST_IDLE => s_axis_tready <= '1'; + when ST_PA => s_axis_tready <= '1'; + when ST_PB => s_axis_tready <= not buffer_full; + when ST_PC => s_axis_tready <= '1'; + when ST_PD => s_axis_tready <= not buffer_full; + end case; +end process; +---------------------------------------------------------------------------------- +reg_buf_gen: if C_IMP_TYPE = 0 generate +begin + process(axis_aclk) + begin + if(axis_aclk = '1' and axis_aclk'event)then + if(pixels_valid = '0')then + if(((sm_rx_state = ST_PB) or (sm_rx_state = ST_PD)) and (s_axis_tvalid = '1'))then + pixels_valid <= '1'; + end if; + else + if(buffer_re = '1')then + pixels_valid <= '0'; + end if; + end if; + end if; + end process; + + buffer_full <= pixels_valid; + buffer_empty <= not pixels_valid; + buffer_out_data <= last & user & pixel_d & pixel_c & pixel_b & pixel_a; + +end generate; +---------------------------------------------------------------------------------- +fifo_buf_gen: if C_IMP_TYPE = 1 generate +begin + buffer_in_data <= last & user & pixel_d & pixel_c & pixel_b & pixel_a; + + FIFO_inst: srl_fifo + generic map( + C_DEPTH => 32, + C_WIDTH => 42 + ) + port map( + clk_in => axis_aclk, + we_in => buffer_we, + re_in => buffer_re, + full_out => buffer_full, + empty_out => buffer_empty, + data_in => buffer_in_data, + data_out => buffer_out_data + ); +end generate; +---------------------------------------------------------------------------------- +serial_out_gen: if C_OUT_TYPE = 1 generate +begin + process(axis_aclk) + begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_tx_state is + when ST_WAIT => + if(buffer_empty = '0')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0); + m_axis_tuser <= buffer_out_data(40); + m_axis_tlast <= '0'; + sm_tx_state <= ST_TXA; + end if; + when ST_TXA => + if(m_axis_tready = '1')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(19 downto 10); + m_axis_tuser <= '0'; + m_axis_tlast <= '0'; + sm_tx_state <= ST_TXB; + end if; + when ST_TXB => + if(m_axis_tready = '1')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(29 downto 20); + m_axis_tuser <= '0'; + m_axis_tlast <= '0'; + sm_tx_state <= ST_TXC; + end if; + when ST_TXC => + if(m_axis_tready = '1')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data(39 downto 30); + m_axis_tuser <= '0'; + m_axis_tlast <= buffer_out_data(41); + sm_tx_state <= ST_TXD; + end if; + when ST_TXD => + if(m_axis_tready = '1')then + if(buffer_empty = '0')then + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0); + m_axis_tuser <= buffer_out_data(40); + m_axis_tlast <= '0'; + sm_tx_state <= ST_TXA; + else + sm_tx_state <= ST_WAIT; + m_axis_tlast <= '0'; + end if; + end if; + end case; + end if; + end process; + buffer_re <= '1' when ((sm_tx_state = ST_TXC) and (m_axis_tready = '1')) else '0'; + m_axis_tvalid <= '1' when (sm_tx_state /= ST_WAIT) else '0'; +end generate; -- serial_out_gen + +parallel4_out_gen: if C_OUT_TYPE = 4 generate +begin + m_axis_tdata(15 downto 0) <= "000000" & buffer_out_data( 9 downto 0); + m_axis_tdata(31 downto 16) <= "000000" & buffer_out_data(19 downto 10); + m_axis_tdata(47 downto 32) <= "000000" & buffer_out_data(29 downto 20); + m_axis_tdata(63 downto 48) <= "000000" & buffer_out_data(39 downto 30); + m_axis_tuser <= buffer_out_data(40); + m_axis_tlast <= buffer_out_data(41); + m_axis_tvalid <= not buffer_empty; + buffer_re <= m_axis_tready; +end generate; -- parallel4_out_gen +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/hdl/srl_fifo.vhd b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/hdl/srl_fifo.vhd new file mode 100644 index 0000000..4330b33 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/hdl/srl_fifo.vhd @@ -0,0 +1,113 @@ +------------------------------------------------------------------------------- +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko +-- +-- SRL based FWPT FIFO +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VComponents.all; +------------------------------------------------------------------------------- +entity srl_fifo is +generic( + C_DEPTH : integer := 64; + C_WIDTH : integer := 8 +); +port ( + clk_in : in STD_LOGIC; + we_in : in STD_LOGIC; + re_in : in STD_LOGIC; + full_out : out STD_LOGIC; + empty_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0) +); +end srl_fifo; +------------------------------------------------------------------------------- +architecture Behavioral of srl_fifo is +------------------------------------------------------------------------------- +type arr_type is array(C_DEPTH/32 downto 0) of STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); +signal ddata : arr_type; +type arrp_type is array(C_DEPTH/32+1 downto 0) of STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); +signal cdata : arrp_type; +signal word_cnt : UNSIGNED(5 downto 0); +signal addr_cnt : UNSIGNED(4 downto 0); +signal srl_addr : STD_LOGIC_VECTOR(4 downto 0); +signal srl_ce : STD_LOGIC; +type fifo_state_type is (ST_EMPTY, ST_NOT_EMPTY, ST_FULL); +signal fifo_state : fifo_state_type := ST_EMPTY; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +cdata(0) <= data_in; +width_gen: for i in C_WIDTH - 1 downto 0 generate +begin + depth_gen: for j in (C_DEPTH/32)-1 downto 0 generate + begin + SRLC32E_1 : SRLC32E + port map ( + D => cdata(j)(i), + Q => ddata(j)(i), + Q31 => cdata(j+1)(i), + A => srl_addr(4 downto 0), + CE => srl_ce, + CLK => clk_in + ); + end generate; +end generate; +srl_addr <= STD_LOGIC_VECTOR(addr_cnt); + +full_out <= '1' when (fifo_state = ST_FULL ) else '0'; +empty_out <= '1' when (fifo_state = ST_EMPTY) else '0'; +srl_ce <= '1' when ((we_in = '1') and (fifo_state /= ST_FULL)) else '0'; + +single_stage_gen: if C_DEPTH = 32 generate +begin + data_out <= ddata(0); +end generate; +multi_stage_gen: if C_DEPTH > 32 generate +begin + data_out <= ddata(TO_INTEGER(addr_cnt(addr_cnt'high downto 5))); +end generate; + +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + case fifo_state is + when ST_EMPTY => + addr_cnt <= (others => '0'); + if(we_in = '1')then + word_cnt <= TO_UNSIGNED(1, word_cnt'length); + fifo_state <= ST_NOT_EMPTY; + end if; + when ST_NOT_EMPTY => + if(we_in = '1')then + if(re_in = '0')then -- Write + if(word_cnt = TO_UNSIGNED((C_DEPTH-1), word_cnt'length))then + fifo_state <= ST_FULL; + end if; + word_cnt <= word_cnt + 1; + addr_cnt <= addr_cnt + 1; + end if; + elsif(re_in = '1')then + if(word_cnt = TO_UNSIGNED(1, word_cnt'length))then + fifo_state <= ST_EMPTY; + word_cnt <= word_cnt - 1; + else + word_cnt <= word_cnt - 1; + addr_cnt <= addr_cnt - 1; + end if; + end if; + when ST_FULL => + if(re_in = '1')then + word_cnt <= word_cnt - 1; + addr_cnt <= addr_cnt - 1; + fifo_state <= ST_NOT_EMPTY; + end if; + end case; + end if; +end process; +------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/src/srl_fifo.vhd b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/src/srl_fifo.vhd new file mode 100644 index 0000000..a853ac4 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/src/srl_fifo.vhd @@ -0,0 +1,111 @@ +------------------------------------------------------------------------------- +-- Company: Trenz Electronic +-- Engineer: Oleksandr Kiyenko +-- +-- SRL based FWPT FIFO +------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.all; +library UNISIM; +use UNISIM.VComponents.all; +------------------------------------------------------------------------------- +entity srl_fifo is +generic( + C_DEPTH : integer := 32; + C_WIDTH : integer := 8 +); +port ( + clk_in : in STD_LOGIC; + we_in : in STD_LOGIC; + re_in : in STD_LOGIC; + full_out : out STD_LOGIC; + empty_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0) +); +end srl_fifo; +------------------------------------------------------------------------------- +architecture Behavioral of srl_fifo is +------------------------------------------------------------------------------- +type arr_type is array(C_DEPTH/32 downto 0) of STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); +signal ddata : arr_type; +type arrp_type is array(C_DEPTH/32+1 downto 0) of STD_LOGIC_VECTOR(C_WIDTH - 1 downto 0); +signal cdata : arrp_type; +signal word_cnt : UNSIGNED(5 downto 0); +signal addr_cnt : UNSIGNED(4 downto 0); +signal srl_addr : STD_LOGIC_VECTOR(4 downto 0); +signal srl_ce : STD_LOGIC; +type fifo_state_type is (ST_EMPTY, ST_NOT_EMPTY, ST_FULL); +signal fifo_state : fifo_state_type := ST_EMPTY; +------------------------------------------------------------------------------- +begin +------------------------------------------------------------------------------- +cdata(0) <= data_in; +width_gen: for i in C_WIDTH - 1 downto 0 generate +begin + depth_gen: for j in C_DEPTH/32 downto 0 generate + begin + SRLC32E_1 : SRLC32E + port map ( + D => cdata(j)(i), + Q => ddata(j)(i), + Q31 => cdata(j+1)(i), + A => srl_addr(4 downto 0), + CE => srl_ce, + CLK => clk_in + ); + end generate; +end generate; +srl_addr <= STD_LOGIC_VECTOR(addr_cnt); + +full_out <= '1' when (fifo_state = ST_FULL ) else '0'; +empty_out <= '1' when (fifo_state = ST_EMPTY) else '0'; +srl_ce <= '1' when ((we_in = '1') and ((fifo_state /= ST_FULL) or (re_in = '1'))) else '0'; + +single_stage_gen: if C_DEPTH = 32 generate +begin + data_out <= ddata(0); +end generate; +-- multi_stage_gen: if C_DEPTH > 32 generate +-- begin + -- data_out <= ddata(TO_INTEGER(addr_cnt(addr_cnt'high downto 5))); +-- end generate; + +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + case fifo_state is + when ST_EMPTY => + if(we_in = '1')then + word_cnt <= word_cnt + 1; + fifo_state <= ST_NOT_EMPTY; + end if; + when ST_NOT_EMPTY => + if(we_in = '1')then + if(re_in = '0')then -- Write + if(word_cnt = TO_UNSIGNED((C_DEPTH-1), word_cnt'width))then + fifo_state <= ST_FULL; + end if; + word_cnt <= word_cnt + 1; + addr_cnt <= addr_cnt + 1; + end if; + elsif(re_in = '1')then + if(word_cnt = TO_UNSIGNED(1, word_cnt'width))then + fifo_state <= ST_EMPTY; + word_cnt <= word_cnt - 1; + else + word_cnt <= word_cnt - 1; + addr_cnt <= addr_cnt - 1; + end if; + end if; + when ST_FULL => + if((re_in = '1') and (we_in = '0'))then + word_cnt <= word_cnt - 1; + addr_cnt <= addr_cnt - 1; + end if; + end case; + end if; +end process; +------------------------------------------------------------------------------- +end Behavioral; diff --git a/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/xgui/axis_raw_unpack_v1_0.tcl b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/xgui/axis_raw_unpack_v1_0.tcl new file mode 100644 index 0000000..cbb2c6c --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_raw_unpack_1.0/xgui/axis_raw_unpack_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_IMP_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_OUT_TYPE" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_IMP_TYPE { PARAM_VALUE.C_IMP_TYPE } { + # Procedure called to update C_IMP_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IMP_TYPE { PARAM_VALUE.C_IMP_TYPE } { + # Procedure called to validate C_IMP_TYPE + return true +} + +proc update_PARAM_VALUE.C_OUT_TYPE { PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to update C_OUT_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_OUT_TYPE { PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to validate C_OUT_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.C_IMP_TYPE { MODELPARAM_VALUE.C_IMP_TYPE PARAM_VALUE.C_IMP_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IMP_TYPE}] ${MODELPARAM_VALUE.C_IMP_TYPE} +} + +proc update_MODELPARAM_VALUE.C_OUT_TYPE { MODELPARAM_VALUE.C_OUT_TYPE PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_OUT_TYPE}] ${MODELPARAM_VALUE.C_OUT_TYPE} +} + diff --git a/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/component.xml b/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/component.xml new file mode 100644 index 0000000..b9448e0 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/component.xml @@ -0,0 +1,324 @@ + + + trenz.biz + user + axis_to_i2s + 1.0 + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axis_to_i2s + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 5b9a2668 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axis_to_i2s + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5b9a2668 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f64a5dae + + + + + + + s_axis_aclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aresetn + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tdata + + in + + 15 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_bclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_lrclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_sdata + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/axis_to_i2s.vhd + vhdlSource + CHECKSUM_5b9a2668 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/axis_to_i2s.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_to_i2s_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + AXI4-Stream to I2S v1.0 + + + Component_Name + axis_to_i2s_v1_0 + + + + + + virtex7 + kintex7 + artix7 + zynq + + + /Embedded_Processing/AXI_Peripheral + /Embedded_Processing/AXI_Peripheral/Low_Speed_Peripheral + /UserIP + + AXI4-Stream to I2S v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 4 + + xilinx.com:user:axis_to_i2s:1.0 + + 2016-04-29T07:00:54Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_to_i2s_1.0 + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_to_i2s_1.0 + + + + 2015.4.2 + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/hdl/axis_to_i2s.vhd b/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/hdl/axis_to_i2s.vhd new file mode 100644 index 0000000..fa14fc3 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/hdl/axis_to_i2s.vhd @@ -0,0 +1,66 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity axis_to_i2s is +port ( + -- Ports of Axi Slave Bus Interface S_AXIS + s_axis_aclk : in STD_LOGIC; + s_axis_aresetn : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(15 downto 0); + s_axis_tvalid : in STD_LOGIC; + -- I2S Signals + i2s_bclk : in STD_LOGIC; + i2s_lrclk : in STD_LOGIC; + i2s_sdata : out STD_LOGIC +); +end axis_to_i2s; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_to_i2s is +---------------------------------------------------------------------------------- +signal input_data : STD_LOGIC_VECTOR(15 downto 0); +signal bclk_sr : STD_LOGIC_VECTOR( 1 downto 0); +signal lrclk_sr : STD_LOGIC_VECTOR( 1 downto 0); +signal data_sr : STD_LOGIC_VECTOR(31 downto 0); +signal load_flag : STD_LOGIC; +signal channel_flag : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +s_axis_tready <= '1'; +process(s_axis_aclk) +begin + if(s_axis_aclk = '1' and s_axis_aclk'event)then + bclk_sr <= bclk_sr(0) & i2s_bclk; + lrclk_sr <= lrclk_sr(0) & i2s_lrclk; + if(s_axis_tvalid = '1')then + input_data <= s_axis_tdata; + end if; + + if((lrclk_sr = "10") or (lrclk_sr = "01"))then -- LR Edge + channel_flag <= '1'; + elsif(bclk_sr = "01")then -- Rising edge + channel_flag <= '0'; + end if; + + if(bclk_sr = "01")then -- Rising edge + load_flag <= channel_flag; + end if; + + if(bclk_sr = "10")then -- Falling edge + if(load_flag = '1')then + data_sr <= input_data & x"0000"; + else + data_sr <= data_sr(30 downto 0) & '0'; + end if; + end if; + end if; +end process; +i2s_sdata <= data_sr(31); +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/xgui/axis_to_i2s_v1_0.tcl b/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/xgui/axis_to_i2s_v1_0.tcl new file mode 100644 index 0000000..66195ab --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_to_i2s_1.0/xgui/axis_to_i2s_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/component.xml b/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/component.xml new file mode 100644 index 0000000..8c3a78c --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/component.xml @@ -0,0 +1,535 @@ + + + trenz.biz + user + axis_video_dwidth_converter + 1.0 + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TUSER + + + s_axis_tuser + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + + + axis_aresetn + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_aclk + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis:m_axis + + + ASSOCIATED_RESET + axis_aresetn + + + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_video_dwidth_converter_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + c5686eda + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_video_dwidth_converter_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + c5686eda + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 6001f6d0 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_IN_TYPE + C In Type + 1 + + + C_OUT_TYPE + C Out Type + 1 + + + C_DATA_WIDTH + C Data Width + 32 + + + + + + choice_list_07c83d4f + 16 + 32 + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_719c03b1 + 1 + 4 + + + choice_pairs_95e1d6c3 + 1 + 2 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axis_video_dwidth_converter_v1_0.vhd + vhdlSource + CHECKSUM_c5686eda + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axis_video_dwidth_converter_v1_0.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axis_video_dwidth_converter_v1_0.tcl + tclSource + CHECKSUM_7e8a0bf1 + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + AXI4-Stream Video Data Width Converter + + + Component_Name + axis_video_dwidth_converter_v1_0 + + + C_IN_TYPE + Input Type + 1 + + + C_OUT_TYPE + Output Type + 1 + + + C_DATA_WIDTH + Data Width + 32 + + + + + + zynq + virtex7 + qvirtex7 + kintex7 + kintex7l + qkintex7 + qkintex7l + artix7 + artix7l + aartix7 + qartix7 + qzynq + azynq + virtexu + virtexuplus + kintexuplus + zynquplus + kintexu + + + /AXI_Peripheral + /Video_&_Image_Processing + + AXI4-Stream Video Data Width Converter v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 9 + + xilinx.com:user:axis_video_dwidth_converter:1.0 + + 2017-05-17T13:30:41Z + + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_video_dwidth_converter_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_video_dwidth_converter_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/hdl/axis_video_dwidth_converter_v1_0.vhd b/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/hdl/axis_video_dwidth_converter_v1_0.vhd new file mode 100644 index 0000000..723cbee --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/hdl/axis_video_dwidth_converter_v1_0.vhd @@ -0,0 +1,146 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity axis_video_dwidth_converter_v1_0 is +generic ( + C_DATA_WIDTH : integer := 32; + C_IN_TYPE : integer range 1 to 4 := 4; + C_OUT_TYPE : integer range 1 to 4 := 1 +); +port ( + axis_aclk : in STD_LOGIC; + axis_aresetn : in STD_LOGIC; + -- Ports of Axi Slave Bus Interface S_AXIS + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_IN_TYPE*C_DATA_WIDTH-1 downto 0); + s_axis_tuser : in STD_LOGIC; + s_axis_tlast : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + -- Ports of Axi Master Bus Interface M_AXIS + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC +); +end axis_video_dwidth_converter_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_video_dwidth_converter_v1_0 is +---------------------------------------------------------------------------------- +type sm_state_type is (ST_IDLE, ST_1W, ST_2W, ST_3W); +signal sm_state : sm_state_type := ST_IDLE; +signal tdata_buffer : STD_LOGIC_VECTOR((C_IN_TYPE-C_OUT_TYPE)*C_DATA_WIDTH-1 downto 0); +signal tlast_buffer : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +bypass_gen: if ((C_IN_TYPE = 1) and (C_OUT_TYPE = 1))generate +begin + m_axis_tvalid <= s_axis_tvalid; + m_axis_tdata <= s_axis_tdata; + m_axis_tuser <= s_axis_tuser; + m_axis_tlast <= s_axis_tlast; + s_axis_tready <= m_axis_tready; +end generate; +---------------------------------------------------------------------------------- +repack_gen: if ((C_IN_TYPE /= 1) or (C_OUT_TYPE /= 1)) generate +begin + process(sm_state, s_axis_tvalid) + begin + case sm_state is + when ST_IDLE => m_axis_tvalid <= s_axis_tvalid; + when ST_1W => m_axis_tvalid <= '1'; + when ST_2W => m_axis_tvalid <= '1'; + when ST_3W => m_axis_tvalid <= '1'; + end case; + end process; + + process(sm_state, s_axis_tuser) + begin + case sm_state is + when ST_IDLE => m_axis_tuser <= s_axis_tuser; + when ST_1W => m_axis_tuser <= '0'; + when ST_2W => m_axis_tuser <= '0'; + when ST_3W => m_axis_tuser <= '0'; + end case; + end process; + + process(sm_state, s_axis_tuser) + begin + case sm_state is + when ST_IDLE => m_axis_tlast <= '0'; + when ST_1W => + if(C_OUT_TYPE = 2)then + m_axis_tlast <= tlast_buffer; + else + m_axis_tlast <= '0'; + end if; + when ST_2W => m_axis_tlast <= '0'; + when ST_3W => m_axis_tlast <= tlast_buffer; + end case; + end process; + + out_1p_gen: if C_OUT_TYPE = 1 generate + begin + process(sm_state, s_axis_tdata, tdata_buffer) + begin + case sm_state is + when ST_IDLE => m_axis_tdata <= s_axis_tdata(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + when ST_1W => m_axis_tdata <= tdata_buffer(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + when ST_2W => m_axis_tdata <= tdata_buffer(C_OUT_TYPE*C_DATA_WIDTH*2-1 downto C_OUT_TYPE*C_DATA_WIDTH*1); + when ST_3W => m_axis_tdata <= tdata_buffer(C_OUT_TYPE*C_DATA_WIDTH*3-1 downto C_OUT_TYPE*C_DATA_WIDTH*2); + end case; + end process; + end generate; + + out_2p_gen: if C_OUT_TYPE = 2 generate + begin + process(sm_state, s_axis_tdata, tdata_buffer) + begin + case sm_state is + when ST_IDLE => m_axis_tdata <= s_axis_tdata(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + when ST_1W => m_axis_tdata <= tdata_buffer(C_OUT_TYPE*C_DATA_WIDTH-1 downto 0); + when others => null; + end case; + end process; + end generate; + + process(axis_aclk) + begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_state is + when ST_IDLE => + if((s_axis_tvalid = '1') and (m_axis_tready = '1'))then + tdata_buffer <= s_axis_tdata(s_axis_tdata'left downto C_OUT_TYPE*C_DATA_WIDTH); + tlast_buffer <= s_axis_tlast; + sm_state <= ST_1W; + end if; + when ST_1W => + if(m_axis_tready = '1')then + if(C_OUT_TYPE = 2)then + sm_state <= ST_IDLE; + else + sm_state <= ST_2W; + end if; + end if; + when ST_2W => + if(m_axis_tready = '1')then + sm_state <= ST_3W; + end if; + when ST_3W => + if(m_axis_tready = '1')then + sm_state <= ST_IDLE; + end if; + end case; + end if; + end process; + + s_axis_tready <= m_axis_tready when sm_state = ST_IDLE else '0'; +end generate; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/xgui/axis_video_dwidth_converter_v1_0.tcl b/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/xgui/axis_video_dwidth_converter_v1_0.tcl new file mode 100644 index 0000000..6b5cb6a --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_video_dwidth_converter_1.0/xgui/axis_video_dwidth_converter_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_IN_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_OUT_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_DATA_WIDTH" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.C_DATA_WIDTH { PARAM_VALUE.C_DATA_WIDTH } { + # Procedure called to update C_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_DATA_WIDTH { PARAM_VALUE.C_DATA_WIDTH } { + # Procedure called to validate C_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to update C_IN_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to validate C_IN_TYPE + return true +} + +proc update_PARAM_VALUE.C_OUT_TYPE { PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to update C_OUT_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_OUT_TYPE { PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to validate C_OUT_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.C_IN_TYPE { MODELPARAM_VALUE.C_IN_TYPE PARAM_VALUE.C_IN_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IN_TYPE}] ${MODELPARAM_VALUE.C_IN_TYPE} +} + +proc update_MODELPARAM_VALUE.C_OUT_TYPE { MODELPARAM_VALUE.C_OUT_TYPE PARAM_VALUE.C_OUT_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_OUT_TYPE}] ${MODELPARAM_VALUE.C_OUT_TYPE} +} + +proc update_MODELPARAM_VALUE.C_DATA_WIDTH { MODELPARAM_VALUE.C_DATA_WIDTH PARAM_VALUE.C_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_DATA_WIDTH}] ${MODELPARAM_VALUE.C_DATA_WIDTH} +} + diff --git a/zynqberrydemo3/ip_lib/axis_video_resize_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/axis_video_resize_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_video_resize_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/axis_video_resize_1.0/component.xml b/zynqberrydemo3/ip_lib/axis_video_resize_1.0/component.xml new file mode 100644 index 0000000..8183acb --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_video_resize_1.0/component.xml @@ -0,0 +1,521 @@ + + + trenz.biz + user + axis_video_resize + 1.0 + + + S_AXIS + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + TUSER + + + s_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + TUSER + + + m_axis_tuser + + + + + + WIZ_DATA_WIDTH + 32 + + + + + axis_aresetn + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + axis_aclk + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + S_AXIS:M_AXIS + + + ASSOCIATED_RESET + axis_aresetn + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + axis_video_resize_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 3d0341d7 + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + axis_video_resize_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + 3d0341d7 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b9a712e9 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + s_axis_tdata + + in + + 31 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tuser + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tlast + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tvalid + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + s_axis_tready + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_HORISONTAL_RES + C Horisontal Res + 1280 + + + C_VERTICAL_RES + C Vertical Res + 720 + + + C_IN_TYPE + C In Type + 1 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_719c03b1 + 1 + 4 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/axis_video_resize_v1_0.vhd + vhdlSource + CHECKSUM_3d0341d7 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/axis_video_resize_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/axis_video_resize_v1_0.tcl + tclSource + CHECKSUM_ea8138be + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + Resize video stream + + + Component_Name + axis_video_resize_v1_0 + + + C_HORISONTAL_RES + Horisontal Resolution + 1280 + + + C_VERTICAL_RES + Vertical Resolution + 720 + + + C_IN_TYPE + Input Type + 1 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /AXI_Peripheral + /Video_&_Image_Processing + + Video Resize v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 5 + + xilinx.com:user:axis_video_resize:1.0 + + 2017-05-16T12:54:08Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/axis_video_resize_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/axis_video_resize_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/axis_video_resize_1.0/hdl/axis_video_resize_v1_0.vhd b/zynqberrydemo3/ip_lib/axis_video_resize_1.0/hdl/axis_video_resize_v1_0.vhd new file mode 100644 index 0000000..a70a46e --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_video_resize_1.0/hdl/axis_video_resize_v1_0.vhd @@ -0,0 +1,115 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity axis_video_resize_v1_0 is +generic ( + C_IN_TYPE : integer range 1 to 4 := 1; + C_HORISONTAL_RES : integer := 1280; + C_VERTICAL_RES : integer := 720 +); +port ( + axis_aclk : in STD_LOGIC; + axis_aresetn : in STD_LOGIC; + -- Ports of Axi Slave Bus Interface S_AXIS + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_IN_TYPE*32-1 downto 0); + s_axis_tuser : in STD_LOGIC; + s_axis_tlast : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + + -- Ports of Axi Master Bus Interface M_AXIS + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_IN_TYPE*32-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC + ); +end axis_video_resize_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of axis_video_resize_v1_0 is +---------------------------------------------------------------------------------- +signal hor_cnt : UNSIGNED(15 downto 0); +signal ver_cnt : UNSIGNED(15 downto 0); +type sm_state_type is (ST_IDLE, ST_HOR_LINE, ST_HOR_CROP); +signal sm_state : sm_state_type := ST_IDLE; +signal vert_pass : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +s_axis_tready <= m_axis_tready; +m_axis_tdata <= s_axis_tdata; +m_axis_tuser <= s_axis_tuser; +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + case sm_state is + when ST_IDLE => -- Wait for start of frame + vert_pass <= '1'; + ver_cnt <= TO_UNSIGNED(0,16); + hor_cnt <= TO_UNSIGNED(C_IN_TYPE,16); + if((s_axis_tvalid = '1') and (m_axis_tready = '1') and (s_axis_tuser = '1'))then + sm_state <= ST_HOR_LINE; + end if; + when ST_HOR_LINE => + if((s_axis_tvalid = '1') and (m_axis_tready = '1'))then + if(s_axis_tuser = '1')then + ver_cnt <= TO_UNSIGNED(0,16); + vert_pass <= '1'; + elsif(s_axis_tlast = '1')then + if(ver_cnt >= TO_UNSIGNED((C_VERTICAL_RES-1),16))then + vert_pass <= '0'; + end if; + ver_cnt <= ver_cnt + 1; + end if; + + if(s_axis_tlast = '1')then + hor_cnt <= TO_UNSIGNED(0,16); + else + if(hor_cnt >= TO_UNSIGNED((C_HORISONTAL_RES - C_IN_TYPE),16))then + sm_state <= ST_HOR_CROP; + end if; + hor_cnt <= hor_cnt + TO_UNSIGNED(C_IN_TYPE, 16); + end if; + end if; + when ST_HOR_CROP => + if((s_axis_tvalid = '1') and (m_axis_tready = '1') and (s_axis_tlast = '1'))then + hor_cnt <= TO_UNSIGNED(0,16); + sm_state <= ST_HOR_LINE; + if(ver_cnt >= TO_UNSIGNED((C_VERTICAL_RES-1),16))then + vert_pass <= '0'; + end if; + ver_cnt <= ver_cnt + 1; + end if; + end case; + end if; +end process; + +process(sm_state, s_axis_tvalid, s_axis_tuser, vert_pass) +begin + case sm_state is + when ST_IDLE => m_axis_tvalid <= s_axis_tvalid and s_axis_tuser; + when ST_HOR_LINE => m_axis_tvalid <= s_axis_tvalid and (vert_pass or s_axis_tuser); + when ST_HOR_CROP => m_axis_tvalid <= '0'; + end case; +end process; + +process(sm_state, hor_cnt) +begin + case sm_state is + when ST_IDLE => m_axis_tlast <= '0'; + when ST_HOR_LINE => + if(hor_cnt >= TO_UNSIGNED((C_HORISONTAL_RES - C_IN_TYPE),16))then + m_axis_tlast <= '1'; + else + m_axis_tlast <= '0'; + end if; + when ST_HOR_CROP => m_axis_tlast <= '0'; + end case; +end process; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/axis_video_resize_1.0/xgui/axis_video_resize_v1_0.tcl b/zynqberrydemo3/ip_lib/axis_video_resize_1.0/xgui/axis_video_resize_v1_0.tcl new file mode 100644 index 0000000..75490a1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/axis_video_resize_1.0/xgui/axis_video_resize_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_IN_TYPE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_HORISONTAL_RES" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_VERTICAL_RES" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_HORISONTAL_RES { PARAM_VALUE.C_HORISONTAL_RES } { + # Procedure called to update C_HORISONTAL_RES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_HORISONTAL_RES { PARAM_VALUE.C_HORISONTAL_RES } { + # Procedure called to validate C_HORISONTAL_RES + return true +} + +proc update_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to update C_IN_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IN_TYPE { PARAM_VALUE.C_IN_TYPE } { + # Procedure called to validate C_IN_TYPE + return true +} + +proc update_PARAM_VALUE.C_VERTICAL_RES { PARAM_VALUE.C_VERTICAL_RES } { + # Procedure called to update C_VERTICAL_RES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_VERTICAL_RES { PARAM_VALUE.C_VERTICAL_RES } { + # Procedure called to validate C_VERTICAL_RES + return true +} + + +proc update_MODELPARAM_VALUE.C_HORISONTAL_RES { MODELPARAM_VALUE.C_HORISONTAL_RES PARAM_VALUE.C_HORISONTAL_RES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_HORISONTAL_RES}] ${MODELPARAM_VALUE.C_HORISONTAL_RES} +} + +proc update_MODELPARAM_VALUE.C_VERTICAL_RES { MODELPARAM_VALUE.C_VERTICAL_RES PARAM_VALUE.C_VERTICAL_RES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_VERTICAL_RES}] ${MODELPARAM_VALUE.C_VERTICAL_RES} +} + +proc update_MODELPARAM_VALUE.C_IN_TYPE { MODELPARAM_VALUE.C_IN_TYPE PARAM_VALUE.C_IN_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IN_TYPE}] ${MODELPARAM_VALUE.C_IN_TYPE} +} + diff --git a/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/component.xml b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/component.xml new file mode 100644 index 0000000..c91798f --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/component.xml @@ -0,0 +1,1035 @@ + + + trenz.biz + user + csi2_d_phy_rx + 1.0 + + + RX_MIPI_PPI + RX_MIPI_PPI + RX_MIPI_PPI + + + + + + + DL1_RXACTIVEHS + + + dl1_rxactivehs + + + + + CL_ENABLE + + + cl_enable + + + + + DL1_RXDATAHS + + + dl1_datahs + + + + + CL_STOPSTATE + + + cl_stopstate + + + + + DL0_RXSYNCHS + + + dl0_rxsynchs + + + + + DL1_RXVALIDHS + + + dl1_rxvalidhs + + + + + DL0_RXACTIVEHS + + + dl0_rxactivehs + + + + + DL1_RXSYNCHS + + + dl1_rxsynchs + + + + + CL_RXCLKACTIVEHS + + + cl_rxclkactivehs + + + + + DL0_ENABLE + + + dl0_enable + + + + + DL0_RXDATAHS + + + dl0_datahs + + + + + DL1_ENABLE + + + dl1_enable + + + + + DL0_RXVALIDHS + + + dl0_rxvalidhs + + + + + DL2_RXSYNCHS + + + dl2_rxsynchs + + + + + DL3_RXACTIVEHS + + + dl3_rxactivehs + + + + + DL3_RXDATAHS + + + dl3_datahs + + + + + DL2_RXDATAHS + + + dl2_datahs + + + + + DL3_RXSYNCHS + + + dl3_rxsynchs + + + + + DL3_RXVALIDHS + + + dl3_rxvalidhs + + + + + DL3_ENABLE + + + dl3_enable + + + + + DL2_RXVALIDHS + + + dl2_rxvalidhs + + + + + DL2_RXACTIVEHS + + + dl2_rxactivehs + + + + + DL2_ENABLE + + + dl2_enable + + + + + + in_delay_clk + + + + + + + CLK + + + in_delay_clk + + + + + + data_err + + + + + + + ACK + + + trig_ack + + + + + TRIG + + + trig_req + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + csi2_d_phy_rx + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 705bfa8d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + csi2_d_phy_rx + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f9df0448 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b6781f17 + + + + + + + in_delay_clk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + clk_rxp + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_rxn + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_rxp + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_rxn + + in + + 1 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_lp_p + + in + + 0 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + true + + + + + + data_lp_n + + in + + 0 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + + true + + + + + + trig_req + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + trig_ack + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rxbyteclkhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cl_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + cl_stopstate + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cl_rxclkactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl0_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + dl0_rxactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl0_rxvalidhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl0_rxsynchs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl0_datahs + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl1_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x1 + + + + + dl1_rxactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl1_rxvalidhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl1_rxsynchs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl1_datahs + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl2_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + dl2_rxactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl2_rxvalidhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl2_rxsynchs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl2_datahs + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl3_enable + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + dl3_rxactivehs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl3_rxvalidhs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl3_rxsynchs + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dl3_datahs + + out + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_NUM_LANES + C Num Lanes + 2 + + + C_NUM_LP_LANES + C Num Lp Lanes + 1 + + + C_D0_SWAP + C D0 Swap + FALSE + + + C_D1_SWAP + C D1 Swap + FALSE + + + C_D2_SWAP + C D2 Swap + FALSE + + + C_D3_SWAP + C D3 Swap + FALSE + + + C_DIFF_TERM + C Diff Term + FALSE + + + C_ADD_IDELAYCTRL + C Add Idelayctrl + FALSE + + + C_IODELAY_GROUP + C Iodelay Group + csi_dly_grp + + + C_USE_DELAY + C Use Delay + TRUE + + + C_CALIB_WAIT + C Calib Wait + 2047 + + + C_RATE_LIMIT + C Rate Limit + 10 + + + + + + choice_list_e6469819 + 1 + 2 + 4 + + + choice_list_f5166eba + 0 + 1 + 2 + 4 + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/csi2_d_phy_rx.xdc + xdc + USED_IN_implementation + USED_IN_synthesis + + + hdl/phy_clock_system.vhd + vhdlSource + + + hdl/line_if.vhd + vhdlSource + + + hdl/csi2_d_phy_rx.vhd + vhdlSource + CHECKSUM_8021b24b + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/phy_clock_system.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/line_if.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/csi2_d_phy_rx.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/csi2_d_phy_rx_v1_0.tcl + tclSource + CHECKSUM_30433af4 + XGUI_VERSION_2 + + + + CSI-2 D-PHY RX Interface + + + C_NUM_LANES + Data Lanes + 2 + + + C_NUM_LP_LANES + LP Lanes + 1 + + + C_D0_SWAP + D0 P/N Swap + FALSE + + + C_D1_SWAP + D1 P/N Swap + FALSE + + + C_D2_SWAP + D2 P/N Swap + FALSE + + + C_D3_SWAP + D3 P/N Swap + FALSE + + + C_DIFF_TERM + Add Differential Termination + FALSE + + + C_ADD_IDELAYCTRL + Add Idelayctrl + FALSE + + + C_IODELAY_GROUP + Iodelay Group Name + csi_dly_grp + + + Component_Name + csi2_d_phy_rx_v1_0 + + + C_USE_DELAY + Use Delay + TRUE + + + C_CALIB_WAIT + Calibration Cycle + 2047 + + + C_RATE_LIMIT + Error Rate Limit + 10 + + + + + + virtex7 + artix7 + kintex7 + zynq + qzynq + + + /UserIP + /Video_&_Image_Processing + + CSI-2 D-PHY RX v1_0 + Trenz Electronic GmbH + http://www.trenz.biz + 35 + + xilinx.com:user:csi2_d_phy_rx:1.0 + + 2017-05-24T13:20:36Z + + + b:/cores/2015.4/design/te0726/demo/ip_lib/csi2_d_phy_rx_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/csi2_d_phy_rx_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.vhd b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.vhd new file mode 100644 index 0000000..0d0bf83 --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.vhd @@ -0,0 +1,293 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use ieee.numeric_std.all; +Library UNISIM; +use UNISIM.vcomponents.all; +---------------------------------------------------------------------------------- +entity csi2_d_phy_rx is +generic ( + C_NUM_LANES : integer range 1 to 4 := 2; -- Number of data lanes + C_NUM_LP_LANES : integer range 0 to 4 := 1; -- Number of lanes that support LP input + C_D0_SWAP : BOOLEAN := FALSE; + C_D1_SWAP : BOOLEAN := FALSE; + C_D2_SWAP : BOOLEAN := FALSE; + C_D3_SWAP : BOOLEAN := FALSE; + ------------------------------------------------------------------------------- + C_USE_DELAY : BOOLEAN := TRUE; + C_DIFF_TERM : BOOLEAN := FALSE; + C_ADD_IDELAYCTRL : BOOLEAN := FALSE; + C_IODELAY_GROUP : STRING := "csi_dly_grp"; + C_CALIB_WAIT : INTEGER := 2047; + C_RATE_LIMIT : INTEGER := 10 +); +port ( + in_delay_clk : in STD_LOGIC; + -- Camera physical interface + clk_rxp : in STD_LOGIC; + clk_rxn : in STD_LOGIC; + data_rxp : in STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); + data_rxn : in STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); + data_lp_p : in STD_LOGIC_VECTOR(C_NUM_LP_LANES-1 downto 0); + data_lp_n : in STD_LOGIC_VECTOR(C_NUM_LP_LANES-1 downto 0); + -- Calibration + trig_req : in STD_LOGIC; + trig_ack : out STD_LOGIC; + -- MIPI PPI + rxbyteclkhs : out STD_LOGIC; -- Main byte clock bitrate/8 + cl_enable : in STD_LOGIC := '1'; -- PPI ShutDown ? + cl_stopstate : out STD_LOGIC; -- PPI StopState + cl_rxclkactivehs : out STD_LOGIC; -- optional, PPI RxClkActiveHS + dl0_enable : in STD_LOGIC; + dl0_rxactivehs : out STD_LOGIC; + dl0_rxvalidhs : out STD_LOGIC; + dl0_rxsynchs : out STD_LOGIC; + dl0_datahs : out STD_LOGIC_VECTOR(7 downto 0); + dl1_enable : in STD_LOGIC; + dl1_rxactivehs : out STD_LOGIC; + dl1_rxvalidhs : out STD_LOGIC; + dl1_rxsynchs : out STD_LOGIC; + dl1_datahs : out STD_LOGIC_VECTOR(7 downto 0); + dl2_enable : in STD_LOGIC; + dl2_rxactivehs : out STD_LOGIC; + dl2_rxvalidhs : out STD_LOGIC; + dl2_rxsynchs : out STD_LOGIC; + dl2_datahs : out STD_LOGIC_VECTOR(7 downto 0); + dl3_enable : in STD_LOGIC; + dl3_rxactivehs : out STD_LOGIC; + dl3_rxvalidhs : out STD_LOGIC; + dl3_rxsynchs : out STD_LOGIC; + dl3_datahs : out STD_LOGIC_VECTOR(7 downto 0) +); +end csi2_d_phy_rx; +---------------------------------------------------------------------------------- +architecture Behavioral of csi2_d_phy_rx is +---------------------------------------------------------------------------------- +component phy_clock_system is +generic ( + C_USE_DELAY : BOOLEAN := FALSE; + C_DIFF_TERM : BOOLEAN := FALSE; + C_IODELAY_GROUP : STRING := "csi_dly_grp"; + C_CALIB_WAIT : INTEGER := 2047; + C_ACC_LIMIT : INTEGER := 100000; + C_RATE_LIMIT : INTEGER := 5 +); +port ( + clock_upd_req : in STD_LOGIC; + clock_upd_ack : out STD_LOGIC; + in_clk_p : in STD_LOGIC; + in_clk_n : in STD_LOGIC; + in_ref_clk : in STD_LOGIC; + out_dclk : out STD_LOGIC; + out_pclk : out STD_LOGIC; + out_uclk : out STD_LOGIC +); +end component; + +component line_if is +generic ( + C_DIFF_TERM : BOOLEAN := FALSE +); +port ( + in_d_p : in STD_LOGIC; + in_d_n : in STD_LOGIC; + in_pclk : in STD_LOGIC; + in_dclk : in STD_LOGIC; + in_rst : in STD_LOGIC; + out_data : out STD_LOGIC_VECTOR(7 downto 0) +); +end component; +---------------------------------------------------------------------------------- +constant C_ACC_LIMIT : INTEGER := 1000000; +attribute IODELAY_GROUP : STRING; +signal rst_iserdes : STD_LOGIC; +signal dclk : STD_LOGIC; +signal pclk : STD_LOGIC; +signal uclk : STD_LOGIC; +signal prev_raw_valid : STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); +signal line_raw_sync : STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); +signal line_raw_out : STD_LOGIC_VECTOR(C_NUM_LANES*8-1 downto 0); +signal raw_valid : STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); +signal raw_fe_data : STD_LOGIC_VECTOR(C_NUM_LANES*8-1 downto 0); +signal raw_fe_valid : STD_LOGIC_VECTOR(C_NUM_LANES-1 downto 0); +signal swap_vec : STD_LOGIC_VECTOR(3 downto 0); +signal clock_upd_req : STD_LOGIC; +signal clock_upd_ack : STD_LOGIC; +signal data_err_i : UNSIGNED(C_NUM_LANES-1 downto 0); +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +swap_vec(0) <= '1' when C_D0_SWAP = TRUE else '0'; +swap_vec(1) <= '1' when C_D1_SWAP = TRUE else '0'; +swap_vec(2) <= '1' when C_D2_SWAP = TRUE else '0'; +swap_vec(3) <= '1' when C_D3_SWAP = TRUE else '0'; +---------------------------------------------------------------------------------- +IDELAYCTRL_gen: if (C_ADD_IDELAYCTRL = TRUE) and (C_USE_DELAY = TRUE) generate +attribute IODELAY_GROUP of IdlyCtrl_inst_0 : label is C_IODELAY_GROUP; +begin + IdlyCtrl_inst_0 : IDELAYCTRL + port map ( + REFCLK => in_delay_clk, + RST => '0', + RDY => open + ); +end generate; +---------------------------------------------------------------------------------- +process(in_delay_clk) +begin + if(in_delay_clk = '1' and in_delay_clk'event)then + clock_upd_req <= trig_req; + end if; +end process; +---------------------------------------------------------------------------------- +clock_system_inst: phy_clock_system +generic map( + C_USE_DELAY => C_USE_DELAY, + C_DIFF_TERM => C_DIFF_TERM, + C_IODELAY_GROUP => C_IODELAY_GROUP, + C_CALIB_WAIT => C_CALIB_WAIT, + C_ACC_LIMIT => C_ACC_LIMIT, + C_RATE_LIMIT => C_RATE_LIMIT +) +port map( + clock_upd_req => clock_upd_req, + clock_upd_ack => clock_upd_ack, + in_clk_p => clk_rxp, + in_clk_n => clk_rxn, + in_ref_clk => in_delay_clk, + out_dclk => dclk, + out_pclk => pclk, + out_uclk => uclk +); +rst_iserdes <= '0'; + +bits_gen: for i in 0 to C_NUM_LANES-1 generate +begin + line_if_inst: line_if + generic map( + C_DIFF_TERM => C_DIFF_TERM + ) + port map( + in_d_p => data_rxp(i), + in_d_n => data_rxn(i), + in_pclk => pclk, + in_dclk => dclk, + in_rst => rst_iserdes, + out_data => line_raw_out(i*8+7 downto i*8) + ); +end generate; + +without_lp_gen: if C_NUM_LP_LANES = 0 generate +begin + raw_valid <= (others => '1'); + line_raw_sync <= (others => '0'); +end generate; + +with_lp_gen: if C_NUM_LP_LANES > 0 generate +begin +process(pclk) +begin + if(pclk = '1' and pclk'event)then + for i in 0 to C_NUM_LP_LANES-1 loop + raw_valid(i) <= not (data_lp_p(i) or data_lp_n(i)); + prev_raw_valid(i) <= raw_valid(i); + if((prev_raw_valid(i) = '0') and ((data_lp_p(i) or data_lp_n(i)) = '0'))then + line_raw_sync(i) <= '1'; + else + line_raw_sync(i) <= '0'; + end if; + end loop; + end if; +end process; + +ext_lp_gen: if C_NUM_LP_LANES < C_NUM_LANES generate +begin + process(pclk) + begin + if(pclk = '1' and pclk'event)then + for i in C_NUM_LP_LANES to C_NUM_LANES-1 loop + raw_valid(i) <= not (data_lp_p(0) or data_lp_n(0)); + prev_raw_valid(i) <= raw_valid(i); + if((prev_raw_valid(i) = '0') and ((data_lp_p(0) or data_lp_n(0)) = '0'))then + line_raw_sync(i) <= '1'; + else + line_raw_sync(i) <= '0'; + end if; + end loop; + end if; + end process; +end generate; +end generate; + +process(uclk) +begin + if(uclk = '0' and uclk'event)then + for i in 0 to C_NUM_LANES-1 loop + if(swap_vec(i) = '0')then + raw_fe_data(i*8+7 downto i*8) <= line_raw_out(i*8+7 downto i*8); + else + raw_fe_data(i*8+7 downto i*8) <= not line_raw_out(i*8+7 downto i*8); + end if; + end loop; + raw_fe_valid <= raw_valid; + end if; +end process; + +process(uclk) +begin + if(uclk = '1' and uclk'event)then + dl0_rxvalidhs <= raw_fe_valid(0); + dl0_rxactivehs <= raw_fe_valid(0); + dl0_datahs <= raw_fe_data(7 downto 0); + dl0_rxsynchs <= line_raw_sync(0); + end if; +end process; + +lane_1_gen: if C_NUM_LANES > 1 generate +begin + process(uclk) + begin + if(uclk = '1' and uclk'event)then + dl1_rxvalidhs <= raw_fe_valid(1); + dl1_rxactivehs <= raw_fe_valid(1); + dl1_datahs <= raw_fe_data(15 downto 8); + dl1_rxsynchs <= line_raw_sync(1); + end if; + end process; +end generate; + +lane_2_gen: if C_NUM_LANES > 2 generate +begin + process(uclk) + begin + if(uclk = '1' and uclk'event)then + dl2_rxvalidhs <= raw_fe_valid(2); + dl2_rxactivehs <= raw_fe_valid(2); + dl2_datahs <= raw_fe_data(23 downto 16); + dl2_rxsynchs <= line_raw_sync(2); + end if; + end process; +end generate; + +lane_3_gen: if C_NUM_LANES > 3 generate +begin + process(uclk) + begin + if(uclk = '1' and uclk'event)then + dl3_rxvalidhs <= raw_fe_valid(3); + dl3_rxactivehs <= raw_fe_valid(3); + dl3_datahs <= raw_fe_data(31 downto 24); + dl3_rxsynchs <= line_raw_sync(3); + end if; + end process; +end generate; + +rxbyteclkhs <= uclk; -- Main byte clock bitrate/8 +cl_stopstate <= '0'; -- PPI StopState +cl_rxclkactivehs <= '1'; -- optional, PPI RxClkActiveHS +---------------------------------------------------------------------------------- +end Behavioral; + diff --git a/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.xdc b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.xdc new file mode 100644 index 0000000..c7c796f --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/csi2_d_phy_rx.xdc @@ -0,0 +1,4 @@ +set_false_path -from [get_pins clock_system_inst/invers_clk_s_reg/C] -to [get_pins clock_system_inst/dly_gen.BUFGCTRL_inst/S1] +set_false_path -from [get_pins clock_system_inst/invers_clk_c_reg/C] -to [get_pins clock_system_inst/dly_gen.BUFGCTRL_inst/CE1] +set_false_path -from [get_pins clock_system_inst/direct_clk_s_reg/C] -to [get_pins clock_system_inst/dly_gen.BUFGCTRL_inst/S0] +set_false_path -from [get_pins clock_system_inst/direct_clk_c_reg/C] -to [get_pins clock_system_inst/dly_gen.BUFGCTRL_inst/CE0] diff --git a/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/line_if.vhd b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/line_if.vhd new file mode 100644 index 0000000..0e879fb --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/line_if.vhd @@ -0,0 +1,97 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity line_if is +generic ( + C_DIFF_TERM : BOOLEAN := FALSE +); +port ( + in_d_p : in STD_LOGIC; + in_d_n : in STD_LOGIC; + in_pclk : in STD_LOGIC; + in_dclk : in STD_LOGIC; + in_rst : in STD_LOGIC; + out_data : out STD_LOGIC_VECTOR(7 downto 0) +); +end line_if; +---------------------------------------------------------------------------------- +architecture arch_imp of line_if is +---------------------------------------------------------------------------------- +signal data_s : STD_LOGIC; +signal data_iserdes : STD_LOGIC_VECTOR(7 downto 0); +signal dclk_n : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +d_ibufds_inst : IBUFDS +generic map ( + DIFF_TERM => C_DIFF_TERM +) +port map ( + I => in_d_p, + IB => in_d_n, + O => data_s +); + +dclk_n <= not in_dclk; +ISERDESE2_inst : ISERDESE2 +generic map ( + DATA_RATE => "DDR", -- DDR, SDR + DATA_WIDTH => 8, -- Parallel data width (2-8,10,14) + DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE) + DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE) + INIT_Q1 => '0', + INIT_Q2 => '0', + INIT_Q3 => '0', + INIT_Q4 => '0', + INTERFACE_TYPE => "NETWORKING", -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE + IOBDELAY => "NONE", -- NONE, BOTH, IBUF, IFD + NUM_CE => 2, -- Number of clock enables (1,2) + OFB_USED => "FALSE", -- Select OFB path (FALSE, TRUE) + SERDES_MODE => "MASTER", -- MASTER, SLAVE + SRVAL_Q1 => '0', + SRVAL_Q2 => '0', + SRVAL_Q3 => '0', + SRVAL_Q4 => '0' +) +port map ( + O => open, -- 1-bit output: Combinatorial output + Q1 => data_iserdes(7), + Q2 => data_iserdes(6), + Q3 => data_iserdes(5), + Q4 => data_iserdes(4), + Q5 => data_iserdes(3), + Q6 => data_iserdes(2), + Q7 => data_iserdes(1), + Q8 => data_iserdes(0), + SHIFTOUT1 => open, + SHIFTOUT2 => open, + BITSLIP => '0', -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to + CE1 => '1', + CE2 => '1', + CLKDIVP => '0', -- 1-bit input: TBD + CLK => in_dclk, -- 1-bit input: High-speed clock + CLKB => dclk_n, -- 1-bit input: High-speed secondary clock + CLKDIV => in_pclk, -- 1-bit input: Divided clock + OCLK => '0', -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" + DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion + DYNCLKSEL => '0', -- 1-bit input: Dynamic CLK/CLKB inversion + D => data_s, -- 1-bit input: Data input + DDLY => '0', -- 1-bit input: Serial data from IDELAYE2 + OFB => '0', -- 1-bit input: Data feedback from OSERDESE2 + OCLKB => '0', -- 1-bit input: High speed negative edge output clock + RST => in_rst, -- 1-bit input: Active high asynchronous reset + SHIFTIN1 => '0', + SHIFTIN2 => '0' +); + +out_data <= data_iserdes; +--------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/phy_clock_system.vhd b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/phy_clock_system.vhd new file mode 100644 index 0000000..942a2c1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/hdl/phy_clock_system.vhd @@ -0,0 +1,316 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity phy_clock_system is +generic ( + C_USE_DELAY : BOOLEAN := FALSE; + C_DIFF_TERM : BOOLEAN := FALSE; + C_IDELAY_TYPE : STRING := "FIXED"; + C_IODELAY_GROUP : STRING := "csi_dly_grp"; + C_ACC_LIMIT : INTEGER := 100000; + C_RATE_LIMIT : INTEGER := 5; + C_CALIB_WAIT : INTEGER := 2047 +); +port ( + -- Debug + --cntvalue_out : out STD_LOGIC_VECTOR(4 downto 0); + --state_out : out STD_LOGIC_VECTOR(3 downto 0); + + clock_upd_req : in STD_LOGIC; + clock_upd_ack : out STD_LOGIC; + in_clk_p : in STD_LOGIC; + in_clk_n : in STD_LOGIC; + in_ref_clk : in STD_LOGIC; + out_dclk : out STD_LOGIC; + out_pclk : out STD_LOGIC; + out_uclk : out STD_LOGIC +); +end phy_clock_system; +---------------------------------------------------------------------------------- +architecture arch_imp of phy_clock_system is +---------------------------------------------------------------------------------- +attribute IODELAY_GROUP : STRING; +---------------------------------------------------------------------------------- +signal clk_g : STD_LOGIC; -- Clock after IBUFGDS +signal clk_d : STD_LOGIC; -- Clock after IDELAYE2 +signal clk_dn : STD_LOGIC; -- Clock after IDELAYE2 +signal clk_dg : STD_LOGIC; -- Clock after IBUFGDS +signal clk_bufmr : STD_LOGIC; +signal clk_bufio : STD_LOGIC; +signal clk_bufr : STD_LOGIC; +signal rst_bufmr : STD_LOGIC; +type sm_state_type is (ST_CHECK, ST_FIND_GOOD, ST_GOOD_WAIT, + ST_FIND_BAD, ST_BAD_WAIT, ST_CALK_DLY, ST_SET_DLY, ST_SET_WAIT); +signal sm_state : sm_state_type; +signal wait_cnt : integer range 0 to C_CALIB_WAIT; +signal delay_ce : STD_LOGIC; +signal delay_rst : STD_LOGIC; +signal delay_set : STD_LOGIC; +signal delay_set_val : STD_LOGIC_VECTOR(4 downto 0); +signal curr_delay : UNSIGNED(4 downto 0); +signal start_dly : UNSIGNED(5 downto 0); +signal end_dly : UNSIGNED(5 downto 0); +signal sum_dly : UNSIGNED(5 downto 0); +signal invers_clk : STD_LOGIC := '0'; +signal direct_clk : STD_LOGIC := '1'; +signal direct_clk_s : STD_LOGIC; +signal invers_clk_s : STD_LOGIC := '0'; +signal direct_clk_c : STD_LOGIC; +signal invers_clk_c : STD_LOGIC := '0'; +signal req_i : STD_LOGIC; +signal err_sr : STD_LOGIC_VECTOR(1 downto 0); +signal acc_cnt : INTEGER range 0 to C_ACC_LIMIT-1; +signal acc_val : INTEGER range 0 to C_ACC_LIMIT-1; +signal err_rate : INTEGER range 0 to C_ACC_LIMIT-1; +---------------------------------------------------------------------------------- +attribute ASYNC_REG : string; +attribute ASYNC_REG of req_i : signal is "true"; +attribute keep : string; +attribute keep of direct_clk_s : signal is "true"; +attribute keep of direct_clk_c : signal is "true"; +attribute keep of invers_clk_s : signal is "true"; +attribute keep of invers_clk_c : signal is "true"; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +-- Test +clk_ibufgds_inst : IBUFGDS +generic map ( + DIFF_TERM => C_DIFF_TERM +) +port map ( + I => in_clk_p, + IB => in_clk_n, + O => clk_g +); + +process(in_ref_clk) +begin + if(in_ref_clk = '1' and in_ref_clk'event)then + direct_clk_s <= not invers_clk; + invers_clk_s <= invers_clk; + direct_clk_c <= not invers_clk; + invers_clk_c <= invers_clk; + end if; +end process; +--direct_clk <= not invers_clk; + +dly_gen: if C_USE_DELAY = TRUE generate +attribute IODELAY_GROUP of IDELAYE2_inst : label is C_IODELAY_GROUP; +begin + IDELAYE2_inst : IDELAYE2 + generic map ( + CINVCTRL_SEL => "FALSE", -- Enable dynamic clock inversion (FALSE, TRUE) + DELAY_SRC => "IDATAIN", -- Delay input (IDATAIN, DATAIN) + HIGH_PERFORMANCE_MODE => "TRUE", -- Reduced jitter ("TRUE"), Reduced power ("FALSE") + IDELAY_TYPE => "VAR_LOAD", -- FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE + IDELAY_VALUE => 0, -- Input delay tap setting (0-31) + PIPE_SEL => "FALSE", -- Select pipelined mode, FALSE, TRUE + REFCLK_FREQUENCY => 200.0, -- IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0). + SIGNAL_PATTERN => "CLOCK" -- DATA, CLOCK input signal + ) + port map ( + --CNTVALUEOUT => cntvalue_out,-- 5-bit output: Counter value output + CNTVALUEOUT => open, -- 5-bit output: Counter value output + DATAOUT => clk_d, -- 1-bit output: Delayed data output + C => in_ref_clk, -- 1-bit input: Clock input + CE => '0', -- 1-bit input: Active high enable increment/decrement input + CINVCTRL => '0', -- 1-bit input: Dynamic clock inversion input + CNTVALUEIN => delay_set_val, -- 5-bit input: Counter value input + DATAIN => '0', -- 1-bit input: Internal delay data input + IDATAIN => clk_g, -- 1-bit input: Data input from the I/O + INC => '1', -- 1-bit input: Increment / Decrement tap delay input + LD => delay_set, -- 1-bit input: Load IDELAY_VALUE input + LDPIPEEN => '0', -- 1-bit input: Enable PIPELINE register to load data input + REGRST => '0' -- 1-bit input: Active-high reset tap-delay input + ); + clk_dn <= not clk_d; + + BUFGCTRL_inst : BUFGCTRL + generic map ( + INIT_OUT => 0, -- Initial value of BUFGCTRL output (0/1) + PRESELECT_I0 => FALSE, -- BUFGCTRL output uses I0 input (TRUE/FALSE) + PRESELECT_I1 => FALSE -- BUFGCTRL output uses I1 input (TRUE/FALSE) + ) + port map ( + O => clk_dg, -- 1-bit output: Clock Output pin + CE0 => direct_clk_c, -- 1-bit input: Clock enable input for I0 input + CE1 => invers_clk_c, -- 1-bit input: Clock enable input for I1 input + I0 => clk_d, -- 1-bit input: Primary clock input + I1 => clk_dn, -- 1-bit input: Secondary clock input + IGNORE0 => '0', -- 1-bit input: Clock ignore input for I0 + IGNORE1 => '0', -- 1-bit input: Clock ignore input for I1 + S0 => direct_clk_s, -- 1-bit input: Clock select input for I0 + S1 => invers_clk_s -- 1-bit input: Clock select input for I1 + ); + + process(in_ref_clk) + begin + if(in_ref_clk = '1' and in_ref_clk'event)then + req_i <= clock_upd_req; + clock_upd_ack <= req_i; + err_sr <= err_sr(0) & req_i; + if(acc_cnt = C_ACC_LIMIT-1)then + acc_cnt <= 0; + err_rate <= acc_val; + acc_val <= 0; + else + if(err_sr = "01")then + acc_val <= acc_val + 1; + end if; + acc_cnt <= acc_cnt + 1; + end if; + end if; + end process; + + process(in_ref_clk) + begin + if(in_ref_clk = '1' and in_ref_clk'event)then + case sm_state is + when ST_CHECK => + if(err_rate > C_RATE_LIMIT)then + sm_state <= ST_GOOD_WAIT; + curr_delay <= (others => '0'); + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + else + delay_set <= '0'; + end if; + + when ST_FIND_GOOD => + if(req_i = '0')then -- We found start of the eye + sm_state <= ST_FIND_BAD; + start_dly <= resize(curr_delay,6); + else + if(curr_delay < TO_UNSIGNED(31,5))then + curr_delay <= curr_delay + 1; + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + sm_state <= ST_GOOD_WAIT; + else -- Data not found + invers_clk <= not invers_clk; + curr_delay <= (others => '0'); + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + sm_state <= ST_GOOD_WAIT; + end if; + end if; + + when ST_GOOD_WAIT => + delay_set <= '0'; + if(wait_cnt = 0)then + sm_state <= ST_FIND_GOOD; + else + wait_cnt <= wait_cnt - 1; + end if; + + when ST_FIND_BAD => + if((req_i = '1') or (curr_delay = TO_UNSIGNED(31,5)))then -- We found end of the eye + sm_state <= ST_CALK_DLY; + end_dly <= resize(curr_delay,6); + else + curr_delay <= curr_delay + 1; + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + sm_state <= ST_BAD_WAIT; + end if; + + when ST_BAD_WAIT => + delay_set <= '0'; + if(wait_cnt = 0)then + sm_state <= ST_FIND_BAD; + else + wait_cnt <= wait_cnt - 1; + end if; + + when ST_CALK_DLY => + sum_dly <= start_dly + end_dly; + sm_state <= ST_SET_DLY; + + when ST_SET_DLY => + curr_delay <= sum_dly(5 downto 1); + delay_set <= '1'; + wait_cnt <= C_CALIB_WAIT; + sm_state <= ST_SET_WAIT; + + when ST_SET_WAIT => + delay_set <= '0'; + if(wait_cnt = 0)then + sm_state <= ST_CHECK; + else + wait_cnt <= wait_cnt - 1; + end if; + end case; + end if; + end process; + delay_set_val <= STD_LOGIC_VECTOR(curr_delay); + + -- process(in_ref_clk) + -- begin + -- if(in_ref_clk = '1' and in_ref_clk'event)then + -- case sm_state is + -- when ST_CHECK => state_out <= x"0"; + -- when ST_FIND_GOOD => state_out <= x"2"; + -- when ST_GOOD_WAIT => state_out <= x"3"; + -- when ST_FIND_BAD => state_out <= x"4"; + -- when ST_BAD_WAIT => state_out <= x"5"; + -- when ST_CALK_DLY => state_out <= x"6"; + -- when ST_SET_DLY => state_out <= x"7"; + -- when ST_SET_WAIT => state_out <= x"8"; + -- end case; + -- end if; + -- end process; + +end generate; + +no_dly_gen: if C_USE_DELAY = FALSE generate +begin + clk_dg <= clk_g; +end generate; + +BUFMRCE_inst : BUFMRCE +generic map ( + CE_TYPE => "ASYNC", -- SYNC, ASYNC + INIT_OUT => 0 -- Initial output and stopped polarity, (0-1) +) +port map ( + O => clk_bufmr, -- 1-bit output: Clock output (connect to BUFIOs/BUFRs) + CE => '1', -- 1-bit input: Active high buffer enable + I => clk_dg -- 1-bit input: Clock input (Connect to IBUF) +); + +BUFIO_inst : BUFIO +port map ( + O => clk_bufio, -- 1-bit output: Clock output (connect to I/O clock loads). + I => clk_bufmr -- 1-bit input: Clock input (connect to an IBUF or BUFMR). +); +out_dclk <= clk_bufio; + +rst_bufmr <= '0'; +BUFR_inst : BUFR +generic map ( + BUFR_DIVIDE => "4", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" + SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES" +) +port map ( + O => clk_bufr, -- 1-bit output: Clock output port + CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only) + CLR => rst_bufmr, -- 1-bit input: Active high, asynchronous clear (Divided modes only) + I => clk_bufmr -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect +); +out_pclk <= clk_bufr; + +usr_BUFG_inst : BUFG +port map ( + O => out_uclk, -- 1-bit output: Clock output + I => clk_bufr -- 1-bit input: Clock input +); +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/xgui/csi2_d_phy_rx_v1_0.tcl b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/xgui/csi2_d_phy_rx_v1_0.tcl new file mode 100644 index 0000000..ad3c5bd --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi2_d_phy_rx_1.0/xgui/csi2_d_phy_rx_v1_0.tcl @@ -0,0 +1,198 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_NUM_LANES" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_NUM_LP_LANES" -parent ${Page_0} -widget comboBox + #Adding Group + set Camera_Interface [ipgui::add_group $IPINST -name "Camera Interface" -parent ${Page_0}] + ipgui::add_param $IPINST -name "C_DIFF_TERM" -parent ${Camera_Interface} + ipgui::add_param $IPINST -name "C_D0_SWAP" -parent ${Camera_Interface} + ipgui::add_param $IPINST -name "C_D1_SWAP" -parent ${Camera_Interface} + ipgui::add_param $IPINST -name "C_D2_SWAP" -parent ${Camera_Interface} + set C_D3_SWAP [ipgui::add_param $IPINST -name "C_D3_SWAP" -parent ${Camera_Interface}] + set_property tooltip {D3 P/N Swap} ${C_D3_SWAP} + + #Adding Group + set Clocking_System [ipgui::add_group $IPINST -name "Clocking System" -parent ${Page_0}] + ipgui::add_param $IPINST -name "C_USE_DELAY" -parent ${Clocking_System} + set C_IODELAY_GROUP [ipgui::add_param $IPINST -name "C_IODELAY_GROUP" -parent ${Clocking_System}] + set_property tooltip {Iodelay Group} ${C_IODELAY_GROUP} + ipgui::add_param $IPINST -name "C_ADD_IDELAYCTRL" -parent ${Clocking_System} + ipgui::add_param $IPINST -name "C_CALIB_WAIT" -parent ${Clocking_System} + ipgui::add_param $IPINST -name "C_RATE_LIMIT" -parent ${Clocking_System} + + + +} + +proc update_PARAM_VALUE.C_ADD_IDELAYCTRL { PARAM_VALUE.C_ADD_IDELAYCTRL } { + # Procedure called to update C_ADD_IDELAYCTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_ADD_IDELAYCTRL { PARAM_VALUE.C_ADD_IDELAYCTRL } { + # Procedure called to validate C_ADD_IDELAYCTRL + return true +} + +proc update_PARAM_VALUE.C_CALIB_WAIT { PARAM_VALUE.C_CALIB_WAIT } { + # Procedure called to update C_CALIB_WAIT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_CALIB_WAIT { PARAM_VALUE.C_CALIB_WAIT } { + # Procedure called to validate C_CALIB_WAIT + return true +} + +proc update_PARAM_VALUE.C_D0_SWAP { PARAM_VALUE.C_D0_SWAP } { + # Procedure called to update C_D0_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D0_SWAP { PARAM_VALUE.C_D0_SWAP } { + # Procedure called to validate C_D0_SWAP + return true +} + +proc update_PARAM_VALUE.C_D1_SWAP { PARAM_VALUE.C_D1_SWAP } { + # Procedure called to update C_D1_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D1_SWAP { PARAM_VALUE.C_D1_SWAP } { + # Procedure called to validate C_D1_SWAP + return true +} + +proc update_PARAM_VALUE.C_D2_SWAP { PARAM_VALUE.C_D2_SWAP } { + # Procedure called to update C_D2_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D2_SWAP { PARAM_VALUE.C_D2_SWAP } { + # Procedure called to validate C_D2_SWAP + return true +} + +proc update_PARAM_VALUE.C_D3_SWAP { PARAM_VALUE.C_D3_SWAP } { + # Procedure called to update C_D3_SWAP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_D3_SWAP { PARAM_VALUE.C_D3_SWAP } { + # Procedure called to validate C_D3_SWAP + return true +} + +proc update_PARAM_VALUE.C_DIFF_TERM { PARAM_VALUE.C_DIFF_TERM } { + # Procedure called to update C_DIFF_TERM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_DIFF_TERM { PARAM_VALUE.C_DIFF_TERM } { + # Procedure called to validate C_DIFF_TERM + return true +} + +proc update_PARAM_VALUE.C_IODELAY_GROUP { PARAM_VALUE.C_IODELAY_GROUP } { + # Procedure called to update C_IODELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_IODELAY_GROUP { PARAM_VALUE.C_IODELAY_GROUP } { + # Procedure called to validate C_IODELAY_GROUP + return true +} + +proc update_PARAM_VALUE.C_NUM_LANES { PARAM_VALUE.C_NUM_LANES } { + # Procedure called to update C_NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_NUM_LANES { PARAM_VALUE.C_NUM_LANES } { + # Procedure called to validate C_NUM_LANES + return true +} + +proc update_PARAM_VALUE.C_NUM_LP_LANES { PARAM_VALUE.C_NUM_LP_LANES } { + # Procedure called to update C_NUM_LP_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_NUM_LP_LANES { PARAM_VALUE.C_NUM_LP_LANES } { + # Procedure called to validate C_NUM_LP_LANES + return true +} + +proc update_PARAM_VALUE.C_RATE_LIMIT { PARAM_VALUE.C_RATE_LIMIT } { + # Procedure called to update C_RATE_LIMIT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_RATE_LIMIT { PARAM_VALUE.C_RATE_LIMIT } { + # Procedure called to validate C_RATE_LIMIT + return true +} + +proc update_PARAM_VALUE.C_USE_DELAY { PARAM_VALUE.C_USE_DELAY } { + # Procedure called to update C_USE_DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_USE_DELAY { PARAM_VALUE.C_USE_DELAY } { + # Procedure called to validate C_USE_DELAY + return true +} + + +proc update_MODELPARAM_VALUE.C_NUM_LANES { MODELPARAM_VALUE.C_NUM_LANES PARAM_VALUE.C_NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_NUM_LANES}] ${MODELPARAM_VALUE.C_NUM_LANES} +} + +proc update_MODELPARAM_VALUE.C_NUM_LP_LANES { MODELPARAM_VALUE.C_NUM_LP_LANES PARAM_VALUE.C_NUM_LP_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_NUM_LP_LANES}] ${MODELPARAM_VALUE.C_NUM_LP_LANES} +} + +proc update_MODELPARAM_VALUE.C_D0_SWAP { MODELPARAM_VALUE.C_D0_SWAP PARAM_VALUE.C_D0_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D0_SWAP}] ${MODELPARAM_VALUE.C_D0_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D1_SWAP { MODELPARAM_VALUE.C_D1_SWAP PARAM_VALUE.C_D1_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D1_SWAP}] ${MODELPARAM_VALUE.C_D1_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D2_SWAP { MODELPARAM_VALUE.C_D2_SWAP PARAM_VALUE.C_D2_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D2_SWAP}] ${MODELPARAM_VALUE.C_D2_SWAP} +} + +proc update_MODELPARAM_VALUE.C_D3_SWAP { MODELPARAM_VALUE.C_D3_SWAP PARAM_VALUE.C_D3_SWAP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_D3_SWAP}] ${MODELPARAM_VALUE.C_D3_SWAP} +} + +proc update_MODELPARAM_VALUE.C_DIFF_TERM { MODELPARAM_VALUE.C_DIFF_TERM PARAM_VALUE.C_DIFF_TERM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_DIFF_TERM}] ${MODELPARAM_VALUE.C_DIFF_TERM} +} + +proc update_MODELPARAM_VALUE.C_ADD_IDELAYCTRL { MODELPARAM_VALUE.C_ADD_IDELAYCTRL PARAM_VALUE.C_ADD_IDELAYCTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_ADD_IDELAYCTRL}] ${MODELPARAM_VALUE.C_ADD_IDELAYCTRL} +} + +proc update_MODELPARAM_VALUE.C_IODELAY_GROUP { MODELPARAM_VALUE.C_IODELAY_GROUP PARAM_VALUE.C_IODELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_IODELAY_GROUP}] ${MODELPARAM_VALUE.C_IODELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.C_USE_DELAY { MODELPARAM_VALUE.C_USE_DELAY PARAM_VALUE.C_USE_DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_USE_DELAY}] ${MODELPARAM_VALUE.C_USE_DELAY} +} + +proc update_MODELPARAM_VALUE.C_CALIB_WAIT { MODELPARAM_VALUE.C_CALIB_WAIT PARAM_VALUE.C_CALIB_WAIT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_CALIB_WAIT}] ${MODELPARAM_VALUE.C_CALIB_WAIT} +} + +proc update_MODELPARAM_VALUE.C_RATE_LIMIT { MODELPARAM_VALUE.C_RATE_LIMIT PARAM_VALUE.C_RATE_LIMIT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_RATE_LIMIT}] ${MODELPARAM_VALUE.C_RATE_LIMIT} +} + diff --git a/zynqberrydemo3/ip_lib/csi_to_axis_1.0/bd/bd.tcl b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/bd/bd.tcl new file mode 100644 index 0000000..690e4e1 --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/bd/bd.tcl @@ -0,0 +1,86 @@ + +proc init { cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + set full_sbusif_list [list ] + + foreach busif $all_busif { + if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { + set busif_param_list [list] + set busif_name [get_property NAME $busif] + if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { + continue + } + foreach tparam $axi_standard_param_list { + lappend busif_param_list "C_${busif_name}_${tparam}" + } + bd::mark_propagate_only $cell_handle $busif_param_list + } + } +} + + +proc pre_propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + if { $val_on_cell != "" } { + set_property CONFIG.${tparam} $val_on_cell $busif + } + } + } + } +} + + +proc propagate {cellpath otherInfo } { + + set cell_handle [get_bd_cells $cellpath] + set all_busif [get_bd_intf_pins $cellpath/*] + set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] + + foreach busif $all_busif { + if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { + continue + } + if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { + continue + } + + set busif_name [get_property NAME $busif] + foreach tparam $axi_standard_param_list { + set busif_param_name "C_${busif_name}_${tparam}" + + set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] + set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] + + if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { + #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. + if { $val_on_cell_intf_pin != "" } { + set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle + } + } + } + } +} + diff --git a/zynqberrydemo3/ip_lib/csi_to_axis_1.0/component.xml b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/component.xml new file mode 100644 index 0000000..f123cdd --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/component.xml @@ -0,0 +1,1180 @@ + + + trenz.biz + user + csi_to_axis + 1.0 + + + M_AXIS + + + + + + + TDATA + + + m_axis_tdata + + + + + TLAST + + + m_axis_tlast + + + + + TUSER + + + m_axis_tuser + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + WIZ_DATA_WIDTH + 32 + + + + + RX_MIPI_PPI + RX_MIPI_PPI + RX_MIPI_PPI + + + + + + + DL1_RXACTIVEHS + + + dl1_rxactivehs + + + + + DL0_RXSYNCHS + + + dl0_rxsynchs + + + + + DL1_RXVALIDHS + + + dl1_rxvalidhs + + + + + CL_ENABLE + + + cl_enable + + + + + DL1_RXDATAHS + + + dl1_datahs + + + + + DL0_RXACTIVEHS + + + dl0_rxactivehs + + + + + CL_STOPSTATE + + + cl_stopstate + + + + + DL1_RXSYNCHS + + + dl1_rxsynchs + + + + + DL0_ENABLE + + + dl0_enable + + + + + DL0_RXDATAHS + + + dl0_datahs + + + + + DL1_ENABLE + + + dl1_enable + + + + + DL0_RXVALIDHS + + + dl0_rxvalidhs + + + + + CL_RXCLKACTIVEHS + + + cl_rxclkactivehs + + + + + DL2_RXSYNCHS + + + dl2_rxsynchs + + + + + DL3_RXACTIVEHS + + + dl3_rxactivehs + + + + + DL3_RXDATAHS + + + dl3_datahs + + + + + DL2_RXDATAHS + + + dl2_datahs + + + + + DL3_RXSYNCHS + + + dl3_rxsynchs + + + + + DL3_RXVALIDHS + + + dl3_rxvalidhs + + + + + DL3_ENABLE + + + dl3_enable + + + + + DL2_RXVALIDHS + + + dl2_rxvalidhs + + + + + DL2_RXACTIVEHS + + + dl2_rxactivehs + + + + + DL2_ENABLE + + + dl2_enable + + + + + + m_axis_aresetn + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + M_AXIS + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + data_err + + + + + + + ACK + + + trig_ack + + + + + TRIG + + + trig_req + + + + + + + + + xilinx_vhdlsynthesis + VHDL Synthesis + vhdlSource:vivado.xilinx.com:synthesis + vhdl + csi_to_axis_v1_0 + + xilinx_vhdlsynthesis_view_fileset + + + + viewChecksum + 86b17c2f + + + + + xilinx_vhdlbehavioralsimulation + VHDL Simulation + vhdlSource:vivado.xilinx.com:simulation + vhdl + csi_to_axis_v1_0 + + xilinx_vhdlbehavioralsimulation_view_fileset + + + + viewChecksum + c5d94c0e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3bb3a441 + + + + + bd_tcl + Block Diagram + :vivado.xilinx.com:block.diagram + + bd_tcl_view_fileset + + + + viewChecksum + 16328387 + + + + + + + enable_in + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + rxbyteclkhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + cl_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + cl_stopstate + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + cl_rxclkactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl0_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + dl0_rxactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl0_rxvalidhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl0_rxsynchs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl0_datahs + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + dl1_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0x1 + + + + + + true + + + + + + dl1_rxactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + dl1_rxvalidhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + true + + + + + + dl1_rxsynchs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + dl1_datahs + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + true + + + + + + dl2_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + dl2_rxactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + dl2_rxvalidhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + dl2_rxsynchs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + dl2_datahs + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + dl3_enable + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + false + + + + + + dl3_rxactivehs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + dl3_rxvalidhs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + + false + + + + + + dl3_rxsynchs + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + dl3_datahs + + in + + 7 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 0 + + + + + + false + + + + + + trig_req + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + trig_ack + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + m_axis_tdata + + out + + 15 + 0 + + + + STD_LOGIC_VECTOR + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tuser + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tlast + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tvalid + + out + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_tready + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + 1 + + + + + m_axis_aclk + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + m_axis_aresetn + + in + + + STD_LOGIC + xilinx_vhdlsynthesis + xilinx_vhdlbehavioralsimulation + + + + + + + + C_M_AXIS_TDATA_WIDTH + C M AXIS TDATA WIDTH + Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + 32 + + + C_LANES + C Lanes + 2 + + + C_TIMEOUT + C Timeout + 127 + + + + + + choice_list_6fc15197 + 32 + + + choice_list_9d8b0d81 + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_e6469819 + 1 + 2 + 4 + + + + + xilinx_vhdlsynthesis_view_fileset + + hdl/csi_to_axis.xdc + xdc + USED_IN_implementation + USED_IN_synthesis + + + hdl/csi2_parser.vhd + vhdlSource + + + hdl/lane_align.vhd + vhdlSource + + + hdl/lane_merge.vhd + vhdlSource + + + hdl/csi_to_axis_v1_0.vhd + vhdlSource + CHECKSUM_9c64e067 + + + + xilinx_vhdlbehavioralsimulation_view_fileset + + hdl/csi2_parser.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/lane_align.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/lane_merge.vhd + vhdlSource + USED_IN_ipstatic + + + hdl/csi_to_axis_v1_0.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/csi_to_axis_v1_0.tcl + tclSource + CHECKSUM_67ac9fac + XGUI_VERSION_2 + + + + bd_tcl_view_fileset + + bd/bd.tcl + tclSource + + + + CSI-2 to AXI4-Stream + + + C_M_AXIS_TDATA_WIDTH + C M AXIS TDATA WIDTH + Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH. + 32 + + + + false + + + + + + Component_Name + csi_to_axis_v1_0 + + + C_LANES + Data Lanes + 2 + + + C_TIMEOUT + Line Align Timeout + 127 + + + + + + virtex7 + artix7 + kintex7 + zynq + qzynq + + + /AXI_Peripheral + /Video_&_Image_Processing + + CSI-2 to AXI4-Stream v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 46 + + xilinx.com:user:csi_to_axis:1.0 + + 2017-05-17T10:14:06Z + + b:/cores/2015.4/design/te0726/demo/ip_lib/csi_to_axis_1.0 + b:/cores/2016.4/design/TE0726/te0726_m_demo1/ip_lib/csi_to_axis_1.0 + + + + 2016.4 + + + + + + + + diff --git a/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi2_parser.vhd b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi2_parser.vhd new file mode 100644 index 0000000..6b76fdb --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi2_parser.vhd @@ -0,0 +1,147 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity csi2_parser is +generic( + C_LANES : INTEGER range 1 to 4 := 2 +); +port ( + enable_in : in STD_LOGIC; + resync_out : out STD_LOGIC; + axis_aclk : in STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + s_axis_tvalid : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + + frame_start_dbg : out STD_LOGIC; + line_start_dbg : out STD_LOGIC; + packet_id_dbg : out STD_LOGIC_VECTOR(7 downto 0); + packet_id_upd : out STD_LOGIC; + packet_size_dbg : out STD_LOGIC_VECTOR(15 downto 0); + transfer_cnt_dbg : out STD_LOGIC_VECTOR(15 downto 0) +); +end csi2_parser; +---------------------------------------------------------------------------------- +architecture arch_imp of csi2_parser is +---------------------------------------------------------------------------------- +constant C_SOT : STD_LOGIC_VECTOR(7 downto 0) := x"B8"; +constant C_RAW10 : STD_LOGIC_VECTOR(7 downto 0) := x"2B"; +constant C_EOF : STD_LOGIC_VECTOR(7 downto 0) := x"01"; +constant C_WAIT : INTEGER := 15; +---------------------------------------------------------------------------------- +type sm_state_type is (ST_IDLE, ST_HDRA, ST_HDRB, ST_TRANSFER, ST_RESYNC); +signal sm_state : sm_state_type := ST_IDLE; +---------------------------------------------------------------------------------- +signal packet_size : STD_LOGIC_VECTOR(15 downto 0); +signal packet_cs : STD_LOGIC_VECTOR( 7 downto 0); +signal packet_id : STD_LOGIC_VECTOR( 7 downto 0); +signal transfer_cnt : UNSIGNED(15 downto 0); +signal start_of_frame : STD_LOGIC; +signal start_of_line : STD_LOGIC; +signal enable_req : STD_LOGIC; +signal enable : STD_LOGIC; +signal wait_cnt : INTEGER range 0 to C_WAIT-1 := 0; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process(axis_aclk) +begin + if(axis_aclk = '1' and axis_aclk'event)then + m_axis_tdata <= s_axis_tdata; + enable_req <= enable_in; + case sm_state is + when ST_IDLE => + m_axis_tvalid <= '0'; + m_axis_tlast <= '0'; + packet_id_upd <= '0'; + if(s_axis_tvalid = '1')then + if((s_axis_tdata(7 downto 0) = C_SOT) and (s_axis_tdata(15 downto 8) = C_SOT))then + sm_state <= ST_HDRA; + else + sm_state <= ST_RESYNC; + end if; + end if; + when ST_RESYNC => + m_axis_tvalid <= '0'; + m_axis_tlast <= '0'; + if(s_axis_tvalid = '0')then + sm_state <= ST_IDLE; + end if; + when ST_HDRA => + if(s_axis_tvalid = '1')then + packet_size( 7 downto 0) <= s_axis_tdata(15 downto 8); + packet_id <= s_axis_tdata( 7 downto 0); + if((s_axis_tdata( 7 downto 0) = C_RAW10) or (s_axis_tdata( 7 downto 0) = C_EOF))then -- Correct ID + sm_state <= ST_HDRB; + else + sm_state <= ST_RESYNC; + end if; + else + sm_state <= ST_RESYNC; + end if; + when ST_HDRB => + if(s_axis_tvalid = '1')then + packet_cs <= s_axis_tdata(15 downto 8); + packet_size(15 downto 8) <= s_axis_tdata( 7 downto 0); + if(packet_id = C_RAW10)then + sm_state <= ST_TRANSFER; + transfer_cnt <= (others => '0'); + start_of_line <= '1'; + else + sm_state <= ST_RESYNC; + packet_id_dbg <= packet_id; + packet_id_upd <= '1'; + end if; + if(packet_id = C_EOF)then + start_of_frame <= '1'; + enable <= enable_req; + end if; + else + sm_state <= ST_RESYNC; + end if; + when ST_TRANSFER => + if(s_axis_tvalid = '1')then + start_of_frame <= '0'; + start_of_line <= '0'; + m_axis_tuser <= start_of_frame; + m_axis_tvalid <= enable; + if(transfer_cnt >= (UNSIGNED(packet_size)-2))then + m_axis_tlast <= '1'; + sm_state <= ST_RESYNC; + else + transfer_cnt <= transfer_cnt + 2; + end if; + else + m_axis_tlast <= '1'; + sm_state <= ST_IDLE; + end if; + end case; + end if; +end process; + +frame_start_dbg <= start_of_frame; +line_start_dbg <= start_of_line; +packet_size_dbg <= packet_size; +transfer_cnt_dbg <= STD_LOGIC_VECTOR(transfer_cnt); + +process(sm_state) +begin + if( + ((sm_state = ST_IDLE) and (s_axis_tvalid = '1') and ((s_axis_tdata(7 downto 0) /= C_SOT) or (s_axis_tdata(15 downto 8) /= C_SOT))) or + ((sm_state = ST_HDRA) and not ((s_axis_tdata( 7 downto 0) = C_RAW10) or (s_axis_tdata( 7 downto 0) = C_EOF))) + )then + resync_out <= '1'; + else + resync_out <= '0'; + end if; +end process; +--------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis.xdc b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis.xdc new file mode 100644 index 0000000..d270ab4 --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis.xdc @@ -0,0 +1 @@ +set_false_path -to [get_pins parser_inst/enable_req_reg/D] \ No newline at end of file diff --git a/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis_v1_0.vhd b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis_v1_0.vhd new file mode 100644 index 0000000..a475d76 --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/csi_to_axis_v1_0.vhd @@ -0,0 +1,272 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +library UNISIM; +use UNISIM.VComponents.all; +---------------------------------------------------------------------------------- +entity csi_to_axis_v1_0 is +generic ( + C_M_AXIS_TDATA_WIDTH : INTEGER := 32; + C_LANES : INTEGER range 1 to 4 := 2; + C_TIMEOUT : INTEGER := 127 +); +port ( + -- Transfer enable + enable_in : in STD_LOGIC; + -- MIPI PPI + rxbyteclkhs : in STD_LOGIC; + cl_enable : out STD_LOGIC := '1'; + cl_stopstate : in STD_LOGIC; + cl_rxclkactivehs : in STD_LOGIC; + dl0_enable : out STD_LOGIC := '1'; + dl0_rxactivehs : in STD_LOGIC; + dl0_rxvalidhs : in STD_LOGIC; + dl0_rxsynchs : in STD_LOGIC; + dl0_datahs : in STD_LOGIC_VECTOR(7 downto 0); + dl1_enable : out STD_LOGIC; + dl1_rxactivehs : in STD_LOGIC; + dl1_rxvalidhs : in STD_LOGIC; + dl1_rxsynchs : in STD_LOGIC; + dl1_datahs : in STD_LOGIC_VECTOR(7 downto 0); + dl2_enable : out STD_LOGIC; + dl2_rxactivehs : in STD_LOGIC; + dl2_rxvalidhs : in STD_LOGIC; + dl2_rxsynchs : in STD_LOGIC; + dl2_datahs : in STD_LOGIC_VECTOR(7 downto 0); + dl3_enable : out STD_LOGIC; + dl3_rxactivehs : in STD_LOGIC; + dl3_rxvalidhs : in STD_LOGIC; + dl3_rxsynchs : in STD_LOGIC; + dl3_datahs : in STD_LOGIC_VECTOR(7 downto 0); + -- Status + trig_req : out STD_LOGIC; + trig_ack : in STD_LOGIC; + -- AXIS + m_axis_aclk : in STD_LOGIC; + m_axis_aresetn : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + m_axis_tready : in STD_LOGIC + -- -- Debug +-- raw_data_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- raw_valid_dbg : out STD_LOGIC_VECTOR( 1 downto 0); +-- align_data_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- align_valid_dbg : out STD_LOGIC_VECTOR( 1 downto 0); +-- merge_data_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- merge_valid_dbg : out STD_LOGIC; +-- frame_start_dbg : out STD_LOGIC; +-- line_start_dbg : out STD_LOGIC; +-- parse_data_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- parse_valid_dbg : out STD_LOGIC; +-- parse_user_dbg : out STD_LOGIC; +-- parse_last_dbg : out STD_LOGIC; +-- packet_id_dbg : out STD_LOGIC_VECTOR( 7 downto 0); +-- packet_id_upd_dbd : out STD_LOGIC; +-- packet_size_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- transfer_cnt_dbg : out STD_LOGIC_VECTOR(15 downto 0); +-- align_resync_dbg : out STD_LOGIC; +-- merge_resync_dbg : out STD_LOGIC +); +end csi_to_axis_v1_0; +---------------------------------------------------------------------------------- +architecture arch_imp of csi_to_axis_v1_0 is +---------------------------------------------------------------------------------- +component lane_align is +generic( + C_LANES : INTEGER range 1 to 4 := 2; + C_TIMEOUT : INTEGER := 127 +); +port ( + clk_in : in STD_LOGIC; + resync : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_in : in STD_LOGIC_VECTOR(C_LANES-1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_out : out STD_LOGIC_VECTOR(C_LANES-1 downto 0); + err_req : out STD_LOGIC; + err_ack : in STD_LOGIC +); +end component; + +component lane_merge is +generic( + C_LANES : INTEGER range 1 to 4 := 2 +); +port( + clk_in : in STD_LOGIC; + resync_in : in STD_LOGIC; + resync_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_in : in STD_LOGIC_VECTOR(C_LANES-1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_out : out STD_LOGIC +); +end component; + +component csi2_parser is +generic( + C_LANES : INTEGER range 1 to 4 := 2 +); +port ( + enable_in : in STD_LOGIC; + resync_out : out STD_LOGIC; + axis_aclk : in STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + s_axis_tvalid : in STD_LOGIC; + m_axis_tvalid : out STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + m_axis_tuser : out STD_LOGIC; + m_axis_tlast : out STD_LOGIC; + -- Debug + frame_start_dbg : out STD_LOGIC; + line_start_dbg : out STD_LOGIC; + packet_id_dbg : out STD_LOGIC_VECTOR(7 downto 0); + packet_id_upd : out STD_LOGIC; + packet_size_dbg : out STD_LOGIC_VECTOR(15 downto 0); + transfer_cnt_dbg : out STD_LOGIC_VECTOR(15 downto 0) +); +end component; +---------------------------------------------------------------------------------- +signal pclk : STD_LOGIC; +signal raw_data : STD_LOGIC_VECTOR(8*C_LANES-1 downto 0); +signal align_data : STD_LOGIC_VECTOR(8*C_LANES-1 downto 0); +signal merge_data : STD_LOGIC_VECTOR(8*C_LANES-1 downto 0); +signal raw_valid : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +signal align_valid : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +signal merge_valid : STD_LOGIC; +signal tuser_drv : STD_LOGIC; +signal tlast_drv : STD_LOGIC; +signal tvalid_drv : STD_LOGIC; +signal tdata_drv : STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); +signal frame_start : STD_LOGIC; +signal line_start : STD_LOGIC; +signal packet_id : STD_LOGIC_VECTOR(7 downto 0); +signal packet_id_upd : STD_LOGIC; +signal packet_size : STD_LOGIC_VECTOR(15 downto 0); +signal transfer_cnt : STD_LOGIC_VECTOR(15 downto 0); +signal align_resync : STD_LOGIC; +signal merge_resync : STD_LOGIC; +signal parse_resync : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +pclk <= rxbyteclkhs; -- Main byte clock bitrate/8 +cl_enable <= '1'; -- PPI ShutDown ? +---------------------------------------------------------------------------------- +-- Lane 0 +dl0_enable <= '1'; +raw_valid(0) <= dl0_rxvalidhs; +raw_data( 7 downto 0) <= dl0_datahs; +---------------------------------------------------------------------------------- +-- Lane 1 +lane_1_gen: if C_LANES > 1 generate +begin + dl1_enable <= '1'; + raw_valid(1) <= dl1_rxvalidhs; + raw_data(15 downto 8) <= dl1_datahs; +end generate; +---------------------------------------------------------------------------------- +-- Lane 2 +lane_2_gen: if C_LANES > 2 generate +begin + dl2_enable <= '1'; + raw_valid(2) <= dl2_rxvalidhs; + raw_data(23 downto 16) <= dl2_datahs; +end generate; +---------------------------------------------------------------------------------- +-- Lane 3 +lane_3_gen: if C_LANES > 3 generate +begin + dl3_enable <= '1'; + raw_valid(3) <= dl3_rxvalidhs; + raw_data(31 downto 24) <= dl3_datahs; +end generate; +---------------------------------------------------------------------------------- +lane_align_inst: lane_align +generic map( + C_LANES => C_LANES, + C_TIMEOUT => C_TIMEOUT +) +port map( + clk_in => pclk, + resync => align_resync, + data_in => raw_data, + valid_in => raw_valid, + data_out => align_data, + valid_out => align_valid, + err_req => trig_req, + err_ack => trig_ack +); +---------------------------------------------------------------------------------- +lane_merge_inst: lane_merge +generic map( + C_LANES => C_LANES +) +port map( + clk_in => pclk, + resync_in => parse_resync, + resync_out => merge_resync, + data_in => align_data, + valid_in => align_valid, + data_out => merge_data, + valid_out => merge_valid +); +---------------------------------------------------------------------------------- +align_resync <= merge_resync or parse_resync; +---------------------------------------------------------------------------------- +parser_inst: csi2_parser +generic map( + C_LANES => C_LANES +) +port map( + enable_in => enable_in, + resync_out => parse_resync, + axis_aclk => pclk, + s_axis_tdata => merge_data, + s_axis_tvalid => merge_valid, + m_axis_tvalid => tvalid_drv, + m_axis_tdata => tdata_drv, + m_axis_tuser => tuser_drv, + m_axis_tlast => tlast_drv, + + frame_start_dbg => frame_start, + line_start_dbg => line_start, + packet_id_dbg => packet_id, + packet_id_upd => packet_id_upd, + packet_size_dbg => packet_size, + transfer_cnt_dbg => transfer_cnt +); +---------------------------------------------------------------------------------- +m_axis_tvalid <= tvalid_drv; +m_axis_tdata <= tdata_drv; +m_axis_tuser <= tuser_drv; +m_axis_tlast <= tlast_drv; +---------------------------------------------------------------------------------- +-- Debug +---------------------------------------------------------------------------------- +--raw_data_dbg <= raw_data; +--raw_valid_dbg <= raw_valid; +--align_data_dbg <= align_data; +--align_valid_dbg <= align_valid; +--merge_data_dbg <= merge_data; +--merge_valid_dbg <= merge_valid; +--frame_start_dbg <= frame_start; +--line_start_dbg <= line_start; +--parse_data_dbg <= tdata_drv; +--parse_valid_dbg <= tvalid_drv; +--parse_user_dbg <= tuser_drv; +--parse_last_dbg <= tlast_drv; +--packet_id_dbg <= packet_id; +--packet_id_upd_dbd <= packet_id_upd; +--packet_size_dbg <= packet_size; +--transfer_cnt_dbg <= transfer_cnt; +--align_resync_dbg <= align_resync; +--merge_resync_dbg <= merge_resync; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/lane_align.vhd b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/lane_align.vhd new file mode 100644 index 0000000..40ddf67 --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/lane_align.vhd @@ -0,0 +1,123 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity lane_align is +generic( + C_LANES : INTEGER range 1 to 4 := 2; + C_TIMEOUT : INTEGER := 127 +); +port ( + clk_in : in STD_LOGIC; + resync : in STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_in : in STD_LOGIC_VECTOR(C_LANES-1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_out : out STD_LOGIC_VECTOR(C_LANES-1 downto 0); + err_req : out STD_LOGIC; + err_ack : in STD_LOGIC +); +end lane_align; +---------------------------------------------------------------------------------- +architecture arch_imp of lane_align is +---------------------------------------------------------------------------------- +constant C_SOT : STD_LOGIC_VECTOR(15 downto 0) := x"B800"; +constant ones_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0) := (others => '1'); +constant zero_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0) := (others => '0'); +constant C_CNT_LIMIT : integer := 1; +---------------------------------------------------------------------------------- +type sr_data_type is array (0 to C_LANES-1) of STD_LOGIC_VECTOR(23 downto 0); +signal data_sr : sr_data_type; +type buf_data_type is array (0 to C_LANES-1) of STD_LOGIC_VECTOR(15 downto 0); +signal data_dly : buf_data_type; +signal sot_found : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +type shift_type is array (0 to C_LANES-1) of integer range 0 to 8; +signal data_shift_det : shift_type; +signal data_shift : shift_type; +signal transfer : STD_LOGIC_VECTOR(C_LANES-1 downto 0); + +type to_cnt_type is array (0 to C_LANES-1) of integer range 0 to C_TIMEOUT; +signal to_cnt : to_cnt_type; +signal to_flag : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +---------------------------------------------------------------------------------- +signal err_ack_i : STD_LOGIC; +attribute ASYNC_REG : string; +attribute ASYNC_REG of err_ack_i : signal is "true"; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process(data_sr) +begin + sot_found <= (others => '0'); + data_shift_det <= (others => 0); + for j in 0 to C_LANES-1 loop + for i in 0 to 8 loop + if(data_sr(j)(i+15 downto i) = C_SOT)then + sot_found(j) <= '1'; + data_shift_det(j) <= i; + end if; + end loop; + end loop; +end process; + +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + --err_ack_i <= err_ack; + err_req <= '0'; + for i in 0 to C_LANES-1 loop + + if(valid_in(i) = '1')then + data_sr(i) <= data_in(i*8+7 downto i*8) & data_sr(i)(23 downto 8); + end if; + data_dly(i) <= data_sr(i)(23 downto 8); + + if(transfer(i) = '0')then + if((valid_in(i) = '1') and (sot_found(i) = '1'))then + data_shift <= data_shift_det; + transfer(i) <= '1'; + end if; + if(valid_in(i) = '1')then + if(sot_found(i) = '1')then + to_flag(i) <= '0'; + to_cnt(i) <= 0; + else + if(to_cnt(i) /= C_TIMEOUT)then + to_cnt(i) <= to_cnt(i) + 1; + else + to_flag(i) <= '1'; + end if; + end if; + end if; + else + if((valid_in(i) = '0') or (resync = '1'))then + transfer(i) <= '0'; + to_cnt(i) <= 0; + end if; + end if; + + -- if(to_cnt(i) = C_TIMEOUT-1)then + -- err_req <= '1'; + -- elsif(err_ack_i)then + -- err_req <= '0'; + -- end if; + end loop; + if(UNSIGNED(to_flag) /= TO_UNSIGNED(0,C_LANES))then + err_req <= '1'; + else + err_req <= '0'; + end if; + end if; +end process; + +out_gen: for i in 0 to C_LANES-1 generate +begin + data_out(i*8+7 downto i*8) <= data_dly(i)(data_shift(i)+7 downto data_shift(i)); + valid_out(i) <= transfer(i); +end generate; +--------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/lane_merge.vhd b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/lane_merge.vhd new file mode 100644 index 0000000..6906471 --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/hdl/lane_merge.vhd @@ -0,0 +1,118 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity lane_merge is +generic( + C_LANES : INTEGER range 1 to 4 := 2 +); +port ( + clk_in : in STD_LOGIC; + resync_in : in STD_LOGIC; + resync_out : out STD_LOGIC; + data_in : in STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_in : in STD_LOGIC_VECTOR(C_LANES-1 downto 0); + data_out : out STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); + valid_out : out STD_LOGIC +); +end lane_merge; +---------------------------------------------------------------------------------- +architecture arch_imp of lane_merge is +---------------------------------------------------------------------------------- +constant C_SOT : STD_LOGIC_VECTOR(7 downto 0) := x"B8"; +constant ones_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0) := (others => '1'); +constant zero_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0) := (others => '0'); +---------------------------------------------------------------------------------- +type sm_state_type is (ST_IDLE, ST_FIRST, ST_TRANSFER, ST_RESYNC); +signal sm_state : sm_state_type := ST_IDLE; +---------------------------------------------------------------------------------- +signal data_dl : STD_LOGIC_VECTOR(C_LANES*8-1 downto 0); +signal valid_dl : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +signal align_vec : STD_LOGIC_VECTOR(C_LANES-1 downto 0); +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + data_dl <= data_in; + valid_dl <= valid_in; + case sm_state is + when ST_IDLE => + if(valid_in /= zero_vec)then + align_vec <= valid_in; + sm_state <= ST_FIRST; + -- valid_out <= '1'; + -- else + -- valid_out <= '0'; + end if; + when ST_FIRST => + if((valid_in /= ones_vec) or (resync_in = '1'))then + align_vec <= (others => '0'); + sm_state <= ST_RESYNC; + resync_out <= '1'; + else + sm_state <= ST_TRANSFER; + valid_out <= '1'; + for i in 0 to C_LANES-1 loop + if(data_in(i*8+7 downto i*8) = C_SOT)then + align_vec(i) <= '0'; -- Not delayed + else + align_vec(i) <= '1'; -- Delayed + end if; + end loop; + end if; + + when ST_TRANSFER => + -- if((valid_in /= ones_vec) or (resync_in = '1'))then + -- align_vec <= (others => '0'); + -- sm_state <= ST_RESYNC; + -- resync_out <= '1'; + -- valid_out <= '0'; + -- end if; + if(valid_in /= ones_vec)then + align_vec <= (others => '0'); + sm_state <= ST_IDLE; + valid_out <= '0'; + elsif(resync_in = '1')then + align_vec <= (others => '0'); + sm_state <= ST_RESYNC; + resync_out <= '1'; + valid_out <= '0'; + end if; + when ST_RESYNC => + resync_out <= '0'; + if(valid_in = zero_vec)then + sm_state <= ST_IDLE; + end if; + end case; + + --valid_out <= '0'; + --valid_out <= '1'; + for i in 0 to C_LANES-1 loop + --if(valid_dl(i) = '1')then + -- valid_out <= '1'; + --end if; + -- if(align_vec(i) = '1')then + -- if(valid_dl(i) = '0')then + -- valid_out <= '0'; + -- end if; + -- else + -- if(valid_in(i) = '0')then + -- valid_out <= '0'; + -- end if; + -- end if; + if(align_vec(i) = '1')then + data_out(i*8+7 downto i*8) <= data_dl(i*8+7 downto i*8); + else + data_out(i*8+7 downto i*8) <= data_in(i*8+7 downto i*8); + end if; + end loop; + end if; +end process; +--------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/csi_to_axis_1.0/xgui/csi_to_axis_v1_0.tcl b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/xgui/csi_to_axis_v1_0.tcl new file mode 100644 index 0000000..bea5392 --- /dev/null +++ b/zynqberrydemo3/ip_lib/csi_to_axis_1.0/xgui/csi_to_axis_v1_0.tcl @@ -0,0 +1,56 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + set C_M_AXIS_TDATA_WIDTH [ipgui::add_param $IPINST -name "C_M_AXIS_TDATA_WIDTH" -parent ${Page_0} -widget comboBox] + set_property tooltip {Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.} ${C_M_AXIS_TDATA_WIDTH} + ipgui::add_param $IPINST -name "C_LANES" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "C_TIMEOUT" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_LANES { PARAM_VALUE.C_LANES } { + # Procedure called to update C_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_LANES { PARAM_VALUE.C_LANES } { + # Procedure called to validate C_LANES + return true +} + +proc update_PARAM_VALUE.C_TIMEOUT { PARAM_VALUE.C_TIMEOUT } { + # Procedure called to update C_TIMEOUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_TIMEOUT { PARAM_VALUE.C_TIMEOUT } { + # Procedure called to validate C_TIMEOUT + return true +} + +proc update_PARAM_VALUE.C_M_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } { + # Procedure called to update C_M_AXIS_TDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_M_AXIS_TDATA_WIDTH { PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } { + # Procedure called to validate C_M_AXIS_TDATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH { MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH PARAM_VALUE.C_M_AXIS_TDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_M_AXIS_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXIS_TDATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_LANES { MODELPARAM_VALUE.C_LANES PARAM_VALUE.C_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_LANES}] ${MODELPARAM_VALUE.C_LANES} +} + +proc update_MODELPARAM_VALUE.C_TIMEOUT { MODELPARAM_VALUE.C_TIMEOUT PARAM_VALUE.C_TIMEOUT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_TIMEOUT}] ${MODELPARAM_VALUE.C_TIMEOUT} +} + diff --git a/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/component.xml b/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/component.xml new file mode 100644 index 0000000..8e19f3e --- /dev/null +++ b/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/component.xml @@ -0,0 +1,228 @@ + + + trenz.biz + user + i2s_to_pwm + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + i2s_to_pwm + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 560fdf3f + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + i2s_to_pwm + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 560fdf3f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 85d97987 + + + + + + + clk_in + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_bclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_lrclk + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i2s_sdata + + in + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pwm_l_out + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pwm_r_out + + out + + + STD_LOGIC + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_SYS_FREQ + C Sys Freq + 150000000 + + + C_PWM_FREQ + C Pwm Freq + 100000 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + hdl/i2s_to_pwm.vhd + vhdlSource + CHECKSUM_560fdf3f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + hdl/i2s_to_pwm.vhd + vhdlSource + USED_IN_ipstatic + + + + xilinx_xpgui_view_fileset + + xgui/i2s_to_pwm_v1_0.tcl + tclSource + CHECKSUM_8d217f22 + XGUI_VERSION_2 + + + + I2S to PWM v1.0 + + + C_SYS_FREQ + Clock Frequency + 150000000 + + + C_PWM_FREQ + PWM Frequency + 100000 + + + Component_Name + i2s_to_pwm_v1_0 + + + + + + virtex7 + artix7 + kintex7 + zynq + + + /Communication_&_Networking/Serial_Interfaces + /Digital_Signal_Processing/Modulation + /UserIP + + I2S to PWM v1.0 + Trenz Electronic GmbH + http://www.trenz.biz + 7 + + xilinx.com:user:i2s_to_pwm:1.0 + + 2016-04-04T15:47:26Z + + + b:/cores/2015.4/design/te0726/demo/ip_lib/i2s_to_pwm_1.0 + b:/cores/2015.4/design/te0726/demo/ip_lib/i2s_to_pwm_1.0 + + + + 2015.4.2 + + + + + + + diff --git a/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/hdl/i2s_to_pwm.vhd b/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/hdl/i2s_to_pwm.vhd new file mode 100644 index 0000000..1e989ba --- /dev/null +++ b/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/hdl/i2s_to_pwm.vhd @@ -0,0 +1,133 @@ +---------------------------------------------------------------------------------- +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko +---------------------------------------------------------------------------------- +library ieee; +use ieee.STD_LOGIC_1164.all; +use ieee.numeric_std.all; +---------------------------------------------------------------------------------- +entity i2s_to_pwm is +generic ( + C_SYS_FREQ : INTEGER := 150000000; + C_PWM_FREQ : INTEGER := 100000 -- Usually from 50 to 100 kHz +); +port ( + -- General + clk_in : in STD_LOGIC; + -- I2S Signals + i2s_bclk : in STD_LOGIC; + i2s_lrclk : in STD_LOGIC; + i2s_sdata : in STD_LOGIC; + -- PWM Outs + pwm_l_out : out STD_LOGIC; + pwm_r_out : out STD_LOGIC +); +end i2s_to_pwm; +---------------------------------------------------------------------------------- +architecture arch_imp of i2s_to_pwm is +---------------------------------------------------------------------------------- +-- For 16 bit sound +constant C_S_CNT_MAX : INTEGER := 32767; +constant C_S_CNT_MIN : INTEGER := -32767; +constant C_STEP : INTEGER := 131072 / (C_SYS_FREQ/C_PWM_FREQ); +---------------------------------------------------------------------------------- +signal left_s_ch_val : SIGNED(15 downto 0); -- Data latches +signal right_s_ch_val : SIGNED(15 downto 0); +signal pwm_s_cnt : SIGNED(15 downto 0); -- Reference signal +signal pwm_s_cnt_dir : STD_LOGIC; -- Saw direction +---------------------------------------------------------------------------------- +signal bclk_sr : STD_LOGIC_VECTOR(1 downto 0); +signal lrclk_sr : STD_LOGIC_VECTOR(1 downto 0); +signal sdata : STD_LOGIC; +---------------------------------------------------------------------------------- +signal bit_addr : INTEGER range 0 to 31; +signal data_reg : STD_LOGIC_VECTOR(31 downto 0); +signal lsb_left : STD_LOGIC; +signal lsb_right : STD_LOGIC; +signal update_left : STD_LOGIC; +signal update_right : STD_LOGIC; +---------------------------------------------------------------------------------- +begin +---------------------------------------------------------------------------------- +-- I2S Decode +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + bclk_sr <= bclk_sr(0) & i2s_bclk; + lrclk_sr <= lrclk_sr(0) & i2s_lrclk; + sdata <= i2s_sdata; + if(lrclk_sr = "01")then -- End of left + lsb_left <= '1'; + elsif(bclk_sr = "01")then -- Rising edge + lsb_left <= '0'; + end if; + if(lrclk_sr = "10")then -- End of rigth + lsb_right <= '1'; + elsif(bclk_sr = "01")then -- Rising edge + lsb_right <= '0'; + end if; + + if(bclk_sr = "01")then -- Rising edge + if((lsb_left = '1') or (lsb_right = '1'))then + bit_addr <= 31; + elsif(bit_addr /= 0)then + bit_addr <= bit_addr - 1; + end if; + data_reg(bit_addr) <= sdata; + update_left <= lsb_left; + update_right <= lsb_right; + else + update_left <= '0'; + update_right <= '0'; + end if; + + if(update_left = '1')then + left_s_ch_val <= SIGNED(data_reg(31 downto 16)); + end if; + if(update_right = '1')then + right_s_ch_val <= SIGNED(data_reg(31 downto 16)); + end if; + end if; +end process; + +-- PWM Coding +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + -- Triangle reference signal + if(pwm_s_cnt_dir = '0')then -- Up count + if(pwm_s_cnt >= TO_SIGNED((C_S_CNT_MAX - C_STEP),16))then + pwm_s_cnt_dir <= '1'; + pwm_s_cnt <= pwm_s_cnt - C_STEP; + else + pwm_s_cnt <= pwm_s_cnt + C_STEP; + end if; + else -- Down count + if(pwm_s_cnt <= TO_SIGNED((C_S_CNT_MIN + C_STEP),16))then + pwm_s_cnt_dir <= '0'; + pwm_s_cnt <= pwm_s_cnt + C_STEP; + else + pwm_s_cnt <= pwm_s_cnt - C_STEP; + end if; + end if; + end if; +end process; + +process(clk_in) +begin + if(clk_in = '1' and clk_in'event)then + -- Comparators + if(left_s_ch_val > pwm_s_cnt)then + pwm_l_out <= '1'; + else + pwm_l_out <= '0'; + end if; + if(right_s_ch_val > pwm_s_cnt)then + pwm_r_out <= '1'; + else + pwm_r_out <= '0'; + end if; + end if; +end process; +---------------------------------------------------------------------------------- +end arch_imp; diff --git a/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/xgui/i2s_to_pwm_v1_0.tcl b/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/xgui/i2s_to_pwm_v1_0.tcl new file mode 100644 index 0000000..3fa319f --- /dev/null +++ b/zynqberrydemo3/ip_lib/i2s_to_pwm_1.0/xgui/i2s_to_pwm_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_PWM_FREQ" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_SYS_FREQ" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_PWM_FREQ { PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to update C_PWM_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_PWM_FREQ { PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to validate C_PWM_FREQ + return true +} + +proc update_PARAM_VALUE.C_SYS_FREQ { PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to update C_SYS_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_SYS_FREQ { PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to validate C_SYS_FREQ + return true +} + + +proc update_MODELPARAM_VALUE.C_SYS_FREQ { MODELPARAM_VALUE.C_SYS_FREQ PARAM_VALUE.C_SYS_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_SYS_FREQ}] ${MODELPARAM_VALUE.C_SYS_FREQ} +} + +proc update_MODELPARAM_VALUE.C_PWM_FREQ { MODELPARAM_VALUE.C_PWM_FREQ PARAM_VALUE.C_PWM_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_PWM_FREQ}] ${MODELPARAM_VALUE.C_PWM_FREQ} +} + diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h b/zynqberrydemo3/os/petalinux/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h new file mode 100644 index 0000000..18e88e0 --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h @@ -0,0 +1,175 @@ +/* + * This file is auto-generated by PetaLinux SDK + * DO NOT MODIFY this file, the modification will not persist + */ + +#ifndef __PLNX_CONFIG_H +#define __PLNX_CONFIG_H + +/* Board oscillator frequency */ +#define CONFIG_ZYNQ_PS_CLK_FREQ 33333333UL + +/* The following table includes the supported baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400} + +/* use serial multi for all serial devices */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +/* Board name */ + +/* processor - ps7_cortexa9_0 */ +#define CONFIG_CPU_FREQ_HZ 666666687 +#define CONFIG_CLOCKS +#define CONFIG_CMD_CLK +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_SYS_LDSCRIPT "arch/arm/mach-zynq/u-boot.lds" + +/* main_memory - ps7_ddr_0 */ + +/* Memory testing handling */ +#define CONFIG_SYS_MEMTEST_START 0x0 +#define CONFIG_SYS_MEMTEST_END (0x0 + 0x1000) +#define CONFIG_SYS_TEXT_BASE 0x00400000 +#define CONFIG_SYS_LOAD_ADDR 0x0 /* default load address */ +#define CONFIG_NR_DRAM_BANKS 1 + +/* Size of malloc() pool */ +#define SIZE 0xC00000 +#define CONFIG_SYS_MALLOC_LEN SIZE + +/* Physical Memory Map */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* uart - ps7_uart_1 */ +#define CONFIG_ZYNQ_SERIAL +#define PSSERIAL0 "psserial0=setenv stdout ttyPS0;setenv stdin ttyPS0\0" +#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0" +#define CONSOLE_ARG "console=console=ttyPS0,115200\0" +#define SERIAL_MULTI "serial=setenv stdout serial;setenv stdin serial\0" +#define CONFIG_BAUDRATE 115200 + +/* spi_flash - ps7_qspi_0 */ +#define XILINX_PS7_QSPI_CLK_FREQ_HZ 190476196 +#define CONFIG_SF_DEFAULT_SPEED (XILINX_PS7_QSPI_CLK_FREQ_HZ / 4) +#define CONFIG_SF_DUAL_FLASH +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x500000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +/* sdio - ps7_sd_1 */ +#define CONFIG_ZYNQ_SDHCI1 0xE0101000 +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SUPPORT_VFAT +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 + +/* devcfg - ps7_dev_cfg_0 */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_ZYNQPL +#define CONFIG_CMD_FPGA_LOADFS + +/* ps7_scutimer_0 */ +#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 +#define CONFIG_SYS_TIMER_COUNTS_DOWN +#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) + +/* FPGA */ + +/* Make the BOOTM LEN big enough for the compressed image */ +#define CONFIG_SYS_BOOTM_LEN 0xF000000 + + +/* BOOTP options */ +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/*Command line configuration.*/ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_SAVES + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 2048/* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_LONGHELP + +/* architecture dependent code */ +#define CONFIG_SYS_USR_EXCEP /* user exception */ +#define CONFIG_SYS_HZ 1000 + +/* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Don't define BOOTARGS, we get it from the DTB chosen fragment */ +#undef CONFIG_BOOTARGS + +#define CONFIG_ENV_OVERWRITE /* Allow to overwrite the u-boot environment variables */ + +#define CONFIG_LMB + +/* Initial memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ 0x08000000 + +/* PREBOOT */ +#define CONFIG_PREBOOT "echo U-BOOT for petalinux;setenv preboot; echo; " + +/* Extra U-Boot Env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + SERIAL_MULTI \ + CONSOLE_ARG \ + PSSERIAL0 \ + "importbootenv=echo \"Importing environment from SD ...\"; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "loadbootenv=load mmc $sdbootdev:$partid ${loadbootenv_addr} ${bootenv}\0" \ + "sd_uEnvtxt_existence_test=test -e mmc $sdbootdev:$partid /uEnv.txt\0" \ + "uenvboot=" \ + "if run sd_uEnvtxt_existence_test; then" \ + "run loadbootenv" \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv; \0" \ + "sdboot=echo boot Petalinux; run uenvboot ; mmcinfo && fatload mmc 0 ${netstart} ${kernel_img} && bootm \0" \ + "autoload=no\0" \ + "clobstart=0x10000000\0" \ + "netstart=0x10000000\0" \ + "dtbnetstart=0x11800000\0" \ + "loadaddr=0x10000000\0" \ + "boot_img=BOOT.BIN\0" \ + "install_boot=mmcinfo && fatwrite mmc 0 ${clobstart} ${boot_img} ${filesize}\0" \ + "bootenvsize=0x20000\0" \ + "bootenvstart=0x500000\0" \ + "eraseenv=sf probe 0 && sf erase ${bootenvstart} ${bootenvsize}\0" \ + "jffs2_img=rootfs.jffs2\0" \ + "sd_update_jffs2=echo Updating jffs2 from SD; mmcinfo && fatload mmc 0:1 ${clobstart} ${jffs2_img} && run install_jffs2\0" \ + "install_jffs2=sf probe 0 && sf erase ${jffs2start} ${jffs2size} && " \ + "sf write ${clobstart} ${jffs2start} ${filesize}\0" \ + "kernel_img=image.ub\0" \ + "install_kernel=mmcinfo && fatwrite mmc 0 ${clobstart} ${kernel_img} ${filesize}\0" \ + "cp_kernel2ram=mmcinfo && fatload mmc 0 ${netstart} ${kernel_img}\0" \ + "dtb_img=system.dtb\0" \ + "sd_update_dtb=echo Updating dtb from SD; mmcinfo && fatload mmc 0:1 ${clobstart} ${dtb_img} && run install_dtb\0" \ + "fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \ + "test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \ + "test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \ + "default_bootcmd=run cp_kernel2ram && bootm ${netstart}\0" \ +"" + +/* BOOTCOMMAND */ +#define CONFIG_BOOTCOMMAND "run default_bootcmd" + +#endif /* __PLNX_CONFIG_H */ diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/fbgrab/files/fbgrab.c b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/fbgrab/files/fbgrab.c new file mode 100644 index 0000000..fc89f5a --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/fbgrab/files/fbgrab.c @@ -0,0 +1,428 @@ +/* + * fbgrab - takes screenshots using the framebuffer. + * + * (C) Gunnar Monell 2002 + * + * This program is free Software, see the COPYING file + * and is based on Stephan Beyer's FBShot + * (C) 2000. + * + * For features and differences, read the manual page. + * + * This program has been checked with "splint +posixlib" without + * warnings. Splint is available from http://www.splint.org/ . + * Patches and enhancements of fbgrab have to fulfill this too. + */ + +#include +#include +#include +#include +#include + +#include +#include /* to handle vt changing */ +#include /* PNG lib */ +#include /* to handle framebuffer ioctls */ + +#define VERSION "1.0 beta 1" +#define DEFAULT_FB "/dev/fb0" +#define MAX_LEN 512 +#define UNDEFINED -1 + +/*@noreturn@*/ static void fatal_error(char *message) +{ + fprintf(stderr, "%s\n", message); + exit(EXIT_FAILURE); +} + +static void usage(char *binary) +{ + printf("Usage: %s\t[-hi] [-{C|c} vt] [-d dev] [-s n]\n" + "\t\t[-f fromfile -w n -h n -b n] filename.png\n", binary); +} + +static void help(char *binary) +{ + printf("fbgrab - takes screenshots using the framebuffer, v%s\n", VERSION); + + usage(binary); + + printf("\nPossible options:\n"); +/* please keep this list alphabetical */ + printf("\t-b n \tforce use of n bits/pixel, required when reading from file\n"); + printf("\t-C n \tgrab from console n, for slower framebuffers\n"); + printf("\t-c n \tgrab from console n\n"); + printf("\t-d dev\tuse framebuffer device dev instead of default\n"); + printf("\t-f file\t read from file instead of framebuffer\n"); + printf("\t-h n \tset height to n pixels, required when reading from file\n" + "\t\tcan be used to force height when reading from framebuffer\n"); + printf("\t-i \tturns on interlacing in PNG\n"); + printf("\t-s n \tsleep n seconds before making screenshot\n"); + printf("\t-w n \tset width to n pixels, required when reading from file\n" + "\t\tcan be used to force width when reading from framebuffer\n"); + printf("\t-? \tprint this usage information\n"); +} + + +static void chvt(int num) +{ + int fd; + + if(-1 == (fd = open("/dev/console", O_RDWR))) + fatal_error("Cannot open /dev/console"); + + if (ioctl(fd, VT_ACTIVATE, num) != 0) + fatal_error("ioctl VT_ACTIVATE"); + + if (ioctl(fd, VT_WAITACTIVE, num) != 0) + fatal_error("ioctl VT_WAITACTIVE"); + + (void) close(fd); +} + +static unsigned short int change_to_vt(unsigned short int vt_num) +{ + int fd; + unsigned short int old_vt; + struct vt_stat vt_info; + + memset(&vt_info, 0, sizeof(struct vt_stat)); + + if(-1 == (fd=open("/dev/console", O_RDONLY))) + fatal_error("Couldn't open /dev/console"); + + if (ioctl(fd, VT_GETSTATE, &vt_info) != 0) + fatal_error("ioctl VT_GETSTATE"); + + (void) close (fd); + + old_vt = vt_info.v_active; + + chvt((int) vt_num); /* go there for information */ + + return old_vt; +} + +static void get_framebufferdata(char *device, struct fb_var_screeninfo *fb_varinfo_p) +{ + int fd; + + /* now open framebuffer device */ + if(-1 == (fd=open(device, O_RDONLY))) + { + fprintf (stderr, "Error: Couldn't open %s.\n", device); + exit(EXIT_FAILURE); + } + + if (ioctl(fd, FBIOGET_VSCREENINFO, fb_varinfo_p) != 0) + fatal_error("ioctl FBIOGET_VSCREENINFO"); + + (void) close(fd); +} + +static void read_framebuffer(char *device, size_t bytes, unsigned char *buf_p) +{ + int fd; + + if(-1 == (fd=open(device, O_RDONLY))) + { + fprintf (stderr, "Error: Couldn't open %s.\n", device); + exit(EXIT_FAILURE); + } + + if (buf_p == NULL || read(fd, buf_p, bytes) != (ssize_t) bytes) + fatal_error("Error: Not enough memory or data\n"); +} + +static void convert1555to32(int width, int height, + unsigned char *inbuffer, + unsigned char *outbuffer) +{ + unsigned int i; + + for (i=0; i < (unsigned int) height*width*2; i+=2) + { + /* BLUE = 0 */ + outbuffer[(i<<1)+0] = (inbuffer[i+1] & 0x7C) << 1; + /* GREEN = 1 */ + outbuffer[(i<<1)+1] = (((inbuffer[i+1] & 0x3) << 3) | + ((inbuffer[i] & 0xE0) >> 5)) << 3; + /* RED = 2 */ + outbuffer[(i<<1)+2] = (inbuffer[i] & 0x1f) << 3; + /* ALPHA = 3 */ + outbuffer[(i<<1)+3] = '\0'; + } +} + +static void convert565to32(int width, int height, + unsigned char *inbuffer, + unsigned char *outbuffer) +{ + unsigned int i; + + for (i=0; i < (unsigned int) height*width*2; i+=2) + { + /* BLUE = 0 */ + outbuffer[(i<<1)+0] = (inbuffer[i] & 0x1f) << 3; + /* GREEN = 1 */ + outbuffer[(i<<1)+1] = (((inbuffer[i+1] & 0x7) << 3) | + (inbuffer[i] & 0xE0) >> 5) << 2; + /* RED = 2 */ + outbuffer[(i<<1)+2] = (inbuffer[i+1] & 0xF8); + /* ALPHA = 3 */ + outbuffer[(i<<1)+3] = '\0'; + } +} + +static void convert888to32(int width, int height, + unsigned char *inbuffer, + unsigned char *outbuffer) +{ + unsigned int i; + + for (i=0; i < (unsigned int) height*width; i++) + { + /* BLUE = 0 */ + outbuffer[(i<<2)+0] = inbuffer[i*3+0]; + /* GREEN = 1 */ + outbuffer[(i<<2)+1] = inbuffer[i*3+1]; + /* RED = 2 */ + outbuffer[(i<<2)+2] = inbuffer[i*3+2]; + /* ALPHA */ + outbuffer[(i<<2)+3] = '\0'; + } +} + +static void write_PNG(unsigned char *outbuffer, char *filename, + int width, int height, int interlace) +{ + int i; + int bit_depth=0, color_type; + png_bytep row_pointers[height]; + png_structp png_ptr; + png_infop info_ptr; + FILE *outfile = fopen(filename, "wb"); + + for (i=0; i 0) + { + if (UNDEFINED == bitdepth || UNDEFINED == width || UNDEFINED == height) + { + printf("Width, height and bitdepth are mandatory when reading from file\n"); + exit(EXIT_FAILURE); + } + } + else + { + if (NULL == device) + { + device = getenv("FRAMEBUFFER"); + if (NULL == device) + { + device = DEFAULT_FB; + } + } + + get_framebufferdata(device, &fb_varinfo); + + if (UNDEFINED == bitdepth) + bitdepth = (int) fb_varinfo.bits_per_pixel; + + if (UNDEFINED == width) + width = (int) fb_varinfo.xres; + + if (UNDEFINED == height) + height = (int) fb_varinfo.yres; + + strncpy(infile, device, MAX_LEN - 1); + } + + buf_size = width * height * (((unsigned int) bitdepth + 7) >> 3); + + buf_p = malloc(buf_size); + + if(buf_p == NULL) + fatal_error("Not enough memory"); + + memset(buf_p, 0, buf_size); + + read_framebuffer(infile, buf_size, buf_p); + + if (UNDEFINED != old_vt) + (void) change_to_vt((unsigned short int) old_vt); + + convert_and_write(buf_p, outfile, width, height, bitdepth, interlace); + + (void) free(buf_p); + + return 0; +} + diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c new file mode 100644 index 0000000..4456768 --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c @@ -0,0 +1,359 @@ +/* +* +* gpio-demo app +* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or (b) that interact +* with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_ROOT "/sys/class/gpio" +#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0])) + +static enum {NONE, IN, OUT, CYLON, KIT} gpio_opt = NONE; + +static const unsigned long cylon[] = { + 0x00000080, 0x00000040, 0x00000020, 0x00000010, + 0x00000008, 0x00000004, 0x00000002, 0x00000001, + 0x00000002, 0x00000004, 0x00000008, + 0x00000010, 0x00000020, 0x00000040, 0x00000080, +}; + +static const unsigned long kit[] = { + 0x000000e0, 0x00000070, 0x00000038, 0x0000001c, + 0x0000000e, 0x00000007, 0x00000003, 0x00000001, + 0x00000003, 0x00000007, 0x0000000e, + 0x0000001c, 0x00000038, 0x00000070, 0x000000e0, +}; + +static int gl_gpio_base = 0; + +static void usage (char *argv0) +{ + char *basename = strrchr(argv0, '/'); + if (!basename) + basename = argv0; + + fprintf(stderr, + "Usage: %s [-g GPIO_BASE] COMMAND\n" + "\twhere COMMAND is one of:\n" + "\t\t-i\t\tInput value from GPIO and print it\n" + "\t\t-o\tVALUE\tOutput value to GPIO\n" + "\t\t-c\t\tCylon test pattern\n" + "\t\t-k\t\t KIT test pattern\n" + "\tGPIO_BASE indicates which GPIO chip to talk to (The number can be \n" + "\tfound at /sys/class/gpio/gpiochipN).\n" + "\tThe highest gpiochipN is the first gpio listed in the dts file, \n" + "\tand the lowest gpiochipN is the last gpio listed in the dts file.\n" + "\tE.g.If the gpiochip240 is the LED_8bit gpio, and I want to output '1' \n" + "\tto the LED_8bit gpio, the command should be:\n" + "\t\tgpio-demo -g 240 -o 1\n" + "\n" + "\tgpio-demo written by Xilinx Inc.\n" + "\n" + , basename); + exit(-2); +} + +static int open_gpio_channel(int gpio_base) +{ + char gpio_nchan_file[128]; + int gpio_nchan_fd; + int gpio_max; + int nchannel; + char nchannel_str[5]; + char *cptr; + int c; + char channel_str[5]; + + char *gpio_export_file = "/sys/class/gpio/export"; + int export_fd=0; + + /* Check how many channels the GPIO chip has */ + sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base); + gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY); + if (gpio_nchan_fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); + return -1; + } + read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str)); + close(gpio_nchan_fd); + nchannel=(int)strtoul(nchannel_str, &cptr, 0); + if (cptr == nchannel_str) { + fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str); + exit(1); + } + + /* Open files for each GPIO channel */ + export_fd=open(gpio_export_file, O_WRONLY); + if (export_fd < 0) { + fprintf(stderr, "Cannot open GPIO to export %d\n", gpio_base); + return -1; + } + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(channel_str, "%d", c); + write(export_fd, channel_str, (strlen(channel_str)+1)); + } + close(export_fd); + return nchannel; +} + +static int close_gpio_channel(int gpio_base) +{ + char gpio_nchan_file[128]; + int gpio_nchan_fd; + int gpio_max; + int nchannel; + char nchannel_str[5]; + char *cptr; + int c; + char channel_str[5]; + + char *gpio_unexport_file = "/sys/class/gpio/unexport"; + int unexport_fd=0; + + /* Check how many channels the GPIO chip has */ + sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base); + gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY); + if (gpio_nchan_fd < 0) { + fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno)); + return -1; + } + read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str)); + close(gpio_nchan_fd); + nchannel=(int)strtoul(nchannel_str, &cptr, 0); + if (cptr == nchannel_str) { + fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str); + exit(1); + } + + /* Close opened files for each GPIO channel */ + unexport_fd=open(gpio_unexport_file, O_WRONLY); + if (unexport_fd < 0) { + fprintf(stderr, "Cannot close GPIO by writing unexport %d\n", gpio_base); + return -1; + } + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(channel_str, "%d", c); + write(unexport_fd, channel_str, (strlen(channel_str)+1)); + } + close(unexport_fd); + return 0; +} + +static int set_gpio_direction(int gpio_base, int nchannel, char *direction) +{ + char gpio_dir_file[128]; + int direction_fd=0; + int gpio_max; + int c; + + gpio_max = gpio_base + nchannel; + for(c = gpio_base; c < gpio_max; c++) { + sprintf(gpio_dir_file, "/sys/class/gpio/gpio%d/direction",c); + direction_fd=open(gpio_dir_file, O_RDWR); + if (direction_fd < 0) { + fprintf(stderr, "Cannot open the direction file for GPIO %d\n", c); + return 1; + } + write(direction_fd, direction, (strlen(direction)+1)); + close(direction_fd); + } + return 0; +} + +static int set_gpio_value(int gpio_base, int nchannel, int value) +{ + char gpio_val_file[128]; + int val_fd=0; + int gpio_max; + char val_str[2]; + int c; + + gpio_max = gpio_base + nchannel; + + for(c = gpio_base; c < gpio_max; c++) { + sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c); + val_fd=open(gpio_val_file, O_RDWR); + if (val_fd < 0) { + fprintf(stderr, "Cannot open the value file of GPIO %d\n", c); + return -1; + } + sprintf(val_str,"%d", (value & 1)); + write(val_fd, val_str, sizeof(val_str)); + close(val_fd); + value >>= 1; + } + return 0; +} + +static int get_gpio_value(int gpio_base, int nchannel) +{ + char gpio_val_file[128]; + int val_fd=0; + int gpio_max; + char val_str[2]; + char *cptr; + int value = 0; + int c; + + gpio_max = gpio_base + nchannel; + + for(c = gpio_max-1; c >= gpio_base; c--) { + sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c); + val_fd=open(gpio_val_file, O_RDWR); + if (val_fd < 0) { + fprintf(stderr, "Cannot open GPIO to export %d\n", c); + return -1; + } + read(val_fd, val_str, sizeof(val_str)); + value <<= 1; + value += (int)strtoul(val_str, &cptr, 0); + if (cptr == optarg) { + fprintf(stderr, "Failed to change %s into integer", val_str); + } + close(val_fd); + } + return value; +} + +void signal_handler(int sig) +{ + switch (sig) { + case SIGTERM: + case SIGHUP: + case SIGQUIT: + case SIGINT: + close_gpio_channel(gl_gpio_base); + exit(0) ; + default: + break; + } +} + +int main(int argc, char *argv[]) +{ + extern char *optarg; + char *cptr; + int gpio_value = 0; + int nchannel = 0; + + int c; + int i; + + opterr = 0; + + while ((c = getopt(argc, argv, "g:io:ck")) != -1) { + switch (c) { + case 'g': + gl_gpio_base = (int)strtoul(optarg, &cptr, 0); + if (cptr == optarg) + usage(argv[0]); + break; + case 'i': + gpio_opt = IN; + break; + case 'o': + gpio_opt = OUT; + gpio_value = (int)strtoul(optarg, &cptr, 0); + if (cptr == optarg) + usage(argv[0]); + break; + case 'c': + gpio_opt = CYLON; + break; + case 'k': + gpio_opt = KIT; + break; + case '?': + usage(argv[0]); + default: + usage(argv[0]); + + } + } + + if (gl_gpio_base == 0) { + usage(argv[0]); + } + + nchannel = open_gpio_channel(gl_gpio_base); + signal(SIGTERM, signal_handler); /* catch kill signal */ + signal(SIGHUP, signal_handler); /* catch hang up signal */ + signal(SIGQUIT, signal_handler); /* catch quit signal */ + signal(SIGINT, signal_handler); /* catch a CTRL-c signal */ + switch (gpio_opt) { + case IN: + set_gpio_direction(gl_gpio_base, nchannel, "in"); + gpio_value=get_gpio_value(gl_gpio_base, nchannel); + fprintf(stdout,"0x%08X\n", gpio_value); + break; + case OUT: + set_gpio_direction(gl_gpio_base, nchannel, "out"); + set_gpio_value(gl_gpio_base, nchannel, gpio_value); + break; + case CYLON: +#define CYLON_DELAY_USECS (10000) + set_gpio_direction(gl_gpio_base, nchannel, "out"); + for (;;) { + for(i=0; i < ARRAY_SIZE(cylon); i++) { + gpio_value=(int)cylon[i]; + set_gpio_value(gl_gpio_base, nchannel, gpio_value); + } + usleep(CYLON_DELAY_USECS); + } + case KIT: +#define KIT_DELAY_USECS (10000) + set_gpio_direction(gl_gpio_base, nchannel, "out"); + for (;;) { + for (i=0; i +#include +#include +#include +#include + +void usage(char *prog) +{ + printf("usage: %s ADDR\n",prog); + printf("\n"); + printf("ADDR may be specified as hex values\n"); +} + + +int main(int argc, char *argv[]) +{ + int fd; + void *ptr; + unsigned addr, page_addr, page_offset; + unsigned page_size=sysconf(_SC_PAGESIZE); + + if(argc!=2) { + usage(argv[0]); + exit(-1); + } + + fd=open("/dev/mem",O_RDONLY); + if(fd<1) { + perror(argv[0]); + exit(-1); + } + + addr=strtoul(argv[1],NULL,0); + page_addr=(addr & ~(page_size-1)); + page_offset=addr-page_addr; + + ptr=mmap(NULL,page_size,PROT_READ,MAP_SHARED,fd,(addr & ~(page_size-1))); + if((int)ptr==-1) { + perror(argv[0]); + exit(-1); + } + + printf("0x%08x\n",*((unsigned *)(ptr+page_offset))); + return 0; +} + + diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c new file mode 100644 index 0000000..e1b2f16 --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/peekpoke/files/poke.c @@ -0,0 +1,81 @@ +/* +* poke utility - for those who remember the good old days! +* + +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or (b) that interact +* with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include +#include +#include +#include +#include + +void usage(char *prog) +{ + printf("usage: %s ADDR VAL\n",prog); + printf("\n"); + printf("ADDR and VAL may be specified as hex values\n"); +} + +int main(int argc, char *argv[]) +{ + int fd; + void *ptr; + unsigned val; + unsigned addr, page_addr, page_offset; + unsigned page_size=sysconf(_SC_PAGESIZE); + + fd=open("/dev/mem",O_RDWR); + if(fd<1) { + perror(argv[0]); + exit(-1); + } + + if(argc!=3) { + usage(argv[0]); + exit(-1); + } + + addr=strtoul(argv[1],NULL,0); + val=strtoul(argv[2],NULL,0); + + page_addr=(addr & ~(page_size-1)); + page_offset=addr-page_addr; + + ptr=mmap(NULL,page_size,PROT_READ|PROT_WRITE,MAP_SHARED,fd,(addr & ~(page_size-1))); + if((int)ptr==-1) { + perror(argv[0]); + exit(-1); + } + + *((unsigned *)(ptr+page_offset))=val; + return 0; +} diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/rpicam.c b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/rpicam.c new file mode 100644 index 0000000..24cd13c --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/rpicam.c @@ -0,0 +1,191 @@ +/* +-- Company: Trenz Electronic GmbH +-- Engineer: Oleksandr Kiyenko + */ +#include +#include +#include +#include +#include +#include +#include +#include "sensor_config.h" + +#define CAMERA_V1_3_IIC_ADDRESS 0x36 +#define CAMERA_V2_1_IIC_ADDRESS 0x10 + +#define CS_CMMN_CHIP_ID_H 0x300A +#define CS_CMMN_CHIP_ID_L 0x300B + +unsigned char i2c_reg_read(int dev_file, unsigned char dev_addr, const unsigned short reg_addr){ + __u8 inbuf[2]; + __u8 outbuf[2]; + struct i2c_rdwr_ioctl_data packets; + struct i2c_msg messages[2]; + + /* + * In order to read a register, we first do a "dummy write" by writing + * 0 bytes to the register we want to read from. This is similar to + * the packet in set_i2c_register, except it's 1 byte rather than 2. + */ + outbuf[0] = reg_addr >> 8; + outbuf[1] = reg_addr & 0xFF; + messages[0].addr = dev_addr; + messages[0].flags = 0; + messages[0].len = 2, //sizeof(outbuf); + messages[0].buf = &outbuf; + /* The data will get returned in this structure */ + messages[1].addr = dev_addr; + messages[1].flags = I2C_M_RD; /* | I2C_M_NOSTART*/ + messages[1].len = 1, //sizeof(inbuf); + messages[1].buf = inbuf; + + /* Send the request to the kernel and get the result back */ + packets.msgs = messages; + packets.nmsgs = 2; + if(ioctl(dev_file, I2C_RDWR, &packets) < 0) { + perror("Unable to send data"); + return 1; + } + + return inbuf[0]; +} + +int i2c_reg_write(int dev_file, unsigned char dev_addr, unsigned short reg_addr, unsigned char reg_data) +{ + unsigned char outbuf[3]; + struct i2c_rdwr_ioctl_data packets; + struct i2c_msg messages[1]; + + messages[0].addr = dev_addr; + messages[0].flags = 0; + messages[0].len = sizeof(outbuf); + messages[0].buf = &outbuf; + /* The first byte indicates which register we'll write */ + outbuf[0] = reg_addr >> 8; + outbuf[1] = reg_addr & 0xFF; + outbuf[2] = reg_data; + /* Transfer the i2c packets to the kernel and verify it worked */ + packets.msgs = messages; + packets.nmsgs = 1; + if(ioctl(dev_file, I2C_RDWR, &packets) < 0) { + perror("Unable to send data"); + return 1; + } + + return 0; +} + +static void i2c_set_write(int dev_file, unsigned char dev_addr, struct sensor_cmd *set){ + int i; + for(i=0; set[i].reg != TABLE_END; i++){ + i2c_reg_write(dev_file, dev_addr, set[i].reg, set[i].val); + } +} + +static void imx219_crop(int dev_file, unsigned char dev_addr, struct sensor_rect crop_rect){ + i2c_reg_write(dev_file, dev_addr, 0x0164, crop_rect.left >> 8); + i2c_reg_write(dev_file, dev_addr, 0x0165, crop_rect.left & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x0166, (crop_rect.width - 1) >> 8); + i2c_reg_write(dev_file, dev_addr, 0x0167, (crop_rect.width - 1) & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x0168, crop_rect.top >> 8); + i2c_reg_write(dev_file, dev_addr, 0x0169, crop_rect.top & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x016A, (crop_rect.height - 1) >> 8); + i2c_reg_write(dev_file, dev_addr, 0x016B, (crop_rect.height - 1) & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x016C, crop_rect.width >> 8); + i2c_reg_write(dev_file, dev_addr, 0x016D, crop_rect.width & 0xff); + i2c_reg_write(dev_file, dev_addr, 0x016E, crop_rect.height >> 8); + i2c_reg_write(dev_file, dev_addr, 0x016F, crop_rect.height & 0xff); +} + + +int main(int argc, char *argv[]) +{ + int i2c_file; + unsigned short model_id; + unsigned int lot_id; + unsigned short chip_id; + unsigned char ret; + + printf("Raspberry Pi Camera Init v1.3\n"); + if(argc < 2){ + printf("%s /dev/i2c-X [mode]\n",argv[0]); + return 0; + } + + if ((i2c_file = open(argv[1], O_RDWR)) < 0) { + perror("Unable to open i2c control file"); + return 0; + } + + if(!((i2c_reg_read(i2c_file, CAMERA_V1_3_IIC_ADDRESS, CS_CMMN_CHIP_ID_H) != 0x56) || (i2c_reg_read(i2c_file, CAMERA_V1_3_IIC_ADDRESS, CS_CMMN_CHIP_ID_L) != 0x47))){ + printf("Camera V1.X configuration\n"); + i2c_reg_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, 0x0100, 0x00); // Disable + i2c_reg_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, 0x0103, 0x01); // Reset + usleep(1); // Wait + i2c_reg_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, 0x0103, 0x00); // Reset + usleep(10 * 1000); // Wait + i2c_set_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, ov5647_sensor_common_10bit); // Load common configuration + i2c_set_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, ov5647_sensor_1296_968_30); // Load specific configuration + i2c_reg_write(i2c_file, CAMERA_V1_3_IIC_ADDRESS, 0x0100, 0x01); // Enable + printf("Camera init complete.\n"); + close(i2c_file); + return 1; + } + + printf("Camera V2.X configuration\n"); + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0000); + if (ret < 0) { + perror("Failure to read Model ID (high byte)\n"); + return 0; + } + model_id = ret << 8; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0001); + if (ret < 0) { + perror("Failure to read Model ID (low byte)\n"); + return 0; + } + model_id |= ret; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0004); + if (ret < 0) { + perror("Failure to read Lot ID (high byte)\n"); + return 0; + } + lot_id = ret << 16; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0005); + if (ret < 0) { + perror("Failure to read Lot ID (mid byte)\n"); + return 0; + } + lot_id |= ret << 8; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x0006); + if (ret < 0) { + perror("Failure to read Lot ID (low byte)\n"); + return 0; + } + lot_id |= ret; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x000D); + if (ret < 0) { + perror("Failure to read Chip ID (high byte)\n"); + return 0; + } + chip_id = ret << 8; + ret = i2c_reg_read(i2c_file, CAMERA_V2_1_IIC_ADDRESS, 0x000E); + if (ret < 0) { + perror("Failure to read Chip ID (low byte)\n"); + return 0; + } + chip_id |= ret; + if (model_id != 0x0219) { + perror("Model not supported!\n"); + return 0; + } + + printf("Found 2.X Camera Model ID 0x%04x, Lot ID 0x%06x, Chip ID 0x%04x\n", model_id, lot_id, chip_id); + i2c_set_write(i2c_file, CAMERA_V2_1_IIC_ADDRESS, imx219_720p_regs); + printf("Camera init complete.\n"); + + close(i2c_file); + return 3; +} + diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/sensor_config.h b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/sensor_config.h new file mode 100644 index 0000000..8f062a5 --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/rpicam/files/sensor_config.h @@ -0,0 +1,705 @@ + +#ifndef SENSOR_CONFIG_H_ +#define SENSOR_CONFIG_H_ + + +#define TABLE_END 0xffff + +//----------------------------------------------------------------------------------------- + +// atomar register element +struct sensor_cmd { + unsigned short reg; + unsigned char val; +}; + +//----------------------------------------------------------------------------------------- + +static struct sensor_cmd ov5647_sensor_common_10bit[] = { + { 0x3034, 0x1A }, // 10 bit mode +// { 0x3034, 0x10 }, // 8 bit mode + { 0x503D, 0x00 }, // Test Pattern + { 0x3035, 0x21 }, // CLK DIV + { 0x3036, 0x46 }, // PLL MULT + { 0x303c, 0x11 }, // PLLS CP + { 0x3106, 0xf5 }, // PLL DIV + { 0x3821, 0x07 }, // TIMING TC + { 0x3820, 0x41 }, // TIMING TC + { 0x3827, 0xec }, + { 0x370c, 0x0f }, + { 0x3612, 0x59 }, + { 0x3503, 0x00 }, // AEC/AGC + { 0x5000, 0x89 }, // Lens Correction + { 0x5001, 0x01 }, // AWB + { 0x5002, 0x41 }, // AWB GAIN, OPT, WIN + { 0x5003, 0x0A }, // BIN + { 0x5a00, 0x08 }, + { 0x3000, 0x00 }, + { 0x3001, 0x00 }, + { 0x3002, 0x00 }, + { 0x3016, 0x08 }, + { 0x3017, 0xe0 }, + { 0x3018, 0x44 }, + { 0x301c, 0xf8 }, + { 0x301d, 0xf0 }, + { 0x3a18, 0x00 }, + { 0x3a19, 0xf8 }, + { 0x3c01, 0x80 }, // 50/60HZ Detection + { 0x3b07, 0x0c }, + { 0x380c, 0x07 }, + { 0x380d, 0x68 }, + { 0x380e, 0x03 }, + { 0x380f, 0xd8 }, + { 0x3814, 0x31 }, + { 0x3815, 0x31 }, + { 0x3708, 0x64 }, + { 0x3709, 0x52 }, + { 0x3630, 0x2e }, + { 0x3632, 0xe2 }, + { 0x3633, 0x23 }, + { 0x3634, 0x44 }, + { 0x3636, 0x06 }, + { 0x3620, 0x65 }, // V BINNING + { 0x3621, 0xe1 }, // H BINNING + { 0x3600, 0x37 }, + { 0x3704, 0xa0 }, + { 0x3703, 0x5a }, + { 0x3715, 0x78 }, + { 0x3717, 0x01 }, + { 0x3731, 0x02 }, + { 0x370b, 0x60 }, + { 0x3705, 0x1a }, + { 0x3f05, 0x02 }, + { 0x3f06, 0x10 }, + { 0x3f01, 0x0a }, + { 0x3a08, 0x01 }, + { 0x3a09, 0x27 }, + { 0x3a0a, 0x00 }, + { 0x3a0b, 0xf6 }, + { 0x3a0d, 0x04 }, + { 0x3a0e, 0x03 }, + { 0x3a0f, 0x58 }, + { 0x3a10, 0x50 }, + { 0x3a1b, 0x58 }, + { 0x3a1e, 0x50 }, + { 0x3a11, 0x60 }, + { 0x3a1f, 0x28 }, + { 0x4001, 0x02 }, + { 0x4004, 0x02 }, + { 0x4000, 0x09 }, + { 0x4837, 0x24 }, + { 0x4050, 0x6e }, + { 0x4051, 0x8f }, + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +static struct sensor_cmd ov5647_sensor_common_test[] = { + { 0x3034, 0x1A }, // 10 bit mode + { 0x503D, 0x80 }, +// { 0x3035, 0x21 }, +// { 0x3036, 0x46 }, +// { 0x303c, 0x11 }, + { 0x3106, 0xf5 }, +// { 0x3821, 0x07 }, +// { 0x3820, 0x41 }, + { 0x3827, 0xec }, + { 0x370c, 0x0f }, +// { 0x3612, 0x59 }, +// { 0x3618, 0x00 }, + { 0x5000, 0x06 }, + { 0x5001, 0x00 }, + { 0x5002, 0x40 }, + { 0x5003, 0x08 }, + { 0x5a00, 0x08 }, + { 0x3000, 0x00 }, + { 0x3001, 0x00 }, + { 0x3002, 0x00 }, + { 0x3016, 0x08 }, + { 0x3017, 0xe0 }, + { 0x3018, 0x44 }, + { 0x301c, 0xf8 }, + { 0x301d, 0xf0 }, + { 0x3a18, 0x00 }, + { 0x3a19, 0xf8 }, + { 0x3c01, 0x80 }, + { 0x3b07, 0x0c }, +// { 0x380c, 0x07 }, +// { 0x380d, 0x68 }, +// { 0x380e, 0x03 }, +// { 0x380f, 0xd8 }, +// { 0x3814, 0x31 }, +// { 0x3815, 0x31 }, +// { 0x3708, 0x64 }, +// { 0x3709, 0x52 }, + { 0x3630, 0x2e }, + { 0x3632, 0xe2 }, + { 0x3633, 0x23 }, + { 0x3634, 0x44 }, + { 0x3636, 0x06 }, + { 0x3620, 0x64 }, + { 0x3621, 0xe0 }, + { 0x3600, 0x37 }, + { 0x3704, 0xa0 }, + { 0x3703, 0x5a }, + { 0x3715, 0x78 }, + { 0x3717, 0x01 }, + { 0x3731, 0x02 }, + { 0x370b, 0x60 }, + { 0x3705, 0x1a }, + { 0x3f05, 0x02 }, + { 0x3f06, 0x10 }, + { 0x3f01, 0x0a }, +// { 0x3a08, 0x01 }, +// { 0x3a09, 0x27 }, +// { 0x3a0a, 0x00 }, +// { 0x3a0b, 0xf6 }, +// { 0x3a0d, 0x04 }, +// { 0x3a0e, 0x03 }, + { 0x3a0f, 0x58 }, + { 0x3a10, 0x50 }, + { 0x3a1b, 0x58 }, + { 0x3a1e, 0x50 }, + { 0x3a11, 0x60 }, + { 0x3a1f, 0x28 }, + { 0x4001, 0x02 }, +// { 0x4004, 0x02 }, + { 0x4000, 0x09 }, +// { 0x4837, 0x24 }, + { 0x4050, 0x6e }, + { 0x4051, 0x8f }, + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +/* 2592 x 1944 @ 15 fps */ + /* + * MIPI Link : 425.000 Mbps + * Pixel clock : 85.000 MHz + * Timing zone : 2752 x 1974 + * FPS : 15.6 + */ +static struct sensor_cmd ov5647_sensor_2592_1944_15[] = { + { 0x3035, 0x21 }, + { 0x3036, 0x66 }, + { 0x303c, 0x11 }, + { 0x3821, 0x06 }, + { 0x3820, 0x00 }, + { 0x3612, 0x5b }, + { 0x3618, 0x04 }, + { 0x380c, 0x0a }, + { 0x380d, 0xc0 }, + { 0x380e, 0x07 }, + { 0x380f, 0xb6 }, + { 0x3814, 0x11 }, + { 0x3815, 0x11 }, + { 0x3708, 0x64 }, + { 0x3709, 0x12 }, + { 0x3808, 0x0a }, + { 0x3809, 0x20 }, + { 0x380a, 0x07 }, + { 0x380b, 0x98 }, + { 0x3800, 0x00 }, + { 0x3801, 0x0c }, + { 0x3802, 0x00 }, + { 0x3803, 0x02 }, + { 0x3804, 0x0a }, + { 0x3805, 0x33 }, + { 0x3806, 0x07 }, + { 0x3807, 0xa1 }, + { 0x3a08, 0x01 }, + { 0x3a09, 0x28 }, + { 0x3a0a, 0x00 }, + { 0x3a0b, 0xf6 }, + { 0x3a0d, 0x07 }, + { 0x3a0e, 0x06 }, + { 0x4004, 0x04 }, + { 0x4837, 0x19 }, + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +/* 1936 x 1088 @ 30 fps */ + /* + * MIPI Link : 416.667 Mbps + * Pixel clock : 83.333 MHz + * Timing zone : 2416 x 1104 + * FPS : 31.2 + */ +static struct sensor_cmd ov5647_sensor_1936_1088_30[] = { + { 0x3035, 0x21 }, + { 0x3036, 0x64 }, + { 0x303c, 0x11 }, + { 0x3821, 0x06 }, + { 0x3820, 0x00 }, + { 0x3612, 0x5b }, + { 0x3618, 0x04 }, + { 0x380c, 0x09 }, + { 0x380d, 0x70 }, + { 0x380e, 0x04 }, + { 0x380f, 0x50 }, + { 0x3814, 0x11 }, + { 0x3815, 0x11 }, + { 0x3708, 0x64 }, + { 0x3709, 0x12 }, + { 0x3808, 0x07 }, + { 0x3809, 0x90 }, /* 80 */ + { 0x380a, 0x04 }, + { 0x380b, 0x40 }, /* 38 */ + { 0x3800, 0x01 }, + { 0x3801, 0x54 }, /* 5c */ + { 0x3802, 0x01 }, + { 0x3803, 0xb0 }, /* b2 */ + { 0x3804, 0x08 }, + { 0x3805, 0xeb }, /* e3 */ + { 0x3806, 0x05 }, + { 0x3807, 0xf3 }, /* f1 */ + { 0x3a08, 0x01 }, + { 0x3a09, 0x4b }, + { 0x3a0a, 0x01 }, + { 0x3a0b, 0x13 }, + { 0x3a0d, 0x04 }, + { 0x3a0e, 0x03 }, + { 0x4004, 0x04 }, + { 0x4837, 0x19 }, + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +/* 1296 x 968 @ 30 fps */ + /* + * MIPI Link : 291.667 Mbps + * Pixel clock : 58.333 MHz + * Timing zone : 1896 x 984 + * FPS : 31.3 + */ +static struct sensor_cmd ov5647_sensor_1296_968_30[] = { + { 0x3035, 0x21 }, + { 0x3036, 0x46 }, + { 0x303c, 0x11 }, + { 0x3821, 0x07 }, + { 0x3820, 0x41 }, + { 0x3612, 0x59 }, + { 0x3618, 0x00 }, + { 0x380c, 0x07 }, + { 0x380d, 0x68 }, + { 0x380e, 0x03 }, + { 0x380f, 0xd8 }, + { 0x3814, 0x31 }, + { 0x3815, 0x31 }, + { 0x3708, 0x64 }, + { 0x3709, 0x52 }, + { 0x3808, 0x05 }, + { 0x3809, 0x10 }, /* 00 */ + { 0x380a, 0x03 }, + { 0x380b, 0xc8 }, /* c0 */ + { 0x3800, 0x00 }, + { 0x3801, 0x00 }, /* 18 */ + { 0x3802, 0x00 }, + { 0x3803, 0x08 }, /* 0e */ + { 0x3804, 0x0a }, + { 0x3805, 0x3b }, /* 27 */ + { 0x3806, 0x07 }, + { 0x3807, 0x9b }, /* 95 */ + { 0x3a08, 0x01 }, + { 0x3a09, 0x27 }, + { 0x3a0a, 0x00 }, + { 0x3a0b, 0xf6 }, + { 0x3a0d, 0x04 }, + { 0x3a0e, 0x03 }, + { 0x4004, 0x02 }, + { 0x4837, 0x24 }, + + { 0x5001, 0x01 }, // AWB on + { 0x5002, 0x41 }, // AWB on + { TABLE_END, 0x00 }, +}; + +//----------------------------------------------------------------------------------------- + +/* 1280 x 720 @ 30 fps */ + /* + * MIPI Link : 291.667 Mbps + * Pixel clock : 58.333 MHz + * Timing zone : 1896 x 984 + * FPS : 31.3 + */ +static struct sensor_cmd ov5647_sensor_1280_720_30[] = { + { 0x3035, 0x21 }, // * + { 0x3036, 0x46 }, // * PLL multiplier + { 0x303c, 0x11 }, // * PLL div + { 0x3821, 0x07 }, // * Timing + { 0x3820, 0x41 }, // * Timing + { 0x3612, 0x59 }, // ? + { 0x3618, 0x00 }, // ? + { 0x380c, 0x07 }, // * Horisontal size [12:8] 1896 + { 0x380d, 0x68 }, // * Horisontal size [7:0] + { 0x380e, 0x03 }, // * total vertical size [9:8] 984 + { 0x380f, 0xd8 }, // * total vertical size [7:0] + { 0x3814, 0x31 }, // * timing x inc + { 0x3815, 0x31 }, // * timing y inc + { 0x3708, 0x64 }, // + { 0x3709, 0x52 }, // + { 0x3808, 0x05 }, // out horisontal [11:8] 1280 + { 0x3809, 0x00 }, // out horisontal [7:0] + { 0x380a, 0x02 }, // out vertical [11:8] 720 + { 0x380b, 0xd0 }, // out vertical [7:0] + { 0x3800, 0x00 }, // + X start [11:8] + { 0x3801, 0x00 }, // + X start [7:0] /* 18 */ + { 0x3802, 0x00 }, // + Y start [11:8] + { 0x3803, 0x08 }, // + Y start [7:0] /* 0e */ + { 0x3804, 0x0a }, // + X end [11:8] + { 0x3805, 0x3b }, // + X end [7:0] /* 27 */ + { 0x3806, 0x07 }, // + Y end [11:8] + { 0x3807, 0x9b }, // + Y end [7:0] /* 95 */ + { 0x3a08, 0x01 }, // + { 0x3a09, 0x27 }, // + { 0x3a0a, 0x00 }, // + { 0x3a0b, 0xf6 }, // + { 0x3a0d, 0x04 }, // + { 0x3a0e, 0x03 }, // + { 0x4004, 0x02 }, // + { 0x4837, 0x24 }, // * PCLK period + + { 0x5001, 0x01 }, // AWB on + { 0x5002, 0x41 }, // AWB on + + { TABLE_END, 0x00 }, // +}; + +//----------------------------------------------------------------------------------------- + +static struct sensor_cmd ov5647_sensor_640_480_90[] = { + { 0x3035, 0x11 }, + { 0x3036, 0x2a }, + { 0x3821, 0x07 }, + { 0x3820, 0x41 }, + { 0x3612, 0x49 }, + { 0x3618, 0x00 }, + { 0x380c, 0x07 }, + { 0x380d, 0x30 }, + { 0x380e, 0x01 }, + { 0x380f, 0x78 }, + { 0x3814, 0x71 }, + { 0x3815, 0x31 }, + { 0x3709, 0x52 }, + { 0x3808, 0x02 }, + { 0x3809, 0x80 }, + { 0x380a, 0x01 }, + { 0x380b, 0xe8 }, + { 0x3800, 0x00 }, + { 0x3801, 0x10 }, + { 0x3802, 0x00 }, + { 0x3803, 0x00 }, + { 0x3804, 0x0a }, + { 0x3805, 0x2f }, + { 0x3806, 0x07 }, + { 0x3807, 0x9f }, + { 0x4004, 0x02 }, + { TABLE_END, 0x00 }, // +}; + +//----------------------------------------------------------------------------------------- +static const struct sensor_cmd imx219_miscellaneous[] = { + { 0x30EB, 0x05 }, /* Access Code for address over 0x3000 */ + { 0x30EB, 0x0C }, /* Access Code for address over 0x3000 */ + { 0x300A, 0xFF }, /* Access Code for address over 0x3000 */ + { 0x300B, 0xFF }, /* Access Code for address over 0x3000 */ + { 0x30EB, 0x05 }, /* Access Code for address over 0x3000 */ + { 0x30EB, 0x09 }, /* Access Code for address over 0x3000 */ + { 0x0114, 0x03 }, /* CSI_LANE_MODE[1:0} */ + { 0x0128, 0x00 }, /* DPHY_CNTRL */ + { 0x012A, 0x18 }, /* EXCK_FREQ[15:8] */ + { 0x012B, 0x00 }, /* EXCK_FREQ[7:0] */ + { 0x0160, 0x0A }, /* FRM_LENGTH_A[15:8] */ + { 0x0161, 0x83 }, /* FRM_LENGTH_A[7:0] */ + { 0x0162, 0x0D }, /* LINE_LENGTH_A[15:8] */ + { 0x0163, 0x78 }, /* LINE_LENGTH_A[7:0] */ + { 0x0170, 0x01 }, /* X_ODD_INC_A[2:0] */ + { 0x0171, 0x01 }, /* Y_ODD_INC_A[2:0] */ + { 0x0174, 0x00 }, /* BINNING_MODE_H_A */ + { 0x0175, 0x00 }, /* BINNING_MODE_V_A */ + { 0x018C, 0x0A }, /* CSI_DATA_FORMAT_A[15:8] */ + { 0x018D, 0x0A }, /* CSI_DATA_FORMAT_A[7:0] */ + { 0x0301, 0x05 }, /* VTPXCK_DIV */ + { 0x0303, 0x01 }, /* VTSYCK_DIV */ + { 0x0304, 0x03 }, /* PREPLLCK_VT_DIV[3:0] */ + { 0x0305, 0x03 }, /* PREPLLCK_OP_DIV[3:0] */ + { 0x0306, 0x00 }, /* PLL_VT_MPY[10:8] */ + { 0x0307, 0x57 }, /* PLL_VT_MPY[7:0] */ + { 0x0309, 0x0A }, /* OPPXCK_DIV[4:0] */ + { 0x030B, 0x01 }, /* OPSYCK_DIV */ + { 0x030C, 0x00 }, /* PLL_OP_MPY[10:8] */ + { 0x030D, 0x5A }, /* PLL_OP_MPY[7:0] */ + { 0x455E, 0x00 }, /* CIS Tuning */ + { 0x471E, 0x4B }, /* CIS Tuning */ + { 0x4767, 0x0F }, /* CIS Tuning */ + { 0x4750, 0x14 }, /* CIS Tuning */ + { 0x4540, 0x00 }, /* CIS Tuning */ + { 0x47B4, 0x14 }, /* CIS Tuning */ + { 0x4713, 0x30 }, /* CIS Tuning */ + { 0x478B, 0x10 }, /* CIS Tuning */ + { 0x478F, 0x10 }, /* CIS Tuning */ + { 0x4793, 0x10 }, /* CIS Tuning */ + { 0x4797, 0x0E }, /* CIS Tuning */ + { 0x479B, 0x0E }, /* CIS Tuning */ + { TABLE_END, 0x00 } +}; +/* 3280x2464@15 FPS */ +static const struct sensor_cmd imx219_1test[] = { + {0x0100, 0x00}, // 0=OFF, 1=Stream, 2=MAX + {0x30EB, 0x05}, + {0x30EB, 0x0C}, + {0x300A, 0xFF}, + {0x300B, 0xFF}, + {0x30EB, 0x05}, + {0x30EB, 0x09}, + {0x0114, 0x01}, // CSI MIPI Lanes [1:0] (0x01=2, 0x03=4) + {0x0128, 0x00}, // DPHY_CNTRL + {0x012A, 0x18}, // EXCK_FREQ [15:8] + {0x012B, 0x00}, // EXCK_FREQ [7:0] + {0x0157, 0x00}, // Analog Gain + {0x0158, 0x00}, // Digital Gain [15:8] + {0x0159, 0x00}, // Digital Gain [7:0] + // {0x015A, 0x01}, // Shutter/Integration Time [15:8] + // {0x015B, 0x00}, // Shutter/Integration Time [7:0] + {0x0160, 0x09}, // Frame Length [15:8] + {0x0161, 0xC8}, // Frame Length [7:0] + {0x0162, 0x0D}, // Line Length [15:8] + {0x0163, 0x78}, // Line Length [7:0] + {0x0164, 0x00}, + {0x0165, 0x00}, + {0x0166, 0x0C}, + {0x0167, 0xCF}, + {0x0168, 0x00}, + {0x0169, 0x00}, + {0x016A, 0x09}, + {0x016B, 0x9F}, + {0x016C, 0x0C}, + {0x016D, 0xD0}, + {0x016E, 0x09}, + {0x016F, 0xA0}, + {0x0170, 0x01}, // X_ODD_INC [2:0] + {0x0171, 0x01}, // Y_ODD_INC [2:0] + {0x0172, 0x03}, + {0x0174, 0x00}, // Binning Mode H_A + {0x0175, 0x00}, // Binning Mode V_A + {0x018C, 0x0A}, // CSI Data Format [15:8] + {0x018D, 0x0A}, // CSI Data Format [7:0] + {0x0301, 0x05}, // VTPXCK_DIV + {0x0303, 0x01}, // VTSYCK_DIV + {0x0304, 0x03}, // PREPLLCK_VT_DIV [3:0] + {0x0305, 0x03}, // PREPLLCK_OP_DIV [3:0] + {0x0306, 0x00}, // PLL_VT_MPY [10:8] + {0x0307, 0x2B}, // PLL_VT_MPY [7:0] + {0x0309, 0x0A}, // OPPXCK_DIV [4:0] + {0x030B, 0x01}, // OPSYCK_DIV + {0x030C, 0x00}, // PLL_OP_MPY [10:8] + {0x030D, 0x55}, // PLL_OP_MPY [7:0] + {0x455E, 0x00}, // CIS Tuning ? + {0x471E, 0x4B}, // CIS Tuning ? + {0x4767, 0x0F}, // CIS Tuning ? + {0x4750, 0x14}, // CIS Tuning ? + {0x4540, 0x00}, // CIS Tuning ? + {0x47B4, 0x14}, // CIS Tuning ? + {0x4713, 0x30}, // CIS Tuning ? + {0x478B, 0x10}, // CIS Tuning ? + {0x478F, 0x10}, // CIS Tuning ? + {0x4797, 0x0E}, // CIS Tuning ? + {0x479B, 0x0E}, // CIS Tuning ? + {TABLE_END, 0x00} +}; + +static struct sensor_cmd imx219_720p_regs[] = { //720: 1280*720@30fps + {0x30EB, 0x05}, + {0x30EB, 0x0C}, + {0x300A, 0xFF}, + {0x300B, 0xFF}, + {0x30EB, 0x05}, + {0x30EB, 0x09}, + + {0x0114, 0x01}, // CSI_LANE_MODE = 2-lane + {0x0128, 0x00}, // DPHY_CTRL = auto mode + + {0x012A, 0x13}, // EXCLK_FREQ[15:8] + {0x012B, 0x34}, // EXCLK_FREQ[7:0] = 4916 MHz + + {0x0160, 0x04}, // FRM_LENGTH_A[15:8] + {0x0161, 0x60}, // FRM_LENGTH_A[7:0] = 1120 + {0x0162, 0x0D}, // LINE_LENGTH_A[15:8] + {0x0163, 0x78}, // LINE_LENGTH_A[7:0] = 3448 + {0x0164, 0x01}, // XADD_STA_A[11:8] + {0x0165, 0x58}, // XADD_STA_A[7:0] = X top left = 344 + {0x0166, 0x0B}, // XADD_END_A[11:8] + {0x0167, 0x77}, // XADD_END_A[7:0] = X bottom right = 2935 + {0x0168, 0x01}, // YADD_STA_A[11:8] + {0x0169, 0xF0}, // YADD_STA_A[7:0] = Y top left = 496 + {0x016A, 0x07}, // YADD_END_A[11:8] + {0x016B, 0xAF}, // YADD_END_A[7:0] = Y bottom right = 1967 + {0x016C, 0x05}, // x_output_size[11:8] + {0x016D, 0x10}, // x_output_size[7:0] = 1296 + {0x016E, 0x02}, // y_output_size[11:8] + {0x016F, 0xE0}, // y_output_size[7:0] = 736 + {0x0170, 0x01}, // X_ODD_INC_A + {0x0171, 0x01}, // Y_ODD_INC_A + {0x0174, 0x01}, // BINNING_MODE_H_A = x2-binning + {0x0175, 0x01}, // BINNING_MODE_V_A = x2-binning +// {0x0174, 0x00}, // BINNING_MODE_H_A = no-binning +// {0x0175, 0x00}, // BINNING_MODE_V_A = no-binning + {0x0176, 0x01}, // BINNING_CAL_MODE_H_A + {0x0177, 0x01}, // BINNING_CAL_MODE_V_A + {0x018C, 0x0A}, // CSI_DATA_FORMAT_A[15:8] + {0x018D, 0x0A}, // CSI_DATA_FORMAT_A[7:0] + {0x0301, 0x05}, + {0x0303, 0x01}, + {0x0304, 0x02}, + {0x0305, 0x02}, + {0x0309, 0x0A}, // OPPXCK_DIV + {0x030B, 0x01}, // OPSYCK_DIV + + {0x0306, 0x00}, // PLL_VT_MPY[10:8] + //{0x0307, 0x2E}, // PLL_VT_MPY[7:0] = 46 + {0x0307, 0x17}, // PLL_VT_MPY[7:0] = 23 + //{0x0307, 0x0F}, // PLL_VT_MPY[7:0] = 15 + + {0x030C, 0x00}, // PLL_OP_MPY[10:8] + //{0x030D, 0x5C}, // PLL_OP_MPY[7:0] = 92 + {0x030D, 0x2E}, // PLL_OP_MPY[7:0] = 46 + //{0x030D, 0x1E}, // PLL_OP_MPY[7:0] = 30 + + {0x455E, 0x00}, + {0x471E, 0x4B}, + {0x4767, 0x0F}, + {0x4750, 0x14}, + {0x4540, 0x00}, + {0x47B4, 0x14}, + {0x4713, 0x30}, + {0x478B, 0x10}, + {0x478F, 0x10}, + {0x4793, 0x10}, + {0x4797, 0x0E}, + {0x479B, 0x0E}, + //{0x0601, 0x02}, // Test pattern = Color bar + {0x0601, 0x00}, // Test pattern = Normal work + {0x0620, 0x00}, // TP_WINDOW_X_OFFSET[11:8] + {0x0621, 0x00}, // TP_WINDOW_X_OFFSET[7:0] + {0x0621, 0x00}, // TP_WINDOW_Y_OFFSET[11:8] + {0x0623, 0x00}, // TP_WINDOW_Y_OFFSET[7:0] + {0x0624, 0x05}, // TP_WINDOW_WIDTH[11:8] + {0x0625, 0x00}, // TP_WINDOW_WIDTH[7:0] = 1280 + {0x0626, 0x02}, // TP_WINDOW_HEIGHT[11:8] + {0x0627, 0xD0}, // TP_WINDOW_HEIGHT[7:0] = 720 + {0x0100, 0x01}, /* mode select streaming on */ + {TABLE_END, 0x00} +}; + +static struct sensor_cmd imx219_720p_45fps_regs[] = { //720: 1280*720@45fps + {0x30EB, 0x05}, + {0x30EB, 0x0C}, + {0x300A, 0xFF}, + {0x300B, 0xFF}, + {0x30EB, 0x05}, + {0x30EB, 0x09}, + + {0x0114, 0x01}, + {0x0128, 0x00}, + + {0x012A, 0x13}, // EXCLK_FREQ[15:8] + {0x012B, 0x34}, // EXCLK_FREQ[7:0] = 4916 MHz + +// {0x012A, 0x09}, // EXCLK_FREQ[15:8] +// {0x012B, 0x9A}, // EXCLK_FREQ[7:0] = 2458 MHz + +// {0x012A, 0x26}, // * EXCLK_FREQ[15:8] +// {0x012B, 0x68}, // * EXCLK_FREQ[7:0] = 4916 MHz +// {0x012A, 0x18}, // * EXCLK_FREQ[15:8] +// {0x012B, 0x00}, // * EXCLK_FREQ[7:0] = 4916 MHz + + {0x0160, 0x04}, + {0x0161, 0x60}, + {0x0162, 0x0D}, + {0x0163, 0x78}, + {0x0164, 0x01}, + {0x0165, 0x58}, + {0x0166, 0x0B}, + {0x0167, 0x77}, + {0x0168, 0x01}, + {0x0169, 0xF0}, + {0x016A, 0x07}, + {0x016B, 0xAF}, + {0x016C, 0x05}, + {0x016D, 0x10}, + {0x016E, 0x02}, + {0x016F, 0xE0}, + {0x0170, 0x01}, + {0x0171, 0x01}, + {0x0174, 0x01}, + {0x0175, 0x01}, + {0x0176, 0x01}, + {0x0177, 0x01}, + {0x018C, 0x0A}, + {0x018D, 0x0A}, + {0x0301, 0x05}, + {0x0303, 0x01}, + {0x0304, 0x02}, + {0x0305, 0x02}, + {0x0306, 0x00}, + {0x0307, 0x2E}, + {0x0309, 0x0A}, + {0x030B, 0x01}, + + //{0x030C, 0x00}, // PLL_OP_MPY[10:8] + //{0x030D, 0x5C}, // PLL_OP_MPY[7:0] = 92 + + {0x030C, 0x00}, // PLL_OP_MPY[10:8] + {0x030D, 0xB8}, // PLL_OP_MPY[7:0] = 184 + + {0x455E, 0x00}, + {0x471E, 0x4B}, + {0x4767, 0x0F}, + {0x4750, 0x14}, + {0x4540, 0x00}, + {0x47B4, 0x14}, + {0x4713, 0x30}, + {0x478B, 0x10}, + {0x478F, 0x10}, + {0x4793, 0x10}, + {0x4797, 0x0E}, + {0x479B, 0x0E}, + {0x0100, 0x01}, /* mode select streaming on */ + {TABLE_END, 0x00} +}; + + + +static const struct sensor_cmd imx219_start[] = { + {0x0100, 0x01}, /* mode select streaming on */ + {TABLE_END, 0x00} +}; +static const struct sensor_cmd imx219_stop[] = { + {0x0100, 0x00}, /* mode select streaming off */ + {TABLE_END, 0x00} +}; +static const struct sensor_cmd imx219_test_color_bar[] = { + {0x0600, 0x00}, + {0x0601, 0x02}, + {TABLE_END, 0x00} +}; + +struct sensor_rect { + unsigned short left; + unsigned short top; + unsigned short width; + unsigned short height; +}; + +static const struct sensor_rect imx219_center_1280x720_rect = { + 1000, 872, 1280, 720 +}; + + +#endif diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/startup/files/startup.c b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/startup/files/startup.c new file mode 100644 index 0000000..62523b0 --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-apps/startup/files/startup.c @@ -0,0 +1,39 @@ +/* +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person +* obtaining a copy of this software and associated documentation +* files (the "Software"), to deal in the Software without restriction, +* including without limitation the rights to use, copy, modify, merge, +* publish, distribute, sublicense, and/or sell copies of the Software, +* and to permit persons to whom the Software is furnished to do so, +* subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or (b) that interact +* with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in this +* Software without prior written authorization from Xilinx. +* +*/ + +#include + +int main(int argc, char **argv) +{ + printf("Hello World!\n"); + + return 0; +} diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h new file mode 100644 index 0000000..b6bda5d --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h @@ -0,0 +1,4 @@ + +#include +#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot; echo; fatload mmc 0 0x1FC00000 u-boot.rgba" + diff --git a/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-modules/te-audio-codec/files/te-audio-codec.c b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-modules/te-audio-codec/files/te-audio-codec.c new file mode 100644 index 0000000..5b9575d --- /dev/null +++ b/zynqberrydemo3/os/petalinux/project-spec/meta-user/recipes-modules/te-audio-codec/files/te-audio-codec.c @@ -0,0 +1,99 @@ +/* + * ALSA SoC SPDIF DIT driver + * + * This driver is used by controllers which can operate in DIT (SPDI/F) where + * no codec is needed. This file provides stub codec that can be used + * in these configurations. TI DaVinci Audio controller uses this driver. + * + * Author: Steve Chen, + * Copyright: (C) 2009 MontaVista Software, Inc., + * Copyright: (C) 2009 Texas Instruments, India + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "te-audio-codec" + +#define STUB_RATES (SNDRV_PCM_RATE_8000_192000 | \ + SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \ + SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000) +#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dapm_widget dit_widgets[] = { + SND_SOC_DAPM_OUTPUT("te-out"), +}; + +static const struct snd_soc_dapm_route dit_routes[] = { + { "te-out", NULL, "Playback" }, +}; + +static struct snd_soc_codec_driver soc_codec_spdif_dit = { + .component_driver = { + .dapm_widgets = dit_widgets, + .num_dapm_widgets = ARRAY_SIZE(dit_widgets), + .dapm_routes = dit_routes, + .num_dapm_routes = ARRAY_SIZE(dit_routes), + }, +}; + +static struct snd_soc_dai_driver dit_stub_dai = { + .name = "dit-hifi", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 384, + .rates = STUB_RATES, + .formats = STUB_FORMATS, + }, +}; + +static int spdif_dit_probe(struct platform_device *pdev) +{ + return snd_soc_register_codec(&pdev->dev, &soc_codec_spdif_dit, + &dit_stub_dai, 1); +} + +static int spdif_dit_remove(struct platform_device *pdev) +{ + snd_soc_unregister_codec(&pdev->dev); + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id spdif_dit_dt_ids[] = { + { .compatible = "te,te-audio", }, + { } +}; +MODULE_DEVICE_TABLE(of, spdif_dit_dt_ids); +#endif + +static struct platform_driver spdif_dit_driver = { + .probe = spdif_dit_probe, + .remove = spdif_dit_remove, + .driver = { + .name = DRV_NAME, + .of_match_table = of_match_ptr(spdif_dit_dt_ids), + }, +}; + +module_platform_driver(spdif_dit_driver); + +MODULE_AUTHOR("Steve Chen "); +MODULE_DESCRIPTION("SPDIF dummy codec driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:" DRV_NAME); + diff --git a/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_io_report.txt b/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_io_report.txt new file mode 100644 index 0000000..57bed7b --- /dev/null +++ b/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_io_report.txt @@ -0,0 +1,267 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Tue Jun 13 10:05:17 2017 +| Host : W8-64-02 running 64-bit major release (build 9200) +| Command : report_io -force -file B:/Design/cores/2017.1/design/TE0726/zynqberrydemo3/vivado/zynqberrydemo3.runs/impl_1/zynqberrydemo3_io_report.txt -format text +| Design : zsys_wrapper +| Device : xc7z007s +| Speed File : -1 +| Package : clg225 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 130 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | ++------------+-------------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A2 | DDR_dq[1] | | PS_DDR_DQ1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A3 | DDR_dq[7] | | PS_DDR_DQ7_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A4 | DDR_dq[5] | | PS_DDR_DQ5_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A5 | FIXED_IO_mio[1] | | PS_MIO1_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| A7 | FIXED_IO_mio[3] | | PS_MIO3_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A8 | FIXED_IO_mio[2] | | PS_MIO2_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A9 | FIXED_IO_mio[5] | | PS_MIO5_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A10 | FIXED_IO_mio[6] | | PS_MIO6_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A12 | FIXED_IO_mio[30] | | PS_MIO52_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A13 | FIXED_IO_mio[26] | | PS_MIO38_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A14 | FIXED_IO_mio[23] | | PS_MIO35_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| A15 | FIXED_IO_mio[16] | | PS_MIO28_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B1 | DDR_dm[0] | | PS_DDR_DM0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| B4 | DDR_dq[4] | | PS_DDR_DQ4_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B6 | FIXED_IO_mio[8] | | PS_MIO8_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B7 | FIXED_IO_mio[12] | | PS_MIO12_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B9 | FIXED_IO_mio[14] | | PS_MIO14_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B10 | FIXED_IO_mio[11] | | PS_MIO11_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B11 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B12 | FIXED_IO_mio[28] | | PS_MIO48_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| B14 | FIXED_IO_mio[24] | | PS_MIO36_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| B15 | FIXED_IO_mio[18] | | PS_MIO30_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C1 | DDR_dq[3] | | PS_DDR_DQ3_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C3 | DDR_dq[6] | | PS_DDR_DQ6_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C4 | DDR_dq[2] | | PS_DDR_DQ2_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C6 | FIXED_IO_mio[13] | | PS_MIO13_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C8 | FIXED_IO_mio[4] | | PS_MIO4_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C9 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C10 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| C11 | FIXED_IO_mio[21] | | PS_MIO33_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C12 | FIXED_IO_mio[19] | | PS_MIO31_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C13 | FIXED_IO_mio[31] | | PS_MIO53_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C14 | FIXED_IO_mio[25] | | PS_MIO37_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| C15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D1 | DDR_dq[9] | | PS_DDR_DQ9_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D3 | DDR_dm[1] | | PS_DDR_DM1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D4 | DDR_dq[0] | | PS_DDR_DQ0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D5 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | +| D6 | FIXED_IO_mio[10] | | PS_MIO10_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| D8 | FIXED_IO_mio[0] | | PS_MIO0_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D9 | FIXED_IO_mio[7] | | PS_MIO7_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D10 | FIXED_IO_mio[15] | | PS_MIO15_500 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D11 | FIXED_IO_mio[17] | | PS_MIO29_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D13 | FIXED_IO_mio[29] | | PS_MIO49_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D14 | FIXED_IO_mio[27] | | PS_MIO39_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| D15 | FIXED_IO_mio[22] | | PS_MIO34_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| E1 | DDR_dq[8] | | PS_DDR_DQ8_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| E2 | DDR_dq[10] | | PS_DDR_DQ10_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| E3 | DDR_dq[11] | | PS_DDR_DQ11_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| E4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E6 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E8 | | | RSVDGND | GND | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| E11 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | +| E12 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | +| E13 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | +| E14 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| E15 | FIXED_IO_mio[20] | | PS_MIO32_501 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| F1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| F2 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| F3 | DDR_dq[12] | | PS_DDR_DQ12_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| F4 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | +| F5 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | +| F6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | +| F7 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | +| F8 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | +| F9 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| F10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F11 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | +| F12 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | +| F13 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | +| F14 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | +| F15 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | +| G1 | DDR_dq[13] | | PS_DDR_DQ13_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| G2 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| G3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G4 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G6 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| G7 | Vp_Vn_v_p | Dedicated | VP_0 | INPUT | LVCMOS18* | 0 | | | | NONE | | UNFIXED | | | | NONE | +| G8 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | +| G9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| G11 | gpio_1_tri_io[13] | High Range | IO_L1P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G12 | gpio_1_tri_io[23] | High Range | IO_L2P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G14 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | +| G15 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | +| H1 | DDR_dq[14] | | PS_DDR_DQ14_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| H2 | DDR_dq[15] | | PS_DDR_DQ15_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| H3 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| H4 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | +| H5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| H6 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H7 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | +| H8 | Vp_Vn_v_n | Dedicated | VN_0 | INPUT | LVCMOS18* | 0 | | | | NONE | | UNFIXED | | | | NONE | +| H9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| H10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H11 | gpio_1_tri_io[14] | High Range | IO_L6P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H12 | gpio_1_tri_io[2] | High Range | IO_L1N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H13 | gpio_1_tri_io[18] | High Range | IO_L2N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H14 | gpio_1_tri_io[8] | High Range | IO_L3N_T0_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H15 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | +| J1 | DDR_addr[10] | | PS_DDR_A10_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| J2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| J3 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| J4 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | +| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| J7 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | +| J8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| J11 | gpio_1_tri_io[19] | High Range | IO_L6N_T0_VREF_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J12 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| J13 | gpio_1_tri_io[7] | High Range | IO_L5P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J14 | gpio_1_tri_io[1] | High Range | IO_L5N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J15 | gpio_1_tri_io[9] | High Range | IO_L4P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K1 | DDR_addr[14] | | PS_DDR_A14_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| K2 | DDR_addr[13] | | PS_DDR_A13_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| K3 | DDR_odt | | PS_DDR_ODT_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| K6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K8 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | +| K9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| K10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K11 | gpio_1_tri_io[20] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K12 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| K13 | gpio_1_tri_io[21] | High Range | IO_L10P_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K15 | gpio_1_tri_io[0] | High Range | IO_L4N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L2 | DDR_addr[11] | | PS_DDR_A11_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| L3 | DDR_cke | | PS_DDR_CKE_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| L4 | DDR_reset_n | | PS_DDR_DRST_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| L7 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | +| L8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | +| L9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L12 | gpio_1_tri_io[22] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L13 | gpio_1_tri_io[12] | High Range | IO_L10N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L14 | gpio_1_tri_io[5] | High Range | IO_L9P_T1_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L15 | gpio_1_tri_io[6] | High Range | IO_L8P_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M1 | DDR_addr[2] | | PS_DDR_A2_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M2 | DDR_addr[12] | | PS_DDR_A12_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| M4 | DDR_addr[3] | | PS_DDR_A3_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M5 | DDR_addr[7] | | PS_DDR_A7_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M6 | DDR_ba[0] | | PS_DDR_BA0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| M7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | +| M8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M9 | csi_d_lp_n[0] | High Range | IO_L19P_T3_34 | INPUT | HSUL_12 | 34 | | | | NONE | | FIXED | PULLDOWN | | Internal | NONE | +| M10 | csi_d_p[0] | High Range | IO_L21P_T3_DQS_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| M11 | csi_d_n[0] | High Range | IO_L21N_T3_DQS_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| M12 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| M13 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| M14 | gpio_1_tri_io[16] | High Range | IO_L9N_T1_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M15 | gpio_1_tri_io[10] | High Range | IO_L8N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N1 | DDR_addr[1] | | PS_DDR_A1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N2 | DDR_ck_n | | PS_DDR_CKN_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N3 | DDR_ck_p | | PS_DDR_CKP_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N4 | DDR_addr[9] | | PS_DDR_A9_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N6 | DDR_ba[2] | | PS_DDR_BA2_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| N7 | PWM_L | High Range | IO_L22P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N8 | PWM_R | High Range | IO_L22N_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N9 | csi_d_lp_p[0] | High Range | IO_L19N_T3_VREF_34 | INPUT | HSUL_12 | 34 | | | | NONE | | FIXED | PULLDOWN | | Internal | NONE | +| N10 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| N11 | csi_c_clk_p | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| N12 | csi_c_clk_n | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| N13 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | +| N14 | gpio_1_tri_io[3] | High Range | IO_L7N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P1 | DDR_addr[0] | | PS_DDR_A0_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P3 | DDR_addr[4] | | PS_DDR_A4_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P4 | DDR_addr[5] | | PS_DDR_A5_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P5 | DDR_addr[6] | | PS_DDR_A6_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P6 | DDR_addr[8] | | PS_DDR_A8_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| P7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| P8 | hdmi_data_p[0] | High Range | IO_L23P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P9 | hdmi_data_n[0] | High Range | IO_L23N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P10 | hdmi_data_p[1] | High Range | IO_L24P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P11 | hdmi_data_p[2] | High Range | IO_L16P_T2_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P13 | csi_d_p[1] | High Range | IO_L18P_T2_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| P14 | csi_d_n[1] | High Range | IO_L18N_T2_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| P15 | gpio_1_tri_io[17] | High Range | IO_L15P_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R1 | DDR_ba[1] | | PS_DDR_BA1_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R2 | DDR_cs_n | | PS_DDR_CS_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R3 | DDR_we_n | | PS_DDR_WE_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| R5 | DDR_cas_n | | PS_DDR_CAS_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R6 | DDR_ras_n | | PS_DDR_RAS_B_502 | BIDIR | LVCMOS18* | | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | +| R7 | hdmi_clk_p | High Range | IO_L20P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R8 | hdmi_clk_n | High Range | IO_L20N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R10 | hdmi_data_n[1] | High Range | IO_L24N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R11 | hdmi_data_n[2] | High Range | IO_L16N_T2_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R12 | gpio_1_tri_io[15] | High Range | IO_L17P_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R13 | gpio_1_tri_io[11] | High Range | IO_L17N_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| R15 | gpio_1_tri_io[4] | High Range | IO_L15N_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | ++------------+-------------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_io_report.xdc b/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_io_report.xdc new file mode 100644 index 0000000..1bc805c --- /dev/null +++ b/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_io_report.xdc @@ -0,0 +1,535 @@ +set_property DIRECTION IN [get_ports {csi_d_lp_p[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}] +set_property DIRECTION IN [get_ports {csi_d_n[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_n[1]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_n[1]}] +set_property DIRECTION IN [get_ports {csi_d_n[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_n[0]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_n[0]}] +set_property DIRECTION IN [get_ports {csi_d_p[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_p[1]}] +set_property DIRECTION IN [get_ports {csi_d_p[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_p[0]}] +set_property DIRECTION IN [get_ports {csi_d_lp_n[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[2]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[1]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[0]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[2]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[1]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[0]}] +set_property DIRECTION OUT [get_ports hdmi_clk_p] +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p] +set_property DIRECTION OUT [get_ports hdmi_clk_n] +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_n] +set_property DIRECTION IN [get_ports csi_c_clk_p] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p] +set_property DIFF_TERM FALSE [get_ports csi_c_clk_p] +set_property DIRECTION IN [get_ports csi_c_clk_n] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_n] +set_property DIFF_TERM FALSE [get_ports csi_c_clk_n] +set_property DIRECTION IN [get_ports Vp_Vn_v_p] +set_property DIRECTION IN [get_ports Vp_Vn_v_n] +set_property DIRECTION OUT [get_ports PWM_R] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_R] +set_property DRIVE 12 [get_ports PWM_R] +set_property SLEW SLOW [get_ports PWM_R] +set_property DIRECTION OUT [get_ports PWM_L] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_L] +set_property DRIVE 12 [get_ports PWM_L] +set_property SLEW SLOW [get_ports PWM_L] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[23]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[23]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[23]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[23]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[22]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[22]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[22]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[21]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[21]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[21]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[21]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[20]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[20]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[20]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[19]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[19]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[19]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[19]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[18]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[18]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[18]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[17]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[17]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[17]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[17]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[16]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[16]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[16]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[15]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[15]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[15]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[14]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[14]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[14]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[13]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[13]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[13]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[12]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[12]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[12]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[11]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[11]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[11]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[10]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[10]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[10]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[9]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[9]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[9]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[8]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[8]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[8]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[7]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[7]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[7]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[6]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[6]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[6]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[5]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[5]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[5]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[4]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[4]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[4]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[3]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[3]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[3]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[2]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[2]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[2]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[1]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[1]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[1]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[0]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[0]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[0]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[31]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[31]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[31]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[31]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[30]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[30]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[30]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[30]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[29]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[29]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[29]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[29]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[28]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[28]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[28]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[28]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[27]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[27]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[27]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[27]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[26]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[26]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[26]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[26]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[25]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[25]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[25]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[25]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[24]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[24]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[24]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[24]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[23]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[23]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[23]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[23]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[22]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[22]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[22]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[22]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[21]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[21]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[21]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[21]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[20]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[20]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[20]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[20]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[19]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[19]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[19]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[19]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[18]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[18]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[18]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[18]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[17]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[17]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[17]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[17]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[16]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[16]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[16]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[16]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[15]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[15]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[15]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[15]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[14]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[14]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[14]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[13]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[13]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[13]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[12]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[12]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[12]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[11]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[11]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[11]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[10]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[10]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[10]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[9]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[9]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[9]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[8]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[8]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[8]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[7]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[7]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[7]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[6]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[6]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[6]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[5]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[5]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[5]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[4]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[4]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[4]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[3]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[3]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[3]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[2]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[2]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[2]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[1]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[1]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[1]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {FIXED_IO_mio[0]}] +set_property DRIVE 12 [get_ports {FIXED_IO_mio[0]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[0]}] +set_property DIRECTION INOUT [get_ports FIXED_IO_ddr_vrn] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ddr_vrn] +set_property DRIVE 12 [get_ports FIXED_IO_ddr_vrn] +set_property SLEW SLOW [get_ports FIXED_IO_ddr_vrn] +set_property DIRECTION INOUT [get_ports FIXED_IO_ddr_vrp] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ddr_vrp] +set_property DRIVE 12 [get_ports FIXED_IO_ddr_vrp] +set_property SLEW SLOW [get_ports FIXED_IO_ddr_vrp] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_clk] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ps_clk] +set_property DRIVE 12 [get_ports FIXED_IO_ps_clk] +set_property SLEW SLOW [get_ports FIXED_IO_ps_clk] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_porb] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ps_porb] +set_property DRIVE 12 [get_ports FIXED_IO_ps_porb] +set_property SLEW SLOW [get_ports FIXED_IO_ps_porb] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_srstb] +set_property IOSTANDARD LVCMOS18 [get_ports FIXED_IO_ps_srstb] +set_property DRIVE 12 [get_ports FIXED_IO_ps_srstb] +set_property SLEW SLOW [get_ports FIXED_IO_ps_srstb] +set_property DIRECTION INOUT [get_ports {DDR_dqs_p[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dqs_p[1]}] +set_property DRIVE 12 [get_ports {DDR_dqs_p[1]}] +set_property SLEW SLOW [get_ports {DDR_dqs_p[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_p[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dqs_p[0]}] +set_property DRIVE 12 [get_ports {DDR_dqs_p[0]}] +set_property SLEW SLOW [get_ports {DDR_dqs_p[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_n[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dqs_n[1]}] +set_property DRIVE 12 [get_ports {DDR_dqs_n[1]}] +set_property SLEW SLOW [get_ports {DDR_dqs_n[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_n[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dqs_n[0]}] +set_property DRIVE 12 [get_ports {DDR_dqs_n[0]}] +set_property SLEW SLOW [get_ports {DDR_dqs_n[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[15]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[15]}] +set_property DRIVE 12 [get_ports {DDR_dq[15]}] +set_property SLEW SLOW [get_ports {DDR_dq[15]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[14]}] +set_property DRIVE 12 [get_ports {DDR_dq[14]}] +set_property SLEW SLOW [get_ports {DDR_dq[14]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[13]}] +set_property DRIVE 12 [get_ports {DDR_dq[13]}] +set_property SLEW SLOW [get_ports {DDR_dq[13]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[12]}] +set_property DRIVE 12 [get_ports {DDR_dq[12]}] +set_property SLEW SLOW [get_ports {DDR_dq[12]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[11]}] +set_property DRIVE 12 [get_ports {DDR_dq[11]}] +set_property SLEW SLOW [get_ports {DDR_dq[11]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[10]}] +set_property DRIVE 12 [get_ports {DDR_dq[10]}] +set_property SLEW SLOW [get_ports {DDR_dq[10]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[9]}] +set_property DRIVE 12 [get_ports {DDR_dq[9]}] +set_property SLEW SLOW [get_ports {DDR_dq[9]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[8]}] +set_property DRIVE 12 [get_ports {DDR_dq[8]}] +set_property SLEW SLOW [get_ports {DDR_dq[8]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[7]}] +set_property DRIVE 12 [get_ports {DDR_dq[7]}] +set_property SLEW SLOW [get_ports {DDR_dq[7]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[6]}] +set_property DRIVE 12 [get_ports {DDR_dq[6]}] +set_property SLEW SLOW [get_ports {DDR_dq[6]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[5]}] +set_property DRIVE 12 [get_ports {DDR_dq[5]}] +set_property SLEW SLOW [get_ports {DDR_dq[5]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[4]}] +set_property DRIVE 12 [get_ports {DDR_dq[4]}] +set_property SLEW SLOW [get_ports {DDR_dq[4]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[3]}] +set_property DRIVE 12 [get_ports {DDR_dq[3]}] +set_property SLEW SLOW [get_ports {DDR_dq[3]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[2]}] +set_property DRIVE 12 [get_ports {DDR_dq[2]}] +set_property SLEW SLOW [get_ports {DDR_dq[2]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[1]}] +set_property DRIVE 12 [get_ports {DDR_dq[1]}] +set_property SLEW SLOW [get_ports {DDR_dq[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dq[0]}] +set_property DRIVE 12 [get_ports {DDR_dq[0]}] +set_property SLEW SLOW [get_ports {DDR_dq[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dm[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dm[1]}] +set_property DRIVE 12 [get_ports {DDR_dm[1]}] +set_property SLEW SLOW [get_ports {DDR_dm[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dm[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_dm[0]}] +set_property DRIVE 12 [get_ports {DDR_dm[0]}] +set_property SLEW SLOW [get_ports {DDR_dm[0]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_ba[2]}] +set_property DRIVE 12 [get_ports {DDR_ba[2]}] +set_property SLEW SLOW [get_ports {DDR_ba[2]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_ba[1]}] +set_property DRIVE 12 [get_ports {DDR_ba[1]}] +set_property SLEW SLOW [get_ports {DDR_ba[1]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_ba[0]}] +set_property DRIVE 12 [get_ports {DDR_ba[0]}] +set_property SLEW SLOW [get_ports {DDR_ba[0]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[14]}] +set_property DRIVE 12 [get_ports {DDR_addr[14]}] +set_property SLEW SLOW [get_ports {DDR_addr[14]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[13]}] +set_property DRIVE 12 [get_ports {DDR_addr[13]}] +set_property SLEW SLOW [get_ports {DDR_addr[13]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[12]}] +set_property DRIVE 12 [get_ports {DDR_addr[12]}] +set_property SLEW SLOW [get_ports {DDR_addr[12]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[11]}] +set_property DRIVE 12 [get_ports {DDR_addr[11]}] +set_property SLEW SLOW [get_ports {DDR_addr[11]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[10]}] +set_property DRIVE 12 [get_ports {DDR_addr[10]}] +set_property SLEW SLOW [get_ports {DDR_addr[10]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[9]}] +set_property DRIVE 12 [get_ports {DDR_addr[9]}] +set_property SLEW SLOW [get_ports {DDR_addr[9]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[8]}] +set_property DRIVE 12 [get_ports {DDR_addr[8]}] +set_property SLEW SLOW [get_ports {DDR_addr[8]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[7]}] +set_property DRIVE 12 [get_ports {DDR_addr[7]}] +set_property SLEW SLOW [get_ports {DDR_addr[7]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[6]}] +set_property DRIVE 12 [get_ports {DDR_addr[6]}] +set_property SLEW SLOW [get_ports {DDR_addr[6]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[5]}] +set_property DRIVE 12 [get_ports {DDR_addr[5]}] +set_property SLEW SLOW [get_ports {DDR_addr[5]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[4]}] +set_property DRIVE 12 [get_ports {DDR_addr[4]}] +set_property SLEW SLOW [get_ports {DDR_addr[4]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[3]}] +set_property DRIVE 12 [get_ports {DDR_addr[3]}] +set_property SLEW SLOW [get_ports {DDR_addr[3]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[2]}] +set_property DRIVE 12 [get_ports {DDR_addr[2]}] +set_property SLEW SLOW [get_ports {DDR_addr[2]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[1]}] +set_property DRIVE 12 [get_ports {DDR_addr[1]}] +set_property SLEW SLOW [get_ports {DDR_addr[1]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports {DDR_addr[0]}] +set_property DRIVE 12 [get_ports {DDR_addr[0]}] +set_property SLEW SLOW [get_ports {DDR_addr[0]}] +set_property DIRECTION INOUT [get_ports DDR_cas_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_cas_n] +set_property DRIVE 12 [get_ports DDR_cas_n] +set_property SLEW SLOW [get_ports DDR_cas_n] +set_property DIRECTION INOUT [get_ports DDR_ck_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_ck_n] +set_property DRIVE 12 [get_ports DDR_ck_n] +set_property SLEW SLOW [get_ports DDR_ck_n] +set_property DIRECTION INOUT [get_ports DDR_ck_p] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_ck_p] +set_property DRIVE 12 [get_ports DDR_ck_p] +set_property SLEW SLOW [get_ports DDR_ck_p] +set_property DIRECTION INOUT [get_ports DDR_cke] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_cke] +set_property DRIVE 12 [get_ports DDR_cke] +set_property SLEW SLOW [get_ports DDR_cke] +set_property DIRECTION INOUT [get_ports DDR_cs_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_cs_n] +set_property DRIVE 12 [get_ports DDR_cs_n] +set_property SLEW SLOW [get_ports DDR_cs_n] +set_property DIRECTION INOUT [get_ports DDR_odt] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_odt] +set_property DRIVE 12 [get_ports DDR_odt] +set_property SLEW SLOW [get_ports DDR_odt] +set_property DIRECTION INOUT [get_ports DDR_ras_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_ras_n] +set_property DRIVE 12 [get_ports DDR_ras_n] +set_property SLEW SLOW [get_ports DDR_ras_n] +set_property DIRECTION INOUT [get_ports DDR_reset_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_reset_n] +set_property DRIVE 12 [get_ports DDR_reset_n] +set_property SLEW SLOW [get_ports DDR_reset_n] +set_property DIRECTION INOUT [get_ports DDR_we_n] +set_property IOSTANDARD LVCMOS18 [get_ports DDR_we_n] +set_property DRIVE 12 [get_ports DDR_we_n] +set_property SLEW SLOW [get_ports DDR_we_n] +set_property PACKAGE_PIN N12 [get_ports csi_c_clk_n] +set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p] +set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}] +set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}] +set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}] +set_property PACKAGE_PIN M11 [get_ports {csi_d_n[0]}] +set_property PACKAGE_PIN P14 [get_ports {csi_d_n[1]}] +set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}] +set_property INTERNAL_VREF 0.6 [get_iobanks 34] +set_property PACKAGE_PIN R8 [get_ports hdmi_clk_n] +set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p] +set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}] +set_property PACKAGE_PIN P9 [get_ports {hdmi_data_n[0]}] +set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}] +set_property PACKAGE_PIN R10 [get_ports {hdmi_data_n[1]}] +set_property PACKAGE_PIN R11 [get_ports {hdmi_data_n[2]}] +set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}] +set_property PACKAGE_PIN K15 [get_ports {gpio_1_tri_io[0]}] +set_property PACKAGE_PIN J14 [get_ports {gpio_1_tri_io[1]}] +set_property PACKAGE_PIN H12 [get_ports {gpio_1_tri_io[2]}] +set_property PACKAGE_PIN N14 [get_ports {gpio_1_tri_io[3]}] +set_property PACKAGE_PIN R15 [get_ports {gpio_1_tri_io[4]}] +set_property PACKAGE_PIN L14 [get_ports {gpio_1_tri_io[5]}] +set_property PACKAGE_PIN L15 [get_ports {gpio_1_tri_io[6]}] +set_property PACKAGE_PIN J13 [get_ports {gpio_1_tri_io[7]}] +set_property PACKAGE_PIN H14 [get_ports {gpio_1_tri_io[8]}] +set_property PACKAGE_PIN J15 [get_ports {gpio_1_tri_io[9]}] +set_property PACKAGE_PIN M15 [get_ports {gpio_1_tri_io[10]}] +set_property PACKAGE_PIN R13 [get_ports {gpio_1_tri_io[11]}] +set_property PACKAGE_PIN L13 [get_ports {gpio_1_tri_io[12]}] +set_property PACKAGE_PIN G11 [get_ports {gpio_1_tri_io[13]}] +set_property PACKAGE_PIN H11 [get_ports {gpio_1_tri_io[14]}] +set_property PACKAGE_PIN R12 [get_ports {gpio_1_tri_io[15]}] +set_property PACKAGE_PIN M14 [get_ports {gpio_1_tri_io[16]}] +set_property PACKAGE_PIN P15 [get_ports {gpio_1_tri_io[17]}] +set_property PACKAGE_PIN H13 [get_ports {gpio_1_tri_io[18]}] +set_property PACKAGE_PIN J11 [get_ports {gpio_1_tri_io[19]}] +set_property PACKAGE_PIN K11 [get_ports {gpio_1_tri_io[20]}] +set_property PACKAGE_PIN K13 [get_ports {gpio_1_tri_io[21]}] +set_property PACKAGE_PIN L12 [get_ports {gpio_1_tri_io[22]}] +set_property PACKAGE_PIN G12 [get_ports {gpio_1_tri_io[23]}] +set_property PACKAGE_PIN N8 [get_ports PWM_R] +set_property PACKAGE_PIN N7 [get_ports PWM_L] +#revert back to original instance +current_instance -quiet diff --git a/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_ip_status_report.txt b/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_ip_status_report.txt new file mode 100644 index 0000000..9e80c08 --- /dev/null +++ b/zynqberrydemo3/prebuilt/hardware/te0726_7s/reports/zynqberrydemo3_ip_status_report.txt @@ -0,0 +1,152 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Tue Jun 13 10:05:17 2017 +| Host : W8-64-02 running 64-bit major release (build 9200) +| Command : report_ip_status +------------------------------------------------------------------------------------ + +IP Status Summary + +1. Project IP Status +-------------------- +Your project uses 29 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. + +More information on the Xilinx versioning policy is available at www.xilinx.com. + +Project IP Instances ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | +| | | | Log | | Version | | License | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_Video_IO_2_HDMI_TMDS_0_0 | Up-to-date | No changes required | Change | Video IO to HDMI | 1.0 | 1.0 (Rev. 26) | Included | xc7z007sclg225-1 | +| | | | Log not | TMDS Interface | (Rev. | | | | +| | | | available | v1.0 | 26) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_i2s_adi_0_0 | Up-to-date | No changes required | Change | AXI I2S Audio | 1.2 | 1.2 (Rev. 1) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_interconnect_0_0 | Up-to-date | No changes required | *(1) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_mem_intercon_0 | Up-to-date | No changes required | *(2) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_reg32_0_0 | Up-to-date | No changes required | Change | AXI Register Bank | 1.0 | 1.0 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | Log not | 16/16 v1.0 | (Rev. | | | | +| | | | available | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_vdma_0_0 | Up-to-date | No changes required | *(3) | AXI Video Direct | 6.3 | 6.3 | Included | xc7z007sclg225-1 | +| | | | | Memory Access | | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_vdma_0_1 | Up-to-date | No changes required | *(4) | AXI Video Direct | 6.3 | 6.3 | Included | xc7z007sclg225-1 | +| | | | | Memory Access | | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_0_0 | Up-to-date | No changes required | *(5) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_3_0 | Up-to-date | No changes required | *(6) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_4_0 | Up-to-date | No changes required | *(7) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_fb_conv_0_0 | Up-to-date | No changes required | Change | axis_fb_conv_v1.0 | 1.0 | 1.0 (Rev. 5) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 5) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_raw_demosaic_0_0 | Up-to-date | No changes required | Change | RAW Demosaic v1.0 | 1.0 | 1.0 (Rev. 20) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 20) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_raw_unpack_0_0 | Up-to-date | No changes required | Change | RAW10 Unpack v1.0 | 1.0 | 1.0 (Rev. 17) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 17) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_to_i2s_0_0 | Up-to-date | No changes required | Change | AXI4-Stream to I2S | 1.0 | 1.0 (Rev. 4) | Included | xc7z007sclg225-1 | +| | | | Log not | v1.0 | (Rev. | | | | +| | | | available | | 4) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_clk_wiz_1_0 | Up-to-date | No changes required | *(8) | Clocking Wizard | 5.4 | 5.4 | Included | xc7z007sclg225-1 | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_csi2_d_phy_rx_0_0 | Up-to-date | No changes required | Change | CSI-2 D-PHY RX | 1.0 | 1.0 (Rev. 35) | Included | xc7z007sclg225-1 | +| | | | Log not | v1_0 | (Rev. | | | | +| | | | available | | 35) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_csi_to_axis_0_0 | Up-to-date | No changes required | Change | CSI-2 to | 1.0 | 1.0 (Rev. 46) | Included | xc7z007sclg225-1 | +| | | | Log not | AXI4-Stream v1.0 | (Rev. | | | | +| | | | available | | 46) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_i2s_to_pwm_0_0 | Up-to-date | No changes required | Change | I2S to PWM v1.0 | 1.0 | 1.0 (Rev. 7) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 7) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_proc_sys_reset_0_0 | Up-to-date | No changes required | *(9) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z007sclg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_proc_sys_reset_1_0 | Up-to-date | No changes required | *(10) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z007sclg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_processing_system7_0_0 | Up-to-date | No changes required | *(11) | ZYNQ7 Processing | 5.5 | 5.5 (Rev. 5) | Included | xc7z007sclg225-1 | +| | | | | System | (Rev. | | | | +| | | | | | 5) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_processing_system7_0_axi_periph_0 | Up-to-date | No changes required | *(12) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_rst_processing_system7_0_50M_0 | Up-to-date | No changes required | *(13) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z007sclg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_v_axi4s_vid_out_0_0 | Up-to-date | No changes required | *(14) | AXI4-Stream to | 4.0 | 4.0 (Rev. 6) | Included | xc7z007sclg225-1 | +| | | | | Video Out | (Rev. | | | | +| | | | | | 6) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_v_tc_0_0 | Up-to-date | No changes required | *(15) | Video Timing | 6.1 | 6.1 (Rev. 10) | Included | xc7z007sclg225-1 | +| | | | | Controller | (Rev. | | | | +| | | | | | 10) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xadc_wiz_0_0 | Up-to-date | No changes required | *(16) | XADC Wizard | 3.3 | 3.3 (Rev. 3) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 3) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlconcat_0_0 | Up-to-date | No changes required | *(17) | Concat | 2.1 | 2.1 (Rev. 1) | Included | xc7z007sclg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlslice_0_0 | Up-to-date | No changes required | Change | Slice | 1.0 | 1.0 (Rev. 1) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlslice_1_0 | Up-to-date | No changes required | Change | Slice | 1.0 | 1.0 (Rev. 1) | Included | xc7z007sclg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +*(1) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(2) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(3) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt +*(4) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt +*(5) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(6) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(7) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(8) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/clk_wiz_v5_4/doc/clk_wiz_v5_4_changelog.txt +*(9) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(10) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(11) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/processing_system7_v5_5/doc/processing_system7_v5_5_changelog.txt +*(12) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(13) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt +*(14) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/v_axi4s_vid_out_v4_0/doc/v_axi4s_vid_out_v4_0_changelog.txt +*(15) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/v_tc_v6_1/doc/v_tc_v6_1_changelog.txt +*(16) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/xadc_wiz_v3_3/doc/xadc_wiz_v3_3_changelog.txt +*(17) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/xlconcat_v2_1/doc/xlconcat_v2_1_changelog.txt + + diff --git a/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_io_report.txt b/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_io_report.txt new file mode 100644 index 0000000..6030434 --- /dev/null +++ b/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_io_report.txt @@ -0,0 +1,267 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Wed Jun 14 17:17:24 2017 +| Host : W8-64-02 running 64-bit major release (build 9200) +| Command : report_io -force -file B:/Design/cores/2017.1/design/TE0726/zynqberrydemo3/vivado/zynqberrydemo3.runs/impl_1/zynqberrydemo3_io_report.txt -format text +| Design : zsys_wrapper +| Device : xc7z010 +| Speed File : -1 +| Package : clg225 +| Package Version : FINAL 2012-11-02 +| Package Pin Delay Version : VERS. 2.0 2012-11-02 +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 130 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A2 | DDR_dq[1] | | PS_DDR_DQ1_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A3 | DDR_dq[7] | | PS_DDR_DQ7_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A4 | DDR_dq[5] | | PS_DDR_DQ5_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| A5 | FIXED_IO_mio[1] | | PS_MIO1_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| A7 | FIXED_IO_mio[3] | | PS_MIO3_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A8 | FIXED_IO_mio[2] | | PS_MIO2_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A9 | FIXED_IO_mio[5] | | PS_MIO5_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A10 | FIXED_IO_mio[6] | | PS_MIO6_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| A11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| A12 | FIXED_IO_mio[30] | | PS_MIO52_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A13 | FIXED_IO_mio[26] | | PS_MIO38_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A14 | FIXED_IO_mio[23] | | PS_MIO35_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| A15 | FIXED_IO_mio[16] | | PS_MIO28_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B1 | DDR_dm[0] | | PS_DDR_DM0_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| B2 | DDR_dqs_n[0] | | PS_DDR_DQS_N0_502 | BIDIR | DIFF_SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| B3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| B4 | DDR_dq[4] | | PS_DDR_DQ4_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| B5 | FIXED_IO_mio[9] | | PS_MIO9_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B6 | FIXED_IO_mio[8] | | PS_MIO8_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B7 | FIXED_IO_mio[12] | | PS_MIO12_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| B9 | FIXED_IO_mio[14] | | PS_MIO14_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B10 | FIXED_IO_mio[11] | | PS_MIO11_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| B11 | FIXED_IO_ps_srstb | | PS_SRST_B_501 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| B12 | FIXED_IO_mio[28] | | PS_MIO48_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| B14 | FIXED_IO_mio[24] | | PS_MIO36_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| B15 | FIXED_IO_mio[18] | | PS_MIO30_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C1 | DDR_dq[3] | | PS_DDR_DQ3_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C2 | DDR_dqs_p[0] | | PS_DDR_DQS_P0_502 | BIDIR | DIFF_SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C3 | DDR_dq[6] | | PS_DDR_DQ6_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C4 | DDR_dq[2] | | PS_DDR_DQ2_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| C6 | FIXED_IO_mio[13] | | PS_MIO13_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| C7 | FIXED_IO_ps_clk | | PS_CLK_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| C8 | FIXED_IO_mio[4] | | PS_MIO4_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| C9 | FIXED_IO_ps_porb | | PS_POR_B_500 | BIDIR | LVCMOS33 | | 12 | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| C10 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| C11 | FIXED_IO_mio[21] | | PS_MIO33_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C12 | FIXED_IO_mio[19] | | PS_MIO31_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C13 | FIXED_IO_mio[31] | | PS_MIO53_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C14 | FIXED_IO_mio[25] | | PS_MIO37_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| C15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D1 | DDR_dq[9] | | PS_DDR_DQ9_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| D2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D3 | DDR_dm[1] | | PS_DDR_DM1_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| D4 | DDR_dq[0] | | PS_DDR_DQ0_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| D5 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | +| D6 | FIXED_IO_mio[10] | | PS_MIO10_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D7 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | +| D8 | FIXED_IO_mio[0] | | PS_MIO0_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D9 | FIXED_IO_mio[7] | | PS_MIO7_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D10 | FIXED_IO_mio[15] | | PS_MIO15_500 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | | | | NONE | +| D11 | FIXED_IO_mio[17] | | PS_MIO29_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| D13 | FIXED_IO_mio[29] | | PS_MIO49_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D14 | FIXED_IO_mio[27] | | PS_MIO39_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| D15 | FIXED_IO_mio[22] | | PS_MIO34_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| E1 | DDR_dq[8] | | PS_DDR_DQ8_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E2 | DDR_dq[10] | | PS_DDR_DQ10_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E3 | DDR_dq[11] | | PS_DDR_DQ11_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| E4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E6 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E8 | | | RSVDGND | GND | | | | | | | | | | | | | +| E9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| E10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| E11 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | +| E12 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | +| E13 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | +| E14 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | +| E15 | FIXED_IO_mio[20] | | PS_MIO32_501 | BIDIR | LVCMOS33 | | 8 | SLOW | | NONE | | FIXED | PULLUP | | | NONE | +| F1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| F2 | DDR_dqs_n[1] | | PS_DDR_DQS_N1_502 | BIDIR | DIFF_SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| F3 | DDR_dq[12] | | PS_DDR_DQ12_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| F4 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | +| F5 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | +| F6 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | 3.30 | | | | | | +| F7 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | +| F8 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | +| F9 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| F10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| F11 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | +| F12 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | +| F13 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | +| F14 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | +| F15 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | +| G1 | DDR_dq[13] | | PS_DDR_DQ13_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| G2 | DDR_dqs_p[1] | | PS_DDR_DQS_P1_502 | BIDIR | DIFF_SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| G3 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G4 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G6 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| G7 | Vp_Vn_v_p | Dedicated | VP_0 | INPUT | LVCMOS18* | 0 | | | | NONE | | UNFIXED | | | | NONE | +| G8 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | +| G9 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | +| G10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| G11 | gpio_1_tri_io[13] | High Range | IO_L1P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G12 | gpio_1_tri_io[23] | High Range | IO_L2P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| G13 | | | GND | GND | | | | | | | 0.0 | | | | | | +| G14 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | +| G15 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | +| H1 | DDR_dq[14] | | PS_DDR_DQ14_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H2 | DDR_dq[15] | | PS_DDR_DQ15_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H3 | FIXED_IO_ddr_vrp | | PS_DDR_VRP_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| H4 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | +| H5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| H6 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H7 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | +| H8 | Vp_Vn_v_n | Dedicated | VN_0 | INPUT | LVCMOS18* | 0 | | | | NONE | | UNFIXED | | | | NONE | +| H9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| H10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| H11 | gpio_1_tri_io[14] | High Range | IO_L6P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H12 | gpio_1_tri_io[2] | High Range | IO_L1N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H13 | gpio_1_tri_io[18] | High Range | IO_L2N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H14 | gpio_1_tri_io[8] | High Range | IO_L3N_T0_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| H15 | | High Range | VCCO_35 | VCCO | | 35 | | | | | any** | | | | | | +| J1 | DDR_addr[10] | | PS_DDR_A10_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| J3 | FIXED_IO_ddr_vrn | | PS_DDR_VRN_502 | BIDIR | SSTL135_T_DCI | | | FAST | DCI SPLIT | FP_VTT_50 | | FIXED | | | | SPLIT | +| J4 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | +| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| J7 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | +| J8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| J10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| J11 | gpio_1_tri_io[19] | High Range | IO_L6N_T0_VREF_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J12 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| J13 | gpio_1_tri_io[7] | High Range | IO_L5P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J14 | gpio_1_tri_io[1] | High Range | IO_L5N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| J15 | gpio_1_tri_io[9] | High Range | IO_L4P_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K1 | DDR_addr[14] | | PS_DDR_A14_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K2 | DDR_addr[13] | | PS_DDR_A13_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K3 | DDR_odt | | PS_DDR_ODT_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K5 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | +| K6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | +| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K8 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | 3.30 | | | | | | +| K9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | +| K10 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K11 | gpio_1_tri_io[20] | High Range | IO_L11P_T1_SRCC_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K12 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | +| K13 | gpio_1_tri_io[21] | High Range | IO_L10P_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| K14 | | | GND | GND | | | | | | | 0.0 | | | | | | +| K15 | gpio_1_tri_io[0] | High Range | IO_L4N_T0_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L2 | DDR_addr[11] | | PS_DDR_A11_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L3 | DDR_cke | | PS_DDR_CKE_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L4 | DDR_reset_n | | PS_DDR_DRST_B_502 | BIDIR | SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L6 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | +| L7 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | +| L8 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | +| L9 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | +| L10 | | | VCCINT | VCCINT | | | | | | | | | | | | | +| L11 | | | GND | GND | | | | | | | 0.0 | | | | | | +| L12 | gpio_1_tri_io[22] | High Range | IO_L12P_T1_MRCC_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L13 | gpio_1_tri_io[12] | High Range | IO_L10N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L14 | gpio_1_tri_io[5] | High Range | IO_L9P_T1_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| L15 | gpio_1_tri_io[6] | High Range | IO_L8P_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M1 | DDR_addr[2] | | PS_DDR_A2_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M2 | DDR_addr[12] | | PS_DDR_A12_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| M4 | DDR_addr[3] | | PS_DDR_A3_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M5 | DDR_addr[7] | | PS_DDR_A7_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M6 | DDR_ba[0] | | PS_DDR_BA0_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | +| M8 | | | GND | GND | | | | | | | 0.0 | | | | | | +| M9 | csi_d_lp_n[0] | High Range | IO_L19P_T3_34 | INPUT | HSUL_12 | 34 | | | | NONE | | FIXED | PULLDOWN | | Internal | NONE | +| M10 | csi_d_p[0] | High Range | IO_L21P_T3_DQS_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| M11 | csi_d_n[0] | High Range | IO_L21N_T3_DQS_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| M12 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | +| M13 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| M14 | gpio_1_tri_io[16] | High Range | IO_L9N_T1_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| M15 | gpio_1_tri_io[10] | High Range | IO_L8N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N1 | DDR_addr[1] | | PS_DDR_A1_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N2 | DDR_ck_n | | PS_DDR_CKN_502 | BIDIR | DIFF_SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| N3 | DDR_ck_p | | PS_DDR_CKP_502 | BIDIR | DIFF_SSTL135 | | | FAST | | FP_VTT_50 | | FIXED | | | | NONE | +| N4 | DDR_addr[9] | | PS_DDR_A9_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | +| N6 | DDR_ba[2] | | PS_DDR_BA2_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N7 | PWM_L | High Range | IO_L22P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N8 | PWM_R | High Range | IO_L22N_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N9 | csi_d_lp_p[0] | High Range | IO_L19N_T3_VREF_34 | INPUT | HSUL_12 | 34 | | | | NONE | | FIXED | PULLDOWN | | Internal | NONE | +| N10 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| N11 | csi_c_clk_p | High Range | IO_L13P_T2_MRCC_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| N12 | csi_c_clk_n | High Range | IO_L13N_T2_MRCC_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| N13 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | +| N14 | gpio_1_tri_io[3] | High Range | IO_L7N_T1_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| N15 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P1 | DDR_addr[0] | | PS_DDR_A0_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P2 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P3 | DDR_addr[4] | | PS_DDR_A4_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P4 | DDR_addr[5] | | PS_DDR_A5_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P5 | DDR_addr[6] | | PS_DDR_A6_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P6 | DDR_addr[8] | | PS_DDR_A8_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| P7 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| P8 | hdmi_data_p[0] | High Range | IO_L23P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P9 | hdmi_data_n[0] | High Range | IO_L23N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P10 | hdmi_data_p[1] | High Range | IO_L24P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P11 | hdmi_data_p[2] | High Range | IO_L16P_T2_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| P12 | | | GND | GND | | | | | | | 0.0 | | | | | | +| P13 | csi_d_p[1] | High Range | IO_L18P_T2_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| P14 | csi_d_n[1] | High Range | IO_L18N_T2_34 | INPUT | LVDS_25 | 34 | | | | NONE | | FIXED | | | | NONE | +| P15 | gpio_1_tri_io[17] | High Range | IO_L15P_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R1 | DDR_ba[1] | | PS_DDR_BA1_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R2 | DDR_cs_n | | PS_DDR_CS_B_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R3 | DDR_we_n | | PS_DDR_WE_B_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | +| R5 | DDR_cas_n | | PS_DDR_CAS_B_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R6 | DDR_ras_n | | PS_DDR_RAS_B_502 | BIDIR | SSTL135 | | | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R7 | hdmi_clk_p | High Range | IO_L20P_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R8 | hdmi_clk_n | High Range | IO_L20N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R9 | | | GND | GND | | | | | | | 0.0 | | | | | | +| R10 | hdmi_data_n[1] | High Range | IO_L24N_T3_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R11 | hdmi_data_n[2] | High Range | IO_L16N_T2_34 | OUTPUT | TMDS_33 | 34 | | | | FP_3.3_50 | | FIXED | | | | NONE | +| R12 | gpio_1_tri_io[15] | High Range | IO_L17P_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R13 | gpio_1_tri_io[11] | High Range | IO_L17N_T2_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | +| R14 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | +| R15 | gpio_1_tri_io[4] | High Range | IO_L15N_T2_DQS_34 | BIDIR | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | ++------------+-------------------+------------+-------------------------+-------------+--------------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+----------+------------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_io_report.xdc b/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_io_report.xdc new file mode 100644 index 0000000..bf8968b --- /dev/null +++ b/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_io_report.xdc @@ -0,0 +1,589 @@ +set_property PACKAGE_PIN C9 [get_ports FIXED_IO_ps_porb] +set_property PACKAGE_PIN K3 [get_ports DDR_odt] +set_property PACKAGE_PIN C7 [get_ports FIXED_IO_ps_clk] +set_property PACKAGE_PIN G2 [get_ports {DDR_dqs_p[1]}] +set_property PACKAGE_PIN A12 [get_ports {FIXED_IO_mio[30]}] +set_property PACKAGE_PIN A8 [get_ports {FIXED_IO_mio[2]}] +set_property PACKAGE_PIN B12 [get_ports {FIXED_IO_mio[28]}] +set_property PACKAGE_PIN D14 [get_ports {FIXED_IO_mio[27]}] +set_property PACKAGE_PIN A13 [get_ports {FIXED_IO_mio[26]}] +set_property PACKAGE_PIN C14 [get_ports {FIXED_IO_mio[25]}] +set_property PACKAGE_PIN B14 [get_ports {FIXED_IO_mio[24]}] +set_property PACKAGE_PIN A14 [get_ports {FIXED_IO_mio[23]}] +set_property PACKAGE_PIN D15 [get_ports {FIXED_IO_mio[22]}] +set_property PACKAGE_PIN C11 [get_ports {FIXED_IO_mio[21]}] +set_property PACKAGE_PIN E15 [get_ports {FIXED_IO_mio[20]}] +set_property PACKAGE_PIN A5 [get_ports {FIXED_IO_mio[1]}] +set_property PACKAGE_PIN B15 [get_ports {FIXED_IO_mio[18]}] +set_property PACKAGE_PIN D11 [get_ports {FIXED_IO_mio[17]}] +set_property PACKAGE_PIN A15 [get_ports {FIXED_IO_mio[16]}] +set_property PACKAGE_PIN D10 [get_ports {FIXED_IO_mio[15]}] +set_property PACKAGE_PIN B9 [get_ports {FIXED_IO_mio[14]}] +set_property PACKAGE_PIN C6 [get_ports {FIXED_IO_mio[13]}] +set_property PACKAGE_PIN B7 [get_ports {FIXED_IO_mio[12]}] +set_property PACKAGE_PIN B10 [get_ports {FIXED_IO_mio[11]}] +set_property PACKAGE_PIN D6 [get_ports {FIXED_IO_mio[10]}] +set_property PACKAGE_PIN D8 [get_ports {FIXED_IO_mio[0]}] +set_property PACKAGE_PIN B6 [get_ports {FIXED_IO_mio[8]}] +set_property PACKAGE_PIN D9 [get_ports {FIXED_IO_mio[7]}] +set_property PACKAGE_PIN A10 [get_ports {FIXED_IO_mio[6]}] +set_property PACKAGE_PIN A9 [get_ports {FIXED_IO_mio[5]}] +set_property PACKAGE_PIN C8 [get_ports {FIXED_IO_mio[4]}] +set_property PACKAGE_PIN A7 [get_ports {FIXED_IO_mio[3]}] +set_property PACKAGE_PIN C13 [get_ports {FIXED_IO_mio[31]}] +set_property PACKAGE_PIN D13 [get_ports {FIXED_IO_mio[29]}] +set_property PACKAGE_PIN C12 [get_ports {FIXED_IO_mio[19]}] +set_property PACKAGE_PIN H3 [get_ports FIXED_IO_ddr_vrp] +set_property PACKAGE_PIN R6 [get_ports DDR_ras_n] +set_property PACKAGE_PIN L4 [get_ports DDR_reset_n] +set_property PACKAGE_PIN R3 [get_ports DDR_we_n] +set_property PACKAGE_PIN J3 [get_ports FIXED_IO_ddr_vrn] +set_property PACKAGE_PIN B11 [get_ports FIXED_IO_ps_srstb] +set_property PACKAGE_PIN K1 [get_ports {DDR_addr[14]}] +set_property PACKAGE_PIN N1 [get_ports {DDR_addr[1]}] +set_property PACKAGE_PIN M1 [get_ports {DDR_addr[2]}] +set_property PACKAGE_PIN M4 [get_ports {DDR_addr[3]}] +set_property PACKAGE_PIN P3 [get_ports {DDR_addr[4]}] +set_property PACKAGE_PIN P4 [get_ports {DDR_addr[5]}] +set_property PACKAGE_PIN P5 [get_ports {DDR_addr[6]}] +set_property PACKAGE_PIN M5 [get_ports {DDR_addr[7]}] +set_property PACKAGE_PIN P6 [get_ports {DDR_addr[8]}] +set_property PACKAGE_PIN P1 [get_ports {DDR_addr[0]}] +set_property PACKAGE_PIN J1 [get_ports {DDR_addr[10]}] +set_property PACKAGE_PIN L2 [get_ports {DDR_addr[11]}] +set_property PACKAGE_PIN K2 [get_ports {DDR_addr[13]}] +set_property PACKAGE_PIN M2 [get_ports {DDR_addr[12]}] +set_property PACKAGE_PIN N4 [get_ports {DDR_addr[9]}] +set_property PACKAGE_PIN M6 [get_ports {DDR_ba[0]}] +set_property PACKAGE_PIN R1 [get_ports {DDR_ba[1]}] +set_property PACKAGE_PIN N6 [get_ports {DDR_ba[2]}] +set_property PACKAGE_PIN N3 [get_ports DDR_ck_p] +set_property PACKAGE_PIN R5 [get_ports DDR_cas_n] +set_property PACKAGE_PIN N2 [get_ports DDR_ck_n] +set_property PACKAGE_PIN B5 [get_ports {FIXED_IO_mio[9]}] +set_property PACKAGE_PIN L3 [get_ports DDR_cke] +set_property PACKAGE_PIN R2 [get_ports DDR_cs_n] +set_property PACKAGE_PIN B1 [get_ports {DDR_dm[0]}] +set_property PACKAGE_PIN D3 [get_ports {DDR_dm[1]}] +set_property PACKAGE_PIN H2 [get_ports {DDR_dq[15]}] +set_property PACKAGE_PIN A2 [get_ports {DDR_dq[1]}] +set_property PACKAGE_PIN C4 [get_ports {DDR_dq[2]}] +set_property PACKAGE_PIN C1 [get_ports {DDR_dq[3]}] +set_property PACKAGE_PIN B4 [get_ports {DDR_dq[4]}] +set_property PACKAGE_PIN A4 [get_ports {DDR_dq[5]}] +set_property PACKAGE_PIN C3 [get_ports {DDR_dq[6]}] +set_property PACKAGE_PIN A3 [get_ports {DDR_dq[7]}] +set_property PACKAGE_PIN E1 [get_ports {DDR_dq[8]}] +set_property PACKAGE_PIN D4 [get_ports {DDR_dq[0]}] +set_property PACKAGE_PIN E2 [get_ports {DDR_dq[10]}] +set_property PACKAGE_PIN E3 [get_ports {DDR_dq[11]}] +set_property PACKAGE_PIN F3 [get_ports {DDR_dq[12]}] +set_property PACKAGE_PIN G1 [get_ports {DDR_dq[13]}] +set_property PACKAGE_PIN H1 [get_ports {DDR_dq[14]}] +set_property PACKAGE_PIN D1 [get_ports {DDR_dq[9]}] +set_property PACKAGE_PIN B2 [get_ports {DDR_dqs_n[0]}] +set_property PACKAGE_PIN F2 [get_ports {DDR_dqs_n[1]}] +set_property PACKAGE_PIN C2 [get_ports {DDR_dqs_p[0]}] +set_property PACKAGE_PIN N12 [get_ports csi_c_clk_n] +set_property PACKAGE_PIN N11 [get_ports csi_c_clk_p] +set_property PACKAGE_PIN M9 [get_ports {csi_d_lp_n[0]}] +set_property PACKAGE_PIN N9 [get_ports {csi_d_lp_p[0]}] +set_property PACKAGE_PIN M10 [get_ports {csi_d_p[0]}] +set_property PACKAGE_PIN M11 [get_ports {csi_d_n[0]}] +set_property PACKAGE_PIN P14 [get_ports {csi_d_n[1]}] +set_property PACKAGE_PIN P13 [get_ports {csi_d_p[1]}] +set_property INTERNAL_VREF 0.6 [get_iobanks 34] +set_property PACKAGE_PIN R8 [get_ports hdmi_clk_n] +set_property PACKAGE_PIN R7 [get_ports hdmi_clk_p] +set_property PACKAGE_PIN P8 [get_ports {hdmi_data_p[0]}] +set_property PACKAGE_PIN P9 [get_ports {hdmi_data_n[0]}] +set_property PACKAGE_PIN P10 [get_ports {hdmi_data_p[1]}] +set_property PACKAGE_PIN R10 [get_ports {hdmi_data_n[1]}] +set_property PACKAGE_PIN R11 [get_ports {hdmi_data_n[2]}] +set_property PACKAGE_PIN P11 [get_ports {hdmi_data_p[2]}] +set_property PACKAGE_PIN K15 [get_ports {gpio_1_tri_io[0]}] +set_property PACKAGE_PIN J14 [get_ports {gpio_1_tri_io[1]}] +set_property PACKAGE_PIN H12 [get_ports {gpio_1_tri_io[2]}] +set_property PACKAGE_PIN N14 [get_ports {gpio_1_tri_io[3]}] +set_property PACKAGE_PIN R15 [get_ports {gpio_1_tri_io[4]}] +set_property PACKAGE_PIN L14 [get_ports {gpio_1_tri_io[5]}] +set_property PACKAGE_PIN L15 [get_ports {gpio_1_tri_io[6]}] +set_property PACKAGE_PIN J13 [get_ports {gpio_1_tri_io[7]}] +set_property PACKAGE_PIN H14 [get_ports {gpio_1_tri_io[8]}] +set_property PACKAGE_PIN J15 [get_ports {gpio_1_tri_io[9]}] +set_property PACKAGE_PIN M15 [get_ports {gpio_1_tri_io[10]}] +set_property PACKAGE_PIN R13 [get_ports {gpio_1_tri_io[11]}] +set_property PACKAGE_PIN L13 [get_ports {gpio_1_tri_io[12]}] +set_property PACKAGE_PIN G11 [get_ports {gpio_1_tri_io[13]}] +set_property PACKAGE_PIN H11 [get_ports {gpio_1_tri_io[14]}] +set_property PACKAGE_PIN R12 [get_ports {gpio_1_tri_io[15]}] +set_property PACKAGE_PIN M14 [get_ports {gpio_1_tri_io[16]}] +set_property PACKAGE_PIN P15 [get_ports {gpio_1_tri_io[17]}] +set_property PACKAGE_PIN H13 [get_ports {gpio_1_tri_io[18]}] +set_property PACKAGE_PIN J11 [get_ports {gpio_1_tri_io[19]}] +set_property PACKAGE_PIN K11 [get_ports {gpio_1_tri_io[20]}] +set_property PACKAGE_PIN K13 [get_ports {gpio_1_tri_io[21]}] +set_property PACKAGE_PIN L12 [get_ports {gpio_1_tri_io[22]}] +set_property PACKAGE_PIN G12 [get_ports {gpio_1_tri_io[23]}] +set_property PACKAGE_PIN N8 [get_ports PWM_R] +set_property PACKAGE_PIN N7 [get_ports PWM_L] +set_property DIRECTION IN [get_ports {csi_d_lp_p[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_p[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_p[0]}] +set_property DIRECTION IN [get_ports {csi_d_n[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_n[1]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_n[1]}] +set_property DIRECTION IN [get_ports {csi_d_n[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_n[0]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_n[0]}] +set_property DIRECTION IN [get_ports {csi_d_p[1]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[1]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_p[1]}] +set_property DIRECTION IN [get_ports {csi_d_p[0]}] +set_property IOSTANDARD LVDS_25 [get_ports {csi_d_p[0]}] +set_property DIFF_TERM FALSE [get_ports {csi_d_p[0]}] +set_property DIRECTION IN [get_ports {csi_d_lp_n[0]}] +set_property IOSTANDARD HSUL_12 [get_ports {csi_d_lp_n[0]}] +set_property PULLDOWN true [get_ports {csi_d_lp_n[0]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[2]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[1]}] +set_property DIRECTION OUT [get_ports {hdmi_data_n[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_n[0]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[2]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[2]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[1]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[1]}] +set_property DIRECTION OUT [get_ports {hdmi_data_p[0]}] +set_property IOSTANDARD TMDS_33 [get_ports {hdmi_data_p[0]}] +set_property DIRECTION OUT [get_ports hdmi_clk_p] +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_p] +set_property DIRECTION OUT [get_ports hdmi_clk_n] +set_property IOSTANDARD TMDS_33 [get_ports hdmi_clk_n] +set_property DIRECTION IN [get_ports csi_c_clk_p] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_p] +set_property DIFF_TERM FALSE [get_ports csi_c_clk_p] +set_property DIRECTION IN [get_ports csi_c_clk_n] +set_property IOSTANDARD LVDS_25 [get_ports csi_c_clk_n] +set_property DIFF_TERM FALSE [get_ports csi_c_clk_n] +set_property DIRECTION IN [get_ports Vp_Vn_v_p] +set_property DIRECTION IN [get_ports Vp_Vn_v_n] +set_property DIRECTION OUT [get_ports PWM_R] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_R] +set_property DRIVE 12 [get_ports PWM_R] +set_property SLEW SLOW [get_ports PWM_R] +set_property DIRECTION OUT [get_ports PWM_L] +set_property IOSTANDARD LVCMOS33 [get_ports PWM_L] +set_property DRIVE 12 [get_ports PWM_L] +set_property SLEW SLOW [get_ports PWM_L] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[23]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[23]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[23]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[23]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[22]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[22]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[22]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[21]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[21]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[21]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[21]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[20]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[20]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[20]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[19]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[19]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[19]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[19]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[18]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[18]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[18]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[17]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[17]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[17]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[17]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[16]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[16]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[16]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[15]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[15]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[15]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[14]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[14]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[14]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[13]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[13]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[13]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[12]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[12]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[12]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[11]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[11]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[11]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[10]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[10]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[10]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[9]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[9]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[9]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[8]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[8]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[8]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[7]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[7]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[7]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[6]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[6]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[6]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[5]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[5]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[5]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[4]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[4]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[4]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[3]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[3]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[3]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[2]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[2]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[2]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[1]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[1]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[1]}] +set_property DIRECTION INOUT [get_ports {gpio_1_tri_io[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {gpio_1_tri_io[0]}] +set_property DRIVE 12 [get_ports {gpio_1_tri_io[0]}] +set_property SLEW SLOW [get_ports {gpio_1_tri_io[0]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[31]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[31]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[31]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[31]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[31]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[30]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[30]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[30]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[30]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[30]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[29]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[29]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[29]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[29]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[29]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[28]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[28]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[28]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[28]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[28]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[27]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[27]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[27]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[27]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[27]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[26]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[26]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[26]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[26]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[26]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[25]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[25]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[25]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[25]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[25]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[24]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[24]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[24]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[24]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[24]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[23]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[23]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[23]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[23]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[23]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[22]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[22]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[22]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[22]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[22]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[21]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[21]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[21]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[21]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[21]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[20]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[20]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[20]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[20]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[20]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[19]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[19]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[19]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[19]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[19]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[18]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[18]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[18]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[18]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[18]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[17]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[17]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[17]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[17]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[17]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[16]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[16]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[16]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[16]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[16]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[15]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[15]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[15]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[15]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[14]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[14]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[14]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[14]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[13]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[13]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[13]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[13]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[12]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[12]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[12]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[12]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[11]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[11]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[11]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[11]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[10]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[10]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[10]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[10]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[9]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[9]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[9]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[9]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[9]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[8]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[8]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[8]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[8]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[7]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[7]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[7]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[6]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[6]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[6]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[5]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[5]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[5]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[4]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[4]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[4]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[3]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[3]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[3]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[2]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[2]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[2]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[1]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[1]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[1]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[1]}] +set_property DIRECTION INOUT [get_ports {FIXED_IO_mio[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {FIXED_IO_mio[0]}] +set_property DRIVE 8 [get_ports {FIXED_IO_mio[0]}] +set_property SLEW SLOW [get_ports {FIXED_IO_mio[0]}] +set_property PULLUP true [get_ports {FIXED_IO_mio[0]}] +set_property DIRECTION INOUT [get_ports FIXED_IO_ddr_vrn] +set_property IOSTANDARD SSTL135_T_DCI [get_ports FIXED_IO_ddr_vrn] +set_property SLEW FAST [get_ports FIXED_IO_ddr_vrn] +set_property DIRECTION INOUT [get_ports FIXED_IO_ddr_vrp] +set_property IOSTANDARD SSTL135_T_DCI [get_ports FIXED_IO_ddr_vrp] +set_property SLEW FAST [get_ports FIXED_IO_ddr_vrp] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_clk] +set_property IOSTANDARD LVCMOS33 [get_ports FIXED_IO_ps_clk] +set_property DRIVE 12 [get_ports FIXED_IO_ps_clk] +set_property SLEW FAST [get_ports FIXED_IO_ps_clk] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_porb] +set_property IOSTANDARD LVCMOS33 [get_ports FIXED_IO_ps_porb] +set_property DRIVE 12 [get_ports FIXED_IO_ps_porb] +set_property SLEW FAST [get_ports FIXED_IO_ps_porb] +set_property DIRECTION INOUT [get_ports FIXED_IO_ps_srstb] +set_property IOSTANDARD LVCMOS33 [get_ports FIXED_IO_ps_srstb] +set_property DRIVE 12 [get_ports FIXED_IO_ps_srstb] +set_property SLEW FAST [get_ports FIXED_IO_ps_srstb] +set_property DIRECTION INOUT [get_ports {DDR_dqs_p[1]}] +set_property IOSTANDARD DIFF_SSTL135_T_DCI [get_ports {DDR_dqs_p[1]}] +set_property SLEW FAST [get_ports {DDR_dqs_p[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_p[0]}] +set_property IOSTANDARD DIFF_SSTL135_T_DCI [get_ports {DDR_dqs_p[0]}] +set_property SLEW FAST [get_ports {DDR_dqs_p[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_n[1]}] +set_property IOSTANDARD DIFF_SSTL135_T_DCI [get_ports {DDR_dqs_n[1]}] +set_property SLEW FAST [get_ports {DDR_dqs_n[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dqs_n[0]}] +set_property IOSTANDARD DIFF_SSTL135_T_DCI [get_ports {DDR_dqs_n[0]}] +set_property SLEW FAST [get_ports {DDR_dqs_n[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[15]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[15]}] +set_property SLEW FAST [get_ports {DDR_dq[15]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[14]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[14]}] +set_property SLEW FAST [get_ports {DDR_dq[14]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[13]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[13]}] +set_property SLEW FAST [get_ports {DDR_dq[13]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[12]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[12]}] +set_property SLEW FAST [get_ports {DDR_dq[12]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[11]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[11]}] +set_property SLEW FAST [get_ports {DDR_dq[11]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[10]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[10]}] +set_property SLEW FAST [get_ports {DDR_dq[10]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[9]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[9]}] +set_property SLEW FAST [get_ports {DDR_dq[9]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[8]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[8]}] +set_property SLEW FAST [get_ports {DDR_dq[8]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[7]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[7]}] +set_property SLEW FAST [get_ports {DDR_dq[7]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[6]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[6]}] +set_property SLEW FAST [get_ports {DDR_dq[6]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[5]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[5]}] +set_property SLEW FAST [get_ports {DDR_dq[5]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[4]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[4]}] +set_property SLEW FAST [get_ports {DDR_dq[4]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[3]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[3]}] +set_property SLEW FAST [get_ports {DDR_dq[3]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[2]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[2]}] +set_property SLEW FAST [get_ports {DDR_dq[2]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[1]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[1]}] +set_property SLEW FAST [get_ports {DDR_dq[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dq[0]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dq[0]}] +set_property SLEW FAST [get_ports {DDR_dq[0]}] +set_property DIRECTION INOUT [get_ports {DDR_dm[1]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dm[1]}] +set_property SLEW FAST [get_ports {DDR_dm[1]}] +set_property DIRECTION INOUT [get_ports {DDR_dm[0]}] +set_property IOSTANDARD SSTL135_T_DCI [get_ports {DDR_dm[0]}] +set_property SLEW FAST [get_ports {DDR_dm[0]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[2]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_ba[2]}] +set_property SLEW SLOW [get_ports {DDR_ba[2]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[1]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_ba[1]}] +set_property SLEW SLOW [get_ports {DDR_ba[1]}] +set_property DIRECTION INOUT [get_ports {DDR_ba[0]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_ba[0]}] +set_property SLEW SLOW [get_ports {DDR_ba[0]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[14]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[14]}] +set_property SLEW SLOW [get_ports {DDR_addr[14]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[13]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[13]}] +set_property SLEW SLOW [get_ports {DDR_addr[13]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[12]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[12]}] +set_property SLEW SLOW [get_ports {DDR_addr[12]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[11]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[11]}] +set_property SLEW SLOW [get_ports {DDR_addr[11]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[10]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[10]}] +set_property SLEW SLOW [get_ports {DDR_addr[10]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[9]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[9]}] +set_property SLEW SLOW [get_ports {DDR_addr[9]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[8]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[8]}] +set_property SLEW SLOW [get_ports {DDR_addr[8]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[7]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[7]}] +set_property SLEW SLOW [get_ports {DDR_addr[7]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[6]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[6]}] +set_property SLEW SLOW [get_ports {DDR_addr[6]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[5]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[5]}] +set_property SLEW SLOW [get_ports {DDR_addr[5]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[4]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[4]}] +set_property SLEW SLOW [get_ports {DDR_addr[4]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[3]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[3]}] +set_property SLEW SLOW [get_ports {DDR_addr[3]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[2]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[2]}] +set_property SLEW SLOW [get_ports {DDR_addr[2]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[1]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[1]}] +set_property SLEW SLOW [get_ports {DDR_addr[1]}] +set_property DIRECTION INOUT [get_ports {DDR_addr[0]}] +set_property IOSTANDARD SSTL135 [get_ports {DDR_addr[0]}] +set_property SLEW SLOW [get_ports {DDR_addr[0]}] +set_property DIRECTION INOUT [get_ports DDR_cas_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_cas_n] +set_property SLEW SLOW [get_ports DDR_cas_n] +set_property DIRECTION INOUT [get_ports DDR_ck_n] +set_property IOSTANDARD DIFF_SSTL135 [get_ports DDR_ck_n] +set_property SLEW FAST [get_ports DDR_ck_n] +set_property DIRECTION INOUT [get_ports DDR_ck_p] +set_property IOSTANDARD DIFF_SSTL135 [get_ports DDR_ck_p] +set_property SLEW FAST [get_ports DDR_ck_p] +set_property DIRECTION INOUT [get_ports DDR_cke] +set_property IOSTANDARD SSTL135 [get_ports DDR_cke] +set_property SLEW SLOW [get_ports DDR_cke] +set_property DIRECTION INOUT [get_ports DDR_cs_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_cs_n] +set_property SLEW SLOW [get_ports DDR_cs_n] +set_property DIRECTION INOUT [get_ports DDR_odt] +set_property IOSTANDARD SSTL135 [get_ports DDR_odt] +set_property SLEW SLOW [get_ports DDR_odt] +set_property DIRECTION INOUT [get_ports DDR_ras_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_ras_n] +set_property SLEW SLOW [get_ports DDR_ras_n] +set_property DIRECTION INOUT [get_ports DDR_reset_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_reset_n] +set_property SLEW FAST [get_ports DDR_reset_n] +set_property DIRECTION INOUT [get_ports DDR_we_n] +set_property IOSTANDARD SSTL135 [get_ports DDR_we_n] +set_property SLEW SLOW [get_ports DDR_we_n] +#revert back to original instance +current_instance -quiet diff --git a/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_ip_status_report.txt b/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_ip_status_report.txt new file mode 100644 index 0000000..70a6a22 --- /dev/null +++ b/zynqberrydemo3/prebuilt/hardware/te0726_m/reports/zynqberrydemo3_ip_status_report.txt @@ -0,0 +1,152 @@ +Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2017.1 (win64) Build 1846317 Fri Apr 14 18:55:03 MDT 2017 +| Date : Wed Jun 14 17:17:24 2017 +| Host : W8-64-02 running 64-bit major release (build 9200) +| Command : report_ip_status +------------------------------------------------------------------------------------ + +IP Status Summary + +1. Project IP Status +-------------------- +Your project uses 29 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. + +More information on the Xilinx versioning policy is available at www.xilinx.com. + +Project IP Instances ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | +| | | | Log | | Version | | License | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_Video_IO_2_HDMI_TMDS_0_0 | Up-to-date | No changes required | Change | Video IO to HDMI | 1.0 | 1.0 (Rev. 26) | Included | xc7z010clg225-1 | +| | | | Log not | TMDS Interface | (Rev. | | | | +| | | | available | v1.0 | 26) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_i2s_adi_0_0 | Up-to-date | No changes required | Change | AXI I2S Audio | 1.2 | 1.2 (Rev. 1) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_interconnect_0_0 | Up-to-date | No changes required | *(1) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_mem_intercon_0 | Up-to-date | No changes required | *(2) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_reg32_0_0 | Up-to-date | No changes required | Change | AXI Register Bank | 1.0 | 1.0 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | Log not | 16/16 v1.0 | (Rev. | | | | +| | | | available | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_vdma_0_0 | Up-to-date | No changes required | *(3) | AXI Video Direct | 6.3 | 6.3 | Included | xc7z010clg225-1 | +| | | | | Memory Access | | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axi_vdma_0_1 | Up-to-date | No changes required | *(4) | AXI Video Direct | 6.3 | 6.3 | Included | xc7z010clg225-1 | +| | | | | Memory Access | | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_0_0 | Up-to-date | No changes required | *(5) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_3_0 | Up-to-date | No changes required | *(6) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_data_fifo_4_0 | Up-to-date | No changes required | *(7) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | FIFO | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_fb_conv_0_0 | Up-to-date | No changes required | Change | axis_fb_conv_v1.0 | 1.0 | 1.0 (Rev. 5) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 5) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_raw_demosaic_0_0 | Up-to-date | No changes required | Change | RAW Demosaic v1.0 | 1.0 | 1.0 (Rev. 20) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 20) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_raw_unpack_0_0 | Up-to-date | No changes required | Change | RAW10 Unpack v1.0 | 1.0 | 1.0 (Rev. 17) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 17) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_axis_to_i2s_0_0 | Up-to-date | No changes required | Change | AXI4-Stream to I2S | 1.0 | 1.0 (Rev. 4) | Included | xc7z010clg225-1 | +| | | | Log not | v1.0 | (Rev. | | | | +| | | | available | | 4) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_clk_wiz_1_0 | Up-to-date | No changes required | *(8) | Clocking Wizard | 5.4 | 5.4 | Included | xc7z010clg225-1 | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_csi2_d_phy_rx_0_0 | Up-to-date | No changes required | Change | CSI-2 D-PHY RX | 1.0 | 1.0 (Rev. 35) | Included | xc7z010clg225-1 | +| | | | Log not | v1_0 | (Rev. | | | | +| | | | available | | 35) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_csi_to_axis_0_0 | Up-to-date | No changes required | Change | CSI-2 to | 1.0 | 1.0 (Rev. 46) | Included | xc7z010clg225-1 | +| | | | Log not | AXI4-Stream v1.0 | (Rev. | | | | +| | | | available | | 46) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_i2s_to_pwm_0_0 | Up-to-date | No changes required | Change | I2S to PWM v1.0 | 1.0 | 1.0 (Rev. 7) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 7) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_proc_sys_reset_0_0 | Up-to-date | No changes required | *(9) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z010clg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_proc_sys_reset_1_0 | Up-to-date | No changes required | *(10) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z010clg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_processing_system7_0_0 | Up-to-date | No changes required | *(11) | ZYNQ7 Processing | 5.5 | 5.5 (Rev. 5) | Included | xc7z010clg225-1 | +| | | | | System | (Rev. | | | | +| | | | | | 5) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_processing_system7_0_axi_periph_0 | Up-to-date | No changes required | *(12) | AXI Interconnect | 2.1 | 2.1 (Rev. 13) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 13) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_rst_processing_system7_0_50M_0 | Up-to-date | No changes required | *(13) | Processor System | 5.0 | 5.0 (Rev. 11) | Included | xc7z010clg225-1 | +| | | | | Reset | (Rev. | | | | +| | | | | | 11) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_v_axi4s_vid_out_0_0 | Up-to-date | No changes required | *(14) | AXI4-Stream to | 4.0 | 4.0 (Rev. 6) | Included | xc7z010clg225-1 | +| | | | | Video Out | (Rev. | | | | +| | | | | | 6) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_v_tc_0_0 | Up-to-date | No changes required | *(15) | Video Timing | 6.1 | 6.1 (Rev. 10) | Included | xc7z010clg225-1 | +| | | | | Controller | (Rev. | | | | +| | | | | | 10) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xadc_wiz_0_0 | Up-to-date | No changes required | *(16) | XADC Wizard | 3.3 | 3.3 (Rev. 3) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 3) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlconcat_0_0 | Up-to-date | No changes required | *(17) | Concat | 2.1 | 2.1 (Rev. 1) | Included | xc7z010clg225-1 | +| | | | | | (Rev. | | | | +| | | | | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlslice_0_0 | Up-to-date | No changes required | Change | Slice | 1.0 | 1.0 (Rev. 1) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +| zsys_xlslice_1_0 | Up-to-date | No changes required | Change | Slice | 1.0 | 1.0 (Rev. 1) | Included | xc7z010clg225-1 | +| | | | Log not | | (Rev. | | | | +| | | | available | | 1) | | | | ++----------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+ +*(1) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(2) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_interconnect_v2_1/doc/axi_interconnect_v2_1_changelog.txt +*(3) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt +*(4) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axi_vdma_v6_3/doc/axi_vdma_v6_3_changelog.txt +*(5) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(6) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(7) c:/Xilinx/Vivado/2017.1/data/ip/xilinx/axis_data_fifo_v1_1/doc/axis_data_fifo_v1_1_changelog.txt +*(8) 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zP&Qa<&@7Q^P!={dXdmw=9mSqq>WJ>WIXY8=r#Gh>WM{<<@E+v$;&t$4q1jo!7fH_g zoN!t{A>|vo|8Li`h{o5E`S!WHQ1)-8Q ze)6~cW5kp1YrD(E^ZCHtSN=w;_#5I~ZsYM4Z2h;phluC?&2q`p<@XXBkFUz>?|@If zWSQFV-z0{)R@v7PUgf@$pZ?qGChr0f=8`bEcELFy`Kg#sWApEJh?Gn2EAZ!B`rm<* zc=ES_%YQ?>65&z?i6{TY$tvP)U4yWfyYDQTIDBhf>FxtzrYL3 literal 0 HcmV?d00001 diff --git a/zynqberrydemo3/scripts/reinitialise_all.tcl b/zynqberrydemo3/scripts/reinitialise_all.tcl new file mode 100644 index 0000000..0fafdc3 --- /dev/null +++ b/zynqberrydemo3/scripts/reinitialise_all.tcl @@ -0,0 +1,123 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/08 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/02/02 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- + +proc reinitialise {} { + TE::UTILS::te_msg TE_INIT-59 INFO "Reinitialise Scripts \n \ + Current directory: [pwd] \n \ + At moment, this attributes can't be refreshed: \n \ + TE::VIVADO_AVAILABLE : $TE::VIVADO_AVAILABLE \n \ + TE::LABTOOL_AVAILABLE : $TE::LABTOOL_AVAILABLE \n \ + TE::SDK_AVAILABLE : $TE::SDK_AVAILABLE \n \ + TE::SDSOC_AVAILABLE : $TE::SDSOC_AVAILABLE \n \ + Xilinx SDSOC Scripts \n \ + ------" + set cur [pwd] + cd .. + # ----------------------------------------------------------------------------------------------------------------------------------------- + # load scripts + # ----------------------------------------------------------------------------------------------------------------------------------------- + source ./scripts/script_settings.tcl + source ./scripts/script_environment.tcl + source ./scripts/script_vivado.tcl + source ./scripts/script_te_utils.tcl + source ./scripts/script_designs.tcl + source ./scripts/script_external.tcl + source ./scripts/script_usrcommands.tcl + source ./scripts/script_sdsoc.tcl + #sources from other programs: + # source ./scripts/main.tcl + # source ./scripts/hsi.tcl + #currently SDSOC Runs only with batch start + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # initial variables + # ----------------------------------------------------------------------------------------------------------------------------------------- + if {[catch {TE::INIT::basic_inits} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-60 ERROR "Script (TE::INIT::basic_inits) failed: $result."; return -code error} + #------ + set projectname "NA" + set BOARD "" + if {[file exists ${TE::BASEFOLDER}/design_basic_settings.cmd]} { + set fp [open "${TE::BASEFOLDER}/design_basic_settings.cmd" r] + set file_data [read $fp] + close $fp + set tmp [split $file_data "\n"] + foreach t $tmp { + if {[string match "@set PARTNUMBER=*" $t] } { + set splittstring [split $t "="] + set BOARD [lindex $splittstring [expr [llength $splittstring]-1]] + } + if {[string match "@set ZIP_PATH=*" $t] } { + set splittstring [split $t "="] + set TE::ZIP_PATH [lindex $splittstring [expr [llength $splittstring]-1]] + TE::UTILS::te_msg TE_INIT-61 STATUS "Restore ZIP path from design_basic_settings.cmd \n \ + TE::ZIP_PATH : ${TE::ZIP_PATH} \n \ + ------" + } + if {[string match "@set XILINXGIT_DEVICETREE=*" $t] } { + set splittstring [split $t "="] + set TE::XILINXGIT_DEVICETREE [lindex $splittstring [expr [llength $splittstring]-1]] + TE::UTILS::te_msg TE_INIT-62 STATUS "Restore XILINXGIT_DEVICETREE path from design_basic_settings.cmd \n \ + TE::XILINXGIT_DEVICETREE : ${TE::XILINXGIT_DEVICETREE} \n \ + ------" + } + if {[string match "@set XILINXGIT_UBOOT=*" $t] } { + set splittstring [split $t "="] + set TE::XILINXGIT_UBOOT [lindex $splittstring [expr [llength $splittstring]-1]] + TE::UTILS::te_msg TE_INIT-63 STATUS "Restore XILINXGIT_UBOOT path from design_basic_settings.cmd \n \ + TE::XILINXGIT_UBOOT : ${TE::XILINXGIT_UBOOT} \n \ + ------" + } + if {[string match "@set XILINXGIT_LINUX=*" $t] } { + set splittstring [split $t "="] + set TE::XILINXGIT_LINUX [lindex $splittstring [expr [llength $splittstring]-1]] + TE::UTILS::te_msg TE_INIT-64 STATUS "Restore XILINXGIT_LINUX path from design_basic_settings.cmd \n \ + TE::XILINXGIT_LINUX : ${TE::XILINXGIT_LINUX} \n \ + ------" + } + } + } + if {[catch {set projectname [get_projects]} result]} { + TE::UTILS::te_msg TE_INIT-65 STATUS "Reinitialise Vivado Labtools with board part variable from design_basic_settings.cmd." + if {[catch {TE::INIT::init_board [TE::BDEF::find_id $BOARD] 0} result]} {set cur [pwd]; TE::UTILS::te_msg TE_INIT-66 ERROR "Script (TE::INIT::init_board /[TE::BDEF::find_id/]) failed: $result."; return -code error} + cd $TE::VLABPROJ_PATH + } else { + TE::UTILS::te_msg TE_INIT-66 STATUS "Reinitialise Vivado" + set pfolder [file tail [pwd]] + cd $cur + if {$pfolder != $projectname} {set cur [pwd]; TE::UTILS::te_msg TE_INIT-67 ERROR "Inconsistent project name, get project [get_projects], expected $pfolder from project folder"; return -code error} + cd .. + #initial vivado variables + if {[catch {TE::VIV::restore_scriptprops} result]} {set cur [pwd]; TE::UTILS::te_msg TE_INIT-68 ERROR "Script (TE::VIV::restore_scriptprops) failed: $result."; return -code error} + cd $TE::VPROJ_PATH + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished initial variables + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- +} +# ----------------------------------------------------------------------------------------------------------------------------------------- +# run reinitialisation +# ----------------------------------------------------------------------------------------------------------------------------------------- +reinitialise +# ----------------------------------------------------------------------------------------------------------------------------------------- +# finished run reinitialisation +# ----------------------------------------------------------------------------------------------------------------------------------------- \ No newline at end of file diff --git a/zynqberrydemo3/scripts/script_designs.tcl b/zynqberrydemo3/scripts/script_designs.tcl new file mode 100644 index 0000000..46ae5e0 --- /dev/null +++ b/zynqberrydemo3/scripts/script_designs.tcl @@ -0,0 +1,402 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/04 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2010/03/06 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval ::TE { + namespace eval INIT { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--basic_inits: initial some variables and list + proc basic_inits {} { + if {[catch {TE::INIT::print_version} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-71 ERROR "Script (TE::INIT::print_version) failed: $result."; return -code error} + if {[catch {TE::INIT::print_environment_settings} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-72 ERROR "Script (TE::INIT::print_environment_settings) failed: $result."; return -code error} + if {[catch {TE::INIT::init_pathvar} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-73 ERROR "Script (TE::INIT::init_pathvar) failed: $result."; return -code error} + if {[catch {TE::INIT::init_boardlist} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status;create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-74 ERROR "Script (TE::INIT::init_boardlist) failed: $result."; return -code error} + if {[catch {TE::INIT::init_app_list} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-75 ERROR "Script (TE::INIT::init_app_list) failed: $result."; return -code error} + if {[catch {TE::INIT::init_zip_ignore_list} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-76 ERROR "Script (TE::INIT::init_zip_ignore_list) failed: $result."; return -code error} + if {[catch {TE::INIT::init_mod_list} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-77 ERROR "Script (TE::INIT::init_mod_list) failed: $result."; return -code error} + if {[catch {TE::INIT::init_usr_tcl} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-78 ERROR "Script (TE::INIT::init_usr_tcl) failed: $result."; return -code error} + if {[file exists ${TE::SET_PATH}/development_settings.tcl]} { + TE::UTILS::te_msg TE_INIT-79 INFO "Source ${TE::SET_PATH}/development_settings.tcl." + if {[catch {source ${TE::SET_PATH}/development_settings.tcl} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-80 ERROR "Script (source development_settings.tcl) failed: $result."; return -code error} + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # cmd functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--run_te_procedure: run tcl Function from cmd file + proc run_te_procedure {TCL_PROCEDURE BOARD} { + TE::UTILS::te_msg TE_INIT-81 INFO "Run TE::INIT::run_te_procedure $TCL_PROCEDURE $BOARD" + #-- + if {[catch {TE::INIT::remove_status_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-82 ERROR "Script (TE::INIT::remove_status_files) failed: $result."; return -code error} + #-- + #Attention not all Procedures can start directly from shell + if {[catch {TE::INIT::basic_inits} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-83 ERROR "Script (TE::INIT::basic_inits) failed: $result."; return -code error} + if {[catch {init_board [TE::BDEF::find_id $BOARD] 0} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-84 ERROR "Script (TE::INIT::init_board /[TE::BDEF::find_id/]) failed: $result."; return -code error} + if {[catch {eval $TCL_PROCEDURE} result]} {abort_status "Error Run TE-TCLProcedure from batch file..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-85 ERROR "Script (${TCL_PROCEDURE}) failed: $result."; return -code error} + } + #-------------------------------- + #--clear_project_all:todo:use run_te_procedure + proc clear_project_all {} { + TE::UTILS::te_msg TE_INIT-86 INFO "Run TE::INIT::clear_project_all " + if {[catch {TE::UTILS::clean_all_generated_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-87 ERROR "Script (TE::UTILS::clean_all_generated_files) failed: $result."; return -code error} + } + #-------------------------------- + #--run_labtools:todo:use run_te_procedure + proc run_labtools {BOARD} { + TE::UTILS::te_msg TE_INIT-88 INFO "Run TE::INIT::run_labtools $BOARD" + #-- + if {[catch {TE::INIT::remove_status_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-89 ERROR "Script (TE::INIT::remove_status_files) failed: $result."; return -code error} + #-- + if {[catch {TE::INIT::basic_inits} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-90 ERROR "Script (TE::INIT::basic_inits) failed: $result."; return -code error} + if {[catch {init_board [TE::BDEF::find_id $BOARD] 0} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-91 ERROR "Script (TE::INIT::init_board /[TE::BDEF::find_id/]) failed: $result."; return -code error} + if {[catch {TE::INIT::generate_labtools_project GUI} result]} {abort_status "Error Generate LabTools Project..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-92 ERROR "Script (TE::INIT::generate_labtools_project) failed: $result."; return -code error} + } + #-------------------------------- + #--program_zynq_bin: + proc program_zynq_bin {USE_BASEFOLDER BOARD SWAPP LABTOOLS} { + TE::UTILS::te_msg TE_INIT-93 INFO "Run TE::INIT::program_zynq_bin $USE_BASEFOLDER $BOARD $SWAPP $LABTOOLS" + #-- + if {[catch {TE::INIT::remove_status_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-94 ERROR "Script (TE::INIT::remove_status_files) failed: $result."; return -code error} + #-- + set return_filename "" + if {[catch {TE::INIT::basic_inits} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-95 ERROR "Script (TE::INIT::basic_inits) failed: $result."; return -code error} + if {$LABTOOLS} { + if {[catch {TE::INIT::generate_labtools_project} result]} {abort_status "Error Generate LabTools Project..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-96 ERROR "Script (TE::INIT::generate_labtools_project) failed: $result."; return -code error} + if {$USE_BASEFOLDER} { + if {[catch {set return_filename [TE::pr_program_flash_binfile -used_board $BOARD -swapp $SWAPP -used_basefolder_binfile]} result]} {abort_status "Error external Zynq Flash configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-97 ERROR "Script (TE::pr_program_flash_binfile) failed: $result."; return -code error} + } else { + if {[catch {set return_filename [TE::pr_program_flash_binfile -used_board $BOARD -swapp $SWAPP]} result]} {abort_status "Error external Zynq Flash configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-98 ERROR "Script (TE::pr_program_flash_binfile) failed: $result."; return -code error} + } + } else { + #dummi project need for jtag reboot memory + set curpath [pwd] + if {[catch {TE::INIT::generate_dummi_project} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-169 ERROR "Script (TE::INIT::generate_dummi_project) failed: $result."; return -code error} + if {$USE_BASEFOLDER} { + if {[catch {set return_filename [TE::pr_program_flash_binfile -used_board $BOARD -swapp $SWAPP -used_basefolder_binfile]} result]} {abort_status "Error external Zynq Flash configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-99 ERROR "Script (TE::pr_program_flash_binfile) failed: $result."; return -code error} + } else { + if {[catch {set return_filename [TE::pr_program_flash_binfile -used_board $BOARD -swapp $SWAPP]} result]} {abort_status "Error external Zynq Flash configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-100 ERROR "Script (TE::pr_program_flash_binfile) failed: $result."; return -code error} + } + if {[catch {TE::INIT::delete_dummi_project $curpath} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-101 ERROR "Script (TE::INIT::delete_dummi_project) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_INIT-102 INFO "Programming Flash without Error (Programming File: ${return_filename}) \n \ + ------" + } + #-------------------------------- + #--program_fpga_mcs: + proc program_fpga_mcs {USE_BASEFOLDER BOARD SWAPP LABTOOLS} { + TE::UTILS::te_msg TE_INIT-103 INFO "Run TE::INIT::program_fpga_mcs $USE_BASEFOLDER $BOARD $SWAPP $LABTOOLS" + #-- + if {[catch {TE::INIT::remove_status_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-104 ERROR "Script (TE::INIT::remove_status_files) failed: $result."; return -code error} + #-- + set return_filename "" + if {[catch {TE::INIT::basic_inits} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-105 ERROR "Script (TE::INIT::basic_inits) failed: $result."; return -code error} + if {$LABTOOLS} { + if {[catch {TE::INIT::generate_labtools_project} result]} {abort_status "Error Generate LabTools Project..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-106 ERROR "Script (TE::INIT::generate_labtools_project) failed: $result."; return -code error} + if {$USE_BASEFOLDER} { + if {[catch {set return_filename [TE::pr_program_flash_mcsfile -used_board $BOARD -swapp $SWAPP -used_basefolder_mcsfile]} result]} {abort_status "Error external Zynq Flash configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-107 ERROR "Script (TE::pr_program_flash_mcsfile) failed: $result."; return -code error} + } else { + if {[catch {set return_filename [TE::pr_program_flash_mcsfile -used_board $BOARD -swapp $SWAPP]} result]} {abort_status "Error external Zynq Flash configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-108 ERROR "Script (TE::pr_program_flash_mcsfile) failed: $result."; return -code error} + } + } else { + #dummi project need for jtag reboot memory + set curpath [pwd] + if {[catch {TE::INIT::generate_dummi_project} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-109 ERROR "Script (TE::INIT::generate_dummi_project) failed: $result."; return -code error} + if {$USE_BASEFOLDER} { + if {[catch {set return_filename [TE::pr_program_flash_mcsfile -used_board $BOARD -swapp $SWAPP -used_basefolder_mcsfile]} result]} {abort_status "Error external Zynq Flash configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-110 ERROR "Script (TE::pr_program_flash_mcsfile) failed: $result."; return -code error} + } else { + if {[catch {set return_filename [TE::pr_program_flash_mcsfile -used_board $BOARD -swapp $SWAPP]} result]} {abort_status "Error external Zynq Flash configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-111 ERROR "Script (TE::pr_program_flash_mcsfile) failed: $result."; return -code error} + } + if {[catch {TE::INIT::delete_dummi_project $curpath} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-112 ERROR "Script (TE::INIT::delete_dummi_project) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_INIT-113 INFO "Programming Flash without Error (Programming File: ${return_filename}) \n \ + ------" + } + #-------------------------------- + #--program_fpga_bit: + proc program_fpga_bit {USE_BASEFOLDER BOARD SWAPP LABTOOLS} { + TE::UTILS::te_msg TE_INIT-114 INFO "Run TE::INIT::program_fpga_bit $USE_BASEFOLDER $BOARD $SWAPP $LABTOOLS" + #-- + if {[catch {TE::INIT::remove_status_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-115 ERROR "Script (TE::INIT::remove_status_files) failed: $result."; return -code error} + #-- + set return_filename "" + if {[catch {TE::INIT::basic_inits} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-116 ERROR "Script (TE::INIT::basic_inits) failed: $result."; return -code error} + if {$LABTOOLS} { + if {[catch {TE::INIT::generate_labtools_project} result]} {abort_status "Error Generate LabTools Project..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-117 ERROR "Script (TE::INIT::generate_labtools_project) failed: $result."; return -code error} + if {$USE_BASEFOLDER} { + if {[catch {set return_filename [TE::pr_program_jtag_bitfile -used_board $BOARD -swapp $SWAPP -used_basefolder_bitfile]} result]} {abort_status "Error external Bitfile configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-118 ERROR "Script (TE::pr_program_jtag_bitfile) failed: $result."; return -code error} + } else { + if {[catch {set return_filename [TE::pr_program_jtag_bitfile -used_board $BOARD -swapp $SWAPP]} result]} {abort_status "Error external Bitfile configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-119 ERROR "Script (TE::pr_program_jtag_bitfile) failed: $result."; return -code error} + } + } else { + #dummi project need for jtag reboot memory + set curpath [pwd] + if {[catch {TE::INIT::generate_dummi_project} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-120 ERROR "Script (TE::INIT::generate_dummi_project) failed: $result."; return -code error} + if {$USE_BASEFOLDER} { + if {[catch {set return_filename [TE::pr_program_jtag_bitfile -used_board $BOARD -swapp $SWAPP -used_basefolder_bitfile]} result]} {abort_status "Error external Bitfile configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-121 ERROR "Script (TE::pr_program_jtag_bitfile) failed: $result."; return -code error} + } else { + if {[catch {set return_filename [TE::pr_program_jtag_bitfile -used_board $BOARD -swapp $SWAPP]} result]} {abort_status "Error external Bitfile configuration..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-122 ERROR "Script (TE::pr_program_jtag_bitfile) failed: $result."; return -code error} + } + if {[catch {TE::INIT::delete_dummi_project $curpath} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-123 ERROR "Script (TE::INIT::delete_dummi_project) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_INIT-124 INFO "Programming FPGA without Error (Programming File: ${return_filename}) \n \ + ------" + } + #-------------------------------- + #--run_sdk: + proc run_sdk {BOARD} { + TE::UTILS::te_msg TE_INIT-125 INFO "Run TE::INIT::run_sdk $BOARD" + #-- + if {[catch {TE::INIT::remove_status_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-126 ERROR "Script (TE::INIT::remove_status_files) failed: $result."; return -code error} + #-- + if {[catch {TE::INIT::basic_inits} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-127 ERROR "Script (TE::INIT::basic_inits) failed: $result."; return -code error} + if {[catch {TE::sw_run_sdk -prebuilt_hdf [TE::BDEF::find_id $BOARD]} result]} {abort_status "Error external SDK starting..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-128 ERROR "Script (TE::sw_run_sdk) failed: $result."; return -code error} + } + #-------------------------------- + #--run_project: VIVADO project + proc run_project {BOARD RUN GUI CLEAN} { + TE::UTILS::te_msg TE_INIT-129 INFO "Run TE::INIT::run_project $BOARD $RUN $GUI $CLEAN" + #-- + if {[catch {TE::INIT::remove_status_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-130 ERROR "Script (TE::INIT::remove_status_files) failed: $result."; return -code error} + #-- + if {[catch {TE::INIT::basic_inits} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-131 ERROR "Script (TE::INIT::basic_inits) failed: $result."; return -code error} + + switch $CLEAN { + 0 {} + 1 { + if {[catch {TE::UTILS::clean_vivado_project} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-132 ERROR "Script (TE::UTILS::clean_vivado_project) failed: $result."; return -code error} + } + 2 { + if {[catch {TE::UTILS::clean_vivado_project} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-133 ERROR "Script (TE::UTILS::clean_vivado_project) failed: $result."; return -code error} + if {[catch {TE::UTILS::clean_workspace_hsi} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-134 ERROR "Script (TE::UTILS::clean_workspace_hsi) failed: $result."; return -code error} + } + 3 { + if {[catch {TE::UTILS::clean_all_generated_files} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-135 ERROR "Script (TE::UTILS::clean_all_generated_files) failed: $result."; return -code error} + } + 4 { + if {[catch {TE::UTILS::clean_all_generated_files;TE::UTILS::clean_prebuilt_all} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-136 ERROR "Script (TE::UTILS::clean_all_generated_files , TE::UTILS::clean_prebuilt_all) failed: $result."; return -code error} + } + default {abort_status "Error Initialisation..."; create_allboardfiles_status; return -code error "Error: Design clean option $CLEAN not available, use [show_help]";} + } + if {$RUN > 0 } { + if {[catch {init_board [TE::BDEF::find_id $BOARD] 0} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-137 ERROR "Script (TE::INIT::init_board /[TE::BDEF::find_id/]) failed: $result."; return -code error} + } + switch $RUN { + -1 {TE::UTILS::te_msg TE_INIT-138 INFO " Clear only Mode selected..."} + 0 {start_existing_project $GUI } + 1 {generate_single_project $GUI } + 2 {generate_single_project_all $GUI } + 3 {generate_board_file_project_all $GUI } + default {abort_status "Error Initialisation..."; create_allboardfiles_status; return -code error "Error: Design run option $OPT not available, use [show_help]";} + } + TE::UTILS::te_msg TE_INIT-139 INFO "Run project finished without Error. \n \ + ------" + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished cmd functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--generate_dummi_project: for external programming without labtools and sdk only + proc generate_dummi_project {} { + file mkdir $TE::VPROJ_PATH/tmp + cd $TE::VPROJ_PATH/tmp + TE::UTILS::te_msg TE_INIT-140 STATUS "Create temporary vivado project in: [pwd]" + ::create_project -force tmp $TE::VPROJ_PATH/tmp + } + #-------------------------------- + #--delete_dummi_project: for external programming without labtools and sdk only + proc delete_dummi_project {oldpath} { + ::close_project + TE::UTILS::te_msg TE_INIT-141 STATUS "Delete temporary vivado project in: [pwd]" + cd $oldpath + if {[catch {file delete -force -- $TE::VPROJ_PATH/tmp} result ]} { + # somtimes is locked from other process + # puts "Info:(TE) Can't delete temporary folder." + } + } + #-------------------------------- + #--start_existing_project: + proc start_existing_project {GUI} { + if { [file exists $TE::VPROJ_PATH] } { + cd $TE::VPROJ_PATH + if { [file exists ${TE::VPROJ_NAME}.xpr] } { + TE::UTILS::te_msg TE_INIT-142 STATUS "Open existing project (File: ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.xpr)." + if {[catch {TE::VIV::open_project} result]} { TE::UTILS::te_msg TE_INIT-143 ERROR "Script (TE::VIV::open_project) failed: $result."; return -code error} + if {$GUI >= 1} {start_gui} + } else { + return -code error "Error: $TE::VPROJ_NAME.xpr not found in [pwd]"; + } + } else { + return -code error "Error: ${TE::VPROJ_PATH}/$TE::VPROJ_NAME.xpr not found"; + } + #--------------------------------------------- + } + #-------------------------------- + #--generate_single_project: + proc generate_single_project {GUI } { + if { [file exists $TE::VPROJ_PATH] } { + cd $TE::VPROJ_PATH + if { [file exists *.xpr] } { + return -code error "Error: Project folder not empty, clear [pwd]"; + } + } else { + TE::UTILS::te_msg TE_INIT-144 STATUS "Generate new project (Path: ${TE::VPROJ_PATH})." + file mkdir $TE::VPROJ_PATH + cd $TE::VPROJ_PATH + if {[catch {TE::VIV::create_project} result]} { TE::UTILS::te_msg TE_INIT-145 ERROR "Script (TE::VIV::create_project) failed: $result."; return -code error} + if {$GUI == 1} { start_gui } + if {[catch {TE::VIV::import_design} result]} { TE::UTILS::te_msg TE_INIT-146 ERROR "Script (TE::VIV::import_design) failed: $result."; return -code error} + if {$GUI == 2} { start_gui } + } + } + #-------------------------------- + #--generate_single_project_all: + proc generate_single_project_all {GUI} { + if {$GUI == 1} { generate_single_project 1 } else {generate_single_project 0 } + #-------------------------------------------------------- + run_current_project_all + #-------------------------------------------------------- + if {$GUI == 2} { start_gui} + } + #-------------------------------- + #--generate_board_file_project_all: + proc generate_board_file_project_all {GUI} { + + + foreach sublist $TE::BDEF::BOARD_DEFINITION { + set rundesign true + set id [lindex $sublist 0] + if {$id ne "ID" } { + if {[llength $TE::DESIGNRUNS] > 0} { + if {[lsearch -exact $TE::DESIGNRUNS $id] == -1} { + TE::UTILS::te_msg TE_INIT-147 STATUS "Skip ID: $id" + set rundesign false + } + } + if {$rundesign == true} { + TE::UTILS::te_msg TE_INIT-148 STATUS "Run project id $id (Path: [pwd]) \n \ + ------" + if {[catch {TE::UTILS::clean_vivado_project} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-149 ERROR "Script (TE::UTILS::clean_vivado_project) failed: $result."; return -code error} + if {[catch {TE::UTILS::clean_workspace_hsi} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-150 ERROR "Script (TE::UTILS::clean_workspace_hsi) failed: $result."; return -code error} + if {[catch {init_board $id 0} result]} {abort_status "Error Initialisation..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-151 ERROR "Script (TE::init_board) failed: $result."; return -code error} + if {[catch {generate_single_project_all 0} result]} {abort_status "Error generate projects..."; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-152 ERROR "Script (TE::generate_single_project_all) failed: $result."; return -code error} + + TE::VIV::close_project + } + } + } + create_allboardfiles_status + } + #-------------------------------- + #--run_current_project_all: + proc run_current_project_all {} { + # if {[catch {TE::VIV::build_design ${TE::GEN_HW_BIT} ${TE::GEN_HW_MCS} ${TE::GEN_HW_RPT}} result]} {TE::VIV::report_summary;set message "Error:(TE) Script (TE::VIV::build_design) failed: $result."; abort_status $emessage; puts $emessage; return -code error} + set hw_options [list] + if {!${TE::GEN_HW_BIT}} {lappend hw_options "-disable_bitgen"; TE::UTILS::te_msg TE_INIT-153 WARNING "Auto-generation of Bit-file is disabled."} + if {!${TE::GEN_HW_RPT}} {lappend hw_options "-disable_reports"; TE::UTILS::te_msg TE_INIT-154 WARNING "Auto-generation of Report-file is disabled."} + if {!${TE::GEN_HW_HDF}} {lappend hw_options "-disable_hdf"; TE::UTILS::te_msg TE_INIT-155 WARNING "Auto-generation of HDF-file is disabled."} + if {!${TE::GEN_HW_MCS}} {lappend hw_options "-disable_mcsgen"; TE::UTILS::te_msg TE_INIT-156 WARNING "Auto-generation of MCS-file is disabled."} + if {[catch {eval TE::hw_build_design ${hw_options}} result]} {TE::VIV::report_summary;set emessage "Error: Script (TE::hw_build_design) failed: $result."; abort_status $emessage; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-157 ERROR "$emessage" ; return -code error} + #---------------------------------------------------------- + set sw_options [list] + if {!${TE::GEN_SW_HSI}} {lappend sw_options "-no_hsi"; TE::UTILS::te_msg TE_INIT-158 WARNING "Auto-generation of ELF-files is disabled."} + if {!${TE::GEN_SW_BIF}} {lappend sw_options "-no_bif"; TE::UTILS::te_msg TE_INIT-159 WARNING "Auto-generation of BIF-files is disabled."} + if {!${TE::GEN_SW_BIN}} {lappend sw_options "-no_bin"; TE::UTILS::te_msg TE_INIT-160 WARNING "Auto-generation of BIN-files is disabled."} + if {!${TE::GEN_SW_BITMCS}} {lappend sw_options "-no_bitmcs"; TE::UTILS::te_msg TE_INIT-161 WARNING "Auto-generation of BIT-files and MCS-files is disabled."} + if {${TE::GEN_SW_USEPREBULTHDF}} {lappend sw_options "-prebuilt_hdf_only"; lappend sw_options "$TE::SHORTDIR"; TE::UTILS::te_msg TE_INIT-162 WARNING "Prebuilt HDF is used."} + if {${TE::GEN_SW_FORCEBOOTGEN}} {lappend sw_options "-force_bin"; TE::UTILS::te_msg TE_INIT-163 WARNING "Force Boot.bin is used."} + lappend sw_options "-clear" + if {[catch {eval TE::sw_run_hsi ${sw_options}} result]} { set emessage "Error: Script (TE::sw_run_hsi) failed: $result."; abort_status $emessage; create_allboardfiles_status; TE::UTILS::te_msg TE_INIT-164 ERROR "$emessage" ; return -code error} + abort_status "Ok" + } + #-------------------------------- + #--generate_labtools_project: + proc generate_labtools_project { {gui ""} } { + if { [file exists $TE::VLABPROJ_PATH] } { + cd $TE::VLABPROJ_PATH + if { [file exists ${TE::VPROJ_NAME}.lpr] } { + if {[catch {TE::VLAB::open_project} result]} { TE::UTILS::te_msg TE_INIT-165 ERROR "Script (TE::VLAB::open_project) failed: $result."; return -code error} + } else { + if {[catch {TE::VLAB::create_project} result]} { TE::UTILS::te_msg TE_INIT-166 ERROR "Script (TE::VLAB::create_project) failed: $result."; return -code error} + } + } else { + TE::UTILS::te_msg TE_INIT-167 STATUS "Generate new project (Path: $TE::VLABPROJ_PATH)" + file mkdir $TE::VLABPROJ_PATH + cd $TE::VLABPROJ_PATH + if {[catch {TE::VLAB::create_project} result]} { TE::UTILS::te_msg TE_INIT-168 ERROR "Script (TE::VLAB::create_project) failed: $result."; return -code error} + } + if {$gui ne ""} { + start_gui + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished project design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # status files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--remove_status_files: + proc remove_status_files {} { + if { [file exists ${TE::LOG_PATH}/allboardparts.txt] } { + file delete -force ${TE::LOG_PATH}/allboardparts.txt + } + if { [file exists ${TE::LOG_PATH}/status.txt] } { + file delete -force ${TE::LOG_PATH}/status.txt + } + } + #-------------------------------- + #--create_allboardfiles_status: + proc create_allboardfiles_status {} { + set report_file ${TE::LOG_PATH}/allboardparts.txt + set fp_w [open ${report_file} "w"] + puts $fp_w "it's generate only for powershell polling..." + close $fp_w + } + #-------------------------------- + #--abort_status: + proc abort_status {message} { + set report_file ${TE::LOG_PATH}/status.txt + + if { ![file exists ${report_file}]} { + set fp_w [open ${report_file} "w"] + puts $fp_w "Run ${TE::BOARDPART} with Status $message" + close $fp_w + } else { + set fp_a [open ${report_file} "a"] + puts $fp_a "Run ${TE::BOARDPART} with Status $message" + close $fp_a + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished status files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "INFO:(TE) Load Designs script finished" +} + + diff --git a/zynqberrydemo3/scripts/script_environment.tcl b/zynqberrydemo3/scripts/script_environment.tcl new file mode 100644 index 0000000..c81803b --- /dev/null +++ b/zynqberrydemo3/scripts/script_environment.tcl @@ -0,0 +1,46 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/03 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/02/02 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval ::TE { + namespace eval ENV { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # initial vivado lib paths + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--set_path_boarddef: + proc set_path_boarddef {} { + TE::UTILS::te_msg TE_INIT-69 INFO "Set Board Definition path: $TE::BOARDDEF_PATH" + set_param board.repoPaths $TE::BOARDDEF_PATH + } + #-------------------------------- + #--set_path_boarddef: + proc set_path_ip {} { + TE::UTILS::te_msg TE_INIT-70 INFO "Set IP path : $TE::IP_PATH" + set_property IP_REPO_PATHS $TE::IP_PATH [current_fileset] + ::update_ip_catalog + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished vivado lib paths + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + + } + puts "INFO:(TE) Load environment script finished" +} + + diff --git a/zynqberrydemo3/scripts/script_external.tcl b/zynqberrydemo3/scripts/script_external.tcl new file mode 100644 index 0000000..7e17185 --- /dev/null +++ b/zynqberrydemo3/scripts/script_external.tcl @@ -0,0 +1,786 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/11 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/05/13 $ +# -------------------------------------------------------------------- +# -- 2017/05/12 bugfix missing bracket +# -- 2017/05/18 add pmuf to zynqmp bif +# -- 2017/06/13 add pmuf hsi/sdk support +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval EXT { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # *elf generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--run_sdk: + proc run_sdk {} { + set cur_path [pwd] + cd $TE::WORKSPACE_SDK_PATH + set tmplist [list] + if {[file exists ${TE::XILINXGIT_DEVICETREE}]} { + TE::UTILS::te_msg TE_SW-0 STATUS "Include Xilinx Device Tree git clone." + lappend tmplist "-lp" $TE::LIB_PATH + lappend tmplist "-lp" ${TE::XILINXGIT_DEVICETREE} + } else { + TE::UTILS::te_msg TE_SW-1 WARNING "Xilinx Device Tree git clone path not found (${TE::XILINXGIT_DEVICETREE})." + lappend tmplist "-lp" $TE::LIB_PATH + } + set command exec + lappend command xsdk + lappend command -workspace ${TE::WORKSPACE_SDK_PATH} + set hdffilename "" + [catch {set hdffilename [glob -join -dir ${TE::WORKSPACE_SDK_PATH}/ *.hdf]}] + if {[file exists ${TE::WORKSPACE_SDK_PATH}/${TE::PR_TOPLEVELNAME}.hdf]} { + lappend command -hwspec ${TE::WORKSPACE_SDK_PATH}/${TE::PR_TOPLEVELNAME}.hdf + } elseif {[file exists ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf]} { + lappend command -hwspec ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + } else { + lappend command -hwspec ${hdffilename} + } + # lappend command -hwspec ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + # lappend command -bit ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.bit + lappend command {*}$tmplist + # lappend command --vivrun + TE::UTILS::te_msg TE_SW-2 INFO "Start SKD: \n \ + Run \"$command\" in $TE::WORKSPACE_SDK_PATH \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-0 INFO "Command results from SDK \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } + #-------------------------------- + #--run_hsi: + proc run_hsi {} { + # list 0 for table header + if { [llength $TE::SW_APPLIST] > 1} { + set cur_path [pwd] + cd $TE::WORKSPACE_HSI_PATH + set tmp_libpath [list] + lappend tmp_libpath $TE::LIB_PATH + if {[file exists ${TE::XILINXGIT_DEVICETREE}]} { + TE::UTILS::te_msg TE_SW-3 STATUS "Include Xilinx Device Tree git clone." + lappend tmp_libpath ${TE::XILINXGIT_DEVICETREE} + } else { + TE::UTILS::te_msg TE_SW-4 WARNING "Xilinx Device Tree git clone path not found (${TE::XILINXGIT_DEVICETREE})." + } + set tmp_sw_liblist [list] + lappend tmp_sw_liblist $tmp_libpath + set tmp_sw_applist [list] + lappend tmp_sw_applist $TE::SW_APPLIST + # + set command exec + lappend command hsi + lappend command -source ${TE::SCRIPT_PATH}/script_hsi.tcl + lappend command -tclargs + lappend command "--sw_list ${tmp_sw_applist} --lib $tmp_sw_liblist --vivrun" + # lappend command --vivrun + TE::UTILS::te_msg TE_SW-5 INFO "Start HSI: \n \ + Run \"$command\" in $TE::WORKSPACE_HSI_PATH \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-1 INFO "Command results from HSI \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + TE::UTILS::copy_sw_files + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished *elf generation + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # *bit/*mcs generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--generate_app_bit_mcs: + proc generate_app_bit_mcs {{fname ""}} { + #microblaze + set int_shortdir ${TE::SHORTDIR} + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + } + #run only if *.mmi exists + if {[file exists ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi]} { + # read processor from mmi + set fp [open "${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi" r] + set file_data [read $fp] + close $fp + set tmp [split $file_data "\n"] + foreach t $tmp { + if {[string match *InstPath=* $t] } { + set splittstring [split $t "="] + set next false + set hitval "NA" + foreach part $splittstring { + if {$next} { + set hitval $part + break + } + if {[string match *InstPath* $part] } { + set next true + } + } + set hitval [string map {">" ""} $hitval] + set hitval [string map {"\"" ""} $hitval] + if { $hitval eq "NA"} { + TE::UTILS::te_msg TE_SW-6 ERROR "Processor not found in ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi." + return -code error "Processor not found in ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi."; + } + } + } + #--------------- + foreach sw_applist_line ${TE::SW_APPLIST} { + #generate modified mcs or bit only if app_list.csv->steps=0(generate all), add file to mcs use "FIRM" + set app_name [lindex $sw_applist_line 1] + if {[lindex $sw_applist_line 2] eq "0"} { + #read app name + #delete old one + if {[file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/${app_name}.bit]} { + file delete -force ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/${app_name}.bit + } + #make folder if not exists + file mkdir ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + # + #todo:hier noch in default suche? + TE::UTILS::te_msg TE_SW-7 STATUS "Generate ${app_name}.bit with app: ${app_name}." + set command exec + lappend command updatemem + lappend command -force + lappend command -meminfo ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi + lappend command -data ${TE::PREBUILT_SW_PATH}/${int_shortdir}/${app_name}.elf + lappend command -bit ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.bit + lappend command -proc $hitval + lappend command -out ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/${app_name}.bit + TE::UTILS::te_msg TE_SW-8 INFO "Start Update Memory: \n \ + Run \"$command\" in ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-2 INFO "Command results from Update Memory \"$command\": \n \ + $result \n \ + ------" + } + #write mcs + if {[lindex $sw_applist_line 2] eq "0" || [lindex $sw_applist_line 2] eq "FIRM"} { + if {$TE::CFGMEM_MEMSIZE_MB ne "NA"} { + #todo generate relativ path from absolute paths + set rel_bitfile "../prebuilt/hardware" + set rel_bitfile2 "../prebuilt/boot_images" + set rel_data_file ".." + #make folder if not exists + file mkdir ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + # + TE::UTILS::te_msg TE_SW-8 STATUS "Generate ${app_name}.mcs with app: ${app_name}." + #set bitfile to mcs load + if {[lindex $sw_applist_line 2] eq "FIRM"} { + set load_data "up 0x0 ${rel_bitfile}/${int_shortdir}/${TE::VPROJ_NAME}.bit " + } else { + set load_data "up 0x0 ${rel_bitfile2}/${int_shortdir}/${app_name}/${app_name}.bit " + } + #get upload data 01: + set data_index 5 + while {$data_index < [llength $sw_applist_line] } { + if {[lindex $sw_applist_line 5] ne "NA"} { + set load_data "$load_data up [lindex $sw_applist_line [expr $data_index+1]] ${rel_data_file}/[lindex $sw_applist_line $data_index] " + } + set data_index [expr $data_index+3] + } + #write mcs + # -loadbit $load_bit + write_cfgmem -force -format mcs -checksum FF -interface $TE::CFGMEM_IF -size $TE::CFGMEM_MEMSIZE_MB \ + -loaddata $load_data \ + -file ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/${app_name}.mcs + } else { + TE::UTILS::te_msg TE_SW-9 {CRITICAL WARNING} "FPGA FLASH TYP is not specified in *.board_files.csv. *.mcs file is not generated." + } + } + } + } else { + TE::UTILS::te_msg TE_SW-10 WARNING "${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.mmi not found. Nothing is done." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished *bit/*mcs generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # *bin/*bif generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--generate_bif_files: + proc generate_bif_files {{fname ""}} { + set int_shortdir ${TE::SHORTDIR} + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + } + #todo generate relativ path from absolute paths + set checkfile "" + set fsbl_name "" + set rel_bif_bitfile "../../../hardware" + set rel_bif_fsbl "../../../software" + set rel_bif_hsipmu "../../../software" + set rel_bif_data01_file "../../../../" + set rel_bif_appfile "../../../" + set rel_base "" + set bif_bitfile "" + set bif_fsbl "" + set bif_data01_file "" + set bif_appfile "" + + #check bitfile + if {![file exists ${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.bit]} { + # search default + if {![file exists ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit]} { + # default not found + TE::UTILS::te_msg TE_SW-11 ERROR "Bit-file was not found (${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.bit or ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit)" + return -code error "Project bit-file was not found (${TE::PREBUILT_HW_PATH}/${int_shortdir}/${TE::VPROJ_NAME}.bit or ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit)"; + } else { + set bif_bitfile "${rel_bif_bitfile}/default/${TE::VPROJ_NAME}.bit" + } + } else { + set bif_bitfile "${rel_bif_bitfile}/${int_shortdir}/${TE::VPROJ_NAME}.bit" + } + #search for fsbl + foreach sw_applist_line ${TE::SW_APPLIST} { + #read fsbl name + if {[lindex $sw_applist_line 2] eq "FSBL" || [lindex $sw_applist_line 2] eq "FSBL_EXT"} { + set fsbl_name [lindex $sw_applist_line 1] + if {![file exists ${TE::PREBUILT_SW_PATH}/${int_shortdir}/${fsbl_name}.elf]} { + # generate fsbl not found search default + if {![file exists ${TE::PREBUILT_SW_PATH}/default/${fsbl_name}.elf]} { + # default fsbl not found + TE::UTILS::te_msg TE_SW-12 ERROR "FSBL ELF-file was not found (${TE::PREBUILT_SW_PATH}/${int_shortdir}/${fsbl_name}.elf or ${TE::PREBUILT_SW_PATH}/default/${fsbl_name}.elf)." + return -code error "FSBL ELF-file was not found (${TE::PREBUILT_SW_PATH}/${int_shortdir}/${fsbl_name}.elf or ${TE::PREBUILT_SW_PATH}/default/${fsbl_name}.elf)."; + } else { + set bif_fsbl "${rel_bif_fsbl}/default/${fsbl_name}.elf" + TE::UTILS::te_msg TE_SW-13 INFO "Use FSBL from: ${bif_fsbl}" + } + } else { + set bif_fsbl "${rel_bif_fsbl}/${int_shortdir}/${fsbl_name}.elf" + TE::UTILS::te_msg TE_SW-14 INFO "Use FSBL from: ${bif_fsbl}" + } + } + } + foreach sw_applist_line ${TE::SW_APPLIST} { + #generate *.bif only if app_list.csv->steps=0(generate all) or steps=1(*.bif and *.bin use *.elf from prebuild folders ) + if {[lindex $sw_applist_line 2] eq "0" || [lindex $sw_applist_line 2] eq "1" || [lindex $sw_applist_line 2] eq "FSBL_APP"} { + #set correct folders + switch [lindex $sw_applist_line 3] { + "petalinux" { + set checkfile "${TE::PREBUILT_OS_PATH}/petalinux" + set rel_base "${rel_bif_appfile}os/petalinux" + + } + default {#standalone + set checkfile "${TE::PREBUILT_SW_PATH}" + set rel_base "${rel_bif_appfile}software" + } + } + #read fsbl name + #read app name and additional configs + set app_name [lindex $sw_applist_line 1] + TE::UTILS::te_msg TE_SW-15 STATUS "Generate BIF-file for: ${app_name}" + #delete old folder + if {[file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}]} { + file delete -force ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + } + #make new one + file mkdir ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + + if {![file exists ${checkfile}/${int_shortdir}/${app_name}.elf]} { + if { [lindex $sw_applist_line 2] eq "FSBL_APP"} { + # fsbl boot.bin only + set bif_appfile "" + } elseif {![file exists ${checkfile}/default/${app_name}.elf]} { + # search default + # default not found + TE::UTILS::te_msg TE_SW-16 ERROR "Application ELF-file was not found (${checkfile}/${int_shortdir}/${app_name}.elf or ${checkfile}/default/${app_name}.elf)." + return -code error "Application ELF-file was not found (${checkfile}/${int_shortdir}/${app_name}.elf or ${checkfile}/default/${app_name}.elf)."; + } else { + set bif_appfile "${rel_base}/default/${app_name}.elf" + } + + } else { + set bif_appfile "${rel_base}/${int_shortdir}/${app_name}.elf" + } + if {$TE::IS_ZSYS} { + #Zynq + set data01_file [lindex $sw_applist_line 5] + set data01_load [lindex $sw_applist_line 6] + set data01_offset [lindex $sw_applist_line 7] + #replace na with "" + if {[string match $data01_file "NA"]} { set bif_data01_file ""} else { set bif_data01_file "${rel_bif_data01_file}${data01_file}"} + if {[string match $data01_load "NA"]} { set data01_load ""} + if {[string match $data01_offset "NA"]} { set data01_offset ""} + + write_bif ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif $bif_fsbl $bif_bitfile $bif_appfile $bif_data01_file $data01_load $data01_offset "" "" "" + } elseif {$TE::IS_ZUSYS} { + #uzynq + set fsbl_config [lindex $sw_applist_line 5] + if {[string match $fsbl_config "NA"]} { set fsbl_config ""} + set destination_cpu [lindex $sw_applist_line 6] + if {[string match $destination_cpu "NA"]} { set destination_cpu ""} + set exception_level [lindex $sw_applist_line 7] + if {[string match $exception_level "NA"]} { set exception_level ""} + set atf [lindex $sw_applist_line 8] + if {[string match $atf "NA"]} { set atf ""} elseif {[file exists ${checkfile}/${int_shortdir}/${atf}]} { + set atf ${rel_base}/${int_shortdir}/${atf} + } elseif {[file exists ${checkfile}/default/${atf}]} { + set atf ${rel_base}/default/${atf} + } else { + TE::UTILS::te_msg TE_SW-17 WARNING "ATF File was not found in ${checkfile}/${int_shortdir}/${atf} or ${checkfile}/default/${atf}" + set atf "" + } + set pmu [lindex $sw_applist_line 9] + if {[string match $pmu "NA"]} { + set pmu "" + TE::UTILS::te_msg TE_SW-65 WARNING "PMU File not selected on apps_list.csv" + } elseif {[file exists ${TE::PREBUILT_SW_PATH}/${int_shortdir}/${pmu}]} { + set pmu ${rel_bif_hsipmu}/${int_shortdir}/${pmu} + } elseif {[file exists ${TE::PREBUILT_SW_PATH}/default/${pmu}]} { + set pmu ${rel_bif_hsipmu}/default/${pmu} + } elseif {[file exists ${checkfile}/${int_shortdir}/${pmu}]} { + set pmu ${rel_base}/${int_shortdir}/${pmu} + } elseif {[file exists ${checkfile}/default/${pmu}]} { + set pmu ${rel_base}/default/${pmu} + } else { + TE::UTILS::te_msg TE_SW-64 WARNING "PMU File ($pmu) was not found in all possible prebuilt folders" + set pmu "" + } + TE::UTILS::te_msg TE_SW-66 INFO "Use PMU from: ${pmu}" + + write_zusys_bif -biffile ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif -fsbl_config $fsbl_config -bootloader $bif_fsbl -pmu $pmu -bitfile $bif_bitfile -app $bif_appfile -destination_cpu $destination_cpu -exception_level $exception_level -atf $atf + + } else { + #error + TE::UTILS::te_msg TE_SW-18 ERROR "ZSYS or ZUSYS is not defined." + } + } + } + } + #-------------------------------- + #--write_bif: + proc write_bif { biffile {fsblfile "zynq_fsbl.elf"} {bitfile ""} {elffile ""} {data01_file ""} {data01_load ""} {data01_offset ""} {dtbfile ""} {intfile ""} {ssblfile ""} } { + + set bif_fp [open "$biffile" w] + + puts $bif_fp "the_ROM_image:\n\u007B" + # + # init data + # + if {$intfile!=""} { puts -nonewline $bif_fp { [init]}} + if {$intfile!=""} { puts $bif_fp $intfile} + if {$intfile == ""} {TE::UTILS::te_msg TE_SW-19 STATUS "INT FILE NOT DEFINED..."} + # + # FSBL + # + if {$fsblfile!=""} { puts -nonewline $bif_fp { [bootloader]}} + if {$fsblfile!=""} { puts $bif_fp $fsblfile} + if {$fsblfile == ""} {TE::UTILS::te_msg TE_SW-21 STATUS "FSBL FILE NOT DEFINED..."} + # + # BIT file + # + if {$bitfile!=""} { puts $bif_fp " $bitfile"} + if {$bitfile == ""} {TE::UTILS::te_msg TE_SW-22 STATUS "BIT FILE NOT DEFINED..."} + # + # .ELF file + # + if {$elffile!=""} { puts $bif_fp " $elffile"} + if {$elffile == ""} {TE::UTILS::te_msg TE_SW-23 STATUS "ELF FILE NOT DEFINED..."} + # + # SSBL + # + if {$ssblfile!=""} { puts $bif_fp " $ssblfile"} + if {$ssblfile == ""} {TE::UTILS::te_msg TE_SW-24 STATUS "SSBL FILE NOT DEFINED..."} + # + # DTB file + # + if {$dtbfile!=""} { puts $bif_fp " $dtbfile"} + if {$dtbfile == ""} {TE::UTILS::te_msg TE_SW-25 STATUS "DTB FILE NOT DEFINED..."} + # + # image.ub ore IMAGE file + # + + if {$data01_load!="" || $data01_offset!=""} { puts -nonewline $bif_fp { [}} + if {$data01_load!="" } { puts -nonewline $bif_fp {load = };puts -nonewline $bif_fp "$data01_load"} + if {$data01_load!="" && $data01_offset!=""} { puts -nonewline $bif_fp { , }} + if {$data01_offset!="" } { puts -nonewline $bif_fp {offset = };puts -nonewline $bif_fp "$data01_offset"} + if {$data01_load!="" || $data01_offset!=""} { puts -nonewline $bif_fp {]}} + if {$data01_file!=""} { puts $bif_fp $data01_file} + + if {$data01_load == ""} {TE::UTILS::te_msg TE_SW-26 STATUS "FILE01 LOAD NOT DEFINED..."} + if {$data01_offset == ""} {TE::UTILS::te_msg TE_SW-27 STATUS "FILE01 OFFSET NOT DEFINED..."} + if {$data01_file == ""} {TE::UTILS::te_msg TE_SW-28 STATUS "FILE01 FILE NOT DEFINED..."} + + + puts $bif_fp "\u007D" + + close $bif_fp + + } + #-------------------------------- + #--write_zusys_bif: + proc write_zusys_bif {{args ""}} { + set biffile "" + set fsbl_config "" + set bootloader "" + set pmu "" + set bitfile "" + set destination_cpu "" + set exception_level "" + #bl31.elf + set atf "" + set app "" + + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-biffile" { incr option; set biffile [lindex $args $option]} + "-fsbl_config" { incr option; set fsbl_config [lindex $args $option]} + "-bootloader" { incr option; set bootloader [lindex $args $option]} + "-pmu" { incr option; set pmu [lindex $args $option]} + "-bitfile" { incr option; set bitfile [lindex $args $option]} + "-destination_cpu" { incr option; set destination_cpu [lindex $args $option]} + "-exception_level" { incr option; set exception_level [lindex $args $option]} + "-atf" { incr option; set atf [lindex $args $option]} + "-app" { incr option; set app [lindex $args $option]} + default {TE::UTILS::te_msg TE_SW-29 ERROR "unrecognised option for BIF generation: [lindex $args $option]";return -code error } + } + } + set bif_fp [open "$biffile" w] + + puts $bif_fp "//arch = zynqmp; split = false; format = BIN" + puts $bif_fp "the_ROM_image:\n\u007B" + #fsbl_config + if {$fsbl_config!=""} { puts -nonewline $bif_fp { [fsbl_config]}} + if {$fsbl_config!=""} { puts $bif_fp $fsbl_config} + if {$fsbl_config == ""} {TE::UTILS::te_msg TE_SW-30 STATUS "FSBL_CONFIG NOT DEFINED..."} + #bootloader + if {$bootloader!=""} { puts -nonewline $bif_fp { [bootloader]}} + if {$bootloader!=""} { puts $bif_fp $bootloader} + if {$bootloader == ""} {TE::UTILS::te_msg TE_SW-31 STATUS "BOOTLOADER NOT DEFINED..."} + #pmuf + if {$pmu!=""} { puts -nonewline $bif_fp { [pmufw_image]}} + if {$pmu!=""} { puts $bif_fp $pmu} + if {$pmu == ""} {TE::UTILS::te_msg TE_SW-31 STATUS "PMU NOT DEFINED..."} + #bitfile + if {$bitfile!=""} { puts -nonewline $bif_fp { [destination_device = pl]}} + if {$bitfile!=""} { puts $bif_fp $bitfile} + if {$bitfile == ""} {TE::UTILS::te_msg TE_SW-32 STATUS "BITFILE NOT DEFINED..."} + #atf + if {$atf!=""} { puts -nonewline $bif_fp { [}} + if {$atf!=""} { puts -nonewline $bif_fp "destination_cpu =$destination_cpu"} + if {$atf!=""} { puts -nonewline $bif_fp ", exception_level =el-3"} + if {$atf!=""} { puts -nonewline $bif_fp {]}} + if {$atf!=""} { puts $bif_fp $atf} + if {$atf == ""} {TE::UTILS::te_msg TE_SW-33 STATUS "ATF BL31 ELF NOT DEFINED..."} + #elf + if {$app!=""} { puts -nonewline $bif_fp { [}} + if {$app!=""} { puts -nonewline $bif_fp "destination_cpu =$destination_cpu"} + if {$app!="" && $exception_level!=""} { puts -nonewline $bif_fp ", exception_level =$exception_level"} + if {$app!=""} { puts -nonewline $bif_fp {]}} + if {$app!=""} { puts $bif_fp $app} + if {$app == ""} {TE::UTILS::te_msg TE_SW-34 STATUS "APPLICATION ELF NOT DEFINED..."} + + puts $bif_fp "\u007D" + + close $bif_fp + + } + #-------------------------------- + #--generate_bootbin: + proc generate_bootbin {{fname ""}} { + set int_shortdir ${TE::SHORTDIR} + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + } + foreach sw_applist_line ${TE::SW_APPLIST} { + #generate *.bin only if app_list.csv->steps=0(generate all) or steps=1(*.bif and *.bin use *.elf from prebuild folders ) or steps=2(*.bin use *.elf and *.bif from prebuild folders) + if {[lindex $sw_applist_line 2]==0 || [lindex $sw_applist_line 2]==1 || [lindex $sw_applist_line 2]==2 || [lindex $sw_applist_line 2] eq "FSBL_APP"} { + #read app name + set app_name [lindex $sw_applist_line 1] + #delete old one + if {[file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bin]} { + file delete -force ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bin + } + # + if {![file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif]} { + TE::UTILS::te_msg TE_SW-35 ERROR "Application BIF-File found (${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif)." + return -code error "Application BIF-File found (${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/boot.bif)."; + } + #todo:hier noch in default suche? + TE::UTILS::te_msg TE_SW-36 STATUS "Generate Boot.bin for Application: ${app_name}" + set cur_path [pwd] + cd ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + set command exec + lappend command bootgen + lappend command -image boot.bif + #Ultrascale+Zynq + if {$TE::IS_ZUSYS} { + lappend command -arch zynqmp + } + lappend command -w -o BOOT.bin + # puts $command + TE::UTILS::te_msg TE_SW-37 INFO "Start BootGen: \n \ + Run \"$command\" in ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-3 INFO "Command results from BootGen \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished *bin/*bif generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--get_available_apps: + proc get_available_apps {{fname ""}} { + set int_shortdir ${TE::SHORTDIR} + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + } + set applist [] + [catch {set applist [glob -join -dir ${TE::PREBUILT_BI_PATH}/${int_shortdir}/ *]}] + set app_txt "Following Applications are available: \n" + foreach app $applist { + set tmp [split $app "/"] + set app_txt "$app_txt [lindex $tmp [expr [llength $tmp]-1]]\n" + } + TE::UTILS::te_msg TE_PR-38 INFO "$app_txt ------" + } + #-------------------------------- + #--excecute_zynq_flash_programming: + proc excecute_zynq_flash_programming {use_basefolder app_name {fname ""}} { + set return_filename "" + set int_shortdir ${TE::SHORTDIR} + set int_flashtyp $TE::ZYNQFLASHTYP + set run_path "" + set bootbinname BOOT.bin + if {$fname ne ""} { + set int_shortdir "[TE::BDEF::find_shortdir $fname]" + #get flashtyp form shortdir + set int_flashtyp "[TE::BDEF::get_zynqflashtyp $int_shortdir 4]" + } + if {![string match $int_flashtyp "NA"]} { + set cur_path [pwd] + if {$use_basefolder} { + set binfilename "" + if { ![catch {set binfilename [glob -join -dir ${TE::BASEFOLDER}/ *.bin]}] } { + TE::UTILS::te_msg TE_PR-39 STATUS "Used file:${binfilename}" + set return_filename ${binfilename} + set run_path $TE::BASEFOLDER + set nameonly [file tail [file rootname $binfilename]] + set bootbinname ${nameonly}.bin + } else { + TE::UTILS::te_msg TE_PR-40 ERROR "Bin-File was not found in ${TE::BASEFOLDER}." + return -code error "Bin-File was not found in ${TE::BASEFOLDER}."; + } + cd ${TE::BASEFOLDER} + } else { + if {![file exists ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/BOOT.bin]} { + TE::UTILS::te_msg TE_PR-41 ERROR "Application Bin-File was not found (${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/BOOT.bin)." + return -code error "Application Bin-File was not found (${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/BOOT.bin)."; + } + cd ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + set run_path ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name} + set bootbinname BOOT.bin + TE::UTILS::te_msg TE_PR-40 STATUS "Used file:${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/Boot.bin" + set return_filename ${TE::PREBUILT_BI_PATH}/${int_shortdir}/${app_name}/Boot.bin + } + set command exec + + # lappend command zynq_flash + lappend command program_flash + lappend command -f $bootbinname + lappend command -flash_type $int_flashtyp + TE::UTILS::te_msg TE_PR-41 INFO "Start program flash: \n \ + Run \"$command\" in ${run_path} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-4 INFO "Command results from program flash \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } else { + TE::UTILS::te_msg TE_PR-42 ERROR "Programming failed: Zynq Flash Typ is not specified for this board part. See ${TE::BOARDDEF_PATH}/..._board_files.csv" + } + return $return_filename + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # utilities functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--svn_checkin: + proc svn_checkin {foldername {mgs ""}} { + set message $mgs + if {![file exists $foldername]} { + set message "Error: Folder not found ( $foldername)" + } else { + set cur_path [pwd] + cd ${foldername} + set command exec + lappend command svn + lappend command ci + lappend command -m $message + TE::UTILS::te_msg TE_UTIL-72 INFO "Start SVN Checkin: \n \ + Run \"$command\" in ${foldername} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-5 INFO "Command results from SVN check in \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } + } + #-------------------------------- + #--unzip_project: + proc unzip_project {zipname file_location} { + set command exec + if {${TE::ZIP_PATH} ne ""} { + if {[file tail [file rootname ${TE::ZIP_PATH}]] eq "7z"} { + lappend command ${TE::ZIP_PATH} + lappend command x ${file_location}/${zipname} + lappend command -o${file_location} + } else { + lappend command ${TE::ZIP_PATH} + lappend command -help + # lappend command -e ${file_location}/${zipname} + # lappend command ${file_location} + } + TE::UTILS::te_msg TE_UTIL-73 INFO "Start UNZIP: \n \ + Run \"$command\" \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-6 INFO "Command results from UNZIP \"$command\": \n \ + $result \n \ + ------" + } else { + TE::UTILS::te_msg TE_UTIL-74 {CRITICAL WARNING} "Zip not specified. Set zip path and *exe of the zip program in \"design_basic_settings.cmd\" file : example 7zip: @set ZIP_PATH=C:/Program Files (x86)/7-Zip/7z.exe" + } + } + #-------------------------------- + #--zip_project: + proc zip_project {zipname {excludelist ""}} { + #todo mit übergabeparameter prebuilt weglassen oder so + #remove old backup project copy + set sourcepath [string trim $TE::VPROJ_PATH "vivado"] + set destinationpath ${TE::BACKUP_PATH}/${TE::VPROJ_NAME} + if {[file exists ${destinationpath}]} { + file delete -force ${destinationpath} + } + #create new destination folder + file mkdir ${destinationpath} + set cur_path [pwd] + cd ${TE::BACKUP_PATH} + #get all files + set filelist [ glob ${sourcepath}*] + #remove backup folder + set findex [lsearch $filelist *backup] + set filelist [lreplace $filelist[set filelist {}] $findex $findex] + + foreach el $filelist { + file copy -force ${el} ${destinationpath} + } + set excludelist + foreach el $excludelist { + set find "" + if {[catch {set find [glob -join -dir $destinationpath $el]}]} { + TE::UTILS::te_msg TE_UTIL-75 INFO "$el not found." + } else { + TE::UTILS::te_msg TE_UTIL-76 INFO "Excluded from backup:$find" + file delete -force $find + } + } + set command exec + if {${TE::ZIP_PATH} ne ""} { + if {[file tail [file rootname ${TE::ZIP_PATH}]] eq "7z"} { + lappend command ${TE::ZIP_PATH} + lappend command a -tzip "$zipname.zip" + lappend command "./${TE::VPROJ_NAME}/" + lappend command -r + } else { + lappend command ${TE::ZIP_PATH} + lappend command -r + lappend command "$zipname.zip" + lappend command "./${TE::VPROJ_NAME}/*.*" + } + TE::UTILS::te_msg TE_UTIL-77 INFO "Start ZIP: \n \ + Run \"$command\" \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-7 INFO "Command results from ZIP \"$command\": \n \ + $result \n \ + ------" + } else { + TE::UTILS::te_msg TE_UTIL-78 {CRITICAL WARNING} "Zip not specified. Set zip path and *exe of the zip program in \"design_basic_settings.cmd\" file : example 7zip: @set ZIP_PATH=C:/Program Files (x86)/7-Zip/7z.exe" + } + #remove project copy + if {[file exists ${destinationpath}]} { + file delete -force ${destinationpath} + } + cd $cur_path + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished utilities functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # SDSoC functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--run_sdsoc: + proc run_sdsoc {} { + set cur_path [pwd] + cd ${TE::SDSOC_PATH} + set command exec + lappend command sdsoc + lappend command -workspace ${TE::SDSOC_PATH} + # lappend command -lp ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + TE::UTILS::te_msg TE_SW-38 INFO "Start SDSoC: \n \ + Run \"$command\" in ${TE::SDSOC_PATH} \n \ + Please Wait.. \n \ + ------" + set result [eval $command] + TE::UTILS::te_msg TE_EXT-8 INFO "Command results from SDSoC \"$command\": \n \ + $result \n \ + ------" + cd $cur_path + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished sdsoc functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "INFO:(TE) Load Vivado script finished" +} + + diff --git a/zynqberrydemo3/scripts/script_hsi.tcl b/zynqberrydemo3/scripts/script_hsi.tcl new file mode 100644 index 0000000..3fa4ab1 --- /dev/null +++ b/zynqberrydemo3/scripts/script_hsi.tcl @@ -0,0 +1,270 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/05 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/06/13 $ +# -------------------------------------------------------------------- +# -- 2017/06/13 add pmuf hsi support +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval HSI { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # TE HSI variablen declaration + # ----------------------------------------------------------------------------------------------------------------------------------------- + variable HDF_NAME + variable LIB_PATH + variable SW_APPLIST + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished TE HSI variablen declaration + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hsi hw functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--open_project: + proc open_project {} { + if {[catch {set TE::HSI::HDF_NAME [glob -join -dir [pwd] *.hdf]} result]} { puts "Error:(TE) Script (TE::HSI::hsi_open_project) failed: $result."; return -code error} + #todo: eventuell mal extra verzeichnis erstellen, wie sdk + open_hw_design ${TE::HSI::HDF_NAME} + } + #-------------------------------- + #--set_repopath: + proc set_repopath {} { + set_repo_path ${TE::HSI::LIB_PATH} + } + #-------------------------------- + #--close_project: + proc close_project {} { + close_hw_design [current_hw_design] + } + #-------------------------------- + #--get_processors: + proc get_processors {PROCESSOR_ID} { + set proc [get_cells -filter {IP_TYPE==PROCESSOR}] + if {[llength $proc] == 0} { + return -code error "Error:(TE) No Processor found in design ${TE::HSI::HDF_NAME}"; + } else { + if {[llength $proc] > 1} { + puts "Info:(TE) Multiple Processors found." + } + if {[llength $proc] > $PROCESSOR_ID} { + puts "Info:(TE) Processor [lindex $proc $PROCESSOR_ID] is used." + return [lindex $proc $PROCESSOR_ID] + } else { + return -code error "Error:(TE) No Processor ID $PROCESSOR_ID not found in design ${TE::HSI::HDF_NAME}"; + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished hw functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hsi sw functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--create_sw_project: + proc create_sw_project {app_name os uart {proc_id 0}} { + puts "Test: $app_name , $proc_id" + set cpu [get_processors $proc_id] + set hwdesign [current_hw_design] + set swdesign [hsi::create_sw_design system -proc $cpu -app $app_name -os $os] + set os [hsi::get_os] + if {$uart ne "NA"} { + #workaround to change uart -> currently generate_app will delete bsp and write default one + generate_app -hw $hwdesign -sw $swdesign -app $app_name -proc $cpu -dir $app_name -os $os + hsi::close_sw_design $swdesign + hsi::open_sw_design ${app_name}/${app_name}_bsp/system.mss + #reset old variables + set swdesign [get_sw_designs] + set os [hsi::get_os] + #set uart properties + common::set_property CONFIG.stdin $uart $os + common::set_property CONFIG.stdout $uart $os + #generate bsp + hsi::generate_bsp -dir ${app_name}/${app_name}_bsp/ -compile + cd ${app_name} + set result "" + #run make + if {[catch {set result [eval exec make]}]} {puts "Info:(TE) $result"} + cd .. + } else { + generate_app -hw $hwdesign -sw $swdesign -app $app_name -proc $cpu -os $os -dir $app_name -verbose -compile + } + close_sw_design $swdesign + } + #-------------------------------- + #--create_devicetree_project: + proc create_devicetree_project {app_name os} { + set cpu [get_processors 0] + set hwdesign [current_hw_design] + set swdesign [hsi::create_sw_design $app_name -proc $cpu -os $os] + generate_target -dir $app_name + close_sw_design $swdesign + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished sw functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hsi run functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--run_sw_apps: + proc run_sw_apps {} { + #search and generate fsbl and device tree + foreach sw_applist_line ${TE::HSI::SW_APPLIST} { + #generate fsbl only + if {[lindex $sw_applist_line 2] eq "FSBL" } { + set name [lindex $sw_applist_line 1] + set os [lindex $sw_applist_line 3] + set uart [lindex $sw_applist_line 4] + puts "Info:(TE) generate FSBL: $name os: $os Uart: $uart" + create_sw_project $name $os $uart + } + #generate pmu UynqMP only + if {[lindex $sw_applist_line 2] eq "PMU" } { + set name [lindex $sw_applist_line 1] + set os [lindex $sw_applist_line 3] + set uart [lindex $sw_applist_line 4] + #select pmu + set proc_id 6 + puts "Info:(TE) generate PMU: $name os: $os Uart: $uart" + create_sw_project $name $os $uart $proc_id + } + #generate device tree only + if {[lindex $sw_applist_line 2] eq "DTS" } { + set name [lindex $sw_applist_line 1] + set os [lindex $sw_applist_line 3] + puts "Info:(TE) generate Device-Tree: $name os: $os" + create_devicetree_project $name $os + } + } + #search and generate software apps + foreach sw_applist_line ${TE::HSI::SW_APPLIST} { + #generate *.bin only if app_list.csv->steps=0(generate all) or steps=3(*.elf only ) + if {[lindex $sw_applist_line 2] == 0 || [lindex $sw_applist_line 2] == 3} { + set name [lindex $sw_applist_line 1] + set os [lindex $sw_applist_line 3] + set uart [lindex $sw_applist_line 4] + puts "Info:(TE) generate app: $name os: $os Uart: $uart" + create_sw_project $name $os $uart + } + } + } + #-------------------------------- + #--debug_sw_app_list: + proc debug_sw_app_list {} { + set TE::HSI::SW_APPLIST [list] + foreach lpath ${TE::HSI::LIB_PATH} { + if {[file exists ${lpath}/apps_list.csv]} { + puts "Info:(TE) Read Software list from ${lpath}/apps_list.csv" + set fp [open "${lpath}/apps_list.csv" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + # set fsbl_name "" + foreach line $data { + # check file version ignore comments and empty lines + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #check version + set tmp [split $line "="] + #version is ignored for debug only + } elseif {[string match *#* $line] != 1 && [string length $line] > 0} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #splitt and append + set tmp [split $line ","] + lappend TE::HSI::SW_APPLIST $tmp + } + } + } + } + puts "------------------------------------------" + } + #-------------------------------- + #--run_all: + proc run_all {} { + #todo: run all als option und hsi auch über batch separat startbar + puts "Info:(TE) HSI...run all..." + if {[catch {open_project} result]} { puts "Error:(TE) Script (TE::HSI::open_project) failed: $result."; return -code error} + if {[catch {set_repopath} result]} { puts "Error:(TE) Script (TE::HSI::set_repopath) failed: $result."; return -code error} + #---------------------------------------- + if {[catch {run_sw_apps} result]} { puts "Error:(TE) Script (TE::HSI::run_sw_apps) failed: $result."; return -code error} + #---------------------------------------- + if {[catch {close_project} result]} { puts "Error:(TE) Script (TE::HSI::close_project) failed: $result."; return -code error} + } + #-------------------------------- + #--return_option: + proc return_option {option argc argv} { + if { $argc <= [expr $option + 1]} { + return -code error "Error:(TE) Read parameter failed" + } else { + puts "Info:(TE) Parameter Option Value: [lindex $argv [expr $option + 1]]" + return [lindex $argv [expr $option + 1]] + } + } + #-------------------------------- + #--hsi_main: + proc hsi_main {} { + global argc + global argv + set tmp_argc 0 + set tmp_argv 0 + if {$argc >= 1 } { + set tmp_argv [lindex $argv 0] + set tmp_argc [llength $tmp_argv] + } + + set vivrun false + variable SW_APPLIST + variable LIB_PATH + + for {set option 0} {$option < $tmp_argc} {incr option} { + puts "Info:(TE) Parameter Index: $option" + puts "Info:(TE) Parameter Option: [lindex $tmp_argv $option]" + switch [lindex $tmp_argv $option] { + "--sw_list" { set SW_APPLIST [return_option $option $tmp_argc $tmp_argv];incr option } + "--lib" { set LIB_PATH [return_option $option $tmp_argc $tmp_argv];incr option } + "--vivrun" { set vivrun true } + default { puts "" } + } + } + if {$vivrun==true} { + if {[catch {run_all} result]} { puts "Error:(TE) Script (TE::HSI::run_all) failed: $result."; exit} + exit + } + + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished run functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hsi run scripts + # ----------------------------------------------------------------------------------------------------------------------------------------- + if {[catch {hsi_main} result]} { puts "Error:(TE) Script (TE::HSI::hsi_main) failed: $result."; exit} + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished hsi run scripts + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "Info: Load HSI scripts finished" +} + + diff --git a/zynqberrydemo3/scripts/script_main.tcl b/zynqberrydemo3/scripts/script_main.tcl new file mode 100644 index 0000000..28d8483 --- /dev/null +++ b/zynqberrydemo3/scripts/script_main.tcl @@ -0,0 +1,184 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/02 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/06/30 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +puts "-----------------------------------------------------------------------" +#load source scripts +source ../scripts/script_settings.tcl +source ../scripts/script_environment.tcl +source ../scripts/script_vivado.tcl +source ../scripts/script_te_utils.tcl +source ../scripts/script_external.tcl +source ../scripts/script_designs.tcl +source ../scripts/script_usrcommands.tcl +source ../scripts/script_sdsoc.tcl +#sources from other programs: +# source ../scripts/main.tcl +# source ../scripts/hsi.tcl +set sdsoc_available "0" +catch {set sdsoc_available $::env(SDSOC_AVAILABLE)} +if {$sdsoc_available} { + set x_dir "" + set x_vers "" + catch {set x_dir $::env(XILDIR)} + catch {set x_vers $::env(VIVADO_VERSION)} + puts "INFO:(TE) Source Xilinx SDSoC Scripts (${x_dir}/SDx/${x_vers}/scripts/vivado/sdsoc_pfm.tcl)." + source -notrace ${x_dir}/SDx/${x_vers}/scripts/vivado/sdsoc_pfm.tcl +} +puts "-----------------------------------------------------------------------" + +namespace eval TE { + namespace eval INIT { + variable my_script $argv0 + # + + proc return_option {option} { + global argc + global argv + + if { $argc <= [expr $option + 1]} { + puts "ERROR:(TE) Read Parameter failed" + show_help + } else { + puts "INFO:(TE) Parameter Option Value: [lindex $argv [expr $option + 1]]" + return [lindex $argv [expr $option + 1]] + } + } + + proc show_help_batchfile_commands {} { + variable my_script + puts "--TODO: Rework Info for main" + puts "INFO:(TE) Batch-File TCL-Script start options:" + puts "write: vivado -source ../scripts/script_main.tcl -mode batch -notrace -tclargs " + puts "Options:" + puts "Programming:" + puts "--TODO: explanation" + puts "Create/Run Vivado project:" + puts "--run : run option: \ + -1-no nothing is done \ + 0 -open existing project(default) \ + 1 -create selected boardpart project \ + 2 -run selected boardpart project \ + 3 -run all boardpart project" + puts "--boardpart : Trenz Board ID from TEXXXX_boardfiles.csv (you can use ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list)" + puts "--gui : gui mode option:\ + 0 -disable(default) \ + 1 -before project generation \ + 2 -after project generation" + puts "--clean : clean project option:\ + 0 -no(default) \ + 1 -vivado project \ + 2 -vivado and hsi workspace \ + 3 -all (vivado, hsi and sdk workspace )\ + 4 -all and prebuilt (vivado, hsi and sdk workspace and prebuilt)" + puts "--help : display this help and exit" + puts "" + puts "Example: vivado -source ../scripts/script_main.tcl -mode batch -notrace -tclargs --part xc7z020clg484-1 --boardpart trenz.biz:te0720-02-1cf:part0:1.0 --clean" + } + + proc main {} { + global argc + global argv + # + set use_teprocedure "NA" + set use_labtoolsonly false + set use_run_labtools false + set use_clear_all false + set use_run_prebuild_sdk false + set use_zynq_programming false + set use_mcs_programming false + set use_bit_programming false + set use_basefolder false + set use_programming_app "NA" + set use_vivadogui 0 + set use_run 0 + set use_clean 0 + set use_board "NA" + cd .. + + puts "-----------------------------------------------------------------------" + init_pathvar + # + puts "-----------------------------------------------------------------------" + # + if {$argc == 0} { + puts "" + puts "INFO:(TE) Default configuration will be used." + puts "" + } else { + for {set option 0} {$option < $argc} {incr option} { + puts "INFO:(TE) Parameter Index: $option" + puts "INFO:(TE) Parameter Option: [lindex $argv $option]" + switch [lindex $argv $option] { + "--clear_all" { set use_clear_all true } + "--run_te_procedure" { set use_teprocedure [return_option $option]; incr option } + "--run_prebuild_sdk" { set use_run_prebuild_sdk true } + "--run_labtools" { set use_run_labtools true } + "--program_bin" { set use_zynq_programming true } + "--program_mcs" { set use_mcs_programming true } + "--program_bit" { set use_bit_programming true } + "--program_swapp" { set use_programming_app [return_option $option]; incr option } + "--use_basefolder" { set use_basefolder [return_option $option]; incr option } + "--labtools" { set use_labtoolsonly true } + "--run" { set use_run [return_option $option]; incr option } + "--boardpart" { set use_board [return_option $option]; incr option } + "--gui" { set use_vivadogui [return_option $option]; incr option } + "--clean" { set use_clean [return_option $option]; incr option } + "--help" { show_help_batchfile_commands } + "" { } + default { puts "Warning:(TE) unrecognised option: [lindex $argv $option]"; show_help } + } + } + } + + set starttime [clock seconds] + puts "-----------------------------------------------------------------------" + if {$use_clear_all} { + if {[catch {clear_project_all } result]} { puts "ERROR:(TE) Script (TE::INIT::clear_project_all) failed: $result."; return -code error} + } elseif {$use_teprocedure ne "NA"} { + if {[catch {run_te_procedure $use_teprocedure $use_board} result]} { puts "ERROR:(TE) Script (TE::INIT::run_te_procedure) failed: $result."; return -code error} + } elseif {$use_run_labtools} { + if {[catch {run_labtools $use_board } result]} { puts "ERROR:(TE) Script (TE::INIT::run_labtools) failed: $result."; return -code error} + } elseif {$use_run_prebuild_sdk} { + if {[catch {run_sdk $use_board } result]} { puts "ERROR:(TE) Script (TE::INIT::run_sdk) failed: $result."; return -code error} + } elseif {$use_bit_programming} { + if {[catch {program_fpga_bit $use_basefolder $use_board $use_programming_app $use_labtoolsonly} result]} { puts "ERROR:(TE) Script (TE::INIT::program_fpga_bit) failed: $result."; return -code error} + } elseif {$use_mcs_programming} { + if {[catch {program_fpga_mcs $use_basefolder $use_board $use_programming_app $use_labtoolsonly} result]} { puts "ERROR:(TE) Script (TE::INIT::program_fpga_mcs) failed: $result."; return -code error} + } elseif {$use_zynq_programming} { + if {[catch {program_zynq_bin $use_basefolder $use_board $use_programming_app $use_labtoolsonly} result]} { puts "ERROR:(TE) Script (TE::INIT::program_zynq_bin) failed: $result."; return -code error} + } else { + if {[catch {run_project $use_board $use_run $use_vivadogui $use_clean} result]} { puts "ERROR:(TE) Script (TE::INIT::run_project) failed: $result."; return -code error} + } + puts "-----------------------------------------------------------------------" + set stoptime [clock seconds] + set timeelapsed [expr $stoptime -$starttime] + + set report_file ${TE::LOG_PATH}/time_elapsed.txt + set fp_w [open ${report_file} "w"] + puts $fp_w "Times elapsed..." + puts $fp_w "$timeelapsed seconds" + puts $fp_w "..." + close $fp_w + + #--------------------------------------------- + } + + + + if {[catch {main} result]} { + puts "ERROR:(TE) Script (TE::main) failed: $result." + } + } +} \ No newline at end of file diff --git a/zynqberrydemo3/scripts/script_sdsoc.tcl b/zynqberrydemo3/scripts/script_sdsoc.tcl new file mode 100644 index 0000000..4f4e2c2 --- /dev/null +++ b/zynqberrydemo3/scripts/script_sdsoc.tcl @@ -0,0 +1,367 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/04/11 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2016/10/06 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval SDSOC { + + #------------------------------------ + #--create_sdsoc_structure: ... + proc create_sdsoc_structure {} { + #clear old sdsoc + puts "Info:(TE) Delete old SDSOC Project Structure (${TE::SDSOC_PATH})." + TE::UTILS::clean_sdsoc + puts "Info:(TE) Create new SDSOC Project Structure(${TE::SDSOC_PATH})." + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + #-------------------- + #old 2015.4 + # if {[file exists ${TE::SET_PATH}/sdsoc/arm-xilinx-eabi]} { + # file copy -force ${TE::SET_PATH}/sdsoc/arm-xilinx-eabi ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + # } else { + # file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/arm-xilinx-eabi + # } + # if {[file exists ${TE::SET_PATH}/sdsoc/arm-xilinx-linux-gnueabi]} { + # file copy -force ${TE::SET_PATH}/sdsoc/arm-xilinx-linux-gnueabi ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + # } else { + # file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/arm-xilinx-linux-gnueabi + # } + #new 2016.2 + #different settings between 7Series and UltraScaleZynq + if {$TE::IS_ZSYS || $TE::IS_MSYS } { + if {[file exists ${TE::SET_PATH}/sdsoc/aarch32-none]} { + file copy -force ${TE::SET_PATH}/sdsoc/aarch32-none ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + #used for different memory versions + if {[file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld_${TE::SHORTDIR}]} { + if {[file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld]} { + file delete -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld + } + file copy -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld_${TE::SHORTDIR} ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none/lscript.ld + } + } else { + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch32-none + } + } elseif {$TE::IS_ZUSYS} { + if {[file exists ${TE::SET_PATH}/sdsoc/aarch64-none-elf]} { + file copy -force ${TE::SET_PATH}/sdsoc/aarch64-none-elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + #used for different memory versions + if {[file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld_${TE::SHORTDIR}]} { + if {[file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld]} { + file delete -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld + } + file copy -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld_${TE::SHORTDIR} ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf/lscript.ld + } + } else { + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/aarch64-none-elf + } + } + #-------------------- + if {[file exists ${TE::SET_PATH}/sdsoc/boot]} { + file copy -force ${TE::SET_PATH}/sdsoc/boot ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + set prebuit_pl_path ${TE::PREBUILT_OS_PATH}/petalinux/default/ + if {[file exists ${TE::PREBUILT_OS_PATH}/petalinux/${TE::SHORTDIR}]} { + set prebuit_pl_path ${TE::PREBUILT_OS_PATH}/petalinux/${TE::SHORTDIR} + } + if {$TE::IS_ZSYS || $TE::IS_MSYS } { + #search for petalinux generated fsbl.elf + set elf_list [] + if { [catch {set elf_list [ glob ${prebuit_pl_path}/*.elf ] }] } { + } else { + foreach elf $elf_list { + if {[string match *fsbl* $elf]} { + file copy -force $elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/zynq_fsbl.elf + } + } + } + #search for sdk generated fsbl.elf -> overwrite petalinux fsbl.elf if exist + set elf_list [] + if { [catch {set elf_list [ glob ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/*.elf ] }] } { + } else { + foreach elf $elf_list { + if {[string match *fsbl* $elf]} { + file copy -force $elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/zynq_fsbl.elf + } + } + } + #copy rest of prebuilt files + # if {[file exists ${prebuit_pl_path}/urootfs.cpio.gz]} { + # file copy -force ${prebuit_pl_path}/urootfs.cpio.gz ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/uramdisk.image.gz + # } + # if {[file exists ${prebuit_pl_path}/system.dtb]} { + # file copy -force ${prebuit_pl_path}/system.dtb ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/devicetree.dtb + # } + # if {[file exists ${prebuit_pl_path}/uImage]} { + # file copy -force ${prebuit_pl_path}/uImage ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + if {[file exists ${prebuit_pl_path}/image.ub]} { + file copy -force ${prebuit_pl_path}/image.ub ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + if {[file exists ${prebuit_pl_path}/u-boot.elf]} { + file copy -force ${prebuit_pl_path}/u-boot.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + } elseif {$TE::IS_ZUSYS} { + #search for petalinux generated fsbl.elf + set elf_list [] + if { [catch {set elf_list [ glob ${prebuit_pl_path}/*.elf ] }] } { + } else { + foreach elf $elf_list { + if {[string match *fsbl* $elf]} { + file copy -force $elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/fsbl.elf + } + } + } + #search for sdk generated fsbl.elf -> overwrite petalinux fsbl.elf if exist + set elf_list [] + if { [catch {set elf_list [ glob ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/*.elf ] }] } { + } else { + foreach elf $elf_list { + if {[string match *fsbl* $elf]} { + file copy -force $elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/fsbl.elf + } + } + } + # #copy rest of prebuilt files + # if {[file exists ${prebuit_pl_path}/urootfs.cpio.gz]} { + # file copy -force ${prebuit_pl_path}/urootfs.cpio.gz ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/uramdisk.tar.gz + # } + # if {[file exists ${prebuit_pl_path}/system.dtb]} { + # file copy -force ${prebuit_pl_path}/system.dtb ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + # if {[file exists ${prebuit_pl_path}/uImage]} { + # file copy -force ${prebuit_pl_path}/uImage ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + # if {[file exists ${prebuit_pl_path}/bl31.elf]} { + # file copy -force ${prebuit_pl_path}/bl31.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + # if {[file exists ${prebuit_pl_path}/u-boot.elf]} { + # file copy -force ${prebuit_pl_path}/u-boot.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + # } + #copy rest of prebuilt files + if {[file exists ${prebuit_pl_path}/image.ub]} { + file copy -force ${prebuit_pl_path}/image.ub ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + if {[file exists ${prebuit_pl_path}/bl31.elf]} { + file copy -force ${prebuit_pl_path}/bl31.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + if {[file exists ${prebuit_pl_path}/u-boot.elf]} { + file copy -force ${prebuit_pl_path}/u-boot.elf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot/ + } + } + } else { + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/boot + } + #-------------------- + if {[file exists ${TE::SET_PATH}/sdsoc/samples]} { + file copy -force ${TE::SET_PATH}/sdsoc/samples ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + } else { + # file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/samples + } + #-------------------- + if {[file exists ${TE::SET_PATH}/sdsoc/hardware]} { + file copy -force ${TE::SET_PATH}/sdsoc/hardware ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit]} { + file copy -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/hardware/prebuilt/bitstream.bit + } + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf]} { + file copy -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/hardware/prebuilt/export/${TE::PR_TOPLEVELNAME}.hdf + } + } else { + file mkdir ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/hardware + } + } + #------------------------------------ + #--check_vivado_project: ... + proc check_and_modify_vivado_project {check_only} { + if {$check_only} { + puts "---------------------" + puts "Info:(TE) Run SDSOC check:" + puts " Notes:" + puts " -Errors: could not fixed automaticly" + puts " -Warnings: can be fixed automaticly or can be ignored." + puts " Run:" + } else { puts "Info:(TE) Run SDSOC check (modify project):"} + #------------------ + #check sdsoc environment : + # + if {!$TE::SDSOC_AVAILABLE } { + set txt "Error:(TE) SDSOC environment not set." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) SDSOC environment check passed";} + #------------------ + #check zip program : + # + if {![file exists $TE::ZIP_PATH]} { + set txt "Error:(TE) SDSOC ZIP program not found ($TE::ZIP_PATH)." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) SDSOC ZIP program check passed";} + #------------------ + #check pfm settings : + #file to generate hw.pfm + if {![file exists ${TE::SET_PATH}/sdsoc/sdsoc_pfm.tcl]} { + set txt "Error:(TE) Project specific TCL-File for HW_PFM-generation not found (${TE::SET_PATH}/sdsoc_pfm.tcl)." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) HW PFM check passed";} + #------------------ + #check pfm settings : + #file to generate sw.pfm (currently is only a copy) + if {![file exists ${TE::SET_PATH}/sdsoc/sdsoc_sw.pfm]} { + set txt "Error:(TE) Project specific File for SW_PFM-generation not found (${TE::SET_PATH}/sdsoc_sw.pfm)." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) SW PFM check passed";} + #------------------ + #check project name: + #must be platform_name (${TE::VPROJ_NAME}) + if {![file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.xpr]} { + set txt "Error:(TE) Vivado project name is not SDSOC compatible, should be: ${TE::VPROJ_NAME}.xpr" + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Vivado project name check passed";} + #------------------ + #check toplevel name: + #should be _wrapper + set toplevel [get_property top [current_fileset]] + if {![string match *_wrapper $toplevel]} { + set txt "Error:(TE) Top level is not SDSOC compatible, should be: *_wrapper" + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Top Level Name check passed";} + # if {![string match ${TE::VPROJ_NAME}* $toplevel]} { + # set txt "Warning:(TE) Current top level should be: ${TE::VPROJ_NAME}*" + # if {!$check_only} { + # # currently nothing must be done + # # return -code error $txt + # } else {puts " $txt";} + # } + #------------------ + #check processor system: + #must be processor system + if {!$TE::IS_ZSYS && !$TE::IS_ZUSYS && !$TE::IS_MSYS } { + set txt "Error:(TE) Block Design contains no processor system (Checked with TE::INIT::check_bdtyp)." + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Processor check passed";} + #------------------ + #check project language: + #must be verilog + if {[get_property target_language [current_project]] ne "Verilog"} { + set txt "Warning:(TE) Vivado isn't a Verilog Project." + if {!$check_only} { + #change language + set_property target_language Verilog [current_project] + puts "Info:(TE) Target Language check passed (Project Modify:Set target Language to Verilog)" + # return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Target Language check passed";} + #------------------ + #check bd files: + #currently only one bdfile supported (TE) + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + set txt "Error:(TE) No Block Design found. Should be only one!" + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } elseif {[llength $bd_files]>1 } { + set txt "Error:(TE) More than one Block Design found. Should be only one!" + if {!$check_only} { + return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) BD-Design count check passed";} + #------------------ + #check top level file language: + #must be verilog + set bd $bd_files + # open_bd_design $bd -quiet + # set bd_name [get_bd_designs] + set bd_name [open_bd_design $bd -quiet] + if {![file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.v]} { + set txt "Warning:(TE) Toplevel file should be Verilog." + if {!$check_only} { + #remove old vhdl toplevel + remove_files ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.vhd + file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.vhd + #make verilog top + make_wrapper -files [get_files $bd] -top + add_files -norecurse ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.v + update_compile_order -fileset ${TE::SOURCE_NAME} + update_compile_order -fileset ${TE::SIM_NAME} + puts "Info:(TE) Top Level check passed (Project Modify: Regenerate Toplevel as Verilog file)" + # return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Top Level check passed";} + close_bd_design [get_bd_designs $bd] + #------------------ + #check board part : + #board part not allowed + if {[get_property board_part [current_project]] ne ""} { + set txt "Warning:(TE) Board Part usage is not allowed for SDSOC." + if {!$check_only} { + TE::ADV::beta_hw_remove_board_part + puts "Info:(TE) Board Part check passed (Project Modify: Remove Board Part properties)" + # return -code error $txt + } else {puts " $txt";} + } else {puts " Info:(TE) Board Part check passed";} + #------------------ + puts "---------------------" + } + + #------------------------------------ + #--export_vivado_project: ... + proc export_vivado_sdsoc_project {} { + puts "Info:(TE) Create SDSOC Vivado Project on: ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/vivado" + if { [file exists ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/vivado] } { + file delete -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/vivado + } + archive_project ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/${TE::VPROJ_NAME}.xpr.zip -temp_dir ${TE::VPROJ_PATH}/.Xil/Vivado-xxxx- -force -include_config_settings + TE::EXT::unzip_project ${TE::VPROJ_NAME}.xpr.zip ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + file rename -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/${TE::VPROJ_NAME} ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/vivado + file delete -force ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/${TE::VPROJ_NAME}.xpr.zip + } + #------------------------------------ + #--create_sdsoc_pfm: ... + proc create_sdsoc_pfm {} { + puts "Info:(TE) Create SDSOC Vivado Project pfm: ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/" + #open bd design + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + puts "Warning:(TE) No BD-File found." + } + foreach bd $bd_files { + open_bd_design $bd + } + #generate hw pfm + puts "Info:(TE) Generate ${TE::VPROJ_NAME}_hw.pfm" + source -notrace ${TE::SET_PATH}/sdsoc/sdsoc_pfm.tcl + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}_hw.pfm ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/ + #generate sw pfm (todo generate content from existing files) + puts "Info:(TE) Generate ${TE::VPROJ_NAME}_sw.pfm" + file copy -force ${TE::SET_PATH}/sdsoc/sdsoc_sw.pfm ${TE::SDSOC_PATH}/${TE::VPROJ_NAME}/${TE::VPROJ_NAME}_sw.pfm + } + # # ------------------------------------------------------- + } + + puts "Info:(TE) Load SDSOC script finished" +} + + diff --git a/zynqberrydemo3/scripts/script_settings.tcl b/zynqberrydemo3/scripts/script_settings.tcl new file mode 100644 index 0000000..be6c429 --- /dev/null +++ b/zynqberrydemo3/scripts/script_settings.tcl @@ -0,0 +1,874 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/02 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/06/28 $ +# -------------------------------------------------------------------- +# -- 2017/06/13 new release version +# -- 2017/06/28 new board part csv version +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval ::TE { + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # TE variable declaration + # ----------------------------------------------------------------------------------------------------------------------------------------- + # overwrite Setting: + # create TCL file: /settings/development_settings.tcl + # overwrite example: + # set TE:: + # set TE::GEN_HW_BIT false + # ----------------------------------- + # Unsupported Settings: + # --------------------- + # Currently only one BD is allowed + # Multi BD Design is official not supported (maybe not all functions run correctly): + # For Multi BD Design do following: + # 1. set variable BD_MULTI to true + # 2. Make own Top-level File (Name: _top) in the folder "/hdl/" with file name: "_top.vhd" or "_top.v" + variable BD_MULTI false + # + variable DESIGNRUNS [list] + # ----------------------------------- + # Build Settings: + # Attention: there are dependencies between this properties! + # --------------------- + variable GEN_HW_DELETEOLDFILES true + variable GEN_HW_BIT true + variable GEN_HW_MCS true + variable GEN_HW_RPT true + variable GEN_HW_HDF true + variable GEN_SW_HSI true + variable GEN_SW_BIF true + variable GEN_SW_BIN true + variable GEN_SW_BITMCS true + variable GEN_SW_USEPREBULTHDF false + variable GEN_SW_FORCEBOOTGEN false + # ----------------------------------- + # Basic Settings: + # Attention: do not change following variables manually! + # --------------------- + # project path + variable BASEFOLDER + variable VPROJ_NAME + variable VPROJ_PATH + variable VLABPROJ_PATH + variable BOARDDEF_PATH + variable FIRMWARE_PATH + variable IP_PATH + variable BD_PATH + variable XDC_PATH + variable HDL_PATH + variable SET_PATH + variable WORKSPACE_PATH + variable WORKSPACE_HSI_PATH + variable WORKSPACE_SDK_PATH + variable LIB_PATH + variable PREBUILT_PATH + variable PREBUILT_HW_PATH + variable PREBUILT_SW_PATH + variable PREBUILT_BI_PATH + variable PREBUILT_OS_PATH + variable SCRIPT_PATH + variable DOC_PATH + variable LOG_PATH + variable BACKUP_PATH + variable ZIP_PATH + variable SDSOC_PATH + # ----------------------------------- + variable ZIP_IGNORE_LIST [list] + # ----------------------------------- + variable BATCH_FILE_NAME + variable VIVADO_AVAILABLE + variable LABTOOL_AVAILABLE + variable SDK_AVAILABLE + variable SDSOC_AVAILABLE + # ----------------------------------- + variable XILINXGIT_DEVICETREE + variable XILINXGIT_UBOOT + variable XILINXGIT_LINUX + # ----------------------------------- + # board_files + variable ID "NA" + variable PRODID "NA" + variable BOARDPART "NA" + variable PARTNAME "NA" + variable SHORTDIR "NA" + variable ZYNQFLASHTYP "NA" + variable FPGAFLASHTYP "NA" + variable CFGMEM_IF "NA" + variable CFGMEM_MEMSIZE_MB "NA" + # ----------------------------------- + #project run (use default name) + #for renaming use prefix sim*, syn*, imp* and con*! + variable TIMEOUT 120 + variable RUNNING_JOBS 4 + #todo: multiple runs and strategies and modified strategies + variable SIM_NAME sim_1 + variable SYNTH_NAME synth_1 + variable IMPL_NAME impl_1 + variable CONST_NAME constrs_1 + variable SOURCE_NAME sources_1 + # ----------------------------------- + # check csv file ids + variable SCRIPTVER "2017.1.03" + variable BOARDDEF_CSV "1.3" + variable SW_IP_CSV "2.0" + variable BDMOD_CSV "1.1" + variable ZIP_CSV "1.0" + # ----------------------------------- + variable SW_APPLIST [list] + #BOARD_DEFINITION currently in BDEF todo set to init in settings + variable BD_MOD_COMMENT [list] + variable BD_MOD_ADD [list] + variable BD_MOD_PCOMMENT [list] + variable BD_MOD_PADD [list] + variable BD_TCLNAME "NA" + variable PR_TOPLEVELNAME "NA" + variable IS_ZSYS false + variable IS_ZUSYS false + variable IS_MSYS false + variable IS_FSYS false + # ----------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished TE variables declaration + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + namespace eval INIT { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--import_usr_tcl: + proc init_usr_tcl {} { + # hidden function: official not supported + set usr_script [] + if { ![catch {set usr_script [glob -join -dir ${TE::SET_PATH}/usr/ *.tcl]}] } { + TE::UTILS::te_msg TE_INIT-58 INFO "Load additional user TCL-script:\n ${usr_script}" + uplevel 1 [ list ::source ${usr_script}] + } + } + #-------------------------------- + #--print_version: + proc print_version {} { + set viv_version "NA" + if {[catch {set viv_version [lindex [split [::version] "\n"] 0]}]} { set viv_version "NA" } + set TE::BATCH_FILE_NAME "NA" + if {[catch {set TE::BATCH_FILE_NAME $::env(batchfile_name)}]} { set TE::BATCH_FILE_NAME "NA" } + + TE::UTILS::te_msg TE_INIT-0 INFO "Script Info:\n \ + Vivado Version: $viv_version\n \ + TE Script Version: $TE::SCRIPTVER\n \ + Board Part (Definition Files) CSV Version: $TE::BOARDDEF_CSV\n \ + Software IP CSV Version: $TE::SW_IP_CSV\n \ + Board Design Modify CSV Version: $TE::BDMOD_CSV\n \ + ZIP ignore CSV Version: $TE::ZIP_CSV\n \ + ---\n \ + Start project with: $TE::BATCH_FILE_NAME\n \ + ------" + } + #-------------------------------- + #--print_environment_settings: + proc print_environment_settings {} { + set TE::VIVADO_AVAILABLE 0 + set TE::LABTOOL_AVAILABLE 0 + set TE::SDK_AVAILABLE 0 + set TE::SDSOC_AVAILABLE 0 + [catch {set TE::VIVADO_AVAILABLE $::env(VIVADO_AVAILABLE)}] + [catch {set TE::LABTOOL_AVAILABLE $::env(LABTOOL_AVAILABLE)}] + [catch {set TE::SDK_AVAILABLE $::env(SDK_AVAILABLE)}] + [catch {set TE::SDSOC_AVAILABLE $::env(SDSOC_AVAILABLE)}] + TE::UTILS::te_msg TE_INIT-1 INFO "Script Environment:\n \ + Vivado Setting: $TE::VIVADO_AVAILABLE \n \ + LabTools Setting: $TE::LABTOOL_AVAILABLE \n \ + SDK Setting: $TE::SDK_AVAILABLE \n \ + SDSOC Setting: $TE::SDSOC_AVAILABLE \n \ + ------" + + if {$TE::SDK_AVAILABLE==1 && $TE::SDSOC_AVAILABLE==1} { + TE::UTILS::te_msg TE_INIT-2 WARNING "SDK settings are overwritten by SDSOC settings." + } + } + #-------------------------------- + #--init_pathvar: + proc init_pathvar {} { + set tmppath [pwd] + if {[file tail [pwd]]=="vivado"} { + cd .. + } + set TE::BASEFOLDER [pwd] + set TE::VPROJ_NAME [file tail [pwd]] + set TE::VPROJ_PATH [pwd]/vivado + set TE::VLABPROJ_PATH [pwd]/vivado_lab + #-- + set TE::BOARDDEF_PATH [pwd]/board_files + set TE::FIRMWARE_PATH [pwd]/firmware + #-- + set TE::IP_PATH [pwd]/ip_lib + set TE::BD_PATH [pwd]/block_design + set TE::XDC_PATH [pwd]/constraints + set TE::HDL_PATH [pwd]/hdl + set TE::SET_PATH [pwd]/settings + #-- + set TE::WORKSPACE_PATH [pwd]/workspace + set TE::WORKSPACE_HSI_PATH ${TE::WORKSPACE_PATH}/hsi + set TE::WORKSPACE_SDK_PATH ${TE::WORKSPACE_PATH}/sdk + #-- + set TE::LIB_PATH [pwd]/sw_lib + set TE::SCRIPT_PATH [pwd]/scripts + set TE::DOC_PATH [pwd]/doc + #-- + set TE::PREBUILT_PATH [pwd]/prebuilt + set TE::PREBUILT_BI_PATH ${TE::PREBUILT_PATH}/boot_images + set TE::PREBUILT_HW_PATH ${TE::PREBUILT_PATH}/hardware + set TE::PREBUILT_SW_PATH ${TE::PREBUILT_PATH}/software + set TE::PREBUILT_OS_PATH ${TE::PREBUILT_PATH}/os + #-- + set TE::LOG_PATH [pwd]/v_log + set TE::BACKUP_PATH [pwd]/backup + #-- + set TE::ZIP_PATH "" + [catch {set TE::ZIP_PATH $::env(ZIP_PATH)}] + #-- + set TE::SDSOC_PATH [pwd]/sdsoc + set TE::XILINXGIT_DEVICETREE "" + [catch {set TE::XILINXGIT_DEVICETREE $::env(XILINXGIT_DEVICETREE)}] + set TE::XILINXGIT_UBOOT "" + [catch {set TE::XILINXGIT_UBOOT $::env(XILINXGIT_UBOOT)}] + set TE::XILINXGIT_LINUX "" + [catch {set TE::XILINXGIT_LINUX $::env(XILINXGIT_LINUX)}] + #-- + TE::UTILS::te_msg TE_INIT-3 INFO "Initial project names and paths:\n \ + TE::VPROJ_NAME: $TE::VPROJ_NAME \n \ + TE::VPROJ_PATH: $TE::VPROJ_PATH \n \ + TE::VLABPROJ_PATH: $TE::VLABPROJ_PATH \n \ + TE::BOARDDEF_PATH: $TE::BOARDDEF_PATH \n \ + TE::FIRMWARE_PATH: $TE::FIRMWARE_PATH \n \ + TE::IP_PATH: $TE::IP_PATH \n \ + TE::BD_PATH: $TE::BD_PATH \n \ + TE::XDC_PATH: $TE::XDC_PATH \n \ + TE::HDL_PATH: $TE::HDL_PATH \n \ + TE::SET_PATH: $TE::SET_PATH \n \ + TE::WORKSPACE_HSI_PATH: $TE::WORKSPACE_HSI_PATH \n \ + TE::WORKSPACE_SDK_PATH: $TE::WORKSPACE_SDK_PATH \n \ + TE::LIB_PATH: $TE::LIB_PATH \n \ + TE::SCRIPT_PATH: $TE::SCRIPT_PATH \n \ + TE::DOC_PATH: $TE::DOC_PATH \n \ + TE::PREBUILT_BI_PATH: $TE::PREBUILT_BI_PATH \n \ + TE::PREBUILT_HW_PATH: $TE::PREBUILT_HW_PATH \n \ + TE::PREBUILT_SW_PATH: $TE::PREBUILT_SW_PATH \n \ + TE::PREBUILT_OS_PATH: $TE::PREBUILT_OS_PATH \n \ + TE::LOG_PATH: $TE::LOG_PATH \n \ + TE::BACKUP_PATH: $TE::BACKUP_PATH \n \ + TE::ZIP_PATH: $TE::ZIP_PATH \n \ + TE::SDSOC_PATH: $TE::SDSOC_PATH \n \ + TE::XILINXGIT_DEVICETREE: $TE::XILINXGIT_DEVICETREE \n \ + TE::XILINXGIT_UBOOT: $TE::XILINXGIT_UBOOT \n \ + TE::XILINXGIT_LINUX: $TE::XILINXGIT_LINUX \n \ + ------" + + cd $tmppath + } + #-------------------------------- + #--init_board: + proc init_board {ID POS} { + TE::BDEF::get_check_unique_name $ID $POS + + set TE::ID [TE::BDEF::get_id $ID $POS] + set TE::PRODID [TE::BDEF::get_prodid $ID $POS] + set TE::BOARDPART [TE::BDEF::get_boardname $ID $POS] + set TE::PARTNAME [TE::BDEF::get_partname $ID $POS] + set TE::SHORTDIR [TE::BDEF::get_shortname $ID $POS] + set TE::ZYNQFLASHTYP [TE::BDEF::get_zynqflashtyp $ID $POS] + set tmp [TE::BDEF::get_fpgaflashtyp $ID $POS] + #todo extrakt CFGMEM_IF and CFGMEM_MEMSIZE_MB from FPGAFLASHTYP-name and from bitfile configuration + set tmp [split $tmp "|"] + if {[llength $tmp] eq 3} { + set TE::FPGAFLASHTYP [lindex $tmp 0] + set TE::CFGMEM_IF [lindex $tmp 1] + set TE::CFGMEM_MEMSIZE_MB [lindex $tmp 2] + } else { + set TE::FPGAFLASHTYP $tmp + set TE::CFGMEM_IF "NA" + set TE::CFGMEM_MEMSIZE_MB "NA" + } + TE::UTILS::te_msg TE_INIT-4 INFO "Board Part definition:\n \ + TE::ID: $TE::ID \n \ + TE::PRODID: $TE::PRODID \n \ + TE::PARTNAME: $TE::PARTNAME \n \ + TE::BOARDPART: $TE::BOARDPART \n \ + TE::SHORTDIR: $TE::SHORTDIR \n \ + TE::ZYNQFLASHTYP: $TE::ZYNQFLASHTYP \n \ + TE::FPGAFLASHTYP: $TE::FPGAFLASHTYP \n \ + ------" + } + #-------------------------------- + #--init_part_only: init fpga part if found in csv (used if board part is not defined on open project) + proc init_part_only {partname} { + #--check if fpga part is unique + #-2 not found + #-1 some same + #0 unique + #1 all same + set pcheck [TE::BDEF::get_check_unique_name $partname 2] + if {$pcheck == 0 } { + set TE::ID [TE::BDEF::get_id $partname 2] + set TE::PRODID "NA" + set TE::BOARDPART "NA" + set TE::PARTNAME [TE::BDEF::get_partname $partname 2] + set TE::SHORTDIR [TE::BDEF::get_shortname $partname 2] + set TE::ZYNQFLASHTYP [TE::BDEF::get_zynqflashtyp $partname 2] + set tmp [TE::BDEF::get_fpgaflashtyp $partname 2] + #todo extrakt CFGMEM_IF and CFGMEM_MEMSIZE_MB from FPGAFLASHTYP-name and from bitfile configuration + set tmp [split $tmp "|"] + if {[llength $tmp] eq 3} { + set TE::FPGAFLASHTYP [lindex $tmp 0] + set TE::CFGMEM_IF [lindex $tmp 1] + set TE::CFGMEM_MEMSIZE_MB [lindex $tmp 2] + } else { + set TE::FPGAFLASHTYP $tmp + set TE::CFGMEM_IF "NA" + set TE::CFGMEM_MEMSIZE_MB "NA" + } + + TE::UTILS::te_msg TE_INIT-5 WARNING "Board Part definition initialisation with unique part name:\n \ + TE::ID: $TE::ID \n \ + TE::PRODID: $TE::PRODID \n \ + TE::PARTNAME: $TE::PARTNAME \n \ + TE::BOARDPART: $TE::BOARDPART \n \ + TE::SHORTDIR: $TE::SHORTDIR \n \ + TE::ZYNQFLASHTYP: $TE::ZYNQFLASHTYP \n \ + TE::FPGAFLASHTYP: $TE::FPGAFLASHTYP \n \ + ------" + } elseif {$pcheck == 1 } { + #todo check if flash is the same on all definitions + set TE::ID "NA" + set TE::PRODID "NA" + set TE::BOARDPART "NA" + set TE::PARTNAME [TE::BDEF::get_partname $partname 2] + #short name is fpga name + set TE::SHORTDIR [TE::BDEF::get_shortname $partname 2] + set TE::ZYNQFLASHTYP "NA" + set TE::FPGAFLASHTYP "NA" + set TE::CFGMEM_IF "NA" + set TE::CFGMEM_MEMSIZE_MB "NA" + TE::UTILS::te_msg TE_INIT-6 WARNING "Board Part definition initialisation with same part name:\n \ + TE::ID: $TE::ID \n \ + TE::PRODID: $TE::PRODID \n \ + TE::PARTNAME: $TE::PARTNAME \n \ + TE::BOARDPART: $TE::BOARDPART \n \ + TE::SHORTDIR: $TE::SHORTDIR \n \ + TE::ZYNQFLASHTYP: $TE::ZYNQFLASHTYP \n \ + TE::FPGAFLASHTYP: $TE::FPGAFLASHTYP \n \ + ------" + } else { + set TE::ID "NA" + set TE::PRODID "NA" + set TE::BOARDPART "NA" + set TE::PARTNAME $partname + set TE::SHORTDIR $partname + set TE::ZYNQFLASHTYP "NA" + set TE::FPGAFLASHTYP "NA" + set TE::CFGMEM_IF "NA" + set TE::CFGMEM_MEMSIZE_MB "NA" + puts "Warning:(TE) Part name not found, use requested name:" + TE::UTILS::te_msg TE_INIT-7 {CRITICAL WARNING} "Board Part definition initialisation with unknown part name:\n \ + TE::ID: $TE::ID \n \ + TE::PRODID: $TE::PRODID \n \ + TE::PARTNAME: $TE::PARTNAME \n \ + TE::BOARDPART: $TE::BOARDPART \n \ + TE::SHORTDIR: $TE::SHORTDIR \n \ + TE::ZYNQFLASHTYP: $TE::ZYNQFLASHTYP \n \ + TE::FPGAFLASHTYP: $TE::FPGAFLASHTYP \n \ + ------" + } + + } + #-------------------------------- + #--check_bdtyp: check BD typ + proc check_bdtyp {} { + set bd_files [] + set TE::BD_TCLNAME "NA" + set TE::PR_TOPLEVELNAME "NA" + set TE::IS_ZSYS false + set TE::IS_ZUSYS false + set TE::IS_MSYS false + set TE::IS_FSYS false + #get bd_filelist + set bd_files [TE::UTILS::search_bd_files] + foreach bd $bd_files { + set TE::BD_TCLNAME [file tail [file rootname $bd]] + set TE::PR_TOPLEVELNAME "[string trim $TE::BD_TCLNAME "_bd"]_wrapper" + TE::UTILS::te_msg TE_INIT-8 INFO "Found BD-Design:\n \ + TE::BD_TCLNAME: $TE::BD_TCLNAME \n \ + TE::PR_TOPLEVELNAME: $TE::PR_TOPLEVELNAME \n \ + ------" + #check typ for other functions + if {[string match *zsys* $TE::BD_TCLNAME ]} {set TE::IS_ZSYS true; TE::UTILS::te_msg TE_INIT-9 STATUS " TE::IS_ZSYS: $TE::IS_ZSYS" + } elseif {[string match *zusys* $TE::BD_TCLNAME ]} {set TE::IS_ZUSYS true; TE::UTILS::te_msg TE_INIT-10 STATUS " TE::IS_ZUSYS: $TE::IS_ZUSYS" + } elseif {[string match *msys* $TE::BD_TCLNAME ]} {set TE::IS_MSYS true; TE::UTILS::te_msg TE_INIT-11 STATUS " TE::IS_MSYS: $TE::IS_MSYS" + } elseif {[string match *fsys* $TE::BD_TCLNAME ]} {set TE::IS_FSYS true; TE::UTILS::te_msg TE_INIT-12 STATUS " TE::IS_FSYS: $TE::IS_FSYS" + } else { + TE::UTILS::te_msg TE_INIT-13 WARNING "Not all TE-functions support unknown BD Filename. Use: \n \ + \"*zsys*.tcl\" for Systems with Zynq \n \ + \"*zusys*.tcl\" for Systems with UltraScale Zynq \n \ + \"*msys*.tcl\" for Systems with MicroBlaze \n \ + \"*fsys*.tcl\" for Systems with FPGA-Fabric design only \n \ + ------" + } + } + } + #-------------------------------- + #--init_boardlist: + proc init_boardlist {} { + set board_files "" + set TE::BDEF::BOARD_DEFINITION [list] + if { [catch {set board_files [ glob $TE::BOARDDEF_PATH/*board_files_mod.csv ] }] } { + if { [catch {set board_files [ glob $TE::BOARDDEF_PATH/*board_files.csv ] }] } { + TE::UTILS::te_msg TE_INIT-14 WARNING "No board part definition list found (Path: ${TE::BOARDDEF_PATH})." + } + } else { + TE::UTILS::te_msg TE_INIT-15 WARNING "Modified board part definition list found (File: ${board_files})." + } + if {$board_files ne ""} { + TE::UTILS::te_msg TE_INIT-16 INFO "Read board part definition list (File ${board_files})." + set fp [open "${board_files}" r] + set file_data [read $fp] + close $fp + # set TE::BDEF::BOARD_DEFINITION [list] + set data [split $file_data "\n"] + foreach line $data { + # check file version ignore comments and empty lines + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + set tmp [split $line "="] + if {[string match [lindex $tmp 1] $TE::BOARDDEF_CSV] != 1} { + TE::UTILS::te_msg TE_INIT-17 ERROR "Wrong board part definition CSV version (${TE::BOARDDEF_PATH}/board_files.csv) get [lindex $tmp 1] expected ${TE::BOARDDEF_CSV}." + return -code error "Wrong board part definition CSV version (${TE::BOARDDEF_PATH}/board_files.csv) get [lindex $tmp 1] expected ${TE::BOARDDEF_CSV}." + } + } elseif {[string match *#* $line] != 1 && [string length $line] > 0} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #splitt and append + set tmp [split $line ","] + lappend TE::BDEF::BOARD_DEFINITION $tmp + } + } + } + } + #-------------------------------- + #--init_app_list: + proc init_app_list {} { + set TE::SW_APPLIST [list] + if {[file exists ${TE::LIB_PATH}/apps_list.csv]} { + TE::UTILS::te_msg TE_INIT-18 INFO "Read Software list (File: ${TE::LIB_PATH}/apps_list.csv)." + set fp [open "${TE::LIB_PATH}/apps_list.csv" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + # set fsbl_name "" + foreach line $data { + # check file version ignore comments and empty lines + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #check version + set tmp [split $line "="] + if {[string match [lindex $tmp 1] $TE::SW_IP_CSV] != 1} { + TE::UTILS::te_msg TE_INIT-19 ERROR "Wrong Software Definition CSV Version (${TE::LIB_PATH}/apps_list.csv) get [lindex $tmp 1] expected ${TE::SW_IP_CSV}." + return -code error "Wrong Software Definition CSV Version (${TE::LIB_PATH}/apps_list.csv) get [lindex $tmp 1] expected $TE::SW_IP_CSV" + } + } elseif {[string match *#* $line] != 1 && [string length $line] > 0} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #splitt and append + set tmp [split $line ","] + lappend TE::SW_APPLIST $tmp + } + } + #------------------------------------------ + if {![file exists ${TE::XILINXGIT_DEVICETREE}]} { + set tmp_index -1 + foreach sw_applist_line ${TE::SW_APPLIST} { + incr tmp_index + #currently remove Device Tree from list (currently only additonal files) + if {[lindex $sw_applist_line 2] eq "DTS" } { + TE::UTILS::te_msg TE_INIT-20 {CRITICAL WARNING} "Xilinx Devicetree git clone path not found (Path: ${TE::XILINXGIT_DEVICETREE}). Device-Tree generation will be removed from apps_list.csv" + set TE::SW_APPLIST [lreplace $TE::SW_APPLIST $tmp_index $tmp_index] + } + } + } + #------------------------------------------ + } else { + TE::UTILS::te_msg TE_INIT-21 INFO "No software apps_list used." + } + } + #-------------------------------- + #--init_zip_ignore_list: + proc init_zip_ignore_list {} { + set TE::ZIP_IGNORE_LIST [list] + if {[file exists ${TE::SET_PATH}/zip_ignore_list.csv]} { + TE::UTILS::te_msg TE_INIT-22 INFO "Read ZIP ignore list (File: ${TE::LIB_PATH}/apps_list.csv)." + set fp [open "${TE::SET_PATH}/zip_ignore_list.csv" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + foreach line $data { + # check file version ignore comments and empty lines + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #check version + set tmp [split $line "="] + if {[string match [lindex $tmp 1] $TE::ZIP_CSV] != 1} { + TE::UTILS::te_msg TE_INIT-23 ERROR " Wrong Zip ignore definition CSV Version (${TE::SET_PATH}/zip_ignore_list.csv) get [lindex $tmp 1] expected ${TE::ZIP_CSV}." + return -code error "Wrong Zip ignore definition CSV Version (${TE::SET_PATH}/zip_ignore_list.csv) get [lindex $tmp 1] expected ${TE::ZIP_CSV}." + } + } elseif {[string match *#* $line] != 1 && [string length $line] > 0} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #splitt and append + set tmp [split $line ","] + lappend TE::ZIP_IGNORE_LIST $tmp + } + } + } else { + TE::UTILS::te_msg TE_INIT-24 INFO "No Zip ignore list used." + } + } + #-------------------------------- + #--init_mod_list: + proc init_mod_list {} { + set TE::BD_MOD_COMMENT [list] + set TE::BD_MOD_ADD [list] + set TE::BD_MOD_PCOMMENT [list] + set TE::BD_MOD_PADD [list] + if {[file exists ${TE::BD_PATH}/mod_bd.csv]} { + TE::UTILS::te_msg TE_INIT-25 INFO "Read BD modify list (File: ${TE::BD_PATH}/mod_bd.csv)." + set fp [open "${TE::BD_PATH}/mod_bd.csv" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + foreach line $data { + #ignore comments and empty lines + if {[string match *#* $line] != 1 && [string length $line] > 0} { + # check file version + if {[string match *CSV_VERSION* $line] } { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #check version + set tmp [split $line "="] + if {[string match [lindex $tmp 1] $TE::BDMOD_CSV] != 1} { + TE::UTILS::te_msg TE_INIT-26 ERROR " Wrong BD Modify CSV Version (${TE::BD_PATH}/mod_bd.csv) get [lindex $tmp 1] expected ${TE::BDMOD_CSV}." + return -code error " Wrong BD Modify CSV Version (${TE::BD_PATH}/mod_bd.csv) get [lindex $tmp 1] expected $TE::BDMOD_CSV" + } + } else { + #split line + set temp [split $line ","] + if {[llength $temp] <3} { + TE::UTILS::te_msg TE_INIT-27 WARNING "Not enough elements on line ($line). Line ignored." + } else { + #get line id +remove spaces and tabs + set line_id [string map {"\t" ""} [string map {" " ""} [lindex $temp 0]]] + #sort + if {$line_id eq "id"} { + #table header + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + set temp [split $line ","] + lappend TE::BD_MOD_COMMENT $temp + lappend TE::BD_MOD_ADD $temp + lappend TE::BD_MOD_PCOMMENT $temp + lappend TE::BD_MOD_PADD $temp + } elseif {$line_id==0} { + # ID 0: remove(comment) line + lappend TE::BD_MOD_COMMENT $temp + } elseif {$line_id==1} { + # ID 1: add line + if {[llength $temp] >3} { + # replaced removed comma from modify txt + set newinsert_list [list] + lappend newinsert_list [lindex $temp 0] + lappend newinsert_list [lindex $temp 1] + set addstring [lindex $temp 2] + for {set i 3} {$i < [llength $temp]} {incr i} { + set addstring "${addstring},[lindex $temp $i]" + } + lappend newinsert_list $addstring + set temp $newinsert_list + } + lappend TE::BD_MOD_ADD $temp + } elseif {$line_id==2} { + # ID 2: remove(comment) property + lappend TE::BD_MOD_PCOMMENT $temp + } elseif {$line_id==3} { + # ID 3: add property + lappend TE::BD_MOD_PADD $temp + } else { + #unsupported lines ignored + TE::UTILS::te_msg TE_INIT-28 WARNING "Unsupported id ($line_id). Line ignored." + } + } + } + } + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + + namespace eval BDEF { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # board part definition functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + variable BOARD_DEFINITION [list] + #{"ID" "PRODID" "PARTNAME" "BOARDNAME" "SHORTDIR"} + #extract board definition list from board definition file "board_files.csv" + #-------------------------------- + #--find_shortdir: + proc find_shortdir {NAME} { + variable BOARD_DEFINITION + #search in id + set value [get_shortname $NAME 0] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-29 STATUS "Found Shortname: $value";return $value} + #search in productid + set value [get_shortname $NAME 1] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-30 STATUS "Found Shortname: $value";return $value} + #search in boardname + set value [get_shortname $NAME 3] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-31 STATUS "Found Shortname: $value";return $value} + #search in shortname + set value [get_shortname $NAME 4] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-32 STATUS "Found Shortname: $value";return $value} + #search in part name (only if unique) + if {[get_check_unique_name $NAME 2]==0} { + set value [get_shortname $NAME 2] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-33 STATUS "Found Shortname: $value";return $value} + } + #default + TE::UTILS::te_msg TE_INIT-34 STATUS "No Shortname found for ${NAME}, use default " + return "default" + } + #-------------------------------- + #--find_id: + proc find_id {NAME} { + variable BOARD_DEFINITION + #search in id + set value [get_id $NAME 0] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-35 STATUS "Found ID: $value";return $value} + #search in productid + set value [get_id $NAME 1] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-36 STATUS "Found ID: $value";return $value} + #search in boardname + set value [get_id $NAME 3] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-37 STATUS "Found ID: $value";return $value} + #search in shortname + set value [get_id $NAME 4] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-38 STATUS "Found ID: $value";return $value} + #search in part name (only if unique) + if {[get_check_unique_name $NAME 2]==0} { + set value [get_id $NAME 2] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-39 STATUS "Found ID: $value";return $value} + } + #default + TE::UTILS::te_msg TE_INIT-40 STATUS "No ID found for ${NAME}, use NA " + return "NA" + } + #-------------------------------- + #--find_partname: + proc find_partname {NAME} { + variable BOARD_DEFINITION + #search in id + set value [get_partname $NAME 0] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-41 STATUS "Found part name: $value";return $value} + #search in productid + set value [get_partname $NAME 1] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-42 STATUS "Found part name: $value";return $value} + #search in boardname + set value [get_partname $NAME 3] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-43 STATUS "Found part name: $value";return $value} + #search in shortname + set value [get_partname $NAME 4] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-44 STATUS "Found part name: $value";return $value} + #search in part name (only if unique) + if {[get_check_unique_name $NAME 2]==0} { + set value [get_partname $NAME 2] + if {$value ne "NA"} {TE::UTILS::te_msg TE_INIT-45 STATUS "Found part name: $value";return $value} + } + #default + TE::UTILS::te_msg TE_INIT-46 STATUS "No part name found for ${NAME}, use NA " + return "NA" + } + #-------------------------------- + #--get_check_unique_name: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_check_unique_name {NAME POS} { + variable BOARD_DEFINITION + set part_count 0 + set max_count [expr [llength $BOARD_DEFINITION] -1] + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + set part_count [expr $part_count+1] + } + } + #-2 not found + #-1 some same + #0 unique + #1 all same + if {$part_count==0} { + TE::UTILS::te_msg TE_INIT-47 STATUS "Board part csv name check: $NAME not found on position $POS." + return -2 + } elseif {$part_count==$max_count} { + TE::UTILS::te_msg TE_INIT-48 STATUS "Board part csv name check: All names ($NAME) are equal on position $POS." + return 1 + } elseif {$part_count==1} { + TE::UTILS::te_msg TE_INIT-49 STATUS "Board part csv name check: $NAME is unique on position $POS." + return 0 + } else { + TE::UTILS::te_msg TE_INIT-50 STATUS "Board part csv name check: Only some names ($NAME) are equal on position $POS." + return -1 + } + } + #-------------------------------- + #--get_id: Name--> search name, POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_id {NAME POS} { + variable BOARD_DEFINITION + set last_id 0 + foreach sublist $BOARD_DEFINITION { + if {$last_id < [lindex $sublist 0] && [lindex $sublist 0] ne "ID"} { + set last_id [lindex $sublist 0] + } + # if { [string equal $NAME [lindex $sublist $POS]] } { + # return [lindex $sublist 0] + # } + if { [string match -nocase $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 0] + } + } + if {$NAME eq "LAST_ID"} { + #return the the highest id from the list + return $last_id + } + #default + TE::UTILS::te_msg TE_INIT-51 STATUS "ID not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_prodid: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_prodid {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 1] + } + } + #default + TE::UTILS::te_msg TE_INIT-52 STATUS "Product ID not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_partname: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_partname {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 2] + } + } + #default + TE::UTILS::te_msg TE_INIT-53 STATUS "Part Name not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_boardname: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_boardname {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 3] + } + } + #default + TE::UTILS::te_msg TE_INIT-54 STATUS "Board Name not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_shortname: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_shortname {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 4] + } + } + #default + TE::UTILS::te_msg TE_INIT-55 STATUS "Short Name not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_zynqflashtyp: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_zynqflashtyp {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 5] + } + } + #default + TE::UTILS::te_msg TE_INIT-56 STATUS "Zynq Flash typ not found for $NAME $POS, return default: NA" + return "NA" + } + #-------------------------------- + #--get_fpgaflashtyp: POS: Table position ID(0)(unique) PRODID(1)(unique),PARTNAME(2),BOARDNAME(3)(unique),SHORTNAME(4)(unique),ZYNQFLASHTYP(5),FPGAFLASHTYP(6) + proc get_fpgaflashtyp {NAME POS} { + variable BOARD_DEFINITION + foreach sublist $BOARD_DEFINITION { + if { [string equal $NAME [lindex $sublist $POS]] } { + return [lindex $sublist 6] + } + } + #default + TE::UTILS::te_msg TE_INIT-57 STATUS "FPGA Flash typ not found for $NAME $POS, return default: NA" + return "NA" + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished initial functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "INFO:(TE) Load Settings Script finished" +} \ No newline at end of file diff --git a/zynqberrydemo3/scripts/script_te_utils.tcl b/zynqberrydemo3/scripts/script_te_utils.tcl new file mode 100644 index 0000000..003af23 --- /dev/null +++ b/zynqberrydemo3/scripts/script_te_utils.tcl @@ -0,0 +1,766 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/04 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/05/18 $ +# -------------------------------------------------------------------- +# -- 2017/06/13 rise te_msg cnt +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval UTILS { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #-------------------------------- + #--te_msg: + proc te_msg {vmsg_id vmsg_sev vmsg_msg} { + # vmsg_id: TE_INIT, TE_UT, TE_EXT, TE_BD, TE_HW, TE_SW, TE_PR + #last vmsg_nr: + #TE_INIT 169 -> TE initialisation + #TE_UTIL 99 -> TE utilities + #TE_EXT 8 -> External + #TE_PS 1 -> PS modification 0,1-> external tcl-scripts with settings! + #TE_BD 26 -> Block Design + #TE_HW 81 -> HW Design + #TE_SW 66 -> SW Design + #TE_PR 84 -> Programming + # vmsg_sev: STATUS, INFO, WARNING, {CRITICAL WARNING}, ERROR + # set vmsg_id TE_DEF;set vmsg_sev STATUS;set vmsg_msg "Info"; + # common::send_msg_id "$vmsg_id" $vmsg_sev $vmsg_msg + if {[catch {common::send_msg_id "$vmsg_id" $vmsg_sev $vmsg_msg}] } {puts "${vmsg_sev}: ($vmsg_id) $vmsg_msg"} + #Info: Do not start Text with: -- + #TE::UTILS::te_msg TE_INIT-2 WARNING "SDK settings are overwritten by SDSOC settings." + #TE::UTILS::te_msg TE_INIT-0 INFO "Script Info: \n \ + # ------" + + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # search source files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--search_bd_files: search in TE::BD_PATH for *.tcl files return list + proc search_bd_files {} { + # search for block design for the board part only (folder with tcl must exist, otherwise base BD_Path is used!) + #currently only on bd.tcl is allowed + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::BD_PATH}/${TE::SHORTDIR} *.tcl]}] } { + if { [catch {set bd_files [glob -join -dir ${TE::BD_PATH}/ *.tcl]}] } { + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + TE::UTILS::te_msg TE_UTIL-0 WARNING "No Block-Design Export was found in ${TE::BD_PATH}, start vivado without bd-design" + } else { + TE::UTILS::te_msg TE_UTIL-1 WARNING "No Block-Design Export was found, use current Vivado project Block-Designs from:${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ ." + } + } + } + set bd_names "" + foreach bd $bd_files { + set bd_names "$bd_names $bd \n" + } + TE::UTILS::te_msg TE_UTIL-2 INFO "Following block designs were found: \n \ + $bd_names \ + ------" + if {!$TE::BD_MULTI} { + if {[llength $bd_files]>1 } { + TE::UTILS::te_msg TE_UTIL-3 WARNING "Currently only one Block-Design is supported with TE-scripts, deleted or rename file-extension from unused *.tcl in ${TE::BD_PATH} or ${TE::BD_PATH}/${TE::SHORTDIR}." + return -code error "Currently only one Block-Design is supported with TE-scripts, deleted or rename file-extension from unused *.tcl in ${TE::BD_PATH} or ${TE::BD_PATH}/${TE::SHORTDIR}." + } + } + return $bd_files + } + #-------------------------------- + #--search_xdc_files: search in TE::XDC_PATH for *xdc files return list + proc search_xdc_files {} { + # search for xdc file if bord part folder exist, this used too + set xdc_files [] + set base_xdc_files [] + set bp_xdc_files [] + if { [catch {set base_xdc_files [ glob $TE::XDC_PATH/*.xdc ] }] } { + TE::UTILS::te_msg TE_UTIL-4 WARNING "*.xdc search: ${TE::XDC_PATH}/ is empty." + } + if {[file exists ${TE::XDC_PATH}/${TE::SHORTDIR}/]} { + if { [catch {set bp_xdc_files [ glob $TE::XDC_PATH/${TE::SHORTDIR}/*.xdc ] }] } { + TE::UTILS::te_msg TE_UTIL-5 WARNING "*.xdc search: ${TE::XDC_PATH}/${TE::SHORTDIR}/ is empty." + } + #generate empty target xdc for gui constrains + if { ![file exists ${TE::XDC_PATH}/${TE::SHORTDIR}/vivado_target.xdc]} { + TE::UTILS::te_msg TE_UTIL-6 INFO "Generate ${TE::XDC_PATH}/${TE::SHORTDIR}/vivado_target.xdc" + close [ open ${TE::XDC_PATH}/${TE::SHORTDIR}/vivado_target.xdc w ] + lappend bp_xdc_files ${TE::XDC_PATH}/${TE::SHORTDIR}/vivado_target.xdc + } + set xdc_files [concat $base_xdc_files $bp_xdc_files] + } else { + set xdc_files $base_xdc_files + #generate empty target xdc for gui constrains + if { ![file exists ${TE::XDC_PATH}/vivado_target.xdc]} { + TE::UTILS::te_msg TE_UTIL-7 INFO "Generate ${TE::XDC_PATH}/vivado_target.xdc" + close [ open ${TE::XDC_PATH}/vivado_target.xdc w ] + lappend xdc_files ${TE::XDC_PATH}/vivado_target.xdc + } + } + + set xdc_names "" + foreach xdc $xdc_files { + set xdc_names "$xdc_names $xdc \n" + } + TE::UTILS::te_msg TE_UTIL-8 INFO "Following xdc files were found: \n \ + $xdc_names \ + ------" + + return $xdc_files + } + #-------------------------------- + #--search_xci_files: search in TE::HDL_PATH for *.xci files return list + proc search_xci_files {} { + set xci_files [list] + set xci_files_main [list] + set xci_files_sub [list] + catch {set xci_files_main [glob -join -dir $TE::HDL_PATH/xci/ *.xci]} + catch {set xci_files_sub [glob -join -dir $TE::HDL_PATH/xci/${TE::SHORTDIR}/ *.xci]} + set xci_files [concat $xci_files_main $xci_files_sub] + set xci_names "" + foreach xci_f $xci_files { + set xci_names "$xci_names $xci_f \n" + } + TE::UTILS::te_msg TE_UTIL-9 INFO "Following xci files were found: \n \ + $xci_names \ + ------" + + return $xci_files + } + #-------------------------------- + #--search_elf_files: search in TE::FIRMWARE_PATH for *.elf files return list + proc search_elf_files {} { + set elf_files_sub [list] + catch {set elf_files_sub [glob -join -dir ${TE::FIRMWARE_PATH} */*.elf]} + + set elf_names "" + foreach elf_f $elf_files_sub { + set elf_names "$elf_names $elf_f \n" + } + TE::UTILS::te_msg TE_UTIL-10 INFO "Following elf files were found: \n \ + $elf_names \ + ------" + + return $elf_files_sub + } + #-------------------------------- + #--search_hdl_files: search in TE::HDL_PATH for *.vhd and *.v files return list + proc search_hdl_files {} { + set hdl_files [list] + set vhd_files [list] + set vhd_files_sub1 [list] + set vhd_files_sub2 [list] + set v_files [list] + set v_files_sub1 [list] + set v_files_sub2 [list] + set sv_files [list] + set sv_files_sub1 [list] + set sv_files_sub2 [list] + catch {set vhd_files [glob -join -dir ${TE::HDL_PATH} *.vhd]} + catch {set vhd_files_sub1 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ *.vhd]} + catch {set vhd_files_sub2 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.vhd]} + catch {set v_files [glob -join -dir ${TE::HDL_PATH} *.v]} + catch {set v_files_sub1 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.v]} + catch {set v_files_sub2 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.v]} + catch {set sv_files [glob -join -dir ${TE::HDL_PATH} *.sv]} + catch {set sv_files_sub1 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.sv]} + catch {set sv_files_sub2 [glob -join -dir ${TE::HDL_PATH}/${TE::SHORTDIR}/ */*.sv]} + set hdl_files [concat $vhd_files $vhd_files_sub1 $vhd_files_sub2 $v_files $v_files_sub1 $v_files_sub2 $sv_files $sv_files_sub1 $sv_files_sub2] + + set hdl_names "" + foreach hdl_f $hdl_files { + set hdl_names "$hdl_names $hdl_f \n" + } + TE::UTILS::te_msg TE_UTIL-11 INFO "Following hdl files were found: \n \ + $hdl_names \ + ------" + + return $hdl_files + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished search source files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # modify block design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--modify_block_design_tcl: + proc setinfo_to_block_design_tcl {datalist mod_file} { + TE::UTILS::te_msg TE_UTIL-22 INFO "Block Design tcl: info lines were added." + set data $datalist + if {$mod_file} { + # set data [linsert $data[set data {}] 0 "puts \"Info:(TE) This block design file has been modified. Modifications labelled with comment tag # #TE_MOD# on the Block-Design tcl-file.\""] + set data [linsert $data[set data {}] 0 "TE::UTILS::te_msg TE_BD-1 INFO \"This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag # #TE_MOD# on the Block-Design tcl-file.\""] + } + # set data [linsert $data[set data {}] 0 "puts \"Info:(TE) This block design file has been exported with Reference-Design Scripts from Trenz Electronic GmbH for Board Part:${TE::BOARDPART} with FPGA ${TE::PARTNAME} at [ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"].\""] + set data [linsert $data[set data {}] 0 "TE::UTILS::te_msg TE_BD-0 INFO \"This block design tcl-file was generate with Trenz Electronic GmbH Board Part:${TE::BOARDPART}, FPGA: ${TE::PARTNAME} at [ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"].\""] + return $data + } + #-------------------------------- + #--modify_block_design_tcl: load and save block design tcl (sub functions used for modifications) + proc modify_block_design_tcl {file_name mod_file} { + TE::UTILS::te_msg TE_UTIL-12 STATUS "Open bd design export [file tail [file rootname $file_name]]" + #read file to string list + set fp_r [open ${file_name} "r"] + set file_data [read $fp_r] + close $fp_r + + set data [split $file_data "\n"] + + #modify list elements () + if {$mod_file} { + if {[catch {set data [modify_block_design_commentlines $data]} result]} { TE::UTILS::te_msg TE_UTIL-13 ERROR "Script (TE::UTILS::modify_block_design_commentlines) failed: $result."; return -code error} + if {[catch {set data [modify_block_design_commentdesignprops $data]} result]} { TE::UTILS::te_msg TE_UTIL-14 ERROR "Script (TE::UTILS::modify_block_design_commentdesignprops) failed: $result."; return -code error} + if {[catch {set data [modify_block_design_add_lines $data]} result]} { TE::UTILS::te_msg TE_UTIL-15 ERROR "Script (TE::UTILS::modify_block_design_add_lines) failed: $result."; return -code error} + if {[catch {set data [modify_block_design_add_designprops $data]} result]} { TE::UTILS::te_msg TE_UTIL-16 ERROR "Script (TE::UTILS::modify_block_design_add_designprops) failed: $result."; return -code error} + } + # write info header + if {[catch {set data [TE::UTILS::setinfo_to_block_design_tcl $data $mod_file]} result]} { TE::UTILS::te_msg TE_UTIL-17 ERROR "Script (TE::UTILS::setinfo_to_block_design_tcl) failed: $result."; return -code error} + #write all list elements to file + set fp_w [open ${file_name} "w"] + foreach line $data { + puts $fp_w $line + } + close $fp_w + } + #-------------------------------- + #--modify_block_design_commentlines: + proc modify_block_design_commentlines {datalist} { + #data=tcl content + set data $datalist + #modify list elements + set line_index -1 + set mod_count 0 + foreach line $data { + incr line_index + foreach cname $TE::BD_MOD_COMMENT { + set line_check [lindex $cname 1] + #comment lines on tcl file, modified lines are ignored + if {[string match $line_check $line] && ![string match *#TE_MOD#* $line]} { + set data [lreplace $data[set data {}] $line_index $line_index "# #TE_MOD# $line"] + incr mod_count + } + } + } + TE::UTILS::te_msg TE_UTIL-18 INFO "Block Design tcl: $mod_count lines were commented out." + return $data + } + #-------------------------------- + #--modify_block_design_commentdesignprops: + proc modify_block_design_commentdesignprops {datalist} { + #data=tcl content + set data $datalist + #modify list elements + set mod_count 0 + foreach cname $TE::BD_MOD_PCOMMENT { + set prop_start_name "set_property -dict" + #get instant name + set inst_name [lindex $cname 1] + set prop_stop_name "\] \$$inst_name" + #modify list elements + set line_index -1 + set prop_start -1 + set prop_stop -1 + #search for property boundaries + foreach line $data { + incr line_index + if {[string match *$prop_start_name* $line] && ![string match *#TE_MOD#* $line]} { + set prop_start $line_index + } + if {[string match *$prop_stop_name $line] && ![string match *#TE_MOD#* $line]} { + set prop_stop $line_index + break; + } + } + #only if component found + if {$prop_start>=0 && $prop_stop>$prop_start} { + + set removed_items [list] + set item_cnt -1 + #removed items + foreach item $cname { + incr item_cnt + #ignore id and line_check + if {$item_cnt>1} { + set i $prop_stop + while {$i >= $prop_start} { + set i [expr $i-1] + set newline "[lindex $data $i]" + if {[string match *$item* $newline] && ![string match *#TE_MOD#* $newline]} { + lappend removed_items "# #TE_MOD# $newline" + set data [lreplace $data[set data {}] $i $i] + incr mod_count + } + } + } + } + #add removed items as comment after the component list + set inserpos [expr $prop_stop + 2 - [llength $removed_items]] + set data [linsert $data[set data {}] $inserpos "# #TE_MOD# #Empty Line"] + foreach el [lreverse $removed_items] { + set data [linsert $data[set data {}] $inserpos $el] + } + # if all properties are removed, clear empty property container + if {[expr $prop_stop-$prop_start]==[llength $removed_items]} { + set tmp "# #TE_MOD# [lindex $data $prop_start]" + set data [lreplace $data[set data {}] $prop_start $prop_start $tmp] + set tmp "# #TE_MOD# [lindex $data [expr $prop_start+1]]" + set data [lreplace $data[set data {}] [expr $prop_start+1] [expr $prop_start+1] $tmp] + } + } + } + TE::UTILS::te_msg TE_UTIL-19 INFO "Block Design tcl: $mod_count properties were commented out." + return $data + } + #-------------------------------- + #--modify_block_design_add_lines: + proc modify_block_design_add_lines {datalist} { + #data=tcl content + set data $datalist + #modify list elements + set line_index -1 + set mod_count 0 + foreach cname $TE::BD_MOD_ADD { + set line_check [lindex $cname 1] + set line_index -1 + foreach line $data { + incr line_index + #add lines on tcl file, modified lines are ignored + if {[string match $line_check $line] && ![string match *#TE_MOD#* $line]} { + # set data [lreplace $data[set data {}] $line_index $line_index "# #TE_MOD# $line"] + set data [linsert $data[set data {}] [expr $line_index+1] "# #TE_MOD#_Add next line#"] + set data [linsert $data[set data {}] [expr $line_index+2] [lindex $cname 2]] + incr mod_count + break + } + } + } + TE::UTILS::te_msg TE_UTIL-20 INFO "Block Design tcl: $mod_count lines were added." + return $data + } + #-------------------------------- + #--modify_block_design_add_designprops: + proc modify_block_design_add_designprops {datalist} { + #data=tcl content + set data $datalist + #modify list elements + set mod_count 0 + foreach cname $TE::BD_MOD_PADD { + #get instant name + set inst_name [lindex $cname 1] + set prop_stop_name "\] \$$inst_name" + #modify list elements + set line_index -1 + set prop_start -1 + set prop_stop -1 + set all_props_removed -1 + #search for property boundaries + foreach line $data { + incr line_index + if {[string match *$prop_stop_name $line]} { + if {![string match *#TE_MOD#* $line] } { + set prop_stop $line_index + } else { + set all_props_removed $line_index + } + break; + } + } + #if component props found + if {$prop_stop>-1} { + #add removed items as comment after the component list + set inserpos [expr $prop_stop + 1] + set el_index -1 + #add property as comment + foreach el $cname { + incr el_index + #ignore id and line_check + if {$el_index>1} { + set data [linsert $data[set data {}] $inserpos "# #TE_MOD#_add_property# $el"] + } + } + #add property + set inserpos [expr $prop_stop + -1] + set el_index -1 + foreach el $cname { + incr el_index + #ignore id and line_check + if {$el_index>1} { + set data [linsert $data[set data {}] $inserpos "$el \\"] + incr mod_count + } + } + } elseif {$all_props_removed>-1} { + #add removed items as comment after the component list + set inserpos [expr $all_props_removed + 1] + set el_index -1 + #add property as comment + foreach el $cname { + incr el_index + #ignore id and line_check + if {$el_index>1} { + set data [linsert $data[set data {}] $inserpos "# #TE_MOD#_add_property# $el"] + } + } + #add property + set inserpos [expr $all_props_removed + 1] + set el_index -1 + set data [linsert $data[set data {}] $inserpos " set_property -dict \[ list \\"] + incr inserpos + foreach el $cname { + incr el_index + #ignore id and line_check + if {$el_index>1} { + set data [linsert $data[set data {}] $inserpos "$el \\"] + incr inserpos + incr mod_count + } + } + set data [linsert $data[set data {}] $inserpos " \] \$[lindex $cname 1]"] + } + } + TE::UTILS::te_msg TE_UTIL-21 INFO "Block Design tcl: $mod_count properties were added." + return $data + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished modify block design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # generate workspace functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--workspace_info: + proc workspace_info {infofile info} { + set report_file ${infofile} + set fp_w [open ${report_file} "w"] + puts $fp_w "$info" + close $fp_w + } + #-------------------------------- + #--generate_workspace_hsi: + proc generate_workspace_hsi {{fname ""}} { + if {$fname eq ""} { + #use generated vivado data for workspace + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef]} { + file mkdir ${TE::WORKSPACE_HSI_PATH}/ + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef ${TE::WORKSPACE_HSI_PATH}/${TE::VPROJ_NAME}.hdf + # file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit ${TE::WORKSPACE_HSI_PATH} + workspace_info "${TE::WORKSPACE_PATH}/hsi_info.txt" "HSI Data used from ${TE::VPROJ_PATH}" + } else {TE::UTILS::te_msg TE_UTIL-23 WARNING "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef not found, HSI workspace was not generated."} + } else { + #use prebuilt data for workspace + set shortname "[TE::BDEF::find_shortdir $fname]" + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf]} { + file mkdir ${TE::WORKSPACE_HSI_PATH}/ + file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf ${TE::WORKSPACE_HSI_PATH}/${TE::VPROJ_NAME}.hdf + # file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.bit ${TE::WORKSPACE_HSI_PATH} + workspace_info "${TE::WORKSPACE_PATH}/hsi_info.txt" "HSI Data used from ${TE::PREBUILT_HW_PATH}/${shortname}" + } else {TE::UTILS::te_msg TE_UTIL-24 WARNING "${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf not found, HSI workspace was not generated."} + } + } + #-------------------------------- + #--generate_workspace_sdk: + proc generate_workspace_sdk {{fname ""}} { + #todo mal schauen ob vorher gelöcht werden muss oder ob überschreiben reicht + if {$fname eq ""} { + #use generated vivado data for workspace + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef]} { + file mkdir ${TE::WORKSPACE_SDK_PATH}/ + # file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + #use Toplevelname instead fo Project name -> export from Vivado GUI can used to + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef ${TE::WORKSPACE_SDK_PATH}/${TE::PR_TOPLEVELNAME}.hdf + # file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit ${TE::WORKSPACE_SDK_PATH} + workspace_info "${TE::WORKSPACE_PATH}/sdk_info.txt" "SDK Data used from ${TE::VPROJ_PATH}" + } else {TE::UTILS::te_msg TE_UTIL-25 WARNING "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef not found, SDK workspace was not generated."} + } else { + #use prebuilt data for workspace + set shortname "[TE::BDEF::find_shortdir $fname]" + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf]} { + file mkdir ${TE::WORKSPACE_SDK_PATH}/ + # file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + #use Toplevelname instead fo Project name -> export from Vivado GUI can used to + file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf ${TE::WORKSPACE_SDK_PATH}/${TE::VPROJ_NAME}.hdf + # file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf ${TE::WORKSPACE_SDK_PATH}/${TE::PR_TOPLEVELNAME}.hdf + # file copy -force ${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.bit ${TE::WORKSPACE_SDK_PATH} + workspace_info "${TE::WORKSPACE_PATH}/sdk_info.txt" "SDK Data used from ${TE::PREBUILT_HW_PATH}/${shortname}" + } else {TE::UTILS::te_msg TE_UTIL-26 WARNING "${TE::PREBUILT_HW_PATH}/${shortname}/${TE::VPROJ_NAME}.hdf not found, SDK workspace was not generated."} + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished generate workspace functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # copy files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--copy_hw_files: + proc copy_hw_files { {deleteOldFile true}} { + #make new one + file mkdir ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR} + if {${TE::PR_TOPLEVELNAME} eq "NA" } { + TE::UTILS::te_msg TE_UTIL-27 {CRITICAL WARNING} "Script variable TE::PR_TOPLEVELNAME was not set, script properties will be reload." + TE::VIV::restore_scriptprops + } + #copy files only if bitfiles exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit]} { + #delete old prebuilt bitfile + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit} result]} {TE::UTILS::te_msg TE_UTIL-28 {CRITICAL WARNING} " $result"} + } + #copy and rename bitfile + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit + TE::UTILS::te_msg TE_UTIL-29 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.bit was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit" + #-------------------------------- + #delete old prebuilt lpr + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.lpr] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.lpr} result]} {TE::UTILS::te_msg TE_UTIL-30 {CRITICAL WARNING} " $result"} + } + #copy and rename lpr + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.hw/${TE::VPROJ_NAME}.lpr ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.lpr + TE::UTILS::te_msg TE_UTIL-31 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.lpr was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.hw/${TE::VPROJ_NAME}.lpr" + #-------------------------------- + #delete old prebuilt ltx_file + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.ltx] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.ltx} result]} {TE::UTILS::te_msg TE_UTIL-32 {CRITICAL WARNING} " $result"} + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/debug_nets.ltx]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/debug_nets.ltx ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.ltx + TE::UTILS::te_msg TE_UTIL-33 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.ltx was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/debug_nets.ltx" + } else {TE::UTILS::te_msg TE_UTIL-34 INFO "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/debug_nets.ltx was not found."} + #delete old prebuilt hdf_file (hdf only on processor systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf} result]} {TE::UTILS::te_msg TE_UTIL-35 {CRITICAL WARNING} " $result"} + } + if {!$TE::IS_FSYS} { + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef]} { + #optional only on processor system: check bd file name --> for fsys no *hwdef and *sydef files needed + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf + TE::UTILS::te_msg TE_UTIL-35 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.hdf was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef" + } else {TE::UTILS::te_msg TE_UTIL-36 {CRITICAL WARNING} "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef was not found."} + } + #delete old prebuilt mmi (not for zynq systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mmi] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mmi} result]} {TE::UTILS::te_msg TE_UTIL-38 {CRITICAL WARNING} " $result"} + } + #delete old prebuilt mcs_file (not for zynq systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mcs] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mcs} result]} {TE::UTILS::te_msg TE_UTIL-39 {CRITICAL WARNING} " $result"} + } + #delete old prebuilt prm_file (not for zynq systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.prm] && $deleteOldFile } { + if {[catch {file delete -force ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.prm} result]} {TE::UTILS::te_msg TE_UTIL-40 {CRITICAL WARNING} " $result"} + } + #copy mmi + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mmi]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mmi ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mmi + TE::UTILS::te_msg TE_UTIL-41 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mmi was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mmi" + } else {TE::UTILS::te_msg TE_UTIL-42 WARNING "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mmi was not found."} + #copy mcs + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs]} { + #optional only on systems without processor used see TE::VIV::write_cfgmem for selection + #compare timestamps, if mcs is older than bitfile, rerun write mcs_file --> if gui is used to generate bitfile mcs will not recreate + set bittime [file mtime ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit] + set mcstime [file mtime ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs] + if {$mcstime < $bittime} { + TE::UTILS::te_msg TE_UTIL-43 INFO "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs is older as ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit . Regenerate mcs." + + if {[catch {TE::VIV::write_viv_cfgmem} result]} { TE::UTILS::te_msg TE_UTIL-44 ERROR "Script (TE::VIV::write_viv_cfgmem) failed: $result."; return -code error} + } + file mkdir ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.prm ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.prm + TE::UTILS::te_msg TE_UTIL-45 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.prm was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.prm" + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${TE::VPROJ_NAME}.mcs + TE::UTILS::te_msg TE_UTIL-46 INFO "${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports/${TE::VPROJ_NAME}.mcs was replaced with ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs" + } else {TE::UTILS::te_msg TE_UTIL-47 WARNING "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs was not found."} + + } else {TE::UTILS::te_msg TE_UTIL-48 {CRITICAL WARNING} "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit was not found. Nothing was copied to prebuilt folder."} + } + #-------------------------------- + #--copy_sw_files: + proc copy_sw_files {} { + set dirs [glob -directory $TE::WORKSPACE_HSI_PATH *] + if { [llength $dirs] >0} { + #make new one + file mkdir ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR} + #copy files + foreach dir $dirs { + if {[file exists $dir/executable.elf]} { + #apps+fsbl + set fname [file tail $dir] + #delete old prebuilt elf file + if {[file exists ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/${fname}.elf]} { + if {[catch {file delete -force ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/${fname}.elf} result]} {TE::UTILS::te_msg TE_UTIL-49 {CRITICAL WARNING} " $result"} + } + #copy file + file copy -force $dir/executable.elf ${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/${fname}.elf + TE::UTILS::te_msg TE_UTIL-50 INFO "${TE::PREBUILT_SW_PATH}/${TE::SHORTDIR}/${fname}.elf was replaced with $dir/executable.elf" + } elseif {[file exists $dir/skeleton.dtsi]} { + #device tree + set fname [file tail $dir] + set devtree_folder ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/${fname} + file mkdir ${devtree_folder} + if {[file exists ${devtree_folder}/skeleton.dtsi]} { + if {[catch {file delete -force ${devtree_folder}/skeleton.dtsi} result]} {TE::UTILS::te_msg TE_UTIL-51 {CRITICAL WARNING} " $result"} + } + if {[file exists ${devtree_folder}/system.dts]} { + if {[catch {file delete -force ${devtree_folder}/system.dts} result]} {TE::UTILS::te_msg TE_UTIL-52 {CRITICAL WARNING} " $result"} + } + if {[file exists ${devtree_folder}/zynq-7000.dtsi]} { + if {[catch {file delete -force ${devtree_folder}/zynq-7000.dtsi} result]} {TE::UTILS::te_msg TE_UTIL-53 {CRITICAL WARNING} " $result"} + } + file copy -force $dir/skeleton.dtsi ${devtree_folder}/skeleton.dtsi + file copy -force $dir/system.dts ${devtree_folder}/system.dts + file copy -force $dir/zynq-7000.dtsi ${devtree_folder}/zynq-7000.dtsi + TE::UTILS::te_msg TE_UTIL-54 INFO "Following device tree files are replaced \n \ + ${devtree_folder}/skeleton.dtsi was replaced with $dir/skeleton.dtsi \n \ + ${devtree_folder}/system.dts was replaced with $dir/system.dts \n \ + ${devtree_folder}/zynq-7000.dtsi was replaced with $dir/zynq-7000.dtsi \n \ + ------" + } + } + } else { + TE::UTILS::te_msg TE_UTIL-55 {CRITICAL WARNING} "$TE::WORKSPACE_HSI_PATH was empty. Nothing was copied to prebuilt folder." + } + } + #-------------------------------- + #--copy_hw_reports: + proc copy_hw_reports {} { + TE::UTILS::te_msg TE_UTIL-56 STATUS "Create reports in ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports" + file mkdir ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + #copy only if new bitfile exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit]} { + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc]} { + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc ${TE::PREBUILT_HW_PATH}/${TE::SHORTDIR}/reports + } + } + #create allways summary + create_prebuilt_hw_summary + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished copy files functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--create_prebuilt_hw_summary: + proc create_prebuilt_hw_summary {} { + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}_summary.csv + set prebuilt_file ${TE::PREBUILT_HW_PATH}/hardware_summary.csv + #todo hardware_summary.csv erase of to large + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + if { ![file exists ${prebuilt_file}]} { + set fp_w [open ${prebuilt_file} "w"] + puts $fp_w [lindex $data 0] + puts $fp_w [lindex $data 1] + close $fp_w + } else { + set fp_a [open ${prebuilt_file} "a"] + puts $fp_a [lindex $data 1] + close $fp_a + } + TE::UTILS::te_msg TE_UTIL-57 INFO "Add HW report to: ${TE::PREBUILT_HW_PATH}/hardware_summary.csv" + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # clear functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--clean_vivado_project: + proc clean_vivado_project {} { + if { [file exists $TE::VPROJ_PATH] } { + if {[catch {file delete -force $TE::VPROJ_PATH} result]} {TE::UTILS::te_msg TE_UTIL-59 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-56 INFO "$TE::VPROJ_PATH was deleted."} + } + } + #-------------------------------- + #--clean_labtools_project: + proc clean_labtools_project {} { + if { [file exists $TE::VLABPROJ_PATH] } { + if {[catch {file delete -force $TE::VLABPROJ_PATH} result]} {TE::UTILS::te_msg TE_UTIL-60 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-61 INFO "$TE::VLABPROJ_PATH was deleted."} + } + } + #-------------------------------- + #--clean_workspace_hsi: + proc clean_workspace_hsi {} { + if { [file exists ${TE::WORKSPACE_HSI_PATH}] } { + if {[catch {file delete -force $TE::WORKSPACE_HSI_PATH} result]} {TE::UTILS::te_msg TE_UTIL-62 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-63 INFO "$TE::WORKSPACE_HSI_PATH was deleted."} + } + } + #-------------------------------- + #--clean_workspace_sdk: + proc clean_workspace_sdk {} { + if { [file exists ${TE::WORKSPACE_SDK_PATH}] } { + if {[catch {file delete -force $TE::WORKSPACE_SDK_PATH} result]} {TE::UTILS::te_msg TE_UTIL-64 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-65 INFO "$TE::WORKSPACE_SDK_PATH was deleted."} + } + } + #-------------------------------- + #--clean_workspace_all: + proc clean_workspace_all {} { + if { [file exists ${TE::WORKSPACE_PATH}] } { + if {[catch {file delete -force $TE::WORKSPACE_PATH} result]} {TE::UTILS::te_msg TE_UTIL-66 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-67 INFO "$TE::WORKSPACE_PATH was deleted."} + } + } + #-------------------------------- + #--clean_sdsoc: + proc clean_sdsoc {} { + if { [file exists ${TE::SDSOC_PATH}] } { + if {[catch {file delete -force $TE::SDSOC_PATH} result]} {TE::UTILS::te_msg TE_UTIL-68 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-69 INFO "$TE::SDSOC_PATH was deleted."} + } + } + #-------------------------------- + #--clean_all_generated_files: + proc clean_all_generated_files {} { + clean_vivado_project + clean_labtools_project + clean_workspace_hsi + clean_workspace_sdk + clean_workspace_all + clean_sdsoc + TE::UTILS::te_msg TE_UTIL-71 INFO "Clean all generated files finished." + } + #-------------------------------- + #--clean_prebuilt_all: + proc clean_prebuilt_all {} { + if { [file exists ${TE::PREBUILT_PATH}] } { + if {[catch {file delete -force $TE::PREBUILT_PATH} result]} {TE::UTILS::te_msg TE_UTIL-70 {CRITICAL WARNING} " $result"} else {TE::UTILS::te_msg TE_UTIL-71 INFO "$TE::PREBUILT_PATH was deleted."} + } + } + #todo clean prebuilt single part -> bi hw ,sw, os + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + puts "INFO:(TE) Load Utilities script finished" +} + + diff --git a/zynqberrydemo3/scripts/script_usrcommands.tcl b/zynqberrydemo3/scripts/script_usrcommands.tcl new file mode 100644 index 0000000..a6b12a9 --- /dev/null +++ b/zynqberrydemo3/scripts/script_usrcommands.tcl @@ -0,0 +1,991 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/16 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/02/06 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +# source in namespace of TE +namespace eval TE { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # help functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--help: + proc help {{args ""}} { + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-help" { set run_help true; incr option } + + default {TE::UTILS::te_msg TE_UTIL-79 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Help: \n\ + Description:\n\ + \ Display currently available user functions\n\ + Syntax:\n\ + \ help \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE\n\ + " + TE::UTILS::te_msg TE_INIT-93 STATUS $te_txt + } else { + TE::INIT::print_version + set te_txt "TE Script Help:\n\ + Available TE-Functions:" + if {![catch {set projectname [get_projects]} result]} { + set te_txt "$te_txt\n\ + \ ---------------------------------\n\ + \ Beta Test (advanced usage only!):\n\ + \ TE::ADV::beta_util_sdsoc_project \[-check_only\] \[-start_sdsoc\] \[-help\]\n\ + \ TE::ADV::beta_hw_remove_board_part \[-permanent\] \[-help\]\n\ + \ TE::ADV::beta_hw_export_rtl_ip \[-help\]" + } + set te_txt "$te_txt\n\ + \ ----------\n\ + \ Utilities:\n\ + \ TE::util_zip_project \[-save_all\] \[-remove_prebuilt\] \[-manual_filename \] \[-help\]\n\ + \ ------------\n\ + \ Programming:\n\ + \ TE::pr_init_hardware_manager \[-help\]\n\ + \ TE::pr_program_jtag_bitfile \[-used_board \] \[-swapp \] \[-available_apps\] \[-used_basefolder_bitfile\] \[-help\]\n\ + \ TE::pr_program_flash_binfile \[-no_reboot\] \[-used_board \] \[-swapp \] \[-available_apps\] \[-force_hw_manager\] \[-used_basefolder_binfile\] \[-help\]\n\ + \ TE::pr_program_flash_mcsfile \[-no_reboot\] \[-used_board \] \[-swapp \] \[-available_apps\] \[-used_basefolder_mcsfile\] \[-help\]" + if {![catch {set projectname [get_projects]} result]} { + # # on vivado project + set te_txt "$te_txt\n\ + \ ----------\n\ + \ Software Design:\n\ + \ TE::sw_run_hsi \[-run_only\] \[-prebuilt_hdf \] \[-no_hsi\] \[-no_bif\] \[-no_bin\] \[-no_bitmcs\] \[-force_bin\] \[-clear\] \[-help\]\n\ + \ TE::sw_run_sdk \[-open_only\] \[-update_hdf_only\] \[-prebuilt_hdf \] \[-clear\] \[-help\]\n\ + \ ----------\n\ + \ Hardware Design:\n\ + \ TE::hw_blockdesign_create_bd \[-bd_name\] \[-msys_local_mem\] \[-msys_ecc\] \[-msys_cache\] \[-msys_debug_module\] \[-msys_axi_periph\] \[-msys_axi_intc\] \[-msys_clk\] \[-help\]\n\ + \ TE::hw_blockdesign_export_tcl \[-no_mig_contents\] \[-no_validate\] \[-mod_tcl\] \[-svntxt \] \[-board_part_only\] \[-help\]\n\ + \ TE::hw_build_design \[-disable_bitgen\] \[-disable_hdf\] \[-disable_mcsgen\] \[-disable_reports\] \[-export_prebuilt\] \[-export_prebuilt_only\] \[-help\]" + } + set te_txt "$te_txt\n\ + ------------------------------------------\n\ + Note:Run only predefined TE-functions from this list. Run other TE-functions directly may cause errors.\n\ + Note:For more Informations see Trenz Electronic Wiki: https://wiki.trenz-electronic.de/display/PD/Project+Delivery \n\ + ------------------------------------------\n\ + " + TE::UTILS::te_msg TE_INIT-94 STATUS $te_txt + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished help functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # hardware generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--hw_blockdesign_create_new_bd: + proc hw_blockdesign_create_bd {{args ""}} { + set bd_name "fsys" + set msys_local_mem "8KB" + set msys_ecc "None" + set msys_cache "None" + set msys_debug_module "Debug Only" + set msys_axi_periph "Enabled" + set msys_axi_intc "0" + set msys_clk "None" + + + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-bd_name" {incr option; set bd_name [lindex $args $option]} + "-help" {set run_help true} + default {TE::UTILS::te_msg TE_UTIL-80 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Create Block Design: \n\ + Description:\n\ + \ Create new Block Design with specified name. \n\ + \ Special Block Design names: \n\ + \ fsys -> used for FPGA-Fabric Design only. Generate empty Block Design. \n\ + \ msys -> used for Microblaze Design only. Generate Microblaze with defined parameters. \n\ + \ zsys -> used for 7Series Zynq Design only. Generate 7 Series Zynq with Board Part configuration and Carrier Board extended settings (if available). \n\ + \ zusys -> used for UltraScale Plus Zynq Design only. Generate UltraScale Plus Zynq with Board Part configuration and Carrier Board extended settings (if available). \n\ + Syntax:\n\ + \ TE::hw_blockdesign_create_bd \[-bd_name\] \[-msys_local_mem\] \[-msys_ecc\] \[-msys_cache\] \[-msys_debug_module\] \[-msys_axi_periph\] \[-msys_axi_intc\] \[-msys_clk\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-help\] Print help.\n\ + \ \[-bd_name\] Use one of the predefined names (def:fsys): fsys, msys, zsys, zusys \n\ + \ \[-msys_local_mem\] Use one of the predefined values(def:8KB): None, 4KB, 8KB, 16KB, 32KB, 64KB, 128KB \n\ + \ \[-msys_ecc\] Use one of the predefined values(def:None): None, Basic, Full \n\ + \ \[-msys_cache\] Use one of the predefined values(def:None): None, 4KB, 8KB, 16KB, 32KB, 64KB \n\ + \ \[-msys_debug_module\] Use one of the predefined values(def:Debug Only): None, Debug Only, \"Debug \& UART\", \"Extended Debug\" \n\ + \ \[-msys_axi_periph\] Use one of the predefined values(def:Enabled): Disabled, Enabled \n\ + \ \[-msys_axi_intc\] Use one of the predefined values(def:0): 0, 1 \n\ + \ \[-msys_clk\] Use one of the predefined values(def:None): None, \"New Clocking Wizard (100 MHz)\", \"New External Port (100 MHz)\" \n\ + Categories:\n\ + \ TE::VIV\n\ + " + TE::UTILS::te_msg TE_BD-19 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_BD-20 STATUS "Start Create Block Design." + # m_settings only used for msys + set m_settings {local_mem $msys_local_mem ecc $msys_ecc cache $msys_cache debug_module $msys_debug_module axi_periph $msys_axi_periph axi_intc $msys_axi_intc clk $msys_clk} + if {[catch {TE::VIV::create_new_blockdesign $bd_name $m_settings } result]} {TE::UTILS::te_msg TE_BD-21 ERROR "Script (TE::VIV::create_new_blockdesign) failed: $result."; return -code error} + TE::UTILS::te_msg TE_BD-22 STATUS "Create Block Design finished." + } + } + #-------------------------------- + #--hw_blockdesign_export_tcl: + proc hw_blockdesign_export_tcl {{args ""}} { + set no_mig "" + set no_validate "" + set boardpart_only "" + set mod_tcl "" + set svn_check false + set svn_msg "" + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-no_mig_contents" {set no_mig [lindex $args $option]} + "-mod_tcl" {set mod_tcl [lindex $args $option]} + "-no_validate" {set no_validate [lindex $args $option]} + "-svntxt" {incr option; set svn_check true; set svn_msg [lindex $args $option]} + "-board_part_only" {set boardpart_only [lindex $args $option]} + "-help" {set run_help true} + default {TE::UTILS::te_msg TE_UTIL-81 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Export Block Design: \n\ + Description:\n\ + \ Export Block Design as TCL-file. \n\ + \ File destination is $TE::BD_PATH or ${TE::BD_PATH}/${TE::SHORTDIR}/, if sub-folder exists. \n\ + \ If ${TE::BD_PATH}/${TE::SHORTDIR}/ exists, Block Designs from $TE::BD_PATH are ignored on project creation. \n\ + \ Attention: Open block-design will be saved automatically before export is run.\n\ + Syntax:\n\ + \ TE::hw_blockdesign_export_tcl \[-no_mig_contents\] \[-no_validate\] \[-mod_tcl\] \[-svntxt \] \[-board_part_only\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-no_mig_contents\] Vivado specific option when MIG is used: MIG-Configuration is excluded from TCL-File. Reference to mig.prj is used instead. Wrong usage will damaged design functionality!\n\ + \ \[-no_validate\] Design is saved without validation.\n\ + \ \[-board_part_only\] Export for this bord part only (tcl is stored in ${TE::BD_PATH}/${TE::SHORTDIR}/). \n\ + \ \[-mod_tcl\] TCL Content would be modified with content from $TE::BD_PATH\\mod_bd.tcl. If mod_bd.tcl don't exist or all commands inside are commented, nothing is changed. Wrong usage will damaged design functionality! \n\ + \ \[-svntxt \] Send svn commit with Text if SVN-versioning is used for the files in $TE::BD_PATH.\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VIV, TE::UTILS, TE::EXT\n\ + " + TE::UTILS::te_msg TE_BD-23 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_BD-24 STATUS "Start Export Block Design." + if {[catch {TE::VIV::export_blockdesign $no_mig $no_validate $boardpart_only $mod_tcl} result]} {TE::UTILS::te_msg TE_BD-24 ERROR "Script (TE::VIV::export_blockdesign) failed: $result."; return -code error} + if {$svn_check} { + if {[catch {TE::EXT::svn_checkin ${TE::BD_PATH} $svn_msg} result]} {TE::UTILS::te_msg TE_BD-25 ERROR "Script (TE::EXT::svn_checkin) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_BD-26 STATUS "Export Block Design finished." + } + } + #-------------------------------- + #--hw_build_design: + proc hw_build_design {{args ""}} { + set run_build true + set bitgen true + set mcsgen true + set reportgen true + set hdfgen true + set export_prebuild false + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-disable_bitgen" { set bitgen false} + "-disable_hdf" { set hdfgen false} + "-disable_mcsgen" { set mcsgen false} + "-disable_reports" { set reportgen false} + "-export_prebuilt_only" { set export_prebuild true; set run_build false} + "-export_prebuilt" { set export_prebuild true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-82 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Build Design: \n\ + Description:\n\ + \ Run Synthesises and Implementation with Bitstream generation. \n\ + \ Generate BIT-File on all BD-Names and MCS-File only on none Zynq/UltraScale Systems. \n\ + Syntax:\n\ + \ TE::hw_build_design \[-disable_bitgen\] \[-disable_hdf\] \[-disable_mcsgen\] \[-disable_reports\] \[-export_prebuilt\] \[-export_prebuilt_only\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-disable_bitgen\] Bit-File generation is disabled. \n\ + \ \[-disable_hdf\] HDF-File generation is disabled(delete *.sysdef). \n\ + \ \[-disable_mcsgen\] MCS-File generation for none Zynq/UltraScale Systems is disabled. \n\ + \ \[-disable_reports\] Report-Files generation for prebuilt folder is disabled. \n\ + \ \[-export_prebuilt\] Export generated HW-Files to the prebuilt folder (copy is done automatically, when hsi, sdk or jtag programming scripts starts in VIVADO). \n\ + \ \[-export_prebuilt_only\] Export generated HW-Files to the prebuilt folder without rebuild the design. \n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VIV,TE::UTILS\n\ + " + TE::UTILS::te_msg TE_HW-59 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_HW-60 STATUS "Start Build Design." + if {$run_build} { + if {[catch {TE::VIV::build_design $bitgen $mcsgen $reportgen $hdfgen} result]} {TE::UTILS::te_msg TE_HW-61 ERROR "Script (TE::VIV::build_design) failed: $result."; return -code error} + } + # copy is done if hsi, sdk or jtag programming is started or + if {$export_prebuild} { + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_HW-62 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_HW-63 INFO "No Hardware Reports found."} + } + TE::UTILS::te_msg TE_HW-64 STATUS "Build Design finished." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished hardware generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # software generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--sw_run_hsi: + proc sw_run_hsi {{args ""}} { + set run_help false + set run_copy true + set run_clear false + set run_prebuilt false + set run_prebuilt_hdf_only false + set run_hsi true + set run_bif true + set run_bin true + set force_bin false + set run_bitmcs true + set prebuilt_name "" + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-run_only" { set run_copy false} + "-prebuilt_hdf" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-prebuilt_hdf_only" { incr option; set run_prebuilt_hdf_only true; set prebuilt_name [lindex $args $option]} + "-no_hsi" { set run_hsi false} + "-no_bif" { set run_bif false} + "-no_bin" { set run_bin false} + "-no_bitmcs" { set run_bitmcs false} + "-force_bin" { set force_bin true} + "-clear" { set run_clear true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-83 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Run HSI: \n\ + Description:\n\ + \ Start HSI and create all software apps (*elf) and corresponding boot.bif and boot.bin (for Zynq/UZynq only) or .bit and .mcs (for MicroBlaze only), which are specified in apps_list.csv\n\ + \ Copy HW File and reports from the vivado project to the prebuilt folder if -prebuild_hdf isn't set (default)\n\ + \ *.hdef and *.sysdef are ignored if BD-Name is fsys (Without processor system). \n\ + \ Attention: Need SDK installation! \n\ + Syntax:\n\ + \ TE::sw_run_hsi \[-run_only\] \[-prebuilt_hdf \] \[-no_hsi\] \[-no_bif\] \[-no_bin\] \[-no_bitmcs\] \[-clear\] \[-help\]\n\ + Returns:\n\ + No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-prebuilt_hdf \] used *.bit and *.hdf from prebuilt folder instead of vivado project. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used. \n\ + \ \[-run_only\] used old data in workspace (*.bit and *.hdf)\n\ + \ \[-no_hsi\] disable *.elf generation\n\ + \ \[-no_bif\] disable boot.bif generation (for Zynq System only)\n\ + \ \[-no_bin\] disable boot.bin generation (for Zynq System only)\n\ + \ \[-force_bin\] disabllefor Zynq check for bif and bin generation\n\ + \ \[-no_bitmcs\] disable {appname}.bit and .mcs (for MicroBlaze System only) generation\n\ + \ \[-clear\] delete old data before workspace is created\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::UTILS, TE::EXT\n\ + " + TE::UTILS::te_msg TE_SW-39 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_SW-40 STATUS "Start HSI." + if {$run_clear} { + if {[catch {TE::UTILS::clean_workspace_hsi} result]} {TE::UTILS::te_msg TE_SW-41 ERROR "Script (TE::UTILS::clean_workspace_hsi) failed: $result."; return -code error} + } + + if {$run_hsi} { + if {$run_copy} { + if {$run_prebuilt} { + if {[catch {TE::UTILS::generate_workspace_hsi $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-42 ERROR "Script (TE::UTILS::generate_workspace_hsi) failed: $result."; return -code error} + } elseif {$run_prebuilt_hdf_only} { + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_SW-43 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_SW-44 INFO "No Hardware Reports found. "} + if {[catch {TE::UTILS::generate_workspace_hsi $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-45 ERROR "Script (TE::UTILS::generate_workspace_hsi) failed: $result."; return -code error} + } else { + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_SW-46 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_SW-47 INFO "No Hardware Reports found. "} + if {[catch {TE::UTILS::generate_workspace_hsi} result]} {TE::UTILS::te_msg TE_SW-48 ERROR "Script (TE::UTILS::generate_workspace_hsi) failed: $result."; return -code error} + } + } + if {[catch {TE::EXT::run_hsi} result]} {TE::UTILS::te_msg TE_SW-49 ERROR "Script (TE::EXT::run_hsi) failed: $result."; return -code error} + } + if {$TE::IS_ZSYS || $TE::IS_ZUSYS || $force_bin} { + #.bif and .bin only on zynq systems + if {$run_bif} { + if {[catch {TE::EXT::generate_bif_files $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-50 ERROR "Script (TE::EXT::generate_bif_files) failed: $result."; return -code error} + } + if {$run_bin} { + if {[catch {TE::EXT::generate_bootbin $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-51 ERROR "Script (TE::EXT::generate_bootbin) failed: $result."; return -code error} + } + } elseif {$TE::IS_MSYS} { + if {$run_bitmcs} { + if {[catch {TE::EXT::generate_app_bit_mcs $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-52 ERROR "Script (TE::EXT::generate_app_bit_mcs) failed: $result."; return -code error} + } + } else { + set te_txt "Boot.bif and Boot.bin only for Zynq-FPGAs available. .bit and .mcs only for MicroBlaze available. System will be checked with block design name, current BD file name is $TE::BD_TCLNAME .Use:\n\ + \ \"zsys_bd.tcl\" for Systems with Zynq \n\ + \ \"zusys_bd.tcl\" for Systems with UltraScale Zynq\n\ + \ \"msys_bd.tcl\" for Systems with MicroBlaze\n\ + \ \"fsys_bd.tcl\" for Systems with FPGA-Fabric design only\n\ + " + TE::UTILS::te_msg TE_SW-53 INFO $te_txt + } + TE::UTILS::te_msg TE_SW-54 STATUS "HSI finished." + } + } + #-------------------------------- + #--sw_run_sdk: + proc sw_run_sdk {{args ""}} { + set run_help false + set run_copy true + set start_sdk true + set run_clear false + set run_prebuilt false + set prebuilt_name "" + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-open_only" { set run_copy false} + "-update_hdf_only" { set start_sdk false} + "-prebuilt_hdf" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-clear" { set run_clear true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-84 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Run SDK: \n\ + Description:\n\ + \ Start SDK project in external folder $TE::WORKSPACE_SDK_PATH\n\ + \ Copy HW File and reports from the vivado project to the prebuilt folder if -prebuild_hdf isn't set (default)\n\ + \ *.hdef and *.sysdef are ignored if BD-Name is fsys (Without processor system). \n\ + \ Attention: If you use VIVADO GUI Command (File->Export-> Export Hardware..(Include Bit-file!) or File->Launch SDK) to Update or open SKD set new export path and workspace: $TE::WORKSPACE_SDK_PATH\n\ + \ Attention: Need SDK installation! \n\ + Syntax:\n\ + \ TE::sw_run_sdk \[-open_only\] \[-update_hdf_only\] \[-prebuilt_hdf \] \[-clear\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-prebuilt_hdf \] used *.hdf from prebuilt folder instead of vivado project. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used. \n\ + \ \[-open_only\] open SDK without update the *.hdf file \n\ + \ \[-update_hdf_only\] copy the new *.hdf file into the SDK workspace without open SDK\n\ + \ \[-clear\] delete old data before workspace is created\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::UTILS, TE::EXT\n\ + " + TE::UTILS::te_msg TE_SW-55 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_SW-56 STATUS "Start SDK" + if {$run_clear} { + if {[catch {TE::UTILS::clean_workspace_sdk} result]} {TE::UTILS::te_msg TE_SW-57 ERROR "Script (TE::UTILS::clean_workspace_sdk) failed: $result."; return -code error} + } + if {$run_copy} { + if {$run_prebuilt} { + if {[catch {TE::UTILS::generate_workspace_sdk $prebuilt_name} result]} {TE::UTILS::te_msg TE_SW-58 ERROR "Script (TE::UTILS::generate_workspace_sdk) failed: $result."; return -code error} + } else { + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_SW-59 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_SW-60 INFO "No Hardware Reports found."} + if {[catch {TE::UTILS::generate_workspace_sdk} result]} {TE::UTILS::te_msg TE_SW-61 ERROR "Script (TE::UTILS::generate_workspace_sdk) failed: $result."; return -code error} + } + } + if {$start_sdk} { + if {[catch {TE::EXT::run_sdk} result]} {TE::UTILS::te_msg TE_SW-62 ERROR "Script (TE::EXT::run_sdk) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_SW-63 STATUS "SDK finished." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished software generation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--pr_program_flash_binfile: + proc pr_program_flash_binfile {{args ""}} { + set return_filename "" + set use_basefolder false + set use_sdk_flash true + set run_help false + set run_prebuilt false + set appname "" + set prebuilt_name "" + set print_available_apps false + set reboot true + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-no_reboot" { set reboot false} + "-used_board" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-swapp" { incr option; set appname [lindex $args $option]} + "-available_apps" { set print_available_apps true} + "-force_hw_manager" { set use_sdk_flash false} + "-used_basefolder_binfile" {set use_basefolder true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-85 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Program Flash with Bin-File: \n\ + Description:\n\ + \ Programming specified FPGA-Flash with bin-file (Zynq-Processors only).\n\ + \ It will be program the boot.bin from the corresponding prebuilt folder, which is set in the vivado project, if -used_board isn't set.\n\ + Syntax:\n\ + \ TE::pr_program_flash_binfile \[-no_reboot\] \[-used_board \] \[-swapp \] \[-available_apps\] \[-used_basefolder_binfile\] \[-help\]\n\ + Returns:\n\ + \ Programming file-name.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-no_reboot\] Memory will be only configured, no JTag reboot is done.\n\ + \ \[-used_board \] Used prebuilt folder board version instead of Vivado project settings. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used.\n\ + \ \[-swapp \] Software APP name which should be programmed.\n\ + \ \[-available_apps\] Return available software APP names from selected the prebuilt boot_images folder.\n\ + \ \[-force_hw_manager\] Force LabTools Hardware-Manager instead of SDK-Programmer. Boot.bin can be configured via SDK-Programmer or LabTools Hardware-Manager. If both available SDK-Programmer is used default. \n\ + \ \[-used_basefolder_binfile\] Use base-folder bin-file ($TE::BASEFOLDER). Should be only one *.bin!\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::EXT, TE::VLAB\n\ + " + TE::UTILS::te_msg TE_PR-43 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_PR-44 STATUS "Start Flash Programming with BIN File" + set starttime [clock seconds] + if {$print_available_apps} { + if {[catch {TE::EXT::get_available_apps $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-45 ERROR "Script (TE::EXT::get_available_apps) failed: $result."; return -code error} + } else { + if {$appname eq ""} {TE::UTILS::te_msg TE_PR-46 ERROR "No APP name is selected see \[pr_program_flash_binfile -help\]: $result."; return -code error} + if {$prebuilt_name ne ""} { + set id "[TE::BDEF::find_id $prebuilt_name]" + set zynqflashtyp_int [TE::BDEF::get_zynqflashtyp $id 0] + } else { + set zynqflashtyp_int $TE::ZYNQFLASHTYP + } + + set check_zynqflash false + if {$zynqflashtyp_int ne "NA"} { + set check_zynqflash true + } + + if {$::env(SDK_AVAILABLE) && $check_zynqflash && $use_sdk_flash} { + if {[catch {set return_filename [TE::EXT::excecute_zynq_flash_programming $use_basefolder $appname $prebuilt_name]} result]} {TE::UTILS::te_msg TE_PR-47 ERROR "Script (TE::EXT::excecute_zynq_flash_programming) failed: $result."; return -code error} + if {$reboot} { + set hw_close true + if {[catch {set hw_close [TE::VLAB::hw_open_jtag]} result]} {TE::UTILS::te_msg TE_PR-48 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + if {[catch {TE::VLAB::hw_fpga_boot_from_memory $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-49 ERROR "Script (TE::VLAB::hw_fpga_boot_from_memory) failed: $result."; return -code error} + if {$hw_close} { + if {[catch {TE::VLAB::hw_close_jtag} result]} {TE::UTILS::te_msg TE_PR-50 ERROR "Script (TE::VLAB::hw_close_jtag) failed: $result."; return -code error} + } + } + } else { + set hw_close true + if {[catch {set hw_close [TE::VLAB::hw_open_jtag]} result]} {TE::UTILS::te_msg TE_PR-51 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + + if {[catch {TE::VLAB::hw_create_flash_device $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-52 ERROR "Script (TE::VLAB::hw_create_flash_device) failed: $result."; return -code error} + if {[catch {set return_filename [TE::VLAB::hw_program_fpga_flash $use_basefolder "" bin $appname $prebuilt_name]} result]} {TE::UTILS::te_msg TE_PR-53 ERROR "Script (TE::VLAB::hw_program_fpga_flash) failed: $result."; return -code error} + + if {$reboot} { + if {[catch {TE::VLAB::hw_fpga_boot_from_memory $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-54 ERROR "Script (TE::VLAB::hw_fpga_boot_from_memory) failed: $result."; return -code error} + } + if {$hw_close} { + if {[catch {TE::VLAB::hw_close_jtag} result]} {TE::UTILS::te_msg TE_PR-55 ERROR "Script (TE::VLAB::hw_close_jtag) failed: $result."; return -code error} + } + } + } + set stoptime [clock seconds] + set timeelapsed [expr $stoptime -$starttime] + TE::UTILS::te_msg TE_PR-56 INFO "Programming elapsed time: $timeelapsed seconds" + TE::UTILS::te_msg TE_PR-57 STATUS "Flash Programming with BIN File finished" + } + return $return_filename + } + #-------------------------------- + #--pr_program_flash_mcsfile: + proc pr_program_flash_mcsfile {{args ""}} { + set return_filename "" + set run_help false + set run_prebuilt false + set appname "" + set prebuilt_name "" + set print_available_apps false + set reboot true + set term "pull-none" + set use_basefolder false + #pull-none (default)#pull-up #pull-down + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-no_reboot" { set reboot false} + "-used_board" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-unused_io_termination" { incr option; set term [lindex $args $option]} + "-swapp" { incr option; set appname [lindex $args $option]} + "-available_apps" { set print_available_apps true} + "-used_basefolder_mcsfile" {set use_basefolder true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-86 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Program Flash with MCS File: \n\ + Description:\n\ + \ Programming specified FPGA-Flash with mcs-File (No Zynq-Processors only).\n\ + \ It will be program the .mcs from the corresponding prebuilt folder which is set in the vivado/labtool project, if -used_board isn't set. \n\ + Syntax:\n\ + \ TE::pr_program_flash_mcsfile \[-no_reboot\] \[-used_board \] \[-unused_io_termination \] \[-swapp \] \[-available_apps\] \[-used_basefolder_mcsfile\] \[-help\]\n\ + Returns:\n\ + \ Programming file-name.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-no_reboot\] Memory will be only configured, no JTag reboot is done.\n\ + \ \[-used_board \] Used prebuilt folder board version instead of vivado project settings. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used.\n\ + \ \[-unused_io_termination \] Set termination for unused Device IO-Pins Available Settings are: pull-none, pull-up or pull-down. Default pull-none is used.\n\ + \ \[-swapp \] Software app name which should be programmed(If app name isn't set, the mcs-file from the prebuilt hardware folder is used). \n\ + \ \[-available_apps\] Return available software app names from selected the prebuilt boot_images folder.\n\ + \ \[-used_basefolder_mcsfile\] Use base-folder mcs-file ($TE::BASEFOLDER). Should be only one *.mcs!\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::EXT, TE::VLAB\n\ + " + TE::UTILS::te_msg TE_PR-58 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_PR-59 STATUS "Start Flash Programming with BIN File" + set starttime [clock seconds] + if {$print_available_apps} { + if {[catch {TE::EXT::get_available_apps $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-60 ERROR "Script (TE::EXT::get_available_apps) failed: $result."; return -code error} + } else { + if {!$run_prebuilt} { + if {![catch {set projectname [get_projects]} result]} { + #copy only on vivado project + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_PR-61 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_PR-62 INFO "No Hardware Reports found."} + } + } + set hw_close true + if {[catch {set hw_close [TE::VLAB::hw_open_jtag]} result]} {TE::UTILS::te_msg TE_PR-63 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + + if {[catch {TE::VLAB::hw_create_flash_device $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-64 ERROR "Script (TE::VLAB::hw_create_flash_device) failed: $result."; return -code error} + if {[catch {set return_filename [TE::VLAB::hw_program_fpga_flash $use_basefolder $term mcs $appname $prebuilt_name]} result]} {TE::UTILS::te_msg TE_PR-65 ERROR "Script (TE::VLAB::hw_program_fpga_flash) failed: $result."; return -code error} + + if {$reboot} { + if {[catch {TE::VLAB::hw_fpga_boot_from_memory $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-66 ERROR "Script (TE::VLAB::hw_fpga_boot_from_memory) failed: $result."; return -code error} + } + if {$hw_close} { + if {[catch {TE::VLAB::hw_close_jtag} result]} {TE::UTILS::te_msg TE_PR-67 ERROR "Script (TE::VLAB::hw_close_jtag) failed: $result."; return -code error} + } + } + set stoptime [clock seconds] + set timeelapsed [expr $stoptime -$starttime] + TE::UTILS::te_msg TE_PR-68 INFO "Programming elapsed time: $timeelapsed seconds" + TE::UTILS::te_msg TE_PR-69 STATUS "Flash Programming with BIN File finished." + } + return $return_filename + } + #-------------------------------- + #--pr_program_jtag_bitfile: + proc pr_program_jtag_bitfile {{args ""}} { + set return_filename "" + set print_available_apps false + set run_help false + set run_prebuilt false + set use_basefolder false + set prebuilt_name "" + set appname "" + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-used_board" { incr option; set run_prebuilt true; set prebuilt_name [lindex $args $option]} + "-swapp" { incr option; set appname [lindex $args $option]} + "-available_apps" { set print_available_apps true} + "-used_basefolder_bitfile" {set use_basefolder true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-87 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Program FPGA with Bit File: \n\ + Description:\n\ + \ Programming FPGA with BIT-File.\n\ + \ Copy HW File and reports from the Vivado project to the prebuilt folder, if -used_board isn't set (default)\n\ + Syntax:\n\ + \ TE::pr_program_jtag_bitfile \[-used_board \] \[-used_basefolder_bitfile\] \[-help\]\n\ + Returns:\n\ + \ Programming file-name.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-used_board \] Used prebuilt folder board version instead of vivado project settings. Available is ID,PRODID,BOARDNAME or SHORTNAME from TExxxx_board_file.csv list. If name not found, \"default\" is used.\n\ + \ \[-swapp \] Software app name which should be programmed. (If app name isn't set, the bit-file from the prebuilt hardware folder is used)\n\ + \ \[-available_apps\] Return available software app names from selected the prebuilt boot_images folder.\n\ + \ \[-used_basefolder_bitfile\] Use base-folder bit-file ($TE::BASEFOLDER). Should be only one *.bit!\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VLAB\n\ + " + TE::UTILS::te_msg TE_PR-70 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_PR-71 STATUS "Start FPGA Programming with Bit File" + set starttime [clock seconds] + if {$print_available_apps} { + if {[catch {TE::EXT::get_available_apps $prebuilt_name} result]} {TE::UTILS::te_msg TE_PR-72 ERROR "Script (TE::EXT::get_available_apps) failed: $result."; return -code error} + } else { + if {!$run_prebuilt} { + if {![catch {set projectname [get_projects]} result]} { + #copy only on vivado project + if {[catch {TE::UTILS::copy_hw_files $TE::GEN_HW_DELETEOLDFILES} result]} {TE::UTILS::te_msg TE_PR-73 ERROR "Script (TE::UTILS::copy_hw_files) failed: $result."; return -code error} + if {[catch {TE::UTILS::copy_hw_reports} result]} {TE::UTILS::te_msg TE_PR-74 INFO "No Hardware Reports found. "} + } + } + set hw_wasclosed false + if {[current_hw_server] eq ""} {set hw_wasclosed true} + if {[catch {TE::VLAB::hw_open_jtag} result]} {TE::UTILS::te_msg TE_PR-75 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + if {[catch {set return_filename [TE::VLAB::hw_program_fpga_device $use_basefolder $appname $prebuilt_name]} result]} {TE::UTILS::te_msg TE_PR-76 ERROR "Script (TE::VLAB::hw_program_fpga_device) failed: $result."; return -code error} + if {$hw_wasclosed} { + if {[catch {TE::VLAB::hw_close_jtag} result]} {TE::UTILS::te_msg TE_PR-77 ERROR "Script (TE::VLAB::hw_close_jtag) failed: $result."; return -code error} + } + } + set stoptime [clock seconds] + set timeelapsed [expr $stoptime -$starttime] + TE::UTILS::te_msg TE_PR-78 INFO "Programming elapsed time: $timeelapsed seconds" + TE::UTILS::te_msg TE_PR-79 STATUS "FPGA Programming with BIT File finished." + } + return $return_filename + } + #-------------------------------- + #--pr_init_hardware_manager: + proc pr_init_hardware_manager {{args ""}} { + set run_help false + set run_prebuilt false + set prebuilt_name "" + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-88 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Initialise Hardware Manager: \n\ + Description:\n\ + \ Open Hardware-Manager, auto-connect target device and initialise flash memory with configuration from *_board_files.csv.\n\ + \ If flash memory isn't specified, it will be ignored. \n\ + Syntax:\n\ + \ TE::pr_init_hardware_manager \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VLAB\n\ + " + TE::UTILS::te_msg TE_PR-80 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_PR-81 STATUS "Start Init Hardware Manager" + if {[catch {TE::VLAB::hw_open_jtag} result]} {TE::UTILS::te_msg TE_PR-82 ERROR "Script (TE::VLAB::hw_open_jtag) failed: $result."; return -code error} + if {${TE::FPGAFLASHTYP} ne "NA"} { + if {[catch {TE::VLAB::hw_create_flash_device} result]} {TE::UTILS::te_msg TE_PR-83 ERROR "Script (TE::VLAB::hw_create_flash_device) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_PR-84 STATUS "Initialise Hardware Manager finished." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # utilities functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--util_zip_project: + proc util_zip_project {{args ""}} { + set run_help false + set manual_name false + set tmp [split $TE::SHORTDIR "_"] + set zipname "" + + #settings + set remove_prebuilt false + set save_all false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-manual_filename" { incr option; set zipname [lindex $args $option];set manual_name true} + "-remove_prebuilt" { set remove_prebuilt true} + "-save_all" { set save_all true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-89 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {!$manual_name} { + #boardname + set zipname [lindex $tmp 0] + #projectname + set zipname "${zipname}-${TE::VPROJ_NAME}" + if {$remove_prebuilt} { + set zipname "${zipname}_noprebuilt" + } + if {$save_all} { + set zipname "${zipname}_all" + } + #vivado version + set zipname "${zipname}-vivado_$::env(VIVADO_VERSION)" + #Scipt version (last id) + set tmp [split $TE::SCRIPTVER "."] + set scriptver [lindex $tmp [expr [llength $tmp]-1]] + set zipname "${zipname}-build_${scriptver}" + #timestamp + set date "[ clock format [clock seconds] -format "%Y%m%d%H%M%S"]" + set zipname "${zipname}_${date}" + } + if {$run_help} { + set te_txt "TE Script Backup Project: \n\ + Description:\n\ + \ Generate Zip file from current project in folder $TE::BACKUP_PATH.\n\ + \ Supported ZIP-Programs:7z.exe (7 zip) and zip.exe (Info ZIP) \n\ + \ Did not save files, which are specified in /settings/zip_ignore_list.csv.\n\ + Syntax:\n\ + \ TE::util_zip_project \[-save_all\] \[-remove_prebuilt\] \[-manual_filename \] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-manual_filename \] Specify name instead auto-generate name.\n\ + \ \[-remove_prebuilt\] Save backup without prebuilt(Command is ignored if -save_all is selected).\n\ + \ \[-save_all\] Save all, otherwise work path like vivado, workspace, vlog and other specified folders/files are excluded.\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::EXT\n\ + " + TE::UTILS::te_msg TE_UTIL-95 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_UTIL-96 STATUS "Start Backup Project:" + if {$save_all} { + if {[catch {TE::EXT::zip_project $zipname} result]} {TE::UTILS::te_msg TE_UTIL-97 ERROR "Script (TE::EXT::zip_project) failed: $result."; return -code error} + } else { + #default list for old projects: + set excludelist "vivado vivado_lab workspace v_log run_prebuilt_all.cmd block_design/mod_bd.csv scripts/.svn sdsoc settings/development_settings.tcl" + #read ignore list from file + if {[llength $TE::ZIP_IGNORE_LIST] > 0} { + set excludelist [] + foreach entry $TE::ZIP_IGNORE_LIST { + if {[lindex $entry 0]==0} { + #only id0 objects + lappend excludelist [lindex $entry 1] + } elseif {[lindex $entry 0]==1} { + #only id1 objects + set find [] + catch {set find [glob -join -dir $TE::BASEFOLDER [lindex $entry 1]]} + foreach el $find { + set sl_start [expr [string length $TE::BASEFOLDER]+1] + set sl_stop [string length $el] + lappend excludelist [string range $el $sl_start $sl_stop] + } + } + } + } + if {$remove_prebuilt} { + lappend excludelist "prebuilt" + } + if {[catch {TE::EXT::zip_project $zipname $excludelist} result]} {TE::UTILS::te_msg UTIL-98 ERROR " Script (TE::EXT::zip_project) failed: $result."; return -code error} + } + TE::UTILS::te_msg UTIL-99 STATUS "Backup Project finished." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished utilities functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # beta test functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + namespace eval ADV { + #-------------------------------- + #--beta_util_sdsoc_project: + proc beta_util_sdsoc_project {{args ""}} { + set run_help false + set start_sdsoc false + set check_sdsoc false + + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-check_only" { set check_sdsoc true} + "-start_sdsoc" { set start_sdsoc true} + "-help" { set run_help true} + default {TE::UTILS::te_msg TE_UTIL-90 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + + if {$run_help} { + set te_txt "TE Script SDSoC Project: \n\ + Description:\n\ + \ Generate SDSoC project structure in $TE::SDSOC_PATH.\n\ + \ 7-ZIP-Program is required (see design_basic_settings.cmd).\n\ + \ Attention: This Project will be modified! To restore, close this Project after SDSOC generation an run create project batch file.\n\ + Syntax:\n\ + \ TE::ADV::beta_util_sdsoc_project \[-check_only\] \[-start_sdsoc\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-check_only\] Check this project for SDSOC support (no modification are done).\n\ + \ \[-start_sdsoc\] Start SDSOC with workspace: $TE::SDSOC_PATH.\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::SDSOC, TE::EXT\n\ + " + TE::UTILS::te_msg TE_HW-65 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_HW-66 STATUS "Start SDSoC Project:" + if {$check_sdsoc} { + if {[catch {TE::SDSOC::check_and_modify_vivado_project true} result]} {TE::UTILS::te_msg TE_HW-67 ERROR "Script (TE::SDSOC::check_and_modify_vivado_project) failed: $result."; return -code error} + } elseif {$start_sdsoc} { + if {[catch {TE::EXT::run_sdsoc} result]} {TE::UTILS::te_msg TE_HW-68 ERROR "Script (TE::EXT::run_sdsoc) failed: $result."; return -code error} + } else { + if {[catch {TE::SDSOC::create_sdsoc_structure} result]} {TE::UTILS::te_msg TE_HW-69 ERROR "Script (TE::SDSOC::create_sdsoc_structure) failed: $result."; return -code error} + if {[catch {TE::SDSOC::check_and_modify_vivado_project false} result]} {TE::UTILS::te_msg TE_HW-70 ERROR "Script (TE::SDSOC::check_and_modify_vivado_project) failed: $result."; return -code error} + #todo rebuild project files + if {[catch {TE::SDSOC::export_vivado_sdsoc_project} result]} {TE::UTILS::te_msg TE_HW-71 ERROR "Script (TE::SDSOC::export_vivado_sdsoc_project) failed: $result."; return -code error} + if {[catch {TE::SDSOC::create_sdsoc_pfm} result]} {TE::UTILS::te_msg TE_HW-72 ERROR "Script (TE::SDSOC::create_sdsoc_pfm) failed: $result."; return -code error} + } + TE::UTILS::te_msg TE_HW-73 STATUS "SDSoC Project finished." + } + } + #-------------------------------- + #--beta_hw_remove_board_part + proc beta_hw_remove_board_part {{args ""}} { + set temp_only true + set run_help false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-permanent" {set temp_only false} + "-help" {set run_help true} + default {TE::UTILS::te_msg TE_UTIL-91 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Remove Board part: \n\ + Description:\n\ + \ Remove board part from project.\n\ + \ Attention:\n\ + \ Function not supported for all Block-Design IPs.\n\ + \ Check design after automatically modifications are done!\n\ + \ To restore project after permanent modification do:\n\ + \ Delete ${TE::BD_PATH}/*.tcl.\n\ + \ Rename ${TE::BD_PATH}/*.tcl_backup into ${TE::BD_PATH}/*.tcl.\n\ + \ Delete ${TE::BOARDDEF_PATH}/*_board_files_mod.csv.\n\ + Syntax:\n\ + \ TE::ADV::beta_hw_remove_board_part \[-permanent\] \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-permanent\] Board Part is removed permanently for this vivado project.TCL-File is generated and alternative board_part.cvs is used on design creation.\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VIV, TE::UTILS\n\ + " + TE::UTILS::te_msg TE_HW-74 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_HW-75 STATUS "Start Remove Board Part:" + if {[catch {TE::VIV::design_exclude_boarddef $temp_only} result]} {TE::UTILS::te_msg TE_HW-76 ERROR "Script (TE::VIV::design_exclude_boarddef) failed: $result."; return -code error} + TE::UTILS::te_msg TE_HW-77 STATUS "Remove Board Part finished." + } + } + #-------------------------------- + #--beta_hw_export_rtl_ip + proc beta_hw_export_rtl_ip {{args ""}} { + set run_help false + set board_part_only false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-help" {set run_help true} + default {TE::UTILS::te_msg TE_UTIL-92 ERROR "Unrecognised option: [lindex $args $option]."; set run_help true;break } + } + } + if {$run_help} { + set te_txt "TE Script Remove Board part: \n\ + Description:\n\ + \ Export RTL-IP Cores (*.xci), which are not included in a Block-Design to ${TE::HDL_PATH}/xci/${TE::SHORTDIR}.\n\ + \ HDL and *.xci files, which include in the folder $TE::HDL_PATH are load automatically on project creation.\n\ + Syntax:\n\ + \ TE::ADV::beta_hw_export_rtl_ip \[-help\]\n\ + Returns:\n\ + \ No return value.\n\ + Usage:\n\ + \ Name Description\n\ + \ -------------------------\n\ + \ \[-help\] Print help.\n\ + Categories:\n\ + \ TE::VIV, TE::UTILS\n\ + " + TE::UTILS::te_msg TE_HW-78 STATUS $te_txt + } else { + TE::UTILS::te_msg TE_HW-79 STATUS "Start Export RTL-IPs:" + if {[catch {TE::VIV::export_xci} result]} {TE::UTILS::te_msg TE_HW-80 ERROR "Script (TE::VIV::export_xci) failed: $result."; return -code error} + TE::UTILS::te_msg TE_HW-81 STATUS "Export RTL-IPs finished." + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished beta test functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + puts "INFO:(TE) Load User Command scripts finished" +} \ No newline at end of file diff --git a/zynqberrydemo3/scripts/script_vivado.tcl b/zynqberrydemo3/scripts/script_vivado.tcl new file mode 100644 index 0000000..78317ca --- /dev/null +++ b/zynqberrydemo3/scripts/script_vivado.tcl @@ -0,0 +1,1556 @@ +# -------------------------------------------------------------------- +# -- ***************************** +# -- * Trenz Electronic GmbH * +# -- * Holzweg 19A * +# -- * 32257 Bünde * +# -- * Germany * +# -- ***************************** +# -------------------------------------------------------------------- +# --$Autor: Hartfiel, John $ +# --$Email: j.hartfiel@trenz-electronic.de $ +# --$Create Date:2016/02/03 $ +# --$Modify Autor: Hartfiel, John $ +# --$Modify Date: 2017/04/13 $ +# -------------------------------------------------------------------- +# -------------------------------------------------------------------- +namespace eval TE { + namespace eval VIV { + + # ------------------------------------------------------- + # ----advanced functions are currently official not supported + # ------------------------------------------------------- + #-------------------------------- + #--export_vivado_setting: + proc export_vivado_setting {} { + # hidden function: official not supported + set old_file_data "" + if {![file exists $TE::SET_PATH]} { + file mkdir ${TE::SET_PATH}/ + } elseif {[file exists ${TE::SET_PATH}/project_settings.tcl]} { + # additional project settings + set fp_r [open ${TE::SET_PATH}/project_settings.tcl "r"] + set old_file_data [read $fp_r] + close $fp_r + } + set fp_w [open ${TE::SET_PATH}/project_settings.tcl "w"] + + puts $fp_w "##############################" + puts $fp_w "# --------------------------------------------------------------------" + puts $fp_w "# -- ***************************** " + puts $fp_w "# -- * Trenz Electronic GmbH * " + puts $fp_w "# -- * Holzweg 19A * " + puts $fp_w "# -- * 32257 Bünde * " + puts $fp_w "# -- * Germany * " + puts $fp_w "# -- ***************************** " + puts $fp_w "# --------------------------------------------------------------------" + puts $fp_w "##############################" + puts $fp_w "##Automatically exported settings:" + puts $fp_w "##Creation time: [ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"]" + puts $fp_w "##Board Part: [get_property board_part [current_project]]" + puts $fp_w "##Part: [get_property part [current_project]]" + puts $fp_w "#Export Settings currently not available." + puts $fp_w "#This file will be read on project generation only." + puts $fp_w "##############################" + puts $fp_w "#Old file settings:" + puts $fp_w $old_file_data + puts $fp_w "##############################" + puts $fp_w "#exported file settings:" + puts $fp_w "puts \"Info:(TE) Automatically exported settings.\"" + puts $fp_w "#set_property \"board_part\" [get_property board_part [current_project]] \[current_project\]" + puts $fp_w "#set_property \"part\" [get_property part [current_project]] \[current_project\]" + close $fp_w + TE::UTILS::te_msg TE_HW-0 STATUS "${TE::SET_PATH}/project_settings.tcl was created." + } + #-------------------------------- + #--import_vivado_setting: + proc import_vivado_setting {} { + # hidden function: official not supported + if {[file exists ${TE::SET_PATH}/project_settings.tcl]} { + # additional project settings + TE::UTILS::te_msg TE_HW-1 INFO "Load additional project properties from ${TE::SET_PATH}/project_settings.tcl" + source ${TE::SET_PATH}/project_settings.tcl + } + } + + #-------------------------------- + #--design_exclude_boarddef: + proc design_exclude_boarddef {temp_only} { + # hidden function: official not supported + #run only if board part is defined + if {[get_property board_part [current_project]] ne ""} { + #get bd files + set bd_files [list] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + } + if {[llength $bd_files]>1} { + TE::UTILS::te_msg TE_HW-1 ERROR "Exclude Board part failed. Only one Block Design supported for this function." + return -code error; + } + #run rtl for xdc export + synth_design -rtl -name rtl_1 + set pjc_xdc_path "${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::CONST_NAME}" + file mkdir $pjc_xdc_path + #export io locs (needed if constrain in board part only) + write_xdc -force -mode port ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc + #remove wrong properties + set fp_r [open ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc "r"] + set file_data [read $fp_r] + close $fp_r + set data [split $file_data "\n"] + set fp_w [open ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc "w"] + puts $fp_w "##############################" + puts $fp_w "# --------------------------------------------------------------------" + puts $fp_w "# -- ***************************** " + puts $fp_w "# -- * Trenz Electronic GmbH * " + puts $fp_w "# -- * Holzweg 19A * " + puts $fp_w "# -- * 32257 Buende * " + puts $fp_w "# -- * Germany * " + puts $fp_w "# -- ***************************** " + puts $fp_w "# --------------------------------------------------------------------" + puts $fp_w "##############################" + puts $fp_w "##Automatically exported port constrains from exclude board part function:" + puts $fp_w "##Creation time: [ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"]" + puts $fp_w "##Board Part: [get_property board_part [current_project]]" + puts $fp_w "##Part: [get_property part [current_project]]" + puts $fp_w "##############################" + foreach line $data { + #ignore some properties + if {![string match "*set_property DIRECTION*" $line] && ![string match "*set_property IBUF_LOW_PWR*" $line] && ![string match "*current_instance -quiet*" $line]} { + puts $fp_w $line + } + } + close $fp_w + + #add constrains file + add_files -fileset ${TE::CONST_NAME} ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc + set_property used_in_synthesis false [get_files ${pjc_xdc_path}/_i_exclude_boardpart_io_loc.xdc] + #modify some ip setting manually + set mig_project "" + # set mig_addr_offset "" + foreach bd $bd_files { + open_bd_design $bd + TE::UTILS::te_msg TE_HW-2 INFO "Exclude Board part: Remove Board Part settings from IPs in $bd" + #------------- + #mig + if {[catch {[get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]}]} { + TE::UTILS::te_msg TE_HW-3 WARNING "Exclude Board part: MIG was found modified. Check Settings after run in $bd" + catch {set_property CONFIG.BOARD_MIG_PARAM Custom [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]} + catch {set mig_project [get_property CONFIG.XML_INPUT_FILE [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]]} + # catch {set mig_addr_offset [get_property range [get_bd_addr_segs -of_objects [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]]]} + } + #------------- + #TE ASIO + if {[catch {[get_bd_cells -hierarchical -filter {VLNV=~"*axis_asio_gpio*"}]}]} { + TE::UTILS::te_msg TE_HW-4 WARNING "Exclude Board part: ASIO IP was found and modified. Check Settings after run in $bd" + catch {set_property CONFIG.USE_BOARD_FLOW false [get_bd_cells -hierarchical -filter {VLNV=~"*axis_asio_gpio*"}]} + catch {set_property CONFIG.P0_BOARD_INTERFACE Custom [get_bd_cells -hierarchical -filter {VLNV=~"*axis_asio_gpio*"}]} + } + } + #disable board definition + set_property "part" "[get_property part [current_project]]" [current_project] + #update ip's + set ip_names [get_ips] + if {[llength $ip_names]>0 } { + ::report_ip_status -name ip_status + foreach ip $ip_names { + TE::UTILS::te_msg TE_HW-5 INFO "Exclude Board part: Upgrade IP: $ip_names" + if {[catch {::upgrade_ip [get_ips $ip]}] } {TE::UTILS::te_msg TE_HW-6 {CRITICAL WARNING} "Exclude Board part: Upgrade IP: $ip_names failed and will be ignored." } + } + ::report_ip_status -name ip_status + } + #restore some ip setting manually + foreach bd $bd_files { + #------------- + #mig + if {[catch {[get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]}]} { + catch {set_property CONFIG.XML_INPUT_FILE $mig_project [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]} + catch {assign_bd_address [get_bd_addr_segs -of_objects [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]]} + # catch {set_property range $mig_addr_offset [get_bd_addr_segs -of_objects [get_bd_cells -hierarchical -filter {VLNV=~"*mig_7series*"}]]} + } + #------------- + #TE ASIO + if {[catch {[get_bd_cells -hierarchical -filter {VLNV=~"*axis_asio_gpio*"}]}]} { + } + #------------- + validate_bd_design + save_bd_design + close_bd_design [current_bd_design] + } + + if {!$temp_only} { + TE::UTILS::te_msg TE_HW-7 WARNING "Exclude Board part: Remove Board part on Backup files permanently." + # ----------------------------------------------------------------- + #copy exported xdc fie + file copy -force ${pjc_xdc_path}/exclude_boardpart_io_loc.xdc ${TE::XDC_PATH}/_i_exclude_boardpart_io_loc.xdc + # ----------------------------------------------------------------- + #backup old block designs tcl files + set bd_folder ${TE::BD_PATH}/ + if {[file exists ${TE::BD_PATH}/${TE::SHORTDIR}/]} { + set bd_folder ${TE::BD_PATH}/${TE::SHORTDIR}/ + } + set bd_names [] + if { ![catch {set bd_names [glob -join -dir ${bd_folder}/ *.tcl]}] } { + foreach bd $bd_names { + if {![file exists ${bd}_backup]} { + TE::UTILS::te_msg TE_HW-8 STATUS "Exclude Board part: Write Backup file: ${bd}_backup" + file copy -force ${bd} ${bd}_backup + } + } + } + # ----------------------------------------------------------------- + #write new bd file + TE::hw_blockdesign_export_tcl + # ----------------------------------------------------------------- + # write new board_files. + set board_files "" + if { [catch {set board_files [ glob $TE::BOARDDEF_PATH/*board_files.csv ] }] } { + TE::UTILS::te_msg TE_HW-9 WARNING "Exclude Board part: Board Part CSV list not found. Create *board_file_mod.csv generation failed." + } else { + set fp [open "${board_files}" r] + set file_data [read $fp] + close $fp + set data [split $file_data "\n"] + set newdata [] + #boardname:3 + foreach line $data { + if {[string match *#* $line] != 1 && [string match *CSV_VERSION* $line] } { + lappend newdata $line + lappend newdata "#Attention:This is a modified Board part CSV files." + } elseif {[string match *#* $line] != 1 && [string length $line] > 7} { + #remove spaces + set line [string map {" " ""} $line] + #remove tabs + set line [string map {"\t" ""} $line] + #split and replaced + set tmp [split $line ","] + set tmp [lreplace $tmp[set tmp {}] 3 3 NA] + set newstring "" + set first 1 + foreach el $tmp { + if {$first} { + set newstring "$el" + set first 0 + } else { + set newstring "$newstring,$el" + } + } + lappend newdata $newstring + } else { + lappend newdata $line + } + } + #write all list elements to file + set new_name [file tail $board_files] + set new_name [file rootname $new_name] + set board_files "$TE::BOARDDEF_PATH/${new_name}_mod.csv" + set fp_w [open ${board_files} "w"] + foreach line $newdata { + puts $fp_w $line + } + close $fp_w + } + #----------------------------------------------------------------- + } + TE::UTILS::te_msg TE_HW-10 INFO "Exclude Board Part is done." + } else { + TE::UTILS::te_msg TE_HW-11 WARNING "Exclude Board Part failed, Board Part is not specified." + } + } + #-------------------------------- + #--design_include_boarddef: + proc design_include_boarddef {} { + TE::UTILS::te_msg TE_HW-12 WARNING "Sorry design_include_boarddef currently not available." + } + + #-------------------------------- + #--import_hdl: + proc import_hdl {} { + # hidden function: official not supported + if {[file exists $TE::HDL_PATH]} { + TE::UTILS::te_msg TE_HW-13 INFO "Import HDL files." + set hdl_names [TE::UTILS::search_hdl_files] + add_files $hdl_names + if {[lsearch $hdl_names *${TE::VPROJ_NAME}_top.vhd*]==0} { + #vhdl + set_property top ${TE::VPROJ_NAME}_top [current_fileset] + #overwrite bd_import toplevel_settings + set TE::PR_TOPLEVELNAME ${TE::VPROJ_NAME}_top + TE::UTILS::te_msg TE_HW-14 INFO "Set TE::PR_TOPLEVELNAME:$TE::PR_TOPLEVELNAME" + } elseif {[lsearch $hdl_names *${TE::VPROJ_NAME}_top.v*]==0} { + #Verilog + set_property top ${TE::VPROJ_NAME}_top [current_fileset] + #overwrite bd_import toplevel_settings + set TE::PR_TOPLEVELNAME ${TE::VPROJ_NAME}_top + TE::UTILS::te_msg TE_HW-15 INFO "Set TE::PR_TOPLEVELNAME:$TE::PR_TOPLEVELNAME" + } + # set attributes + foreach hdl $hdl_names { + set hdl_name [file tail [file rootname $hdl]] + if {[string match "*_simonly_*" $hdl_name] } { + set_property used_in_synthesis false [get_files $hdl] + TE::UTILS::te_msg TE_HW-16 INFO "Set $hdl_name synthesis property to false." + } + if {[string match "*_synonly_*" $hdl_name] } { + set_property used_in_simulation false [get_files $hdl] + TE::UTILS::te_msg TE_HW-17 INFO "Set $hdl_name simulation property to false." + } + } + } + } + + #------------------------------------ + #--import_xci: import xci files + proc import_xci {} { + # hidden function: official not supported + if {[file exists $TE::HDL_PATH/xci]} { + TE::UTILS::te_msg TE_HW-18 INFO "Import XCI files." + set ip_names [TE::UTILS::search_xci_files] + import_ip -files $ip_names + catch {set ip_names [get_ips]} + foreach ip $ip_names { + ##ips without block design ips + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] } { + TE::UTILS::te_msg TE_HW-19 INFO "Run out of context IP for: $ip" + generate_target {instantiation_template} [get_files ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] + update_compile_order -fileset ${TE::SOURCE_NAME} + generate_target all [get_files ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] + if {[get_property generate_synth_checkpoint [get_files ${ip}.xci]] == 1 && [get_property is_enabled [get_files ${ip}.xci]] == 1} { + create_ip_run [get_files -of_objects [get_fileset ${TE::SOURCE_NAME}] ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] + launch_run -jobs $TE::RUNNING_JOBS ${ip}_synth_1 + } + } + } + foreach ip $ip_names { + ##ips without ips from block design + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] } { + if {[get_property generate_synth_checkpoint [get_files ${ip}.xci]] == 1 && [get_property is_enabled [get_files ${ip}.xci]] == 1} { + wait_on_run -timeout ${TE::TIMEOUT} ${ip}_synth_1 + } + } + } + } + } + #------------------------------------ + #--export_xci: export xci files + proc export_xci {} { + # hidden function: official not supported + set ip_names [list] + catch {set ip_names [get_ips]} + if {[llength $ip_names] > 0} { + file mkdir $TE::HDL_PATH/xci/${TE::SHORTDIR} + + set ip_report "" + foreach ip $ip_names { + ##ips without block design ips + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci] } { + set ip_report "$ip_report \n $ip" + file copy -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/ip/${ip}/${ip}.xci $TE::HDL_PATH/xci/${TE::SHORTDIR}/${ip}.xci + } + } + TE::UTILS::te_msg TE_HW-20 INFO "Export: \n \ + $ip_report \n \ + to folder $TE::HDL_PATH/xci/${TE::SHORTDIR}/ \n \ + ------" + } + } + # ------------------------------------------------------- + # finished advanced function + # ------------------------------------------------------- + # ------------------------------------------------------- + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project creation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #------------------------------------ + #--create_project: create vivado project, set board definition and ip path, set default vivado properties + proc create_project {} { + #set board part file definition path + TE::ENV::set_path_boarddef + #create vivado project + ::create_project -force $TE::VPROJ_NAME $TE::VPROJ_PATH + #set local ip path + TE::ENV::set_path_ip + #set vivado properties + set_vprops + + } + #------------------------------------ + #--open_project: open excisting vivado project and restore importent script variables with settings from project + proc open_project {} { + #set board part file definition path + TE::ENV::set_path_boarddef + #open vivado project + ::open_project ${TE::VPROJ_NAME}.xpr + #restore vivado properties to script variables + restore_scriptprops + } + #------------------------------------ + #--close_project: close excisting vivado project + proc close_project {} { + #close vivado project + ::close_project + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished creation functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project property functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #------------------------------------ + #--set_vprops: + proc set_vprops {} { + #set std properties + set_property "default_lib" "xil_defaultlib" [current_project] + set_property "simulator_language" "Mixed" [current_project] + set_property "target_language" "VHDL" [current_project] + if {[info exists TE::PARTNAME]} { + if {![string match $TE::PARTNAME "NA"]} { + set_property "part" $TE::PARTNAME [current_project] + } + } + if {[info exists TE::BOARDPART]} { + if {![string match $TE::BOARDPART "NA"]} { + set_property "board_part" $TE::BOARDPART [current_project] + } + } + #---------------------------------------------------------- + #hidden function write settings + import_vivado_setting + #---------------------------------------------------------- + #overwrite xilinx defaults + set_property name $TE::SIM_NAME [get_filesets sim_1] + set_property name $TE::SYNTH_NAME [get_runs synth_1] + set_property name $TE::IMPL_NAME [get_runs impl_1] + set_property name $TE::CONST_NAME [get_filesets constrs_1] + #---------------------------------------------------------- + } + #------------------------------------ + #--restore_scriptprops: + proc restore_scriptprops {} { + set ID [get_property board_part [current_project]] + if {$ID ne ""} { + TE::INIT::init_board $ID 3 + } else { + TE::INIT::init_part_only [get_property part [current_project]] + } + #check bd file names for some additional functions + if {[catch {TE::INIT::check_bdtyp} result]} {TE::UTILS::te_msg TE_HW-21 Error "Script (TE::INIT::check_bdtyp) failed: $result."; return -code error} + #check board parts + if { ![string equal $TE::PARTNAME [get_property part [current_project]]] } { + TE::UTILS::te_msg TE_HW-22 {CRITICAL WARNING} "Current part name is set to [get_property part [current_project]], expect $TE::PARTNAME for board part definition file $TE::BOARDPART" + } + #check top level name + if { ![string equal $TE::PR_TOPLEVELNAME [get_property top [current_fileset]]] } { + TE::UTILS::te_msg TE_HW-23 WARNING "Current top level name is set to [get_property top [current_fileset]], expect $TE::PR_TOPLEVELNAME from default initialisation. Set TE::PR_TOPLEVELNAME to [get_property top [current_fileset]]." + set TE::PR_TOPLEVELNAME [get_property top [current_fileset]] + } + #---------------------------------------------------------- + #set run paths + set TE::SIM_NAME [get_property name [get_filesets sim*]] + set TE::SYNTH_NAME [get_property name [get_runs syn*]] + set TE::IMPL_NAME [get_property name [get_runs imp*]] + set TE::CONST_NAME [get_property name [get_filesets con*]] + + TE::UTILS::te_msg TE_HW-24 INFO "Restore project parameters:\n \ + TE::SIM_NAME: $TE::SIM_NAME \n \ + TE::SYNTH_NAME: $TE::SYNTH_NAME \n \ + TE::IMPL_NAME: $TE::IMPL_NAME \n \ + TE::CONST_NAME: $TE::CONST_NAME \n \ + ------" + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished project property functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project source functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--import_design: + proc import_design {} { + TE::UTILS::te_msg TE_HW-25 STATUS "Start import design" + #load backup constrains and block design + set xdc_files [TE::UTILS::search_xdc_files] + import_xdc $xdc_files + set_xdcsetting $xdc_files + import_blockdesign + import_hdl + import_xci + import_elf + } + #-------------------------------- + #--import_xdc: + proc import_xdc {xdc_files} { + set target_file "" + foreach xdc $xdc_files { + read_xdc $xdc + if {[file tail $xdc] eq "vivado_target.xdc"} { + set target_file $xdc + } + } + + set_property target_constrs_file $target_file [current_fileset -constrset] + } + #-------------------------------- + #--set_xdcsetting: + proc set_xdcsetting {xdc_files} { + #set xdc properties depending on xdc name: processing order an usage + foreach xdc_file $xdc_files { + if {[string match *_e_* $xdc_file] == 1} { + set_property PROCESSING_ORDER EARLY [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-26 STATUS "Set processing order early for $xdc_file" + } elseif {[string match *_l_* $xdc_file] == 1} { + set_property PROCESSING_ORDER LATE [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-27 STATUS "Set processing order late for $xdc_file" + } else { + set_property PROCESSING_ORDER NORMAL [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-28 STATUS "Set processing order normal for $xdc_file" + } + if {[string match *_s_* $xdc_file] == 1} { + set_property USED_IN_IMPLEMENTATION 0 [get_files $xdc_file] + set_property USED_IN_SYNTHESIS 1 [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-29 STATUS "Set use for synthesis only for $xdc_file" + } elseif {[string match *_i_* $xdc_file] == 1} { + set_property USED_IN_SYNTHESIS 0 [get_files $xdc_file] + set_property USED_IN_IMPLEMENTATION 1 [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-30 STATUS "Set use for implementation only for $xdc_file" + } else { + set_property USED_IN_SYNTHESIS 1 [get_files $xdc_file] + set_property USED_IN_IMPLEMENTATION 1 [get_files $xdc_file] + TE::UTILS::te_msg TE_HW-31 STATUS "Set use for synthesis and implementation for $xdc_file" + } + } + } + #-------------------------------- + #--reload_blockdesign: delete all bd and load bd.tcl files from backup + proc reload_blockdesign {} { + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + } + foreach bd $bd_files { + TE::UTILS::te_msg TE_HW-32 STATUS "Remove:$bd" + remove_files $bd + set bd_dir [file dirname $bd] + file delete -force $bd_dir + } + import_blockdesign + } + #-------------------------------- + #--import_blockdesign: imports and compile bd designs for vivado + proc import_blockdesign {} { + #check bd filenames for some additional functions + if {[catch {TE::INIT::check_bdtyp} result]} {TE::UTILS::te_msg TE_HW-33 ERROR "Script (TE::INIT::check_bdtyp) failed: $result."; return -code error} + + set bd_files [TE::UTILS::search_bd_files] + if {[llength $bd_files]>0 } { + #run bd tcl + foreach bd $bd_files { + # + if {[file extension $bd] eq ".tcl"} { + source $bd + close_bd_design [get_bd_designs] + } + } + #compile bd + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + } + foreach bd $bd_files { + open_bd_design $bd + validate_bd_design -force + generate_target all [get_files $bd] + #check if hdf to exists + set bd_name [get_bd_designs] + set tl_name "NA" + if { [catch {set tl_name [glob -join -dir $TE::HDL_PATH/ ${TE::VPROJ_NAME}_top.*]}] & [catch {set tl_name [glob -join -dir $TE::HDL_PATH/${TE::SHORTDIR}/ ${TE::VPROJ_NAME}_top.*]}] } { + TE::UTILS::te_msg TE_HW-34 INFO "Generate top level wrapper" + make_wrapper -files [get_files $bd] -top + add_files -norecurse ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/$bd_name/hdl/${bd_name}_wrapper.vhd + } else { + TE::UTILS::te_msg TE_HW-35 INFO "Use custom HDL top level file" + } + close_bd_design [get_bd_designs $bd] + #todo: use more bd files -> currently its check on init function only one is allowed + } + update_compile_order -fileset ${TE::SOURCE_NAME} + update_compile_order -fileset ${TE::SIM_NAME} + } + } + #-------------------------------- + #--export_blockdesign: export bd designs to clear vivado folder (if folder ${TE::BD_PATH}/${TE::SHORTDIR} exist it will be export for this boardpart only) + #-- create pdf for each bd and sub hierarchy + proc export_blockdesign {{args ""}} { + #read args + set bd_folder ${TE::BD_PATH} + set no_mig "" + set valid_bd true + set this_boardpart_only false + set mod_tcl false + set args_cnt [llength $args] + for {set option 0} {$option < $args_cnt} {incr option} { + switch [lindex $args $option] { + "-no_mig_contents" {set no_mig [lindex $args $option]} + "-no_validate" {set valid_bd false} + "-mod_tcl" {set mod_tcl true} + "-board_part_only" {set this_boardpart_only true} + "" {} + default { TE::UTILS::te_msg TE_HW-36 {CRITICAL WARNING} "Unrecognised option [lindex $args $option]is ignored" } + } + } + if {$this_boardpart_only} { + file mkdir ${TE::BD_PATH}/${TE::SHORTDIR}/ + } + if {[file exists ${TE::BD_PATH}/${TE::SHORTDIR}/]} { + set bd_folder ${TE::BD_PATH}/${TE::SHORTDIR}/ + } + #search for open projects + set bd_open false + set bd_open_file "" + set bd_open_name "" + + if {[current_bd_design -quiet] ne ""} { + #save currend bd configuration + # validate_bd_design -force + save_bd_design + set bd_open true + set bd_open_name "[current_bd_design]" + TE::UTILS::te_msg TE_BD-2 INFO "$bd_open_name was saved." + set bd_open_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/${bd_open_name}/${bd_open_name}.bd + # close_bd_design [get_bd_designs $bd_open_file] + } + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + TE::UTILS::te_msg TE_BD-3 WARNING "No BD-File was found." + } + if {!$TE::BD_MULTI} { + if {[llength $bd_files]>1 } { + TE::UTILS::te_msg TE_BD-4 WARNING "Currently only one block design supported, deleted unused bd.tcl from ${bd_folder}." + } + } + + foreach bd $bd_files { + open_bd_design $bd + if {$valid_bd} { + TE::UTILS::te_msg TE_BD-5 INFO "Validate Design." + validate_bd_design + } else { + TE::UTILS::te_msg TE_BD-6 WARNING "Validate Design disabled." + } + } + set vivado_bd_design_name [] + if { [catch {set vivado_bd_design_name [get_bd_designs]}] } { + TE::UTILS::te_msg TE_BD-7 {CRITICAL WARNING} "Block designs was not found." + + } else { + + set txt "Stored Block Designs: \n " + foreach bd $vivado_bd_design_name { + # puts "-exclude Layout, IP-Version and MIG-content" + # write_bd_tcl -force -exclude_layout -no_ip_version -no_mig_contents ${bd_folder}/${bd}_bd.tcl + set bf_tcl_name ${bd_folder}/${bd}_bd.tcl + set txt "${txt} File: ${bf_tcl_name} \n" + if {$no_mig eq ""} { + write_bd_tcl -force ${bf_tcl_name} + } else { + set txt "${txt} -Option: Remove MIG-Contents \n" + write_bd_tcl -force $no_mig ${bf_tcl_name} + } + # modify bd + if {[catch {TE::UTILS::modify_block_design_tcl ${bf_tcl_name} ${mod_tcl}} result]} { TE::UTILS::te_msg TE_BD-8 ERROR "Script (TE::UTILS::modify_block_design_tcl) failed: $result."; return -code error} + #export blockdesign as pdf + #sel doc_path + set doc_path ${TE::DOC_PATH}/ + if {[file exists ${TE::BD_PATH}/${TE::SHORTDIR}/]} { + set doc_path ${TE::DOC_PATH}/${TE::SHORTDIR}/ + } + file mkdir ${doc_path}/ + #delete old bd_*.pdf + set old_pdfs [] + if { [catch {set old_pdfs [glob -join -dir ${doc_path}/ bd_*.pdf]}] } { + } else { + TE::UTILS::te_msg TE_BD-9 INFO "Delete old Block Design PDFs in ${doc_path}" + foreach old_pdf $old_pdfs { + if {[catch {file delete -force ${old_pdf}}]} { + TE::UTILS::te_msg TE_BD-10 WARNING "Delete ${old_pdf} failed." + } + } + } + set txt "${txt} -Option: Write PDF-Layouts \n" + set sname bd_${TE::VPROJ_NAME}_hier_top.pdf + if {[catch {write_bd_layout -force -format pdf -scope all -orientation landscape ${doc_path}/${sname}}]} { + TE::UTILS::te_msg TE_BD-11 WARNING "Write ${doc_path}/${sname} failed." + } + set allsubs [get_bd_cells -filter {TYPE == hier}] + foreach sub $allsubs { + set tmp [string map {"/" ""} [join $sub]] + set sname bd_${TE::VPROJ_NAME}_hier_${tmp}.pdf + if {[catch {write_bd_layout -force -format pdf -hierarchy [get_bd_cells $sub] -orientation landscape ${doc_path}/${sname}}]} { + TE::UTILS::te_msg TE_BD-12 WARNING "Write ${doc_path}/${sname} failed." + } + } + # save is needed because print subsystem mod bd file + save_bd_design + # + if { $bd ne $bd_open_name || !$bd_open} { + close_bd_design [get_bd_designs ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/${bd}/${bd}.bd] + } + } + TE::UTILS::te_msg TE_BD-13 INFO "$txt" + } + } + #-------------------------------- + #--import_elf: + proc import_elf {} { + if {[file exists $TE::FIRMWARE_PATH]} { + set elf_names [TE::UTILS::search_elf_files] + # set microblaze elf + foreach elf_f $elf_names { + add_files -norecurse $elf_f + set tmp [split $elf_f "/"] + set tmpLength [llength $tmp] + if {$tmpLength>2} { + set elf_file [lindex $tmp [expr $tmpLength-1]] + set m_name [lindex $tmp [expr $tmpLength-2]] + set f_obj "*${m_name}/${elf_file}" + #todo multi bd design + set bd_files [list] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + } + foreach bd $bd_files { + set bd_name [file tail [file rootname $bd]] + set_property SCOPED_TO_REF $bd_name [get_files -all -of_objects [get_fileset sources_1] ${f_obj}] + #mcs only used if name contains SYSCONTROL or MCS + if {[string match -nocase *SYSCONTROL* $m_name] || [string match -nocase *MCS* $m_name]} { + set_property SCOPED_TO_CELLS "${m_name}/U0/microblaze_I" [get_files -all -of_objects [get_fileset sources_1] ${f_obj}] + } else { + set_property SCOPED_TO_CELLS "${m_name}" [get_files -all -of_objects [get_fileset sources_1] ${f_obj}] + } + } + } + } + } + } + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished project source functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project new block design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--creat_new_blockdesign: create empty block design with zynq initialisation: fsys,msys,zsys,zusys + proc create_new_blockdesign {{type fsys} {msys_conf {local_mem "8KB" ecc "None" cache "None" debug_module "Debug Only" axi_periph "Enabled" axi_intc "0" clk "None"}}} { + #check other bd files exists, currently only one is supported with this function + set bd_files [] + if { [catch {set bd_files [glob -join -dir ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.srcs/${TE::SOURCE_NAME}/bd/ * *.bd]}] } { + create_bd_design $type + if {$type eq "fsys"} { + TE::UTILS::te_msg TE_BD-14 INFO "For fsys Block Design is currently no additional initialisation intended." + } elseif {$type eq "zusys"} { + create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e zynq_ultra_ps_e_0 + apply_bd_automation -rule xilinx.com:bd_rule:zynq_ultra_ps_e -config {apply_board_preset "1" } [get_bd_cells zynq_ultra_ps_e_0] + + set tcl_ext [] + if { [catch {set tcl_ext [glob -join -dir ${TE::BOARDDEF_PATH}/carrier_extension/ *_preset.tcl]}] } { + } + foreach carrier_ext $tcl_ext { + TE::UTILS::te_msg TE_BD-15 INFO "Import carrier_settings from:[file tail $carrier_ext]." + source $carrier_ext + } + } elseif {$type eq "zsys"} { + create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7 processing_system7_0 + apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } [get_bd_cells processing_system7_0] + set tcl_ext [] + if { [catch {set tcl_ext [glob -join -dir ${TE::BOARDDEF_PATH}/carrier_extension/ *_preset.tcl]}] } { + } + foreach carrier_ext $tcl_ext { + TE::UTILS::te_msg TE_BD-16 INFO "Import carrier_settings from:[file tail $carrier_ext]." + source $carrier_ext + } + } elseif {$type eq "msys"} { + create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze microblaze_0 + #set test {local_mem "8KB" ecc "None" cache "None" debug_module "Debug Only" axi_periph "Enabled" axi_intc "0" clk "None"} + apply_bd_automation -rule xilinx.com:bd_rule:microblaze -config $msys_conf [get_bd_cells microblaze_0] + } else { + TE::UTILS::te_msg TE_BD-17 {CRITICAL WARNING} "Unknown Block-Design Type. No Type specific initialisation is done." + } + } else { + TE::UTILS::te_msg TE_BD-18 ERROR "Currently TE-Scripts supports only one Block-Design. Generation is cancelled." + return -code error + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished new block design functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # project build functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--build_design: + proc build_design {{bitgen true} {mcsgen true} {reportgen true} {hdfgen true}} { + if {[catch {run_synth} result]} {TE::UTILS::te_msg TE_HW-37 ERROR "Script (TE::VIV::run_synth) failed: $result."; return -code error} + if {[catch {run_impl} result]} {TE::UTILS::te_msg TE_HW-38 ERROR "Script (TE::VIV::run_impl) failed: $result."; return -code error} + if {$bitgen} { + if {[catch {write_viv_bitfile} result]} {TE::UTILS::te_msg TE_HW-39 ERROR "Script (TE::VIV::write_viv_bitfile) failed: $result."; return -code error} + } else { + #delete old one if exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit} result]} {TE::UTILS::te_msg TE_HW-40 WARNING "$result"} + } + TE::UTILS::te_msg TE_HW-41 WARNING "Bit-file generation is disabled on build design run." + } + if {$mcsgen} { + if {[catch {write_viv_cfgmem} result]} {TE::UTILS::te_msg TE_HW-42 ERROR "Script (TE::VIV::write_viv_cfgmem) failed: $result."; return -code error} + } else { + #delete old one if exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs} result]} {TE::UTILS::te_msg TE_HW-43 WARNING "$result"} + } + TE::UTILS::te_msg TE_HW-44 WARNING "MCS-file generation is disabled on build design run" + } + if {$reportgen} { + if {[catch {report_design} result]} {TE::UTILS::te_msg TE_HW-45 ERROR "Script (TE::VIV::report_design) failed: $result."; return -code error} + } else { + #delete old one if exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt} result]} {TE::UTILS::te_msg TE_HW-46 WARNING "$result"} + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt} result]} {TE::UTILS::te_msg TE_HW-47 WARNING "$result"} + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv} result]} {TE::UTILS::te_msg TE_HW-48 WARNING "$result"} + } + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc} result]} {TE::UTILS::te_msg TE_HW-49 WARNING "$result"} + } + TE::UTILS::te_msg TE_HW-50 WARNING "Report-files generation is disabled on build design run." + } + if {$hdfgen} { + #is done automatically with bitgen -> *.sysdef + } else { + #delete old one if exists + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef]} { + if {[catch {file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.sysdef} result]} {TE::UTILS::te_msg TE_HW-51 WARNING "$result"} + } + TE::UTILS::te_msg TE_HW-52 WARNING "HDF-files generation is disabled on build design run." + } + } + #-------------------------------- + #--run_synth: + proc run_synth {} { + #syntheses + reset_run $TE::SYNTH_NAME + launch_runs $TE::SYNTH_NAME -jobs $TE::RUNNING_JOBS + wait_on_run -timeout $TE::TIMEOUT $TE::SYNTH_NAME + } + #-------------------------------- + #--run_impl: + proc run_impl {} { + #implementation and bitgen + reset_run $TE::IMPL_NAME + # launch_runs $TE::IMPL_NAME + launch_runs $TE::IMPL_NAME -to_step route_design -jobs $TE::RUNNING_JOBS + wait_on_run -timeout $TE::TIMEOUT $TE::IMPL_NAME + } + #-------------------------------- + #--write_viv_bitfile: + proc write_viv_bitfile {} { + launch_runs $TE::IMPL_NAME -to_step write_bitstream -jobs $TE::RUNNING_JOBS + wait_on_run -timeout $TE::TIMEOUT $TE::IMPL_NAME + } + #-------------------------------- + #--write_viv_cfgmem: + proc write_viv_cfgmem {} { + #used only if bd name is no zynq design (without processor system)! + if {[file exists ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs]} { file delete -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs } + if {!$TE::IS_ZSYS && !$TE::IS_ZUSYS} { + if {$TE::CFGMEM_MEMSIZE_MB ne "NA"} { + #check supported from *board_files.csv + #write mcs with *board_files.csv settings + if {[catch { write_cfgmem -force -format mcs -interface $TE::CFGMEM_IF -size $TE::CFGMEM_MEMSIZE_MB \ + -loadbit "up 0x0 ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit" \ + -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs\ + }]} { + #if failed try SPIX1 (default ) (faster than open design) + TE::UTILS::te_msg TE_HW-53 INFO "Generate MCS failed with $TE::CFGMEM_IF from *board_files.csv specification, try to generate SPIx1." + if {[catch { write_cfgmem -force -format mcs -interface SPIX1 -size $TE::CFGMEM_MEMSIZE_MB \ + -loadbit "up 0x0 ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit" \ + -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs\ + }]} { + #if failed get propery from design (needs some time) + TE::UTILS::te_msg TE_HW-54 INFO "Generate MCS failed with SPIx1, try to get information from implemented Design." + open_run $TE::IMPL_NAME + set tmp_cfgmem_if "SPIx[get_property BITSTREAM.CONFIG.SPI_BUSWIDTH [current_design]]" + close_design + write_cfgmem -force -format mcs -interface $tmp_cfgmem_if -size $TE::CFGMEM_MEMSIZE_MB \ + -loadbit "up 0x0 ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.bit" \ + -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.mcs + TE::UTILS::te_msg TE_HW-55 INFO "Generate MCS with $tmp_cfgmem_if from current design setting (BITSTREAM.CONFIG.SPI_BUSWIDTH), but current Board Part supports $TE::CFGMEM_IF" + } else { + TE::UTILS::te_msg TE_HW-56 INFO "Generate MCS with SPIX1 (BITSTREAM.CONFIG.SPI_BUSWIDTH 1) from Bitfile, but current Board Part supports $TE::CFGMEM_IF also!" + } + } + } else { + TE::UTILS::te_msg TE_HW-57 {CRITICAL WARNING} "FPGAFLASHTYP Mem Size in MB is not specified in *.board_files.csv. *.mcs file is not generated." + } + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished built functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # report functions (todo to utilities) + # ----------------------------------------------------------------------------------------------------------------------------------------- + + #-------------------------------- + #--report_design: + proc report_design {} { + #-------------check toplevel name (if modified) + if { ![string equal $TE::PR_TOPLEVELNAME [get_property top [current_fileset]]] } { + TE::UTILS::te_msg TE_HW-58 INFO "Top Level Name ([get_property top [current_fileset]]) is not same then exspected from BD-File delivery ($TE::PR_TOPLEVELNAME). [get_property top [current_fileset]] is used in Script settings now." + set TE::PR_TOPLEVELNAME [get_property top [current_fileset]] + } + #-------------block design reports + #-------------synthese reports + #-------------implement reports + open_run $TE::IMPL_NAME + + #todo: + # report_debug_core -file ${TE::VPROJ_NAME}_debug_cores.txt + report_ip_status -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_ip_status_report.txt + report_io -force -file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.txt -format text + write_csv -force ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.csv + write_xdc -force -mode port ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::VPROJ_NAME}_io_report.xdc + + report_summary + close_design + } + #-------------------------------- + #--report_run: + proc report_run {} { + #todo eventuell auftrennen und dann noch report schreiben, wenn nicht alles durch geht + set date "[ clock format [clock seconds] -format "%Y-%m-%dT%H:%M:%S"]" + set status "Error" + set founderror -1 + #synth + set sythn_counts [extract_synth_summary] + set sythn_counts_split [split $sythn_counts ","] + set value [lindex $sythn_counts_split [expr [llength $sythn_counts_split]-1]] + if {$value != 0} {set founderror 1} + #impl + set impl_counts [extract_impl_summary] + set impl_counts_split [split $impl_counts ","] + set value [lindex $impl_counts_split [expr [llength $impl_counts_split]-1]] + if {$value != 0} {set founderror 1} + #drc + set drc_counts [extract_drc_summary] + set drc_counts_split [split $drc_counts ","] + set value [lindex $drc_counts_split [expr [llength $drc_counts_split]-1]] + if {$value != 0} {set founderror 1} + #timing + set timing_counts [extract_timing_summary] + set timing_counts_split [split $timing_counts ","] + set value [lindex $timing_counts_split [expr [llength $timing_counts_split]-1]] + if {[string compare "NA" $value ]==0} {set founderror 0} elseif {$value != 0} {set founderror 1} + if {$founderror == -1} {set status "Ok"} elseif {$founderror == 0} {set status "Ok(NA)"} + #write report + set report "[format "%-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s," "$date" "$status" "$TE::VPROJ_NAME" "$TE::SHORTDIR" "$TE::BOARDPART" "$TE::SYNTH_NAME" "$TE::IMPL_NAME" "[lindex $sythn_counts_split 0]" "[lindex $sythn_counts_split 1]" "[lindex $sythn_counts_split 2]" "[lindex $sythn_counts_split 3]" "[lindex $impl_counts_split 0]" "[lindex $impl_counts_split 1]" "[lindex $impl_counts_split 2]" "[lindex $impl_counts_split 3]" "[lindex $drc_counts_split 0]" "[lindex $drc_counts_split 1]" "[lindex $timing_counts_split 0]" "[lindex $timing_counts_split 1]" "[lindex $timing_counts_split 2]"]" + return $report + } + #-------------------------------- + #--report_summary: + proc report_summary {} { + set fp_w [open ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}_summary.csv "w"] + #write header + puts $fp_w [format "%-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s, %-40s," "Date" "Status" "ProjName" "BoardDefShortName" "BoardDefName" "SynthName" "ImplName" "SynthInfo" "SynthWarnings" "SynthCritWarnings" "SynthError" "ImplInfo" "ImplWarnings" "ImplCritWarnings" "ImplError" "ImplDRCWarnings" "ImplDRCError" "ImplTimingWNS" "ImplTimingFaildEndpoints" "ImplTimingTNS"] + + puts $fp_w [report_run] + close $fp_w + } + #-------------------------------- + #--extract_synth_summary: + proc extract_synth_summary {} { + set synth_returns "0,0,0,FileNotFound" + + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::SYNTH_NAME}/${TE::PR_TOPLEVELNAME}.vds + if { ![file exists ${report_file}]} {return $synth_returns} + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + + foreach line $data { + if {[string match "*Infos*Warnings*Critical Warnings*Errors encountered*" $line]} { + set tmp [string map {"and" "," " " "" "Infos" "" "Warnings" "" "Critical" "" "Errors" "" "encountered." ""} "$line"] + #use only last log output + #return Infos, Warnings, Critical Warnings , Errors + set synth_returns $tmp + } + } + return $synth_returns + } + #-------------------------------- + #--extract_impl_summary: + proc extract_impl_summary {} { + set impl_returns "0,0,0,FileNotFound" + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.vdi + if { ![file exists ${report_file}]} {return $impl_returns} + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + + foreach line $data { + if {[string match "*Infos*Warnings*Critical Warnings*Errors encountered*" $line]} { + set tmp [string map {"and" "," " " "" "Infos" "" "Warnings" "" "Critical" "" "Errors" "" "encountered." ""} "$line"] + #use only last log output + #return Infos, Warnings, Critical Warnings , Errors + set impl_returns $tmp + } + } + return $impl_returns + } + #-------------------------------- + #--extract_drc_summary: + proc extract_drc_summary {} { + set drc_returns "0,FileNotFound" + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}.vdi + if { ![file exists ${report_file}]} {return $drc_returns} + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + set err_count 0 + set warn_count 0 + + foreach line $data { + if {[string match "*DRC finished with*" $line]} { + set index [string first "with" $line 0] + set tmp [string range $line $index [string length $line]] + set tmp [string map {" " "" "with" "" "Errors" "" "Warnings" "" "Advisories" ""} "$tmp"] + set tmp [split $tmp ","] + if {[llength $tmp]==1} { + if {[string is integer [lindex $tmp 0]]} { + set err_count [expr $err_count + [lindex $tmp 0]] + } else { + set err_count 999999 + } + } else { + if {[string is integer [lindex $tmp 0]]} { + set err_count [expr $err_count + [lindex $tmp 0]] + } else { + set err_count 999999 + } + if {[string is integer [lindex $tmp 1]]} { + set warn_count [expr $warn_count + [lindex $tmp 1]] + } else { + set warn_count 999999 + } + } + } + } + #return Warnings, Errors + set drc_returns "$warn_count, $err_count" + return $drc_returns + } + #-------------------------------- + #--extract_timing_summary: + proc extract_timing_summary {} { + set timing_returns "0,0,FileNotFound" + set report_file ${TE::VPROJ_PATH}/${TE::VPROJ_NAME}.runs/${TE::IMPL_NAME}/${TE::PR_TOPLEVELNAME}_timing_summary_routed.rpt + if { ![file exists ${report_file}]} {return $timing_returns} + set fp_r [open ${report_file} "r"] + set file_data [read $fp_r] + set data [split $file_data "\n"] + close $fp_r + + set lineindex -1 + foreach line $data { + incr lineindex + if {[string match "*Design Timing Summary*" $line]} { + break; + } + } + set lineindex [expr $lineindex +6] + set tmp [join [lindex $data $lineindex] " "] + set timing_returns "[lindex $tmp 0],[lindex $tmp 2],[lindex $tmp 1]" + #return WNS, Faild Endpoints, TNS + return $timing_returns + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished report functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + namespace eval VLAB { + # ----------------------------------------------------------------------------------------------------------------------------------------- + # vlab project functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + #-------------------------------- + #--create_project: + proc create_project {} { + #create vivado lab project + ::create_project -force $TE::VPROJ_NAME $TE::VLABPROJ_PATH + #set props.. + } + #-------------------------------- + #--open_project: + proc open_project {} { + #open vivado lab project + ::open_project ${TE::VPROJ_NAME}.lpr + } + #-------------------------------- + #--close_project: + proc close_project {} { + #close vivado project + ::close_project + } + #-------------------------------- + #--hw_open_jtag: + proc hw_open_jtag {} { + + #start new session + ::open_hw + if {[current_hw_server -quiet] eq ""} { + ::connect_hw_server + } + if {[current_hw_device -quiet] eq ""} { + ::open_hw_target + return true + } else { + return false + } + } + #-------------------------------- + #--hw_close_jtag: + proc hw_close_jtag {} { + ::close_hw + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished vlab project functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # device functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--hw_create_flash_device: + proc hw_create_flash_device {{fname ""}} { + #todo configs auswählbar + set partname_int "" + set flashtyp_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set id "[TE::BDEF::find_id $fname]" + set tmp [TE::BDEF::get_fpgaflashtyp $id 0] + set tmp [split $tmp "|"] + if {[llength $tmp] eq 3} { + set flashtyp_int [lindex $tmp 0] + } else { + set flashtyp_int $tmp + } + + } else { + set partname_int $TE::PARTNAME + set flashtyp_int $TE::FPGAFLASHTYP + } + set hw_fpga_name [hw_get_fpga $partname_int] + set_property PROBES.FILE "" $hw_fpga_name + #reset old propefiles + create_hw_cfgmem -hw_device $hw_fpga_name -mem_dev [lindex [get_cfgmem_parts ${flashtyp_int}] 0] + set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.VERIFY 0 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if {[catch {refresh_hw_device $hw_fpga_name}] } {} + } + #-------------------------------- + #--hw_get_fpga: + proc hw_get_fpga {{partname ""}} { + set partname_int $partname + if {$partname_int eq ""} {set partname_int $TE::PARTNAME} + set hw_fpga_name NA + set hw_fpga_found false + + foreach hwd [get_hw_devices] { + set name [lindex [split $hwd "_"] 0] + set hw_fpga_found [string match *$name* $partname_int] + if {$hw_fpga_found} {set hw_fpga_name $hwd;break;} + } + if {$hw_fpga_found} { + # ::refresh_hw_device $hw_fpga_name + } else { + # change compared name from automotive and defence grade fpga (has same hw-id than commercial) + set alt_partname [string map {xa xc xq xc} $partname_int] + foreach hwd [get_hw_devices] { + set name [lindex [split $hwd "_"] 0] + set hw_fpga_found [string match *$name* $alt_partname] + if {$hw_fpga_found} {set hw_fpga_name $hwd;break;} + } + if {$hw_fpga_found} { + # ::refresh_hw_device $hw_fpga_name + } else { + set rpt_txt "$partname_int Device not found. \n" + foreach hwd [get_hw_devices] { + set name [lindex [split $hwd "_"] 0] + set rpt_txt "$rpt_txt $partname_int and $alt_partname compare with *$name* failed. \n" + } + TE::UTILS::te_msg TE_PR-0 WARNING "$rpt_txt" + } + } + return $hw_fpga_name + } + #-------------------------------- + #--hw_fpga_boot_from_memory: + proc hw_fpga_boot_from_memory {{fname ""}} { + set partname_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + } else { + set partname_int $TE::PARTNAME + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$hw_fpga_name ne "NA"} { + ::boot_hw_device $hw_fpga_name + TE::UTILS::te_msg TE_PR-1 INFO "Reboot Device is done." + ::refresh_hw_device $hw_fpga_name + TE::UTILS::te_msg TE_PR-2 INFO "Reboot Device is done." + } else { + TE::UTILS::te_msg TE_PR-3 ERROR "Boot from Memory failed. Device not found." + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished device functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + # ----------------------------------------------------------------------------------------------------------------------------------------- + # property functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--hw_set_bit_and_ltx_files: setup for bitfile configuration via labtools/vivado + proc hw_set_bit_and_ltx_files {use_basefolder app_name {fname ""}} { + set return_filename "" + set partname_int "" + set shortdir_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set shortdir_int "[TE::BDEF::find_shortdir $fname]" + } else { + set partname_int $TE::PARTNAME + set shortdir_int $TE::SHORTDIR + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$hw_fpga_name ne "NA"} { + if {$use_basefolder} { + set bitfilename "" + if { ![catch {set bitfilename [glob -join -dir ${TE::BASEFOLDER}/ *.bit]}] } { + TE::UTILS::te_msg TE_PR-4 INFO "Used file:${bitfilename}" + set return_filename ${bitfilename} + set_property PROGRAM.FILE ${bitfilename} $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-5 ERROR "Bitfile not found in ${TE::BASEFOLDER}. Nothing is done." + return -code error + } + } else { + if {$app_name eq "" || $app_name eq "NA"} { + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit]} { + #use bitfile from hardware folder (with bootloop for microblaze systems) + set_property PROGRAM.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit $hw_fpga_name + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-6 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-7 INFO "Used file:${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit" + set return_filename ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit + } else { + #use default bit from hardware folder (with bootloop for microblaze systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit]} { + set_property PROGRAM.FILE ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit $hw_fpga_name + if {[file exists ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-8 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-9 INFO "Used file:${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit" + set return_filename ${TE::PREBUILT_HW_PATH}/default/${TE::VPROJ_NAME}.bit + } else { + TE::UTILS::te_msg TE_PR-10 ERROR "${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.bit not found. Nothing is done." + return -code error + } + } + } else { + #use bitfile from bootimage folder (with programmed apps for microblaze systems) + set bitfilename "" + if { ![catch {set bitfilename [glob -join -dir ${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/ *.bit]}] } { + set_property PROGRAM.FILE ${bitfilename} $hw_fpga_name + #search in hardware folder for ltx + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-11 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-12 INFO "Used file:${bitfilename}" + set return_filename ${bitfilename} + } else { + TE::UTILS::te_msg TE_PR-13 ERROR "${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/*.bit not found. Nothing is done." + return -code error + } + } + } + } else { + TE::UTILS::te_msg TE_PR-14 ERROR "Program FPGA failed. Device not found." + return -code error + } + return $return_filename + } + #-------------------------------- + #--hw_set_bin_and_ltx_files: setup for binfile configuration via labtools/vivado + proc hw_set_bin_and_ltx_files {use_basefolder app_name fname} { + set return_filename "" + set partname_int "" + set shortdir_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set shortdir_int "[TE::BDEF::find_shortdir $fname]" + } else { + set partname_int $TE::PARTNAME + set shortdir_int $TE::SHORTDIR + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$hw_fpga_name ne "NA"} { + if {$use_basefolder} { + set binfilename "" + set ltxfilename "" + if { ![catch {set binfilename [glob -join -dir ${TE::BASEFOLDER}/ *.bin]}] } { + TE::UTILS::te_msg TE_PR-15 INFO "Used file:${binfilename}" + set return_filename ${binfilename} + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${binfilename}" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if { ![catch {set ltxfilename [glob -join -dir ${TE::BASEFOLDER}/ *.ltx]}] } { + set_property PROBES.FILE ${ltxfilename} $hw_fpga_name + } else { + set_property PROBES.FILE "" $hw_fpga_name + } + } else { + TE::UTILS::te_msg TE_PR-16 {CRITICAL WARNING} "Bin file not found in ${TE::BASEFOLDER}. Nothing is done." + return -code error + } + } else { + set binfilename "" + if { ![catch {set binfilename [glob -join -dir ${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/ *.bin]}] } { + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${binfilename}" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-17 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-18 INFO "Used file: ${binfilename}" + set return_filename ${binfilename} + } else { + TE::UTILS::te_msg TE_PR-19 ERROR "${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/*.bin not found. Nothing is done." + return -code error + } + } + } else { + TE::UTILS::te_msg TE_PR-20 ERROR "Program FPGA failed. Device not found." + return -code error + } + return $return_filename + } + #-------------------------------- + #--hw_set_mcs_and_ltx_files: setup for mcsfile configuration via labtools/vivado + proc hw_set_mcs_and_ltx_files {use_basefolder term app_name fname} { + set return_filename "" + set partname_int "" + set shortdir_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set shortdir_int "[TE::BDEF::find_shortdir $fname]" + } else { + set partname_int $TE::PARTNAME + set shortdir_int $TE::SHORTDIR + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$hw_fpga_name ne "NA"} { + if {$use_basefolder} { + set mcsfilename "" + set ltxfilename "" + if { ![catch {set mcsfilename [glob -join -dir ${TE::BASEFOLDER}/ *.mcs]}] } { + TE::UTILS::te_msg TE_PR-21 INFO "Used file:${mcsfilename}" + set return_filename ${mcsfilename} + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${mcsfilename}" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.UNUSED_PIN_TERMINATION ${term} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if { ![catch {set ltxfilename [glob -join -dir ${TE::BASEFOLDER}/ *.ltx]}] } { + set_property PROBES.FILE ${ltxfilename} $hw_fpga_name + } else { + set_property PROBES.FILE "" $hw_fpga_name + } + } else { + TE::UTILS::te_msg TE_PR-22 ERROR "MCS-file not found in ${TE::BASEFOLDER}. Nothing is done." + return -code error + } + } else { + if {$app_name eq "" || $app_name eq "NA"} { + #use mcs from hardware folder (with bootloop for microblaze systems) + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs]} { + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.UNUSED_PIN_TERMINATION ${term} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-23 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-24 INFO "Used file:${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs" + set return_filename ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs + } else { + TE::UTILS::te_msg TE_PR-25 ERROR "${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.mcs not found. Nothing is done" + return -code error + } + } else { + #use mcs from bootimage folder (with configured app for microblaze systems) + set mcsfilename "" + if { ![catch {set mcsfilename [glob -join -dir ${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/ *.mcs]}] } { + set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.FILES [list "${mcsfilename}" ] [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + set_property PROGRAM.UNUSED_PIN_TERMINATION ${term} [ get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + #search ltx from hardware folder + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + } else { + TE::UTILS::te_msg TE_PR-26 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + TE::UTILS::te_msg TE_PR-27 INFO "Used file:${mcsfilename}" + set return_filename ${mcsfilename} + } else { + TE::UTILS::te_msg TE_PR-28 ERROR "${TE::PREBUILT_BI_PATH}/${shortdir_int}/${app_name}/*.mcs not found. Nothing is done." + return -code error + } + } + } + } else { + TE::UTILS::te_msg TE_PR-29 ERROR "Program FPGA failed. Device not found." + return -code error + } + return $return_filename + } + + #-------------------------------- + #--hw_reload_prope_file_device: + proc hw_reload_prope_file_device {{fname ""}} { + set partname_int "" + set shortdir_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + set shortdir_int "[TE::BDEF::find_shortdir $fname]" + } else { + set partname_int $TE::PARTNAME + set shortdir_int $TE::SHORTDIR + } + set hw_fpga_name [hw_get_fpga $partname_int] + + if {[file exists ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx]} { + set_property PROBES.FILE ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx $hw_fpga_name + TE::UTILS::te_msg TE_PR-30 INFO "New Probes file is set: ${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx" + + } else { + TE::UTILS::te_msg TE_PR-31 INFO "No Probes file (${TE::PREBUILT_HW_PATH}/${shortdir_int}/${TE::VPROJ_NAME}.ltx) was found." + set_property PROBES.FILE "" $hw_fpga_name + } + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished property functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + # ----------------------------------------------------------------------------------------------------------------------------------------- + # programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + #-------------------------------- + #--hw_program_fpga_device: + proc hw_program_fpga_device { use_basefolder appname {fname ""}} { + #bitfile + set return_filename "" + set partname_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + } else { + set partname_int $TE::PARTNAME + } + set hw_fpga_name [hw_get_fpga $partname_int] + + if {![catch {set return_filename [hw_set_bit_and_ltx_files $use_basefolder $appname $fname]}] } { + program_hw_devices $hw_fpga_name + TE::UTILS::te_msg TE_PR-32 INFO "Programming BIT-file finished." + if {[catch {refresh_hw_device $hw_fpga_name}] } {} + } else { + TE::UTILS::te_msg TE_PR-33 ERROR "Program FPGA failed." + return -code error + } + return $return_filename + } + #-------------------------------- + #--hw_program_fpga_flash: + proc hw_program_fpga_flash {use_basefolder term bin appname {fname ""}} { + set return_filename "" + set partname_int "" + if {$fname ne ""} { + set partname_int "[TE::BDEF::find_partname $fname]" + } else { + set partname_int $TE::PARTNAME + } + set hw_fpga_name [hw_get_fpga $partname_int] + if {$bin eq "bin"} { + #program bin file + if {![catch {set return_filename [hw_set_bin_and_ltx_files $use_basefolder $appname $fname]}] } { + program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + TE::UTILS::te_msg TE_PR-34 INFO "Programming BIN-file finished." + if {[catch {refresh_hw_device $hw_fpga_name}] } {} + } else { + TE::UTILS::te_msg TE_PR-35 ERROR "Program Flash failed." + return -code error + } + } else { + #program mcs file + if {![catch {set return_filename [hw_set_mcs_and_ltx_files $use_basefolder $term $appname $fname]}] } { + if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE $hw_fpga_name] [get_property MEM_TYPE [get_property CFGMEM_PART [get_property PROGRAM.HW_CFGMEM $hw_fpga_name]]]] } { create_hw_bitstream -hw_device $hw_fpga_name [get_property PROGRAM.HW_CFGMEM_BITFILE $hw_fpga_name]; program_hw_devices $hw_fpga_name; }; + program_hw_cfgmem -hw_cfgmem [get_property PROGRAM.HW_CFGMEM $hw_fpga_name] + TE::UTILS::te_msg TE_PR-36 INFO "Programming MCS-file finished." + if {[catch {refresh_hw_device $hw_fpga_name}] } {} + } else { + TE::UTILS::te_msg TE_PR-37 ERROR "Program Flash failed." + return -code error + } + } + return $return_filename + } + # ----------------------------------------------------------------------------------------------------------------------------------------- + # finished programming functions + # ----------------------------------------------------------------------------------------------------------------------------------------- + + + + # ----------------------------------------------------------------------------------------------------------------------------------------- + } + + puts "INFO:(TE) Load Vivado script finished" +} + + diff --git a/zynqberrydemo3/settings/project_settings.tcl b/zynqberrydemo3/settings/project_settings.tcl new file mode 100644 index 0000000..777dc02 --- /dev/null +++ b/zynqberrydemo3/settings/project_settings.tcl @@ -0,0 +1,2 @@ +set_property flow {Vivado Implementation 2017} [get_runs ${TE::IMPL_NAME}] +set_property strategy Performance_Explore [get_runs ${TE::IMPL_NAME}] diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/data/zynq_fsbl.tcl b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/data/zynq_fsbl.tcl new file mode 100644 index 0000000..e072f6f --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/data/zynq_fsbl.tcl @@ -0,0 +1,97 @@ +proc swapp_get_name {} { + return "Zynq FSBL - TE modified"; +} + +proc swapp_get_description {} { + return "First Stage Bootloader (FSBL) for Zynq. The FSBL configures the FPGA with HW bit stream (if it exists) \ + and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the \ + non-volatile memory (NAND/NOR/QSPI) to RAM (DDR) and starts executing it. It supports multiple partitions, \ + and each partition can be a code image or a bit stream.\ + TE-Modification: Modified HDMI Output DMA and Camera Input DMA on fsbl_hooks.c. Add. vdma.h, vdma.c\ + FSBL Template: 2017.1 \ + "; +} + +proc swapp_get_supported_processors {} { + return "ps7_cortexa9"; +} + +proc swapp_get_supported_os {} { + return "standalone"; +} + +proc check_standalone_os {} { + set oslist [hsi::get_os]; + + if { [llength $oslist] != 1 } { + return 0; + } + set os [lindex $oslist 0]; + + if { $os != "standalone" } { + error "This application is supported only on the Standalone Board Support Package."; + } +} + +proc swapp_is_supported_sw {} { + # make sure we are using standalone OS + #check_standalone_os; + + # make sure xilffs and xilrsa libraries are available + + set librarylist_1 [hsi::get_libs -filter "NAME==xilffs"]; + + + if { [llength $librarylist_1] == 0 } { + error "This application requires xilffs library in the Board Support Package."; + } +} + +proc swapp_is_supported_hw {} { + + # check processor type + set proc_instance [hsi::get_sw_processor]; + set hw_processor [common::get_property HW_INSTANCE $proc_instance] + + set proc_type [common::get_property IP_NAME [hsi::get_cells -hier $hw_processor]]; + + if { $proc_type != "ps7_cortexa9" } { + error "This application is supported only for CortexA9 processors."; + } + + return 1; +} + + +proc get_stdout {} { + set os [hsi::get_os]; + set stdout [common::get_property CONFIG.STDOUT $os]; + return $stdout; +} + +proc check_stdout_hw {} { + set p7_uarts [hsi::get_cells -hier -filter "IP_NAME=ps7_uart"]; +} + +proc swapp_generate {} { + # generate/copy ps init files + ::hsi::utils::generate_psinit + + #delete unnecessary files (only ps7_init.c & ps7_init.h are needed for FSBL) + + set files(0) "ps7_init.html" + set files(1) "ps7_init.tcl" + set files(2) "ps7_init_gpl.c" + set files(3) "ps7_init_gpl.h" + + foreach init_file [array get files] { + file delete -force $init_file + } + +} + +proc swapp_get_linker_constraints {} { + + # don't generate a linker script. fsbl has its own linker script + return "lscript no"; +} diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl.h new file mode 100644 index 0000000..a0cf67b --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl.h @@ -0,0 +1,546 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file fsbl.h +* +* Contains the function prototypes, defines and macros for the +* First Stage Boot Loader (FSBL) functionality +* +* 

    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a	jz	03/04/11	Initial release
+* 2.00a	mb 	06/06/12	Removed the qspi define, will be picked from
+*						xparameters.h file
+* 3.00a np/mb 08/08/12	Added the error codes for the FSBL hook errors.
+* 						Added the debug levels
+* 4.00a sgd 02/28/13	Removed DDR initialization check
+*                       Removed DDR ECC initialization code
+*						Modified hand off address check to 1MB
+*						Added RSA authentication support
+*						Removed LPBK_DLY_ADJ register setting code as we use
+* 					 	divisor 8
+*						Removed check for Fabric is already initialized
+*
+* 						CR's fixed and description
+* 						689026:	FSBL doesn't hold PL resets active during
+* 						bit download
+* 						Resolution: PL resets are released just before
+* 						handoff
+*
+* 						689077:	FSBL hangs at Handoff clearing the
+* 						TX UART buffer
+*						Resolution: STDOUT_BASEADDRESS macro value changes
+*						based UART select, hence used STDOUT_BASEADDRESS
+*						as UART base address
+*
+* 						695578: FSBL failed to load standalone application
+* 						in secure bootmode
+*               		Resolution: Application will be placed at load address
+*               		instead of DDR temporary address
+*
+*               		699475: FSBL functionality is broken and its
+*               		not able to boot in QSPI/NAND bootmode
+*               		Resolution: New flags are added DevCfg driver
+*               		for handling loopback
+*               		XDCFG_CONCURRENT_NONSEC_READ_WRITE
+*                       XDCFG_CONCURRENT_SECURE_READ_WRITE
+*
+*               		683145: Define stack area for FIQ, UNDEF modes
+*               		in linker file
+*               		Resolution: FSBL linker modified to create stack area
+*               		for FIQ, UNDEF
+*                       
+*                       705664: FSBL fails to decrypt the bitstream when 
+*                       the image is AES encrypted using non-zero key value
+*                       Resolution: Fabric cleaning will not be done
+*                       for AES-E-Fuse encryption
+*                       
+*                       Watchdog disabled for AES E-Fuse encryption
+*
+* 5.00a sgd 05/17/13    Fallback support for E-Fuse encryption
+*                       Added QSPI Flash Size > 128Mbit support
+* 					    QSPI Dual Stack support
+* 					    Added Md5 checksum support
+*
+*                       CR's fixed and description
+*                       692045	FSBL: Linker script of FSBL has PHDR workaround,
+* 					    this needs to be fixed
+* 					    Resolution: Removed PHDR from Linker file
+*                       
+*                       704287	FSBL: fsbl.h file has a few error codes that 
+*                       are not used by FSBL, that needs to be removed
+*                       Resolution: Removed unused error codes
+*
+*                       704379	FSBL: Check if DDR is in proper state before
+*                       handoff
+* 					    Resolution: Added DDR initialization check
+* 					                           
+*                       709077	If FSBL_DEBUG and FSBL_DEBUG_INFO are defined, 
+*                       the debug level is FSBL_DEBUG only.
+*                       
+*                       710128 FSBL: Linux boot failing without load attribute
+*                       set for Linux partitions in BIF
+*                       Resolution: FSBL will load partitions with valid load
+*                       address and stop loading if any invalid load address
+*
+*                       708728 Issues seen while making HP interconnect
+*                       32 bit wide
+*                       Resolution: ps7_post_config function generated by PCW
+*                       will be called after Bit stream download
+*                       Added MMC support
+* 6.00a	kc	07/31/2013	CR's fixed and description
+* 						724166 FSBL doesn’t use PPK authenticated by Boot ROM
+* 						 for authenticating the Partition images
+* 						Resolution: FSBL now uses the PPK left by Boot ROM in
+* 						OCM for authencating the SPK
+*
+* 						724165 Partition Header used by FSBL is not
+* 						authenticated
+* 						Resolution: FSBL now authenticates the partition header
+*
+* 						691150 ps7_init does not check for peripheral
+* 						initialization failures or timeout on polls
+* 						Resolution: Return value of ps7_init() is now checked
+* 						by FSBL and prints the error string
+*
+* 						708316  PS7_init.tcl file should have Error mechanism
+* 						for all mask_poll
+* 						Resolution: Return value of ps7_init() is now checked
+* 						by FSBL and prints the error string
+*
+* 						732062 FSBL fails to build if UART not available
+* 						Resolution: Added define to call xil_printf only
+* 						if uart is defined
+*
+* 						722979 Provide customer-friendly changelogs in FSBL
+* 						Resolution: Added CR description for all the files
+*
+* 						732865 Backward compatibility for ps7_init function
+*						Resolution: Added a new define for ps7_init success
+*						and value is defined based on ps7_init define
+*
+*						Fix for CR#739711 - FSBL not able to read Large
+*						QSPI (512M) in IO Mode
+*						Resolution: Modified the address calculation
+*						algorithm in dual parallel mode for QSPI
+*
+* 7.00a kc  10/18/13    Integrated SD/MMC driver
+*			10/23/13	Support for armcc compiler added
+*						741003 FSBL has to check the HMAC error status after 
+*						decryption
+*						Resolution: Added code for checking the error status 
+*						after PCAP completion
+*						739968 FSBL should do the QSPI config settings for 
+*						Dual parallel configuration in IO mode
+*						Resolution: Added QSPI config settings in qspi.c
+*						724620 FSBL: How to handle PCAP_MODE after bitstream 
+*						configuration.
+*						Resolution: PCAP_MODE and PCAP_PR bits are now cleared  
+* 						after PCAP transfer completion
+*						726178 In the 14.6 FSBL function FabricInit() PROG_B 
+*						is kept active for 5mS.
+*						Resolution: PROG_B is now kept active for 5mS only incase 
+*						if efuse is the aes key source.
+*						755245 FSBL does not load partition if eMMC has only 
+*						one partition
+*						Resolution: Changed the if condition for MMC
+*			12/04/13    764382 FSBL: How to handle PCAP_MODE after bitstream 
+*						configuration
+*						Resolution: Reverted back the changes of 724620. PCAP_MODE
+*						and PCAP_PR bits are not changed
+* 8.00a kc  01/16/13    767798 Fsbl MD5 Checksum failiure for encrypted images
+* 						Resolution: For checksum enabled partitions, total 
+*						total partition image length is copied now.
+*						761895 FSBL should authenticate image only if
+*						partition owner was not set to u-boot
+*						Resolution: Partition owner check added in 
+*						image_mover.c
+* 			02/20/14	775631 - FSBL: FsblGetGlobalTimer() is not proper
+*						Resolution: Function argument is updated from value
+*						to pointer to reflect updated value
+* 9.00a kc  04/16/14	773866 - SetPpk() will fail on secure fallback
+*						unless FSBL* and FSBL are identical in length
+*						Resolution: PPK is set only once now.
+*						785778 - FSBL takes 8 seconds to
+* 						authenticate (RSA) a bitstream on zc706
+* 						Resolution: Data Caches are enabled only for
+* 						authentication.
+* 						791245 - Use of xilrsa in fsbl
+* 						Resolution: Rsa library is removed from fsbl source
+* 						and xilrsa is used from BSP
+* 10.00a kc 07/15/14	804595 Zynq FSBL - Issues with
+* 						fallback image offset handling using MD5
+* 						Resolution: Updated the checksum offset to add with
+* 						image base address
+* 						782309 Fallback support for AES
+* 						encryption with E-Fuse - Enhancement
+* 						Resolution: Same as 773866
+* 						809336 Minor code cleanup
+* 						Resolution Minor code changes
+*        kc 08/27/14	820356 - FSBL compilation fails with IAR compiler
+* 						Resolution: Change of __asm__ to __asm
+* 11.00a kv 10/08/14	826030 - FSBL:LinearBootDeviceFlag is not initialized
+*						in IO mode case.Due to which the variable is
+*						remaining in unknown state.
+*						Resolution: LinearBootDeviceFlag is initialized 0
+*						in main.c
+* 12.00a ssc 12/11/14	839182 - FSBL -In the file sd.c, f_mount is called with
+*                       two arguments but f_mount is expecting the 3 arguments
+*                       from build 2015.1_1210_1, causing compilation error.
+*						Resolution: Arguments for f_mount in InitSD() are
+*						changed as per new signature.
+* 13.00a ssc 04/10/15	846899 - FSBL -In the file pcap.c, to clear DMA done
+*                       count, devcfg.INT_STS register is written to, which is
+*                       not correct.
+*                       Resolution: Corresponding fields in the devcfg.STATUS
+*                       register are written to, for clearing DMA done count.
+* 14.00a gan 01/13/16   869081 -(2016.1)FSBL -In qspi.c, FSBL picks the qspi
+*						read command from LQSPI_CFG register instead of hard
+*		   				coded read command (0x6B).
+* 15.00a gan 07/21/16   953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
+* 						Fabric Initialization sequence is modified to check
+* 						the PL power before sequence starts and checking INIT_B
+* 						reset status twice in case of failure.
+* 16.00a gan 08/02/16   Fix for CR# 955897 -(2016.3)FSBL -
+* 						In pcap.c, check pl power through MCTRL register
+* 						for 3.0 and later versions of silicon.
+*
    +* +* +* +* @note +* +* Flags in FSBL +* +* FSBL_PERF +* +* This Flag can be set at compilation time. This flag is set for +* measuring the performance of FSBL.That is the time taken to execute is +* measured.when this flag is set.Execution time with reference to +* global timer is taken here +* +* Total Execution time is the time taken for executing FSBL till handoff +* to any application . +* If there is a bitstream in the partition header then the +* execution time includes the copying of the bitstream to DDR +* (in case of SD/NAND bootmode) +* and programming the devcfg dma is accounted. +* +* FSBL provides two debug levels +* DEBUG GENERAL - fsbl_printf under this category will appear only when the +* FSBL_DEBUG flag is set during compilation +* DEBUG_INFO - fsbl_printf under this category will appear when the +* FSBL_DEBUG_INFO flag is set during compilation +* For a more detailed output log can be used. +* FSBL_DEBUG_RSA - Define this macro to print more detailed values used in +* RSA functions +* These macros are input to the fsbl_printf function +* +* DEBUG LEVELS +* FSBL_DEBUG level is level 1, when this flag is set all the fsbl_prints +* that are with the DEBUG_GENERAL argument are shown +* FSBL_DEBUG_INFO is level 2, when this flag is set during the +* compilation , the fsbl_printf with DEBUG_INFO will appear on the com port +* +* DEFAULT LEVEL +* By default no print messages will appear. +* +* NON_PS_INSTANTIATED_BITSTREAM +* +* FSBL will not enable the level shifters for a NON PS instantiated +* Bitstream.This flag can be set during compilation for a NON PS instantiated +* bitstream +* +* ECC_ENABLE +* This flag will be defined in the ps7_init.h file when ECC is enabled +* in the DDR configuration (XPS GUI) +* +* RSA_SUPPORT +* This flag is used to enable authentication feature +* Default this macro disabled, reason to avoid increase in code size +* +* MMC_SUPPORT +* This flag is used to enable MMC support feature +* +*******************************************************************************/ +#ifndef XIL_FSBL_H +#define XIL_FSBL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xparameters.h" +#include "xpseudo_asm.h" +#include "xil_printf.h" +#include "pcap.h" +#include "fsbl_debug.h" +#include "ps7_init.h" +#ifdef FSBL_PERF +#include "xtime_l.h" +#include +#endif + + +/************************** Constant Definitions *****************************/ +/* + * SDK release version + */ +#define SDK_RELEASE_YEAR 2017 +#define SDK_RELEASE_QUARTER 1 + +#define WORD_LENGTH_SHIFT 2 + +/* + * On a Successful handoff to an application FSBL sets this SUCCESS code + */ +#define SUCCESSFUL_HANDOFF 0x1 /* Successful Handoff */ + +/* + * Backward compatibility for ps7_init + */ +#ifdef NEW_PS7_ERR_CODE +#define FSBL_PS7_INIT_SUCCESS PS7_INIT_SUCCESS +#else +#define FSBL_PS7_INIT_SUCCESS (1) +#endif + +/* + * ERROR CODES + * The following are the Error codes that FSBL uses + * If the Debug prints are enabled only then the error codes will be + * seen on the com port.Without the debug prints enabled no error codes will + * be visible.There are not saved in any register + * Boot Mode States used for error and status output + * Error codes are defined below + */ +#define ILLEGAL_BOOT_MODE 0xA000 /**< Illegal boot mode */ +#define ILLEGAL_RETURN 0xA001 /**< Illegal return */ +#define PCAP_INIT_FAIL 0xA002 /**< Pcap driver Init Failed */ +#define DECRYPTION_FAIL 0xA003 /**< Decryption Failed */ +#define BITSTREAM_DOWNLOAD_FAIL 0xA004 /**< Bitstream download fail */ +#define DMA_TRANSFER_FAIL 0xA005 /**< DMA Transfer Fail */ +#define INVALID_FLASH_ADDRESS 0xA006 /**< Invalid Flash Address */ +#define DDR_INIT_FAIL 0xA007 /**< DDR Init Fail */ +#define NO_DDR 0xA008 /**< DDR missing */ +#define SD_INIT_FAIL 0xA009 /**< SD Init fail */ +#define NAND_INIT_FAIL 0xA00A /**< Nand Init Fail */ +#define PARTITION_MOVE_FAIL 0xA00B /**< Partition move fail */ +#define AUTHENTICATION_FAIL 0xA00C /**< Authentication fail */ +#define INVALID_HEADER_FAIL 0xA00D /**< Invalid header fail */ +#define GET_HEADER_INFO_FAIL 0xA00E /**< Get header fail */ +#define INVALID_LOAD_ADDRESS_FAIL 0xA00F /**< Invalid load address fail */ +#define PARTITION_CHECKSUM_FAIL 0xA010 /**< Partition checksum fail */ +#define RSA_SUPPORT_NOT_ENABLED_FAIL 0xA011 /**< RSA not enabled fail */ +#define PS7_INIT_FAIL 0xA012 /**< ps7 Init Fail */ +/* + * FSBL Exception error codes + */ +#define EXCEPTION_ID_UNDEFINED_INT 0xA301 /**< Undefined INT Exception */ +#define EXCEPTION_ID_SWI_INT 0xA302 /**< SWI INT Exception */ +#define EXCEPTION_ID_PREFETCH_ABORT_INT 0xA303 /**< Prefetch Abort xception */ +#define EXCEPTION_ID_DATA_ABORT_INT 0xA304 /**< Data Abort Exception */ +#define EXCEPTION_ID_IRQ_INT 0xA305 /**< IRQ Exception Occurred */ +#define EXCEPTION_ID_FIQ_INT 0xA306 /**< FIQ Exception Occurred */ + +/* + * FSBL hook routine failures + */ +#define FSBL_HANDOFF_HOOK_FAIL 0xA401 /**< FSBL handoff hook failed */ +#define FSBL_BEFORE_BSTREAM_HOOK_FAIL 0xA402 /**< FSBL before bit stream + download hook failed */ +#define FSBL_AFTER_BSTREAM_HOOK_FAIL 0xA403 /**< FSBL after bitstream + download hook failed */ + +/* + * Watchdog related Error codes + */ +#define WDT_RESET_OCCURED 0xA501 /**< WDT Reset happened in FSBL */ +#define WDT_INIT_FAIL 0xA502 /**< WDT driver INIT failed */ + +/* + * SLCR Registers + */ +#define PS_RST_CTRL_REG (XPS_SYS_CTRL_BASEADDR + 0x200) +#define FPGA_RESET_REG (XPS_SYS_CTRL_BASEADDR + 0x240) +#define RESET_REASON_REG (XPS_SYS_CTRL_BASEADDR + 0x250) +#define RESET_REASON_CLR (XPS_SYS_CTRL_BASEADDR + 0x254) +#define REBOOT_STATUS_REG (XPS_SYS_CTRL_BASEADDR + 0x258) +#define BOOT_MODE_REG (XPS_SYS_CTRL_BASEADDR + 0x25C) +#define PS_LVL_SHFTR_EN (XPS_SYS_CTRL_BASEADDR + 0x900) + +/* + * Efuse Status Register + */ +#define EFUSE_STATUS_REG (0xF800D010) /**< Efuse Status Register */ +#define EFUSE_STATUS_RSA_ENABLE_MASK (0x400) /**< Status of RSA enable */ + +/* + * PS reset control register define + */ +#define PS_RST_MASK 0x1 /**< PS software reset */ + +/* + * SLCR BOOT Mode Register defines + */ +#define BOOT_MODES_MASK 0x00000007 /**< FLASH types */ + +/* + * Boot Modes + */ +#define JTAG_MODE 0x00000000 /**< JTAG Boot Mode */ +#define QSPI_MODE 0x00000001 /**< QSPI Boot Mode */ +#define NOR_FLASH_MODE 0x00000002 /**< NOR Boot Mode */ +#define NAND_FLASH_MODE 0x00000004 /**< NAND Boot Mode */ +#define SD_MODE 0x00000005 /**< SD Boot Mode */ +#define MMC_MODE 0x00000006 /**< MMC Boot Device */ + +#define RESET_REASON_SRST 0x00000020 /**< Reason for reset is SRST */ +#define RESET_REASON_SWDT 0x00000001 /**< Reason for reset is SWDT */ + +/* + * Golden image offset + */ +#define GOLDEN_IMAGE_OFFSET 0x8000 + +/* + * Silicon Version + */ +#define SILICON_VERSION_1 0 +#define SILICON_VERSION_2 1 +#define SILICON_VERSION_3 2 +#define SILICON_VERSION_3_1 3 + +/* + * DDR start address for storing the data temporarily(1M) + * Need to finalize correct logic + */ +#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR +#define DDR_START_ADDR XPAR_PS7_DDR_0_S_AXI_BASEADDR +#define DDR_END_ADDR XPAR_PS7_DDR_0_S_AXI_HIGHADDR +#else +/* + * In case of PL DDR, this macros defined based PL DDR address + */ +#define DDR_START_ADDR 0x00 +#define DDR_END_ADDR 0x00 +#endif + +#define DDR_TEMP_START_ADDR DDR_START_ADDR +/* + * DDR test pattern + */ +#define DDR_TEST_PATTERN 0xAA55AA55 +#define DDR_TEST_OFFSET 0x100000 +/* + * + */ +#define QSPI_DUAL_FLASH_SIZE 0x2000000; /*32MB*/ +#define QSPI_SINGLE_FLASH_SIZE 0x1000000; /*16MB*/ +#define NAND_FLASH_SIZE 0x8000000; /*128MB*/ +#define NOR_FLASH_SIZE 0x2000000; /*32MB*/ +#define LQSPI_CFG_OFFSET 0xA0 +#define LQSPI_CFG_DUAL_FLASH_MASK 0x40000000 + +/* + * These are the SLCR lock and unlock macros + */ +#define SlcrUnlock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x08, 0xDF0DDF0D) +#define SlcrLock() Xil_Out32(XPS_SYS_CTRL_BASEADDR + 0x04, 0x767B767B) + +#define IMAGE_HEADER_CHECKSUM_COUNT 10 + +/* Boot ROM Image defines */ +#define IMAGE_WIDTH_CHECK_OFFSET (0x020) /**< 0xaa995566 Width Detection word */ +#define IMAGE_IDENT_OFFSET (0x024) /**< 0x584C4E58 "XLNX" */ +#define IMAGE_ENC_FLAG_OFFSET (0x028) /**< 0xA5C3C5A3 */ +#define IMAGE_USR_DEF_OFFSET (0x02C) /**< undefined could be used as */ +#define IMAGE_SOURCE_ADDR_OFFSET (0x030) /**< start address of image */ +#define IMAGE_BYTE_LEN_OFFSET (0x034) /**< length of image> in bytes */ +#define IMAGE_DEST_ADDR_OFFSET (0x038) /**< destination address in OCM */ +#define IMAGE_EXECUTE_ADDR_OFFSET (0x03c) /**< address to start executing at */ +#define IMAGE_TOT_BYTE_LEN_OFFSET (0x040) /**< total length of image in bytes */ +#define IMAGE_QSPI_CFG_WORD_OFFSET (0x044) /**< QSPI configuration data */ +#define IMAGE_CHECKSUM_OFFSET (0x048) /**< Header Checksum offset */ +#define IMAGE_IDENT (0x584C4E58) /**< XLNX pattern */ + +/* Reboot status register defines: + * 0xF0000000 for FSBL fallback mask to notify Boot Rom + * 0x60000000 for FSBL to mark that FSBL has not handoff yet + * 0x00FFFFFF for user application to use across soft reset + */ +#define FSBL_FAIL_MASK 0xF0000000 +#define FSBL_IN_MASK 0x60000000 + +/* The address that holds the base address for the image Boot ROM found */ +#define BASEADDR_HOLDER 0xFFFFFFF8 + +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ + +void OutputStatus(u32 State); +void FsblFallback(void); + +int FsblSetNextPartition(int Num); +void *(memcpy_rom)(void * s1, const void * s2, u32 n); +char *strcpy_rom(char *Dest, const char *Src); + +void ClearFSBLIn(void); +void MarkFSBLIn(void); +void FsblHandoff(u32 FsblStartAddr); +u32 GetResetReason(void); + +#ifdef FSBL_PERF +void FsblGetGlobalTime (XTime * tCur); +void FsblMeasurePerfTime (XTime tCur, XTime tEnd); +#endif +void GetSiliconVersion(void); +void FsblHandoffExit(u32 FsblStartAddr); +void FsblHandoffJtagExit(); +/************************** Variable Definitions *****************************/ +extern int SkipPartition; + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_debug.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_debug.h new file mode 100644 index 0000000..2c41c23 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_debug.h @@ -0,0 +1,82 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file fsbl_debug.h +* +* This file contains the debug verbose information for FSBL print functionality +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a mb	01/09/12 Initial release
+*
+*
    +* +* @note +* +******************************************************************************/ + +#ifndef _FSBL_DEBUG_H +#define _FSBL_DEBUG_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#define DEBUG_GENERAL 0x00000001 /* general debug messages */ +#define DEBUG_INFO 0x00000002 /* More debug information */ + +#if defined (FSBL_DEBUG_INFO) +#define fsbl_dbg_current_types ((DEBUG_INFO) | (DEBUG_GENERAL)) +#elif defined (FSBL_DEBUG) +#define fsbl_dbg_current_types (DEBUG_GENERAL) +#else +#define fsbl_dbg_current_types 0 +#endif + +#ifdef STDOUT_BASEADDRESS +#define fsbl_printf(type,...) \ + if (((type) & fsbl_dbg_current_types)) {xil_printf (__VA_ARGS__); } +#else +#define fsbl_printf(type, ...) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _FSBL_DEBUG_H */ diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c new file mode 100644 index 0000000..e3cab04 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.c @@ -0,0 +1,206 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/***************************************************************************** +* +* @file fsbl_hooks.c +* +* This file provides functions that serve as user hooks. The user can add the +* additional functionality required into these routines. This would help retain +* the normal FSBL flow unchanged. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver   Who  Date        Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a np   08/03/12 Initial release
+*
    +* +* @note +* +******************************************************************************/ + + +#include "fsbl.h" +#include "xstatus.h" +#include "fsbl_hooks.h" + +#include "vdma.h" +#include "xparameters.h" +#include "xil_hal.h" +#include "sleep.h" + +#include "xvtc.h" + +#define ENABLE_CAMERA +// #define DIRECT_CAMERA_VIEW + +#ifdef DIRECT_CAMERA_VIEW +#define HDMI_FB_ADDR 0x1FC00000 +#define CAMERA_FB_ADDR 0x1FC00000 +#endif + +#ifndef DIRECT_CAMERA_VIEW +#define HDMI_FB_ADDR 0x1FC00000 +#define CAMERA_FB_ADDR 0x1F700000 +#endif +/************************** Variable Definitions *****************************/ + + +/************************** Function Prototypes ******************************/ + + +/****************************************************************************** +* This function is the hook which will be called before the bitstream download. +* The user can add all the customized code required to be executed before the +* bitstream download to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 FsblHookBeforeBitstreamDload(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + /* + * User logic to be added here. Errors to be stored in the status variable + * and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookBeforeBitstreamDload function \r\n"); + + return (Status); +} + +/****************************************************************************** +* This function is the hook which will be called after the bitstream download. +* The user can add all the customized code required to be executed after the +* bitstream download to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 FsblHookAfterBitstreamDload(void) +{ + u32 Status; + + Status = XST_SUCCESS; + + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO, "In FsblHookAfterBitstreamDload function \r\n"); + + return (Status); +} + +/****************************************************************************** +* This function is the hook which will be called before the FSBL does a handoff +* to the application. The user can add all the customized code required to be +* executed before the handoff to this routine. +* +* @param None +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +****************************************************************************/ +u32 FsblHookBeforeHandoff(void) +{ + u32 Status; + + Status = XST_SUCCESS; + XVtc Vtc; + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookBeforeHandoff function \r\n"); + + xil_printf("FSBL: Enabling VTC..\n\r"); + XVtc_Config *Config; + Config = XVtc_LookupConfig(XPAR_VTC_0_DEVICE_ID); + if (NULL == Config) { + xil_printf("XVtc_LookupConfig failure\r\n"); + return XST_FAILURE; + } + + Status = XVtc_CfgInitialize(&Vtc, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("XVtc_CfgInitialize failure\r\n"); + return XST_FAILURE; + } + + XVtc_DisableSync(&Vtc); + XVtc_EnableGenerator(&Vtc); + + xil_printf("FSBL: Enabling Out VDMA at 0x%08x..\n\r",HDMI_FB_ADDR); + vdma_out_init(XPAR_VIDEO_OUT_AXI_VDMA_0_DEVICE_ID, HDMI_FB_ADDR, 1280, 720, 4); +#ifdef ENABLE_CAMERA + xil_printf("FSBL: Enabling In VDMA at 0x%08x..\n\r",CAMERA_FB_ADDR); + vdma_in_init(XPAR_VIDEO_IN_AXI_VDMA_0_DEVICE_ID, CAMERA_FB_ADDR, 1280, 720, 4); +#endif + return (Status); +} + + +/****************************************************************************** +* This function is the hook which will be called in case FSBL fall back +* +* @param None +* +* @return None +* +****************************************************************************/ +void FsblHookFallback(void) +{ + /* + * User logic to be added here. + * Errors to be stored in the status variable and returned + */ + fsbl_printf(DEBUG_INFO,"In FsblHookFallback function \r\n"); + while(1); +} + + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h new file mode 100644 index 0000000..784f7ed --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/fsbl_hooks.h @@ -0,0 +1,81 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file fsbl_hooks.h +* +* Contains the function prototypes, defines and macros required by fsbl_hooks.c +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 3.00a	np/mb	10/08/12	Initial release
+*				Corrected the prototype
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef FSBL_HOOKS_H_ +#define FSBL_HOOKS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "fsbl.h" + + +/************************** Function Prototypes ******************************/ + +/* FSBL hook function which is called before bitstream download */ +u32 FsblHookBeforeBitstreamDload(void); + +/* FSBL hook function which is called after bitstream download */ +u32 FsblHookAfterBitstreamDload(void); + +/* FSBL hook function which is called before handoff to the application */ +u32 FsblHookBeforeHandoff(void); + +/* FSBL hook function which is called in FSBL fallback */ +void FsblHookFallback(void); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/image_mover.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/image_mover.c new file mode 100644 index 0000000..1bad673 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/image_mover.c @@ -0,0 +1,1335 @@ +/****************************************************************************** +* +* Copyright (C) 2011 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file image_mover.c +* +* Move partitions to either DDR to execute or to program FPGA. +* It performs partition walk. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz	05/24/11	Initial release
+* 2.00a jz	06/30/11	Updated partition header defs for 64-byte
+*			 			alignment change in data2mem tool
+* 2.00a mb	05/25/12	Updated for standalone based bsp FSBL
+* 			 			Nand/SD encryption and review comments
+* 3.00a np	08/30/12	Added FSBL user hook calls
+* 						(before and after bitstream download.)
+* 4.00a sgd	02/28/13	Fix for CR#691148 Secure bootmode error in devcfg test
+*						Fix for CR#695578 FSBL failed to load standalone 
+*						application in secure bootmode
+*
+* 4.00a sgd	04/23/13	Fix for CR#710128 FSBL failed to load standalone 
+*						application in secure bootmode
+* 5.00a kc	07/30/13	Fix for CR#724165 Partition Header used by FSBL 
+*						is not authenticated
+* 						Fix for CR#724166 FSBL doesn�t use PPK authenticated 
+*						by Boot ROM for authenticating the Partition images 
+* 						Fix for CR#732062 FSBL fails to build if UART not 
+*						available 
+* 7.00a kc  10/30/13    Fix for CR#755245 FSBL does not load partition
+*                       if eMMC has only one partition
+* 8.00a kc  01/16/13    Fix for CR#767798  FSBL MD5 Checksum failure
+* 						for encrypted images
+*						Fix for CR#761895 FSBL should authenticate image
+*						only if partition owner was not set to u-boot
+* 9.00a kc  04/16/14    Fix for CR#785778  FSBL takes 8 seconds to 
+* 						authenticate (RSA) a bitstream on zc706
+* 10.00a kc 07/15/14	Fix for CR#804595 Zynq FSBL - Issues with
+* 						fallback image offset handling using MD5
+* 						Fix for PR#782309 Fallback support for AES
+* 						encryption with E-Fuse - Enhancement
+*
+*
    +* +* @note +* A partition is either an executable or a bitstream to program FPGA +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "fsbl.h" +#include "image_mover.h" +#include "xil_printf.h" +#include "xreg_cortexa9.h" +#include "pcap.h" +#include "fsbl_hooks.h" +#include "md5.h" + +#ifdef XPAR_XWDTPS_0_BASEADDR +#include "xwdtps.h" +#endif + +#ifdef RSA_SUPPORT +#include "rsa.h" +#include "xil_cache.h" +#endif +/************************** Constant Definitions *****************************/ + +/* We are 32-bit machine */ +#define MAXIMUM_IMAGE_WORD_LEN 0x40000000 +#define MD5_CHECKSUM_SIZE 16 + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset); +u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum); +u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum); + +/************************** Variable Definitions *****************************/ +/* + * Partition information flags + */ +u8 EncryptedPartitionFlag; +u8 PLPartitionFlag; +u8 PSPartitionFlag; +u8 SignedPartitionFlag; +u8 PartitionChecksumFlag; +u8 BitstreamFlag; +u8 ApplicationFlag; + +u32 ExecutionAddress; +ImageMoverType MoveImage; + +/* + * Header array + */ +PartHeader PartitionHeader[MAX_PARTITION_NUMBER]; +u32 PartitionCount; +u32 FsblLength; + +#ifdef XPAR_XWDTPS_0_BASEADDR +extern XWdtPs Watchdog; /* Instance of WatchDog Timer */ +#endif + +extern u32 Silicon_Version; +extern u32 FlashReadBaseAddress; +extern u8 LinearBootDeviceFlag; +extern XDcfg *DcfgInstPtr; + +/*****************************************************************************/ +/** +* +* This function +* +* @param +* +* @return +* +* +* @note None +* +****************************************************************************/ +u32 LoadBootImage(void) +{ + u32 RebootStatusRegister = 0; + u32 MultiBootReg = 0; + u32 ImageStartAddress = 0; + u32 PartitionNum; + u32 PartitionDataLength; + u32 PartitionImageLength; + u32 PartitionTotalSize; + u32 PartitionExecAddr; + u32 PartitionAttr; + u32 ExecAddress = 0; + u32 PartitionLoadAddr; + u32 PartitionStartAddr; + u32 PartitionChecksumOffset; + u8 ExecAddrFlag = 0 ; + u32 Status; + PartHeader *HeaderPtr; + u32 EfuseStatusRegValue; +#ifdef RSA_SUPPORT + u32 HeaderSize; +#endif + /* + * Resetting the Flags + */ + BitstreamFlag = 0; + ApplicationFlag = 0; + + RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG); + fsbl_printf(DEBUG_INFO, + "Reboot status register: 0x%08lx\r\n",RebootStatusRegister); + + if (Silicon_Version == SILICON_VERSION_1) { + /* + * Clear out fallback mask from previous run + * We start from the first partition again + */ + if ((RebootStatusRegister & FSBL_FAIL_MASK) == + FSBL_FAIL_MASK) { + fsbl_printf(DEBUG_INFO, + "Reboot status shows previous run falls back\r\n"); + RebootStatusRegister &= ~(FSBL_FAIL_MASK); + Xil_Out32(REBOOT_STATUS_REG, RebootStatusRegister); + } + + /* + * Read the image start address + */ + ImageStartAddress = *(u32 *)BASEADDR_HOLDER; + } else { + /* + * read the multiboot register + */ + MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET); + + fsbl_printf(DEBUG_INFO,"Multiboot Register: 0x%08lx\r\n",MultiBootReg); + + /* + * Compute the image start address + */ + ImageStartAddress = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK) + * GOLDEN_IMAGE_OFFSET; + } + + fsbl_printf(DEBUG_INFO,"Image Start Address: 0x%08lx\r\n",ImageStartAddress); + + /* + * Get partitions header information + */ + Status = GetPartitionHeaderInfo(ImageStartAddress); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Partition Header Load Failed\r\n"); + OutputStatus(GET_HEADER_INFO_FAIL); + FsblFallback(); + } + + /* + * RSA is not implemented in 1.0 and 2.0 + * silicon + */ + if ((Silicon_Version != SILICON_VERSION_1) && + (Silicon_Version != SILICON_VERSION_2)) { + /* + * Read Efuse Status Register + */ + EfuseStatusRegValue = Xil_In32(EFUSE_STATUS_REG); + if (EfuseStatusRegValue & EFUSE_STATUS_RSA_ENABLE_MASK) { + fsbl_printf(DEBUG_GENERAL,"RSA enabled for Chip\r\n"); +#ifdef RSA_SUPPORT + /* + * Set the Ppk + */ + SetPpk(); + + /* + * Read partition header with signature + */ + Status = GetImageHeaderAndSignature(ImageStartAddress, + (u32 *)DDR_TEMP_START_ADDR); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, + "Read Partition Header signature Failed\r\n"); + OutputStatus(GET_HEADER_INFO_FAIL); + FsblFallback(); + } + HeaderSize=TOTAL_HEADER_SIZE+RSA_SIGNATURE_SIZE; + + Status = AuthenticatePartition((u8 *)DDR_TEMP_START_ADDR, HeaderSize); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, + "Partition Header signature Failed\r\n"); + OutputStatus(GET_HEADER_INFO_FAIL); + FsblFallback(); + } +#else + /* + * In case user not enabled RSA authentication feature + */ + fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n"); + OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL); + FsblFallback(); +#endif + } + } + +#ifdef MMC_SUPPORT + /* + * In case of MMC support + * boot image preset in MMC will not have FSBL partition + */ + PartitionNum = 0; +#else + /* + * First partition header was ignored by FSBL + * As it contain FSBL partition information + */ + PartitionNum = 1; +#endif + + while (PartitionNum < PartitionCount) { + + fsbl_printf(DEBUG_INFO, "Partition Number: %lu\r\n", PartitionNum); + + HeaderPtr = &PartitionHeader[PartitionNum]; + + /* + * Print partition header information + */ + HeaderDump(HeaderPtr); + + /* + * Validate partition header + */ + Status = ValidateHeader(HeaderPtr); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "INVALID_HEADER_FAIL\r\n"); + OutputStatus(INVALID_HEADER_FAIL); + FsblFallback(); + } + + /* + * Load partition header information in to local variables + */ + PartitionDataLength = HeaderPtr->DataWordLen; + PartitionImageLength = HeaderPtr->ImageWordLen; + PartitionExecAddr = HeaderPtr->ExecAddr; + PartitionAttr = HeaderPtr->PartitionAttr; + PartitionLoadAddr = HeaderPtr->LoadAddr; + PartitionChecksumOffset = HeaderPtr->CheckSumOffset; + PartitionStartAddr = HeaderPtr->PartitionStart; + PartitionTotalSize = HeaderPtr->PartitionWordLen; + + /* + * Partition owner should be FSBL to validate the partition + */ + if ((PartitionAttr & ATTRIBUTE_PARTITION_OWNER_MASK) != + ATTRIBUTE_PARTITION_OWNER_FSBL) { + /* + * if FSBL is not the owner of partition, + * skip this partition, continue with next partition + */ + fsbl_printf(DEBUG_INFO, "Skipping partition %0lx\r\n", + PartitionNum); + /* + * Increment partition number + */ + PartitionNum++; + continue; + } + + if (PartitionAttr & ATTRIBUTE_PL_IMAGE_MASK) { + fsbl_printf(DEBUG_INFO, "Bitstream\r\n"); + PLPartitionFlag = 1; + PSPartitionFlag = 0; + BitstreamFlag = 1; + if (ApplicationFlag == 1) { +#ifdef STDOUT_BASEADDRESS + xil_printf("\r\nFSBL Warning !!!" + "Bitstream not loaded into PL\r\n"); + xil_printf("Partition order invalid\r\n"); +#endif + break; + } + } + + if (PartitionAttr & ATTRIBUTE_PS_IMAGE_MASK) { + fsbl_printf(DEBUG_INFO, "Application\r\n"); + PSPartitionFlag = 1; + PLPartitionFlag = 0; + ApplicationFlag = 1; + } + + /* + * Encrypted partition will have different value + * for Image length and data length + */ + if (PartitionDataLength != PartitionImageLength) { + fsbl_printf(DEBUG_INFO, "Encrypted\r\n"); + EncryptedPartitionFlag = 1; + } else { + EncryptedPartitionFlag = 0; + } + + /* + * Check for partition checksum check + */ + if (PartitionAttr & ATTRIBUTE_CHECKSUM_TYPE_MASK) { + PartitionChecksumFlag = 1; + } else { + PartitionChecksumFlag = 0; + } + + /* + * RSA signature check + */ + if (PartitionAttr & ATTRIBUTE_RSA_PRESENT_MASK) { + fsbl_printf(DEBUG_INFO, "RSA Signed\r\n"); + SignedPartitionFlag = 1; + } else { + SignedPartitionFlag = 0; + } + + /* + * Load address check + * Loop will break when PS load address zero and partition is + * un-signed or un-encrypted + */ + if ((PSPartitionFlag == 1) && (PartitionLoadAddr < DDR_START_ADDR)) { + if ((PartitionLoadAddr == 0) && + (!((SignedPartitionFlag == 1) || + (EncryptedPartitionFlag == 1)))) { + break; + } else { + fsbl_printf(DEBUG_GENERAL, + "INVALID_LOAD_ADDRESS_FAIL\r\n"); + OutputStatus(INVALID_LOAD_ADDRESS_FAIL); + FsblFallback(); + } + } + + if (PSPartitionFlag && (PartitionLoadAddr > DDR_END_ADDR)) { + fsbl_printf(DEBUG_GENERAL, + "INVALID_LOAD_ADDRESS_FAIL\r\n"); + OutputStatus(INVALID_LOAD_ADDRESS_FAIL); + FsblFallback(); + } + + /* + * Load execution address of first PS partition + */ + if (PSPartitionFlag && (!ExecAddrFlag)) { + ExecAddrFlag++; + ExecAddress = PartitionExecAddr; + } + + /* + * FSBL user hook call before bitstream download + */ + if (PLPartitionFlag) { + Status = FsblHookBeforeBitstreamDload(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"FSBL_BEFORE_BSTREAM_HOOK_FAIL\r\n"); + OutputStatus(FSBL_BEFORE_BSTREAM_HOOK_FAIL); + FsblFallback(); + } + } + + /* + * Move partitions from boot device + */ + Status = PartitionMove(ImageStartAddress, HeaderPtr); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"PARTITION_MOVE_FAIL\r\n"); + OutputStatus(PARTITION_MOVE_FAIL); + FsblFallback(); + } + + if ((SignedPartitionFlag) || (PartitionChecksumFlag)) { + if(PLPartitionFlag) { + /* + * PL partition loaded in to DDR temporary address + * for authentication and checksum verification + */ + PartitionStartAddr = DDR_TEMP_START_ADDR; + } else { + PartitionStartAddr = PartitionLoadAddr; + } + + if (PartitionChecksumFlag) { + /* + * Validate the partition data with checksum + */ + Status = ValidateParition(PartitionStartAddr, + (PartitionTotalSize << WORD_LENGTH_SHIFT), + ImageStartAddress + + (PartitionChecksumOffset << WORD_LENGTH_SHIFT)); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"PARTITION_CHECKSUM_FAIL\r\n"); + OutputStatus(PARTITION_CHECKSUM_FAIL); + FsblFallback(); + } + + fsbl_printf(DEBUG_INFO, "Partition Validation Done\r\n"); + } + + /* + * Authentication Partition + */ + if (SignedPartitionFlag == 1 ) { +#ifdef RSA_SUPPORT + Xil_DCacheEnable(); + Status = AuthenticatePartition((u8*)PartitionStartAddr, + (PartitionTotalSize << WORD_LENGTH_SHIFT)); + if (Status != XST_SUCCESS) { + Xil_DCacheFlush(); + Xil_DCacheDisable(); + fsbl_printf(DEBUG_GENERAL,"AUTHENTICATION_FAIL\r\n"); + OutputStatus(AUTHENTICATION_FAIL); + FsblFallback(); + } + fsbl_printf(DEBUG_INFO,"Authentication Done\r\n"); + Xil_DCacheFlush(); + Xil_DCacheDisable(); +#else + /* + * In case user not enabled RSA authentication feature + */ + fsbl_printf(DEBUG_GENERAL,"RSA_SUPPORT_NOT_ENABLED_FAIL\r\n"); + OutputStatus(RSA_SUPPORT_NOT_ENABLED_FAIL); + FsblFallback(); +#endif + } + + /* + * Decrypt PS partition + */ + if (EncryptedPartitionFlag && PSPartitionFlag) { + Status = DecryptPartition(PartitionStartAddr, + PartitionDataLength, + PartitionImageLength); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"DECRYPTION_FAIL\r\n"); + OutputStatus(DECRYPTION_FAIL); + FsblFallback(); + } + } + + /* + * Load Signed PL partition in Fabric + */ + if (PLPartitionFlag) { + Status = PcapLoadPartition((u32*)PartitionStartAddr, + (u32*)PartitionLoadAddr, + PartitionImageLength, + PartitionDataLength, + EncryptedPartitionFlag); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"BITSTREAM_DOWNLOAD_FAIL\r\n"); + OutputStatus(BITSTREAM_DOWNLOAD_FAIL); + FsblFallback(); + } + } + } + + + /* + * FSBL user hook call after bitstream download + */ + if (PLPartitionFlag) { + Status = FsblHookAfterBitstreamDload(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"FSBL_AFTER_BSTREAM_HOOK_FAIL\r\n"); + OutputStatus(FSBL_AFTER_BSTREAM_HOOK_FAIL); + FsblFallback(); + } + } + /* + * Increment partition number + */ + PartitionNum++; + } + + return ExecAddress; +} + +/*****************************************************************************/ +/** +* +* This function loads all partition header information in global array +* +* @param ImageAddress is the start address of the image +* +* @return - XST_SUCCESS if Get partition Header information successful +* - XST_FAILURE if Get Partition Header information failed +* +* @note None +* +****************************************************************************/ +u32 GetPartitionHeaderInfo(u32 ImageBaseAddress) +{ + u32 PartitionHeaderOffset; + u32 Status; + + + /* + * Get the length of the FSBL from BootHeader + */ + Status = GetFsblLength(ImageBaseAddress, &FsblLength); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n"); + return XST_FAILURE; + } + + /* + * Get the start address of the partition header table + */ + Status = GetPartitionHeaderStartAddr(ImageBaseAddress, + &PartitionHeaderOffset); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n"); + return XST_FAILURE; + } + + /* + * Header offset on flash + */ + PartitionHeaderOffset += ImageBaseAddress; + + fsbl_printf(DEBUG_INFO,"Partition Header Offset:0x%08lx\r\n", + PartitionHeaderOffset); + + /* + * Load all partitions header data in to global variable + */ + Status = LoadPartitionsHeaderInfo(PartitionHeaderOffset, + &PartitionHeader[0]); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Header Information Load Failed\r\n"); + return XST_FAILURE; + } + + /* + * Get partitions count from partitions header information + */ + PartitionCount = GetPartitionCount(&PartitionHeader[0]); + + fsbl_printf(DEBUG_INFO, "Partition Count: %lu\r\n", PartitionCount); + + /* + * Partition Count check + */ + if (PartitionCount >= MAX_PARTITION_NUMBER) { + fsbl_printf(DEBUG_GENERAL, "Invalid Partition Count\r\n"); + return XST_FAILURE; +#ifndef MMC_SUPPORT + } else if (PartitionCount <= 1) { + fsbl_printf(DEBUG_GENERAL, "There is no partition to load\r\n"); + return XST_FAILURE; +#endif + } + + return XST_SUCCESS; +} + + +/*****************************************************************************/ +/** +* +* This function goes to the partition header of the specified partition +* +* @param ImageAddress is the start address of the image +* +* @return Offset Partition header address of the image +* +* @return - XST_SUCCESS if Get Partition Header start address successful +* - XST_FAILURE if Get Partition Header start address failed +* +* @note None +* +****************************************************************************/ +u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset) +{ + u32 Status; + + Status = MoveImage(ImageAddress + IMAGE_PHDR_OFFSET, (u32)Offset, 4); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function goes to the partition header of the specified partition +* +* @param ImageAddress is the start address of the image +* +* @return Offset to Image header table address of the image +* +* @return - XST_SUCCESS if Get Partition Header start address successful +* - XST_FAILURE if Get Partition Header start address failed +* +* @note None +* +****************************************************************************/ +u32 GetImageHeaderStartAddr(u32 ImageAddress, u32 *Offset) +{ + u32 Status; + + Status = MoveImage(ImageAddress + IMAGE_HDR_OFFSET, (u32)Offset, 4); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} +/*****************************************************************************/ +/** +* +* This function gets the length of the FSBL +* +* @param ImageAddress is the start address of the image +* +* @return FsblLength is the length of the fsbl +* +* @return - XST_SUCCESS if fsbl length reading is successful +* - XST_FAILURE if fsbl length reading failed +* +* @note None +* +****************************************************************************/ +u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength) +{ + u32 Status; + + Status = MoveImage(ImageAddress + IMAGE_TOT_BYTE_LEN_OFFSET, + (u32)FsblLength, 4); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed reading FsblLength\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +#ifdef RSA_SUPPORT +/*****************************************************************************/ +/** +* +* This function goes to read the image headers and its signature. Image +* header consists of image header table, image headers, partition +* headers +* +* @param ImageBaseAddress is the start address of the image header +* +* @return Offset Partition header address of the image +* +* @return - XST_SUCCESS if Get Partition Header start address successful +* - XST_FAILURE if Get Partition Header start address failed +* +* @note None +* +****************************************************************************/ +u32 GetImageHeaderAndSignature(u32 ImageBaseAddress, u32 *Offset) +{ + u32 Status; + u32 ImageHeaderOffset; + + /* + * Get the start address of the partition header table + */ + Status = GetImageHeaderStartAddr(ImageBaseAddress, &ImageHeaderOffset); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Get Header Start Address Failed\r\n"); + return XST_FAILURE; + } + + Status = MoveImage(ImageBaseAddress+ImageHeaderOffset, (u32)Offset, + TOTAL_HEADER_SIZE + RSA_SIGNATURE_SIZE); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} +#endif +/*****************************************************************************/ +/** +* +* This function get the header information of the all the partitions and load into +* global array +* +* @param PartHeaderOffset Offset address where the header information present +* +* @param Header Partition header pointer +* +* @return - XST_SUCCESS if Load Partitions Header information successful +* - XST_FAILURE if Load Partitions Header information failed +* +* @note None +* +****************************************************************************/ +u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header) +{ + u32 Status; + + Status = MoveImage(PartHeaderOffset, (u32)Header, sizeof(PartHeader)*MAX_PARTITION_NUMBER); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"Move Image failed\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/*****************************************************************************/ +/** +* +* This function dumps the partition header. +* +* @param Header Partition header pointer +* +* @return None +* +* @note None +* +******************************************************************************/ +void HeaderDump(PartHeader *Header) +{ + fsbl_printf(DEBUG_INFO, "Header Dump\r\n"); + fsbl_printf(DEBUG_INFO, "Image Word Len: 0x%08lx\r\n", + Header->ImageWordLen); + fsbl_printf(DEBUG_INFO, "Data Word Len: 0x%08lx\r\n", + Header->DataWordLen); + fsbl_printf(DEBUG_INFO, "Partition Word Len:0x%08lx\r\n", + Header->PartitionWordLen); + fsbl_printf(DEBUG_INFO, "Load Addr: 0x%08lx\r\n", + Header->LoadAddr); + fsbl_printf(DEBUG_INFO, "Exec Addr: 0x%08lx\r\n", + Header->ExecAddr); + fsbl_printf(DEBUG_INFO, "Partition Start: 0x%08lx\r\n", + Header->PartitionStart); + fsbl_printf(DEBUG_INFO, "Partition Attr: 0x%08lx\r\n", + Header->PartitionAttr); + fsbl_printf(DEBUG_INFO, "Partition Checksum Offset: 0x%08lx\r\n", + Header->CheckSumOffset); + fsbl_printf(DEBUG_INFO, "Section Count: 0x%08lx\r\n", + Header->SectionCount); + fsbl_printf(DEBUG_INFO, "Checksum: 0x%08lx\r\n", + Header->CheckSum); +} + + +/******************************************************************************/ +/** +* +* This function calculates the partitions count from header information +* +* @param Header Partition header pointer +* +* @return Count Partition count +* +* @note None +* +*******************************************************************************/ +u32 GetPartitionCount(PartHeader *Header) +{ + u32 Count=0; + struct HeaderArray *Hap; + + for(Count = 0; Count < MAX_PARTITION_NUMBER; Count++) { + Hap = (struct HeaderArray *)&Header[Count]; + if(IsLastPartition(Hap)!=XST_FAILURE) + break; + } + + return Count; +} + +/******************************************************************************/ +/** +* This function check whether the current partition is the end of partitions +* +* The partition is the end of the partitions if it looks like this: +* 0x00000000 +* 0x00000000 +* .... +* 0x00000000 +* 0x00000000 +* 0xFFFFFFFF +* +* @param H is a pointer to struct HeaderArray +* +* @return +* - XST_SUCCESS if it is the last partition +* - XST_FAILURE if it is not last partition +* +****************************************************************************/ +u32 IsLastPartition(struct HeaderArray *H) +{ + int Index; + + if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != 0xFFFFFFFF) { + return XST_FAILURE; + } + + for (Index = 0; Index < PARTITION_HDR_WORD_COUNT - 1; Index++) { + + if (H->Fields[Index] != 0x0) { + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function validates the partition header. +* +* @param Header Partition header pointer +* +* @return +* - XST_FAILURE if bad header. +* - XST_SUCCESS if successful. +* +* @note None +* +*******************************************************************************/ +u32 ValidateHeader(PartHeader *Header) +{ + struct HeaderArray *Hap; + + Hap = (struct HeaderArray *)Header; + + /* + * If there are no partitions to load, fail + */ + if (IsEmptyHeader(Hap) == XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "IMAGE_HAS_NO_PARTITIONS\r\n"); + return XST_FAILURE; + } + + /* + * Validate partition header checksum + */ + if (ValidatePartitionHeaderChecksum(Hap) != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "PARTITION_HEADER_CORRUPTION\r\n"); + return XST_FAILURE; + } + + /* + * Validate partition data size + */ + if (Header->ImageWordLen > MAXIMUM_IMAGE_WORD_LEN) { + fsbl_printf(DEBUG_GENERAL, "INVALID_PARTITION_LENGTH\r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* This function check whether the current partition header is empty. +* A partition header is considered empty if image word length is 0 and the +* last word is 0. +* +* @param H is a pointer to struct HeaderArray +* +* @return +* - XST_SUCCESS , If the partition header is empty +* - XST_FAILURE , If the partition header is NOT empty +* +* @note Caller is responsible to make sure the address is valid. +* +* +****************************************************************************/ +u32 IsEmptyHeader(struct HeaderArray *H) +{ + int Index; + + for (Index = 0; Index < PARTITION_HDR_WORD_COUNT; Index++) { + if (H->Fields[Index] != 0x0) { + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function checks the header checksum If the header checksum is not valid +* XST_FAILURE is returned. +* +* @param H is a pointer to struct HeaderArray +* +* @return +* - XST_SUCCESS is header checksum is ok +* - XST_FAILURE if the header checksum is not correct +* +* @note None. +* +****************************************************************************/ +u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H) +{ + u32 Checksum; + u32 Count; + + Checksum = 0; + + for (Count = 0; Count < PARTITION_HDR_CHECKSUM_WORD_COUNT; Count++) { + /* + * Read the word from the header + */ + Checksum += H->Fields[Count]; + } + + /* + * Invert checksum, last bit of error checking + */ + Checksum ^= 0xFFFFFFFF; + + /* + * Validate the checksum + */ + if (H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT] != Checksum) { + fsbl_printf(DEBUG_GENERAL, "Error: Checksum 0x%8.8lx != 0x%8.8lx\r\n", + Checksum, H->Fields[PARTITION_HDR_CHECKSUM_WORD_COUNT]); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function load the partition from boot device +* +* @param ImageBaseAddress Base address on flash +* @param Header Partition header pointer +* +* @return +* - XST_SUCCESS if partition move successful +* - XST_FAILURE if check failed move failed +* +* @note None +* +*******************************************************************************/ +u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header) +{ + u32 SourceAddr; + u32 Status; + u8 SecureTransferFlag = 0; + u32 LoadAddr; + u32 ImageWordLen; + u32 DataWordLen; + + SourceAddr = ImageBaseAddress; + SourceAddr += Header->PartitionStart<LoadAddr; + ImageWordLen = Header->ImageWordLen; + DataWordLen = Header->DataWordLen; + + /* + * Add flash base address for linear boot devices + */ + if (LinearBootDeviceFlag) { + SourceAddr += FlashReadBaseAddress; + } + + /* + * Partition encrypted + */ + if(EncryptedPartitionFlag) { + SecureTransferFlag = 1; + } + + /* + * For Signed or checksum enabled partition, + * Total partition image need to copied to DDR + */ + if (SignedPartitionFlag || PartitionChecksumFlag) { + ImageWordLen = Header->PartitionWordLen; + DataWordLen = Header->PartitionWordLen; + } + + /* + * Encrypted and Signed PS partition need to be loaded on to DDR + * without decryption + */ + if (PSPartitionFlag && + (SignedPartitionFlag || PartitionChecksumFlag) && + EncryptedPartitionFlag) { + SecureTransferFlag = 0; + } + + /* + * CPU is used for data transfer in case of non-linear + * boot device + */ + if (!LinearBootDeviceFlag) { + /* + * PL partition copied to DDR temporary location + */ + if (PLPartitionFlag) { + LoadAddr = DDR_TEMP_START_ADDR; + } + + Status = MoveImage(SourceAddr, + LoadAddr, + (ImageWordLen << WORD_LENGTH_SHIFT)); + if(Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "Move Image Failed\r\n"); + return XST_FAILURE; + } + + /* + * As image present at load address + */ + SourceAddr = LoadAddr; + } + + if ((LinearBootDeviceFlag && PLPartitionFlag && + (SignedPartitionFlag || PartitionChecksumFlag)) || + (LinearBootDeviceFlag && PSPartitionFlag) || + ((!LinearBootDeviceFlag) && PSPartitionFlag && SecureTransferFlag)) { + /* + * PL signed partition copied to DDR temporary location + * using non-secure PCAP for linear boot device + */ + if(PLPartitionFlag){ + SecureTransferFlag = 0; + LoadAddr = DDR_TEMP_START_ADDR; + } + + /* + * Data transfer using PCAP + */ + Status = PcapDataTransfer((u32*)SourceAddr, + (u32*)LoadAddr, + ImageWordLen, + DataWordLen, + SecureTransferFlag); + if(Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "PCAP Data Transfer Failed\r\n"); + return XST_FAILURE; + } + + /* + * As image present at load address + */ + SourceAddr = LoadAddr; + } + + /* + * Load Bitstream partition in to fabric only + * if checksum and authentication bits are not set + */ + if (PLPartitionFlag && (!(SignedPartitionFlag || PartitionChecksumFlag))) { + Status = PcapLoadPartition((u32*)SourceAddr, + (u32*)Header->LoadAddr, + Header->ImageWordLen, + Header->DataWordLen, + EncryptedPartitionFlag); + if(Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL, "PCAP Bitstream Download Failed\r\n"); + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function load the decrypts partition +* +* @param StartAddr Source start address +* @param DataLength Data length in words +* @param ImageLength Image length in words +* +* @return +* - XST_SUCCESS if decryption successful +* - XST_FAILURE if decryption failed +* +* @note None +* +*******************************************************************************/ +u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength) +{ + u32 Status; + u8 SecureTransferFlag =1; + + /* + * Data transfer using PCAP + */ + Status = PcapDataTransfer((u32*)StartAddr, + (u32*)StartAddr, + ImageLength, + DataLength, + SecureTransferFlag); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"PCAP Data Transfer failed \r\n"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** +* +* This function Validate Partition Data by using checksum preset in image +* +* @param Partition header pointer +* @param Partition check sum offset +* @return +* - XST_SUCCESS if partition data is ok +* - XST_FAILURE if partition data is corrupted +* +* @note None +* +*******************************************************************************/ +u32 ValidateParition(u32 StartAddr, u32 Length, u32 ChecksumOffset) +{ + u8 Checksum[MD5_CHECKSUM_SIZE]; + u8 CalcChecksum[MD5_CHECKSUM_SIZE]; + u32 Status; + u32 Index; + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Prevent WDT reset + */ + XWdtPs_RestartWdt(&Watchdog); +#endif + + /* + * Get checksum from flash + */ + Status = GetPartitionChecksum(ChecksumOffset, &Checksum[0]); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO, "Actual checksum\r\n"); + + for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) { + fsbl_printf(DEBUG_INFO, "0x%0x ",Checksum[Index]); + } + + fsbl_printf(DEBUG_INFO, "\r\n"); + + /* + * Calculate checksum for the partition + */ + Status = CalcPartitionChecksum(StartAddr, Length, &CalcChecksum[0]); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO, "Calculated checksum\r\n"); + + for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) { + fsbl_printf(DEBUG_INFO, "0x%0x ",CalcChecksum[Index]); + } + + fsbl_printf(DEBUG_INFO, "\r\n"); + + /* + * Compare actual checksum with the calculated checksum + */ + for (Index = 0; Index < MD5_CHECKSUM_SIZE; Index++) { + if(Checksum[Index] != CalcChecksum[Index]) { + fsbl_printf(DEBUG_GENERAL, "Error: " + "Partition DataChecksum 0x%0x!= 0x%0x\r\n", + Checksum[Index], CalcChecksum[Index]); + return XST_FAILURE; + } + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function gets partition checksum from flash +* +* @param Check sum offset +* @param Checksum pointer +* @return +* - XST_SUCCESS if checksum read success +* - XST_FAILURE if unable get checksum +* +* @note None +* +*******************************************************************************/ +u32 GetPartitionChecksum(u32 ChecksumOffset, u8 *Checksum) +{ + u32 Status; + + Status = MoveImage(ChecksumOffset, (u32)Checksum, MD5_CHECKSUM_SIZE); + if(Status != XST_SUCCESS) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function calculates the checksum preset in image +* +* @param Start address +* @param Length of the data +* @param Checksum pointer +* +* @return +* - XST_SUCCESS if Checksum calculate successful +* - XST_FAILURE if Checksum calculate failed +* +* @note None +* +*******************************************************************************/ +u32 CalcPartitionChecksum(u32 SourceAddr, u32 DataLength, u8 *Checksum) +{ + /* + * Calculate checksum using MD5 algorithm + */ + md5((u8*)SourceAddr, DataLength, Checksum, 0 ); + + return XST_SUCCESS; +} + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/image_mover.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/image_mover.h new file mode 100644 index 0000000..dad66f1 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/image_mover.h @@ -0,0 +1,161 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file image_mover.h +* +* This file contains the interface for moving the image from FLASH to OCM + +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz	03/04/11	Initial release
+* 2.00a jz	06/04/11	partition header expands to 12 words
+* 5.00a kc	07/30/13	Added defines for image header information
+* 8.00a kc	01/16/13	Added defines for partition owner attribute
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___IMAGE_MOVER_H___ +#define ___IMAGE_MOVER_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "fsbl.h" + +/************************** Constant Definitions *****************************/ +#define PARTITION_NUMBER_SHIFT 24 +#define MAX_PARTITION_NUMBER (0xE) + +/* Boot Image Header defines */ +#define IMAGE_HDR_OFFSET 0x098 /* Start of image header table */ +#define IMAGE_PHDR_OFFSET 0x09C /* Start of partition headers */ +#define IMAGE_HEADER_SIZE (64) +#define IMAGE_HEADER_TABLE_SIZE (64) +#define TOTAL_PARTITION_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE) +#define TOTAL_IMAGE_HEADER_SIZE (MAX_PARTITION_NUMBER * IMAGE_HEADER_SIZE) +#define TOTAL_HEADER_SIZE (IMAGE_HEADER_TABLE_SIZE + \ + TOTAL_IMAGE_HEADER_SIZE + \ + TOTAL_PARTITION_HEADER_SIZE + 64) + +/* Partition Header defines */ +#define PARTITION_IMAGE_WORD_LEN_OFFSET 0x00 /* Word length of image */ +#define PARTITION_DATA_WORD_LEN_OFFSET 0x04 /* Word length of data */ +#define PARTITION_WORD_LEN_OFFSET 0x08 /* Word length of partition */ +#define PARTITION_LOAD_ADDRESS_OFFSET 0x0C /* Load addr in DDR */ +#define PARTITION_EXEC_ADDRESS_OFFSET 0x10 /* Addr to start executing */ +#define PARTITION_ADDR_OFFSET 0x14 /* Partition word offset */ +#define PARTITION_ATTRIBUTE_OFFSET 0x18 /* Partition type */ +#define PARTITION_HDR_CHECKSUM_OFFSET 0x3C /* Header Checksum offset */ +#define PARTITION_HDR_CHECKSUM_WORD_COUNT 0xF /* Checksum word count */ +#define PARTITION_HDR_WORD_COUNT 0x10 /* Header word len */ +#define PARTITION_HDR_TOTAL_LEN 0x40 /* One partition hdr length*/ + +/* Attribute word defines */ +#define ATTRIBUTE_IMAGE_TYPE_MASK 0xF0 /* Destination Device type */ +#define ATTRIBUTE_PS_IMAGE_MASK 0x10 /* Code partition */ +#define ATTRIBUTE_PL_IMAGE_MASK 0x20 /* Bit stream partition */ +#define ATTRIBUTE_CHECKSUM_TYPE_MASK 0x7000 /* Checksum Type */ +#define ATTRIBUTE_RSA_PRESENT_MASK 0x8000 /* RSA Signature Present */ +#define ATTRIBUTE_PARTITION_OWNER_MASK 0x30000 /* Partition Owner */ + +#define ATTRIBUTE_PARTITION_OWNER_FSBL 0x00000 /* FSBL Partition Owner */ + + +/**************************** Type Definitions *******************************/ +typedef u32 (*ImageMoverType)( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthBytes); + +typedef struct StructPartHeader { + u32 ImageWordLen; /* 0x0 */ + u32 DataWordLen; /* 0x4 */ + u32 PartitionWordLen; /* 0x8 */ + u32 LoadAddr; /* 0xC */ + u32 ExecAddr; /* 0x10 */ + u32 PartitionStart; /* 0x14 */ + u32 PartitionAttr; /* 0x18 */ + u32 SectionCount; /* 0x1C */ + u32 CheckSumOffset; /* 0x20 */ + u32 Pads1[1]; + u32 ACOffset; /* 0x28 */ + u32 Pads2[4]; + u32 CheckSum; /* 0x3C */ +}PartHeader; + +struct HeaderArray { + u32 Fields[16]; +}; + + +/***************** Macros (Inline Functions) Definitions *********************/ +#define MoverIn32 Xil_In32 +#define MoverOut32 Xil_Out32 + +/************************** Function Prototypes ******************************/ +u32 LoadBootImage(void); +u32 GetPartitionHeaderInfo(u32 ImageBaseAddress); +u32 PartitionMove(u32 ImageBaseAddress, PartHeader *Header); +u32 ValidatePartitionHeaderChecksum(struct HeaderArray *H); +u32 GetPartitionHeaderStartAddr(u32 ImageAddress, u32 *Offset); +u32 GetImageHeaderAndSignature(u32 ImageAddress, u32 *Offset); +u32 GetFsblLength(u32 ImageAddress, u32 *FsblLength); +u32 LoadPartitionsHeaderInfo(u32 PartHeaderOffset, PartHeader *Header); +u32 IsEmptyHeader(struct HeaderArray *H); +u32 IsLastPartition(struct HeaderArray *H); +void HeaderDump(PartHeader *Header); +u32 GetPartitionCount(PartHeader *Header); +u32 ValidateHeader(PartHeader *Header); +u32 DecryptPartition(u32 StartAddr, u32 DataLength, u32 ImageLength); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + + +#endif /* ___IMAGE_MOVER_H___ */ + + + + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/main.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/main.c new file mode 100644 index 0000000..958e3c0 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/main.c @@ -0,0 +1,1532 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file main.c +* +* The main file for the First Stage Boot Loader (FSBL). +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz	06/04/11	Initial release
+* 2.00a mb	25/05/12	standalone based FSBL
+* 3.00a np/mb	08/03/12	Added call to FSBL user hook - before handoff.
+*				DDR ECC initialization added
+* 				fsbl print with verbose added
+* 				Performance measurement added
+* 				Flushed the UART Tx buffer
+* 				Added the performance time for ECC DDR init
+* 				Added clearing of ECC Error Code
+* 				Added the watchdog timer value
+* 4.00a sgd 02/28/13	Code Cleanup
+* 						Fix for CR#681014 - ECC init in FSBL should not
+* 						                    call fabric_init()
+* 						Fix for CR#689077 - FSBL hangs at Handoff clearing the
+* 						                    TX UART buffer when using UART0
+* 						                    instead of UART1
+*						Fix for CR#694038 - FSBL debug logs always prints 14.3
+*											as the Revision number - this is
+*										    incorrect
+*						Fix for CR#694039 - FSBL prints "unsupported silicon
+*											version for v3.0" 3.0 Silicon
+*                       Fix for CR#699475 - FSBL functionality is broken and
+*                                           its not able to boot in QSPI/NAND
+*                                           bootmode
+*                       Removed DDR initialization check
+*                       Removed DDR ECC initialization code
+*						Modified hand off address check to 1MB
+*						Added RSA authentication support
+*						Watchdog disabled for AES E-Fuse encryption
+* 5.00a sgd 05/17/13	Fallback support for E-Fuse encryption
+*                       Fix for CR#708728 - Issues seen while making HP
+*                                           interconnect 32 bit wide
+* 6.00a kc  07/30/13    Fix for CR#708316 - PS7_init.tcl file should have
+*                                           Error mechanism for all mask_poll
+*                       Fix for CR#691150 - ps7_init does not check for
+*                                           peripheral initialization failures
+*                                           or timeout on polls
+*                       Fix for CR#724165 - Partition Header used by FSBL is
+*                                           not authenticated
+*                       Fix for CR#724166 - FSBL doesn’t use PPK authenticated
+*                                           by Boot ROM for authenticating
+*                                           the Partition images
+*                       Fix for CR#722979 - Provide customer-friendly
+*                                           changelogs in FSBL
+*                       Fix for CR#732865 - Backward compatibility for ps7_init
+*                       					function
+* 7.00a kc  10/18/13    Integrated SD/MMC driver
+* 8.00a kc  02/20/14	Fix for CR#775631 - FSBL: FsblGetGlobalTimer() 
+*											is not proper
+* 9.00a kc  04/16/14	Fix for CR#724166 - SetPpk() will fail on secure
+*		 									fallback unless FSBL* and FSBL
+*		 									are identical in length
+* 10.00a kc 07/24/14	Fix for CR#809336 - Minor code cleanup
+*        kc 08/27/14	Fix for CR#820356 - FSBL compilation fails with
+* 											IAR compiler
+* 11.00a kv 10/08/14	Fix for CR#826030 - LinearBootDeviceFlag should
+*											be initialized to 0 in IO mode
+*											case
+* 15.00a gan 07/21/16   Fix for CR# 953654 -(2016.3)FSBL -
+* 											In pcap.c/pcap.h/main.c,
+* 											Fabric Initialization sequence
+* 											is modified to check the PL power
+* 											before sequence starts and checking
+* 											INIT_B reset status twice in case
+* 											of failure.
+*
    +* +* @note +* FSBL runs from OCM, Based on the boot mode selected, FSBL will copy +* the partitions from the flash device. If the partition is bitstream then +* the bitstream is programmed in the Fabric and for an partition that is +* an application , FSBL will copy the application into DDR and does a +* handoff.The application should not be starting at the OCM address, +* FSBL does not remap the DDR. Application should use DDR starting from 1MB +* +* FSBL can be stitched along with bitstream and application using bootgen +* +* Refer to fsbl.h file for details on the compilation flags supported in FSBL +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "fsbl.h" +#include "qspi.h" +#include "nand.h" +#include "nor.h" +#include "sd.h" +#include "pcap.h" +#include "image_mover.h" +#include "xparameters.h" +#include "xil_cache.h" +#include "xil_exception.h" +#include "xstatus.h" +#include "fsbl_hooks.h" +#include "xtime_l.h" + +#ifdef XPAR_XWDTPS_0_BASEADDR +#include "xwdtps.h" +#endif + +#ifdef STDOUT_BASEADDRESS +#ifdef XPAR_XUARTPS_0_BASEADDR +#include "xuartps_hw.h" +#endif +#endif + +#ifdef RSA_SUPPORT +#include "rsa.h" +#endif + +/************************** Constant Definitions *****************************/ + +#ifdef XPAR_XWDTPS_0_BASEADDR +#define WDT_DEVICE_ID XPAR_XWDTPS_0_DEVICE_ID +#define WDT_EXPIRE_TIME 100 +#define WDT_CRV_SHIFT 12 +#endif + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#ifdef XPAR_XWDTPS_0_BASEADDR +XWdtPs Watchdog; /* Instance of WatchDog Timer */ +#endif +/************************** Function Prototypes ******************************/ +extern int ps7_init(); +extern char* getPS7MessageInfo(unsigned key); +#ifdef PS7_POST_CONFIG +extern int ps7_post_config(); +#endif + +static void Update_MultiBootRegister(void); +/* Exception handlers */ +static void RegisterHandlers(void); +static void Undef_Handler (void); +static void SVC_Handler (void); +static void PreFetch_Abort_Handler (void); +static void Data_Abort_Handler (void); +static void IRQ_Handler (void); +static void FIQ_Handler (void); + + +#ifdef XPAR_XWDTPS_0_BASEADDR +int InitWatchDog(void); +u32 ConvertTime_WdtCounter(u32 seconds); +void CheckWDTReset(void); +#endif + +u32 NextValidImageCheck(void); + +u32 DDRInitCheck(void); + +/************************** Variable Definitions *****************************/ +/* + * Base Address for the Read Functionality for Image Processing + */ +u32 FlashReadBaseAddress = 0; +/* + * Silicon Version + */ +u32 Silicon_Version; + +/* + * Boot Device flag + */ +u8 LinearBootDeviceFlag=0; + +u32 PcapCtrlRegVal; + +u8 SystemInitFlag; + +extern ImageMoverType MoveImage; +extern XDcfg *DcfgInstPtr; +extern u8 BitstreamFlag; +#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +extern u32 QspiFlashSize; +#endif +/*****************************************************************************/ +/** +* +* This is the main function for the FSBL ROM code. +* +* +* @param None. +* +* @return +* - XST_SUCCESS to indicate success +* - XST_FAILURE.to indicate failure +* +* @note +* +****************************************************************************/ +int main(void) +{ + u32 BootModeRegister = 0; + u32 HandoffAddress = 0; + u32 Status = XST_SUCCESS; + + /* + * PCW initialization for MIO,PLL,CLK and DDR + */ + Status = ps7_init(); + if (Status != FSBL_PS7_INIT_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"PS7_INIT_FAIL : %s\r\n", + getPS7MessageInfo(Status)); + OutputStatus(PS7_INIT_FAIL); + /* + * Calling FsblHookFallback instead of Fallback + * since, devcfg driver is not yet initialized + */ + FsblHookFallback(); + } + + /* + * Unlock SLCR for SLCR register write + */ + SlcrUnlock(); + + /* If Performance measurement is required + * then read the Global Timer value , Please note that the + * time taken for mio, clock and ddr initialisation + * done in the ps7_init function is not accounted in the FSBL + * + */ +#ifdef FSBL_PERF + XTime tCur = 0; + FsblGetGlobalTime(&tCur); +#endif + + /* + * Flush the Caches + */ + Xil_DCacheFlush(); + + /* + * Disable Data Cache + */ + Xil_DCacheDisable(); + + /* + * Register the Exception handlers + */ + RegisterHandlers(); + + /* + * Print the FSBL Banner + */ + fsbl_printf(DEBUG_GENERAL,"\n\rXilinx First Stage Boot Loader \n\r"); + fsbl_printf(DEBUG_GENERAL,"Release %d.%d %s-%s\r\n", + SDK_RELEASE_YEAR, SDK_RELEASE_QUARTER, + __DATE__,__TIME__); + +#ifdef XPAR_PS7_DDR_0_S_AXI_BASEADDR + + /* + * DDR Read/write test + */ + Status = DDRInitCheck(); + if (Status == XST_FAILURE) { + fsbl_printf(DEBUG_GENERAL,"DDR_INIT_FAIL \r\n"); + /* Error Handling here */ + OutputStatus(DDR_INIT_FAIL); + /* + * Calling FsblHookFallback instead of Fallback + * since, devcfg driver is not yet initialized + */ + FsblHookFallback(); + } + + + /* + * PCAP initialization + */ + Status = InitPcap(); + if (Status == XST_FAILURE) { + fsbl_printf(DEBUG_GENERAL,"PCAP_INIT_FAIL \n\r"); + OutputStatus(PCAP_INIT_FAIL); + /* + * Calling FsblHookFallback instead of Fallback + * since, devcfg driver is not yet initialized + */ + FsblHookFallback(); + } + + fsbl_printf(DEBUG_INFO,"Devcfg driver initialized \r\n"); + + /* + * Get the Silicon Version + */ + GetSiliconVersion(); + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Check if WDT Reset has occurred or not + */ + CheckWDTReset(); + + /* + * Initialize the Watchdog Timer so that it is ready to use + */ + Status = InitWatchDog(); + if (Status == XST_FAILURE) { + fsbl_printf(DEBUG_GENERAL,"WATCHDOG_INIT_FAIL \n\r"); + OutputStatus(WDT_INIT_FAIL); + FsblFallback(); + } + fsbl_printf(DEBUG_INFO,"Watchdog driver initialized \r\n"); +#endif + + /* + * Get PCAP controller settings + */ + PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr); + + /* + * Check for AES source key + */ + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * For E-Fuse AES encryption Watch dog Timer disabled and + * User not allowed to do system reset + */ +#ifdef XPAR_XWDTPS_0_BASEADDR + fsbl_printf(DEBUG_INFO,"Watchdog Timer Disabled\r\n"); + XWdtPs_Stop(&Watchdog); +#endif + fsbl_printf(DEBUG_INFO,"User not allowed to do " + "any system resets\r\n"); + } + + /* + * Store FSBL run state in Reboot Status Register + */ + MarkFSBLIn(); + + /* + * Read bootmode register + */ + BootModeRegister = Xil_In32(BOOT_MODE_REG); + BootModeRegister &= BOOT_MODES_MASK; + + /* + * QSPI BOOT MODE + */ +#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR + +#ifdef MMC_SUPPORT + /* + * To support MMC boot + * QSPI boot mode detection ignored + */ + if (BootModeRegister == QSPI_MODE) { + BootModeRegister = MMC_MODE; + } +#endif + + if (BootModeRegister == QSPI_MODE) { + fsbl_printf(DEBUG_GENERAL,"Boot mode is QSPI\n\r"); + InitQspi(); + MoveImage = QspiAccess; + fsbl_printf(DEBUG_INFO,"QSPI Init Done \r\n"); + } else +#endif + + /* + * NAND BOOT MODE + */ +#ifdef XPAR_PS7_NAND_0_BASEADDR + if (BootModeRegister == NAND_FLASH_MODE) { + /* + * Boot ROM always initialize the nand at lower speed + * This is the chance to put it to an optimum speed for your nand + * device + */ + fsbl_printf(DEBUG_GENERAL,"Boot mode is NAND\n"); + + Status = InitNand(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"NAND_INIT_FAIL \r\n"); + /* + * Error Handling here + */ + OutputStatus(NAND_INIT_FAIL); + FsblFallback(); + } + MoveImage = NandAccess; + fsbl_printf(DEBUG_INFO,"NAND Init Done \r\n"); + } else +#endif + + /* + * NOR BOOT MODE + */ + if (BootModeRegister == NOR_FLASH_MODE) { + fsbl_printf(DEBUG_GENERAL,"Boot mode is NOR\n\r"); + /* + * Boot ROM always initialize the nor at lower speed + * This is the chance to put it to an optimum speed for your nor + * device + */ + InitNor(); + fsbl_printf(DEBUG_INFO,"NOR Init Done \r\n"); + MoveImage = NorAccess; + } else + + /* + * SD BOOT MODE + */ +#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR) + + if (BootModeRegister == SD_MODE) { + fsbl_printf(DEBUG_GENERAL,"Boot mode is SD\r\n"); + + /* + * SD initialization returns file open error or success + */ + Status = InitSD("BOOT.BIN"); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"SD_INIT_FAIL\r\n"); + OutputStatus(SD_INIT_FAIL); + FsblFallback(); + } + MoveImage = SDAccess; + fsbl_printf(DEBUG_INFO,"SD Init Done \r\n"); + } else + + if (BootModeRegister == MMC_MODE) { + fsbl_printf(DEBUG_GENERAL,"Booting Device is MMC\r\n"); + + /* + * MMC initialization returns file open error or success + */ + Status = InitSD("BOOT.BIN"); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"MMC_INIT_FAIL\r\n"); + OutputStatus(SD_INIT_FAIL); + FsblFallback(); + } + MoveImage = SDAccess; + fsbl_printf(DEBUG_INFO,"MMC Init Done \r\n"); + } else + +#endif + + /* + * JTAG BOOT MODE + */ + if (BootModeRegister == JTAG_MODE) { + fsbl_printf(DEBUG_GENERAL,"Boot mode is JTAG\r\n"); + /* + * Stop the Watchdog before JTAG handoff + */ +#ifdef XPAR_XWDTPS_0_BASEADDR + XWdtPs_Stop(&Watchdog); +#endif + /* + * Clear our mark in reboot status register + */ + ClearFSBLIn(); + + /* + * SLCR lock + */ + SlcrLock(); + + FsblHandoffJtagExit(); + } else { + fsbl_printf(DEBUG_GENERAL,"ILLEGAL_BOOT_MODE \r\n"); + OutputStatus(ILLEGAL_BOOT_MODE); + /* + * fallback starts, no return + */ + FsblFallback(); + } + + fsbl_printf(DEBUG_INFO,"Flash Base Address: 0x%08lx\r\n", FlashReadBaseAddress); + + /* + * Check for valid flash address + */ + if ((FlashReadBaseAddress != XPS_QSPI_LINEAR_BASEADDR) && + (FlashReadBaseAddress != XPS_NAND_BASEADDR) && + (FlashReadBaseAddress != XPS_NOR_BASEADDR) && + (FlashReadBaseAddress != XPS_SDIO0_BASEADDR)) { + fsbl_printf(DEBUG_GENERAL,"INVALID_FLASH_ADDRESS \r\n"); + OutputStatus(INVALID_FLASH_ADDRESS); + FsblFallback(); + } + + /* + * NOR and QSPI (parallel) are linear boot devices + */ + if ((FlashReadBaseAddress == XPS_NOR_BASEADDR)) { + fsbl_printf(DEBUG_INFO, "Linear Boot Device\r\n"); + LinearBootDeviceFlag = 1; + } + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Prevent WDT reset + */ + XWdtPs_RestartWdt(&Watchdog); +#endif + + /* + * This used only in case of E-Fuse encryption + * For image search + */ + SystemInitFlag = 1; + + /* + * Load boot image + */ + HandoffAddress = LoadBootImage(); + + fsbl_printf(DEBUG_INFO,"Handoff Address: 0x%08lx\r\n",HandoffAddress); + + /* + * For Performance measurement + */ +#ifdef FSBL_PERF + XTime tEnd = 0; + fsbl_printf(DEBUG_GENERAL,"Total Execution time is "); + FsblMeasurePerfTime(tCur,tEnd); +#endif + + /* + * FSBL handoff to valid handoff address or + * exit in JTAG + */ + FsblHandoff(HandoffAddress); + +#else + OutputStatus(NO_DDR); + FsblFallback(); +#endif + + return Status; +} + +/******************************************************************************/ +/** +* +* This function reset the CPU and goes for Boot ROM fallback handling +* +* @param None +* +* @return None +* +* @note None +* +****************************************************************************/ +void FsblFallback(void) +{ + u32 RebootStatusReg; + u32 Status; + u32 HandoffAddr; + u32 BootModeRegister; + + /* + * Read bootmode register + */ + BootModeRegister = Xil_In32(BOOT_MODE_REG); + BootModeRegister &= BOOT_MODES_MASK; + + /* + * Fallback support check + */ + if (!((BootModeRegister == QSPI_MODE) || + (BootModeRegister == NAND_FLASH_MODE) || + (BootModeRegister == NOR_FLASH_MODE))) { + fsbl_printf(DEBUG_INFO,"\r\n" + "This Boot Mode Doesn't Support Fallback\r\n"); + ClearFSBLIn(); + FsblHookFallback(); + } + + /* + * update the Multiboot Register for Golden search hunt + */ + Update_MultiBootRegister(); + + /* + * Notify Boot ROM something is wrong + */ + RebootStatusReg = Xil_In32(REBOOT_STATUS_REG); + + /* + * Set the FSBL Fail mask + */ + Xil_Out32(REBOOT_STATUS_REG, RebootStatusReg | FSBL_FAIL_MASK); + + /* + * Barrier for synchronization + */ + __asm( + "dsb\n\t" + "isb" + ); + + /* + * Check for AES source key + */ + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * Next valid image search can happen only + * when system initialization done + */ + if (SystemInitFlag == 1) { + /* + * Clean the Fabric + */ + Status = FabricInit(); + if(Status != XST_SUCCESS){ + ClearFSBLIn(); + FsblHookFallback(); + } + +#ifdef RSA_SUPPORT + + /* + * Making sure PPK is set for efuse error cases + */ + SetPpk(); +#endif + + /* + * Search for next valid image + */ + Status = NextValidImageCheck(); + if(Status != XST_SUCCESS){ + fsbl_printf(DEBUG_INFO,"\r\nNo Image Found\r\n"); + ClearFSBLIn(); + FsblHookFallback(); + } + + /* + * Load next valid image + */ + HandoffAddr = LoadBootImage(); + + /* + * Handoff to next image + */ + FsblHandoff(HandoffAddr); + } else { + fsbl_printf(DEBUG_INFO,"System Initialization Failed\r\n"); + fsbl_printf(DEBUG_INFO,"\r\nNo Image Search\r\n"); + ClearFSBLIn(); + FsblHookFallback(); + } + } + + /* + * Reset PS, so Boot ROM will restart + */ + Xil_Out32(PS_RST_CTRL_REG, PS_RST_MASK); +} + + +/******************************************************************************/ +/** +* +* This function hands the A9/PS to the loaded user code. +* +* @param none +* +* @return none +* +* @note This function does not return. +* +****************************************************************************/ +void FsblHandoff(u32 FsblStartAddr) +{ + u32 Status; + + /* + * Enable level shifter + */ + if(BitstreamFlag) { + /* + * FSBL will not enable the level shifters for a NON PS instantiated + * Bitstream + * CR# 671028 + * This flag can be set during compilation for a NON PS instantiated + * bitstream + */ +#ifndef NON_PS_INSTANTIATED_BITSTREAM +#ifdef PS7_POST_CONFIG + ps7_post_config(); + /* + * Unlock SLCR for SLCR register write + */ + SlcrUnlock(); +#else + /* + * Set Level Shifters DT618760 + */ + Xil_Out32(PS_LVL_SHFTR_EN, LVL_PL_PS); + fsbl_printf(DEBUG_INFO,"Enabling Level Shifters PL to PS " + "Address = 0x%x Value = 0x%x \n\r", + PS_LVL_SHFTR_EN, Xil_In32(PS_LVL_SHFTR_EN)); + + /* + * Enable AXI interface + */ + Xil_Out32(FPGA_RESET_REG, 0); + fsbl_printf(DEBUG_INFO,"AXI Interface enabled \n\r"); + fsbl_printf(DEBUG_INFO, "FPGA Reset Register " + "Address = 0x%x , Value = 0x%x \r\n", + FPGA_RESET_REG ,Xil_In32(FPGA_RESET_REG)); +#endif +#endif + } + + /* + * FSBL user hook call before handoff to the application + */ + Status = FsblHookBeforeHandoff(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"FSBL_HANDOFF_HOOK_FAIL\r\n"); + OutputStatus(FSBL_HANDOFF_HOOK_FAIL); + FsblFallback(); + } + +#ifdef XPAR_XWDTPS_0_BASEADDR + XWdtPs_Stop(&Watchdog); +#endif + + /* + * Clear our mark in reboot status register + */ + ClearFSBLIn(); + + if(FsblStartAddr == 0) { + /* + * SLCR lock + */ + SlcrLock(); + + fsbl_printf(DEBUG_INFO,"No Execution Address JTAG handoff \r\n"); + FsblHandoffJtagExit(); + } else { + fsbl_printf(DEBUG_GENERAL,"SUCCESSFUL_HANDOFF\r\n"); + OutputStatus(SUCCESSFUL_HANDOFF); + FsblHandoffExit(FsblStartAddr); + } + + OutputStatus(ILLEGAL_RETURN); + + FsblFallback(); +} + +/******************************************************************************/ +/** +* +* This function outputs the status for the provided State in the boot process. +* +* @param State is where in the boot process the output is desired. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void OutputStatus(u32 State) +{ +#ifdef STDOUT_BASEADDRESS +#ifdef XPAR_XUARTPS_0_BASEADDR + u32 UartReg = 0; +#endif + + fsbl_printf(DEBUG_GENERAL,"FSBL Status = 0x%.4lx\r\n", State); + /* + * The TX buffer needs to be flushed out + * If this is not done some of the prints will not appear on the + * serial output + */ +#ifdef XPAR_XUARTPS_0_BASEADDR + UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET); + while ((UartReg & XUARTPS_SR_TXEMPTY) != XUARTPS_SR_TXEMPTY) { + UartReg = Xil_In32(STDOUT_BASEADDRESS + XUARTPS_SR_OFFSET); + } +#endif +#endif +} + +/******************************************************************************/ +/** +* +* This function handles the error and lockdown processing and outputs the status +* for the provided State in the boot process. +* +* This function is called upon exceptions. +* +* @param State - where in the boot process the error occured. +* +* @return None. +* +* @note This function does not return, the PS block is reset +* +****************************************************************************/ +void ErrorLockdown(u32 State) +{ + /* + * Store the error status + */ + OutputStatus(State); + + /* + * Fall back + */ + FsblFallback(); +} + +/******************************************************************************/ +/** +* +* This function copies a memory region to another memory region +* +* @param s1 is starting address for destination +* @param s2 is starting address for the source +* @param n is the number of bytes to copy +* +* @return Starting address for destination +* +****************************************************************************/ +void *(memcpy_rom)(void * s1, const void * s2, u32 n) +{ + char *dst = (char *)s1; + const char *src = (char *)s2; + + /* + * Loop and copy + */ + while (n-- != 0) + *dst++ = *src++; + return s1; +} +/******************************************************************************/ +/** +* +* This function copies a string to another, the source string must be null- +* terminated. +* +* @param Dest is starting address for the destination string +* @param Src is starting address for the source string +* +* @return Starting address for the destination string +* +****************************************************************************/ +char *strcpy_rom(char *Dest, const char *Src) +{ + unsigned i; + for (i=0; Src[i] != '\0'; ++i) + Dest[i] = Src[i]; + Dest[i] = '\0'; + return Dest; +} + + +/******************************************************************************/ +/** +* +* This function sets FSBL is running mask in reboot status register +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void MarkFSBLIn(void) +{ + Xil_Out32(REBOOT_STATUS_REG, + Xil_In32(REBOOT_STATUS_REG) | FSBL_IN_MASK); +} + + +/******************************************************************************/ +/** +* +* This function clears FSBL is running mask in reboot status register +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void ClearFSBLIn(void) +{ + Xil_Out32(REBOOT_STATUS_REG, + (Xil_In32(REBOOT_STATUS_REG)) & ~(FSBL_FAIL_MASK)); +} + +/******************************************************************************/ +/** +* +* This function Registers the Exception Handlers +* +* @param None. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +static void RegisterHandlers(void) +{ + Xil_ExceptionInit(); + + /* + * Initialize the vector table. Register the stub Handler for each + * exception. + */ + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_UNDEFINED_INT, + (Xil_ExceptionHandler)Undef_Handler, + (void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_SWI_INT, + (Xil_ExceptionHandler)SVC_Handler, + (void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_PREFETCH_ABORT_INT, + (Xil_ExceptionHandler)PreFetch_Abort_Handler, + (void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_DATA_ABORT_INT, + (Xil_ExceptionHandler)Data_Abort_Handler, + (void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, + (Xil_ExceptionHandler)IRQ_Handler,(void *) 0); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_FIQ_INT, + (Xil_ExceptionHandler)FIQ_Handler,(void *) 0); + + Xil_ExceptionEnable(); + +} + +static void Undef_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"UNDEFINED_HANDLER\r\n"); + ErrorLockdown (EXCEPTION_ID_UNDEFINED_INT); +} + +static void SVC_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"SVC_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_SWI_INT); +} + +static void PreFetch_Abort_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"PREFETCH_ABORT_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_PREFETCH_ABORT_INT); +} + +static void Data_Abort_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"DATA_ABORT_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_DATA_ABORT_INT); +} + +static void IRQ_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"IRQ_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_IRQ_INT); +} + +static void FIQ_Handler (void) +{ + fsbl_printf(DEBUG_GENERAL,"FIQ_HANDLER \r\n"); + ErrorLockdown (EXCEPTION_ID_FIQ_INT); +} + + +/******************************************************************************/ +/** +* +* This function Updates the Multi boot Register to enable golden image +* search for boot rom +* +* @param None +* +* @return +* return none +* +****************************************************************************/ +static void Update_MultiBootRegister(void) +{ + u32 MultiBootReg = 0; + + if (Silicon_Version != SILICON_VERSION_1) { + /* + * Read the mulitboot register + */ + MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET); + + /* + * Incrementing multiboot register by one + */ + MultiBootReg++; + + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET, + MultiBootReg); + + fsbl_printf(DEBUG_INFO,"Updated MultiBootReg = 0x%08lx\r\n", + MultiBootReg); + } +} + + +/****************************************************************************** +* +* This function reset the CPU and goes for Boot ROM fallback handling +* +* @param None +* +* @return None +* +* @note None +* +*******************************************************************************/ + +u32 GetResetReason(void) +{ + u32 Regval; + + /* We are using REBOOT_STATUS_REG, we have to use bits 23:16 */ + /* for storing the RESET_REASON register value*/ + Regval = ((Xil_In32(REBOOT_STATUS_REG) >> 16) & 0xFF); + + return Regval; +} + + +/****************************************************************************** +* +* This function Gets the ticks from the Global Timer +* +* @param Current time +* +* @return +* None +* +* @note None +* +*******************************************************************************/ +#ifdef FSBL_PERF +void FsblGetGlobalTime (XTime *tCur) +{ + XTime_GetTime(tCur); +} + + +/****************************************************************************** +* +* This function Measures the execution time +* +* @param Current time , End time +* +* @return +* None +* +* @note None +* +*******************************************************************************/ +void FsblMeasurePerfTime (XTime tCur, XTime tEnd) +{ + double tDiff = 0.0; + double tPerfSeconds; + XTime_GetTime(&tEnd); + tDiff = (double)tEnd - (double)tCur; + + /* + * Convert tPerf into Seconds + */ + tPerfSeconds = tDiff/COUNTS_PER_SECOND; + +#if defined(STDOUT_BASEADDRESS) + printf("%f seconds \r\n",tPerfSeconds); +#endif + +} +#endif + +/****************************************************************************** +* +* This function initializes the Watchdog driver and starts the timer +* +* @param None +* +* @return +* - XST_SUCCESS if the Watchdog driver is initialized +* - XST_FAILURE if Watchdog driver initialization fails +* +* @note None +* +*******************************************************************************/ +#ifdef XPAR_XWDTPS_0_BASEADDR +int InitWatchDog(void) +{ + u32 Status = XST_SUCCESS; + XWdtPs_Config *ConfigPtr; /* Config structure of the WatchDog Timer */ + u32 CounterValue = 1; + + ConfigPtr = XWdtPs_LookupConfig(WDT_DEVICE_ID); + Status = XWdtPs_CfgInitialize(&Watchdog, + ConfigPtr, + ConfigPtr->BaseAddress); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"Watchdog Driver init Failed \n\r"); + return XST_FAILURE; + } + + /* + * Setting the divider value + */ + XWdtPs_SetControlValue(&Watchdog, + XWDTPS_CLK_PRESCALE, + XWDTPS_CCR_PSCALE_4096); + /* + * Convert time to Watchdog counter reset value + */ + CounterValue = ConvertTime_WdtCounter(WDT_EXPIRE_TIME); + + /* + * Set the Watchdog counter reset value + */ + XWdtPs_SetControlValue(&Watchdog, + XWDTPS_COUNTER_RESET, + CounterValue); + /* + * enable reset output, as we are only using this as a basic counter + */ + XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL); + + /* + * Start the Watchdog timer + */ + XWdtPs_Start(&Watchdog); + + XWdtPs_RestartWdt(&Watchdog); + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function checks whether WDT reset has happened during FSBL run +* +* If WDT reset happened during FSBL run, then need to fallback +* +* @param None. +* +* @return +* None +* +* @note None +* +****************************************************************************/ +void CheckWDTReset(void) +{ + u32 ResetReason; + u32 RebootStatusRegister; + + RebootStatusRegister = Xil_In32(REBOOT_STATUS_REG); + + /* + * For 1.0 Silicon the reason for Reset is in the ResetReason Register + * Hence this register can be read to know the cause for previous reset + * that happened. + * Check if that reset is a Software WatchDog reset that happened + */ + if (Silicon_Version == SILICON_VERSION_1) { + ResetReason = Xil_In32(RESET_REASON_REG); + } else { + ResetReason = GetResetReason(); + } + /* + * If the FSBL_IN_MASK Has not been cleared, WDT happened + * before FSBL exits + */ + if ((ResetReason & RESET_REASON_SWDT) == RESET_REASON_SWDT ) { + if ((RebootStatusRegister & FSBL_FAIL_MASK) == FSBL_IN_MASK) { + /* + * Clear the SWDT Reset bit + */ + ResetReason &= ~RESET_REASON_SWDT; + if (Silicon_Version == SILICON_VERSION_1) { + /* + * for 1.0 Silicon we need to write + * 1 to the RESET REASON Clear register + */ + Xil_Out32(RESET_REASON_CLR, 1); + } else { + Xil_Out32(REBOOT_STATUS_REG, ResetReason); + } + + fsbl_printf(DEBUG_GENERAL,"WDT_RESET_OCCURED \n\r"); + } + } +} + + +/****************************************************************************** +* +* This function converts time into Watchdog counter value +* +* @param watchdog expire time in seconds +* +* @return +* Counter value for Watchdog +* +* @note None +* +*******************************************************************************/ +u32 ConvertTime_WdtCounter(u32 seconds) +{ + double time = 0.0; + double CounterValue; + u32 Crv = 0; + u32 Prescaler,PrescalerValue; + + Prescaler = XWdtPs_GetControlValue(&Watchdog, XWDTPS_CLK_PRESCALE); + + if (Prescaler == XWDTPS_CCR_PSCALE_0008) + PrescalerValue = 8; + if (Prescaler == XWDTPS_CCR_PSCALE_0064) + PrescalerValue = 64; + if (Prescaler == XWDTPS_CCR_PSCALE_4096) + PrescalerValue = 4096; + + time = (double)(PrescalerValue) / (double)XPAR_PS7_WDT_0_WDT_CLK_FREQ_HZ; + + CounterValue = seconds / time; + + Crv = (u32)CounterValue; + Crv >>= WDT_CRV_SHIFT; + + return Crv; +} + +#endif + + +/****************************************************************************** +* +* This function Gets the Silicon Version stores in global variable +* +* @param None +* +* @return None +* +* @note None +* +*******************************************************************************/ +void GetSiliconVersion(void) +{ + /* + * Get the silicon version + */ + Silicon_Version = XDcfg_GetPsVersion(DcfgInstPtr); + if(Silicon_Version == SILICON_VERSION_3_1) { + fsbl_printf(DEBUG_GENERAL,"Silicon Version 3.1\r\n"); + } else { + fsbl_printf(DEBUG_GENERAL,"Silicon Version %lu.0\r\n", + Silicon_Version + 1); + } +} + + +/****************************************************************************** +* +* This function HeaderChecksum will calculates the header checksum and +* compares with checksum read from flash +* +* @param FlashOffsetAddress Flash offset address +* +* @return +* - XST_SUCCESS if ID matches +* - XST_FAILURE if ID mismatches +* +* @note None +* +*******************************************************************************/ +u32 HeaderChecksum(u32 FlashOffsetAddress){ + u32 Checksum = 0; + u32 Count; + u32 TempValue = 0; + + for (Count = 0; Count < IMAGE_HEADER_CHECKSUM_COUNT; Count++) { + /* + * Read the word from the header + */ + MoveImage(FlashOffsetAddress + IMAGE_WIDTH_CHECK_OFFSET + (Count*4), (u32)&TempValue, 4); + + /* + * Update checksum + */ + Checksum += TempValue; + } + + /* + * Invert checksum, last bit of error checking + */ + Checksum ^= 0xFFFFFFFF; + MoveImage(FlashOffsetAddress + IMAGE_CHECKSUM_OFFSET, (u32)&TempValue, 4); + + /* + * Validate the checksum + */ + if (TempValue != Checksum){ + fsbl_printf(DEBUG_INFO, "Checksum = %8.8lx\r\n", Checksum); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/****************************************************************************** +* +* This function ImageCheckID will do check for XLNX pattern +* +* @param FlashOffsetAddress Flash offset address +* +* @return +* - XST_SUCCESS if ID matches +* - XST_FAILURE if ID mismatches +* +* @note None +* +*******************************************************************************/ +u32 ImageCheckID(u32 FlashOffsetAddress){ + u32 ID; + + /* + * Read in the header info + */ + MoveImage(FlashOffsetAddress + IMAGE_IDENT_OFFSET, (u32)&ID, 4); + + /* + * Check the ID, make sure image is XLNX format + */ + if (ID != IMAGE_IDENT){ + return XST_FAILURE; + } + + return XST_SUCCESS; +} + + +/****************************************************************************** +* +* This function NextValidImageCheck search for valid boot image +* +* @param None +* +* @return +* - XST_SUCCESS if valid image found +* - XST_FAILURE if no image found +* +* @note None +* +*******************************************************************************/ +u32 NextValidImageCheck(void) +{ + u32 ImageBaseAddr; + u32 MultiBootReg; + u32 BootDevMaxSize=0; + + fsbl_printf(DEBUG_GENERAL, "Searching For Next Valid Image"); + + /* + * Setting variable with maximum flash size based on boot mode + */ +#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR + if (FlashReadBaseAddress == XPS_QSPI_LINEAR_BASEADDR) { + BootDevMaxSize = QspiFlashSize; + } +#endif + + if (FlashReadBaseAddress == XPS_NAND_BASEADDR) { + BootDevMaxSize = NAND_FLASH_SIZE; + } + + if (FlashReadBaseAddress == XPS_NOR_BASEADDR) { + BootDevMaxSize = NOR_FLASH_SIZE; + } + + /* + * Read the multiboot register + */ + MultiBootReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET); + + /* + * Compute the image start address + */ + ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK) + * GOLDEN_IMAGE_OFFSET; + + /* + * Valid image search continue till end of the flash + * With increment 32KB in each iteration + */ + while (ImageBaseAddr < BootDevMaxSize) { + + fsbl_printf(DEBUG_INFO,"."); + + /* + * Valid image search using XLNX pattern at fixed offset + * and header checksum + */ + if ((ImageCheckID(ImageBaseAddr) == XST_SUCCESS) && + (HeaderChecksum(ImageBaseAddr) == XST_SUCCESS)) { + + fsbl_printf(DEBUG_GENERAL, "\r\nImage found, offset: 0x%.8lx\r\n", + ImageBaseAddr); + /* + * Update multiboot register + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_MULTIBOOT_ADDR_OFFSET, + MultiBootReg); + + return XST_SUCCESS; + } + + /* + * Increment mulitboot count + */ + MultiBootReg++; + + /* + * Compute the image start address + */ + ImageBaseAddr = (MultiBootReg & PCAP_MBOOT_REG_REBOOT_OFFSET_MASK) + * GOLDEN_IMAGE_OFFSET; + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** +* +* This function Checks for the ddr initialization completion +* +* @param None. +* +* @return +* - XST_SUCCESS if the initialization is successful +* - XST_FAILURE if the initialization is NOT successful +* +* @note None. +* +****************************************************************************/ +u32 DDRInitCheck(void) +{ + u32 ReadVal; + + /* + * Write and Read from the DDR location for sanity checks + */ + Xil_Out32(DDR_START_ADDR, DDR_TEST_PATTERN); + ReadVal = Xil_In32(DDR_START_ADDR); + if (ReadVal != DDR_TEST_PATTERN) { + return XST_FAILURE; + } + + /* + * Write and Read from the DDR location for sanity checks + */ + Xil_Out32(DDR_START_ADDR + DDR_TEST_OFFSET, DDR_TEST_PATTERN); + ReadVal = Xil_In32(DDR_START_ADDR + DDR_TEST_OFFSET); + if (ReadVal != DDR_TEST_PATTERN) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/md5.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/md5.c new file mode 100644 index 0000000..e7cf7ea --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/md5.c @@ -0,0 +1,484 @@ +/* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) + * All rights reserved. + * + * This package is an SSL implementation written + * by Eric Young (eay@cryptsoft.com). + * The implementation was written so as to conform with Netscapes SSL. + * + * This library is free for commercial and non-commercial use as long as + * the following conditions are aheared to. The following conditions + * apply to all code found in this distribution, be it the RC4, RSA, + * lhash, DES, etc., code; not just the SSL code. The SSL documentation + * included with this distribution is covered by the same copyright terms + * except that the holder is Tim Hudson (tjh@cryptsoft.com). + * + * Copyright remains Eric Young's, and as such any Copyright notices in + * the code are not to be removed. + * If this package is used in a product, Eric Young should be given attribution + * as the author of the parts of the library used. + * This can be in the form of a textual message at program startup or + * in documentation (online or textual) provided with the package. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * "This product includes cryptographic software written by + * Eric Young (eay@cryptsoft.com)" + * The word 'cryptographic' can be left out if the rouines from the library + * being used are not cryptographic related :-). + * 4. If you include any Windows specific code (or a derivative thereof) from + * the apps directory (application code) you must include an acknowledgement: + * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" + * + * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * The licence and distribution terms for any publically available version or + * derivative of this code cannot be changed. i.e. this code cannot simply be + * copied and put under another distribution licence + * [including the GNU Public Licence.] + */ +/*****************************************************************************/ +/** +* +* @file md5.c +* +* Contains code to calculate checksum using md5 algorithm +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00a sgd	05/17/13 Initial release
+*
+*
+*
    +* +* @note +* +******************************************************************************/ +/****************************** Include Files *********************************/ + +#include "md5.h" + +/******************************************************************************/ +/** +* +* This function sets the memory +* +* @param dest +* +* @param ch +* +* @param count +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void * MD5Memset( void *dest, int ch, u32 count ) +{ + register char *dst8 = (char*)dest; + + while( count-- ) + *dst8++ = ch; + + return dest; +} + +/******************************************************************************/ +/** +* +* This function copy the memory +* +* @param dest +* +* @param ch +* +* @param count +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void * MD5Memcpy( void *dest, const void *src, + u32 count, boolean doByteSwap ) +{ + register char * dst8 = (char*)dest; + register char * src8 = (char*)src; + + if( doByteSwap == FALSE ) { + while( count-- ) + *dst8++ = *src8++; + } else { + count /= sizeof( u32 ); + + while( count-- ) { + dst8[ 0 ] = src8[ 3 ]; + dst8[ 1 ] = src8[ 2 ]; + dst8[ 2 ] = src8[ 1 ]; + dst8[ 3 ] = src8[ 0 ]; + + dst8 += 4; + src8 += 4; + } + } + + return dest; +} + +/******************************************************************************/ +/** +* +* This function is the core of the MD5 algorithm, +* this alters an existing MD5 hash to +* reflect the addition of 16 longwords of new data. MD5Update blocks +* the data and converts bytes into longwords for this routine. +* +* Use binary integer part of the sine of integers (Radians) as constants. +* Calculated as: +* +* for( i = 0; i < 63; i++ ) +* k[ i ] := floor( abs( sin( i + 1 ) ) Ă— pow( 2, 32 ) ) +* +* Following number is the per-round shift amount. +* +* @param dest +* +* @param ch +* +* @param count +* +* @return None +* +* @note None +* +****************************************************************************/ +void MD5Transform( u32 *buffer, u32 *intermediate ) +{ + register u32 a, b, c, d; + + a = buffer[ 0 ]; + b = buffer[ 1 ]; + c = buffer[ 2 ]; + d = buffer[ 3 ]; + + MD5_STEP( F1, a, b, c, d, intermediate[ 0 ] + 0xd76aa478, 7 ); + MD5_STEP( F1, d, a, b, c, intermediate[ 1 ] + 0xe8c7b756, 12 ); + MD5_STEP( F1, c, d, a, b, intermediate[ 2 ] + 0x242070db, 17 ); + MD5_STEP( F1, b, c, d, a, intermediate[ 3 ] + 0xc1bdceee, 22 ); + MD5_STEP( F1, a, b, c, d, intermediate[ 4 ] + 0xf57c0faf, 7 ); + MD5_STEP( F1, d, a, b, c, intermediate[ 5 ] + 0x4787c62a, 12 ); + MD5_STEP( F1, c, d, a, b, intermediate[ 6 ] + 0xa8304613, 17 ); + MD5_STEP( F1, b, c, d, a, intermediate[ 7 ] + 0xfd469501, 22 ); + MD5_STEP( F1, a, b, c, d, intermediate[ 8 ] + 0x698098d8, 7 ); + MD5_STEP( F1, d, a, b, c, intermediate[ 9 ] + 0x8b44f7af, 12 ); + MD5_STEP( F1, c, d, a, b, intermediate[ 10 ] + 0xffff5bb1, 17 ); + MD5_STEP( F1, b, c, d, a, intermediate[ 11 ] + 0x895cd7be, 22 ); + MD5_STEP( F1, a, b, c, d, intermediate[ 12 ] + 0x6b901122, 7 ); + MD5_STEP( F1, d, a, b, c, intermediate[ 13 ] + 0xfd987193, 12 ); + MD5_STEP( F1, c, d, a, b, intermediate[ 14 ] + 0xa679438e, 17 ); + MD5_STEP( F1, b, c, d, a, intermediate[ 15 ] + 0x49b40821, 22 ); + + MD5_STEP( F2, a, b, c, d, intermediate[ 1 ] + 0xf61e2562, 5 ); + MD5_STEP( F2, d, a, b, c, intermediate[ 6 ] + 0xc040b340, 9 ); + MD5_STEP( F2, c, d, a, b, intermediate[ 11 ] + 0x265e5a51, 14 ); + MD5_STEP( F2, b, c, d, a, intermediate[ 0 ] + 0xe9b6c7aa, 20 ); + MD5_STEP( F2, a, b, c, d, intermediate[ 5 ] + 0xd62f105d, 5 ); + MD5_STEP( F2, d, a, b, c, intermediate[ 10 ] + 0x02441453, 9 ); + MD5_STEP( F2, c, d, a, b, intermediate[ 15 ] + 0xd8a1e681, 14 ); + MD5_STEP( F2, b, c, d, a, intermediate[ 4 ] + 0xe7d3fbc8, 20 ); + MD5_STEP( F2, a, b, c, d, intermediate[ 9 ] + 0x21e1cde6, 5 ); + MD5_STEP( F2, d, a, b, c, intermediate[ 14 ] + 0xc33707d6, 9 ); + MD5_STEP( F2, c, d, a, b, intermediate[ 3 ] + 0xf4d50d87, 14 ); + MD5_STEP( F2, b, c, d, a, intermediate[ 8 ] + 0x455a14ed, 20 ); + MD5_STEP( F2, a, b, c, d, intermediate[ 13 ] + 0xa9e3e905, 5 ); + MD5_STEP( F2, d, a, b, c, intermediate[ 2 ] + 0xfcefa3f8, 9 ); + MD5_STEP( F2, c, d, a, b, intermediate[ 7 ] + 0x676f02d9, 14 ); + MD5_STEP( F2, b, c, d, a, intermediate[ 12 ] + 0x8d2a4c8a, 20 ); + + MD5_STEP( F3, a, b, c, d, intermediate[ 5 ] + 0xfffa3942, 4 ); + MD5_STEP( F3, d, a, b, c, intermediate[ 8 ] + 0x8771f681, 11 ); + MD5_STEP( F3, c, d, a, b, intermediate[ 11 ] + 0x6d9d6122, 16 ); + MD5_STEP( F3, b, c, d, a, intermediate[ 14 ] + 0xfde5380c, 23 ); + MD5_STEP( F3, a, b, c, d, intermediate[ 1 ] + 0xa4beea44, 4 ); + MD5_STEP( F3, d, a, b, c, intermediate[ 4 ] + 0x4bdecfa9, 11 ); + MD5_STEP( F3, c, d, a, b, intermediate[ 7 ] + 0xf6bb4b60, 16 ); + MD5_STEP( F3, b, c, d, a, intermediate[ 10 ] + 0xbebfbc70, 23 ); + MD5_STEP( F3, a, b, c, d, intermediate[ 13 ] + 0x289b7ec6, 4 ); + MD5_STEP( F3, d, a, b, c, intermediate[ 0 ] + 0xeaa127fa, 11 ); + MD5_STEP( F3, c, d, a, b, intermediate[ 3 ] + 0xd4ef3085, 16 ); + MD5_STEP( F3, b, c, d, a, intermediate[ 6 ] + 0x04881d05, 23 ); + MD5_STEP( F3, a, b, c, d, intermediate[ 9 ] + 0xd9d4d039, 4 ); + MD5_STEP( F3, d, a, b, c, intermediate[ 12 ] + 0xe6db99e5, 11 ); + MD5_STEP( F3, c, d, a, b, intermediate[ 15 ] + 0x1fa27cf8, 16 ); + MD5_STEP( F3, b, c, d, a, intermediate[ 2 ] + 0xc4ac5665, 23 ); + + MD5_STEP( F4, a, b, c, d, intermediate[ 0 ] + 0xf4292244, 6 ); + MD5_STEP( F4, d, a, b, c, intermediate[ 7 ] + 0x432aff97, 10 ); + MD5_STEP( F4, c, d, a, b, intermediate[ 14 ] + 0xab9423a7, 15 ); + MD5_STEP( F4, b, c, d, a, intermediate[ 5 ] + 0xfc93a039, 21 ); + MD5_STEP( F4, a, b, c, d, intermediate[ 12 ] + 0x655b59c3, 6 ); + MD5_STEP( F4, d, a, b, c, intermediate[ 3 ] + 0x8f0ccc92, 10 ); + MD5_STEP( F4, c, d, a, b, intermediate[ 10 ] + 0xffeff47d, 15 ); + MD5_STEP( F4, b, c, d, a, intermediate[ 1 ] + 0x85845dd1, 21 ); + MD5_STEP( F4, a, b, c, d, intermediate[ 8 ] + 0x6fa87e4f, 6 ); + MD5_STEP( F4, d, a, b, c, intermediate[ 15 ] + 0xfe2ce6e0, 10 ); + MD5_STEP( F4, c, d, a, b, intermediate[ 6 ] + 0xa3014314, 15 ); + MD5_STEP( F4, b, c, d, a, intermediate[ 13 ] + 0x4e0811a1, 21 ); + MD5_STEP( F4, a, b, c, d, intermediate[ 4 ] + 0xf7537e82, 6 ); + MD5_STEP( F4, d, a, b, c, intermediate[ 11 ] + 0xbd3af235, 10 ); + MD5_STEP( F4, c, d, a, b, intermediate[ 2 ] + 0x2ad7d2bb, 15 ); + MD5_STEP( F4, b, c, d, a, intermediate[ 9 ] + 0xeb86d391, 21 ); + + buffer[ 0 ] += a; + buffer[ 1 ] += b; + buffer[ 2 ] += c; + buffer[ 3 ] += d; + +} + +/******************************************************************************/ +/** +* +* This function Start MD5 accumulation +* Set bit count to 0 and buffer to mysterious initialization constants +* +* @param +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void MD5Init( MD5Context *context ) +{ + + context->buffer[ 0 ] = 0x67452301; + context->buffer[ 1 ] = 0xefcdab89; + context->buffer[ 2 ] = 0x98badcfe; + context->buffer[ 3 ] = 0x10325476; + + context->bits[ 0 ] = 0; + context->bits[ 1 ] = 0; + +} + + +/******************************************************************************/ +/** +* +* This function updates context to reflect the concatenation of another +* buffer full of bytes +* +* @param +* +* @param +* +* @param +* +* @param +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void MD5Update( MD5Context *context, u8 *buffer, + u32 len, boolean doByteSwap ) +{ + register u32 temp; + register u8 * p; + + /* + * Update bitcount + */ + + temp = context->bits[ 0 ]; + + if( ( context->bits[ 0 ] = temp + ( (u32)len << 3 ) ) < temp ) { + /* + * Carry from low to high + */ + context->bits[ 1 ]++; + } + + context->bits[ 1 ] += len >> 29; + + /* + * Bytes already in shsInfo->data + */ + + temp = ( temp >> 3 ) & 0x3f; + + /* + * Handle any leading odd-sized chunks + */ + + if( temp ) { + p = (u8 *)context->intermediate + temp; + + temp = MD5_SIGNATURE_BYTE_SIZE - temp; + + if( len < temp ) { + MD5Memcpy( p, buffer, len, doByteSwap ); + return; + } + + MD5Memcpy( p, buffer, temp, doByteSwap ); + + MD5Transform( context->buffer, (u32 *)context->intermediate ); + + buffer += temp; + len -= temp; + + } + + /* + * Process data in 64-byte, 512 bit, chunks + */ + + while( len >= MD5_SIGNATURE_BYTE_SIZE ) { + MD5Memcpy( context->intermediate, buffer, MD5_SIGNATURE_BYTE_SIZE, + doByteSwap ); + + MD5Transform( context->buffer, (u32 *)context->intermediate ); + + buffer += MD5_SIGNATURE_BYTE_SIZE; + len -= MD5_SIGNATURE_BYTE_SIZE; + + } + + /* + * Handle any remaining bytes of data + */ + MD5Memcpy( context->intermediate, buffer, len, doByteSwap ); + +} + +/******************************************************************************/ +/** +* +* This function final wrap-up - pad to 64-byte boundary with the bit pattern +* 1 0* (64-bit count of bits processed, MSB-first +* +* @param +* +* @param +* +* @param +* +* @param +* +* @return None +* +* @note None +* +****************************************************************************/ +inline void MD5Final( MD5Context *context, u8 *digest, + boolean doByteSwap ) +{ + u32 count; + u8 * p; + + /* + * Compute number of bytes mod 64 + */ + count = ( context->bits[ 0 ] >> 3 ) & 0x3F; + + /* + * Set the first char of padding to 0x80. This is safe since there is + * always at least one byte free + */ + p = context->intermediate + count; + *p++ = 0x80; + + /* + * Bytes of padding needed to make 64 bytes + */ + count = MD5_SIGNATURE_BYTE_SIZE - 1 - count; + + /* + * Pad out to 56 mod 64 + */ + if( count < 8 ) { + /* + * Two lots of padding: Pad the first block to 64 bytes + */ + MD5Memset( p, 0, count ); + + MD5Transform( context->buffer, (u32 *)context->intermediate ); + + /* + * Now fill the next block with 56 bytes + */ + MD5Memset( context->intermediate, 0, 56 ); + } else { + /* + * Pad block to 56 bytes + */ + MD5Memset( p, 0, count - 8 ); + } + + /* + * Append length in bits and transform + */ + ( (u32 *)context->intermediate )[ 14 ] = context->bits[ 0 ]; + ( (u32 *)context->intermediate )[ 15 ] = context->bits[ 1 ]; + + MD5Transform( context->buffer, (u32 *)context->intermediate ); + + /* + * Now return the digest + */ + MD5Memcpy( digest, context->buffer, 16, doByteSwap ); +} + +/******************************************************************************/ +/** +* +* This function calculate and store in 'digest' the MD5 digest of 'len' bytes at +* 'input'. 'digest' must have enough space to hold 16 bytes +* +* @param +* +* @param +* +* @param +* +* @param +* +* @return None +* +* @note None +* +****************************************************************************/ +void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap ) +{ + MD5Context context; + + MD5Init( &context ); + + MD5Update( &context, input, len, doByteSwap ); + + MD5Final( &context, digest, doByteSwap ); +} diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/md5.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/md5.h new file mode 100644 index 0000000..1b28ddd --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/md5.h @@ -0,0 +1,120 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file md5.h +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00a sgd	05/17/13 Initial release
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___MD5_H___ +#define ___MD5_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +#define MD5_SIGNATURE_BYTE_SIZE 64 + +/**************************** Type Definitions *******************************/ + +typedef u8 boolean; +typedef u8 signature[ MD5_SIGNATURE_BYTE_SIZE ]; + +struct MD5Context + { + u32 buffer[ 4 ]; + u32 bits[ 2 ]; + signature intermediate; + }; +typedef struct MD5Context MD5Context; + +/***************** Macros (Inline Functions) Definitions *********************/ + +/* + * The four core functions - F1 is optimized somewhat + */ +#define F1( x, y, z ) ( z ^ ( x & ( y ^ z ) ) ) +#define F2( x, y, z ) F1( z, x, y ) +#define F3( x, y, z ) ( x ^ y ^ z ) +#define F4( x, y, z ) ( y ^ ( x | ~z ) ) + + +/* + * This is the central step in the MD5 algorithm + */ +#define MD5_STEP( f, w, x, y, z, data, s ) \ + ( w += f( x, y, z ) + data, w = w << s | w >> ( 32 - s ), w += x ) + + +/************************** Function Prototypes ******************************/ + +void * MD5Memset( void *dest, int ch, u32 count ); + +void * MD5Memcpy( void *dest, const void *src, u32 count, boolean doByteSwap ); + +void MD5Transform( u32 *buffer, u32 *intermediate ); + +void MD5Init( MD5Context *context ); + +void MD5Update( MD5Context *context, u8 *buffer, u32 len, boolean doByteSwap ); + +void MD5Final( MD5Context *context, u8 *digest, boolean doByteSwap ); + +void md5( u8 *input, u32 len, u8 *digest, boolean doByteSwap ); + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif + + +#endif /* ___MD5_H___ */ diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nand.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nand.c new file mode 100644 index 0000000..9bf4ec0 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nand.c @@ -0,0 +1,295 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file nand.c +* +* Contains code for the NAND FLASH functionality. Bad Block management +* is simple: skip the bad blocks and keep going. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 2.00a  mb	25/05/12 fsbl changes for standalone bsp based
+* 3.00a sgd	30/01/13 Code cleanup
+* 5.00a sgd	17/05/13 Support for Multi Boot
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xparameters.h" +#include "fsbl.h" +#ifdef XPAR_PS7_NAND_0_BASEADDR +#include "nand.h" +#include "xnandps_bbm.h" + + +/************************** Constant Definitions *****************************/ + +#define NAND_DEVICE_ID XPAR_XNANDPS_0_DEVICE_ID + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr, + u64 Offset, + u32 Length); + +/************************** Variable Definitions *****************************/ + +extern u32 FlashReadBaseAddress; +extern u32 FlashOffsetAddress; + +XNandPs *NandInstPtr; +XNandPs NandInstance; /* XNand Instance. */ + +/******************************************************************************/ +/** +* +* This function initializes the controller for the NAND FLASH interface. +* +* @param none +* +* @return +* - XST_SUCCESS if the controller initializes correctly +* - XST_FAILURE if the controller fails to initializes correctly +* +* @note none. +* +****************************************************************************/ +u32 InitNand(void) +{ + + u32 Status; + XNandPs_Config *ConfigPtr; + + /* + * Set up pointers to instance and the config structure + */ + NandInstPtr = &NandInstance; + + /* + * Initialize the flash driver. + */ + ConfigPtr = XNandPs_LookupConfig(NAND_DEVICE_ID); + + if (ConfigPtr == NULL) { + fsbl_printf(DEBUG_GENERAL,"Nand Driver failed \n \r"); + return XST_FAILURE; + } + + Status = XNandPs_CfgInitialize(NandInstPtr, ConfigPtr, + ConfigPtr->SmcBase,ConfigPtr->FlashBase); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"NAND intialization failed \n \r"); + return XST_FAILURE; + } + + /* + * Set up base address for access + */ + FlashReadBaseAddress = XPS_NAND_BASEADDR; + + fsbl_printf(DEBUG_INFO,"InitNand: Geometry = 0x%x\r\n", + NandInstPtr->Geometry.FlashWidth); + + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_GENERAL,"InitNand: Status = 0x%.8x\r\n", + Status); + return XST_FAILURE; + } + + /* + * set up the FLASH access pointers + */ + fsbl_printf(DEBUG_INFO,"Nand driver initialized \n\r"); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** +* +* This function provides the NAND FLASH interface for the Simplified header +* functionality. This function handles bad blocks. +* +* The source address is the absolute good address, bad blocks are skipped +* without incrementing the source address. +* +* @param SourceAddress is address in FLASH data space, absolute good address +* @param DestinationAddress is address in OCM data space +* +* @return XST_SUCCESS if the transfer completes correctly +* XST_FAILURE if the transfer fails to completes correctly +* +* @note none. +* +****************************************************************************/ +u32 NandAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes) +{ + u32 ActLen; + u32 BlockOffset; + u32 Block; + u32 Status; + u32 BytesLeft = LengthBytes; + u32 BlockSize = NandInstPtr->Geometry.BlockSize; + u8 *BufPtr = (u8 *)DestinationAddress; + u32 ReadLen; + u32 BlockReadLen; + u32 Offset; + u32 TmpAddress = 0 ; + u32 BlockCount = 0; + u32 BadBlocks = 0; + + /* + * First get bad blocks before the source address + */ + while (TmpAddress < SourceAddress) { + while (XNandPs_IsBlockBad(NandInstPtr, BlockCount) == + XST_SUCCESS) { + BlockCount ++; + BadBlocks ++; + } + + TmpAddress += BlockSize; + BlockCount ++; + } + + Offset = SourceAddress + BadBlocks * BlockSize; + + /* + * Calculate the actual length including bad blocks + */ + ActLen = XNandPs_CalculateLength(NandInstPtr, Offset, LengthBytes); + + /* + * Check if the actual length cross flash size + */ + if (Offset + ActLen > NandInstPtr->Geometry.DeviceSize) { + return XST_FAILURE; + } + + while (BytesLeft > 0) { + BlockOffset = Offset & (BlockSize - 1); + Block = (Offset & ~(BlockSize - 1))/BlockSize; + BlockReadLen = BlockSize - BlockOffset; + + Status = XNandPs_IsBlockBad(NandInstPtr, Block); + if (Status == XST_SUCCESS) { + /* Move to next block */ + Offset += BlockReadLen; + continue; + } + + /* + * Check if we cross block boundary + */ + if (BytesLeft < BlockReadLen) { + ReadLen = BytesLeft; + } else { + ReadLen = BlockReadLen; + } + + /* + * Read from the NAND flash + */ + Status = XNandPs_Read(NandInstPtr, Offset, ReadLen, BufPtr, NULL); + if (Status != XST_SUCCESS) { + return Status; + } + BytesLeft -= ReadLen; + Offset += ReadLen; + BufPtr += ReadLen; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function returns the length including bad blocks from a given offset and +* length. +* +* @param NandInstPtr is the pointer to the XNandPs instance. +* @param Offset is the flash data address to read from. +* @param Length is number of bytes to read. +* +* @return +* - Return actual length including bad blocks. +* +* @note None. +* +******************************************************************************/ +static u32 XNandPs_CalculateLength(XNandPs *NandInstPtr, + u64 Offset, + u32 Length) +{ + u32 BlockSize = NandInstPtr->Geometry.BlockSize; + u32 CurBlockLen; + u32 CurBlock; + u32 Status; + u32 TempLen = 0; + u32 ActLen = 0; + + while (TempLen < Length) { + CurBlockLen = BlockSize - (Offset & (BlockSize - 1)); + CurBlock = (Offset & ~(BlockSize - 1))/BlockSize; + + /* + * Check if the block is bad + */ + Status = XNandPs_IsBlockBad(NandInstPtr, CurBlock); + if (Status != XST_SUCCESS) { + /* Good Block */ + TempLen += CurBlockLen; + } + ActLen += CurBlockLen; + Offset += CurBlockLen; + if (Offset >= NandInstPtr->Geometry.DeviceSize) { + break; + } + } + + return ActLen; +} + +#endif diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nand.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nand.h new file mode 100644 index 0000000..1f5ee52 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nand.h @@ -0,0 +1,91 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file nand.h +* +* This file contains the interface for the NAND FLASH functionality +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 2.00a mb	30/05/12 added the flag XPAR_PS7_NAND_0_BASEADDR
+* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___NAND_H___ +#define ___NAND_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + + +#ifdef XPAR_PS7_NAND_0_BASEADDR + +#include "xnandps.h" +#include "xnandps_bbm.h" +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +u32 InitNand(void); + +u32 NandAccess( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthWords); +#endif +/************************** Variable Definitions *****************************/ + + +#ifdef __cplusplus +} +#endif + + +#endif /* ___NAND_H___ */ + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nor.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nor.c new file mode 100644 index 0000000..4705bcc --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nor.c @@ -0,0 +1,144 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file nor.c +* +* Contains code for the NOR FLASH functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 2.00a mb	25/05/12 mio init removed
+* 3.00a sgd	30/01/13 Code cleanup
+*
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "fsbl.h" +#include "nor.h" +#include "xstatus.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +extern u32 FlashReadBaseAddress; + +/******************************************************************************/ +/******************************************************************************/ +/** +* +* This function initializes the controller for the NOR FLASH interface. +* +* @param None +* +* @return None +* +* @note None. +* +****************************************************************************/ +void InitNor(void) +{ + + /* + * Set up the base address for access + */ + FlashReadBaseAddress = XPS_NOR_BASEADDR; +} + +/******************************************************************************/ +/** +* +* This function provides the NOR FLASH interface for the Simplified header +* functionality. +* +* @param SourceAddress is address in FLASH data space +* @param DestinationAddress is address in OCM data space +* @param LengthBytes is the data length to transfer in bytes +* +* @return +* - XST_SUCCESS if the write completes correctly +* - XST_FAILURE if the write fails to completes correctly +* +* @note None. +* +****************************************************************************/ +u32 NorAccess(u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes) +{ + u32 Data; + u32 Count; + u32 *SourceAddr; + u32 *DestAddr; + u32 LengthWords; + + /* + * check for non-word tail + * add bytes to cover the end + */ + if ((LengthBytes%4) != 0){ + + LengthBytes += (4 - (LengthBytes & 0x00000003)); + } + + LengthWords = LengthBytes >> WORD_LENGTH_SHIFT; + + SourceAddr = (u32 *)(SourceAddress + FlashReadBaseAddress); + DestAddr = (u32 *)(DestinationAddress); + + /* + * Word transfers, endianism isn't an issue + */ + for (Count=0; Count < LengthWords; Count++){ + + Data = Xil_In32((u32)(SourceAddr++)); + Xil_Out32((u32)(DestAddr++), Data); + } + + return XST_SUCCESS; +} + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nor.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nor.h new file mode 100644 index 0000000..4c15825 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/nor.h @@ -0,0 +1,87 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file nor.h +* +* This file contains the interface for the NOR FLASH functionality +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 10.00a kc 08/04/14 Fix for CR#809336 - Removed smc.h
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___NOR_H___ +#define ___NOR_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +/************************** Constant Definitions *****************************/ + +#define XPS_NOR_BASEADDR XPS_PARPORT0_BASEADDR + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + + +void InitNor(void); + +u32 NorAccess( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthBytes); + +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + + +#endif /* ___NOR_H___ */ + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/pcap.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/pcap.c new file mode 100644 index 0000000..40351c8 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/pcap.c @@ -0,0 +1,816 @@ +/***************************************************************************** +* +* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file pcap.c +* +* Contains code for enabling and accessing the PCAP +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	02/10/10	Initial release
+* 2.00a jz	05/28/11	Add SD support
+* 2.00a mb	25/05/12	using the EDK provided devcfg driver
+* 						Nand/SD encryption and review comments
+* 3.00a mb  16/08/12	Added the poll function
+*						Removed the FPGA_RST_CTRL define
+*						Added the flag for NON PS instantiated bitstream
+* 4.00a sgd 02/28/13	Fix for CR#681014 - ECC init in FSBL should not call
+*                                           fabric_init()
+* 						Fix for CR#689026 - FSBL doesn't hold PL resets active
+* 						                    during bit download
+* 						Fix for CR#699475 - FSBL functionality is broken and
+* 						                    its not able to boot in QSPI/NAND
+* 						                    bootmode
+*						Fix for CR#705664 - FSBL fails to decrypt the
+*						                    bitstream when the image is AES
+*						                    encrypted using non-zero key value
+* 6.00a kc  08/30/13    Fix for CR#722979 - Provide customer-friendly
+*                                           changelogs in FSBL
+* 7.00a kc	10/25/13	Fix for CR#724620 - How to handle PCAP_MODE after
+*						                    bitstream configuration
+*						Fix for CR#726178 - FabricInit() PROG_B is kept active
+*						                    for 5mS.
+* 						Fix for CR#731839 - FSBL has to check the
+* 											HMAC error status after decryption
+*			12/04/13	Fix for CR#764382 - How to handle PCAP_MODE after
+*						                    bitstream configuration - PCAP_MODE
+*											and PCAP_PR bits are not modified
+* 8.00a kc  2/20/14		Fix for CR#775631 - FSBL: FsblGetGlobalTimer() 
+*						is not proper
+* 10.00a kc 07/24/14    Fix for CR#809336 - Minor code cleanup
+* 13.00a ssc 04/10/15   Fix for CR#846899 - Corrected logic to clear
+*                                           DMA done count
+* 15.00a gan 07/21/16   Fix for CR# 953654 -(2016.3)FSBL -
+* 											In pcap.c/pcap.h/main.h,
+* 											Fabric Initialization sequence
+* 											is modified to check the PL power
+* 											before sequence starts and checking
+* 											INIT_B reset status twice in case
+* 											of failure.
+* 16.00a gan 08/02/16   Fix for CR# 955897 -(2016.3)FSBL -
+* 											In pcap.c, check pl power
+* 											through MCTRL register for
+* 											3.0 and later versions of silicon.
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "pcap.h" +#include "nand.h" /* For NAND geometry information */ +#include "fsbl.h" +#include "image_mover.h" /* For MoveImage */ +#include "xparameters.h" +#include "xil_exception.h" +#include "xdevcfg.h" +#include "sleep.h" +#include "xtime_l.h" + +#ifdef XPAR_XWDTPS_0_BASEADDR +#include "xwdtps.h" +#endif +/************************** Constant Definitions *****************************/ +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are only defined here such that a user can easily + * change all the needed parameters in one place. + */ + +#define DCFG_DEVICE_ID XPAR_XDCFG_0_DEVICE_ID + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ +extern int XDcfgPollDone(u32 MaskValue, u32 MaxCount); + +/************************** Variable Definitions *****************************/ +/* Devcfg driver instance */ +static XDcfg DcfgInstance; +XDcfg *DcfgInstPtr; +extern u32 Silicon_Version; +#ifdef XPAR_XWDTPS_0_BASEADDR +extern XWdtPs Watchdog; /* Instance of WatchDog Timer */ +#endif + +/******************************************************************************/ +/** +* +* This function transfer data using PCAP +* +* @param SourceDataPtr is a pointer to where the data is read from +* @param DestinationDataPtr is a pointer to where the data is written to +* @param SourceLength is the length of the data to be moved in words +* @param DestinationLength is the length of the data to be moved in words +* @param SecureTransfer indicated the encryption key location, 0 for +* non-encrypted +* +* @return +* - XST_SUCCESS if the transfer is successful +* - XST_FAILURE if the transfer fails +* +* @note None +* +****************************************************************************/ +u32 PcapDataTransfer(u32 *SourceDataPtr, u32 *DestinationDataPtr, + u32 SourceLength, u32 DestinationLength, u32 SecureTransfer) +{ + u32 Status; + u32 IntrStsReg; + u32 PcapTransferType = XDCFG_CONCURRENT_NONSEC_READ_WRITE; + + /* + * Check for secure transfer + */ + if (SecureTransfer) { + PcapTransferType = XDCFG_CONCURRENT_SECURE_READ_WRITE; + } + +#ifdef FSBL_PERF + XTime tXferCur = 0; + FsblGetGlobalTime(&tXferCur); +#endif + + /* + * Clear the PCAP status registers + */ + Status = ClearPcapStatus(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n"); + return XST_FAILURE; + } + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Prevent WDT reset + */ + XWdtPs_RestartWdt(&Watchdog); +#endif + + /* + * PCAP single DMA transfer setup + */ + SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER); + DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER); + + /* + * Transfer using Device Configuration + */ + Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr, + SourceLength, + (u8 *)DestinationDataPtr, + DestinationLength, PcapTransferType); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status); + return XST_FAILURE; + } + + /* + * Dump the PCAP registers + */ + PcapDumpRegisters(); + + /* + * Poll for the DMA done + */ + Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n"); + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r"); + + /* + * Check for errors + */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) { + fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n"); + return XST_FAILURE; + } + + /* + * For Performance measurement + */ +#ifdef FSBL_PERF + XTime tXferEnd = 0; + fsbl_printf(DEBUG_GENERAL,"Time taken is "); + FsblMeasurePerfTime(tXferCur,tXferEnd); +#endif + + return XST_SUCCESS; +} + + +/******************************************************************************/ +/** +* +* This function loads PL partition using PCAP +* +* @param SourceDataPtr is a pointer to where the data is read from +* @param DestinationDataPtr is a pointer to where the data is written to +* @param SourceLength is the length of the data to be moved in words +* @param DestinationLength is the length of the data to be moved in words +* @param SecureTransfer indicated the encryption key location, 0 for +* non-encrypted +* +* @return +* - XST_SUCCESS if the transfer is successful +* - XST_FAILURE if the transfer fails +* +* @note None +* +****************************************************************************/ +u32 PcapLoadPartition(u32 *SourceDataPtr, u32 *DestinationDataPtr, + u32 SourceLength, u32 DestinationLength, u32 SecureTransfer) +{ + u32 Status; + u32 IntrStsReg; + u32 PcapTransferType = XDCFG_NON_SECURE_PCAP_WRITE; + + /* + * Check for secure transfer + */ + if (SecureTransfer) { + PcapTransferType = XDCFG_SECURE_PCAP_WRITE; + } + +#ifdef FSBL_PERF + XTime tXferCur = 0; + FsblGetGlobalTime(&tXferCur); +#endif + + /* + * Clear the PCAP status registers + */ + Status = ClearPcapStatus(); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_CLEAR_STATUS_FAIL \r\n"); + return XST_FAILURE; + } + + /* + * For Bitstream case destination address will be 0xFFFFFFFF + */ + DestinationDataPtr = (u32*)XDCFG_DMA_INVALID_ADDRESS; + + /* + * New Bitstream download initialization sequence + */ + Status = FabricInit(); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + +#ifdef XPAR_XWDTPS_0_BASEADDR + /* + * Prevent WDT reset + */ + XWdtPs_RestartWdt(&Watchdog); +#endif + + /* + * PCAP single DMA transfer setup + */ + SourceDataPtr = (u32*)((u32)SourceDataPtr | PCAP_LAST_TRANSFER); + DestinationDataPtr = (u32*)((u32)DestinationDataPtr | PCAP_LAST_TRANSFER); + + /* + * Transfer using Device Configuration + */ + Status = XDcfg_Transfer(DcfgInstPtr, (u8 *)SourceDataPtr, + SourceLength, + (u8 *)DestinationDataPtr, + DestinationLength, PcapTransferType); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"Status of XDcfg_Transfer = %lu \r \n",Status); + return XST_FAILURE; + } + + + /* + * Dump the PCAP registers + */ + PcapDumpRegisters(); + + + /* + * Poll for the DMA done + */ + Status = XDcfgPollDone(XDCFG_IXR_DMA_DONE_MASK, MAX_COUNT); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_DMA_DONE_FAIL \r\n"); + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO,"DMA Done ! \n\r"); + + /* + * Poll for FPGA Done + */ + Status = XDcfgPollDone(XDCFG_IXR_PCFG_DONE_MASK, MAX_COUNT); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO,"PCAP_FPGA_DONE_FAIL\r\n"); + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO,"FPGA Done ! \n\r"); + + /* + * Check for errors + */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) { + fsbl_printf(DEBUG_INFO,"Errors in PCAP \r\n"); + return XST_FAILURE; + } + + /* + * For Performance measurement + */ +#ifdef FSBL_PERF + XTime tXferEnd = 0; + fsbl_printf(DEBUG_GENERAL,"Time taken is "); + FsblMeasurePerfTime(tXferCur,tXferEnd); +#endif + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** +* +* This function Initializes the PCAP driver. +* +* @param none +* +* @return +* - XST_SUCCESS if the pcap driver initialization is successful +* - XST_FAILURE if the pcap driver initialization fails +* +* @note none +* +****************************************************************************/ +int InitPcap(void) +{ + XDcfg_Config *ConfigPtr; + int Status = XST_SUCCESS; + DcfgInstPtr = &DcfgInstance; + + /* + * Initialize the Device Configuration Interface driver. + */ + ConfigPtr = XDcfg_LookupConfig(DCFG_DEVICE_ID); + + Status = XDcfg_CfgInitialize(DcfgInstPtr, ConfigPtr, + ConfigPtr->BaseAddr); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO, "XDcfg_CfgInitialize failed \n\r"); + return XST_FAILURE; + } + + return XST_SUCCESS; +} +/******************************************************************************/ +/** +* +* This function programs the Fabric for use. +* +* @param None +* +* @return +* - XST_SUCCESS if the Fabric initialization is successful +* - XST_FAILURE if the Fabric initialization fails +* @note None +* +****************************************************************************/ +u32 FabricInit(void) +{ + u32 PcapReg; + u32 PcapCtrlRegVal; + u32 StatusReg; + u32 MctrlReg; + u32 PcfgInit; + u32 TimerExpired=0; + XTime tCur=0; + XTime tEnd=0; + + + /* + * Set Level Shifters DT618760 - PS to PL enabling + */ + Xil_Out32(PS_LVL_SHFTR_EN, LVL_PS_PL); + fsbl_printf(DEBUG_INFO,"Level Shifter Value = 0x%lx \r\n", + Xil_In32(PS_LVL_SHFTR_EN)); + + /* + * Get DEVCFG controller settings + */ + PcapReg = XDcfg_ReadReg(DcfgInstPtr->Config.BaseAddr, + XDCFG_CTRL_OFFSET); + + /* + * Check the PL power status + */ + if(Silicon_Version >= SILICON_VERSION_3) + { + MctrlReg = XDcfg_GetMiscControlRegister(DcfgInstPtr); + + if((MctrlReg & XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) != + XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK) + { + fsbl_printf(DEBUG_INFO,"Fabric not powered up\r\n"); + return XST_FAILURE; + } + } + + + /* + * Setting PCFG_PROG_B signal to high + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Check for AES source key + */ + PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr); + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * 5msec delay + */ + usleep(5000); + } + + /* + * Setting PCFG_PROG_B signal to low + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Check for AES source key + */ + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * 5msec delay + */ + usleep(5000); + } + + /* + * Polling the PCAP_INIT status for Reset or timeout + */ + + XTime_GetTime(&tCur); + do + { + PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) & + XDCFG_STATUS_PCFG_INIT_MASK); + if(PcfgInit == 0) + { + break; + } + XTime_GetTime(&tEnd); + if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd) + { + TimerExpired = 1; + } + + } while(!TimerExpired); + + if(TimerExpired == 1) + { + TimerExpired = 0; + /* + * Came here due to expiration and PCAP_INIT is set. + * Retry PCFG_PROG_B High -> Low again + */ + + /* + * Setting PCFG_PROG_B signal to high + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Check for AES source key + */ + PcapCtrlRegVal = XDcfg_GetControlRegister(DcfgInstPtr); + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * 5msec delay + */ + usleep(5000); + } + + /* + * Setting PCFG_PROG_B signal to low + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg & ~XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Check for AES source key + */ + if (PcapCtrlRegVal & XDCFG_CTRL_PCFG_AES_FUSE_MASK) { + /* + * 5msec delay + */ + usleep(5000); + } + /* + * Polling the PCAP_INIT status for Reset or timeout (second iteration) + */ + + XTime_GetTime(&tCur); + do + { + PcfgInit = (XDcfg_GetStatusRegister(DcfgInstPtr) & + XDCFG_STATUS_PCFG_INIT_MASK); + if(PcfgInit == 0) + { + break; + } + XTime_GetTime(&tEnd); + if((u64)((u64)tCur + (COUNTS_PER_MILLI_SECOND*30)) > (u64)tEnd) + { + TimerExpired = 1; + } + + } while(!TimerExpired); + + if(TimerExpired == 1) + { + /* + * Came here due to PCAP_INIT is not getting reset + * for PCFG_PROG_B signal High -> Low + */ + fsbl_printf(DEBUG_INFO,"Fabric Init failed\r\n"); + return XST_FAILURE; + } + } + + /* + * Setting PCFG_PROG_B signal to high + */ + XDcfg_WriteReg(DcfgInstPtr->Config.BaseAddr, XDCFG_CTRL_OFFSET, + (PcapReg | XDCFG_CTRL_PCFG_PROG_B_MASK)); + + /* + * Polling the PCAP_INIT status for Set + */ + while(!(XDcfg_GetStatusRegister(DcfgInstPtr) & + XDCFG_STATUS_PCFG_INIT_MASK)); + + /* + * Get Device configuration status + */ + StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr); + fsbl_printf(DEBUG_INFO,"Devcfg Status register = 0x%lx \r\n",StatusReg); + + fsbl_printf(DEBUG_INFO,"PCAP:Fabric is Initialized done\r\n"); + + return XST_SUCCESS; +} +/******************************************************************************/ +/** +* +* This function Clears the PCAP status registers. +* +* @param None +* +* @return +* - XST_SUCCESS if the pcap status registers are cleared +* - XST_FAILURE if errors are there +* - XST_DEVICE_BUSY if Pcap device is busy +* @note None +* +****************************************************************************/ +u32 ClearPcapStatus(void) +{ + + u32 StatusReg; + u32 IntStatusReg; + + /* + * Clear it all, so if Boot ROM comes back, it can proceed + */ + XDcfg_IntrClear(DcfgInstPtr, 0xFFFFFFFF); + + /* + * Get PCAP Interrupt Status Register + */ + IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr); + if (IntStatusReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) { + fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n", + IntStatusReg); + return XST_FAILURE; + } + + /* + * Read the PCAP status register for DMA status + */ + StatusReg = XDcfg_GetStatusRegister(DcfgInstPtr); + + fsbl_printf(DEBUG_INFO,"PCAP:StatusReg = 0x%.8lx\r\n", StatusReg); + + /* + * If the queue is full, return w/ XST_DEVICE_BUSY + */ + if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_F_MASK) == + XDCFG_STATUS_DMA_CMD_Q_F_MASK) { + + fsbl_printf(DEBUG_INFO,"PCAP_DEVICE_BUSY\r\n"); + return XST_DEVICE_BUSY; + } + + fsbl_printf(DEBUG_INFO,"PCAP:device ready\r\n"); + + /* + * There are unacknowledged DMA commands outstanding + */ + if ((StatusReg & XDCFG_STATUS_DMA_CMD_Q_E_MASK) != + XDCFG_STATUS_DMA_CMD_Q_E_MASK) { + + IntStatusReg = XDcfg_IntrGetStatus(DcfgInstPtr); + + if ((IntStatusReg & XDCFG_IXR_DMA_DONE_MASK) != + XDCFG_IXR_DMA_DONE_MASK){ + /* + * Error state, transfer cannot occur + */ + fsbl_printf(DEBUG_INFO,"PCAP:IntStatus indicates error\r\n"); + return XST_FAILURE; + } + else { + /* + * clear out the status + */ + XDcfg_IntrClear(DcfgInstPtr, XDCFG_IXR_DMA_DONE_MASK); + } + } + + if ((StatusReg & XDCFG_STATUS_DMA_DONE_CNT_MASK) != 0) { + XDcfg_SetStatusRegister(DcfgInstPtr, StatusReg | + XDCFG_STATUS_DMA_DONE_CNT_MASK); + } + + fsbl_printf(DEBUG_INFO,"PCAP:Clear done\r\n"); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** +* +* This function prints PCAP register status. +* +* @param none +* +* @return none +* +* @note none +* +****************************************************************************/ +void PcapDumpRegisters (void) { + + fsbl_printf(DEBUG_INFO,"PCAP register dump:\r\n"); + + fsbl_printf(DEBUG_INFO,"PCAP CTRL 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CTRL_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP LOCK 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_LOCK_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP CONFIG 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_CFG_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP ISR 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_STS_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP IMR 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_INT_MASK_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP STATUS 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_STATUS_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP DMA SRC ADDR 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_ADDR_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP DMA DEST ADDR 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_ADDR_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP DMA SRC LEN 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_SRC_LEN_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP DMA DEST LEN 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_DMA_DEST_LEN_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP ROM SHADOW CTRL 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_ROM_SHADOW_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP MBOOT 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MULTIBOOT_ADDR_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP SW ID 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_SW_ID_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP UNLOCK 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_UNLOCK_OFFSET)); + fsbl_printf(DEBUG_INFO,"PCAP MCTRL 0x%x: 0x%08lx\r\n", + XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET, + Xil_In32(XPS_DEV_CFG_APB_BASEADDR + XDCFG_MCTRL_OFFSET)); +} + +/******************************************************************************/ +/** +* +* This function Polls for the DMA done or FPGA done. +* +* @param none +* +* @return +* - XST_SUCCESS if polling for DMA/FPGA done is successful +* - XST_FAILURE if polling for DMA/FPGA done fails +* +* @note none +* +****************************************************************************/ +int XDcfgPollDone(u32 MaskValue, u32 MaxCount) +{ + int Count = MaxCount; + u32 IntrStsReg = 0; + + /* + * poll for the DMA done + */ + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + while ((IntrStsReg & MaskValue) != + MaskValue) { + IntrStsReg = XDcfg_IntrGetStatus(DcfgInstPtr); + Count -=1; + + if (IntrStsReg & FSBL_XDCFG_IXR_ERROR_FLAGS_MASK) { + fsbl_printf(DEBUG_INFO,"FATAL errors in PCAP %lx\r\n", + IntrStsReg); + PcapDumpRegisters(); + return XST_FAILURE; + } + + if(!Count) { + fsbl_printf(DEBUG_GENERAL,"PCAP transfer timed out \r\n"); + return XST_FAILURE; + } + if (Count > (MAX_COUNT-100)) { + fsbl_printf(DEBUG_GENERAL,"."); + } + } + + fsbl_printf(DEBUG_GENERAL,"\n\r"); + + XDcfg_IntrClear(DcfgInstPtr, IntrStsReg & MaskValue); + + return XST_SUCCESS; +} diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/pcap.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/pcap.h new file mode 100644 index 0000000..d9400b0 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/pcap.h @@ -0,0 +1,108 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file pcap.h +* +* This file contains the interface for intiializing and accessing the PCAP +* +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	02/10/10 Initial release
+* 2.00a mb  16/08/12 Added the macros and function prototypes
+* 15.00a gan 07/21/16   953654 -(2016.3)FSBL -In pcap.c/pcap.h/main.c,
+* 						Fabric Initialization sequence is modified to check
+* 						the PL power before sequence starts and checking INIT_B
+* 						reset status twice in case of failure.
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___PCAP_H___ +#define ___PCAP_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xdevcfg.h" + +/************************** Function Prototypes ******************************/ + + +/* Multiboot register offset mask */ +#define PCAP_MBOOT_REG_REBOOT_OFFSET_MASK 0x1FFF +#define PCAP_CTRL_PCFG_AES_FUSE_EFUSE_MASK 0x1000 +/*Miscellaneous Control Register mask*/ +#define XDCFG_MCTRL_PCAP_PCFG_POR_B_MASK 0x00000100 +#define COUNTS_PER_MILLI_SECOND (COUNTS_PER_SECOND/1000) + +#define PCAP_LAST_TRANSFER 1 +#define MAX_COUNT 1000000000 +#define LVL_PL_PS 0x0000000F +#define LVL_PS_PL 0x0000000A + +/* Fix for #672779 */ +#define FSBL_XDCFG_IXR_ERROR_FLAGS_MASK (XDCFG_IXR_AXI_WERR_MASK | \ + XDCFG_IXR_AXI_RTO_MASK | \ + XDCFG_IXR_AXI_RERR_MASK | \ + XDCFG_IXR_RX_FIFO_OV_MASK | \ + XDCFG_IXR_DMA_CMD_ERR_MASK |\ + XDCFG_IXR_DMA_Q_OV_MASK | \ + XDCFG_IXR_P2D_LEN_ERR_MASK |\ + XDCFG_IXR_PCFG_HMAC_ERR_MASK) + +int InitPcap(void); +void PcapDumpRegisters(void); +u32 ClearPcapStatus(void); +u32 FabricInit(void); +int XDcfgPollDone(u32 MaskValue, u32 MaxCount); +u32 PcapLoadPartition(u32 *SourceData, u32 *DestinationData, u32 SourceLength, + u32 DestinationLength, u32 Flags); +u32 PcapDataTransfer(u32 *SourceData, u32 *DestinationData, u32 SourceLength, + u32 DestinationLength, u32 Flags); +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + + +#endif /* ___PCAP_H___ */ + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.c new file mode 100644 index 0000000..cd8a445 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.c @@ -0,0 +1,12946 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.c +* +* This file is automatically generated +* +*****************************************************************************/ + +#include "ps7_init.h" + +unsigned long ps7_pll_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_3_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reserved_reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU ,0x00001081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU ,0x27087290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U ,0x00000000U), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00000003U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x0003F000U ,0x0003C000U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x00010000U ,0x00000000U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x00000200U ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU ,0x00040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000703FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x0 + // .. ==> 0XF8000B00[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000071U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCI_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. reserved_INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE_B = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCI_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. reserved_SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. reserved_DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. reserved_DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. reserved_SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. reserved_SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. reserved_GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. reserved_RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. reserved_VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. reserved_REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. reserved_REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000001U ,0x00000001U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reserved_VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reserved_VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reserved_VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reserved_VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[15:14] = 0x00000000U + // .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reserved_INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reserved_TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reserved_TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reserved_TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. reserved_TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reserved_INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: TRACE CURRENT PORT SIZE + // .. FINISH: TRACE CURRENT PORT SIZE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x000003FFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: OUTPUT ENABLE + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: I2C RESET + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_3_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_LVL_INP_EN_0 = 1 + // .. ==> 0XF8000900[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. USER_LVL_OUT_EN_0 = 1 + // .. ==> 0XF8000900[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USER_LVL_INP_EN_1 = 1 + // .. ==> 0XF8000900[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. USER_LVL_OUT_EN_1 = 1 + // .. ==> 0XF8000900[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. reserved_FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. reserved_FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. reserved_FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. reserved_FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. reserved_FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. reserved_FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. reserved_FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. reserved_FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. reserved_FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_3_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_2_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 + // .. .. ==> 0XF8006078[3:0] = 0x00000001U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U + // .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 + // .. .. ==> 0XF8006078[7:4] = 0x00000001U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U + // .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 + // .. .. ==> 0XF8006078[11:8] = 0x00000001U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U + // .. .. reg_ddrc_t_cksre = 0x6 + // .. .. ==> 0XF8006078[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_t_cksrx = 0x6 + // .. .. ==> 0XF8006078[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_t_ckesr = 0x4 + // .. .. ==> 0XF8006078[25:20] = 0x00000004U + // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U + // .. .. + EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU ,0x00466111U), + // .. .. reg_ddrc_t_ckpde = 0x2 + // .. .. ==> 0XF800607C[3:0] = 0x00000002U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U + // .. .. reg_ddrc_t_ckpdx = 0x2 + // .. .. ==> 0XF800607C[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. reg_ddrc_t_ckdpde = 0x2 + // .. .. ==> 0XF800607C[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_ckdpdx = 0x2 + // .. .. ==> 0XF800607C[15:12] = 0x00000002U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U + // .. .. reg_ddrc_t_ckcsx = 0x3 + // .. .. ==> 0XF800607C[19:16] = 0x00000003U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U + // .. .. + EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU ,0x00032222U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_TEST = 0x3 + // .. ==> 0XF8000B6C[11:10] = 0x00000003U + // .. ==> MASK : 0x00000C00U VAL : 0x00000C00U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU ,0x00000E09U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: TRACE CURRENT PORT SIZE + // .. FINISH: TRACE CURRENT PORT SIZE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: OUTPUT ENABLE + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: I2C RESET + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_2_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_2_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_pll_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: PLL SLCR REGISTERS + // .. .. START: ARM PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000110[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000110[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0xfa + // .. .. ==> 0XF8000110[21:12] = 0x000000FAU + // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U + // .. .. + EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x28 + // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. ARM_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000001U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. SRCSEL = 0x0 + // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. .. .. DIVISOR = 0x2 + // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U + // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U + // .. .. .. CPU_6OR4XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U + // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. .. .. CPU_3OR2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U + // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U + // .. .. .. CPU_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U + // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. .. CPU_1XCLKACT = 0x1 + // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U + // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. .. CPU_PERI_CLKACT = 0x1 + // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U + // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), + // .. .. FINISH: ARM PLL INIT + // .. .. START: DDR PLL INIT + // .. .. PLL_RES = 0x2 + // .. .. ==> 0XF8000114[7:4] = 0x00000002U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000114[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x12c + // .. .. ==> 0XF8000114[21:12] = 0x0000012CU + // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U + // .. .. + EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x20 + // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. DDR_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000002U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. .. DDR_3XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. DDR_2XCLKACT = 0x1 + // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U + // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. .. DDR_3XCLK_DIVISOR = 0x2 + // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U + // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U + // .. .. .. DDR_2XCLK_DIVISOR = 0x3 + // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U + // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), + // .. .. FINISH: DDR PLL INIT + // .. .. START: IO PLL INIT + // .. .. PLL_RES = 0xc + // .. .. ==> 0XF8000118[7:4] = 0x0000000CU + // .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U + // .. .. PLL_CP = 0x2 + // .. .. ==> 0XF8000118[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. LOCK_CNT = 0x145 + // .. .. ==> 0XF8000118[21:12] = 0x00000145U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U + // .. .. + EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U), + // .. .. .. START: UPDATE FB_DIV + // .. .. .. PLL_FDIV = 0x1e + // .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU + // .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U), + // .. .. .. FINISH: UPDATE FB_DIV + // .. .. .. START: BY PASS PLL + // .. .. .. PLL_BYPASS_FORCE = 1 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), + // .. .. .. FINISH: BY PASS PLL + // .. .. .. START: ASSERT RESET + // .. .. .. PLL_RESET = 1 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), + // .. .. .. FINISH: ASSERT RESET + // .. .. .. START: DEASSERT RESET + // .. .. .. PLL_RESET = 0 + // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U + // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), + // .. .. .. FINISH: DEASSERT RESET + // .. .. .. START: CHECK PLL STATUS + // .. .. .. IO_PLL_LOCK = 1 + // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U + // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. .. .. + EMIT_MASKPOLL(0XF800010C, 0x00000004U), + // .. .. .. FINISH: CHECK PLL STATUS + // .. .. .. START: REMOVE PLL BY PASS + // .. .. .. PLL_BYPASS_FORCE = 0 + // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U + // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), + // .. .. .. FINISH: REMOVE PLL BY PASS + // .. .. FINISH: IO PLL INIT + // .. FINISH: PLL SLCR REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_clock_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: CLOCK CONTROL SLCR REGISTERS + // .. CLKACT = 0x1 + // .. ==> 0XF8000128[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. DIVISOR0 = 0x23 + // .. ==> 0XF8000128[13:8] = 0x00000023U + // .. ==> MASK : 0x00003F00U VAL : 0x00002300U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF8000128[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00302301U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000138[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000138[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000138, 0x00000011U ,0x00000001U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000140[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000140[6:4] = 0x00000000U + // .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. DIVISOR = 0x8 + // .. ==> 0XF8000140[13:8] = 0x00000008U + // .. ==> MASK : 0x00003F00U VAL : 0x00000800U + // .. DIVISOR1 = 0x5 + // .. ==> 0XF8000140[25:20] = 0x00000005U + // .. ==> MASK : 0x03F00000U VAL : 0x00500000U + // .. + EMIT_MASKWRITE(0XF8000140, 0x03F03F71U ,0x00500801U), + // .. CLKACT = 0x1 + // .. ==> 0XF800014C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF800014C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF800014C[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF8000150[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF8000150[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000150[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000150[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001401U), + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000154[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000154[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000154[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x14 + // .. ==> 0XF8000154[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. + EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), + // .. CLKACT0 = 0x1 + // .. ==> 0XF800015C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. CLKACT1 = 0x0 + // .. ==> 0XF800015C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. SRCSEL = 0x0 + // .. ==> 0XF800015C[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0xe + // .. ==> 0XF800015C[13:8] = 0x0000000EU + // .. ==> MASK : 0x00003F00U VAL : 0x00000E00U + // .. DIVISOR1 = 0x3 + // .. ==> 0XF800015C[25:20] = 0x00000003U + // .. ==> MASK : 0x03F00000U VAL : 0x00300000U + // .. + EMIT_MASKWRITE(0XF800015C, 0x03F03F33U ,0x00300E01U), + // .. CAN0_MUX = 0x0 + // .. ==> 0XF8000160[5:0] = 0x00000000U + // .. ==> MASK : 0x0000003FU VAL : 0x00000000U + // .. CAN0_REF_SEL = 0x0 + // .. ==> 0XF8000160[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. CAN1_MUX = 0x0 + // .. ==> 0XF8000160[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. CAN1_REF_SEL = 0x0 + // .. ==> 0XF8000160[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000160, 0x007F007FU ,0x00000000U), + // .. CLKACT = 0x1 + // .. ==> 0XF8000168[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. SRCSEL = 0x0 + // .. ==> 0XF8000168[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR = 0x5 + // .. ==> 0XF8000168[13:8] = 0x00000005U + // .. ==> MASK : 0x00003F00U VAL : 0x00000500U + // .. + EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000170[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000170[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000170[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000180[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000180[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000180[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF8000190[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF8000190[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF8000190[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00101400U), + // .. SRCSEL = 0x0 + // .. ==> 0XF80001A0[5:4] = 0x00000000U + // .. ==> MASK : 0x00000030U VAL : 0x00000000U + // .. DIVISOR0 = 0x14 + // .. ==> 0XF80001A0[13:8] = 0x00000014U + // .. ==> MASK : 0x00003F00U VAL : 0x00001400U + // .. DIVISOR1 = 0x1 + // .. ==> 0XF80001A0[25:20] = 0x00000001U + // .. ==> MASK : 0x03F00000U VAL : 0x00100000U + // .. + EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00101400U), + // .. CLK_621_TRUE = 0x1 + // .. ==> 0XF80001C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), + // .. DMA_CPU_2XCLKACT = 0x1 + // .. ==> 0XF800012C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. USB0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. USB1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[3:3] = 0x00000001U + // .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. GEM0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[6:6] = 0x00000001U + // .. ==> MASK : 0x00000040U VAL : 0x00000040U + // .. GEM1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. SDI0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[10:10] = 0x00000001U + // .. ==> MASK : 0x00000400U VAL : 0x00000400U + // .. SDI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. SPI0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. SPI1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[15:15] = 0x00000000U + // .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. CAN0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[16:16] = 0x00000001U + // .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. CAN1_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. I2C0_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[18:18] = 0x00000001U + // .. ==> MASK : 0x00040000U VAL : 0x00040000U + // .. I2C1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. UART0_CPU_1XCLKACT = 0x0 + // .. ==> 0XF800012C[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. UART1_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[21:21] = 0x00000001U + // .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. GPIO_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[22:22] = 0x00000001U + // .. ==> MASK : 0x00400000U VAL : 0x00400000U + // .. LQSPI_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[23:23] = 0x00000001U + // .. ==> MASK : 0x00800000U VAL : 0x00800000U + // .. SMC_CPU_1XCLKACT = 0x1 + // .. ==> 0XF800012C[24:24] = 0x00000001U + // .. ==> MASK : 0x01000000U VAL : 0x01000000U + // .. + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01ED044DU), + // .. FINISH: CLOCK CONTROL SLCR REGISTERS + // .. START: THIS SHOULD BE BLANK + // .. FINISH: THIS SHOULD BE BLANK + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_ddr_init_data_1_0[] = { + // START: top + // .. START: DDR INITIALIZATION + // .. .. START: LOCK DDR + // .. .. reg_ddrc_soft_rstb = 0 + // .. .. ==> 0XF8006000[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 0x1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000080U), + // .. .. FINISH: LOCK DDR + // .. .. reg_ddrc_t_rfc_nom_x32 = 0x81 + // .. .. ==> 0XF8006004[11:0] = 0x00000081U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000081U + // .. .. reg_ddrc_active_ranks = 0x1 + // .. .. ==> 0XF8006004[13:12] = 0x00000001U + // .. .. ==> MASK : 0x00003000U VAL : 0x00001000U + // .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 + // .. .. ==> 0XF8006004[18:14] = 0x00000000U + // .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_block = 0x1 + // .. .. ==> 0XF8006004[20:19] = 0x00000001U + // .. .. ==> MASK : 0x00180000U VAL : 0x00080000U + // .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 + // .. .. ==> 0XF8006004[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 + // .. .. ==> 0XF8006004[26:22] = 0x00000000U + // .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_open_bank = 0x0 + // .. .. ==> 0XF8006004[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_4bank_ram = 0x0 + // .. .. ==> 0XF8006004[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU ,0x00081081U), + // .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf + // .. .. ==> 0XF8006008[10:0] = 0x0000000FU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU + // .. .. reg_ddrc_hpr_max_starve_x32 = 0xf + // .. .. ==> 0XF8006008[21:11] = 0x0000000FU + // .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U + // .. .. reg_ddrc_hpr_xact_run_length = 0xf + // .. .. ==> 0XF8006008[25:22] = 0x0000000FU + // .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U + // .. .. + EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU ,0x03C0780FU), + // .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF800600C[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 + // .. .. ==> 0XF800600C[21:11] = 0x00000002U + // .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U + // .. .. reg_ddrc_lpr_xact_run_length = 0x8 + // .. .. ==> 0XF800600C[25:22] = 0x00000008U + // .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U + // .. .. + EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU ,0x02001001U), + // .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 + // .. .. ==> 0XF8006010[10:0] = 0x00000001U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U + // .. .. reg_ddrc_w_xact_run_length = 0x8 + // .. .. ==> 0XF8006010[14:11] = 0x00000008U + // .. .. ==> MASK : 0x00007800U VAL : 0x00004000U + // .. .. reg_ddrc_w_max_starve_x32 = 0x2 + // .. .. ==> 0XF8006010[25:15] = 0x00000002U + // .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U + // .. .. + EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU ,0x00014001U), + // .. .. reg_ddrc_t_rc = 0x1b + // .. .. ==> 0XF8006014[5:0] = 0x0000001BU + // .. .. ==> MASK : 0x0000003FU VAL : 0x0000001BU + // .. .. reg_ddrc_t_rfc_min = 0x56 + // .. .. ==> 0XF8006014[13:6] = 0x00000056U + // .. .. ==> MASK : 0x00003FC0U VAL : 0x00001580U + // .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 + // .. .. ==> 0XF8006014[20:14] = 0x00000010U + // .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU ,0x0004159BU), + // .. .. reg_ddrc_wr2pre = 0x12 + // .. .. ==> 0XF8006018[4:0] = 0x00000012U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U + // .. .. reg_ddrc_powerdown_to_x32 = 0x6 + // .. .. ==> 0XF8006018[9:5] = 0x00000006U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U + // .. .. reg_ddrc_t_faw = 0x10 + // .. .. ==> 0XF8006018[15:10] = 0x00000010U + // .. .. ==> MASK : 0x0000FC00U VAL : 0x00004000U + // .. .. reg_ddrc_t_ras_max = 0x24 + // .. .. ==> 0XF8006018[21:16] = 0x00000024U + // .. .. ==> MASK : 0x003F0000U VAL : 0x00240000U + // .. .. reg_ddrc_t_ras_min = 0x14 + // .. .. ==> 0XF8006018[26:22] = 0x00000014U + // .. .. ==> MASK : 0x07C00000U VAL : 0x05000000U + // .. .. reg_ddrc_t_cke = 0x4 + // .. .. ==> 0XF8006018[31:28] = 0x00000004U + // .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU ,0x452440D2U), + // .. .. reg_ddrc_write_latency = 0x5 + // .. .. ==> 0XF800601C[4:0] = 0x00000005U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U + // .. .. reg_ddrc_rd2wr = 0x7 + // .. .. ==> 0XF800601C[9:5] = 0x00000007U + // .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U + // .. .. reg_ddrc_wr2rd = 0xe + // .. .. ==> 0XF800601C[14:10] = 0x0000000EU + // .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U + // .. .. reg_ddrc_t_xp = 0x4 + // .. .. ==> 0XF800601C[19:15] = 0x00000004U + // .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U + // .. .. reg_ddrc_pad_pd = 0x0 + // .. .. ==> 0XF800601C[22:20] = 0x00000000U + // .. .. ==> MASK : 0x00700000U VAL : 0x00000000U + // .. .. reg_ddrc_rd2pre = 0x4 + // .. .. ==> 0XF800601C[27:23] = 0x00000004U + // .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U + // .. .. reg_ddrc_t_rcd = 0x7 + // .. .. ==> 0XF800601C[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU ,0x720238E5U), + // .. .. reg_ddrc_t_ccd = 0x4 + // .. .. ==> 0XF8006020[4:2] = 0x00000004U + // .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U + // .. .. reg_ddrc_t_rrd = 0x4 + // .. .. ==> 0XF8006020[7:5] = 0x00000004U + // .. .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. .. reg_ddrc_refresh_margin = 0x2 + // .. .. ==> 0XF8006020[11:8] = 0x00000002U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U + // .. .. reg_ddrc_t_rp = 0x7 + // .. .. ==> 0XF8006020[15:12] = 0x00000007U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U + // .. .. reg_ddrc_refresh_to_x32 = 0x8 + // .. .. ==> 0XF8006020[20:16] = 0x00000008U + // .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U + // .. .. reg_ddrc_sdram = 0x1 + // .. .. ==> 0XF8006020[21:21] = 0x00000001U + // .. .. ==> MASK : 0x00200000U VAL : 0x00200000U + // .. .. reg_ddrc_mobile = 0x0 + // .. .. ==> 0XF8006020[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. reg_ddrc_clock_stop_en = 0x0 + // .. .. ==> 0XF8006020[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. reg_ddrc_read_latency = 0x7 + // .. .. ==> 0XF8006020[28:24] = 0x00000007U + // .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U + // .. .. reg_phy_mode_ddr1_ddr2 = 0x1 + // .. .. ==> 0XF8006020[29:29] = 0x00000001U + // .. .. ==> MASK : 0x20000000U VAL : 0x20000000U + // .. .. reg_ddrc_dis_pad_pd = 0x0 + // .. .. ==> 0XF8006020[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_ddrc_loopback = 0x0 + // .. .. ==> 0XF8006020[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU ,0x27287290U), + // .. .. reg_ddrc_en_2t_timing_mode = 0x0 + // .. .. ==> 0XF8006024[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_prefer_write = 0x0 + // .. .. ==> 0XF8006024[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_max_rank_rd = 0xf + // .. .. ==> 0XF8006024[5:2] = 0x0000000FU + // .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU + // .. .. reg_ddrc_mr_wr = 0x0 + // .. .. ==> 0XF8006024[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_ddrc_mr_addr = 0x0 + // .. .. ==> 0XF8006024[8:7] = 0x00000000U + // .. .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. .. reg_ddrc_mr_data = 0x0 + // .. .. ==> 0XF8006024[24:9] = 0x00000000U + // .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U + // .. .. ddrc_reg_mr_wr_busy = 0x0 + // .. .. ==> 0XF8006024[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_type = 0x0 + // .. .. ==> 0XF8006024[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. reg_ddrc_mr_rdata_valid = 0x0 + // .. .. ==> 0XF8006024[27:27] = 0x00000000U + // .. .. ==> MASK : 0x08000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU ,0x0000003CU), + // .. .. reg_ddrc_final_wait_x32 = 0x7 + // .. .. ==> 0XF8006028[6:0] = 0x00000007U + // .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U + // .. .. reg_ddrc_pre_ocd_x32 = 0x0 + // .. .. ==> 0XF8006028[10:7] = 0x00000000U + // .. .. ==> MASK : 0x00000780U VAL : 0x00000000U + // .. .. reg_ddrc_t_mrd = 0x4 + // .. .. ==> 0XF8006028[13:11] = 0x00000004U + // .. .. ==> MASK : 0x00003800U VAL : 0x00002000U + // .. .. + EMIT_MASKWRITE(0XF8006028, 0x00003FFFU ,0x00002007U), + // .. .. reg_ddrc_emr2 = 0x8 + // .. .. ==> 0XF800602C[15:0] = 0x00000008U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U + // .. .. reg_ddrc_emr3 = 0x0 + // .. .. ==> 0XF800602C[31:16] = 0x00000000U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU ,0x00000008U), + // .. .. reg_ddrc_mr = 0x930 + // .. .. ==> 0XF8006030[15:0] = 0x00000930U + // .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U + // .. .. reg_ddrc_emr = 0x4 + // .. .. ==> 0XF8006030[31:16] = 0x00000004U + // .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U + // .. .. + EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU ,0x00040930U), + // .. .. reg_ddrc_burst_rdwr = 0x4 + // .. .. ==> 0XF8006034[3:0] = 0x00000004U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U + // .. .. reg_ddrc_pre_cke_x1024 = 0x105 + // .. .. ==> 0XF8006034[13:4] = 0x00000105U + // .. .. ==> MASK : 0x00003FF0U VAL : 0x00001050U + // .. .. reg_ddrc_post_cke_x1024 = 0x1 + // .. .. ==> 0XF8006034[25:16] = 0x00000001U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U + // .. .. reg_ddrc_burstchop = 0x0 + // .. .. ==> 0XF8006034[28:28] = 0x00000000U + // .. .. ==> MASK : 0x10000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU ,0x00011054U), + // .. .. reg_ddrc_force_low_pri_n = 0x0 + // .. .. ==> 0XF8006038[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_dis_dq = 0x0 + // .. .. ==> 0XF8006038[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_debug_mode = 0x0 + // .. .. ==> 0XF8006038[6:6] = 0x00000000U + // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. .. reg_phy_wr_level_start = 0x0 + // .. .. ==> 0XF8006038[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_phy_rd_level_start = 0x0 + // .. .. ==> 0XF8006038[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_dq0_wait_t = 0x0 + // .. .. ==> 0XF8006038[12:9] = 0x00000000U + // .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006038, 0x00001FC3U ,0x00000000U), + // .. .. reg_ddrc_addrmap_bank_b0 = 0x7 + // .. .. ==> 0XF800603C[3:0] = 0x00000007U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U + // .. .. reg_ddrc_addrmap_bank_b1 = 0x7 + // .. .. ==> 0XF800603C[7:4] = 0x00000007U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U + // .. .. reg_ddrc_addrmap_bank_b2 = 0x7 + // .. .. ==> 0XF800603C[11:8] = 0x00000007U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U + // .. .. reg_ddrc_addrmap_col_b5 = 0x0 + // .. .. ==> 0XF800603C[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b6 = 0x0 + // .. .. ==> 0XF800603C[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU ,0x00000777U), + // .. .. reg_ddrc_addrmap_col_b2 = 0x0 + // .. .. ==> 0XF8006040[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b3 = 0x0 + // .. .. ==> 0XF8006040[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b4 = 0x0 + // .. .. ==> 0XF8006040[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b7 = 0x0 + // .. .. ==> 0XF8006040[15:12] = 0x00000000U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b8 = 0x0 + // .. .. ==> 0XF8006040[19:16] = 0x00000000U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U + // .. .. reg_ddrc_addrmap_col_b9 = 0xf + // .. .. ==> 0XF8006040[23:20] = 0x0000000FU + // .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U + // .. .. reg_ddrc_addrmap_col_b10 = 0xf + // .. .. ==> 0XF8006040[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. reg_ddrc_addrmap_col_b11 = 0xf + // .. .. ==> 0XF8006040[31:28] = 0x0000000FU + // .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U + // .. .. + EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU ,0xFFF00000U), + // .. .. reg_ddrc_addrmap_row_b0 = 0x6 + // .. .. ==> 0XF8006044[3:0] = 0x00000006U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U + // .. .. reg_ddrc_addrmap_row_b1 = 0x6 + // .. .. ==> 0XF8006044[7:4] = 0x00000006U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U + // .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 + // .. .. ==> 0XF8006044[11:8] = 0x00000006U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U + // .. .. reg_ddrc_addrmap_row_b12 = 0x6 + // .. .. ==> 0XF8006044[15:12] = 0x00000006U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U + // .. .. reg_ddrc_addrmap_row_b13 = 0x6 + // .. .. ==> 0XF8006044[19:16] = 0x00000006U + // .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U + // .. .. reg_ddrc_addrmap_row_b14 = 0x6 + // .. .. ==> 0XF8006044[23:20] = 0x00000006U + // .. .. ==> MASK : 0x00F00000U VAL : 0x00600000U + // .. .. reg_ddrc_addrmap_row_b15 = 0xf + // .. .. ==> 0XF8006044[27:24] = 0x0000000FU + // .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U + // .. .. + EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU ,0x0F666666U), + // .. .. reg_ddrc_rank0_rd_odt = 0x0 + // .. .. ==> 0XF8006048[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_rank0_wr_odt = 0x1 + // .. .. ==> 0XF8006048[5:3] = 0x00000001U + // .. .. ==> MASK : 0x00000038U VAL : 0x00000008U + // .. .. reg_ddrc_rank1_rd_odt = 0x1 + // .. .. ==> 0XF8006048[8:6] = 0x00000001U + // .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U + // .. .. reg_ddrc_rank1_wr_odt = 0x1 + // .. .. ==> 0XF8006048[11:9] = 0x00000001U + // .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. .. reg_phy_rd_local_odt = 0x0 + // .. .. ==> 0XF8006048[13:12] = 0x00000000U + // .. .. ==> MASK : 0x00003000U VAL : 0x00000000U + // .. .. reg_phy_wr_local_odt = 0x3 + // .. .. ==> 0XF8006048[15:14] = 0x00000003U + // .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U + // .. .. reg_phy_idle_local_odt = 0x3 + // .. .. ==> 0XF8006048[17:16] = 0x00000003U + // .. .. ==> MASK : 0x00030000U VAL : 0x00030000U + // .. .. reg_ddrc_rank2_rd_odt = 0x0 + // .. .. ==> 0XF8006048[20:18] = 0x00000000U + // .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U + // .. .. reg_ddrc_rank2_wr_odt = 0x0 + // .. .. ==> 0XF8006048[23:21] = 0x00000000U + // .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_rd_odt = 0x0 + // .. .. ==> 0XF8006048[26:24] = 0x00000000U + // .. .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. .. reg_ddrc_rank3_wr_odt = 0x0 + // .. .. ==> 0XF8006048[29:27] = 0x00000000U + // .. .. ==> MASK : 0x38000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU ,0x0003C248U), + // .. .. reg_phy_rd_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_wr_cmd_to_data = 0x0 + // .. .. ==> 0XF8006050[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_phy_rdc_we_to_re_delay = 0x8 + // .. .. ==> 0XF8006050[11:8] = 0x00000008U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U + // .. .. reg_phy_rdc_fifo_rst_disable = 0x0 + // .. .. ==> 0XF8006050[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_phy_use_fixed_re = 0x1 + // .. .. ==> 0XF8006050[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 + // .. .. ==> 0XF8006050[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 + // .. .. ==> 0XF8006050[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_phy_clk_stall_level = 0x0 + // .. .. ==> 0XF8006050[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[27:24] = 0x00000007U + // .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U + // .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 + // .. .. ==> 0XF8006050[31:28] = 0x00000007U + // .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U + // .. .. + EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU ,0x77010800U), + // .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 + // .. .. ==> 0XF8006058[7:0] = 0x00000001U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U + // .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 + // .. .. ==> 0XF8006058[15:8] = 0x00000001U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U + // .. .. reg_ddrc_dis_dll_calib = 0x0 + // .. .. ==> 0XF8006058[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU ,0x00000101U), + // .. .. reg_ddrc_rd_odt_delay = 0x3 + // .. .. ==> 0XF800605C[3:0] = 0x00000003U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U + // .. .. reg_ddrc_wr_odt_delay = 0x0 + // .. .. ==> 0XF800605C[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. reg_ddrc_rd_odt_hold = 0x0 + // .. .. ==> 0XF800605C[11:8] = 0x00000000U + // .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U + // .. .. reg_ddrc_wr_odt_hold = 0x5 + // .. .. ==> 0XF800605C[15:12] = 0x00000005U + // .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU ,0x00005003U), + // .. .. reg_ddrc_pageclose = 0x0 + // .. .. ==> 0XF8006060[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_lpr_num_entries = 0x1f + // .. .. ==> 0XF8006060[6:1] = 0x0000001FU + // .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU + // .. .. reg_ddrc_auto_pre_en = 0x0 + // .. .. ==> 0XF8006060[7:7] = 0x00000000U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. .. reg_ddrc_refresh_update_level = 0x0 + // .. .. ==> 0XF8006060[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_ddrc_dis_wc = 0x0 + // .. .. ==> 0XF8006060[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_ddrc_dis_collision_page_opt = 0x0 + // .. .. ==> 0XF8006060[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_ddrc_selfref_en = 0x0 + // .. .. ==> 0XF8006060[12:12] = 0x00000000U + // .. .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006060, 0x000017FFU ,0x0000003EU), + // .. .. reg_ddrc_go2critical_hysteresis = 0x0 + // .. .. ==> 0XF8006064[12:5] = 0x00000000U + // .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U + // .. .. reg_arb_go2critical_en = 0x1 + // .. .. ==> 0XF8006064[17:17] = 0x00000001U + // .. .. ==> MASK : 0x00020000U VAL : 0x00020000U + // .. .. + EMIT_MASKWRITE(0XF8006064, 0x00021FE0U ,0x00020000U), + // .. .. reg_ddrc_wrlvl_ww = 0x41 + // .. .. ==> 0XF8006068[7:0] = 0x00000041U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U + // .. .. reg_ddrc_rdlvl_rr = 0x41 + // .. .. ==> 0XF8006068[15:8] = 0x00000041U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U + // .. .. reg_ddrc_dfi_t_wlmrd = 0x28 + // .. .. ==> 0XF8006068[25:16] = 0x00000028U + // .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U + // .. .. + EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU ,0x00284141U), + // .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 + // .. .. ==> 0XF800606C[7:0] = 0x00000010U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U + // .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 + // .. .. ==> 0XF800606C[15:8] = 0x00000016U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U + // .. .. + EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU ,0x00001610U), + // .. .. refresh_timer0_start_value_x32 = 0x0 + // .. .. ==> 0XF80060A0[11:0] = 0x00000000U + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U + // .. .. refresh_timer1_start_value_x32 = 0x8 + // .. .. ==> 0XF80060A0[23:12] = 0x00000008U + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U + // .. .. + EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU ,0x00008000U), + // .. .. reg_ddrc_dis_auto_zq = 0x0 + // .. .. ==> 0XF80060A4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_ddr3 = 0x1 + // .. .. ==> 0XF80060A4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. reg_ddrc_t_mod = 0x200 + // .. .. ==> 0XF80060A4[11:2] = 0x00000200U + // .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U + // .. .. reg_ddrc_t_zq_long_nop = 0x200 + // .. .. ==> 0XF80060A4[21:12] = 0x00000200U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U + // .. .. reg_ddrc_t_zq_short_nop = 0x40 + // .. .. ==> 0XF80060A4[31:22] = 0x00000040U + // .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU ,0x10200802U), + // .. .. t_zq_short_interval_x1024 = 0xcb73 + // .. .. ==> 0XF80060A8[19:0] = 0x0000CB73U + // .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000CB73U + // .. .. dram_rstn_x1024 = 0x69 + // .. .. ==> 0XF80060A8[27:20] = 0x00000069U + // .. .. ==> MASK : 0x0FF00000U VAL : 0x06900000U + // .. .. + EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU ,0x0690CB73U), + // .. .. deeppowerdown_en = 0x0 + // .. .. ==> 0XF80060AC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. deeppowerdown_to_x1024 = 0xff + // .. .. ==> 0XF80060AC[8:1] = 0x000000FFU + // .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU + // .. .. + EMIT_MASKWRITE(0XF80060AC, 0x000001FFU ,0x000001FEU), + // .. .. dfi_wrlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU + // .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU + // .. .. dfi_rdlvl_max_x1024 = 0xfff + // .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU + // .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U + // .. .. ddrc_reg_twrlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. ddrc_reg_trdlvl_max_error = 0x0 + // .. .. ==> 0XF80060B0[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. reg_ddrc_dfi_wr_level_en = 0x1 + // .. .. ==> 0XF80060B0[26:26] = 0x00000001U + // .. .. ==> MASK : 0x04000000U VAL : 0x04000000U + // .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF80060B0[27:27] = 0x00000001U + // .. .. ==> MASK : 0x08000000U VAL : 0x08000000U + // .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 + // .. .. ==> 0XF80060B0[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. + EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU ,0x1CFFFFFFU), + // .. .. reg_ddrc_2t_delay = 0x0 + // .. .. ==> 0XF80060B4[8:0] = 0x00000000U + // .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U + // .. .. reg_ddrc_skip_ocd = 0x1 + // .. .. ==> 0XF80060B4[9:9] = 0x00000001U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. .. reg_ddrc_dis_pre_bypass = 0x0 + // .. .. ==> 0XF80060B4[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060B4, 0x000007FFU ,0x00000200U), + // .. .. reg_ddrc_dfi_t_rddata_en = 0x6 + // .. .. ==> 0XF80060B8[4:0] = 0x00000006U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U + // .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 + // .. .. ==> 0XF80060B8[14:5] = 0x00000003U + // .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U + // .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 + // .. .. ==> 0XF80060B8[24:15] = 0x00000040U + // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U + // .. .. + EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), + // .. .. START: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. Clear_Correctable_DRAM_ECC_error = 1 + // .. .. ==> 0XF80060C4[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), + // .. .. FINISH: RESET ECC ERROR + // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. Clear_Correctable_DRAM_ECC_error = 0x0 + // .. .. ==> 0XF80060C4[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000000U), + // .. .. CORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060C8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. ECC_CORRECTED_BIT_NUM = 0x0 + // .. .. ==> 0XF80060C8[7:1] = 0x00000000U + // .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060C8, 0x000000FFU ,0x00000000U), + // .. .. UNCORR_ECC_LOG_VALID = 0x0 + // .. .. ==> 0XF80060DC[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060DC, 0x00000001U ,0x00000000U), + // .. .. STAT_NUM_CORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[15:8] = 0x00000000U + // .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U + // .. .. STAT_NUM_UNCORR_ERR = 0x0 + // .. .. ==> 0XF80060F0[7:0] = 0x00000000U + // .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU ,0x00000000U), + // .. .. reg_ddrc_ecc_mode = 0x0 + // .. .. ==> 0XF80060F4[2:0] = 0x00000000U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000000U + // .. .. reg_ddrc_dis_scrub = 0x1 + // .. .. ==> 0XF80060F4[3:3] = 0x00000001U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U + // .. .. + EMIT_MASKWRITE(0XF80060F4, 0x0000000FU ,0x00000008U), + // .. .. reg_phy_dif_on = 0x0 + // .. .. ==> 0XF8006114[3:0] = 0x00000000U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U + // .. .. reg_phy_dif_off = 0x0 + // .. .. ==> 0XF8006114[7:4] = 0x00000000U + // .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006114, 0x000000FFU ,0x00000000U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006118[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006118[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006118[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006118[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006118[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006118[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006118[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF800611C[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF800611C[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF800611C[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF800611C[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF800611C[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF800611C[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF800611C[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006120[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006120[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006120[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006120[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006120[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006120[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006120[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_data_slice_in_use = 0x1 + // .. .. ==> 0XF8006124[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_phy_rdlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_gatelvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_wrlvl_inc_mode = 0x0 + // .. .. ==> 0XF8006124[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_tx = 0x0 + // .. .. ==> 0XF8006124[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_board_lpbk_rx = 0x0 + // .. .. ==> 0XF8006124[5:5] = 0x00000000U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. .. reg_phy_bist_shift_dq = 0x0 + // .. .. ==> 0XF8006124[14:6] = 0x00000000U + // .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U + // .. .. reg_phy_bist_err_clr = 0x0 + // .. .. ==> 0XF8006124[23:15] = 0x00000000U + // .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U + // .. .. reg_phy_dq_offset = 0x40 + // .. .. ==> 0XF8006124[30:24] = 0x00000040U + // .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U + // .. .. + EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU ,0x40000001U), + // .. .. reg_phy_wrlvl_init_ratio = 0x1d + // .. .. ==> 0XF800612C[9:0] = 0x0000001DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000001DU + // .. .. reg_phy_gatelvl_init_ratio = 0xf2 + // .. .. ==> 0XF800612C[19:10] = 0x000000F2U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003C800U + // .. .. + EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU ,0x0003C81DU), + // .. .. reg_phy_wrlvl_init_ratio = 0x12 + // .. .. ==> 0XF8006130[9:0] = 0x00000012U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000012U + // .. .. reg_phy_gatelvl_init_ratio = 0xd8 + // .. .. ==> 0XF8006130[19:10] = 0x000000D8U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00036000U + // .. .. + EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU ,0x00036012U), + // .. .. reg_phy_wrlvl_init_ratio = 0xc + // .. .. ==> 0XF8006134[9:0] = 0x0000000CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000000CU + // .. .. reg_phy_gatelvl_init_ratio = 0xde + // .. .. ==> 0XF8006134[19:10] = 0x000000DEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00037800U + // .. .. + EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU ,0x0003780CU), + // .. .. reg_phy_wrlvl_init_ratio = 0x21 + // .. .. ==> 0XF8006138[9:0] = 0x00000021U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000021U + // .. .. reg_phy_gatelvl_init_ratio = 0xee + // .. .. ==> 0XF8006138[19:10] = 0x000000EEU + // .. .. ==> MASK : 0x000FFC00U VAL : 0x0003B800U + // .. .. + EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU ,0x0003B821U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006140[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006140[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006140[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006144[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006144[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006144[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF8006148[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006148[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006148[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_rd_dqs_slave_ratio = 0x35 + // .. .. ==> 0XF800614C[9:0] = 0x00000035U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U + // .. .. reg_phy_rd_dqs_slave_force = 0x0 + // .. .. ==> 0XF800614C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_rd_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800614C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU ,0x00000035U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x9d + // .. .. ==> 0XF8006154[9:0] = 0x0000009DU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000009DU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006154[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006154[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU ,0x0000009DU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x92 + // .. .. ==> 0XF8006158[9:0] = 0x00000092U + // .. .. ==> MASK : 0x000003FFU VAL : 0x00000092U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006158[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006158[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU ,0x00000092U), + // .. .. reg_phy_wr_dqs_slave_ratio = 0x8c + // .. .. ==> 0XF800615C[9:0] = 0x0000008CU + // .. .. ==> MASK : 0x000003FFU VAL : 0x0000008CU + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF800615C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF800615C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU ,0x0000008CU), + // .. .. reg_phy_wr_dqs_slave_ratio = 0xa1 + // .. .. ==> 0XF8006160[9:0] = 0x000000A1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000A1U + // .. .. reg_phy_wr_dqs_slave_force = 0x0 + // .. .. ==> 0XF8006160[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_dqs_slave_delay = 0x0 + // .. .. ==> 0XF8006160[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU ,0x000000A1U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x147 + // .. .. ==> 0XF8006168[10:0] = 0x00000147U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000147U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006168[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006168[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU ,0x00000147U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x12d + // .. .. ==> 0XF800616C[10:0] = 0x0000012DU + // .. .. ==> MASK : 0x000007FFU VAL : 0x0000012DU + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF800616C[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF800616C[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU ,0x0000012DU), + // .. .. reg_phy_fifo_we_slave_ratio = 0x133 + // .. .. ==> 0XF8006170[10:0] = 0x00000133U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000133U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006170[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006170[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU ,0x00000133U), + // .. .. reg_phy_fifo_we_slave_ratio = 0x143 + // .. .. ==> 0XF8006174[10:0] = 0x00000143U + // .. .. ==> MASK : 0x000007FFU VAL : 0x00000143U + // .. .. reg_phy_fifo_we_in_force = 0x0 + // .. .. ==> 0XF8006174[11:11] = 0x00000000U + // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. .. reg_phy_fifo_we_in_delay = 0x0 + // .. .. ==> 0XF8006174[20:12] = 0x00000000U + // .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU ,0x00000143U), + // .. .. reg_phy_wr_data_slave_ratio = 0xdd + // .. .. ==> 0XF800617C[9:0] = 0x000000DDU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000DDU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF800617C[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF800617C[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU ,0x000000DDU), + // .. .. reg_phy_wr_data_slave_ratio = 0xd2 + // .. .. ==> 0XF8006180[9:0] = 0x000000D2U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000D2U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006180[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006180[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU ,0x000000D2U), + // .. .. reg_phy_wr_data_slave_ratio = 0xcc + // .. .. ==> 0XF8006184[9:0] = 0x000000CCU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000CCU + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006184[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006184[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU ,0x000000CCU), + // .. .. reg_phy_wr_data_slave_ratio = 0xe1 + // .. .. ==> 0XF8006188[9:0] = 0x000000E1U + // .. .. ==> MASK : 0x000003FFU VAL : 0x000000E1U + // .. .. reg_phy_wr_data_slave_force = 0x0 + // .. .. ==> 0XF8006188[10:10] = 0x00000000U + // .. .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. .. reg_phy_wr_data_slave_delay = 0x0 + // .. .. ==> 0XF8006188[19:11] = 0x00000000U + // .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU ,0x000000E1U), + // .. .. reg_phy_loopback = 0x0 + // .. .. ==> 0XF8006190[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_phy_bl2 = 0x0 + // .. .. ==> 0XF8006190[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_phy_at_spd_atpg = 0x0 + // .. .. ==> 0XF8006190[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_phy_bist_enable = 0x0 + // .. .. ==> 0XF8006190[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. reg_phy_bist_force_err = 0x0 + // .. .. ==> 0XF8006190[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. reg_phy_bist_mode = 0x0 + // .. .. ==> 0XF8006190[6:5] = 0x00000000U + // .. .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. .. reg_phy_invert_clkout = 0x1 + // .. .. ==> 0XF8006190[7:7] = 0x00000001U + // .. .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 + // .. .. ==> 0XF8006190[8:8] = 0x00000000U + // .. .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. .. reg_phy_sel_logic = 0x0 + // .. .. ==> 0XF8006190[9:9] = 0x00000000U + // .. .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_ratio = 0x100 + // .. .. ==> 0XF8006190[19:10] = 0x00000100U + // .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U + // .. .. reg_phy_ctrl_slave_force = 0x0 + // .. .. ==> 0XF8006190[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006190[27:21] = 0x00000000U + // .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U + // .. .. reg_phy_use_rank0_delays = 0x1 + // .. .. ==> 0XF8006190[28:28] = 0x00000001U + // .. .. ==> MASK : 0x10000000U VAL : 0x10000000U + // .. .. reg_phy_lpddr = 0x0 + // .. .. ==> 0XF8006190[29:29] = 0x00000000U + // .. .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. .. reg_phy_cmd_latency = 0x0 + // .. .. ==> 0XF8006190[30:30] = 0x00000000U + // .. .. ==> MASK : 0x40000000U VAL : 0x00000000U + // .. .. reg_phy_int_lpbk = 0x0 + // .. .. ==> 0XF8006190[31:31] = 0x00000000U + // .. .. ==> MASK : 0x80000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU ,0x10040080U), + // .. .. reg_phy_wr_rl_delay = 0x2 + // .. .. ==> 0XF8006194[4:0] = 0x00000002U + // .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U + // .. .. reg_phy_rd_rl_delay = 0x4 + // .. .. ==> 0XF8006194[9:5] = 0x00000004U + // .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U + // .. .. reg_phy_dll_lock_diff = 0xf + // .. .. ==> 0XF8006194[13:10] = 0x0000000FU + // .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U + // .. .. reg_phy_use_wr_level = 0x1 + // .. .. ==> 0XF8006194[14:14] = 0x00000001U + // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U + // .. .. reg_phy_use_rd_dqs_gate_level = 0x1 + // .. .. ==> 0XF8006194[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U + // .. .. reg_phy_use_rd_data_eye_level = 0x1 + // .. .. ==> 0XF8006194[16:16] = 0x00000001U + // .. .. ==> MASK : 0x00010000U VAL : 0x00010000U + // .. .. reg_phy_dis_calib_rst = 0x0 + // .. .. ==> 0XF8006194[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_phy_ctrl_slave_delay = 0x0 + // .. .. ==> 0XF8006194[19:18] = 0x00000000U + // .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU ,0x0001FC82U), + // .. .. reg_arb_page_addr_mask = 0x0 + // .. .. ==> 0XF8006204[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006208[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006208[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006208[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006208[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006208[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006208, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF800620C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF800620C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF800620C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF800620C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF800620C[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF800620C, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006210[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006210[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006210[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006210[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006210[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006210, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_wr_portn = 0x3ff + // .. .. ==> 0XF8006214[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_wr_portn = 0x0 + // .. .. ==> 0XF8006214[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_wr_portn = 0x0 + // .. .. ==> 0XF8006214[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_wr_portn = 0x0 + // .. .. ==> 0XF8006214[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_dis_rmw_portn = 0x1 + // .. .. ==> 0XF8006214[19:19] = 0x00000001U + // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. .. + EMIT_MASKWRITE(0XF8006214, 0x000F03FFU ,0x000803FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006218[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006218[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006218[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006218[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006218[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006218, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF800621C[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF800621C[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF800621C[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF800621C[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF800621C[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF800621C, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006220[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006220[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006220[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006220[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006220[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006220, 0x000F03FFU ,0x000003FFU), + // .. .. reg_arb_pri_rd_portn = 0x3ff + // .. .. ==> 0XF8006224[9:0] = 0x000003FFU + // .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU + // .. .. reg_arb_disable_aging_rd_portn = 0x0 + // .. .. ==> 0XF8006224[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. reg_arb_disable_urgent_rd_portn = 0x0 + // .. .. ==> 0XF8006224[17:17] = 0x00000000U + // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. .. reg_arb_dis_page_match_rd_portn = 0x0 + // .. .. ==> 0XF8006224[18:18] = 0x00000000U + // .. .. ==> MASK : 0x00040000U VAL : 0x00000000U + // .. .. reg_arb_set_hpr_rd_portn = 0x0 + // .. .. ==> 0XF8006224[19:19] = 0x00000000U + // .. .. ==> MASK : 0x00080000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006224, 0x000F03FFU ,0x000003FFU), + // .. .. reg_ddrc_lpddr2 = 0x0 + // .. .. ==> 0XF80062A8[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. reg_ddrc_per_bank_refresh = 0x0 + // .. .. ==> 0XF80062A8[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_derate_enable = 0x0 + // .. .. ==> 0XF80062A8[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. reg_ddrc_mr4_margin = 0x0 + // .. .. ==> 0XF80062A8[11:4] = 0x00000000U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U ,0x00000000U), + // .. .. reg_ddrc_mr4_read_interval = 0x0 + // .. .. ==> 0XF80062AC[31:0] = 0x00000000U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU ,0x00000000U), + // .. .. reg_ddrc_min_stable_clock_x1 = 0x5 + // .. .. ==> 0XF80062B0[3:0] = 0x00000005U + // .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U + // .. .. reg_ddrc_idle_after_reset_x32 = 0x12 + // .. .. ==> 0XF80062B0[11:4] = 0x00000012U + // .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U + // .. .. reg_ddrc_t_mrw = 0x5 + // .. .. ==> 0XF80062B0[21:12] = 0x00000005U + // .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U + // .. .. + EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU ,0x00005125U), + // .. .. reg_ddrc_max_auto_init_x1024 = 0xa8 + // .. .. ==> 0XF80062B4[7:0] = 0x000000A8U + // .. .. ==> MASK : 0x000000FFU VAL : 0x000000A8U + // .. .. reg_ddrc_dev_zqinit_x32 = 0x12 + // .. .. ==> 0XF80062B4[17:8] = 0x00000012U + // .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U + // .. .. + EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU ,0x000012A8U), + // .. .. START: POLL ON DCI STATUS + // .. .. DONE = 1 + // .. .. ==> 0XF8000B74[13:13] = 0x00000001U + // .. .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. .. + EMIT_MASKPOLL(0XF8000B74, 0x00002000U), + // .. .. FINISH: POLL ON DCI STATUS + // .. .. START: UNLOCK DDR + // .. .. reg_ddrc_soft_rstb = 0x1 + // .. .. ==> 0XF8006000[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. reg_ddrc_powerdown_en = 0x0 + // .. .. ==> 0XF8006000[1:1] = 0x00000000U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. .. reg_ddrc_data_bus_width = 0x0 + // .. .. ==> 0XF8006000[3:2] = 0x00000000U + // .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U + // .. .. reg_ddrc_burst8_refresh = 0x0 + // .. .. ==> 0XF8006000[6:4] = 0x00000000U + // .. .. ==> MASK : 0x00000070U VAL : 0x00000000U + // .. .. reg_ddrc_rdwr_idle_gap = 1 + // .. .. ==> 0XF8006000[13:7] = 0x00000001U + // .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U + // .. .. reg_ddrc_dis_rd_bypass = 0x0 + // .. .. ==> 0XF8006000[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_act_bypass = 0x0 + // .. .. ==> 0XF8006000[15:15] = 0x00000000U + // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. reg_ddrc_dis_auto_refresh = 0x0 + // .. .. ==> 0XF8006000[16:16] = 0x00000000U + // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU ,0x00000081U), + // .. .. FINISH: UNLOCK DDR + // .. .. START: CHECK DDR STATUS + // .. .. ddrc_reg_operating_mode = 1 + // .. .. ==> 0XF8006054[2:0] = 0x00000001U + // .. .. ==> MASK : 0x00000007U VAL : 0x00000001U + // .. .. + EMIT_MASKPOLL(0XF8006054, 0x00000007U), + // .. .. FINISH: CHECK DDR STATUS + // .. FINISH: DDR INITIALIZATION + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_mio_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: OCM REMAPPING + // .. VREF_EN = 0x1 + // .. ==> 0XF8000B00[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLK_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. SRSTN_PULLUP_EN = 0x0 + // .. ==> 0XF8000B00[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B00, 0x00000303U ,0x00000001U), + // .. FINISH: OCM REMAPPING + // .. START: DDRIOB SETTINGS + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B40[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B40[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B40[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B40[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B40[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B40[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B40[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B40[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B44[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B44[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B44[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B44[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B44[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B44[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B44[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B44[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU ,0x00000600U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B48[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B48[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B48[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B48[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B48[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B48[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B48[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B48[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B4C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x1 + // .. ==> 0XF8000B4C[2:1] = 0x00000001U + // .. ==> MASK : 0x00000006U VAL : 0x00000002U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B4C[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B4C[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B4C[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B4C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B4C[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B4C[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU ,0x00000672U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B50[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B50[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B50[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B50[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B50[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B50[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B50[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B50[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B54[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x2 + // .. ==> 0XF8000B54[2:1] = 0x00000002U + // .. ==> MASK : 0x00000006U VAL : 0x00000004U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B54[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x1 + // .. ==> 0XF8000B54[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. DCR_TYPE = 0x3 + // .. ==> 0XF8000B54[6:5] = 0x00000003U + // .. ==> MASK : 0x00000060U VAL : 0x00000060U + // .. IBUF_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0 + // .. ==> 0XF8000B54[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B54[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B54[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU ,0x00000674U), + // .. INP_POWER = 0x0 + // .. ==> 0XF8000B58[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. INP_TYPE = 0x0 + // .. ==> 0XF8000B58[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. DCI_UPDATE = 0x0 + // .. ==> 0XF8000B58[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. TERM_EN = 0x0 + // .. ==> 0XF8000B58[4:4] = 0x00000000U + // .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. DCR_TYPE = 0x0 + // .. ==> 0XF8000B58[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. IBUF_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. TERM_DISABLE_MODE = 0x0 + // .. ==> 0XF8000B58[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. OUTPUT_EN = 0x3 + // .. ==> 0XF8000B58[10:9] = 0x00000003U + // .. ==> MASK : 0x00000600U VAL : 0x00000600U + // .. PULLUP_EN = 0x0 + // .. ==> 0XF8000B58[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU ,0x00000600U), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B5C[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B5C[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x3 + // .. ==> 0XF8000B5C[18:14] = 0x00000003U + // .. ==> MASK : 0x0007C000U VAL : 0x0000C000U + // .. SLEW_N = 0x3 + // .. ==> 0XF8000B5C[23:19] = 0x00000003U + // .. ==> MASK : 0x00F80000U VAL : 0x00180000U + // .. GTL = 0x0 + // .. ==> 0XF8000B5C[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B5C[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU ,0x0018C61CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B60[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B60[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B60[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B60[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B60[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B60[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B64[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B64[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B64[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B64[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B64[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B64[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU ,0x00F9861CU), + // .. DRIVE_P = 0x1c + // .. ==> 0XF8000B68[6:0] = 0x0000001CU + // .. ==> MASK : 0x0000007FU VAL : 0x0000001CU + // .. DRIVE_N = 0xc + // .. ==> 0XF8000B68[13:7] = 0x0000000CU + // .. ==> MASK : 0x00003F80U VAL : 0x00000600U + // .. SLEW_P = 0x6 + // .. ==> 0XF8000B68[18:14] = 0x00000006U + // .. ==> MASK : 0x0007C000U VAL : 0x00018000U + // .. SLEW_N = 0x1f + // .. ==> 0XF8000B68[23:19] = 0x0000001FU + // .. ==> MASK : 0x00F80000U VAL : 0x00F80000U + // .. GTL = 0x0 + // .. ==> 0XF8000B68[26:24] = 0x00000000U + // .. ==> MASK : 0x07000000U VAL : 0x00000000U + // .. RTERM = 0x0 + // .. ==> 0XF8000B68[31:27] = 0x00000000U + // .. ==> MASK : 0xF8000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU ,0x00F9861CU), + // .. VREF_INT_EN = 0x1 + // .. ==> 0XF8000B6C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. VREF_SEL = 0x4 + // .. ==> 0XF8000B6C[4:1] = 0x00000004U + // .. ==> MASK : 0x0000001EU VAL : 0x00000008U + // .. VREF_EXT_EN = 0x0 + // .. ==> 0XF8000B6C[6:5] = 0x00000000U + // .. ==> MASK : 0x00000060U VAL : 0x00000000U + // .. VREF_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[8:7] = 0x00000000U + // .. ==> MASK : 0x00000180U VAL : 0x00000000U + // .. REFIO_EN = 0x1 + // .. ==> 0XF8000B6C[9:9] = 0x00000001U + // .. ==> MASK : 0x00000200U VAL : 0x00000200U + // .. REFIO_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DRST_B_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. CKE_PULLUP_EN = 0x0 + // .. ==> 0XF8000B6C[14:14] = 0x00000000U + // .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU ,0x00000209U), + // .. .. START: ASSERT RESET + // .. .. RESET = 1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000021U), + // .. .. FINISH: ASSERT RESET + // .. .. START: DEASSERT RESET + // .. .. RESET = 0 + // .. .. ==> 0XF8000B70[0:0] = 0x00000000U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x00000021U ,0x00000020U), + // .. .. FINISH: DEASSERT RESET + // .. .. RESET = 0x1 + // .. .. ==> 0XF8000B70[0:0] = 0x00000001U + // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. .. ENABLE = 0x1 + // .. .. ==> 0XF8000B70[1:1] = 0x00000001U + // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. .. VRP_TRI = 0x0 + // .. .. ==> 0XF8000B70[2:2] = 0x00000000U + // .. .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. .. VRN_TRI = 0x0 + // .. .. ==> 0XF8000B70[3:3] = 0x00000000U + // .. .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. .. VRP_OUT = 0x0 + // .. .. ==> 0XF8000B70[4:4] = 0x00000000U + // .. .. ==> MASK : 0x00000010U VAL : 0x00000000U + // .. .. VRN_OUT = 0x1 + // .. .. ==> 0XF8000B70[5:5] = 0x00000001U + // .. .. ==> MASK : 0x00000020U VAL : 0x00000020U + // .. .. NREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[7:6] = 0x00000000U + // .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. .. NREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[10:8] = 0x00000000U + // .. .. ==> MASK : 0x00000700U VAL : 0x00000000U + // .. .. NREF_OPT4 = 0x1 + // .. .. ==> 0XF8000B70[13:11] = 0x00000001U + // .. .. ==> MASK : 0x00003800U VAL : 0x00000800U + // .. .. PREF_OPT1 = 0x0 + // .. .. ==> 0XF8000B70[16:14] = 0x00000000U + // .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U + // .. .. PREF_OPT2 = 0x0 + // .. .. ==> 0XF8000B70[19:17] = 0x00000000U + // .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U + // .. .. UPDATE_CONTROL = 0x0 + // .. .. ==> 0XF8000B70[20:20] = 0x00000000U + // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. .. INIT_COMPLETE = 0x0 + // .. .. ==> 0XF8000B70[21:21] = 0x00000000U + // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. .. TST_CLK = 0x0 + // .. .. ==> 0XF8000B70[22:22] = 0x00000000U + // .. .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. .. TST_HLN = 0x0 + // .. .. ==> 0XF8000B70[23:23] = 0x00000000U + // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. .. TST_HLP = 0x0 + // .. .. ==> 0XF8000B70[24:24] = 0x00000000U + // .. .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. .. TST_RST = 0x0 + // .. .. ==> 0XF8000B70[25:25] = 0x00000000U + // .. .. ==> MASK : 0x02000000U VAL : 0x00000000U + // .. .. INT_DCI_EN = 0x0 + // .. .. ==> 0XF8000B70[26:26] = 0x00000000U + // .. .. ==> MASK : 0x04000000U VAL : 0x00000000U + // .. .. + EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU ,0x00000823U), + // .. FINISH: DDRIOB SETTINGS + // .. START: MIO PROGRAMMING + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000700[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF8000700[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000700[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000700[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000700[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000700, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000704[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000704[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000704[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000704[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000704[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000704[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000704[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000704[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000704[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000704, 0x00003FFFU ,0x00001202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000708[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000708[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000708[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000708[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000708[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000708[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000708[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000708[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000708[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000708, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800070C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800070C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800070C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800070C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800070C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800070C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800070C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800070C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800070C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800070C, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000710[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000710[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000710[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000710[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000710[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000710[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000710[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000710[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000710[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000710, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000714[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000714[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000714[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000714[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000714[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000714[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000714[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000714[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000714[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000714, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000718[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000718[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000718[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000718[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000718[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000718[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000718[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000718[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000718[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000718, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800071C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800071C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800071C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800071C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800071C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800071C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800071C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800071C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800071C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800071C, 0x00003FFFU ,0x00000200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000720[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000720[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000720[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000720[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000720[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000720[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000720[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000720[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000720[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000720, 0x00003FFFU ,0x00000202U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000724[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000724[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000724[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000724[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000724[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000724[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000724[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000724[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000724[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000724, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000728[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000728[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000728[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000728[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000728[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000728[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000728[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000728[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000728[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000728, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800072C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800072C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF800072C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800072C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800072C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800072C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800072C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800072C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800072C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800072C, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000730[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000730[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000730[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000730[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000730[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000730[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000730[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000730[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000730[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000730, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000734[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000734[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000734[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000734[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000734[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000734[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000734[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000734[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000734[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000734, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000738[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000738[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF8000738[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000738[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000738[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000738[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000738[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF8000738[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000738[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000738, 0x00003FFFU ,0x00001200U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800073C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. Speed = 0 + // .. ==> 0XF800073C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800073C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF800073C[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF800073C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800073C, 0x00003F01U ,0x00001201U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000740[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000740[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000740[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000740[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000740[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000740[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000740[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000740[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000740[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000744[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000744[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000744[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000744[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000744[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000744[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000744[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000744[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000744[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000748[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000748[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000748[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000748[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000748[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000748[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000748[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000748[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000748[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800074C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF800074C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800074C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800074C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800074C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800074C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800074C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800074C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF800074C[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000750[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000750[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000750[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000750[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000750[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000750[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000750[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000750[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000750[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000754[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 1 + // .. ==> 0XF8000754[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000754[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000754[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000754[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000754[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000754[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000754[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 1 + // .. ==> 0XF8000754[13:13] = 0x00000001U + // .. ==> MASK : 0x00002000U VAL : 0x00002000U + // .. + EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00002802U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000758[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000758[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000758[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000758[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000758[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000758[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000758[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000758[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000758[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000758, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800075C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800075C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800075C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800075C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800075C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800075C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800075C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800075C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800075C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800075C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000760[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000760[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000760[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000760[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000760[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000760[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000760[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000760[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000760[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000760, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000764[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000764[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000764[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000764[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000764[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000764[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000764[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000764[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000764[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000764, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000768[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF8000768[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF8000768[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF8000768[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000768[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000768[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF8000768[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF8000768[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000768[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000768, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800076C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 1 + // .. ==> 0XF800076C[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. L1_SEL = 0 + // .. ==> 0XF800076C[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF800076C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800076C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800076C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 4 + // .. ==> 0XF800076C[11:9] = 0x00000004U + // .. ==> MASK : 0x00000E00U VAL : 0x00000800U + // .. PULLUP = 0 + // .. ==> 0XF800076C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800076C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800076C, 0x00003FFFU ,0x00000803U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000770[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000770[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000770[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000770[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000770[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000770[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000770[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000770[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000770[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000770, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000774[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000774[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000774[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000774[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000774[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000774[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000774[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000774[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000774[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000774, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000778[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000778[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000778[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000778[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000778[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000778[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000778[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000778[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000778[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000778, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF800077C[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF800077C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800077C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800077C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800077C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800077C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800077C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800077C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800077C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800077C, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000780[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000780[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000780[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000780[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000780[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000780[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000780[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000780[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000780[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000780, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000784[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000784[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000784[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000784[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000784[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000784[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000784[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000784[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000784[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000784, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000788[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000788[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000788[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000788[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000788[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000788[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000788[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000788[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000788[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000788, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800078C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800078C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800078C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800078C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800078C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800078C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800078C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800078C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800078C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800078C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF8000790[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF8000790[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000790[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000790[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000790[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000790[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000790[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000790[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000790[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000790, 0x00003FFFU ,0x00000205U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000794[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000794[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000794[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000794[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000794[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000794[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000794[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000794[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000794[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000794, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF8000798[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF8000798[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF8000798[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF8000798[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF8000798[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF8000798[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF8000798[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF8000798[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF8000798[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000798, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF800079C[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF800079C[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 1 + // .. ==> 0XF800079C[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. L2_SEL = 0 + // .. ==> 0XF800079C[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 0 + // .. ==> 0XF800079C[7:5] = 0x00000000U + // .. ==> MASK : 0x000000E0U VAL : 0x00000000U + // .. Speed = 0 + // .. ==> 0XF800079C[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF800079C[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF800079C[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF800079C[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF800079C, 0x00003FFFU ,0x00000204U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007A8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007A8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007A8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007A8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007A8[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007A8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007A8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007A8[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007A8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007AC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007AC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007AC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007AC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007AC[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007AC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007AC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007AC[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007AC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007B4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007B4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007B4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007B4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007B4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007B8[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007B8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007B8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007B8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007B8[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007B8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007B8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007B8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007B8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU ,0x00001221U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007BC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007BC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007BC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007BC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 1 + // .. ==> 0XF80007BC[7:5] = 0x00000001U + // .. ==> MASK : 0x000000E0U VAL : 0x00000020U + // .. Speed = 0 + // .. ==> 0XF80007BC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007BC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007BC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007BC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU ,0x00001220U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C0[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU ,0x000002E0U), + // .. TRI_ENABLE = 1 + // .. ==> 0XF80007C4[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. L0_SEL = 0 + // .. ==> 0XF80007C4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 7 + // .. ==> 0XF80007C4[7:5] = 0x00000007U + // .. ==> MASK : 0x000000E0U VAL : 0x000000E0U + // .. Speed = 0 + // .. ==> 0XF80007C4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007C4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU ,0x000002E1U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007C8[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007C8[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007C8[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007C8[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007C8[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007C8[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007C8[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007C8[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007C8[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007CC[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007CC[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007CC[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007CC[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 2 + // .. ==> 0XF80007CC[7:5] = 0x00000002U + // .. ==> MASK : 0x000000E0U VAL : 0x00000040U + // .. Speed = 0 + // .. ==> 0XF80007CC[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007CC[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 1 + // .. ==> 0XF80007CC[12:12] = 0x00000001U + // .. ==> MASK : 0x00001000U VAL : 0x00001000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007CC[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU ,0x00001240U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D0[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D0[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D0[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D0[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D0[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D0[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D0[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D0[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D0[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU ,0x00000280U), + // .. TRI_ENABLE = 0 + // .. ==> 0XF80007D4[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. L0_SEL = 0 + // .. ==> 0XF80007D4[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. L1_SEL = 0 + // .. ==> 0XF80007D4[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. L2_SEL = 0 + // .. ==> 0XF80007D4[4:3] = 0x00000000U + // .. ==> MASK : 0x00000018U VAL : 0x00000000U + // .. L3_SEL = 4 + // .. ==> 0XF80007D4[7:5] = 0x00000004U + // .. ==> MASK : 0x000000E0U VAL : 0x00000080U + // .. Speed = 0 + // .. ==> 0XF80007D4[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. IO_Type = 1 + // .. ==> 0XF80007D4[11:9] = 0x00000001U + // .. ==> MASK : 0x00000E00U VAL : 0x00000200U + // .. PULLUP = 0 + // .. ==> 0XF80007D4[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. DisableRcvr = 0 + // .. ==> 0XF80007D4[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU ,0x00000280U), + // .. SDIO0_WP_SEL = 15 + // .. ==> 0XF8000830[5:0] = 0x0000000FU + // .. ==> MASK : 0x0000003FU VAL : 0x0000000FU + // .. SDIO0_CD_SEL = 0 + // .. ==> 0XF8000830[21:16] = 0x00000000U + // .. ==> MASK : 0x003F0000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x0000000FU), + // .. FINISH: MIO PROGRAMMING + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_peripherals_init_data_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B48[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B48, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B4C[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B4C, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B50[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B50, 0x00000180U ,0x00000180U), + // .. IBUF_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[7:7] = 0x00000001U + // .. ==> MASK : 0x00000080U VAL : 0x00000080U + // .. TERM_DISABLE_MODE = 0x1 + // .. ==> 0XF8000B54[8:8] = 0x00000001U + // .. ==> MASK : 0x00000100U VAL : 0x00000100U + // .. + EMIT_MASKWRITE(0XF8000B54, 0x00000180U ,0x00000180U), + // .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // .. START: SRAM/NOR SET OPMODE + // .. FINISH: SRAM/NOR SET OPMODE + // .. START: TRACE CURRENT PORT SIZE + // .. FINISH: TRACE CURRENT PORT SIZE + // .. START: UART REGISTERS + // .. BDIV = 0x6 + // .. ==> 0XE0001034[7:0] = 0x00000006U + // .. ==> MASK : 0x000000FFU VAL : 0x00000006U + // .. + EMIT_MASKWRITE(0XE0001034, 0x000000FFU ,0x00000006U), + // .. CD = 0x3e + // .. ==> 0XE0001018[15:0] = 0x0000003EU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000003EU + // .. + EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU ,0x0000003EU), + // .. STPBRK = 0x0 + // .. ==> 0XE0001000[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. STTBRK = 0x0 + // .. ==> 0XE0001000[7:7] = 0x00000000U + // .. ==> MASK : 0x00000080U VAL : 0x00000000U + // .. RSTTO = 0x0 + // .. ==> 0XE0001000[6:6] = 0x00000000U + // .. ==> MASK : 0x00000040U VAL : 0x00000000U + // .. TXDIS = 0x0 + // .. ==> 0XE0001000[5:5] = 0x00000000U + // .. ==> MASK : 0x00000020U VAL : 0x00000000U + // .. TXEN = 0x1 + // .. ==> 0XE0001000[4:4] = 0x00000001U + // .. ==> MASK : 0x00000010U VAL : 0x00000010U + // .. RXDIS = 0x0 + // .. ==> 0XE0001000[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. RXEN = 0x1 + // .. ==> 0XE0001000[2:2] = 0x00000001U + // .. ==> MASK : 0x00000004U VAL : 0x00000004U + // .. TXRES = 0x1 + // .. ==> 0XE0001000[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U + // .. RXRES = 0x1 + // .. ==> 0XE0001000[0:0] = 0x00000001U + // .. ==> MASK : 0x00000001U VAL : 0x00000001U + // .. + EMIT_MASKWRITE(0XE0001000, 0x000001FFU ,0x00000017U), + // .. IRMODE = 0x0 + // .. ==> 0XE0001004[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. UCLKEN = 0x0 + // .. ==> 0XE0001004[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. CHMODE = 0x0 + // .. ==> 0XE0001004[9:8] = 0x00000000U + // .. ==> MASK : 0x00000300U VAL : 0x00000000U + // .. NBSTOP = 0x0 + // .. ==> 0XE0001004[7:6] = 0x00000000U + // .. ==> MASK : 0x000000C0U VAL : 0x00000000U + // .. PAR = 0x4 + // .. ==> 0XE0001004[5:3] = 0x00000004U + // .. ==> MASK : 0x00000038U VAL : 0x00000020U + // .. CHRL = 0x0 + // .. ==> 0XE0001004[2:1] = 0x00000000U + // .. ==> MASK : 0x00000006U VAL : 0x00000000U + // .. CLKS = 0x0 + // .. ==> 0XE0001004[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XE0001004, 0x00000FFFU ,0x00000020U), + // .. FINISH: UART REGISTERS + // .. START: QSPI REGISTERS + // .. Holdb_dr = 1 + // .. ==> 0XE000D000[19:19] = 0x00000001U + // .. ==> MASK : 0x00080000U VAL : 0x00080000U + // .. + EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), + // .. FINISH: QSPI REGISTERS + // .. START: PL POWER ON RESET REGISTERS + // .. PCFG_POR_CNT_4K = 0 + // .. ==> 0XF8007000[29:29] = 0x00000000U + // .. ==> MASK : 0x20000000U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), + // .. FINISH: PL POWER ON RESET REGISTERS + // .. START: SMC TIMING CALCULATION REGISTER UPDATE + // .. .. START: NAND SET CYCLE + // .. .. FINISH: NAND SET CYCLE + // .. .. START: OPMODE + // .. .. FINISH: OPMODE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: SRAM/NOR CS0 SET CYCLE + // .. .. FINISH: SRAM/NOR CS0 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS0 BASE ADDRESS + // .. .. FINISH: NOR CS0 BASE ADDRESS + // .. .. START: SRAM/NOR CS1 SET CYCLE + // .. .. FINISH: SRAM/NOR CS1 SET CYCLE + // .. .. START: DIRECT COMMAND + // .. .. FINISH: DIRECT COMMAND + // .. .. START: NOR CS1 BASE ADDRESS + // .. .. FINISH: NOR CS1 BASE ADDRESS + // .. .. START: USB RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xff7f + // .. .. .. ==> 0XE000A000[31:16] = 0x0000FF7FU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xFF7F0000U + // .. .. .. DATA_0_LSW = 0x80 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000080U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000080U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xFF7F0080U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: USB RESET + // .. .. START: ENET RESET + // .. .. .. START: DIR MODE BANK 0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE BANK 0 + // .. .. .. START: DIR MODE BANK 1 + // .. .. .. FINISH: DIR MODE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE BANK 0 + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE BANK 0 + // .. .. .. START: OUTPUT ENABLE BANK 1 + // .. .. .. FINISH: OUTPUT ENABLE BANK 1 + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xf7ff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000F7FFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xF7FF0000U + // .. .. .. DATA_0_LSW = 0x800 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000800U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000800U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xF7FF0800U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: ENET RESET + // .. .. START: I2C RESET + // .. .. .. START: DIR MODE GPIO BANK0 + // .. .. .. DIRECTION_0 = 0x2880 + // .. .. .. ==> 0XE000A204[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A204, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: DIR MODE GPIO BANK0 + // .. .. .. START: DIR MODE GPIO BANK1 + // .. .. .. FINISH: DIR MODE GPIO BANK1 + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. START: OUTPUT ENABLE + // .. .. .. OP_ENABLE_0 = 0x2880 + // .. .. .. ==> 0XE000A208[31:0] = 0x00002880U + // .. .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00002880U + // .. .. .. + EMIT_MASKWRITE(0XE000A208, 0xFFFFFFFFU ,0x00002880U), + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: OUTPUT ENABLE + // .. .. .. FINISH: OUTPUT ENABLE + // .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x0 + // .. .. .. ==> 0XE000A000[15:0] = 0x00000000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF0000U), + // .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] + // .. .. .. START: ADD 1 MS DELAY + // .. .. .. + EMIT_MASKDELAY(0XF8F00200, 1), + // .. .. .. FINISH: ADD 1 MS DELAY + // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. MASK_0_LSW = 0xdfff + // .. .. .. ==> 0XE000A000[31:16] = 0x0000DFFFU + // .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xDFFF0000U + // .. .. .. DATA_0_LSW = 0x2000 + // .. .. .. ==> 0XE000A000[15:0] = 0x00002000U + // .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00002000U + // .. .. .. + EMIT_MASKWRITE(0XE000A000, 0xFFFFFFFFU ,0xDFFF2000U), + // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] + // .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] + // .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] + // .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] + // .. .. FINISH: I2C RESET + // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_post_config_1_0[] = { + // START: top + // .. START: SLCR SETTINGS + // .. UNLOCK_KEY = 0XDF0D + // .. ==> 0XF8000008[15:0] = 0x0000DF0DU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU + // .. + EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU), + // .. FINISH: SLCR SETTINGS + // .. START: ENABLING LEVEL SHIFTER + // .. USER_INP_ICT_EN_0 = 3 + // .. ==> 0XF8000900[1:0] = 0x00000003U + // .. ==> MASK : 0x00000003U VAL : 0x00000003U + // .. USER_INP_ICT_EN_1 = 3 + // .. ==> 0XF8000900[3:2] = 0x00000003U + // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU + // .. + EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), + // .. FINISH: ENABLING LEVEL SHIFTER + // .. START: FPGA RESETS TO 0 + // .. reserved_3 = 0 + // .. ==> 0XF8000240[31:25] = 0x00000000U + // .. ==> MASK : 0xFE000000U VAL : 0x00000000U + // .. FPGA_ACP_RST = 0 + // .. ==> 0XF8000240[24:24] = 0x00000000U + // .. ==> MASK : 0x01000000U VAL : 0x00000000U + // .. FPGA_AXDS3_RST = 0 + // .. ==> 0XF8000240[23:23] = 0x00000000U + // .. ==> MASK : 0x00800000U VAL : 0x00000000U + // .. FPGA_AXDS2_RST = 0 + // .. ==> 0XF8000240[22:22] = 0x00000000U + // .. ==> MASK : 0x00400000U VAL : 0x00000000U + // .. FPGA_AXDS1_RST = 0 + // .. ==> 0XF8000240[21:21] = 0x00000000U + // .. ==> MASK : 0x00200000U VAL : 0x00000000U + // .. FPGA_AXDS0_RST = 0 + // .. ==> 0XF8000240[20:20] = 0x00000000U + // .. ==> MASK : 0x00100000U VAL : 0x00000000U + // .. reserved_2 = 0 + // .. ==> 0XF8000240[19:18] = 0x00000000U + // .. ==> MASK : 0x000C0000U VAL : 0x00000000U + // .. FSSW1_FPGA_RST = 0 + // .. ==> 0XF8000240[17:17] = 0x00000000U + // .. ==> MASK : 0x00020000U VAL : 0x00000000U + // .. FSSW0_FPGA_RST = 0 + // .. ==> 0XF8000240[16:16] = 0x00000000U + // .. ==> MASK : 0x00010000U VAL : 0x00000000U + // .. reserved_1 = 0 + // .. ==> 0XF8000240[15:14] = 0x00000000U + // .. ==> MASK : 0x0000C000U VAL : 0x00000000U + // .. FPGA_FMSW1_RST = 0 + // .. ==> 0XF8000240[13:13] = 0x00000000U + // .. ==> MASK : 0x00002000U VAL : 0x00000000U + // .. FPGA_FMSW0_RST = 0 + // .. ==> 0XF8000240[12:12] = 0x00000000U + // .. ==> MASK : 0x00001000U VAL : 0x00000000U + // .. FPGA_DMA3_RST = 0 + // .. ==> 0XF8000240[11:11] = 0x00000000U + // .. ==> MASK : 0x00000800U VAL : 0x00000000U + // .. FPGA_DMA2_RST = 0 + // .. ==> 0XF8000240[10:10] = 0x00000000U + // .. ==> MASK : 0x00000400U VAL : 0x00000000U + // .. FPGA_DMA1_RST = 0 + // .. ==> 0XF8000240[9:9] = 0x00000000U + // .. ==> MASK : 0x00000200U VAL : 0x00000000U + // .. FPGA_DMA0_RST = 0 + // .. ==> 0XF8000240[8:8] = 0x00000000U + // .. ==> MASK : 0x00000100U VAL : 0x00000000U + // .. reserved = 0 + // .. ==> 0XF8000240[7:4] = 0x00000000U + // .. ==> MASK : 0x000000F0U VAL : 0x00000000U + // .. FPGA3_OUT_RST = 0 + // .. ==> 0XF8000240[3:3] = 0x00000000U + // .. ==> MASK : 0x00000008U VAL : 0x00000000U + // .. FPGA2_OUT_RST = 0 + // .. ==> 0XF8000240[2:2] = 0x00000000U + // .. ==> MASK : 0x00000004U VAL : 0x00000000U + // .. FPGA1_OUT_RST = 0 + // .. ==> 0XF8000240[1:1] = 0x00000000U + // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. FPGA0_OUT_RST = 0 + // .. ==> 0XF8000240[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. + EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), + // .. FINISH: FPGA RESETS TO 0 + // .. START: AFI REGISTERS + // .. .. START: AFI0 REGISTERS + // .. .. FINISH: AFI0 REGISTERS + // .. .. START: AFI1 REGISTERS + // .. .. FINISH: AFI1 REGISTERS + // .. .. START: AFI2 REGISTERS + // .. .. FINISH: AFI2 REGISTERS + // .. .. START: AFI3 REGISTERS + // .. .. FINISH: AFI3 REGISTERS + // .. FINISH: AFI REGISTERS + // .. START: LOCK IT BACK + // .. LOCK_KEY = 0X767B + // .. ==> 0XF8000004[15:0] = 0x0000767BU + // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU + // .. + EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU), + // .. FINISH: LOCK IT BACK + // FINISH: top + // + EMIT_EXIT(), + + // +}; + +unsigned long ps7_debug_1_0[] = { + // START: top + // .. START: CROSS TRIGGER CONFIGURATIONS + // .. .. START: UNLOCKING CTI REGISTERS + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. KEY = 0XC5ACCE55 + // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U + // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U + // .. .. + EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), + // .. .. FINISH: UNLOCKING CTI REGISTERS + // .. .. START: ENABLING CTI MODULES AND CHANNELS + // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS + // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS + // .. FINISH: CROSS TRIGGER CONFIGURATIONS + // FINISH: top + // + EMIT_EXIT(), + + // +}; + + +#include "xil_io.h" +#define PS7_MASK_POLL_TIME 100000000 + +char* +getPS7MessageInfo(unsigned key) { + + char* err_msg = ""; + switch (key) { + case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; + case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; + case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; + case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; + case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; + case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; + default: err_msg = "Undefined error status"; break; + } + + return err_msg; +} + +unsigned long +ps7GetSiliconVersion () { + // Read PS version from MCTRL register [31:28] + unsigned long mask = 0xF0000000; + unsigned long *addr = (unsigned long*) 0XF8007080; + unsigned long ps_version = (*addr & mask) >> 28; + return ps_version; +} + +void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { + unsigned long *addr = (unsigned long*) add; + *addr = ( val & mask ) | ( *addr & ~mask); + //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); +} + + +int mask_poll(unsigned long add , unsigned long mask ) { + volatile unsigned long *addr = (volatile unsigned long*) add; + int i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + return -1; + } + i++; + } + return 1; + //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); +} + +unsigned long mask_read(unsigned long add , unsigned long mask ) { + unsigned long *addr = (unsigned long*) add; + unsigned long val = (*addr & mask); + //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); + return val; +} + + + +int +ps7_config(unsigned long * ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + + unsigned long opcode; // current instruction .. + unsigned long args[16]; // no opcode has so many args ... + int numargs; // number of arguments of this instruction + int j; // general purpose index + + volatile unsigned long *addr; // some variable to make code readable + unsigned long val,mask; // some variable to make code readable + + int finish = -1 ; // loop while this is negative ! + int i = 0; // Timeout variable + + while( finish < 0 ) { + numargs = ptr[0] & 0xF; + opcode = ptr[0] >> 4; + + for( j = 0 ; j < numargs ; j ++ ) + args[j] = ptr[j+1]; + ptr += numargs + 1; + + + switch ( opcode ) { + + case OPCODE_EXIT: + finish = PS7_INIT_SUCCESS; + break; + + case OPCODE_CLEAR: + addr = (unsigned long*) args[0]; + *addr = 0; + break; + + case OPCODE_WRITE: + addr = (unsigned long*) args[0]; + val = args[1]; + *addr = val; + break; + + case OPCODE_MASKWRITE: + addr = (unsigned long*) args[0]; + mask = args[1]; + val = args[2]; + *addr = ( val & mask ) | ( *addr & ~mask); + break; + + case OPCODE_MASKPOLL: + addr = (unsigned long*) args[0]; + mask = args[1]; + i = 0; + while (!(*addr & mask)) { + if (i == PS7_MASK_POLL_TIME) { + finish = PS7_INIT_TIMEOUT; + break; + } + i++; + } + break; + case OPCODE_MASKDELAY: + addr = (unsigned long*) args[0]; + mask = args[1]; + int delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while ((*addr < delay)) { + } + break; + default: + finish = PS7_INIT_CORRUPT; + break; + } + } + return finish; +} + +unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; +unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; +unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; +unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; +unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + +int +ps7_post_config() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_post_config_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_post_config_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_post_config_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_debug() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret = -1; + if (si_ver == PCW_SILICON_VERSION_1) { + ret = ps7_config (ps7_debug_1_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else if (si_ver == PCW_SILICON_VERSION_2) { + ret = ps7_config (ps7_debug_2_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } else { + ret = ps7_config (ps7_debug_3_0); + if (ret != PS7_INIT_SUCCESS) return ret; + } + return PS7_INIT_SUCCESS; +} + +int +ps7_init() +{ + // Get the PS_VERSION on run time + unsigned long si_ver = ps7GetSiliconVersion (); + int ret; + //int pcw_ver = 0; + + if (si_ver == PCW_SILICON_VERSION_1) { + ps7_mio_init_data = ps7_mio_init_data_1_0; + ps7_pll_init_data = ps7_pll_init_data_1_0; + ps7_clock_init_data = ps7_clock_init_data_1_0; + ps7_ddr_init_data = ps7_ddr_init_data_1_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; + //pcw_ver = 1; + + } else if (si_ver == PCW_SILICON_VERSION_2) { + ps7_mio_init_data = ps7_mio_init_data_2_0; + ps7_pll_init_data = ps7_pll_init_data_2_0; + ps7_clock_init_data = ps7_clock_init_data_2_0; + ps7_ddr_init_data = ps7_ddr_init_data_2_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; + //pcw_ver = 2; + + } else { + ps7_mio_init_data = ps7_mio_init_data_3_0; + ps7_pll_init_data = ps7_pll_init_data_3_0; + ps7_clock_init_data = ps7_clock_init_data_3_0; + ps7_ddr_init_data = ps7_ddr_init_data_3_0; + ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; + //pcw_ver = 3; + } + + // MIO init + ret = ps7_config (ps7_mio_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // PLL init + ret = ps7_config (ps7_pll_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // Clock init + ret = ps7_config (ps7_clock_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + // DDR init + ret = ps7_config (ps7_ddr_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + + + + // Peripherals init + ret = ps7_config (ps7_peripherals_init_data); + if (ret != PS7_INIT_SUCCESS) return ret; + //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); + return PS7_INIT_SUCCESS; +} + + + + +/* For delay calculation using global timer */ + +/* start timer */ + void perf_start_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable + (1 << 3) | // Auto-increment + (0 << 8) // Pre-scale + ); +} + +/* stop timer and reset timer count regs */ + void perf_reset_clock(void) +{ + perf_disable_clock(); + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; + *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; +} + +/* Compute mask for given delay in miliseconds*/ +int get_number_of_cycles_for_delay(unsigned int delay) +{ + // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + return (APU_FREQ*delay/(2*1000)); + +} + +/* stop timer */ + void perf_disable_clock(void) +{ + *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; +} + +void perf_reset_and_start_timer() +{ + perf_reset_clock(); + perf_start_clock(); +} + + + + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.h new file mode 100644 index 0000000..7b2f445 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/ps7_init.h @@ -0,0 +1,140 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file ps7_init.h +* +* This file can be included in FSBL code +* to get prototype of ps7_init() function +* and error codes +* +*****************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + + +//typedef unsigned int u32; + + +/** do we need to make this name more unique ? **/ +//extern u32 ps7_init_data[]; +extern unsigned long * ps7_ddr_init_data; +extern unsigned long * ps7_mio_init_data; +extern unsigned long * ps7_pll_init_data; +extern unsigned long * ps7_clock_init_data; +extern unsigned long * ps7_peripherals_init_data; + + + +#define OPCODE_EXIT 0U +#define OPCODE_CLEAR 1U +#define OPCODE_WRITE 2U +#define OPCODE_MASKWRITE 3U +#define OPCODE_MASKPOLL 4U +#define OPCODE_MASKDELAY 5U +#define NEW_PS7_ERR_CODE 1 + +/* Encode number of arguments in last nibble */ +#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) +#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr +#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val +#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val +#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask +#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask + +/* Returns codes of PS7_Init */ +#define PS7_INIT_SUCCESS (0) // 0 is success in good old C +#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now +#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out +#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init +#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit +#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init + + +/* Silicon Versions */ +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + +/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ +#define PS7_POST_CONFIG + +/* Freq of all peripherals */ + +#define APU_FREQ 666666687 +#define DDR_FREQ 533333374 +#define DCI_FREQ 10158731 +#define QSPI_FREQ 200000000 +#define SMC_FREQ 10000000 +#define ENET0_FREQ 25000000 +#define ENET1_FREQ 10000000 +#define USB0_FREQ 60000000 +#define USB1_FREQ 60000000 +#define SDIO_FREQ 50000000 +#define UART_FREQ 50000000 +#define SPI_FREQ 10000000 +#define I2C_FREQ 111111115 +#define WDT_FREQ 111111115 +#define TTC_FREQ 50000000 +#define CAN_FREQ 23809523 +#define PCAP_FREQ 200000000 +#define TPIU_FREQ 200000000 +#define FPGA0_FREQ 50000000 +#define FPGA1_FREQ 50000000 +#define FPGA2_FREQ 50000000 +#define FPGA3_FREQ 50000000 + + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 + +int ps7_config( unsigned long*); +int ps7_init(); +int ps7_post_config(); +int ps7_debug(); +char* getPS7MessageInfo(unsigned key); + +void perf_start_clock(void); +void perf_disable_clock(void); +void perf_reset_clock(void); +void perf_reset_and_start_timer(); +int get_number_of_cycles_for_delay(unsigned int delay); +#ifdef __cplusplus +} +#endif + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/qspi.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/qspi.c new file mode 100644 index 0000000..6fdf055 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/qspi.c @@ -0,0 +1,764 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file qspi.c +* +* Contains code for the QSPI FLASH functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 3.00a mb  25/06/12 InitQspi, data is read first and required config bits
+*                    are set
+* 4.00a sg	02/28/13 Cleanup
+* 					 Removed LPBK_DLY_ADJ register setting code as we use
+* 					 divisor 8
+* 5.00a sgd	05/17/13 Added Flash Size > 128Mbit support
+* 					 Dual Stack support
+*					 Fix for CR:721674 - FSBL- Failed to boot from Dual
+*					                     stacked QSPI
+* 6.00a kc  08/30/13 Fix for CR#722979 - Provide customer-friendly
+*                                        changelogs in FSBL
+*                    Fix for CR#739711 - FSBL not able to read Large QSPI
+*                    					 (512M) in IO Mode
+* 7.00a kc  10/25/13 Fix for CR#739968 - FSBL should do the QSPI config
+*                    					 settings for Dual parallel
+*                    					 configuration in IO mode
+* 14.0 gan 01/13/16  Fix for CR#869081 - (2016.1)FSBL picks the qspi read
+*                                        command from LQSPI_CFG register
+*					 					 instead of hard coded read
+*					 					 command (0x6B).
+*
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "qspi.h" +#include "image_mover.h" + +#ifdef XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR +#include "xqspips_hw.h" +#include "xqspips.h" + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define QSPI_DEVICE_ID XPAR_XQSPIPS_0_DEVICE_ID + +/* + * The following constants define the commands which may be sent to the FLASH + * device. + */ +#define QUAD_READ_CMD 0x6B +#define READ_ID_CMD 0x9F + +#define WRITE_ENABLE_CMD 0x06 +#define BANK_REG_RD 0x16 +#define BANK_REG_WR 0x17 +/* Bank register is called Extended Address Reg in Micron */ +#define EXTADD_REG_RD 0xC8 +#define EXTADD_REG_WR 0xC5 + +#define COMMAND_OFFSET 0 /* FLASH instruction */ +#define ADDRESS_1_OFFSET 1 /* MSB byte of address to read or write */ +#define ADDRESS_2_OFFSET 2 /* Middle byte of address to read or write */ +#define ADDRESS_3_OFFSET 3 /* LSB byte of address to read or write */ +#define DATA_OFFSET 4 /* Start of Data for Read/Write */ +#define DUMMY_OFFSET 4 /* Dummy byte offset for fast, dual and quad + reads */ +#define DUMMY_SIZE 1 /* Number of dummy bytes for fast, dual and + quad reads */ +#define RD_ID_SIZE 4 /* Read ID command + 3 bytes ID response */ +#define BANK_SEL_SIZE 2 /* BRWR or EARWR command + 1 byte bank value */ +#define WRITE_ENABLE_CMD_SIZE 1 /* WE command */ +/* + * The following constants specify the extra bytes which are sent to the + * FLASH on the QSPI interface, that are not data, but control information + * which includes the command and address + */ +#define OVERHEAD_SIZE 4 + +/* + * The following constants specify the max amount of data and the size of the + * the buffer required to hold the data and overhead to transfer the data to + * and from the FLASH. + */ +#define DATA_SIZE 4096 + +/* + * The following defines are for dual flash interface. + */ +#define LQSPI_CR_FAST_QUAD_READ 0x0000006B /* Fast Quad Read output */ +#define LQSPI_CR_1_DUMMY_BYTE 0x00000100 /* 1 Dummy Byte between + address and return data */ + +#define SINGLE_QSPI_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \ + LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + +#define DUAL_QSPI_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_LINEAR_MASK | \ + XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \ + XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \ + LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + +#define DUAL_STACK_CONFIG_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \ + LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + +#define SINGLE_QSPI_IO_CONFIG_QUAD_READ (LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + +#define DUAL_QSPI_IO_CONFIG_QUAD_READ (XQSPIPS_LQSPI_CR_TWO_MEM_MASK | \ + XQSPIPS_LQSPI_CR_SEP_BUS_MASK | \ + LQSPI_CR_1_DUMMY_BYTE | \ + LQSPI_CR_FAST_QUAD_READ) + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +XQspiPs QspiInstance; +XQspiPs *QspiInstancePtr; +u32 QspiFlashSize; +u32 QspiFlashMake; +extern u32 FlashReadBaseAddress; +extern u8 LinearBootDeviceFlag; + +/* + * The following variables are used to read and write to the eeprom and they + * are global to avoid having large buffers on the stack + */ +u8 ReadBuffer[DATA_SIZE + DATA_OFFSET + DUMMY_SIZE]; +u8 WriteBuffer[DATA_OFFSET + DUMMY_SIZE]; + +/******************************************************************************/ +/** +* +* This function initializes the controller for the QSPI interface. +* +* @param None +* +* @return None +* +* @note None +* +****************************************************************************/ +u32 InitQspi(void) +{ + XQspiPs_Config *QspiConfig; + int Status; + + QspiInstancePtr = &QspiInstance; + + /* + * Set up the base address for access + */ + FlashReadBaseAddress = XPS_QSPI_LINEAR_BASEADDR; + + /* + * Initialize the QSPI driver so that it's ready to use + */ + QspiConfig = XQspiPs_LookupConfig(QSPI_DEVICE_ID); + if (NULL == QspiConfig) { + return XST_FAILURE; + } + + Status = XQspiPs_CfgInitialize(QspiInstancePtr, QspiConfig, + QspiConfig->BaseAddress); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Set Manual Chip select options and drive HOLD_B pin high. + */ + XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_FORCE_SSELECT_OPTION | + XQSPIPS_HOLD_B_DRIVE_OPTION); + + /* + * Set the prescaler for QSPI clock + */ + XQspiPs_SetClkPrescaler(QspiInstancePtr, XQSPIPS_CLK_PRESCALE_8); + + /* + * Assert the FLASH chip select. + */ + XQspiPs_SetSlaveSelect(QspiInstancePtr); + + /* + * Read Flash ID and extract Manufacture and Size information + */ + Status = FlashReadID(); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + if (XPAR_PS7_QSPI_0_QSPI_MODE == SINGLE_FLASH_CONNECTION) { + + fsbl_printf(DEBUG_INFO,"QSPI is in single flash connection\r\n"); + /* + * For Flash size <128Mbit controller configured in linear mode + */ + if (QspiFlashSize <= FLASH_SIZE_16MB) { + LinearBootDeviceFlag = 1; + + /* + * Enable linear mode + */ + XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION | + XQSPIPS_HOLD_B_DRIVE_OPTION); + + /* + * Single linear read + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, SINGLE_QSPI_CONFIG_QUAD_READ); + + /* + * Enable the controller + */ + XQspiPs_Enable(QspiInstancePtr); + } else { + /* + * Single flash IO read + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, SINGLE_QSPI_IO_CONFIG_QUAD_READ); + + /* + * Enable the controller + */ + XQspiPs_Enable(QspiInstancePtr); + } + } + + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) { + + fsbl_printf(DEBUG_INFO,"QSPI is in Dual Parallel connection\r\n"); + /* + * For Single Flash size <128Mbit controller configured in linear mode + */ + if (QspiFlashSize <= FLASH_SIZE_16MB) { + /* + * Setting linear access flag + */ + LinearBootDeviceFlag = 1; + + /* + * Enable linear mode + */ + XQspiPs_SetOptions(QspiInstancePtr, XQSPIPS_LQSPI_MODE_OPTION | + XQSPIPS_HOLD_B_DRIVE_OPTION); + + /* + * Dual linear read + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_CONFIG_QUAD_READ); + + /* + * Enable the controller + */ + XQspiPs_Enable(QspiInstancePtr); + } else { + /* + * Dual flash IO read + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_QSPI_IO_CONFIG_QUAD_READ); + + /* + * Enable the controller + */ + XQspiPs_Enable(QspiInstancePtr); + + } + + /* + * Total flash size is two time of single flash size + */ + QspiFlashSize = 2 * QspiFlashSize; + } + + /* + * It is expected to same flash size for both chip selection + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) { + + fsbl_printf(DEBUG_INFO,"QSPI is in Dual Stack connection\r\n"); + + QspiFlashSize = 2 * QspiFlashSize; + + /* + * Enable two flash memories on separate buses + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, DUAL_STACK_CONFIG_READ); + } + + return XST_SUCCESS; +} + +/****************************************************************************** +* +* This function reads serial FLASH ID connected to the SPI interface. +* It then deduces the make and size of the flash and obtains the +* connection mode to point to corresponding parameters in the flash +* configuration table. The flash driver will function based on this and +* it presently supports Micron and Spansion - 128, 256 and 512Mbit and +* Winbond 128Mbit +* +* @param none +* +* @return XST_SUCCESS if read id, otherwise XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +u32 FlashReadID(void) +{ + u32 Status; + + /* + * Read ID in Auto mode. + */ + WriteBuffer[COMMAND_OFFSET] = READ_ID_CMD; + WriteBuffer[ADDRESS_1_OFFSET] = 0x00; /* 3 dummy bytes */ + WriteBuffer[ADDRESS_2_OFFSET] = 0x00; + WriteBuffer[ADDRESS_3_OFFSET] = 0x00; + + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer, + RD_ID_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + fsbl_printf(DEBUG_INFO,"Single Flash Information\r\n"); + + fsbl_printf(DEBUG_INFO,"FlashID=0x%x 0x%x 0x%x\r\n", ReadBuffer[1], + ReadBuffer[2], + ReadBuffer[3]); + + /* + * Deduce flash make + */ + if (ReadBuffer[1] == MICRON_ID) { + QspiFlashMake = MICRON_ID; + fsbl_printf(DEBUG_INFO, "MICRON "); + } else if(ReadBuffer[1] == SPANSION_ID) { + QspiFlashMake = SPANSION_ID; + fsbl_printf(DEBUG_INFO, "SPANSION "); + } else if(ReadBuffer[1] == WINBOND_ID) { + QspiFlashMake = WINBOND_ID; + fsbl_printf(DEBUG_INFO, "WINBOND "); + } else if(ReadBuffer[1] == MACRONIX_ID) { + QspiFlashMake = MACRONIX_ID; + fsbl_printf(DEBUG_INFO, "MACRONIX "); + } + + /* + * Deduce flash Size + */ + if (ReadBuffer[3] == FLASH_SIZE_ID_128M) { + QspiFlashSize = FLASH_SIZE_128M; + fsbl_printf(DEBUG_INFO, "128M Bits\r\n"); + } else if (ReadBuffer[3] == FLASH_SIZE_ID_256M) { + QspiFlashSize = FLASH_SIZE_256M; + fsbl_printf(DEBUG_INFO, "256M Bits\r\n"); + } else if ((ReadBuffer[3] == FLASH_SIZE_ID_512M) + || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_512M)) { + QspiFlashSize = FLASH_SIZE_512M; + fsbl_printf(DEBUG_INFO, "512M Bits\r\n"); + } else if ((ReadBuffer[3] == FLASH_SIZE_ID_1G) + || (ReadBuffer[3] == MACRONIX_FLASH_SIZE_ID_1G)) { + QspiFlashSize = FLASH_SIZE_1G; + fsbl_printf(DEBUG_INFO, "1G Bits\r\n"); + } + + return XST_SUCCESS; +} + + +/****************************************************************************** +* +* This function reads from the serial FLASH connected to the +* QSPI interface. +* +* @param Address contains the address to read data from in the FLASH. +* @param ByteCount contains the number of bytes to read. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void FlashRead(u32 Address, u32 ByteCount) +{ + /* + * Setup the write command with the specified address and data for the + * FLASH + */ + u32 LqspiCrReg; + u8 ReadCommand; + + LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr); + ReadCommand = (u8) (LqspiCrReg & XQSPIPS_LQSPI_CR_INST_MASK); + WriteBuffer[COMMAND_OFFSET] = ReadCommand; + WriteBuffer[ADDRESS_1_OFFSET] = (u8)((Address & 0xFF0000) >> 16); + WriteBuffer[ADDRESS_2_OFFSET] = (u8)((Address & 0xFF00) >> 8); + WriteBuffer[ADDRESS_3_OFFSET] = (u8)(Address & 0xFF); + + ByteCount += DUMMY_SIZE; + + /* + * Send the read command to the FLASH to read the specified number + * of bytes from the FLASH, send the read command and address and + * receive the specified number of bytes of data in the data buffer + */ + XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer, + ByteCount + OVERHEAD_SIZE); +} + +/******************************************************************************/ +/** +* +* This function provides the QSPI FLASH interface for the Simplified header +* functionality. +* +* @param SourceAddress is address in FLASH data space +* @param DestinationAddress is address in DDR data space +* @param LengthBytes is the length of the data in Bytes +* +* @return +* - XST_SUCCESS if the write completes correctly +* - XST_FAILURE if the write fails to completes correctly +* +* @note none. +* +****************************************************************************/ +u32 QspiAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes) +{ + u8 *BufferPtr; + u32 Length = 0; + u32 BankSel = 0; + u32 LqspiCrReg; + u32 Status; + u8 BankSwitchFlag = 1; + + /* + * Linear access check + */ + if (LinearBootDeviceFlag == 1) { + /* + * Check for non-word tail, add bytes to cover the end + */ + if ((LengthBytes%4) != 0){ + LengthBytes += (4 - (LengthBytes & 0x00000003)); + } + + memcpy((void*)DestinationAddress, + (const void*)(SourceAddress + FlashReadBaseAddress), + (size_t)LengthBytes); + } else { + /* + * Non Linear access + */ + BufferPtr = (u8*)DestinationAddress; + + /* + * Dual parallel connection actual flash is half + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) { + SourceAddress = SourceAddress/2; + } + + while(LengthBytes > 0) { + /* + * Local of DATA_SIZE size used for read/write buffer + */ + if(LengthBytes > DATA_SIZE) { + Length = DATA_SIZE; + } else { + Length = LengthBytes; + } + + /* + * Dual stack connection + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) { + /* + * Get the current LQSPI configuration value + */ + LqspiCrReg = XQspiPs_GetLqspiConfigReg(QspiInstancePtr); + + /* + * Select lower or upper Flash based on sector address + */ + if (SourceAddress >= (QspiFlashSize/2)) { + /* + * Set selection to U_PAGE + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, + LqspiCrReg | XQSPIPS_LQSPI_CR_U_PAGE_MASK); + + /* + * Subtract first flash size when accessing second flash + */ + SourceAddress = SourceAddress - (QspiFlashSize/2); + + fsbl_printf(DEBUG_INFO, "stacked - upper CS \n\r"); + + /* + * Assert the FLASH chip select. + */ + XQspiPs_SetSlaveSelect(QspiInstancePtr); + } + } + + /* + * Select bank + */ + if ((SourceAddress >= FLASH_SIZE_16MB) && (BankSwitchFlag == 1)) { + BankSel = SourceAddress/FLASH_SIZE_16MB; + + fsbl_printf(DEBUG_INFO, "Bank Selection %lu\n\r", BankSel); + + Status = SendBankSelect(BankSel); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO, "Bank Selection Failed\n\r"); + return XST_FAILURE; + } + + BankSwitchFlag = 0; + } + + /* + * If data to be read spans beyond the current bank, then + * calculate length in current bank else no change in length + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) { + /* + * In dual parallel mode, check should be for half + * the length. + */ + if((SourceAddress & BANKMASK) != ((SourceAddress + (Length/2)) & BANKMASK)) + { + Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress; + /* + * Above length calculated is for single flash + * Length should be doubled since dual parallel + */ + Length = Length * 2; + BankSwitchFlag = 1; + } + } else { + if((SourceAddress & BANKMASK) != ((SourceAddress + Length) & BANKMASK)) + { + Length = (SourceAddress & BANKMASK) + FLASH_SIZE_16MB - SourceAddress; + BankSwitchFlag = 1; + } + } + + /* + * Copying the image to local buffer + */ + FlashRead(SourceAddress, Length); + + /* + * Moving the data from local buffer to DDR destination address + */ + memcpy(BufferPtr, &ReadBuffer[DATA_OFFSET + DUMMY_SIZE], Length); + + /* + * Updated the variables + */ + LengthBytes -= Length; + + /* + * For Dual parallel connection address increment should be half + */ + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_PARALLEL_CONNECTION) { + SourceAddress += Length/2; + } else { + SourceAddress += Length; + } + + BufferPtr = (u8*)((u32)BufferPtr + Length); + } + + /* + * Reset Bank selection to zero + */ + Status = SendBankSelect(0); + if (Status != XST_SUCCESS) { + fsbl_printf(DEBUG_INFO, "Bank Selection Reset Failed\n\r"); + return XST_FAILURE; + } + + if (XPAR_PS7_QSPI_0_QSPI_MODE == DUAL_STACK_CONNECTION) { + + /* + * Reset selection to L_PAGE + */ + XQspiPs_SetLqspiConfigReg(QspiInstancePtr, + LqspiCrReg & (~XQSPIPS_LQSPI_CR_U_PAGE_MASK)); + + fsbl_printf(DEBUG_INFO, "stacked - lower CS \n\r"); + + /* + * Assert the FLASH chip select. + */ + XQspiPs_SetSlaveSelect(QspiInstancePtr); + } + } + + return XST_SUCCESS; +} + + + +/****************************************************************************** +* +* This functions selects the current bank +* +* @param BankSel is the bank to be selected in the flash device(s). +* +* @return XST_SUCCESS if bank selected +* XST_FAILURE if selection failed +* @note None. +* +******************************************************************************/ +u32 SendBankSelect(u8 BankSel) +{ + u32 Status; + + /* + * bank select commands for Micron and Spansion are different + * Macronix bank select is same as Micron + */ + if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) { + /* + * For micron command WREN should be sent first + * except for some specific feature set + */ + WriteBuffer[COMMAND_OFFSET] = WRITE_ENABLE_CMD; + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL, + WRITE_ENABLE_CMD_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* + * Send the Extended address register write command + * written, no receive buffer required + */ + WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_WR; + WriteBuffer[ADDRESS_1_OFFSET] = BankSel; + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL, + BANK_SEL_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + if (QspiFlashMake == SPANSION_ID) { + WriteBuffer[COMMAND_OFFSET] = BANK_REG_WR; + WriteBuffer[ADDRESS_1_OFFSET] = BankSel; + + /* + * Send the Extended address register write command + * written, no receive buffer required + */ + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, NULL, + BANK_SEL_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + /* + * For testing - Read bank to verify + */ + if (QspiFlashMake == SPANSION_ID) { + WriteBuffer[COMMAND_OFFSET] = BANK_REG_RD; + WriteBuffer[ADDRESS_1_OFFSET] = 0x00; + + /* + * Send the Extended address register write command + * written, no receive buffer required + */ + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer, + BANK_SEL_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + if (QspiFlashMake == MICRON_ID || QspiFlashMake == MACRONIX_ID) { + WriteBuffer[COMMAND_OFFSET] = EXTADD_REG_RD; + WriteBuffer[ADDRESS_1_OFFSET] = 0x00; + + /* + * Send the Extended address register write command + * written, no receive buffer required + */ + Status = XQspiPs_PolledTransfer(QspiInstancePtr, WriteBuffer, ReadBuffer, + BANK_SEL_SIZE); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + } + + if (ReadBuffer[1] != BankSel) { + fsbl_printf(DEBUG_INFO, "BankSel %d != Register Read %d\n\r", BankSel, + ReadBuffer[1]); + return XST_FAILURE; + } + + return XST_SUCCESS; +} +#endif + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/qspi.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/qspi.h new file mode 100644 index 0000000..18dc374 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/qspi.h @@ -0,0 +1,128 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file qspi.h +* +* This file contains the interface for the QSPI FLASH functionality +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a ecm	01/10/10 Initial release
+* 3.00a mb  01/09/12 Added the Delay Values defines for qspi
+* 5.00a sgd	05/17/13 Added Flash Size > 128Mbit support
+* 					 Dual Stack support
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___QSPI_H___ +#define ___QSPI_H___ + +#include "fsbl.h" +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "fsbl.h" + +/************************** Constant Definitions *****************************/ +#define SINGLE_FLASH_CONNECTION 0 +#define DUAL_STACK_CONNECTION 1 +#define DUAL_PARALLEL_CONNECTION 2 +#define FLASH_SIZE_16MB 0x1000000 + +/* + * Bank mask + */ +#define BANKMASK 0xF000000 + +/* + * Identification of Flash + * Micron: + * Byte 0 is Manufacturer ID; + * Byte 1 is first byte of Device ID - 0xBB or 0xBA + * Byte 2 is second byte of Device ID describes flash size: + * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20 + * Spansion: + * Byte 0 is Manufacturer ID; + * Byte 1 is Device ID - Memory Interface type - 0x20 or 0x02 + * Byte 2 is second byte of Device ID describes flash size: + * 128Mbit : 0x18; 256Mbit : 0x19; 512Mbit : 0x20 + */ + +#define MICRON_ID 0x20 +#define SPANSION_ID 0x01 +#define WINBOND_ID 0xEF +#define MACRONIX_ID 0xC2 + +#define FLASH_SIZE_ID_128M 0x18 +#define FLASH_SIZE_ID_256M 0x19 +#define FLASH_SIZE_ID_512M 0x20 +#define FLASH_SIZE_ID_1G 0x21 +/* Macronix size constants are different for 512M and 1G */ +#define MACRONIX_FLASH_SIZE_ID_512M 0x1A +#define MACRONIX_FLASH_SIZE_ID_1G 0x1B + +/* + * Size in bytes + */ +#define FLASH_SIZE_128M 0x1000000 +#define FLASH_SIZE_256M 0x2000000 +#define FLASH_SIZE_512M 0x4000000 +#define FLASH_SIZE_1G 0x8000000 + +/************************** Function Prototypes ******************************/ +u32 InitQspi(void); + +u32 QspiAccess( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthBytes); + +u32 FlashReadID(void); +u32 SendBankSelect(u8 BankSel); +/************************** Variable Definitions *****************************/ + + +#ifdef __cplusplus +} +#endif + + +#endif /* ___QSPI_H___ */ + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/rsa.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/rsa.c new file mode 100644 index 0000000..ef6e506 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/rsa.c @@ -0,0 +1,361 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file rsa.c +* +* Contains code for the RSA authentication +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.00a sgd	02/28/13 Initial release
+* 6.00a kc	07/30/13 Added FSBL_DEBUG_RSA to print more RSA buffers
+* 					 Fix for CR#724165 - Partition Header used by FSBL is
+*                                        not authenticated
+*                    Fix for CR#724166 - FSBL doesn’t use PPK authenticated
+*                                        by Boot ROM for authenticating
+*                                        the Partition images
+*                    Fix for CR#722979 - Provide customer-friendly
+*                                        changelogs in FSBL
+* 9.00a kc  04/16/14 Fix for CR#724166 - SetPpk() will fail on secure
+*					 					 fallback unless FSBL* and FSBL are
+*					 					 identical in length
+*					 Fix for CR#791245 - Use of xilrsa in FSBL
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#ifdef RSA_SUPPORT +#include "fsbl.h" +#include "rsa.h" +#include "xilrsa.h" + +#ifdef XPAR_XWDTPS_0_BASEADDR +#include "xwdtps.h" +#endif + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ +#ifdef XPAR_XWDTPS_0_BASEADDR +extern XWdtPs Watchdog; /* Instance of WatchDog Timer */ +#endif + + +/************************** Variable Definitions *****************************/ + +static u8 *PpkModular; +static u8 *PpkModularEx; +static u32 PpkExp; +static u32 PpkAlreadySet=0; + +extern u32 FsblLength; + +void FsblPrintArray (u8 *Buf, u32 Len, char *Str) +{ +#ifdef FSBL_DEBUG_RSA + int Index; + fsbl_printf(DEBUG_INFO, "%s START\r\n", Str); + for (Index=0;Index +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 4.00a sg 02/28/13 Initial release +* +* +* +* @note +* +******************************************************************************/ +#ifndef ___RSA_H___ +#define ___RSA_H___ + +#ifdef __cplusplus +extern "C" { +#endif +/***************************** Include Files *********************************/ + + +#define RSA_PPK_MODULAR_SIZE 256 +#define RSA_PPK_MODULAR_EXT_SIZE 256 +#define RSA_PPK_EXPO_SIZE 64 +#define RSA_SPK_MODULAR_SIZE 256 +#define RSA_SPK_MODULAR_EXT_SIZE 256 +#define RSA_SPK_EXPO_SIZE 64 +#define RSA_SPK_SIGNATURE_SIZE 256 +#define RSA_PARTITION_SIGNATURE_SIZE 256 +#define RSA_SIGNATURE_SIZE 0x6C0 /* Signature size in bytes */ +#define RSA_HEADER_SIZE 4 /* Signature header size in bytes */ +#define RSA_MAGIC_WORD_SIZE 60 /* Magic word size in bytes */ + +void SetPpk(void ); +u32 AuthenticatePartition(u8 *Buffer, u32 Size); +u32 RecreatePaddingAndCheck(u8 *signature, u8 *hash); + +#ifdef __cplusplus +} +#endif + +#endif /* ___RSA_H___ */ diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/sd.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/sd.c new file mode 100644 index 0000000..9fb8086 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/sd.c @@ -0,0 +1,191 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file sd.c +* +* Contains code for the SD card FLASH functionality. +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a jz	04/28/11 Initial release
+* 7.00a kc  10/18/13 Integrated SD/MMC driver
+* 12.00a ssc 12/11/14 Fix for CR# 839182
+*
+*
    +* +* @note +* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xparameters.h" +#include "fsbl.h" + +#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR) + +#ifndef XPAR_PS7_SD_0_S_AXI_BASEADDR +#define XPAR_PS7_SD_0_S_AXI_BASEADDR XPAR_XSDPS_0_BASEADDR +#endif + +#include "xstatus.h" + +#include "ff.h" +#include "sd.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +extern u32 FlashReadBaseAddress; + + +static FIL fil; /* File object */ +static FATFS fatfs; +static char buffer[32]; +static char *boot_file = buffer; + +/******************************************************************************/ +/******************************************************************************/ +/** +* +* This function initializes the controller for the SD FLASH interface. +* +* @param filename of the file that is to be used +* +* @return +* - XST_SUCCESS if the controller initializes correctly +* - XST_FAILURE if the controller fails to initializes correctly +* +* @note None. +* +****************************************************************************/ +u32 InitSD(const char *filename) +{ + + FRESULT rc; + TCHAR *path = "0:/"; /* Logical drive number is 0 */ + + /* Register volume work area, initialize device */ + rc = f_mount(&fatfs, path, 0); + fsbl_printf(DEBUG_INFO,"SD: rc= %.8x\n\r", rc); + + if (rc != FR_OK) { + return XST_FAILURE; + } + + strcpy_rom(buffer, filename); + boot_file = (char *)buffer; + FlashReadBaseAddress = XPAR_PS7_SD_0_S_AXI_BASEADDR; + + rc = f_open(&fil, boot_file, FA_READ); + if (rc) { + fsbl_printf(DEBUG_GENERAL,"SD: Unable to open file %s: %d\n", boot_file, rc); + return XST_FAILURE; + } + + return XST_SUCCESS; + +} + +/******************************************************************************/ +/** +* +* This function provides the SD FLASH interface for the Simplified header +* functionality. +* +* @param SourceAddress is address in FLASH data space +* @param DestinationAddress is address in OCM data space +* @param LengthBytes is the number of bytes to move +* +* @return +* - XST_SUCCESS if the write completes correctly +* - XST_FAILURE if the write fails to completes correctly +* +* @note None. +* +****************************************************************************/ +u32 SDAccess( u32 SourceAddress, u32 DestinationAddress, u32 LengthBytes) +{ + + FRESULT rc; /* Result code */ + UINT br; + + rc = f_lseek(&fil, SourceAddress); + if (rc) { + fsbl_printf(DEBUG_INFO,"SD: Unable to seek to %lx\n", SourceAddress); + return XST_FAILURE; + } + + rc = f_read(&fil, (void*)DestinationAddress, LengthBytes, &br); + + if (rc) { + fsbl_printf(DEBUG_GENERAL,"*** ERROR: f_read returned %d\r\n", rc); + } + + return XST_SUCCESS; + +} /* End of SDAccess */ + + +/******************************************************************************/ +/** +* +* This function closes the file object +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void ReleaseSD(void) { + + f_close(&fil); + return; + + +} +#endif + + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/sd.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/sd.h new file mode 100644 index 0000000..6283eb6 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/sd.h @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file sd.h +* +* This file contains the interface for the Secure Digital (SD) card +* +* 
    +* MODIFICATION HISTORY:
+*
+* Ver	Who	Date		Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a bh	03/10/11 Initial release
+* 7.00a kc  10/18/13 Integrated SD/MMC driver
+*
+*
    +* +* @note +* +******************************************************************************/ +#ifndef ___SD_H___ +#define ___SD_H___ + + +#ifdef __cplusplus +extern "C" { +#endif + + +/************************** Function Prototypes ******************************/ + +#if defined(XPAR_PS7_SD_0_S_AXI_BASEADDR) || defined(XPAR_XSDPS_0_BASEADDR) +u32 InitSD(const char *); + +u32 SDAccess( u32 SourceAddress, + u32 DestinationAddress, + u32 LengthWords); + +void ReleaseSD(void); +#endif +/************************** Variable Definitions *****************************/ +#ifdef __cplusplus +} +#endif + + +#endif /* ___SD_H___ */ + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/vdma.c b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/vdma.c new file mode 100644 index 0000000..329f185 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/vdma.c @@ -0,0 +1,167 @@ +/* + */ + +#include "xil_printf.h" +//#include "sleep.h" + + +#include "vdma.h" + +XAxiVdma OutVdma; +XAxiVdma InVdma; + +XAxiVdma_DmaSetup VDMAOutCfg; +XAxiVdma_DmaSetup VDMAInCfg; + +u32 vdma_version() { + return XAxiVdma_GetVersion(&OutVdma); +} + +int vdma_out_start() { + int Status; + + // MM2S Startup + Status = XAxiVdma_DmaStart(&OutVdma, XAXIVDMA_READ); + if (Status != XST_SUCCESS) + { + xil_printf("Start read transfer failed %d\n\r", Status); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +int vdma_in_start() { + int Status; + + // MM2S Startup + Status = XAxiVdma_DmaStart(&InVdma, XAXIVDMA_WRITE); + if (Status != XST_SUCCESS) + { + xil_printf("Start read transfer failed %d\n\r", Status); + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +int vdma_stop() { + XAxiVdma_DmaStop(&OutVdma, XAXIVDMA_READ); + return XST_SUCCESS; +} + + +int vdma_out_init(short DeviceID, int base_address, int h_width, int v_width, int bpp) +{ + XAxiVdma_Config *Config; + int Status; + + + Config = XAxiVdma_LookupConfig(DeviceID); + if (NULL == Config) { + xil_printf("XAxiVdma_LookupConfig failure\r\n"); + return XST_FAILURE; + } + + Status = XAxiVdma_CfgInitialize(&OutVdma, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("XAxiVdma_CfgInitialize failure\r\n"); + return XST_FAILURE; + } + + VDMAOutCfg.EnableCircularBuf = 1; + VDMAOutCfg.EnableFrameCounter = 0; + VDMAOutCfg.FixedFrameStoreAddr = 0; + + VDMAOutCfg.EnableSync = 1; + VDMAOutCfg.PointNum = 1; + + VDMAOutCfg.FrameDelay = 0; + + VDMAOutCfg.VertSizeInput = v_width; + VDMAOutCfg.HoriSizeInput = h_width * bpp; + VDMAOutCfg.Stride = VDMAOutCfg.HoriSizeInput; + + Status = XAxiVdma_DmaConfig(&OutVdma, XAXIVDMA_READ, &VDMAOutCfg); + if (Status != XST_SUCCESS) { + xdbg_printf(XDBG_DEBUG_ERROR, + "Read channel config failed %d\r\n", Status); + + return XST_FAILURE; + } + + VDMAOutCfg.FrameStoreStartAddr[0] = base_address; + + Status = XAxiVdma_DmaSetBufferAddr(&OutVdma, XAXIVDMA_READ, VDMAOutCfg.FrameStoreStartAddr); + if (Status != XST_SUCCESS) { + xdbg_printf(XDBG_DEBUG_ERROR,"Read channel set buffer address failed %d\r\n", Status); + return XST_FAILURE; + } + + + Status = vdma_out_start(); + if (Status != XST_SUCCESS) { + xil_printf("error starting VDMA..!"); + return Status; + } + return XST_SUCCESS; + +} + +int vdma_in_init(short DeviceID, int base_address, int h_width, int v_width, int bpp) +{ + XAxiVdma_Config *Config; + int Status; + + Config = XAxiVdma_LookupConfig(DeviceID); + if (NULL == Config) { + xil_printf("XAxiVdma_LookupConfig failure\r\n"); + return XST_FAILURE; + } + + Status = XAxiVdma_CfgInitialize(&InVdma, Config, Config->BaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("XAxiVdma_CfgInitialize failure\r\n"); + return XST_FAILURE; + } + + VDMAInCfg.EnableCircularBuf = 1; + VDMAInCfg.EnableFrameCounter = 0; + VDMAInCfg.FixedFrameStoreAddr = 0; + + VDMAInCfg.EnableSync = 1; + VDMAInCfg.PointNum = 1; + + VDMAInCfg.FrameDelay = 0; + + VDMAInCfg.VertSizeInput = v_width; + VDMAInCfg.HoriSizeInput = h_width * bpp; + VDMAInCfg.Stride = VDMAInCfg.HoriSizeInput; + + Status = XAxiVdma_DmaConfig(&InVdma, XAXIVDMA_WRITE, &VDMAInCfg); + if (Status != XST_SUCCESS) { + xdbg_printf(XDBG_DEBUG_ERROR, + "Read channel config failed %d\r\n", Status); + + return XST_FAILURE; + } + + VDMAInCfg.FrameStoreStartAddr[0] = base_address; + + Status = XAxiVdma_DmaSetBufferAddr(&InVdma, XAXIVDMA_WRITE, VDMAInCfg.FrameStoreStartAddr); + if (Status != XST_SUCCESS) { + xdbg_printf(XDBG_DEBUG_ERROR,"Write channel set buffer address failed %d\r\n", Status); + return XST_FAILURE; + } + + + Status = vdma_in_start(); + if (Status != XST_SUCCESS) { + xil_printf("error starting VDMA..!"); + return Status; + } + + return XST_SUCCESS; + +} + diff --git a/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/vdma.h b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/vdma.h new file mode 100644 index 0000000..79c1662 --- /dev/null +++ b/zynqberrydemo3/sw_lib/sw_apps/zynq_fsbl/src/vdma.h @@ -0,0 +1,14 @@ + +#ifndef VDMA_H_ +#define VDMA_H_ + +#include "xaxivdma.h" + + +extern XAxiVdma Vdma; /**< Instance of the VDMA Device */ +int vdma_out_init(short DeviceID, int base_address, int h_width, int v_width, int bpp); +int vdma_in_init(short DeviceID, int base_address, int h_width, int v_width, int bpp); + +u32 vdma_version(); + +#endif /* VDMA_H_ */ -- GitLab

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